Intel iSBC 546, iSBC 547, iSBC 548 Hardware Reference Manual

iSBC®

546/547/548

HIGH PERFORMANCE

TERMINAL CONTROLLERS

HARDWARE REFERENCE MANUAL

Order Number: 122704-001

I

Copyright 1986, Intel Corporation, All Rights Reserved

Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051 r

11

Additional copies of this manual or other Intclliterature may be obtained from:

Literature Department

Intel Corporation

3065 Bowers Avenue

Santa Clara, CA 95051

The int(lrmation in this document is subject to change without notice.

Intel Corporation makes no warranty of any kind with regard to this material. including, but not limited to, the implied warranties of merchantability and fitne~s for a particular purpose. Intel Corporation assumes no respon~ sibility for any errors that may appear in this document. Intel Corporation makes no commitment to update nor to keep current the information contained in this dDcument.

Intel Corporation assumes no responsibility for the usc of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses arc implied.

Intel software products arc copyrighted by and shall remain the property of Intel Corporation. Use, duplication or disclosure is subject to restrictions stated in Inters software license. or as defined in ASPR 7~104.9(a)(9).

No part of this document may be copied or reproduced in any form or by any means without prior written consent of Intel Corporation.

Intel Corporation makes no warranty for the usc of its products and assumes no responsibility for any errors which may appear in this document nor docs it make a commitment to update the information contained herein.

Intel retains the right to make changes to these specifications at any time, without notice.

Contact your local sales office to ohtain the latest specifications bef()re placing your order.

The following are trademarks of Intel Corporation and its affiliates and may be used only to identify Intel products:

Above

BITBLJS

COMMputer

CREDIT

Data Pipeline

GENIUS

-' i

ICICE

ICE rCEL iCS iDBP iDIS iLBX im iMDDX iMMX lnsite

Intel inte l intclBOS lntelcvision intc1igcnt Identifier intcligent Programming lntcllec

Intcllink iOSP iPDS iPSC iRMX iSBC iSBX iSDM iSXM

Library Manager

MCS

Megachassis

MICROMAINFRAME

MLJLTIBUS

MULTICHANNEL

MULTIMODULE

ONCE

OpenNET

Plug~A~Bubblc

PROMPT

Promware

QucX

QUEST

Ripplcmodc

RMX/SO

RUPI

Seamless

SLD

UPI

VLSiCEL

MDS is an ordering code only and is not used as a product name or trademark. MDS" is a regi,tered trademark of Mohawk Data Sciences Corporation.

*MULTlBlJS is a patented Intel bus.

Copyright 1985, Intel Corporation, All Righb Reserved

REV.

-001 Original Issue.

REVISION HISTORY DATE

2/86 iii/tv

PREFACE

This manual provides information about the iSBC 54B and iSBC 547

Eight Channel Terminal Controllers and the iSBC 546 Terminal and

Printer Controller. The iSBC 548 and iSBC 547 boards are functionally identical, but the iSBC 547 is a larger form factor

(10" x 12") board with backpanel connectors on-board. The iSBC 546 is a four channel board with a clock calendar and a centronix printer interface.

General information about all three boards is provided in Chapter

1. Chapter 2 provides a block diagrams and functional descriptions of the boards. Chapter 3 provides the information required to install the board. Programming information is provided in Chapter

4 as well as in Appendix A and B. Connector pin-out information for all boards is shown in Chapter 5. If you need to refer to the schematic diagrams see Chapter 6.

For reference purposes Appendix A provides jumper information for the boards. Appendix B covers the board firmware.

In addition to this manual you will need the following reference material ( all are available from the Intel Literature Department, see page ii for address). o Intel MULTIBUS Handbook, Order Number 210883 o Microsystem Components Handbook, Order Number 230843 o Serial Communications Controller Technical Manual,

Order Number 230834. v

CONTENTS ]

PAGE

CHAPTER 1

GENERAL INFORMATION

1. 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 1-1

1.2 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . l-l

1.3 Board Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.3.1 iSBC 546 Board Description . . . . . . . . . . . . . . . . . . 1-2

1.3.2

1.3.3 iSBC iSBC

547 Board Description . . . . . . . . . . . . . . . . . . 1-3

548 Board Description . . . . . . . . . . . . . . . . . . 1-3

1.4 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

CHAPTER 2

BOARD OPERATION

2 • 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 2-1

2.2 iSBC 547 and iSBC 548 Functional Descriptions .. 2-l

2.3 iSBC 546 Functional Description . . . . . . . . . . . . . . . . . 2-4

CHAPTER 3

INSTALLATION

3 • 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 Unpacking And Inspection . . . . . . . . . . . . . . . . . . . . . . . . . 3-l

3.3 Compatible Equipment . . . . . . . • . . . . . . . . . . . . . . . . . . . . . 3-l

3.4 Installation Considerations . . . . . . . . . . . . . . . . . . . . . . 3-2

3.4.1 Connector Configurations . . . . . . . . . . . . . . . . . . . . . . 3-2

3.4.2 Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.4.3 Cabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.5 Installation Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

CHAPTER 4

PROGRAMMING CONSIDERATIONS

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4 • 2 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.3 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.4 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.4.1 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.4.2

4.4.3

80186 Processor Programming Considerations .... 4-3

8255 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.4.4 DSR Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.5 Baud Rate Programming (All Boards) . . . . . . . . . . . . . . . 4-7 vii

CONTENTS (continued)

PAGE

CHAPTER 5

INTERFACING INFORMATION

5.1 Introduction . . . . to • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

5-1

5.2

5.3

MULTI BUS Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.4 Printer InterfaCE~ (iSBC 546 Only) . . . . . . . . . . . . . . . 5-11

CHAPTER 6

SERVICE ASSISTANCE INFORMATION

6 -1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6-2 Service and Repair Assistance . . . . . . . . . . . . . . . . . . . . 6-1

6-3 Service Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

APPENDIX A

JUMPER INFORMATION

A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.2 Flag Byte Address Jumpers . . . . . . . . . . . . . . . . . . . . . . . . A-4

A.3 MULTIBUS Interrupt Jumpers . . . . . . . . . . . . . . . . . . . . . A-5

A.4 Memory Mapping Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5

APPENDIX B

FIRMWARE

B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

B.2 Firmware Overvie'iliT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

B.2.1 Firmware Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4

B.2.2 Recommendations For High Performance . . . . . . . . . . B-5

B.3 Functional Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . B-6

B.3.1 structures of Dual Ported RAM . . . . . . . . . . . . . . . . . B-6

B.3 . 1. 1

B.3.1.2

Test EnginE~ering Boot Area . . . . . . . . . . . . . . . . . B-7 static Structures . . . . . . . . . . . . . . . . . . . . . . . . . . B-8

B.3.1.3

B . 3 . 1 . 4

B.3.1.5

B.3.1.6

B.3.2

Dynamic Structures . . . . . . . . . . . . . . . . . . . . . . . . . B-10

Queue. . . . . " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 0

Receive Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11

Transmit Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11

Inter-Processor Messages . . . . . . . . . . . . . . . . . . . . . . B-11

B.3.2.l

B.3.2.1.1

B.3.2.1.2

B.3.2.1.3

B.2.2.1.4

B.3.2.1.5

B.3.2.1.6

B.3.2.1.7

B.3.2.1.8

Host CPU to Controller Messages . . . . . . . . . . . . B-ll

Initialize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12

Enable .. ~I

• • • • • • • • • • • • • • • • • • • • • • " • • • • • • • • •

B-13

Disable. ~ . . . . . . . . . . . . . . . . . . . . . . . .

Conf igurE~ . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . B-15

Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . B-20

Abort Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 2

Suspend Transmit . . . . . . . . . . . . . . . " . . . . . . . . . B-23

Resume Transmit . . . . . . . . . . . . . . . . " . . . . . . . . . B-24 viii

TABLEfJ (continued)

3-2 Pin to Pin Wiring List •.....•.......•..•.•...•.... 3-7

5-1 MULTI BUS Connector Pl Pin Assignments . . . . . . • . . . . 5-l

5-2 MULTI BUS Connector Pl Signal Descriptions . . . . . . . 5-3

5-3 Connector P2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . 5-5

5-4 Serial Connectors Pin Assignments, iSBC 546 . . . . . . 5-6

Board

5-5 Serial Connectors Pin A!;signments, iSBC 547 . . . . . . 5-7

Board

5-6 Serial Connectors Pin Assignments, iSBC 548 . . . . . . 5-9

Board

5-7 Printer Interface Connec:::tor J5 Pin Assignments .... 5-ll

5-8 Connector J5 Signal Desc:::riptions . . . . . . . . . . . . . . . . . . 5-12

A-l Jumper Combinations iSBC 546 Boards .....••....... A-l

A-2 Jumper Combinations iSBC 547/548 Boards . . . . . . . . . . A-3

A-3 Flag Byte Address options And Jumpers . . . . . . . . . . . . . A-4

A-4 Memory Map jumpers and Addresses . . . . . . . . . . . . . . . . . . A-6

B-1 iSBC 546/547/548 Firmware Features . . . . . . . . . . . . . . . B-2

B-2 Confidence Test Result Codes . . • . . . . . . . . . . • . . . . . . . . B-59

1-1

1-2

1-3

1-4

2-1

2-2

6-4

A-l

A-2

A-3

B-1

B-2

B-3

B-4

B-5

B-6

3-1

3-2

3-3

3-4

4-1

6-1

6-2

6-3

FIGUlRES iSBC 546, iSBC 547 and iSBC 548 Boards . . . . . . . . 1-5

Block Diagram iSBC 548 High Performance Terminal Controller ... 1-6 iSBC 547 High Performance Terminal Controller ... 1-6 iSBC 548 High Performance Terminal Controller ... 1-7 iSBC 547 and iSBC 548 Functional Block Diagram.2-2 iSBC 546 Functional BLock Diagram . . . . . . . . . . . . . . . 2-6 iSBC 546 Board Connector Locations . . . . . . . . . . . . . 3-4 iSBC 547 Board Connector Locations . . . . . . . . . . . . . . 3-5 iSBC 548 Board Connector Locations . . . . . . . . . . . . . . 3-6 iSBC 548 RS232 Cable Construction . . . . . . . . . . . . . . . 3-8 iSBC 546/547/548 Boards Memory Map . . . . . . . . . . . . . . 4-2

Territorial Service Telephone Numbers . . . . . . . . . . . . 6-2 iSBC 548 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . 6-4 iSBC 547 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . 6-l5 iSBC 546 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . 6-27 iSBC 546 Board Jumper Location . . . . . . . . . . . . . . . . . . A-7 iSBC 547 Board Jumper Location . . . . . . . . . . . . . . . . . . A-8 iSBC 548 Board Jumper Location . . . . . . . . . . . . . . . . . . A-9

Layout of Shared (Dual Port) Memory . . . . . . . . . . . . . . B-6

Test Engineering Boot Area Layout . . . . . . . . . . . . . . . . B-7 static Structure Area Layout . . . . . . . . . . . . . . . . . . . . . B-9

Dynamic Structure Layout . . . . . . . . . . . . . . . . . . . . . . . . . B-10

Layout of Queue Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10

Initialize Message Format . . . . . . . . . . . . . . . . . . . . . . . . B-12 x

FIGURES (continued)

B-19

B-20

B-21

B-22

B-23

B-24

B-25

B-26

B-27

B-28

B-29

B-30

B-31

B-32

B-33

B-34

B-35

B-36

B-37

B-38

B-39

B-7

B-8

B-9

B-10

B-11

B-12

B-13

B-14

B-15

B-16

B-17

B-18

PAGE

Enable Message F0rIl1at . . . . . . . . . . . . . . . . . . . " . . . . . . . . B-13

Disable Message Format . . . . . . . . . . . . . . . . . . " . . . . . . . . B-14

Configure Message Pormat . . . . . . . . . . . . . . . . " . . . . . . . . B-15

Transmit Buffer Message Format . . . . . . . . . . " . . . . . . . . B-21

Abort Transmit Message Format . . . . . . . . . . . " . . . . . . . . B-22

Suspend Transmit Message Format . . . . . . . . . " . . . . . . . . B-23

Resume Transmit Message Format . . . . . . . . . . " . . . . . . . . B-24

Assert DTR Message Format •.............. " . . . . . . . . B-25

Set CTS and CD GatE~s Message Format ..... " . . . . . . . . B-2 6

Clear CTS and CD Gates Message Format ... " . . . . . . . . B-27

Set DSR Report Message Format . . . . . . . . . . . " . . . . . . . . B-28

Clear DSR Report Message Format •........ " . . . . . . . . B-29

Set RI Report Message Format . . . . . . . . . . . . ' ......... B-3 0

Clear RI Report Message Format . . . . . . . . . . ' ......... B-31

Set Break Message Format . . . . . . . . . . . . . . . . ' ......... B-3 3

Clear Break Message Format . . . . . . . . . . . . . . . . . . . . . . . B-34

Download Message Format . . . . . . . . . . . . . . . . . ' ......... B-3 7

Execute Command Message Format . . . . . . . . . . . . . . . . . . . B-38

Clear Receive Buffer Command Message Format ...... B-40

Transmit Complete Message Format . . . . . . . . . . . . . . . . . B-41

Input Available message Format . . . . . . . . . . . . . . . . . . . B-43

Download Complete 'Message Format . . . . . . . . . . . . . . . . . B-44

Carrier Detect Message Format . . . . . . . . . . . . . . . . . . . . B-45

Carrier Loss Message Format .....••.•............. B-46

Initialization Responses Message Format . . . . . . . . . . B-47

Autobaud Complete Message Format . . . . . . . . . . . . . . . . . B-48

Special Character Received Message Format . . . . . . . . B-49

DSR Detected Message Format . . . . . . . . . . . . . . . . . . . . . . B-50

DSR Lost Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . B-51

RI Detected Message Format . . . . . . . . . . . . . . . . . . . . . . . B-52

RI Lost Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . B-53

EPROM Checksum .... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-60 xi

CHAPTER 1

GENERAL INFORMATION

1.1 INTRODUCTION

The iSBC 548, iSBC 547 and iSBC 546 are three single board terminal controllers to be used in the MULTIBUS I environment. The iSBC 548 and iSBC 547 are eight channel controllers. The iSBC 546 has four channels plus a line printer i.nterface and clock/ca.lendar.

The purpose of this chapter is to introduce you to all three boards. The remaining chapters will provide more detailed information on all the boards. This chapter gives a. list of the key features, a brief description of each board and a list of specifications.

1.2 BOARD FEATURES

This section provides a brief list of key features of the iSBC 548 and iSBC 547 boards. o Eight Mhz 80186 Microprocessors. o Supports asynchronous RS232C interface in DTE configuration,on eight channels. o 32K Byte dual-ported B~, 96K Byte local RAM and supports up to 64K Byte EPROM sites populated with :i:irmware (All

Boards) o Each serial channel supports transfer rates up to 19.2K

Baud.

0

0

0

0

Up to 96K Baud (per board) throughput rate (Special

Character or Tandem Mode not used)

Jumper selectable memory mapping

Jumper selectable I/O mapping

Jumper selectable MUL'l'IBUS interrupts

1-1

GENERAL :rNl~ORMATION o The iSBC 547 is a 10"x 12" form factor board with on-board backpanel connectors.

The iSBC 546 board differs from the iSBC 548 and iSBC 548 boards as follows: o Four channels of RS232C instead of eight channels o Line printer interface o Clock calendar with battery back-up

1.3 BOARD DESCRIPTIONS sections 1.3.1, 1.3.2 and 1.3.3 provide general descriptions of the iSBC 548, iSBC 547 and iSBC 546 boards respectively. Figure 1-1 is a much simplified diagram for all three boards. Figures 1-2, 1-3 and 1-4 show the iSBC 548, iSBC 547 and iSBC 546 boards respectively.

1.3.1 iSBC 548 BOARD DESCRIPTION

ThE: iSBC 548 board is a MULTIBUS based terminal con1:roller. The boa.rd communicates with a MULTIBUS host as a slave boa.rd.

The board uses an Intel 80186 microprocessor, operating at 8 Mhz as its cpu.

The 80186 controls eight serial channels sending data to or receiving data from the MUL'TIBUS host. The on-board 80186 gains the attention of the MULTI BUS host by generating an interrupt over the MULTIBUS interface to the host. A flag byte mechanism allows the MULTIBUS host to interrupt the board, to reset thE! board, or to reset an interrupt to the MULTIBUS host generated by the board.

The: iSBC 548 board has four on-·board 82530 Serial Communications

Controllers (SCC). Each 82530 SCC contains two on-chip baud rate generators, allowing each channE~l to be independently programmed for separate baud rates. The maximum baud rate per channel is 19.2K

Baud. Two 40-pin connectors can be attached to IBM PCAT compatible

9-pin connectors via ribbon cable.

ThE! iSBC 548 board has four 64K x 4 DRAM (Dynamic RAM) devices, a total of 128 KBytes per board. The upper 32K Bytes can be addressed by other MULTIBUS boards.

J.-2

GENERAL INFORMATION

The board also includes two 28-pin sockets. These sockets are populated with firmware EPROMs.

1.3.2 iSBC 547 BOARD DESCRIP'l~ION

The iSBC 547 board is a terminal controller expansion to the Intel system 320. The board communicates with a MULTIBUS host as a slave board.

The board uses an Intel 80186 microprocessor, operating at 8 Mhz as its CPU. The 80186 controls eight serial channels sending data to or receiving data from the MULTIBUS host. The on-board 80186 gains t~e attention of the MULTI BUS host by generating an interrupt over the MULTIBUS interface to the host. A flag byte mechanism allows the MULTIBUS host to interrupt the board, to reset the board, or to reset an interrupt to the MULTIBUS host generated by the board.

The eight serial interfaces on the iSBC 547 board are through eight

9-pin connectors. The 9-pin connections are fully compatible with the IBM PCAT connections.

The iSBC 547 board has four on-~)oard 82530 Serial communications

Controllers (SCC). Each 82530 sec contains two on-chip baud rate generators,allowing each channel to be independently programmed for separate baud rates. The maximum baud rate per channel is 19.2K

Baud.

The iSBC 547 board has four 64K x 4 DRAM (Dynamic RAM) devices, a total of 128 KBytes per board. ~~he upper 32K Bytes can be addressed by other MULTIBUS boards.


1.3.3 iSBC 546 BOARD DESCRIPTION

The iSBC 546 board is a terminal and line printer controller. The board communicates with a MULTIBUS host as a slave board.

1-3


The board uses an Intel 80186 microprocessor, operating at 8 Mhz as its cpu. The 80186 controls four serial channels, sending data to or receiving data from the MULTIBUS host, and a line printer interface. The on-board 80186 ga.ins the attention of t.he MULTIBUS host by generating an interrupt over the MULTI BUS interface to the host. A flag byte mechanism allows the MULTIBUS host to interrupt the board, to reset the board, or to reset an interrupt to the

MULTI BUS host generated by the l:Jioard.

The four serial interfaces on the iSBC 546 board are through four

9-pin connectors. The 9-pin connections are fully compatible with the IBM PCAT connections.

The line printer interface is compatible with the IBM line printer interface.

The iSBC 546 board has two on-board 82530 Serial Communications

Controllers (SCC). Each 82530 sec contains two on-chip baud rate generators,allowing each channel to be independently programmed for separate baud rates. The maximum baud rate per channel is 19.2K

Baud.

The iSBC 546 board has four 64K x 4 DRAM (Dynamic RAJ~) devices, a total of 128 KBytes per board. The upper 32K Bytes can be addressed by other MULTIBUS boards.


A clock/calendar circuit, unique to the iSBC 546, is backed up by a non-rechargeable battery which keeps the clock/calendar operating for six months with all other power off.

1-4

GENERAL INFORMATION

RS232

INTERFACE

CHLS 7 AND 8

(iSBC' 5471

548 ONLY)

, - - - - - -

RS232

INTERFACE

CHlS 5 AND 6

(iSBe' 5471

548 ONLY)

'" -

- - -

REFRESH

LOGIC

(ALL BOARDS)

5

MULTIBUS' r 3

REFRESH

CONTROL

SIGNALS

RAM

(ALL BOARDS)

I

RAM CONTROL

SIGNALS

RAM

CONTROL

(ALL BOARDS)

PAINTER

INTERFACE

(iSBe 546

ONLY)

L __ _

80186

MICROPROCESSOR

(ALL BOARDS)

I

CLOCK!

CALENDAR

INTERFACE

(iSBC' 546

ONLY)

I

ROM

(ALL BOARDS)

2335

Figure 1-1. iSBC 546, iSBC

Block Diagram

547 and iSBC 548 Boards,

1-5

PIN 1

TOP

PIN2

BOTTOM

GENERAL INFORMATION

PIN 39

TOP

PIN 40

BOTTOM SERIAL

CONNECTOR J1

PIN 1

TOP

PIN2

BOTTOM

PIN 39

TOP

PIN 40

BOTTOM SERIAL

CONNECTOR J2

MULTIBUS'

CONNECTOR P1

Figure 1-2. iSBC

MULTIBUS'

CONNECTOR P2

548 High Performance Terminal Controller

Figure 1-3. iSBC 547 High Performance Terminal Controller

1-6


PRINTER

INTERFACE

CONNECTOR

J5

SERIAL

CONNECTOR

J4

/

SERIAL

CONNECTOR

J3

/

SERIAL

CONNECTOR

J2

/

MULTI BUS .

CONNECTOR P1

MULTIBUS'

GONNECTOR P2

Figure 1-4. iSBC 548 High Performance Terminal Controller

2341

1-7


1.4 SPECIFICATIONS

Table 1-1 summarizes the iSBC 546, iSBC 547 and iSBC 548 boards specifications.

Table 1-1. iSBC 546, iSBC 547, and iSBC 548 Specifications summary

Board Performance (Transfer Rate) iSBC 547 and iSBC 548 Boards iSBC 546

Eight RS232C channels DTE configured. Maximum transfer rate per channel

19.2K Baud. Typical performance with :firmware is 96K Baud.

Four RS232C channels DTE configured. Maximum transfer rate per channel

19.2K Baud.

Interfaces iSBC 546 Board MULTI BUS connectors PI and

P2. All MUL'I'IBUS signals supported. The board at power-up requires an INIT pulse of at least 50 microseconds duration.

Four RS232C channels, four

9-pin connectors.

Line printer interface, one 25-pin connector.

Interface is compatible with IBM PC Line Printer interface with the exception that. AU'rOFEED* and SELECT-INPUT signals are not supported.

1-8

GENERAL INFORMATION

Table 1-1. iSBC 546, iSBC S47, and iSBC 548 specifications

Sumlllary (continued) iSBC 547 Board iSBC 548 Board

Electrical Requirements

+5.00V + 0.25V

+l2.00V + 0.60V

-12.00V + 0.60V

Environmental Characteristics

Temperature

Humidity

MULTI BUS connectors PI and

P2. All MULTIBUS signals supported. On power-up the board requires an INIT pulse of at least 50 microseconds duration.

Eight RS232C channels eight 9-pin connectors.

MULTI BUS connectors Pl and

P2. All MULTIBUS signals supported. At power-up the board requires an INIT pulse of at least 50 microseconds duration.

Eight RS232C channels, two

40-pin connectors.

(Max. )

(Typ. )

(Max. )

(Typ. ) iSBC 546 iSBC 547 iSBC 548

3.260A

1. 700A

0.075A

0.390A

3.490A

1. 870A

0.l50A

0.082A

3.490A

1. 870A

0.150A

0.082A

(Max. )

(Typ. )

0.069A

0.041

0.l38A

0.082A

0.138A

0.082A o to 55 degrees C, minimum,

200 LFM of airflow

5% to 90%, non-condensing

(25 to 55 degrees C)

1-9


Table 1-1. iSBC 546, iSBC 547, and iSBC 548 specifications

Summary (continued)

Physical Dimensions iSBC 546 iSBC 547 iSBC 548 width

Length

1:2.00 in

(30.48 cm)

10.00 in

(25.40 cm)

12.00 in 12.00 in

(30.48 cm) (30.48 cm)

10,,00 in 7.00 in

(25.40 cm) (17.78 cm)

Height (Including Components) 0.50 in

( 1. 27 cm)

0.50 in 0.50 in

( 1. 27 cm) ( 1. 27 cm)

1-10

CHAPTER 2

BOARD OPERATION

2.1 INTRODUCTION

This chapter describes the operation of the three controller boards, the iSBC 546, the iSBC 547, and the iSBC 548. The iSBC 547 and iSBC 548 boards are functionally identical and their operation will be described jointly. The iSBC 546 board will be considered separately.

2.2 iSBC 547 AND iSBC 548 FUNCTIONAL DESCRIPTIONS

Figure 2-1 is a block diagram for the iSBC 547 and iSBC 548 boards. The boards are functionally identical and differ only in dimensions and in the type and number of serial interface connectors (eight 9-pin connectors for the iSBC 547 and two 40-pin connectors for the iSBC 548).

The iSBC 547 and iSBC 548 boards can not address the MULTIBUS interface, both are slave boards only. The interface to the

~ruLTIBUS is through edge connectors PI and P2.

30th boards use an Intel 80186 microprocessor, operating at 8 Mhz as their main processors. The 80186 has a 16 bit data bus and 16 bit internal architecture. The 80186 provides all bus controls without the need of a separate bus controller device.

'rhe 80186 on the iSBC 547/548 controls eight serial channels sending data ,through them, from the MULTIBUS host or receiving data, through them, to the MUL'l~IBUS host. Data transfer to and from the MULTIBUS is by use of a 32K Byte communication table

(shared dual port memory) in the on-board dual-port RAM. The

HULTIBUS host informs the on-bc)ard 80186 which serial channels are enabled. The 80186 then polls those channels continuously, looking for data from the MULTIBUS host, or the need to supply data to the

HULTIBUS host.

The structure of the communication table is described in Appendix

B, section B.3.1 of this manual. The main blocks in the communication table in the on-board RAM are: a command queue

(dynamic structures area), a status queue (static structures

2-1

BOARD OPERATION

CHANNEL 8

CHANNEL 4

CHANNEL 2

NOTE:

ISBC' 547 AND ISBC" 548 ARE

FUNCTIONALLY IDENTICAL THE

EIGHT SERIAL CHANNELS OF THF

Isac" 547 ARE- BROUGHT our

THROUGH 8 PIN CONNECTORS THE

EIGHT SERIAL CHANNELS OF THE

ISSC' 548 ARE BROUGHT OUT

THROUGH TWO 40·PIN

CONNECTORS

80186

PROCESSOR

C ______

M_V_L,T,',B_V_S_' __ _ _

----<J

REFRESH

LOGIC

REFREQ

·:-----1

, - - - ' " ' - - - - ,

,-~~---o~-o15

A1·A8

RAS',eM,'

- - - -

RAM CONTROL

AND

ARBITRATION

LOGIC

AAM

128 K BYTES

- - -

AD'

IOB~·IOB7

I/O

BUFFER

ENLCL, ENLCH, LDCOEN

~-~-l

-

,.---------"'-=~·I

[I"'"''

L-----,JJ

I

-=' .

2338 j

Figure 2-1. iSBC 547 and iSBC 548 Functicmal Block Diagram

2-2

BOARD OPERATION a~ea), a transmission area (transmit buffers), and a set of rE:!cei ve buffers. The MULTIBUS host gains the attention of the onboard 80186 to the command queUE! by a flag byte interrupt. The onboard 80186 gains the attention of the MULTIBUS host to the status queue by generating an interrupt over the MULTIBUS interface to the host. The interrupt line is jumper selectable as shown in

Table A-2.

T::1e flag byte mechanism allows the MULTIBUS host to interrupt the controller board, to reset the board, or to reset an interrupt to t::le MULTIBUS host generated by the board. The flag byte interrupt, sent by the MULTIBUS host to the controller board is an eige triggered input to the interrupt line of the on-board 80186.

The flag byte is mapped to I/O space at a jumper selectable a::idress (see Appendix A , Table A-2 of this manual). Interrupting tile MULTIBUS host is done by writing data to an I/O port addressed through PCS5* (asterisk indicates signal is active low).

Ea.ch of the controller boards include two 28-pin sockets which are populated by two Intel 2764 EPROMs which contain the controller firmware. Appendix B of this manual describes the firmware in dl:~tail.

Although the controller boards are supplied with 2764 EPROMs the boards can support 27128 and 27256 EPROMs as well. The EPROM runs with zero wait states. The optional EPROMs must have access times o:E 250 ns or less. No jumper changes need be made when the different size EPROMs are used.

Each of the boards has four 64K x 4 DRAMs (Dynamic RAMs), a total of 128K Bytes of on-board RAM. ~rhe upper 32K Bytes of the on-board

RAM can be addressed by other MULTI BUS boards as well as the onb::>ard processor. The dual-port HAM can be seen from the MULTIBUS at several different starting addresses. The starting addresses are jumper selectable (see Table A-3 in Appendix A of this manual). The RAM operates with :z:ero wait states.

'Il:1e RAM is controlled with a PAL (Programmable Array Logic) device. The PAL generates all signals needed to control the RAM, arbitrate between the MULTIBUS host, the refresh logic and the

80186 and enables the address lbuffers as required. The on-board the on-board 80186. The memory arbiter allows refresh of the RAM even when the memory is locked.

2-3

BOARD OPERATION

RAM refresh uses a 1 Mhz output from Timer 1 of the on-board

80186. A divide by 15 counter causes a refresh request to be sent to the PAL arbiter every 15 microseconds. An eight bit counter addresses the RAM.

The serial channels of the controller boards are implemented in flour 82530 Serial Communication Controller (SCC) chips. The baud rate clock for the serial channels is generated by the 82530 secs. Each channel has its own two on-chip baud rate generators, allowing each channel to be programmed separately. Chapter 4 of this manual describes baud rate programming.

The 82530 SCCs are selected by the PCSl* (Peripheral Chip Select) through PCS4* outputs of the on-board 80186. The DSR signals from the RS232 serial connectors are all tied to one input port decoded by the PCSo* line of the 80186.

2.3 iSBC 546 FUNCTIONAL DESCRIPTION

The iSBC 546 board, Figure 2-2, is similar to both the iSBC 547 and 548 boards. It differs primarily in that it has a line printer interface connector and associated circuitry, a clock/calendar circuit and supports only four serial channels.

The iSBC 546 processes data in the same manner as the other two boards; it has the same on-board RAM and controls it in same way as the other boards. The serial channels are controlled in the same manner as on the iSBC 547/548 boards except only two 82530

SCC devices are used.

The line printer interface is implemented through port A of an

8255A Programmable Peripheral Interfa,ce (PPI operated in strobed output mode). A PAL device controls timing and the line printer.

Approximately two microseconds after data is written to port A the PAL generates a LP STB* (Line Printer Strobe) signal to the printer indicating data to the printer is valid. LP STB* stays active for one microsecond. When LP ACK (Line Printer

Acknowledge) is returned by the printer it clears the port and allows more data to be sent.

The 8255A PPI is selected by the PCS3* signal generated by the onboard 80186. The PPI replaces one of the SCC devices in the I/O map for the controller boards.

2-4

BOARD OPERATION

The interface does not have RS2:32 lines 5 through 8, freeing four bits of the DSR port. These four lines are used for line printer status lines LP BUSY (Line Printer Busy), NO PAPER, FAULT and LP

SELECT (Line Printer Select).

The line printer interface is compatible with the IBM line printer interface and with proper cabling interfaces to a Centronix line printer. rrhe clock calendar circuit uses a MM58167 clock chip and a 32.768

KHz crystal. The interface to the MM58167 uses the same PAL device as does the line printer interface. Port B of the 8255A device is used in both input or output strobed mode. PC4* and PC5* generated by the 8255A inform the PAL of either input or output mode.

Coding of the two bits is as follows:

Function PC4*

Output to Clock Mode

Input From Clock Mode

Reset LP and Clock

1

0

1

Interface

Reset Clock Interface 0

Only

PC5*

0

1

1

0

1;'1henever a new clock set is issued or a clock read is started PC4 *

,.3.nd PC5* must be reset to 0,0 and the port set to the appropriate

::node, input or output. Then PC~~* and PC5* are programmed to the correct logic level and the hardware supplies the address to the clock by order, starting from milliseconds and all the way up to

'the clock internal RAM area. Only the first 16 addresses in the clock chip are addressable.

'rhe PAL generates the control ~;ignals for the 8255A PPI. The data sent to the clock or received from the clock consists of eleven

::.')ytes.

'rhe clock/calendar is backed-up by a non-rechargeable battery

'ilhich insures at least six months operation with no off-board power. The battery back-up is ~iumper selectable.

2-5

BOARD OPERATION

PRINTER

CONNECTOR

LOAlO·

LDAT7,

OSR5·0SRs

TRANSCEIVER

PROGRAMMABLE

PERIPHERAL

INTERFACE

10BO-

IOB7

ClKBUSO-

CLKBUS7

ADO-AD?

CHANNEL 4

CLOCK AND

CALENDER

CKT

80186

PROCESSOR

(~

SELMBL, HOS T

REFRESH

LOGIC

~

~

MUlTiBUS" t)

AORO-.IORF

DATO-CIATF

MULTIBUS"

BUFFER

Ii

U

00-015

Al-AB

]

~

AAMCONTROL

AND

ARBITRATION

LOGIC

RAS·. CAS' r--------

RAM

128K BYTES

WRl', WRH'

~

IOBP-9

110

BUFFER

'r----------

ADO-.I\.015

' - - - - - -

LOC DEW

1

ADO-AD15

:::)

RAM

BUFFERS

00-015 i

~

2336

Figure 2-2. iSBC 546 Board Functional Block Diagram

2-6

CHAPTER 3

INSTALLATION

3.1 INTRODUCTION

This chapter explains how to receive, inspect and then install the. iSBC 548, iSBC 547 and iSBC 546 boards. However, before installation you should read Chapter 4 Programming Considerations and Appendix A Jumper Information. Once you have set up the jumpers according to your system requirements proceed with the installation procedures in this chapter.

3.2 UNPACKING AND INSPECTION

Inspect the shipping carton immediately upon receipt for evidence of mishandling during transit. If the shipping carton is damaged or water stained, request the carrier's agent be present when the carton is opened. If the carrier's agent is not present when the carton is opened and the contents are damaged, keep the carton and packing material for the agents inspection.

United states customers can obtain service and repair assistance by contacting the Intel product service hotline in Phoenix, Arizona

(see Chapter 6 for more information). customers outside the United states should contact their sales source (Intel sales office or authorized distributor) for service information and repair assistance.

3.3 COMPATIBLE EQUIPMENT

The iSBC 548 can be installed in any MULTIBUS Compatible chassis.

The iSBC 547 board serves as a terminal controller expansion to the Intel System 320.

The iSBC 546 is part of the basic Intel System 320.

3-1

INSTALLATION

3.4 INSTALLATION CONSIDERATIONS

The following sections describe some of the installation consideration for the three boards.

THe iSBC 548, 547, and 546 boards can be configured to reside in 32 different address locations (see Table A-4) in the MULTIBUS address space. The board's flag byte address (wake-up address) is jumper selectable (see Table A-3) with eight options available in the

MULTIBUS address space. The iSBC 548 and iS4H In the most ideal mult each controller board (iSBC 548, 547 or 546) would have different

I/O mapping, different memory mapping and different .interrupt lines. Under these conditions up to eight controller boards can be used in a system.

In a system application where more than eight controller boards are required the boards are grouped so that several boards share the same I/O address and the same interrupt line. The boards however cannot share the same address space.

As an example, if a system has one unused interrupt line, two unused I/O address lines, in the 8AO through 8A7 range, and 20 unused address locations in the range the controller boards can be configured to (see Table A-4), than 20 different controller boards can be installed in the system. The boards will share the same interrupt line and use either one or two I/O addresses.

3.4.1 CONNECTOR CONFIGURATIONS

On all three boards connectors PI and P2 are the MULTIBUS connectors. Pin assignments for each connector are provided in

Table 5-1 and Table 5-3 respectively. The location of each connector on each board is shown in Figures 3-1, 3-2, and 3-3.

Table 5-1 and Table 5-3 respectively.

On the iSBC 548 board connectors Jl and J2 are the serial I/O connectors (see Table 5-6 for pin assignments).

3-2

INSTALLATION

On the iSBC 547 board connectors Jl through J8 are the serial I/O connectors (see Table 5-5 for pin assignments) .

On the iSBC 546 board connectors Jl through J4 are the serial I/O connectors (see Table 5-4 for pin assignments). connector J5 is the printer interface connector (see Table 5-7 for pin assignments and Table 5-8 for signal descriptions).

3.4.2 BATTERY BACKUP

In order to use the battery backup for the clock/calendar on the iSBC 546 board the jumper between E30 and E3l must be installed by the user. In the default condition (as delivered from the factory) the backup battery is installed but the jumper is not.

3-3

INSTALLATION

PIN 1

TOP

PIN2

BOTTOM

PIN 39

TOP

PIN 40

BOTTOM SERIAL

CONNECTOR J1

PIN 1

TOP

PIN2

BOTTOM

PIN 39

TOP

PIN 40

BOTTOM SERIAL

CONNECTOR J2

MULTIBUS®

CONNECTOR P1

MULTIBUS@

CONNECTOR P2

Figure 3-1. iSBC 548 Board Connector Locations

3-4

2339

INSTALLATION

SERIAL CIHANNEL CONNECTORS

MULTIBUS®

CONNECTOR Pl

MULTIBUS~

CONNECTOR P2

2342

Figure 3-2. iSBC 547 Board Connector Locations

:3-5

INSTALLATION

PRINTER

INTERFACE

CONNECTOR

J5

SERIAL

CONNECTOR

J4

/

SERIAL

CONNECTOR

J3

/

SERIAL

CONNECTOR

J2

/

Figure 3-3. iSBC

MULTIBUS®

CONNECTOR Pl

MULTIBUS®

CONNECTOR P2

546 Board Connector Locations

2341

3.4.3 CABLING

The iSBC 548 board requires two flat 40 conductor cables to connect to the back panel. These cables can be acquired from Intel as part of the Intel 310 Cable Kit or can be fabricated by the user. Table

3-1 summarizes the recommended cable and connector part numbers for the iSBC 548 board. Figure 3-4 shows the cable construction.

Table 3-2 lists the pin to pin wiring for the cable shown in Figure

3-4.

3-6

INSTALLATION

The iSBC 546 and iSBC 547 boards do not require cables. Connection is made directly on the card edge.

Table 3-1. Recommended Cables and Connectors

Connector Manufacturer Part Number

40 Pin or

40 Pin or

40 Pin or

40 Pin

9 Pin

3M

3M

3417··6000 (without strain relief)

3417-6040 (with strain relief)

T&B Ansley 609-4000M (without strain relief)

T&B Ansley 609-400lM (with strain relief

T&B Ansley 609-9P-ML (metal shroud, male)

Table 3-2. Pin to Pin wiring List

9

10

11

12

5

6

7

8

13

14

1

2

3

4

15

16

17

18

40 Pin P4 P3

Connector

40 Pin P2 P1

Connector

5

9

4

8

3

7

2

6

1

-

-

19

-

20

-

-

21

-

-

-

22

-

23

24

25

26

27

-

5 28

-

9 29

-

4 30

-

8 31

-

3 32

-

7 33

5

9

4

8

3

7

2

6

1

-

5

-

9

-

4

-

8

-

3

-

7

-

-

-

-

-

-

2 34

-

2

-

6 35

-

1 36

-

6

-

1

-

-

-

-

P1ns 37 through 40 of 40 p1n connector not used. P1 through P4 are 9-pin connectors.

3-7

INSTALLATION r---~-5

BOTTOM

EACH 9

CONDUCTOR

LENGTH IS 5 INCHES

LAST FOUR

PINS OPEN iSBC® 548

COMPONENT SIDE

40 PIN MALE

CONNECTOR

2334

Figure 3-4. iSBC 548 RS232C Cable Construction

3-8

INSTALLATION

3.5 INSTALLATION PROCEDURE

The following is a general procedure for installing the terminal controller boards.

1. Check Appendix A for the jumper configuration.

2. Ensure that power to your system is turned off.

3. For the iSBC 548 board install the I/O cables to the

40 pin connectors.

4. Install the terminal controller board into the appropriate slot in your cardcage. Ensure that connectors Pl and P2 are fully seated in the cardcage.

3-9

CHAPTER 4

PROGRAMMING CONSIDERATIONS


This chapter describes the programming considerations applicable to the users of the iSBC 546, iSBC 547 and iSBC 548 boards. This information can be used by a user wishing to run his own software on the boards, using the download feature.

4.2 JUMPERS

Appendix A of this manual locates the various jumpers (for all three controller boards) and describes their functions. The user should reference this appendix to verify that the required jumpers have been installed by the factory (the default condition) or to install his own configuration.

4.3 ADDRESSING

Figure 4-1 is a memory map for the iSBC 546/547/548 controllers.

The controller boards include two 28 pin sockets that can support either 2764, 27128 or 27256 EPROMs. Decoding of this memory portion is done by the 80185 processors UCS (Upper Chip Select) signal.

Because of the different EPROMs capacities the starting addresses for this memory portion will vary as follows:

EPROM

2764

27128

27256

Memory Size

16K

32K

64K

Starting Address

FCOOO(H)

F8000(H)

FOOOO(H)

There are four 64K x 4 DRAMS on each controller board, a total of

128K Bytes. The upper 32K Bytes can be addressed by other MULTIBUS

4-1

BOIB6

Microprocessor

OFFFFF(H) ~-===

UCS

__ ~

64K Bytes

FCOOO(H),

2764 EPROM/

FBOOO(H),

2712B EPROM/

FOOOO (H), /

27256 EPROM

PROGRAMMING INFORMATION

On-Board

Memory

16/32~64

K Bytes

EPROM

MULTI BUS

FFBOOO(H)

-:..-

- - -

' - - - - - -

FSOOOO(H)

OFFFFF (H)

I

64K Bytes

Dual Port

RAM

RAM r:,.-

32K Bytes

- - -

-

LCS

12BK Bytes OSOOOO(H) ~ ~

NOTE

Dual-ported RAM can be accessed on the

MULTIBUS between SOOOO(H) and FSOOO(H) or FBOOOO(H) and FFBOOO(H) on any 32K boundary.

Figure 4-1. iSBC 546/547/548 Boards Memory Map

4-2

PROGRAMMING CONSIDERATIONS master boards. The dual-ported RAM can be addressed from the

MULTIBUS interface at any 32K boundary starting between 80000(H) and F8000(H) or between F80000 and FF8000. The starting address is jumper determined see Appendix A). For the iSBC 546 board the default starting address is OFAOOOO(H). For the iSBC 547 and 548 boards the default starting address is OF90000(H).

4.4 PROGRAMMING CONSIDERATIONS sections 4.4.1 through 4.4.3 discuss the programming considerations for the three controller boards

4.4.1 FIRMWARE

The firmware for the controller boards is described in detail in

Appendix B of this manual. The following paragraphs provide a brief description of firmware operation.

The 80186 microprocessors on the iSBC 547 and iSBC 548 boards control eight serial data channels. The 80186 on the iSBC 546 controls four serial data channels. The data received from the channel is communicated to the MULTI BUS host and the data transmitted to the channel is received from the MULTIBUS host. The

MULTIBUS host informs the controller's 80186 which channels to enable and which not. The 80186 continuously polls the enabled channels looking for data or the request for data.

On the iSBC 546 board the line printer channel and clock/calendar are treated like serial channels.

4.4.2 80186 PROCESSOR PROGRAMMING CONSIDERATIONS

When programming the controller's 80186 microprocessor the following guidelines should be followed:

1. The LCS (Lower Chip Select) should be programmed for

128K Byte size and zero wait states.

4-3

PROGRAMMING CONSIDER1!.TIONS

2. The UCS (Upper Chip Select) should be programmed for

64K Byte size and zero wait states.

3. The PCS (Peripheral Chip Select) should be I/O mapped and configured as follows:

PCS o

1

2

Function

Selects DSR port. PCSO is not to to be used for for an output.

Selects serial ports 1 and 2.

Selects serial ports 3 and 4.

3

4

Selects serial ports 5 and 6 on iSBC 547 and 548 boards and line printer interface and clock/calendar on the iSBC 546 board.

Selects serial ports 7 and 8 (iSBC

547 and 548 only)

5 sets MULTI BUS interrupt port when used as an output. PCS5 is not to be used as an input.

One wait state: should be used for the PCS lines.

If the PCS lines base address is O(H) then the I/O map will be as follows:

Address Port Type

0000 0000 OXXX XXXX

0000 0000 1XXX XOOO

0000 0000 1XXX X010

0000 0000 1XXX X100

0000 0000 1XXX X110

DSR Port

Serial Line 2, control

Serial Line 2, data


Serial Line 1, data

I

I/O

I/O

I/O

I/O

4-4


0000 0001 OXXX XOOO

0000 0001 OXXX XOIO

0000 0001 OXXX XIOO

0000 0001 OXXX XIIO

0000 0001 lXXX XOOO

0000 0001 lXXX XOIO

0000 0001 lXXX XIOO

0000 0001 lXXX XIIO

0000 0010 OXXX XOOO

0000 0010 OXXX XOIO

0000 0010 OXXX 0100

0000 0010 OXXX 0110

0000 0010 lXXX XXXX serial Line 4, control

Serial Line 4, data


Serial Line 3, data

Serial Line 6, control or

Line Printer serial Line 6, data or clock/calendar

Serial Line 5, control or Line

I/O

I/O

I/O

I/O

I/O

0

I/O

I/O

Printer and clock/ calendar controls

Serial Line 5 data I/O or 8255 control


Serial Line 8,

0

I/O

I/O data


Serial Line 7, data

MULTI BUS Interrupt

I/O

I/O

0

In the RAM case EXTERNAL RDY overrides INTERNAL RDY. If

INTERNAL RDY is active but EXTERNAL RDY is not, a wait state must be inserted.

The A2 address line selects between serial channels on the same components. When A2 equals a the port with the larger number is selected.

4-5

PROGRAMMING CONSIDERATIONS

The 80186 address mapping I/O should be programmed as follows:

Port Address Data

UMCS (Upper Memory Chip Select)

LMCS (Lower Memory Chip Select)

PACS (Peripheral Chip Select)

MPCS (Mid-Range Peripheral

Chip Select)

OFFAO(H}

OFFA2(H)

OFFA4(H)

OFFA8(H)

4. Timer 1 is programmed for a 1 Mhz output. Its mode control (I/O address 5E(H» should be written with

OC003(H) and the count register (I/O address 5A(H» should be written with 00001(H).

OF038(H)

IFF8(H)

0039(H)

80B9 (H)

5. The interrupt controller should have only one external interrupt. INTI from the flag byte activates interrupt 13 routine.

Except for software interrupts there are only two timer interrupts available, timers 0 and 2 can be used by the firmware.

4.4.3 8255 PROGRAMMING

Programming considerations for the 8255 Programmable Peripheral

Interface (PPI) are as follows:

The 8255 PPI control word (address 186(H» should be programmed

OA4(H) when the clock is to be set, and OA6(H) when the clock is to be read. To set PC4 and PC5 to desired levels, single bit addressing should be used.

To determine if data from the clock is available bit 0 of the input port 184(H) should be checked. If bit 0 is 1 data is available.

To determine if the clock or line printer are ready for more data, port 184(H) bits 0 (for clock) and 3 (for line printer) should be read. A 1 for either bit indicate a readiness for more data.

4-6


4.4.4 DSR PORT

The DSR port control word format for each controller board is shown below:

Dl DO D7 D6 D5 D4 D3 D2

Line No Llne

Fault Printer Paper Printer DSR4

Select Busy lSBC 546 Board

DSR3 DSR2 DSRI

D7

DSR8

D6 D5 D4 D3 D2 Dl DO

DSR7

I

DSR6

I

DS~5

I DSR4

I

DSR3

DSR2 DSRI lSBC 547 and lSBC 548 Boards

4.5 BAUD RATE PROGRAMMING (ALL BOARDS)

To program the baud rate of a specific channel a time constant must be written to its time constant register. The time constant is calculated as follows:

Time Constant

Clock

=

------=-=-~-=~-----

32 X Baud Rate

Where: Clock

=

4.9152 Mhz

2

Baud rates and their corresponding time constants are as follows:

Baud Rate Time Constant (Decimal)

19,200

9,600

4,800

6

14

30

2,400

1,200

600

300

62

126

254

510

4-7

CHAPTER 5

INTERFACING INFORMATION


This chapter provides pin assignments for all connector interfaces of the iSBC 546, iSBC 547 and iSBC 548 boards.

5.2 MULTIBUS INFORMATION

All three boards connect to the MULTI BUS interface through board connectors PI and P2. Table 5-1 lists MULTIBUS connector PI pin assignments, Table 5-2 describes the functions of the PI signals.

Table 5-3 lists MULTIBUS connector P2 pin assignments.

25

27

29

31

33

Pin

7

9

11

I

3

5

13

15

17

19

21

23

Table 5-1. MULTIBUS Connector P1 Pin Assignments

(Component Side) (Circuit Side)

Mneumonic Description

GND

+5V

+5V

+12V

GND

Signal GND

+5 Vdc

+5 Vdc

+12 Vdc

Reserved

Signal GND

MRDC*

XACK*

LOCK*

BHEN*

Mem Read Cmd

XFER Ack

Bus Lock

Byte High En

26

28

30

32

34

14

16

18

20

22

24

2

4

6

8

10

12

Pin Mnemonic Description

GND

+5V

+5V

+12V

GND

INIT

Signal GND

+5 Vdc

+5 Vdc

+12 Vdc

Reserved

Signal GND

Initialize

MWTC*

IOWC*

Mem Write Cmd

I/O Write Cmd

INHl* ~nhibit I

Reserved

ADRI0*

ADRll* Address Bus

ADR12*

ADR13*

5-1

INTERFACING INForumTIoN

Table 5-1. MULTIBUS Connector P1 Pin Assignments (continued)

(Component S~de) (C~rcu~t S~de)

Pin Pin Mnemonic Description

59

61

63

65

67

69

71

73

35

37

39

41

43

45

47

49

51

53

55

57

Mneumonic Description

INT6*

INT4*

INT2*

INTO*

ADRE*

ADRC*

ADRA*

ADR8*

ADR6*

ADR4*

ADR2*

ADRO*

Parallel

Interrupt

Requests

}~ddress Bus

DATE*

DATC*

DATA*

DAT8*

DAT6*

DAT4*

DAT2*

DATO*

Data Bus

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

INT7*

INT5*

INT3*

INT1*

ADRF*

ADRD*

ADRB*

ADR9*

ADR7*

ADR5*

ADR3*

ADR1*

DATF*

DATD*

DATB*

DAT9*

DAT7*

DAT5*

DAT3*

DAT1*

Parallel

Interrupt

Requests

Address Bus

Data Bus

75

77

79

81

GND

-12V

+5V

+5V

Signal GND

Reserved

-1~! Vdc

+5 Vdc

+5 Vdc

76

78

80

82

84

GND

-12V

+5V

+5V 83

85 s~gnals

GND Signal GND 86 GND

. not shown are not used ~n th~s appl~cat~on signal GND

Reserved

-12 Vdc

+5 Vdc

+5 Vdc

Signal GND

5-2


Table 5-2. MULTIBUS

Signal connector Pl signal Descriptions

Functional Description

ADRO* - ADRF*

ADRIO* - ADR13*

DATO* - DATF*

INH1*

INIT*

IOWC*

LOCK*

MRDC*

Address. These 20 lines transmit the address of the memory location or I/O port to be accessed. ADR13 is the most significant address bit.

Data. These 16 bidirectional data lines transmit and receive data to and from the addressed memory location or I/O port. DATF* is the most significant bit.

Inhibit RAM. For system application, allows the RAM addresses to be overlaid by another

RAM or ROM in the system.

Initialize. This signal resets the entire system to a known internal state. The iSBC 546, iSBC 547 and iSBC 548 boards are slave boards and will never generate INIT*.

These boards require an INIT* pulse of 50 microseconds or longer for proper operation.

I/O write. Indicates the address of an I/O port is on the MULTI BUS interface address lines and that the contents on the MULTIBUS interface data lines are to be accepted by the addressed port.

Lock. When the MULTIBUS master accesses the on-board dual port RAM and activates LOCK* the on-board resources are locked out by the dual port RAM until the MULTI BUS master removes LOCK*.

Memory Read Command. Indicates that a memory location address is on the MULTIBUS interface address lines and that the contents of that location are to be read on the MULTIBUS interface data lines.

5-3

INTERFACING INFOru~TION

Table 5-2. MULTIBUS Connector Pl signal Descriptions

(continued)

Signal

MWTC*

XACK*


Memory write Command. Indicates that a memory location address is on the MULTI BUS interface address lines and that the contents on the

MULTI BUS interface data lines are to be written into that location.

Transfer Acknowledge. Indicates to the bus. master that the read or write operation is completed by the generating device and that valid data is available on the MULTIBUS interface.

5-4


Table 5-3. Connector P2 Pin Assignments

(Component Side) (Circuit Sl.de)

!

Pin Mnemonic Description Pin Mnemonic Description

13

15

17

19

21

23

25

27

29

1

3

5

7

9

11

,

31

33

35

37

39

I 41

43

45

47

49

51

53

55 ADR16*

57 ADR14*

59

Address

Bus

14

16

18

20

22

24

26

28

2

4

6

8

10

12

30

32

34

36

38

40

42

44

46

48

50

52

54

56 ADR17*

58 ADR15*

60

Address

Bus

I

I

Note: 1If address lines ADR14 through ADR17 are not used in specific system applications they are held high at connector P2, by the iSBC 546/547/548 boards.

2. Signals not shown are not used in this application.

5-5


5.3 SERIAL INTERFACES

All three boards, iSBC 546, 547 and 548 have RS232C serial interface connectors. The serial interface connectors associated with each board are shown below:

Board iSBC 546 connectors

Four 9 pin connectors, JI through J4 iSBC 547 iSBC 548

Eight 9 pin connectors, JI through J8

Two 40 pin connectors, JI and J2

Pin assignments for the iSBC 546 board connectors are shown in

Table 5-4. Table 5-5 shows the pin assignments for the iSBC 547 boards serial interface connectors and Table 5-6 shows the pin assignments for the iSBC 548 boards serial interface connectors.

Table 5-4. Serial Connectors Pin Assignments, iSBC 546 Board

Connector Jl


Connector J2

Mnemonic Description

1

2

3

CDI

RXDI

TXDI

DTRI

GND

DSRI

RTSI

Carrier Detect

Receive Data

Transmit Data

1

2

3

Data Terminal Rdy 4

CD2

RXD2

TXD2

DTR2

See

Description

Connector Jl

4

5

6

7

Ground

Data Set Ready

Request to Send

5

6

7

GND

DSR2

RTS2

8

9

CTSI

RII

Clear to Send

Ring Indicator

8

9

CTS2

RI2

. . .

Note: 1. Number at the end of the mnemon~c ~nd~cates channel.

5-6


Table 5-4. serial Connectors Pin Assignments, iSBC 546 Board

(continued) connector J3 connector J4

Pin Mnemonic Description Mnemonic Description

5

6

7

8

9

1

2

3

4

CD3

RXD3

TXD3

DTR3

GND

DSR3

RTS3

CTS3

RI3

Carrier Detect

Receive Data

Transmit Data

1

2

3

Data Terminal Rdy 4

Ground

Data Set Ready

5

6

Request to Send

Clear to Send

Ring Indicator

7

8

9

CD4

RXD4

TXD4

DTR4

GND

DSR4

RTS4

CTS4

RI4

See

Description

Connector J3

-

Note: 1. Number at the end of the mnemon1C 1nd1cates channel.

Table 5-5. serial Connectors Pin Assignments, iSBC 547 Board

Connector Jl Connector J2

-

Pin Mnemonic

5

6

7

8

1

2

3

4

9

CDl

RXDl

TXDI

DTRl

GND

DSRl

RTSl

CTSl

RIl

Description

Carrier Detect

Receive Data

1

2

Transmit Data 3

Data terminal Rdy 4

Ground

Data Set Ready

5

6

Request to Send

Clear to Send

Ring Indicator

7

8

9

Mnemonic

CD2

RXD2

TXD2

DTR2

GND

DSR2

RTS2

CTS2

RI2

Description

See

Description

Connector Jl

Connector J3

--


Connector J4

Mnemonic Description

1 CD3

RXD3

See

Description

1 CD4 See

2

TXD3 Connector Jl

2 RXD4 Description

3

DTR3

3 TXD4 Connector Jl

4 4 DTR4

.

Note: 1. Number at the end of the mnemon1C 1nd1cates channel.

5-7

INTERFACING INFORMA'rION

Table 5-5. serial connectors Pin Assignments, iSBC 547 Board

(continued) connector J3


5

6

7

8

9

GND

DSR3

RTS3

CTS3

RI3

See

Description

Connector Jl

5

6

7

8

9 connector J4 l'1nemonic

GND

DSR4

RTS4

CTS4

RI4

Description

See

Description

Connector Jl

1

2

3

4

5

6

7

8

9

Connector J5

Pin Mnemonic Deseription

CD5

RXD5

TXD5

DTR5

GND

DSR5

RTS5

CTS5

RI5

See

Description

Connector Jl

1

2

3

4

5

6

7

8

9

Connector J6

I1nemonic

CD6

RXD6

TXD6

DTR6

GND

DSR6

RTS6

CTS6

RI6

Description

See

Description

Connector Jl

Connector J7 Connector J8

Pin Mnemonic Description Hnemonic Description

1

6

7

8

9

2

3

4

5

CD7

RXD7

TXD7

DTR7

GND

DSR7

RTS7

CTS7

RI7

See

Description

Connector Jl

1

2

3

4

5

6

7

8

9

CD8

RXD8

TXD8

DTR8

GND

DSR8

RTS8

CTS8

RI8

See

Description

Connector Jl

Note: 1. Number at the end of the mnemonlC lndlcates channel.

5-8


Table 5-6. serial Connectors Pin Assignments, iSBC 548 Board

Connector Jl RS232C

Pin Mnemonic Description Pin

GND

RI8

DTR8

CTS8

TXD8

RTS8

RXD8

DSR8

CD8

GND

RI7

DTR7

CTS7

TXD7

RTS7

RXD7

DSR7

CD7

GND

RI6

DTR6

CTS6

TXD6

RTS6

RXD6

DSR6

CD6

GND

RI5

DTR5

CTS5

TXD5

RTS5

RXD5

32

33

34

35

36

24

25

26

27

28

29

30

31

37

38

39

40

15

16

17

18

19

20

21

22

23

7

8

9

10

11

12

13

14

1

2

3

4

5

6

DSR5

CD5

-

-

-

-

Ground

Ring Indicator,Ch8

Data Term Rdy,Ch8

Clear to Send,Ch8

Transmit Data,Ch8

Reg to Send,Ch8

Receive Data,Ch8

Data Set Rdy,Ch8

Carrier Detect,Ch8

Ground

Ring Indicator,Ch7

Data Term Rdy,Ch7

Clear to Send,Ch7

Transmit Data,Ch7

Reg to Send,Ch7

Receive Data,Ch7

Data Set Rdy,Ch7

Carrier Detect,Ch7

Ground

Ring indicator,Ch6

Data Term Rdy,Ch6

Clear to Send,Ch6

Transmit Data,Ch6

Reg to Send,Ch6

Receive Data,Ch6

Data Set Rdy,Ch6

Carrier Detect,Ch6

Ground

Ring Indicator,Ch5

Data Term Rdy,Ch5

Clear to Send,Ch5

Transmit Data,Ch5

Reg to Send,Ch5

Receive Data,Ch5

Data Set Rdy,Ch5

Carrier Detect,Ch5

6

8

1

5

2

4

3

1

22

20

5

2

4

3

6

8

22

20

5

2

4

3

6

8

1

22

20

1

22

20

5

2

4

3

6

8

1

5-9


Table 5-6. serial connectors Pin Assignments, iSBC 548 Board connector J2 RS232C

Pin Mnemonic Description Pi.n

HXD3

DSR3

CD3

GND

RI2

DTR2

CTS2

TXD2

RTS2

RXD2

DSR2

CD2

GND

Rl1

GND

RI4

DTR4

CTS4

TXD4

RTS4

RXD4

DSR4

CD4

GND

RI3

DTR3

CTS3

TXD3

RTS3

27

28

29

30

31

32

33

19

20

21

22

23

24

25

26

12

13

14

15

16

17

18

34

35

36

6

7

8

9

10

11

37

38

39

40

1

2

3

4

5

DTR1

CTS1

TXD1

RTS1

RXDI

DSR1

COl

-

-

-

-

Ground

Ring Indicator,Ch4

Data Term Rdy,Ch4

Clear to Send,Ch4

Transmit Data,Ch4

Req to Send,Ch4

Receive Data,ch4

Data set Rdy,Ch4

Carrier Detect,Ch4

Ground

Ring Indicator,Ch3

Data Term Rdy,Ch3

Clear to Send,Ch3

Transmit Data,Ch3

Req to Send,Ch3

Receive Data,Ch3

Data Set Rdy,Ch3

Carrier Detect,Ch3

Ground

Ring Indicator,Ch2

Data Term Rdy,Ch2

Clear to Send,CH2

Transmit Data,Ch2

Req to Send,Ch2

Receive Data,Ch2

Data Set Rdy,Ch2

Carrier Detect,Ch2

Ground

Ring Indicator,Ch1

Data Term Rdy,Ch1

Clear to Send, ChI

Transmit Data,Ch1

Req to Send, ChI

Receive Data,Chl

Data Set Rdy,Ch1

Carrier Detect,CH1

1

22

20

5

2

4

3

6

8

1

22

20

5

2

4

1

22

20

5

2

4

3

6

8

22

20

5

2

3

6

8

1

4

3

6

8

5-10


5.4 PRINTER INTERFACE (iSBC 546 ONLY)

The iSBC 546 board has a line printer interface connector (J5).

Table 5-7 shows the pin assignments for the connector. Table 5-8 describes the function of the printer interface connector signals.

Table 5-7 Printer Interface Connector J5 Pin Assignments

Pl.n Mnemonic Descriptl.on

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

1

2

3

4

5

6

7

8

LP STB*

LDATO

LDATI

LDAT2

LDAT3

LDAT4

LDAT5

LDAT6

LDAT7

LP ACK

LP BUSY

NO PAPER

LP SELECT

-

FAULT

LP RST

-

GND

GND

GND

GND

GND

GND

GND

GND

Line Printer strobe

Line Printer Data Bit 0








Line Printer Acknowledge

Line Printer Busy

No Paper

Line Printer Select

Not Used

Fault

Line Printer Reset

Not Used

Ground

Ground

Ground

Ground

Ground

Ground

Ground

Ground

5-11

INTERFACING INFOru~TION

Table 5-8. Connector J5 signal Descriptions

Signal

LP STB*

LPDATO through

LPDAT7

LP ACK*

LP BUSY

NO PAPER

LP SELECT

FAULT

LP RST


Line Printer Strobe. This signal is sent to to the line printer and causes the printer to strobe the data on the data lines (LDATO through LDAT7) into the printer.

Data Bus. This is the data bus between the iSBC 546 board and the line printer. The contents of the data bus are strobed into the line printer by LP STB*.

Line Printer Acknowledge. The line printer activates this signal to indicate it has accepted the data strobed off the data lines.

Line Printer Busy. This signal is activated by the line printer to indicate it is busy and cannot accept more data.

No Paper. This signal from the printer indicates it is out of paper.

Line Printer Select. This signal is activated by the line printer to indicate it is ready for use.

Fault. This signal from the printer indicates a-j;)roblem has developed which will prevent further printer operation.

Line Printer Reset. This signal is generated by the iSBC 546 board to reset the line printer.

5-12

CHAPTER 6

SERVICE ASSISTANCE INiFORMATION

6.1 INTRODUCTION

This chapter provides a list of service diagrams a.nd service and repair assistance instructions for the iSBC 548, iSBC 547, and iSBC 546 boards.

6.2 SERVICE AND REPAIR ASSISTANCE

Intel customer Support Service Engineering provide!s both a Return

Replacement Authorization (RRA) and Direct Return Authorization

(DRA) service.

The RRA service provides replacement of a defective board. Return the defective board to Intel, freight prepaid, and Intel will replace the board with a new serial number board. This service is not offered on all products. It is subject to board availability, and is available to customers in non-service areas~. Intel expects to ship 90% of these products within 48 hours of receiving the defective board.

The DRA service provides repair work. Return the defective board to

Intel, freight prepaid, and Intel will repair, tes~t and update the board, with all mandatory Engineering Change Orders. The boards serial number will not change. Normal turn-around time is four to six weeks.

Determine which service fits your needs, RRA or DF~. Before calling customer Support Service (Refer to Figure 6-1 for the telephone number in your area) have the following information ready:

1. Part and serial number of the board.

2. Purchase order number, needed for rep~Lir and shipping charges.

3. If it is a warranty repair, proof of purchase is required. Purchase must have been within 90 days of the service request. without proof of purchase date services will be billed at the current: rate.

6-1


4. Your shipping and billing address.

5. Your Intel contact and your telephone number.

In correspondence with customer support Engineering, reference the authorization number on the packing slip, the purchase order, and other related documents.

Canada - 416·675·2105

602·869·4392 602·869·4951

, j\,

I

I

I-j i

1-

~.1~

602·869·4023 !'

I \

'\J

International - 602·869·4862

602·869·4045

M·01H

Figure 6-1. Territorial Service Telephone Numbers

Before shipping remove all user modifications. Protect the product from damage in transit as follows:

1. Boards should be placed in anti-static bags, and then in padded shipping bags. Large items should be wrapped in anti-static material.

2. Allow room in the box for protective padding, e.g. flow pack, foam etc.

3. write the return authorization number on the outside of the box, and label the box "FRAGILE".

4. Damage sustained due to the lack of compliance safe return packaging could result in ext.ra repair charges.

6-2


5. Forward the board and all correspondence to:

Intel Corporation customer Support Marketing Ad.

Billing Department DV-1-704A

2402 W. Beardsley Road

Phoenix, Arizona 85027

Authorization

*

- - - - -

6.3 SERVICE DIAGRAMS

Figure 6-2 is the schematic diagram for the iSBC 548 board. Figure

6-3 is the schematic diagram for the iSBC 547 board and Figure 6-4 is the schematic diagram for the iSBC 546 board.

On the schematic diagrams a signal mnemonic followed by an asterisk indicates a signal active in the low state. Conversely a signal mnemonic without an asterisk indicates a signal active in the high state.

6-3

m m

SERVICE ASSISTANCE INFORMATION

,'j

~

,' . . . " ,:,

(~ ,~

"" II, ,',

-~.I--

/1'

...... ,.... .. ...

N n _ z ,"

FO i:

~i

~

'-

...

,-.--,.--

......

... .. ., .. '* ..... ..............

Q ... N l~' ....... ' "

~.g: .g: '" ([

<l« r. a:

~~-

I-------~.-= -

,.

........... . e,···oJ'"".-.... ....

.::.

, oI .., ""

....

-.....

'1 ""

~.

_---

""

(IJ

I-;;,t-------t+-

--+-+t-------- ++---F------f--.

~

,..... *

.. ."....

Figure 6-2 iSBC 548 Schematic Diagram (Sheet 2 of 11)

6-5

Dl Dl H Dl

~ ~~

:1

I-~-~~i


"" a;I r.. "-

~ ~ f')

M

N • • <::'~~JM""'"

J : V ! ' ' ' ' ' ' ' ' ' t n V l < J l ' f .

J:UUU<..)UUUU

_::l..J

Il.. "0..

II..

Q..

CO-

'-------+-+-+-H-H-"

.. -1f-;;.J_.

--<>

U

U

'\J Q

'\J I/'l l.~ -If-..

.,.

Il> if'

.

,

.

~j

"

C;

.

0

"

"

~

-~-

- - -


6-7

• '*

Z Q

W 0:

U

I-

:I

L'

I(l Q

0. u:

>-

Vl Q

~~ ~~~~5

Or:


....

-<.Ju ....

.:I: .... j:I::I.

...

~

II: _ j--Q~~

"

.

~~";L_

% ,

~----------------------------,"---.----


6-8

SERVICE ASSISTANCE INFORMATION i

I

I i i

I.

!

I

OJ

Q

Ci

.,., -

.u~,~,,

,."c,."[

,J:

<t

Q oJ: ,_ u

 w o o ':> I', -" ., " " . "

,,' '" "

R

,/) <D ''-

'" Ill ... (')

~

III '" _

III ... _

1\1

M

N N N '"

<JJ "ru ru

I:< _

N ('")., III

~~~~~a:~?i~Q'Q'Q'««a

.J . .J ...J

..J ....J

..J ..J _, ...l ...J ...J ...J .J .J .J

C\J

<\I

...

'Ii w w (") f\,I to

C\J u,

---'


6-9


-------~------------------------------.w

J' c'

- f - -

:1

I

1-

J," ,

"~l-~ =-J~]

F-~'I ~-=~-~

-- [=

1;:tL--::j:~=t=~--J

1-

, 1

I

I

I":-~

"" -,-

-t--

~L ~I: :J=-~1' ~ ~"~ c,j.l

:,; : "--;,':----."."" ;" "_"." __ ."'

!

~ ~ ~

!

~ ~

:M e

! i~H{11~;~~1 ~~ ::~::~~~ ~

_ _

_ : r - u ru ru

~y .~

"" " " "

" ru

0"

J

"

I i

I i

!

I

I '

' ' ' , , ' .. '<t<'lCl.-IL

(, -

"-

.-, ... ::J ::J

"'£l<Qr:£l<lLo..


6-10

[1


~~-"'-"'--~'-----------'--~----'~~-""---

''':.' - - : - -

_'c'~'

'l

:'1"

In V'> II"

,

In ..; "':

~

. . . . . . ,., f"') o,j)

~

I:

\

,

'"

,

:1 i.: '

I '"

- • \>~1 ._- •

:~

" ., i,;.::

I_I

~~,

....

/"

'

',: "

, , / , , '

--

-=~~==---

_ n.J..,"

If).j) I'\, Q)

( I ( [ ( [ ' I :

<I <r <I: <I

ONM

"'---

• "I ...

.",,,...,

",,'"

~

"

". , . , ........

" " "

' "

". ..

::::::::::.::.:::

..

'-----------=--~-~-~---~~,---,-,--~-,-

Figure 6-2 iSBC 548 Schematic Diagram (Sheet 8 of 11)

6-11


.' .'.' .'.'c. '.'

.',','.'.'.'.'.'.""'e,~r.,,,,,

,V,,,','.'""",·" r.'. ".'HeN.V".'",r, "''':'

:f.. \. .

+

~

~-:~~ ~-:~~

!.,

I·

II-,,;-~

I-,,~,

- 1;;;-:,.

~

Figure 6-2 iSBC 548 Schematic Diagram (Sheet 9 of 11)

6-12


!

I

I

I

.!

" T -

,!

I

I:;:'·

.... ," I,·

112

_-==' t=t±::±tJ

nH:

I j >:~<: t;-~

li"

"j

:

1

; 1

I

Jl

~

I ! i i

I

,I

I

U] I

I

I l

I

,

I ~ ':;

I ' > -

,1,1

1 i

I

1 i i: :


6-13

,11~n

!,

.: " ~l'


--'''''-'----=--~-"

.~, 'I

.

.

""~U')llr.o::t.lII

1':1"'111[""1-111:

,)..--

,

£1

"

II ,

, i I i I

Ii

II

:: ,:

~

:,1"1'1

...... '>. ....

1. I,,·

" " " ,I. ,I, ,.

~:

--+4+4-11--1---1--1---1--1--+---1--1-----

'++++-++-.

~--'-. ~-.~

:-:.

----_._-

::

._~~

------+++.~

~---------

' - - - - - - - - - - -

~

,...g

--~

~-:~~========++ttt+=,~,

"

" I . " ,

,~ <, '"

....... 0:.:"',.... ...

Q:I'lIInI¥A<n

I - X I - I - X t -

0::1.1-l1li:1'111-111:

9E

_ ... _---- .. -

-.----.--=.----,----=~---------,--~.~------,~.-


6-14

i~-±-

·1

I

J


...

........ ., * .. . wa-« ... '-""' ... ...

, - 1 - 1 - 1 - 1 - 1 - 1 - ....

<L

Q: (I:

<t '"

U

<I ([

A

~

"'" "'" "'" A"",,",

~, <0 t-.. '" ... v

,~ N

~--:::':....Cl.i...--

............... tl-N!'I"'~..o"-

1-1-1-1-1-1--1-1-

<J:

( [ ( [ < l

1"'-""",,,,,

...............

Q ' " N ,.,., ... If) '" f\.

......... 1 - 1 - 1 - 1 - 1 - 1 «

<l<I<J: aaa:a:

"'>1=01=1""''''0:11'1'''''

................

~;;;~:;::;~~~

~

~

«

Q

Q .

%

~

«

,

.

~

0

Z

-

" ~

E.

---

~~,.- --~--~~.--=:-~~.-~-,; -~-;--,,,-,.~--,


6-16


'I

?'

"J

'-''''!''l

" , ; , D

1')" In ~ "a a

0

~-"---"l' ···~'.'I ~:

.. i,,~-'

.

~,

~I.

-

-~--t---


6-17


- - - - - - - - - - -

"


6-18

I

II

1 W-=:l~

~~

"

SERVICE ASSISTANCE INFORMATION t

L

I r-

'--;: R,.. b\~ =!'~b\

I:

I 0 0 •

I/')

RRRR~-':J

_ N M • U U w o w

'f w

-

-f

w

"f

•

Q

.

....

U U

R : l

. . (J

:r

I-

% :I '" 0 o

Z

~

U


6-19


"<-"'('"· ...

"'",,""11"' _____ .......

<IQ:<t<J:<tQ:G:<t<l:a:G:4¢<l(l:

In I'.

("I(IJ au~

-n!-l[.;::~

" U

"

~---t---

I::!"" i:lo:lo:l'-'1QI:II=IR

([([G:<I:<J:<I<I<E

------

W '" ...... a

~ ct CI o:lRl=lo:l

Q _ < \ I M ...... ,.,"-

: U:J: 0:: t--

0

0 . dl

.

0 -

W"'

I • •

' , w

"

..

~

"'

0

' - - - - - - - - - - - - - - - - - - - - -


6-20

I

I

I; r ..


J

~.

~ tl

D[ g

~-

~

~

~I~

-or

Q (to

~~~~~~~~

'fJ.

.nA,~1 ~

_

~

N

~ jO)

~

. .

• I

~ ~!

I i

I

:

~ ~

0 -

L-

9

~

,,~

;;:!;

~

.~

0 _

• CJ

.. UI o

• •

CJ 111:-

"

_ o

•

N~

\f, N _ .. PI u ............... j j a..Co:Cll:tlQ(CLG. u u

16" 0 -

«

: : u

0 u

:

:


6-21


-' .'.'.'.'.' ,'.' -,,'H,',',',',',',',',',.',',',',','.','.'",,',',' ,',','.',',',',',',','",,',',"""""'"mr·' :

~~~~ 8-~; ilTI ___ _

' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -


6-23


~ ~ n n x

~

~

A

~

.

~

.

~ x

,

«

~

~ x

0,

~ n ,

...

G:

..

... I\l

111111

......

.. ru

UO

......

..

N

RR

......

W

W

>

II)

Ill"

::l ...

1<--_-+-__ j - -

~

1-' e

~

. .n

. A •

..

~ ~

~l

~

. A .

UU

"

.. a u a

-

" 0

.

M

. m

/\JCUNru u

~ u

~

~~~

...

«

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _


6-24


~

. ..

. u

_e" o . xo

. u o . u l'

""nc:<.

. u o

~I~

C,ot

,

-

,1

~~~

~

~~1

(j ,;

-r·'

~ l~"

. , -

~"

o _

9;; ~b;'

_ ru

:

• 0 "

'-l--

-+

~ t~

,

-

'-l-r-

~

J-.

~ ~

~

~

~

~

+r-

~

-+ k= c

~.~-

~

L

-+-

-+

,

,

~

,

""x

' 0 "

','

.0"


6-25

SERVICE ASSISTANCE INFORMATION w

L N

"

,

""" in

tVI X Q

0: 0 I:l IlDVlIII<""'"

" ' ! - V l X I O I

III< U o::l III< U

.. N

~ .

~-

;

~.,

~-

;

-~·ll' ~

.. J) r--

."

~-

..

~

'"

~

. . . m

M..

0 _ m

" '.

0 _

...

@

1\1

-

_

9

..

, _

~-

-11 l! j

~

.


6-26

SERVICE ASSISTANCE INFORMATION i i i

L

U

" N

. l~ "

- -e--~--o

·t-t-t-~-+-t-t-r~~-+-t--1-~-t-~-+~~~j-1-~-~-~~-+~+-I-+~~ r---

"

~ ~

,--

~T-+-+-t-t-+-

S

, ,

I--r-- -

,

-

~r--

,

.

,

;

~

Q

I

U

>

.

, . ' " <D

VI U

0.

Q< (.<;

Q< <') If)

U W "

(~

>-

•• _

':II'"


6-27

--


. . . ....... i ~~g u w u:.: ..

A I-::J

111::::100:;1:

I : E _ . . . I ....

0

. .

...............

Q;I ' " q III U R ... I..

1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 -

( I < ; [ ( [ ( I ( [ ( t c t G :

R R A A R A A A

................. ... n w. t!

~ h' g ,

~!

~

' - - -

MIIJ r· ...... .

",,111111l1li111l1li111111

................

Q - r u M . , I f l . , o l ' . . l1li111111111""l1li"'111 t:I_CIIM""I(l",,,

ARARAARA


6-28

0 z.

1

I

I

~ ~


«

~

.. w

0 t!~

'"''

• • ru <

0 ' r

J

. .

"

"

"

,

0 "

. ..

L

~ xl

Z 2

"

M

" . «

:§ ;:;

" "

~ ~


6-30 x

0

1:;:>1: ruru

<'I""",,,,,,,

" .


.

.

~

~ ill

. ill:

~l ill w. t: t

~:

,~

- - - - - - - .

0

.

~

~

~ o.

.. ..


6-31


..............

- - - - - - - l 1 l i 0 0 0 0 0 0 > 1 1

U o

" «

CU (') ". In

<I<I<l:<I:<J:<l<:l\I(I «<I<l<J:<I<J:

~~~...J...J...J...J...J_I...J...J...J....I...J...J t---

• D D

"""

D dl 0 _

~ ~ u

~ u «

~~ u u

" 0


6-32 c ;i1

~

1

~

0

~I~ ~

5

~ ~

6


, · . ,

"

.

ITt

6

ru

< ' ) " . III 'IJ I\. Q)

---

' " ....

_---

' - - - - - - i - -

L~

'-----

-

~

([ U "( I u "

L<:t

U "ru - . . . ... ru

l-~:~f~·'-----l--;---------J-..W

c " ' ru _ _NO'".,.

""""""""""""""'" I

-ruM"'I/l"""m~. a: <t

--

~

Vl ' " '"

Q

(f)

' " "" ' "

D.. 0

-.J Z

D.. <1

...J ...

::::::::: ...


6-34



6-35

SERVICE ASSISTANC:E: INFORMATION

. " . " . , . .

~ ~:

~ ~I:;·

L__

!

"JZJ

~ l-t;l"'(U(O)""n",,,"

VI I-l-f-->-- ..... I - l - I -

~~~~~~~~~

« ,

I...

U '" ....

0..

Pl<XNu):J a

I Q. 0n

J •

~ ~ ~AlrbF: f~~

10 ". M (\J ... .--

--= =

-

C! _

(\J (') ... In '" "-

::>::>::>::>::>

...J...J...J...J---'

U L J U U U

... ..., f\J

/;1"'00,,-

.... ". ,., M M

~~~~~~~~

0:0 '" t:l _ ruM ... In

(\/!'\J(UOJOJ

,~

.... (\J M ...

11'"1"',,-

,:qI'lPlPlPlPlPlPl

:Lo..o..a. CLo..a. 0..

::::::::

• ol.ln • , •

~r

-If

~

Lf---t-------H-.

I

~;

L-]

I~w"

.J ~

... M

(>') M ru .... t'l "", '" "-

M M M ru ru

I\J

JJ


6-36


_~O

-,~

OUR OU

.

• • 0 R .

OUR OU

-,.

OUR r

• ~ 0

R •

OUR OU

~

~"

,-

"

~"

. ,-

~

~;' ~;

_

~"

-.

~;'

~

~;' ~;

=

U;;;:i:::

"~X

O R '

,-+r-

~ r--'--

!--+

.

It ~

•

L -

L',-"-

~

R:

,

•

·

~

' - -

'--b-'--

~

,

•

~

' -

...

~OR

"~X

O R '

.

"""

" X

O R '

...

~OR

"~X

O R '

L',-r-

~ r--'--

,.;.. tt

~

L--


6-37

APPENDIX A

JUMPER INFORMATION

A.l INTRODUCTION

This appendix provides jumper information for the three controller boards, iSBC 546, iSBC 547 and iSBC 548. The controller boards leave the factory in a specific configuration called the default configuration. Table A-I lists all stake pin combinations (on which jumpers can be installed) for the iSBC 546 board. Table A-2 does the same for the iSBC 547 and iSBC 548 boards. A "Yes" in the

Default column of Table A-lor Table A-2 indicates the default jumpers installed by the factory. sections A-3 through A-6 provide more detailed information about the jumpers. Figures A-I, A-2 and

A-3 show the location of the stake pins on each of the boards

Jumper

Table A-l.

Default

EI - E2

E3 - E4

No

Yes

E5 - E6 No

Jumper Combinations iSBC

Function

Flag Byte Address Jumper

Dual Port RAM Address Jumper


546 Board

E7 - E8

E9 - EIO

No

No

Ell - E12 Yes

El3 - E14 Yes

El5 - E17 Yes

El9 - E24 No





80186 Clockout Jumper (Removed only during factory test)

Makes INTI* the MULTIBUS Interrupt when installed.

E25 - E24 Yes Makes INT2* the MULTIBUS Interrupt when installed.

A-l


Table A-l.

Jumper Default

Jumper Combinations iSBC

(continued)

Functl.on

546 Board

E27 - E24

E23 - E24

E28 - E29

E30 - E3l

No

No

No

No

Makes INT3* the MULTIBUS Interrupt when installed.

Makes INT4* the MULTIBUS Interrupt when when installed.

Dual Port RAM ;~ddress Jumper, installed to select mapping in the lower MByte, not installed to select mapping in the upper

MByte.

Selects Battery Back-up for clock/calendar circuit.

A-2

JUMPER INFORMATION

Table A-2.

Jumper Default

Jumper Combinations iSBC 547/548 Boards

Function

El - E2 No

E3 - E4

E5 - E6

E7 - E8

E9 - E10

Yes

No

Yes

Yes






Ell - E12 No

E13 - E14 Yes

E15 - E17 Yes

E18 - E2l

E19 - E24

No

No



80186 Clockout Jumper (Removed only during factory test)

Makes INT5* the MULTI BUS Interrupt when installed.


E20 - E2l No

E22 - E2l

E23 - E24

E25 - E24

No

No

No

Makes INTO* the MULTIBUS Interrupt when installed.




A-3

JUMPER INFORMATION

Table A-2. Jumper Combinations iSBC 547/548 Boards

(continued)

Jumper Default

E26 - E2l No

E27 - E24

E2S E29

Yes

No

Function



Dual Port RAM Address Jumper, installed to select mapping in the lower MByte, not installed to select mapping in the upper

MByte.

A-2 FLAG BYTE ADDRESS JUMPERS

I/O mapping of the flag byte is a jumper configurable option on the three controller boards. Table A-3 shows the jumpers and configurations available

Table A-3. Flag Byte AddrE~ss options and Jumpers

Flag Byte

Addresses

El - E2

Jumpers

E5 - E6 E9 - EIO

SAO (H)

SAl (H)

SA2(H)

SA3(H)

SA4(H)

SA5(H)

8A6(H)*

8A7(H)**

X

X

X

-

-

X

-

-

X

-

X

-

X

-

-

X

-

X

-

X

X

-

-

X

X =

=

* =

** =

Jumper lnstalled

Jumper not installed

Default flag byte address for iSBC 547 and iSBC 54S

Default flag byte address for iSBC 546

A-4


A.3 MULTIBUS INTERRUPT JUMPERS

The selection of which MULTI BUS Interrupt is used to interrupt the host is jumper selectable. A list of interrupts and there associated jumpers (the jumper installed selects its interrupt) is shown below:

Interru:et

INTO*

INTl*

INT2*

INT3*

INT4*

INT5*

INT6*

INT7*

Jum:eer

E20 - E21 Selectable on iSBC 547/548 only

E19 - E24 Selectable on all boards

E25 - E24 Default installation iSBC 546

Selectable on all boards

E27 - E24 Default installation iSBC 547 and iSBC 548

Selectable on all boards

E23 - E24 Selectable on all boards




A.4 MEMORY MAPPING JUMPERS

Memory mapping of the DRAM is a jumper configurable option on all three controller boards. The jumper combinations and the addresses they select are shown in Table A-4. The jumpers and addresses are identical on all boards.

A-5

JUMPER INFORMATION

Addresses

Table A-4. Memory Map Jumpers and Addresses

Jumpers

E2S - E29 E3 - E4 E7 - ES Ell - E12 E13 - E14

OSOOOO(H)

OSSOOO(H)

090000(H)

09S000(H)

OAOOOO(H)

OASOOO(H)

OBOOOO(H)

OBSOOO(H)

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

-

-

-

-

X

X

-

X

-

X

-

X

-

OCOOOO(H) X

-

-

-

-

-

-

-

-

X X

OCSOOO(H)

ODOOOO(H)

ODSOOO(H)

OEOOOO(H)

OESOOO(H)

OFOOOO(H)

OFSOOO(H)

X

X

X

X

X

X

X

X

-

-

-

-

X

X

X

-

-

X

-

X

-

FSOOOO(H)

-

-

-

-

-

-

-

-

X X X

FSSOOO(H)

F90000(H)*

F9S000(H)

FAOOOO(H)**

FASOOO(H)

FBOOOO(H)

FBSOOO(H)

X

X

X

X

X

X

X

X

X

-

-

-

-

X

X

-

-

X

-

X

-

FCOOOO(H)

-

-

-

-

-

-

-

-

-

-

-

-

-

X

-

-

-

-

X

FCSOOO(H)

FDOOOO(H)

X X

-

X

FDSOOO(H)

FEOOOO(H)

FESOOO(H)

-

X

X

-

X

FFOOOO(H)

FFSOOO (H)

-

. .

* Default address for the 1SBC 547 and 1SBC 54S boards.

** Default address for the iSBC 546 board.

X

=

Jumper installed.

= Jumper not installed.

X

-

X

-

X

-

-

X

X

-

-

X

-

-

X

X

X

-

-

-

X

X

-

X

-

X

-

X

-

X

-

X

A-6


NOTES

DEFAULT JUMPERS ARE:

E3-E4

E11-E12

E13-E14

E15-E17

E25-E24

E18 THROUGH E27 ARE

LOCATED ON THE BOARD.

STAKE PINS ARE INSTALLED

IN E19, E20, E24, E25 AND

E27 ONLY.

E1 : :

;!

E4

E5 • • • • E8

E9··:: E12

E10 E13 E14 o E30 o E31

E15

0

E17 o

E18 E19

E20 .: •• : . E25 o 0

E26 E27

P1

COMPONENT SIDE

E28

00

E29

P2

2343

Figure A-I. iSBC 546 Board Jumper Location

A-7


NOTE


E3-E4

E7-E8

E9-E10

E13-E14

E15-E17

E24-E27

E2 E3

E1

00 00

E4

E5

00 00

E8

E9

00 : :

E12

E10 E13 E14

E15

E17

0 o

COMPONENT SIDE

E28

00

E29

E18 E19

E20.: •• :. E25 o

0

E26 E27-

Figure A-2o iSBC 547 Board Jumper Location

A-a

2344


E1

;~ ;!

E4

E5 • • • • E8

E9 •• ::E12

E10 E13 E14

E15.

E17 •

NOTE


E3·E4

E7·E8

E9·E10

E13·E14

E15·E17

E24·E27

. .

E26 E27

P1

COMPONENT SIDE

E28 • • E29

P2

2340

Figure A-3. iSBC 548 Board Jumper Location

A-9

,

,

• ®

APPENDIX B

FIRMWARE

B.l INTRODUCTION

This appendix describes the user commands for the communication firmware supplied with the iSBC 546, iSBC 547 and iSBC 548 boards.

The firmware makes the boards into terminal controllers. The primary features of the firmware are listed and briefly summarized in Table B-l.

B.2 FIRMWARE OVERVIEW

NOTE

Throughout this appendix the word controllers indicates all three boards, iSBC 546, iSBC 547 and iSBC 548.

References to individual boards will include the model number.

The iSBC 546/547/548 firmware is released as a set of two Intel

EPROMs. The firmware makes the three boards into intelligent terminal controllers which can provide a MULTIBUS host CPU with either four (iSBC 546) or eight (iSBC 547 and iSBC 548) asynchronous serial channels.

MULTIBUS host CPUs view the iSBC 546/547/548 boards as slave peripheral controllers. The host and the controllers communicate via shared data structures and a message passing scheme implemented in the controllers on-board dual ported RAM. The host CPU signals the controller with the hardware I/O mapped flag byte mechanism on the controllers. The controllers signal the host CPU by requesting an interrupt on a jumper selectable MULTIBUS interrupt line.

B-1

FIRMWARE

Table B-1. iSBC

Feature

546/547/548 Firmware Features

Descr1ption

Asynchronous Serial

Channel Support

Block Data Transfer

Modem Control

Tandem Mode Support

The firmware supports the serial channels in asynchronous mode

Parameters such as baud rate, parity generation, parity checking and character length can be programmed independently for each channel.

The firmware relieves the

MULTI BUS host CPU of one character at a time interrupt processing.

The board accepts blocks of data for transmission and interrupts the processor only when the entire block is transmitted.

The firmware provides software control of the Data Terminal Ready

(DTR) line on all channels.

Transitions on the Carrier Detect

(CD) line are sensed and reported to the host CPU. Request to Send

(RTS) is continuously asserted.

In the default mode the transmitter and receiver are enabled independently of the state of the Clear to Send (CTS) and CD modem signals respectively.

A special command from the host instructs the controller boards to make CTS and CD gating signals for transmission and reception respectively.

RI and DSR signal transitions are reported to the host if the host so instructs, otherwise they are not reported.

The firmware provides a flow control facility to synchronize a remote source that may be transmitting so fast that the

B-2

FIRMWARE

Table B-1. iSBC 546/547/548 Firmware Features (continued)

Feature Description controller (iSBC 546/547/548) may exhaust its receive buffer space for that channel. The controller transmits an XOFF character when the number of characters in its receive buffer exceeds a threshold value and transmits an XON character when the buffer drains below its threshold.

Tandem Response Mode

Automatic Baud

Rate Recognition

In this mode the controllers will suspend all transmissions to a line if an XOFF was received from this line, and will resume only upon receipt of XON.

The firmware provides a capability to detect the baud rate of an agent connected to a serial channel. The remote agent must transmit a maximum of four ASCII

"U" CHARACTERS. The detected baud rate must be 19200, 9600, 4800,

2400, 1200, 600, 300, or 150.

Download and Execute

Capability

Power Up Confidence

The firmware provides a capability for the host CPU to load code anywhere in the lowest l28K Byte space of the controller

(except in the DYNAMIC STRUCTURE and QUEUE areas) and for the controller to start (with the exception of code) at any address in this address space.

The firmware executes a sequence of simple tests to establish that crucial components on the boards are functional.

B-3

FIRMWARE

B.2.1 FIRMWARE OPERATION

For the MULTI BUS host to input commands to a controller board in it's system it must do the following:

NOTE

The commands, messages queues and procedures discussed in this section are described in detail in section

B.3

1. Load the commands into the IN-QUEUE, starting at the first location in the queue or in the location immediately after the last location used.

2. Update the IN-QUEUE TA,IL in the Dynamic structure to show the current number of commands in the queue.

3. Send a flag interrupt (write 2 to the I/O address) to the controller board.

When the controller receives the int.errupt it scans the commands in the IN-QUEUE and executes them. The controller then updates the IN-

QUEUE-HEAD to indicate the number of commands it read and executed.

If several controller boards are sharing the same I/O address they all detect the same interrupt. When the IN-QUEUE is scanned,the controllers that find no new commands ignore the interrupt and return to their states before the interrupt.

When a controller board sends a message to the host it writes the message into the OUT-QUEUE and updates the OUT-QUEUE TAIL to indicate the number of messages in the OUT-QUEUE. After the updating the controller sends an interrupt to the host. When the host receives the interrupt it scans the OUT-QUEUE of all controller boards in the system sharing the interrupt line, and reads the available messages. The host then updates the OUT-QUEUE-

HEAD to indicate to the controller that it has read the messages.

The host then resets the interrupt line by writing a 4 to the I/O address of the controller board. All controller boards sharing the same I/O address reset their interrupts together. controller boards should share the same I/O addresses only if the share the same interrupt lines.

B-4

FIRMWARE

B.2.2 RECOMMENDATIONS FOR HIGH PERFORMANCE

To maximize controller board performance the following factors should be considered:

1. Lines that are not used should be disabled.

2. Use of special options (TANDEM Mode, SPECIAL CHAR

Mode and AUTO BAUD Mode, until the baud rate is found) slow board performance greatly. These options should not be used unless necessary.

3. The host should not clear it's buffer immediately after receipt of the INPUT AVAILABLE message. By not clearing the buffer immediately the number of interrupts from the controller board will be reduced. Both host and controller performance will be improved. No new INPUT AVAILABLE message for this line will be received until the CLEAR BUFFER command is sent. The data will be received by the controller but will not be reported until the CLEAR BUFFER command is received.

4. The CD line on the serial input should not be allowed to float. If the line is allowed to float false reports of CD DETECT and CD LOST will occur.

B-S

FIRMWARE

B.3 FUNCTIONAL ARCHITECTURE

A host CPU communicates with the controller boards via a shared data structures and a simple message passing scheme implemented in the dual port RAM on the controller boards. Inter-processor signalling is accomplished by using the hardware I/O mapped wakeup byte on the controllers and requesting an interrupt to the host on a MULTIBUS interrupt line. section B.3.1 describes the structures in dual po ted memory. A description of the messages exchanged by the host CPU and the controllers follows in section B.3.2. Section B.3 .. 3 details the implementation of the message passing scheme. section B.3.4 details the power-up confidence tests.

B.3.l STRUCTURES OF DUAL PORTED RAM sections B.3.1.1 through B.3.1.6 describe the layout of the data structures in dual port memory. The addresses are given in decimal notation and are relative to the start address which is mapped to the MULTIBUS. To the controllers 18000H is the start address.

Figure B-1 shows the memory layout used.

(Size)

13904 Transmit Buffers

(Offset)

18864

15520

3072

Receive Buffers

Queues

3344

272

128 Dynamic structures 144

128

16 static structures

Test Eng Boot Area

16 o

Figure B-1. Layout of Shared (Dual Port) Memory

B-6

FIRMWARE

B.3.l.l Test Engineering Boot Area

This area provides an interface for test programs to run on the board bypassing all normal firmware initialization. On rest, the firmware waits for a minimum of 250 ms for the 12 byte ASCII pattern RIGHTNOWGOTO to be loaded into the first 12 bytes of this area. If the pattern is loaded within 250 ms of reset the firmware executes a far jump to the address specified by a 32-bit 8086 style pointer (16-bit offset plus 16-bit selector) in the next four bytes. If the pattern is not loaded within the 250 ms the firmware continues with its normal initialization. Figure B-2 shows the layout of the Test Engineering Boot Area.

Before the 250 ms wait, the firmware performs no initialization other than setting the internal I/O in the on-board 80186.

(Size)

2

2

12

Jump Address (Selector)

Jump Address (Offset)

Magic Pattern (RIGHTNOWGOTO)

(Offset)

OE(H)

OC(H) o

Figure B-2. Test Engineering Boot Area Layout

B-7

FIRMWARE

B.3.1.2 static structures

Figure B-3 details the static structures area. This area is set by the firmware and must only be read, not modified by the host cpu.

After completing its initialization sequence on reset, the firmware sets the following values in this area:

Board Type

This value set to 02H indicates an iSBC 547 or 548 board. This value set to 03H indicates an iSBC 548 board. To use an iSBC 188/48 driver with this firmware requires that it be modified to recognize the new board types (iSBC 546/547/548.) version

This value indicates the version of the firmware.

The version Vxy is represented by the value (x

(x

*

16) + Y

*

16)

Completion Flag

This flag is set to OFFH when the initialization is completed. This will occur within 10 milliseconds if the board is functional.

Confidence Test Result (Read by the Host)

This value is set to OFFH if all confidence test succeed during initialization. otherwise the value indicates the test that failed.

B-8

FIRMWARE

(Size)

124

1

Reserved

(Offset)

20

Confidence Test Result 19

1

1

1

Completion Flag

Version

Board Type

18

17

16

NOTE

Reserved space should be set to 00 (H) .

Figure B-3. static structure Area Layout

B-9

FIRMWARE

B.3.l.3 Dynamic structures

The message passing scheme utilized for inter-processor communication is implemented as two circular queues in shared memory. One queue (the OUT queue) is used for messages going from the controllers to the host cPU. The other queue (the IN queue) is for messages going from the host CPU to the controllers.

The Dynamic structures area contains the variables that control the queueing mechanism. Figure B-4 details the layout of the Dynamic structures area, the semantics are described in section B.3.3.

(Size)

124

1

1

1

1

Reserved

OUT Queue Head

(Offset)

148

147

OUT Queue Tail

IN Queue Head

IN Queue Tail

146

145

144

Figure B-4.

NOTE

Reserved space should be set to 00 (H) .

Dynamic~ structure Layout

B.3.1.4 Queue

The Queue area contains the actual contents of the inter-processor message passing queues. It is divided into two equal regions as shown in Figure B.5. One region is the IN queue the other is the

OUT queue. section B.3.3 presents more detailed information on the

Queue area.

(Size)

1536

1536

OUT Queue

IN Queue

(Offset)

272 + 1536

272

Figure B-S. Layout of Queue Area

B-10

FIRMWARE

B.3.1.5 Receive Buffers

The Receive Buffers area is divided into eight receive buffers for the eight serial channels supported. Each buffer is 1940 bytes long. The buffer for line i starts at offset 3344 + (i X 1940) for o

< i <7.

B.3.1.6 Transmit Buffers

The Transmit Buffers area is a relatively unstructured area that may be used by the host CPU for allocating transmit buffers or for any other purpose. This area is managed by the host CPU and is not modified by the controllers. The Transmit buffer starts at an offset from the beginning of dual-ported memory 18864.

B.3.2 INTER-PROCESSOR MESSAGES

This section describes the message formats and protocol used for communication between the host CPU and the controllers. section

B.3.2.1 describes the messages sent by the host CPU to the controllers. section B.3.2.2 describes the messages sent by the controllers to the host CPU. section B.3.3 describes the implementation of the message passing scheme.

All messages have a fixed length of 16 bytes. Several messages have fields labelled "Reserved". It is recommended that these fields be set to zero for compatibility with future products.

The messages described, later identify serial channels by "line numbers". Line numbers 1 through 8 correspond to serial channels 1 through 8.

B.3.2.1 Host CPU to Controller Messages

These sections (B.3.2.1 through B.3.2.21) describes messages used by user level software running on the host CPU to communicate with the controller.

B-ll

FIRMWARE

Host CPU to iSBC Controller Messages

B.3.2.1.1 INITIALIZE. This message is used by the host CPU to initialize the controllers.

This message must be the first message sent to the board after reset unless a download and executE! function is to be performed,in which case the Download command must be the first message. If the

Initialize message is not the first message after a reset, it is ignored.

After the Initialize message is processed by the controller all lines are disabled. Each line has to be independently enabled with an Enable Line command before it can be used. The only line specific commands that can be directed to a disabled line are

Configure Line and Enable Line.

The controllers return an Initialize Complete message containing a bit map of the lines determined to be valid. This number will be 6 for the iSBC 546 board or 8 for the iSBC 547 and iSBC 548 boards.

Subsequent line specific commands must be directed to those lines noted as valid. The message format is shown in Figure B-6.

Message Format o

1

2

3

4

15

OlH

Reserved

Reserved

Reserve,d

Reserved

.

Reserve~

NOTE

Reserved space should be set to

00 (H) •

Response An Initialization Complete command is returned. No indication of MULTIMODULE present is returned to the driver.

Figure B-6. Initialize Message Format

B-12

FIRMWARE


B.3.2.1.2 ENABLE. This command is used by the host CPU to enable a serial channel. Once enabled, other commands can be directed to the channel.

The firmware enables the serial channel's receiver and transmitter only on this command. The RTS and DTR modem control signals are asserted and cleared respectively.

An Enable Line command, received when the line is already enabled is ignored by the controllers.

An Enable Command to the line printer causes a reset pulse to be issued to the line printer.

The Enable message format is shown in Figure B-7.

Message Format o

1

2

02H

Line Number

Reserved

Reserved

NOTE


00 (H) •

15

Line Number The serial channel being enabled

Response None

Figure B-7. Enable Message Format

B-13

FIRMWARE


B.3.2.1.3 DISABLE. This command is used to disable a serial channel. In the disabled state, the serial channel's receiver and transmitter are disabled and the DTR and RTS modem control lines are cleared.

It is recommended that this command be used when the line is quiescent, as it clears the state ()f the channel, with any pending output being cancelled and any received characters discarded.

Further, if a pending transmit operation is cancelled in this process no Transmit Complete message is returned.

The Disable message format is shown in Figure B-S.

Message Format o

1

2

03H

Line Number

Reserved

NOTE


00 (H) •

15 Reserve~d

Line Number The serial channel being enabled

Response None

Figure B-8. Disable Message Format

B-14

FIRMWARE


B.3.2.1.4 CONFIGURE. This command is used to set the parameters of a serial channel. It is recommended that this command be used when the line is in the quiescent state, as the command clears the channel, clearing any pending output and discarding any received characters. Further, if a pending transmit operation is cancelled in this process no Transmit Complete message is returned. This command is accepted when the line is disabled.

The Configure message format is shown in Figure B-9.

Message Format

0

1

04H

Line Number

2

3

4

5

Baud Rate

6

Link Parameters

Line Discipline

Mode

7

8

Tandem High water Mark

Tandem Low Water Mark

9 Signal Spl Char High Water Mark

10 XON Character

11

12

XOFF Character

Special Character

13 Special Character



.

F1gure B-9. Conf1gure Message Format

B-1S

FIRMWARE

A description of the format blocks shown in Figure B-9 is provided below:

Line Number

Baud Rate

Link

Parameters

The number of the serial channels being configured

The desired baud rate (both transmit and receive).

The actual baud rate obtained can be computed using the following:

Actual Baud Rate where count

= 153,600/(count + 2)

= trunc(153600/Requested Baud Rate) -2

The highest baud rate that can be specified is therefore 76,800.

A baud rate of zero has special significance. It instructs the controller to place the line in an automatic baud rate recognition mode. In this mode the controller attempts to sense the baud rate of an agent connected to the serial channel. The remote agent is required to transmit a maximum of four

ASCII "U" characters before its baud rate is determined. The remote agent must be set to transmit at one of the following standard baud rates -

19200, 9600, 4800, 2400, 1200, 600, 300, or 150.

Once the baud rate is sensed an Autobaud Complete message is returned to the host.

The.parameters to be used on the physical link:

Bit 1-0: Parity

00 - No parity

10 - Even parity

11 - Odd parity

Bit 3-2 Character length

00 - 6 bits/character

10 7 bits/character

11 8 bits/character

Bit 5-4 Number of stop Bits

00 - 1 stop Bit

01 - 1 1/2 stop Bits

10 - 2 stop bits

B-16

FIRMWARE

Line

Discipline

Mode

Bit 7-6 Reserved

If parity is enabled, an additional bit position , beyond those specified in the Character Length control is added to the transmitted data and expected in received data. The received parity bit is transferred to the CPU as part of the data unless a bits/character is selected. If a parity error is detected on input, the character is discarded.

In the 6 and 7 bits/character modes unused bit positions in transmit data are ignored. Unused bits in receive data are set to 1. If a framing error is detected on input, the character is returned as an a-bit null (OOH).

This block is assigned for future firmware implementations which support more complex functions.

This block is set to OIH for this application.

Used to set special modes:

Bit 0: Tandem Mode Enable o Tandem Mode Off

1 - Tandem Mode On

Bit 1: Signal Special Character Mode Enable o Signal Special Character Mode Off

1 - Signal Special Character Mode On

Bit 2: Tandem Response Mode o Tandem Response Mode Off

1 - Tandem Response Mode On

Bits 3 -7: Reserved

Tandem Mode provides a mechanism for the controllers to throttle a remote transmitter that could potentially cause the controller to run out of receive buffer space. On receiving a character, if the number of characters in the receive buffer is greater than or equal to the Tandem High water Mark an XOFF character is immediately transmitted on the

B-17

FIRMWARE

Tandem High water Mark

Tandem Low water Mark

Signal

Special

Character

High Water

Mark same channel, if an XOFF was transmitted. When the receive buffer drains to a value equal to the

Tandem Low Water Mark an XON character is transmitted to allow the remote source to continue transmitting.

When in the Tandem Response Mode the controllers will suspend transmission to a line if an XOFF signal was received from that line. Transmission will resume upon receipt of XON from that line.

The Signal on Special Character mode facilitates the the expeditious handling of interrupt characters. A common problem with buffered terminal controllers is that when there is SUbstantial type ahead, interrupt characters are buffered with the data on the controller. Consequently, the host does not see the interrupt character until all the data characters preceding it have been copied out of the controller.

The Signal on Character mode provides a solution to this problem. If a special character is received and there are more than some specified number of characters in the receive buffer a Special Character

Received message is sent to the host. The character is then stored in the receive buffer to mark the position of the interrupt in the input stream. The set of (up to four) special characters is user specified. The comparison of a received character to the characters making up this set is restricted to the data portion defined by the specified character length.

The high water mark used for Tandem mode is eight times this value.

The low water mark used for Tandem mode is eight times this value.

The high water mark used in the Signal Special

Character mode is eight times this value.

B-18

FIRMWARE

XON Character The XON character used in Tandem mode.

XOFF Character The XOFF character used in Tandem mode.

Special

Character

The characters forming the special character set in the Signal on Special Character mode.

Defaults Line parameters are set to the following defaults on reset:

9600 baud

7 bits/character

1 stop bit

Even parity

Tandem mode OFF

Signal on special Character mode OFF

Tandem Response mode OFF

Note that all parameters must be specified any time

Configure message is used.

Response An Autobaud Complete message is returned if automatic baud recognition is requested.

B-19

FIRMWARE


B.3.2.1.S TRANSMIT BUFFER. This message is used to initiate the transmission of a sequence of characters on a serial channel.

After the entire transmission completes, a Transmit Complete message is returned to the host. A transmit command is ignored if the line is transmitting a break or has not been enabled or has been placed in an automatic baud rate recognition mode by a previously issued configure command.

A transmission once initiated can be suspended with a Suspend

Transmit message and aborted with an Abort Transmit message.

A transmission to the clock/calendar line must be 11 data bytes as described in section B.3.2.S.

Figure B-10 shows the Transmit message.

B-20

FIRMWARE

Message Format o

1

05H

Line Number

2

3

Buffer Size

4

5

_Buffer Address-

-

6 Reserved

15

:

Reserved

NOTE


00 (H) .

Line Number The serial channel on which transmission is initiated.

Buffer Size The size of the transmit buffer in bytes.

Buffer Add. The 16-bit offset + 16384 (for product compatibility) at the beginning of the transmit buffer in the dual ported address space of the controllers. The host CPU fills the transmit buffer by writing into i t directly prior to issuing this command. In the 6 and 7 bits/character formats the data must appear in the least significant positions of an 8-bit byte. Unused bit positions are ignored.

Response A Transmit Complete message is returned after the ENTIRE sequence of bytes contained in the transmit buffer has been transmitted.

Figure B-10. Transmit Buffer Message Format

B-21

FIRMWARE


B.3.2.1.6 ABORT TRANSMIT. This message is used to abort a transmission already in progress.

This function is expected to be useful for operating system drivers to implement the purge transmit buffer operation commonly requested with an "0" character.

If a transmission is not in progress on the line, the command is ignored. otherwise, a Transmit Complete message is returned. If there are multiple outstanding transmit requests for the line, only the current (the one issued the earliest) is aborted.

Figure B-ll shows the Abort Transmit message format.

Message Format o

1

2

06H

Line Number

Reserved

151 Reserv~

NOTE


00 (H) .

Line Number The serial channel on which transmission is aborted.

Response A Transmit Complete message is returned if a transmission was indeed aborted.

Figure B-11. Abort Transmit Message Format

B-22

FIRMWARE


B.3.2.1.7 SUSPEND TRANSMIT. This command is used to suspend

(rather than abort) a transmission on the line.

If there is no transmission in progress on the particular serial channel, the command is ignored. If the transmission is already suspended, the command is again ignored. A suspended transmission can be resumed with a subsequent Resume Transmit command.

If there are multiple outstanding transmit requests for the line the line will remain suspended until a Resume Transmit command is issued.

Figure B-12 shows the Suspend Transmit message format.

Message Format o

1

2

07H

Line Number

Reserved

15

I

Reserved

NOTE


00 (H) •

Line Number The serial channel on which transmission is suspended.

Response None.

Figure B-12. Suspend Transmit Message Format

B-23

FIRMWARE


B.3.2.1.8 RESUME TRANSMIT. This command is used to resume a previously suspended transmission.

If there is no transmission in progress on the line or if the transmission is not suspended, the command is ignored.

Figure B-13 shows the Resume Transmit message format.

Message Format a

1

2

08H

Line Number

Reserved

15

I

Reserved

NOTE


00 (H) •

Line Number The serial channel on which transmission is resumed.

Response None.

Figure B-13. Resume Transmit Message Format

B-24

FIRMWARE


B.3.2.1.9 ASSERT DTR. This command is used to assert the Data

Terminal Ready (DTR) modem signal on a serial channel.

If the Carrier Detect modem signal is asserted for the line when this command is received, the controllers return a Carrier Detect message even though an OFF to ON transition was not sensed on the

Carrier Detect signal. Thus, the MULTIBUS host can maintain a state variable following the Carrier Detect modem signal by toggling the variable when subsequent Carrier Detect and Carrier Loss messages are received.

Figure B-14 shows the Assert DTR message format.

Message Format o

1

2

09H

Line Number

Reserved

15

I

Reserved

NOTE


00 (H) •

Line Number The serial channel on which DTR is asserted.

Response A Carrier Detect message is returned if the

Carrier Detect is asserted when the command is received.

Figure B-14. Assert DTR Message Format

B-25

FIRMWARE


B.3.2.1.10 SET CTS AND CD GATES. This command causes the controller's specified line not to transmit unless CTS is active and not to receive unless CD is active.

Figure B-15 shows the command format.

Message Format

0

1

2

OAH

Line Number

Reserved

NOTE


00 (H) .

Line Number

15 Reserved

The serial channel on which the CTS and CD gates are set.

Figure B-15. Set CTS and CD Gates Message Format

B-26

FIRMWARE


B.3.2.1.11 CLEAR CTS AND CD GATES. This command causes the controllers to transmit and receive on the specified line regardless of CTS and CD. This is the default condition after reset.


Message Format

0

1

2

OBH

Line Number

Reserved

NOTE


00 (H) .

Line Number

15 Reserved

The serial channel on which the CTS and CD gates are cleared.

Figure B-16. Clear CTS and CD Gates Message Format

B-27

FIRMWARE


B.3.2.1.12 SET DSR REPORT. This command causes the controllers to report changes of the DSR signal on the specified line.


Message Format

Line Number o

1

2

15

OCH

Line Number

Reserved

Reserve~

NOTE


00 (H) •

The serial channel on which DSR Report is set.

Figure B-17. Set DSR Report Message Format

B-28

FIRMWARE


B.3.2.1.13 CLEAR DSR REPORT. This command cancels the previous request to report DSR changes on the specified line. This is the default condition after reset.


Message Format a

1

2 aDH

Line Number

Reserved

NOTE

Reserved space should be set to aa(H) .

Line Number

15 Reserved

The serial channel on which DSR Report is cleared.

Figure B-18. Clear DSR Report Message Format

B-29

FIRMWARE


B.3.2.1.14 SET RI REPORT. This command causes the controllers to report changes of the RI signal on the specified line.


Message Format

0

1

2

15

OEH

Line Number

Reserved

:

Reserved

NOTE


00 (H) •

Line Number The serial channel on which RI Report is set.

Figure B-19. Set RI Report Message Format

B-30

FIRMWARE


B.3.2.1.1S CLEAR RI REPORT. This command cancels the previous request to report RI changes for the specified line.

Figure Figure B-20 shows the command format.

Message Format

0

1

2

OFH

Line Number

Reserved

NOTE


00 (H) •

Line Number

15 Reserved

The serial channel on which RI Report is cleared.

Figure B-20. Clear RI Report Message Format

B-31

FIRMWARE


B.3.2.1.16 CLEAR DTR. This command is used to clear the Data

Terminal ready modem signal on a serial channel.

Figure B-2l shows the Clear DTR message format.

Message Format o

1

2 lOH

Line Number

Reserved

15

I

Reserved

NOTE

Reserved space should bE:! set to

00 (H) •

Line Number The serial channel on which DTR is cleared .

Response None

Figure B-21. Clear DTR Message Format

B-32

FIRMWARE


B.3.2.1.17 SET BREAK. This command is used to force the transmission of continuous zeros (i.e. hold the line in a continuous spacing condition) on a serial channel. This command is ignored if a transmission is in progress on the line. Once a set

Break command is issued, it must be followed by a Clear Break command before any transmit Buffer commands are issued on the particular line.

Figure B-22 shows the set Break message format.

Message Format o

1

2 llH

Line Number

Reserved

15

I

Reserved

NOTE


00 (H) •

Line Number

Response

The serial channel on which break is transmitted.

None

Figure B-22. Set Break Message Format

B-33

FIRMWARE


B.3.2.1.18 CLEAR BREAK. This command is used to clear a transmit break condition on a line caused by a previous Send Break command.

Figure B-23 shows the Clear Break message format.

Message Format o

1

2 l2H

Line Number

Reserved

15

I

Reserved

NOTE


00 (H) •

Line Number

Response

The serial channel on which break is cleared.

None

Figure B-23. Clear Break Message Format

B-34

FIRMWARE

This page intentionally left blank

FIRMWA.RE


B.3.2.1.19 DOWNLOA.D. This command is used to download code into any location in the controllers address space. This allows the flexibility to load code into RAM not visible to the MULTIBUS. The

Execute command can then be used to transfer control of the loaded code.

This command (or sequence of commands) is only allowed directly after a reset. After the download completes a Download Complete message is returned to the MULTIBUS host. since the Download command and subsequent Execute command use the normal message interface, care must be taken not to overwrite memory used to implement the queues: or the lower 16K of local memory where the firmware maintains: its data structures. Further, copying to nonexistent memory may hang up the processor.

The Test program boot mechanism may present an alternative to the use of this command. with the Test program boot mechanism the message to be dowloaded must be downloaded within 250 ms after a reset. Using the Download message still requires a reset but there is no time limitation.

Figure B-24 shows the Download command format.

B-36

FIRMWARE

Message Format

9

10

6

7

8 o

1 l3H

Reserved

2

3 r--

Dest Ptr (Offset) -_

4

5 r-

Dest Ptr (Selector) -:.

Source Offset-___

Size-

Reserved

NOTE


00 (H) .

15

I

Reserved

Dest Ptr The 32-bit 8086 style pointer (offset + selector) to the location in the address space of the controller where the code is to be loaded.

Source Offset The l6-bit offset in the controllers dual-ported

RAM from where the controller is to copy the code to the destination address plus 16384. The code must be loaded into this area prior to issuing this command.

Size

Response

The size in bytes of the code that is copied from dual-port RAM to the destination address.

A Down-load Complete message is returned to the host when the operation completes.

Figure B-24. Download Message Format

B-37

FIRMWARE


B.3.2.1.20 EXECUTE. This command is used to transfer control to previously down-loaded code. The Execute command must be preceded by one or more Download commands.

Figure B-25 shows the Execute command message format.

Message Format o

1 l4H

Reserved

2

3

start Addr (Offset)-

-

4

5 l'tart Addr (Selector) -:.

6 Reserved

NOTE


00 (H) .

15

_ _ _

R_e_s_e_r_~_'_e_d

_ _ _

~ start Address The 32-bit 8086 style (offset + selector) start address of the down-loaded code. The firmware executes a far jump to this address.

Response None.

Figure B-25. Execute Command Message Format

B-38

FIRMWARE


B.3.2.1.21 CLEAR RECEIVE BUFFER. This command is used to respond to an Input Available message from the controllers. The Input

Available message contains an address and a count describing a buffer where received data characters have been accumulated. The

Clear Receive Buffer message is used to inform the controller of the number of characters the MULTI BUS host CPU has copied out of the receive buffer so that the controller can release the corresponding buffer space.

The Clear Receive Buffer message also serves an important synchronization function. The controllers ensure that at most, one

Input Available message per line is pending. That is, it issues an

Input Available message on a particular line only after any previously issued Input Available message has been acknowledged with a clear Receive Buffer message. In this manner, the host CPU can exercise flow control by delaying Clear Receive Buffer messages.

A Clear Receive Buffer message that is received when there is no outstanding Input Available message is ignored by the controllers.

This command has a special use in the clock/calendar and line printer interfaces (on the iSBC 546 board). When issued to these lines with count zero it is a request for input.

Figure B-26 shows the Clear Receive Buffer message format.

B-39

FIRMWARE

Message Format

2

3

4 o

I

ISH

Line Number

Count

Reserved

NOTE


00 (H) •

15

I

Reserved

Line Number

Count

The serial channel from which characters have been cleared.

The number of characters copied out of the receive buffer. The count can be O. The count must not exceed the count specified in the corresponding Input Available message.

Response None.

This message clears the board to send an Input

Available message immediately, if the receive buffer is not empty.

Figure B-26. Clear Receive Buffer Command Message Format

B-40

FIRMWARE

B.3.2.2 controller To Host CPU Messages sections B.3.2.2.l through B.3.2.2.l2 describe messages sent between the controllers and the MULTIBUS host cpu.

B.3.2.2.1 TRANSMIT COMPLETE. This message is sent by the controllers to indicate the completion of a Transmit Buffer command previously issued by the host cpu.

The message returns the actual number of characters transmitted. This message also clears the host cpu to request another Transmit Buffer operation.

Table B-27 shows the Transmit Complete message format.

Message Format

2

3

4 o

1

OlH

Line Number

Actual Count

Reserved

NOTE


00 (H) •

Line Number

Actual Count

151

~

_______

R e_s_e_r_v_e_d ______

~

The serial channel on which a previously issued

Transmit Buffer command has completed.

The actual number of characters transmitted. Thj may be different from the number of characters specified in the Transmit Buffer request if the transmit operation was cancelled by the Abort

Transmit command.

None Response

Figure B-27. Transmit Complete Message Format

B-41

FIRMWARE iSBC Controller to Host CPU Messages

B.3.2.2.2 INPUT AVAILABLE. This message is sent by the controllers to inform the host CPU of pending received characters.

The host CPU must copy the received data into its own buffers and then signal the controllers to release their buffer space by sending it a Clear Receive Buffer message.

The controllers will not issue any further Input Available messages for the channel until the host CPU responds with a Clear Receive

Buffer message. Thus some measure of flow control can be exercised by the host CPU.

Note, the controllers discard characters received with parity errors and replaces characters received with frame errors with eight bit nulls (DOH). The received parity bit is transferred to the CPU unless eight bits/character is selected. In the 6 and 7 bits/character formats unused bit positions are set to 1.

Figure B-28 shows the Input Available message format.

B-42

FIRMWARE

Message Format

Line Number

Offset

Count

Response

4

5

2

3

6 o

1

02H

Line Number

Count

Offset

Reserved

NOTE


00 (H) •

151

~

__

~

The serial channel on which input has been received.

The 16-bit offset from the base of the controller memory to the beginning of the area where the received characters have been accumulated. The firmware adds 16384 bytes to maintain compatibility with other Intel products.

The number of characters available starting at the above offset. Note that the receive buffer for each line is organized as a circular queue and the host CPU must account for any wrap-around implied by the offset and count.

The host CPU must respond with a Clear Receive

Buffer Message.

Figure B-28. Input Available Message Format

B-43


B.3.2.2.3 DOWNLOAD COMPLETE. This message is sent by the controllers to inform the host CPU of the completion of a previously issued Download command. This message also clears the host CPU to issue another Download command or an Execute command.

Figure B-29 shows the Download Complete message format.

Message Format

Response o

1

03H

Reserved

15

I

Reserved

None

NOTE


00 (H) •

Figure B-29. Download Complete Message Format

B-44


B.3.2.2.4 CARRIER DETECT. The controllers send the host CPU this message when an OFF to ON transition is detected on the Carrier

Detect Modem line.

If the Carrier Detect modem signal is asserted for the line when the Assert DTR command is received, the controllers return a

Carrier Detect message even though an OFF to ON transition was not sensed on the Carrier Detect signal. Thus the host can maintain a state variable following the Carrier detect modem signal by toggling the variable when subsequent Carrier Detect and Carrier

Loss messages are received.

Figure B-30 shows the Carrier Detect message format.

Message Format

Line Number

Response o

1

2

04H

Line Number

Reserved

NOTE


00 (H) .

151

~

____

The serial channel on which the carrier was detected.

None

Figure B-30. Carrier Detect Message Format

B-45


B.3.2.2.S CARRIER LOSS. The controllers send the host CPU this message when an ON to OFF transition is detected on the Carrier

Detect Modem line.

Figure B-31 shows the Carrier Loss message format.

Message Format o

1

2

05H

Line Number

Reserved

NOTE


00 (H) •

Line Number

Hesponse

1511-____

The serial channel on which the carrier was lost.

None

Figure B-3l. Carrier Loss Message Format

B-46


B.3.2.2.6 INITIALIZATION RESPONSES. The controllers return this message in response to an Initialize command.

It returns a bit map of the active lines on the board. Only these lines may be used in subsequent line specific commands.

Figure B-32 shows the Initialization Responses message format.

Message Format

3

4 o

1

2

06H

Reserved

Active Lines

Reserved

Reserved

NOTE


00 (H) .

15 Reserved

Active Lines A bit map representing the lines that may be used in subsequent line specific commands.

Bit i is 1 if and only if line i is active for o < i < 7.

Response None

Figure B-32. Initialization Responses Message Format

B-47


B.3.2.2.7 AUTOBAUD COMPLETE. The Controllers return this message after they have completed a baud rate scan initiated on a line by a previous Configure Line command. The host is allowed to issue line specific commands to the line after it receives this message.

Figure B-33 shows the Autobaud Complete message format.

Message Format

Line Number

Baud Rate

Response o

1

2

3

4

07H

Line Number

Baud Rate

Reserved

15

I

Reserved

NOTE


00 (H) .

The serial channel on which the baud rate has been recognized.

The baud rate of the serial ch.annel.

None.

Figure B-33. Autobaud complete Message Format

B-48


B.3.2.2.8 SPECIAL CHARACTER RECEIVED. The controllers return this message in Signal Special Character Mode when a special character is received, and the number of characters in the receive buffer of the line exceeds the Signal Special Character high water mark.

Figure 5-34 shows the Special Character Received message.

Message Format

2

3 o

1

OSH

Line Number

Special Character

Reserved

15

I

Reserved

NOTE


00 (H) •

Line Number The serial channel on which the special character is received.

Special Character The special character received.

Response None

Figure B-34. special Character Received Message Format

B-49


B.3.2.2.9 DSR DETECTED. This message reports DSR going active on the specified line. The line is in DSR Report Mode.

Message Format

Line Number

0

1

2

15

09H

Line Number

Reserved

Reserved

NOTE


00 (H) .

The serial channel on which DSR becomes active.

Figure B-35. DSR Detected Message Format

B-50


B.3.2.2.10 DSR LOST. This message reports DSR going inactive on the specified line. The line is in DSR Report Mode.

Message Format

0

1

2

OAH

Line Number

Reserved

NOTE


00 (H) .

Line Number

15 Reserved

The serial channel on which DSR becomes inactive.

Figure B-36. DSR Lost Message Format

B-Sl


B.3.2.2.11 RI DETECT. This message reports RI going active on the specified line.

Message Format

0

1

2

OBH

Line Number

Reserved

NOTE


00 (H) .

Line Number

15 Reserved

The serial channel on which RI becomes active.

Figure B-37. RI Detected Message Format

B-52


B.3.2.2.12 RI LOST. This message reports RI going inactive on the specified line.

Message Format

0

1

2

OCH

Line Number

Reserved

00

NOTE


(H) .

Line Number

15 Reserved

The serial channel on which RI becomes inactive.

Figure B-38. RI Lost Message Format

B-53

FIRMWARE

B.3.2.3 Sample Host CPU to Controller Interaction

This section presents some typical message interchanges between a host CPU and a controller.

Example 1

This example shows a message interchange that typifies normal operation on a single line.

HOST CPU CONTROLLERS

«<RESET»>

1. INITIALIZE

2.

3. CONFIGURE

4. ENABLE LINE

5. ASSERT DTR

- - - -

>

<-

- - - -

- - - -

>

- - - -

>

- - - -

>

INITIALIZATION RESPONSE

«<Modern establishes carrier»>

6. <-

- - - -

CARRIER DETECT

«<Host copies data into transmit buffer»>

7. TRANSMIT BUFFER

- - - -

>

«<Actual Transmission»>

8.

9.

<-

- - -

TRANSMIT COMPLETE

«<Data Received over the Serial Link»>

<-

- - -

INPUT AVAILABLE

«<CPU reads Received Data»>

10. CLEAR RECV BUFFER

- - - -

>

«<Carrier Drops»>

11.

12. DISABLE

<-

- - - -

- - - -

>

CARRIER LOSS

B-54

FIRMWARE

Example 2

This example illustrates a typical message exchange for a download and execute application

HOST CPU CONTROLLERS

«<RESET»> l .

2.

DOWNLOAD

3. DOWNLOAD

4.

5. EXECUTE

>

<DOWNLOAD COMPLETE

>

<DOWNLOAD COMPLETE

>

«<Down loaded Code begins to execute»>

B.3.2.4 Line Printer

The iSBC 546 provides a line printer controller interface. The interface, between the line printer and the iSBC 546 is Centronics compatible. To use the line printer controller, the same protocol is used as for an RS232C serial channel except the only input possible from this line is a byte of printer status. the line printer corresponds to iSBC 546 line #5 (Channel 4 when counting from 0 to 7).

To read the status of the line printer a Clear Receive Buffer command (with count = 0) must be sent to line #5. A Receive Buffer command is sent from the iSBC 546 board to the CPU host. The command consists of a single byte containing the status shown below:

Bit 4 Line Printer Busy. Logical 1 indicates line printer is busy, logical 0 indicates it is not busy.

Bit 5

Bit 6

Line Printer out of Paper. Logical 1 indicates paper is out, logical 0 indicates there is paper.

Select. Logical 1 indicates line printer is selected, logical 0 indicates the printer is not selected.

B-55

FIRMWARE

Bit 7 Line Printer Fault Detected. Logical 1 indicates normal line printer operation. Logical 0 indicates a fault occurred in the line printer.

B.3.2.5 Clock Generator

The iSBC 546 provides a hardware clock and calendar with battery back-up. The clock/calendar is referred to as simply the clock, and the time/data are referred to as simply the time in this discussion. The clock corresponds to iSBC 546 line #6 (channel 5 when counting from 0 to 7).

The clock uses the Transmit and receive Buffers to set and read the time. To set the time a Transmit command is issued with 11 bytes of data in the Transmit Buffer. To read the time a Clear

Receive Buffer command is issued, with 0 byte count, and in response 11 bytes of data are received in the Receive Buffer.

The data is always communicated in Binary-Encoded Decimal (BCD) format. For both setting and reading, the 11 bytes of data have the following structures:

Byte Meaning Values

9

10

11

5

6

1

2

3

4

7

8

Thousandths of Seconds

Hundredths and Tenths of Seconds

Seconds

Minutes

Hours

Day of Week

Day of Month

Month

Reserved (Set to Zero)

Year

Month (Repeated)

B-56 xO

00 99

0 - 59

0 59

0 - 23

1 - 7

1 31

1 - 12 o -

99

1 12

FIRMWARE

B.3.3 PHYSICAL MESSAGE PASSING

This section describes the physical message passing scheme utilized for communication between the host CPU and the controllers.

B.3.3.1 Data Structures

Message passing is implemented using a pair of circular queues of message-sized (16 bytes) buffers. The circular queues are themselves implemented as 96 element arrays of 16 byte long buffers with head and tail pointers into these arrays.

The arrays are located in dual port memory. The IN Queue area refers to the array used for messages to the controllers and the

OUT queue area refers to the corresponding array used for messages from the controller.

To be definitive consider the following array declarations made for the two queue areas and the control variables.

If In_ queue is non-empty then

In_queue/In_ queue_head/ is the next queue element to be processed by the controller.

If In_queue is non-full then

In queue/In queue tail/ is the next free slot in In_queue -

If out_queue is non-empty then

Out-queue/Out-queue-head/ is the next queue element to be processed by the host CPU

If Out_queue is non-full then

Out queue/Out queue tail/ is the next free slot in Out_queue -

In_queue is empty if and only if in_queue_head = In_queue_tail

In_queue is full if and only if

In_queue tail + 1 = In_queue_head

(modulo 96)

B-S7

FIRMWARE out_queue is empty if and only if

Out_queue_head = Out_queue_tail out_queue is full if and only if out queue tail

(modulo 96)

+ 1 = out_queue_head

B.3.3.2 operations

To ensure correct operation the host CPU must use the following procedures to add elements to the In queue (i.e. to send messages to the controllers) and to remove elements from the out_queue (i.e. to receive messages from the controller).

In the following procedures the host CPU is allowed to modify

In_Clueue_tail and Out_queue_head but is allowed only to read

In_queue_head and out_queue_tail.

Send Message wait until In queue is non-full;

Copy message Into In queue/In queue tail/;

Increment In queue tail by 1 (modulo 96) signal the controller (write 02H to the flag byte I/O port)

Receive Message

Clear the interrupt request (write 04H to the flag byte I/O port) ; while Out queue is non-empty

Copy Out queue/Out queue head/ into local message buffer; - -

Increment Out_queue_head by 1 (modulo 96);

Process message; endwhile;

B-58

FIRMWARE

B.3.4 POWER-UP CONFIDENCE CHECKS

Upon power-up the controller firmware performs some confidence tests to verify the operation of the major on-board chips. When all tests are successfully completed the value FFH is stored in the

Confidence Test Result Byte of the dual port RAM (offset = 19). If any test fails, the 80186 processor is halted and the Result byte contains an indication of the failed test.

Note that during the power-up tests, the processor runs with interrupts disabled.

Table B-2 shows the Confidence Test Result Codes and the corresponding tests performed. A description of each appears in the following sections.

Result

Table B-2. Confidence Test Result Codes

Test Part Board Location

00

10

11

30

50

51

52

53

60

EPROM Checksum Test

DRAM March Test

DRAM Ripple Test

PIT Countdown Test

SCC Register Test

SCC Register Test

SCC Register Test*

SCC Register Test*

Clock/calendar**

* lSBC 547 and 548 only

** iSBC 546 only

-

-

-

80186

82530

82530

82530

82530

58167

-

-

-

U30

U24

U15

U10

U1

U1

B.3.4.1 EPROM Checksum Test

The Controller firmware resides in EPROMs. The contents of the

EPROMs are static, so the unsigned byte-wise sum of all EPROM addresses is known. This sum can be anywhere between 0 and 255 times the address length of the EPROM. The sum is stored at the lowest address of the EPROM and is called a checksum.

The checksum is stored as a DWORD under the PL/M Language data storage conventions. This means that the most significant bits are

B-59

FIRMWARE in higher addresses than the less significant bits. The highest byte of the checksum is defined as always masked to zeros. This is because the EPROM size is never more than 64 KBytes.

Figure B-29 shows the format of the Checksum Test. Note that the checksum is defined not to include the sum of the EPROM addresses in which the checksum itself is stored.

(Offset) (Size)

11

~

_________

O_8_H __________

~1

FFFFFH

1 Test Eng Zero Byte

3 Checksum

EPROM Base + 3

EPROM Base

Figure B-39. EPROM Checksum Test

B-60

FIRMWARE

The Checksum Test is performed using the following procedure:

Checksum = Oi for EPROM address

Checksum

=

EPROM Base + 4 to FFFFFH do

= Checksum + unsigned contents of

(EPROM address)i end fori

Checksum = Checksum and FFFFFFHi if Checksum is not equal to Checksum at EPROM base then fail test

B.3.4.2 DRAM TESTS

The dynamic RAM is tested for integrity by writing a pattern to an address and then reading the pattern back for comparison. Patterns are chosen to test both ON and Off states. The procedure is repeated for all of the on-board non-dual ported RAM. for RAM address = 0 to 17FFEH do for each Pattern do write Pattern to RAM address read Check Pattern from RAM addressi if Check Pattern is not equal to written

Pattern then fail testi end i f i end fori end fori pass_test;

B.3.4.2.1 MARCH TEST. The March Test uses two patterns per address tested. The first is OlOlOlOlOlOlOlOlB and the second is its opposite 1010101010101010B.

B.3.4.2.2 RIPPLE TEST. The Ripple Test uses sixteen patterns per address tested. The first is OOOOOOOOOOOOOOOIB and subsequent patterns are generated by shifting this pattern left by one bit at a time until 1000000000000000B is reached.

B-61

FIRMWARE

B.3.4.3 PIT Countdown Test

The PIT Countdown Test verifies the operation of the Programmable

Interval timers by counting the counters down and generating an interrupt.

The following procedure is used for each of the three timers in the

80186. program 80186 PIC; set IMR to mask all but level 0; program PIT program PIT modes as:

Priority 0;

Software triggered strobe (CONT =0, ALT = 0) load count time (Max Count Register A) as 0064H; loop up to 100 times read PIC POLL Register; if most significant bit is ON and highest_level = 0 then pass test; end if; end loop; fail test:

B.3.4.4 sec Register Test

The SCC Register Test verifies the ability of the host to access the Time Constant Registers of the Serial Communications

Controllers. The following procedure is used: loop twice using March Patterns write March Pattern to Time Constant Registers

(WR12 and WR13) ; read Check Pattern back (RR12 and RR13) ; if Check Pattern is not equal to Written Pattern then end if; fail test; end loop; pass_test;

B-62

FIRMWARE

B.3.4.S Clock/Calendar Test

The clock/calendar test verifies the ability of the 58167 component to be set and to keep time. The following procedure is used: set timer to interrupt every 1.5 msec

On the first interrupt read and store time;

On the second interrupt set time to 12:31:7:23:59:99:90;

On the third interrupt read the time, it should be l:l:l:O:O:O:O:xx else test fails;

On the fourth, do nothing;

On the fifth interrupt set the time to the value stored plus

6 msec;

B-63

Intel iSBC 546, iSBC 547, iSBC 548 Hardware Reference Manual

iSBC®

HIGH PERFORMANCE

TERMINAL CONTROLLERS

HARDWARE REFERENCE MANUAL

PREFACE

CHAPTER 1

GENERAL INFORMATION

BOARD OPERATION

,.---------"'-=~·I

L-----,JJ

INSTALLATION

PROGRAMMING CONSIDERATIONS

CHAPTER 5

INTERFACING INFORMATION

SERVICE ASSISTANCE INiFORMATION

:,; : "--;,':----."."" ;" "_"." __ ."'

nH:

li"

"J

-f

~"

~"

l-~:~f~·'-----l--;---------J-..W

-If

~"

~"

~"

JUMPER INFORMATION

APPENDIX B

FIRMWARE

Reserve~

Reserve~

151

_______

151

____

11

_________

Related manuals

Intel

iSBC 86/30

Intel

iSBC 432/100

Intel

iSBC 86/12

Intel

iSBC 80/30

Intel

9800758-02