STMicroelectronics Evaluation boards for low-cost SD TV decoder using the STi5189/STi5197 SoC Datasheet

STi5197-MBoard, STi5189/97-MB

Evaluation boards for low-cost SD TV decoder using the STi5189/STi5197 SoC

Features

■ Interfaces supporting digital audio and video applications, including:

– HDMI output with CEC support, I

2

C, dual smartcards, infrared receiver, one NIM

– dual RS232 (UART)

– MII/RMII Ethernet and single USB

– S/PDIF input/output, PCM input

– SD video

– on-board 32-Mbyte NOR Flash memory

– on-board 4-Gbyte NAND Flash

– 3 serial Flash devices

– DiSEqC 2.0

TM interfaces

– DVB-CI, STEM

– LMI, DDR SDRAM 64 Mbytes

– BTSC RF modulator

(a) a.

On MB672 only.

June 2009 8149405 Rev D

■

– ATAPI

– cable and/or satellite RF tuners

Diagnostic support:

– LVDS JTAG

– TTL JTAG

Description

The STi5197-MBoard and STi5189/97-MB provide an STB, iDTV and DVD platform for low-cost, SD TV applications, using the

STi5189/STi5197 SoC.

■

■

■

These boards are used for:

SoC validation

SoC demonstration software application development

1/160 www.st.com

1

Contents

Contents

1

2

3

4


Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1

Target audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

Equipment and software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2

Electrostatic discharge (ESD) protection . . . . . . . . . . . . . . . . . . . . . . . . . 10

Product configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1

System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2

Board assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3

Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MB676/MB704 processor board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.4

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5

Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.6

Memory interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.6.1

4.6.2

4.6.3

Local memory interface (LMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Flexible memory interface (FMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SPI Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.7

Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.7.1

4.7.2

4.7.3

4.7.4

4.7.5

USB2.0 host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

HDMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Tuners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

I

2

C interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.8

PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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5

6

Contents

MB762 SD generic peripheral board . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2

Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.4

Dual serial RS232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.5

Infrared receiver and transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.6

Serial I

2

C buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.7

Smartcard slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.8

Flexible memory interface (FMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.8.1

5.8.2

STEM FMI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

FMI support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.9

DVB-CI and transport stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.10

Programming EPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.11

Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.11.1

Analog audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.11.2

SPDIFout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.11.3

PCMin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.11.4

PCMout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.12

Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

MB829 SD modular validation peripheral board . . . . . . . . . . . . . . . . . 28

6.1

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2

Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.4

Dual serial RS232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.5

Infrared receiver and transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.6

Serial I

2

C buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.7

Smartcard slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.8

Flexible memory interface (FMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.8.1

6.8.2

STEM FMI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

FMI support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.9

DVB-CI and transport stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.10

Programming EPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8149405 3/160

Contents STi5197-MBoard, STi5189/97-MB

6.11

Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.11.1

Analog audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.11.2

SPDIFout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.11.3

PCMin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.11.4

PCMout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.12

Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Appendix A MB676/MB704 processor board connectors . . . . . . . . . . . . . . . . . . 38

A.1

Connector layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

A.1.1

Bottom assembly connector layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

A.2

Panel layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

A.3

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

A.3.1

A.3.2

A.3.3

A.3.4

A.3.5

A.3.6

A.3.7

ATX power connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

I

2

C header connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power ground isolators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

External USB physical interface connector. . . . . . . . . . . . . . . . . . . . . . . 45

Debug connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Board to board connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Single USB2.0 type A connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

A.3.8

A.3.9

External clock connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

MII Ethernet connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

A.3.10

HDMI connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

A.3.11

Satellite tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

A.3.12

Digital cable tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Appendix B MB762 SD generic peripheral board connectors . . . . . . . . . . . . . . 56

B.1

Connector layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

B.2

Front and rear panel layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

B.3

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

B.3.1

B.3.2

B.3.3

B.3.4

B.3.5

B.3.6

B.3.7

DC power socket CN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

LVDS debug type G connector CN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Video and audio phono connectors CN3 to CN6, CN8 and CN9 . . . . . . 61

Dual SCART connectors CN7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

NIM connector CN10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

HDD power connector CN11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

PCM audio output debug connector CN12 . . . . . . . . . . . . . . . . . . . . . . . 65

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STi5197-MBoard, STi5189/97-MB Contents

B.3.8

B.3.9

Transport stream data connector CN14 . . . . . . . . . . . . . . . . . . . . . . . . . 66

DVO connector CN15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

B.3.10

JTAG debug (ByteBlaster) connector CN16 . . . . . . . . . . . . . . . . . . . . . . 68

B.3.11

PCM audio input connector CN17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

B.3.12

Smartcard header data connectors CN18/CN19 . . . . . . . . . . . . . . . . . . 69

B.3.13

P6960 series high-density logic probe land pattern CN20 . . . . . . . . . . . 69

B.3.14

ATAPI connector CN21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

B.3.15

DVB-CI connector CN22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

B.3.16

+3V3 I2C blaster connector CN23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

B.3.17

Ethernet MII data connector CN24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

B.3.18

Smartcard sockets CN25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

B.3.19

STEM EMI CN26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

B.3.20

RJ45 Ethernet connector CN27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

B.3.21

Dual RS232 interface CN28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

B.3.22

EMI and PIO peripheral to processor board connectors CN29/CN30 . . 80

B.3.23

RF modulator connector IC11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Appendix C MB829 SD modular validation peripheral board connectors. . . . . 85

C.1

Connector layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

C.2

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

C.2.1

C.2.2

C.2.3

C.2.4

C.2.5

C.2.6

C.2.7

C.2.8

Video and audio phono connectors CN1 to CN9 . . . . . . . . . . . . . . . . . . 87

LVDS debug type G connector CN10 . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

JTAG debug (ByteBlaster) connector CN11 . . . . . . . . . . . . . . . . . . . . . . 89

Dual RS232 interface CN12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

PCM audio output debug connector CN13 . . . . . . . . . . . . . . . . . . . . . . . 90

DVO connector CN14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

PCM audio input connector CN15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

EMI and PIO peripheral to processor board connectors CN16/CN23 . . 92

C.2.9

Transport stream connectors CN24/CN25 . . . . . . . . . . . . . . . . . . . . . . . 97

C.2.10

NIM connector CN26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

C.2.11

ATX power connector CN27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

C.2.12

Smartcard header data connectors CN28/CN29 . . . . . . . . . . . . . . . . . 101

C.2.13

Smartcard sockets CN30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

C.2.14

ATAPI connector CN31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

C.2.15

STEM EMI CN32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

C.2.16

P6960 series high-density logic probe land pattern CN33/CN36 . . . . . 106

C.2.17

DVB-CI connector CN34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

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Contents STi5197-MBoard, STi5189/97-MB

C.2.18

I2C blaster connector CN35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

C.2.19

Ethernet MII data connector CN37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

C.2.20

RJ45 Ethernet connector CN38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Appendix D MB676 23 x 23 processor board jumpers, option resistors and switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

D.1

Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

D.2

Option resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

D.3

Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Appendix E MB704 15 x 15 processor board jumpers, option resistors and switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

E.1

Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

E.2


E.3

Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Appendix F MB762 SD generic peripheral board jumpers, option resistors and switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

F.1

F.2

Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125


F.3

Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Appendix G MB829 SD modular validation peripheral board jumpers, option resistors and switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

G.1

Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

G.2


G.3

Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Appendix H PIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Appendix I Hardware configuration guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

I.1

I.2

FMI EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

I.1.1

I.1.2

I.1.3

FMI decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

FMI EPLD register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

FMI EPLD register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Transport stream EPLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

I.2.1

TS mode descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

6/160 8149405

STi5197-MBoard, STi5189/97-MB Contents

I.3

I.4

I.5

I.6

I.7

I.8

EPLD programming instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

I.3.1

I.3.2

Programming EPLDs using the LVDS connection . . . . . . . . . . . . . . . . 152

JTAG chain setup for use with ByteBlaster connector CN16/CN11 . . . 152

General mode switch settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

SPI devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

I

2

C devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Appendix J Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

8149405 7/160

Introduction

1 Introduction


●

●

The STi5197-MBoard and STi5189/97-MB are evaluation boards, which enable: validation of the STi5189 and STi5197 system-on-chips (SoC) software development and evaluation of the STi5189 and STi5197 SoCs and peripheral applications

The evaluation boards consist of:

●

a processor board, described in Chapter 4 on page 13

– for the STi5189/97-MB, this is an MB676 STi5189 or STi5197 23 x 23 processor board

– for the STi5197-MBoard, this is an MB704 STi5197 15 x 15 processor board

●

●

The 15 x 15 processor board is a cut-down of the 23 x 23 processor board. EMI has been removed (boot from serial Flash only).

an SD peripheral board

– for Revisions A and B of the evaluation boards, this is an MB762 SD generic peripheral board, described in

Chapter 5 on page 18

– for Revisions C and later of the evaulation boards, this is an MB829 SD modular validation peripheral board, described in

Chapter 6 on page 28

a power supply, described in Section 3.3 on page 12

A block diagram of the system is shown in Section 3.1: System block diagram on page 11

.

The STi5197 and STi5189 SoCs contain an ST40-300 core. For more information, see the

STi5197 datasheet (ADCS 8148435) and the STi5189 datasheet (ADCS 8141465).

The target audience for this datasheet includes:

●

●

●

●

● software application and validation teams marketing board manufacturing services (debug) field application engineers original equipment manufacturers (OEM)

1.2 References

STi5197 datasheet (ADCS 8148435)

STi5189 datasheet (ADCS 8141465)

ST Micro Connect 2 datasheet (ADCS 7912386)

ST40 Micro Toolset user manual (ADCS 7379953)

8/160 8149405

STi5197-MBoard, STi5189/97-MB System overview

Figure 1.

STi5197-MBoard, STi5189/97-MB debug setup and interconnection block diagram

Ethernet to suitable test device

RFin

Audio outputs

Ethernet

RJ45

STi5197-MBoard

USB2.0

STi5189/97-MB

HDMI

HDMI

(Upsampled SD)

HDMI/DTV monitor

Windows/Linux PC development host running multiple debug operations

USB2.0

LVDS debug

Power socket

Power

CVBS/YC/RGB/

YPbPr

SD AV outputs

PAL/NTSC monitor and audio system or VCR

Ethernet

LVDS cable

ST Micro Connect 2

10baseT

Ethernet connection

(network or point-point)

Table 1.

System requirements for using the ST40 Micro Toolset on the board

Component Description Supplier Part number

PC/Linux development host

Supported configuration: Windows 2000/XP OS

Pentium class PC, RedHat Linux Enterprise

V3.0 or higher for Linux development (minimum

Pentium II processor exceeding 300 MHz with

32 Mbytes of RAM, greater than 120 Mbytes disk free space).

Any PC supplier

STi5197-MBoard or

STi5189/97-MB

STi5197/STi5189 evaluation board.

STMicroelectronics

ST Micro Connect 2

Hardware interface from Ethernet to motherboard under test.

STMicroelectronics

Not applicable

STi5197-MBoard or STi5189/97-MB

STMC2-20/40/200

ST40 Micro Toolset

ST40 STLinux

Embedded core development toolset.

ST40 STLinux distribution and development environment.

STMicroelectronics

Contact your local

ST sales office

STMicroelectronics from www.stlinux.com

Not applicable

Not applicable HDMI/DVi monitor HD ready monitor.

PAL/NTSC TV

(Legacy) Monitor with SD, composite video input, SCART or VGA.

Reference software STi5189/STi5197 software modules

Any OEM monitor

Any OEM monitor

STMicroelectronics

Packet injector and front-end (optional)

Tuner, QPSK demodulation and FEC for satellite or cable bitstream reception, development board with STEM or NIM interface.

STMicroelectronics

Not applicable

STAPI

PI-NIM

8149405 9/160

System overview

2.1


Equipment and software

The following are required:

●

●

●

●

● an ST Micro Connect 2 (STMC2) with an LVDS cable to link the STMC2 to the board a Windows/Linux capable PC an Ethernet cable to link the PC to the STMC2 and board

ST40 Micro Toolset R4.2.1 or later

ST Micro Connection Package R1.2.1 or later

The STMC2 is a host-target interface that connects to the board’s JTAG port and provides host software with the ability to start up the board, download programs and debug them on the target.

For further information on STMC2, please refer to ST Micro Connect 2 datasheet

(ADCS 7912386).

For information on the ST40 toolset, refer to the ST40 Micro Toolset user manual

(ADCS 7379953).

2.2 Electrostatic discharge (ESD) protection

If the board is used in a standalone manner on the workbench, it must be in a static-free environment, maintaining antistatic precautions at all times. For example, the board must be placed on a grounded antistatic mat and the user must always wear the wrist strap connected to the mat.

10/160 8149405

STi5197-MBoard, STi5189/97-MB Product configuration

3.1 System block diagram

Figure 2.

STi5197-MBoard, STi5189/97-MB system interconnect block diagram

KEY

On the peripheral board

On the processor board

Tuner front end

Transport stream, see

Section 5.9 on page 24

DDR

SDRAM

USB

HDMI

2 x smartcards

2 x RS232

(D type)

JTAG

BTSC modulator

(1)

(1)

On MB762 only.

LMI

ULPI

DVO

STi5189/STi5197

ASC

JTAG

TS

EMI

AV

IR

MII

Buffer ATAPI

Buffer

DVB-CI

I/F

STEM

I/F

Buffer

NAND

Flash

NOR

Flash

Address decoder

Serial

Flash

Audio block, see


Video block, see


Infrared

RX

Ethernet

The STi5189/STi5197 processor is mounted into a socket on the processor board.

The processor board connects to the SD generic peripheral board by two connectors on the underside of the PCB. Connectors CN8 and CN9 on the MB704, and connectors CN11 and

CN12 on the MB676, slot into CN29 and CN30 of the MB762 and CN23 and CN16 of the

MB829 peripheral board.

8149405 11/160

Product configuration STi5197-MBoard, STi5189/97-MB

Power to the processor board is provided from the peripheral board using the board to board connectors. Any different voltages required are generated using voltage regulators, or convertors.

The MB762 peripheral board is powered by a +12V DC power socket. This provides +12V,

+5V and +3V3.

The MB829 peripheral board is powered by an ATX power supply. This provides +12V, -12V,

+5V, -5V, +3V3 and +5V standby.

The power supply to the processor board can be isolated and powered by external power sources for CPUIO (+3V3), ANA (+2V5), CPUINT (+1V) and CPULMI (+2V5 and +3V3 levels). The processor module uses isolating connectors (CN3, CN4, CN5 and CN8 on

MB676 and CN2, CN3, CN4 and CN10 on MB704) to power from an external source.

An ATX power supply connector is also provided on the processor board

(a)

for stand-alone use.

12/160 a.

An ATX power supply is not available on MB704 Revision A boards.

8149405


4 MB676/MB704 processor board

MB676/MB704 processor board

●

●

The processor board is available to support two package sizes (see Chapter 1: Introduction on page 8 ):

MB676 is a 23 x 23 STi5189 or STi5197 processor board

MB704 is a 15 x 15 STi5197 processor board

Warning: On the MB704, if the socket is overtightened when the processor is changed, the board may stop working. The recommended torque is 0.226 Nm or 22.6 cNm.

The processor board is mounted on top of the SD peripheral board and connects through two board to board connectors.

●

●

●

●

●

The main components and functions on the processor board are:

● a socketed SoC, either:

– STi5197, see the STi5197 datasheet (ADCS 8148435)

– STi5189, see the STi5189 datasheet (ADCS 8141465) cable tuner front end satellite tuner front end (MB676 only)

SPI Flash with enhanced security features

LMI memory interface, 64 Mbytes DDR SDRAM interfaces

– USB2.0

●

– HDMI

ATX power supply connector for stand-alone use (not on MB704 revision A boards)

A block diagram of the processor board is shown in

Figure 3 .

Figure 3.

Block diagram of the processor board

Tuner front ends

SPI

Flash

SPI

DDR

SDRAM

USB

LMI

ULPI

Processor board

HDMI DVO

8149405 13/160

MB676/MB704 processor board STi5197-MBoard, STi5189/97-MB

●

●

●

●

●

●

The SD peripheral board provides regulated +12V, +5V and +3V3 supplies to the

MB676/MB704 processor board, through the board to board connectors, CN11/CN8 and

CN12/CN9. These voltage levels are passed through the board and used to power various devices.

The +12V supply provides power to the +8V audio power supply isolator.

The +5V supply is stepped down to produce a voltage level of +2V5.

The +3V3 supply provides power to the processor (CPUIO).

The +3V3 supply is stepped down to produce an adjustable output voltage or a fixed

output voltage of +1V. This is controlled by the jumper J11, see Section D.1: Jumpers on page 111

.

●

Alternatively, the +1V power supply can be sourced from a regulator integrated in the

STi5189/STi5197 device.

The +3V3 supply is stepped down to +1V2 to power the HDMI controller chip.

The +3V3 supply is stepped down to provide +1V8 to power the USB controller chip.

Alternatively, the USB can be powered from the +2V5 supply stepped down to +1V8 using a low-cost diode option. This is selectable with the jumper J17.

The LMI I/O (CPULMI) interface is powered using either the +3V3 supply for SDRAM or the +2V5 supply for DDR.

When the processor board is used in standalone mode, the +12V, +5V and +3V3 supplies are provided directly to the processor board through the ATX power connector CN1/CN16.

Revision A of the MB704 processor board does not have an ATX power connector.

4.2 Reset

The reset sources are:

●

●

●

● power on reset

JTAG reset

SW1 reset reset out from the SD peripheral board

These reset sources are combined to generate the following resets:

●

●

●

●

●

●

Ethernet (MII connector)

USB Phy

HDMI Phy down to SD peripheral board

STi5189/STi5197

SPI Flash

On the MB676 only, each of the above may also be individually activated using an I

2

C write to the corresponding bit of the PIO expander device.

The power on reset uses an ST power management device, to generate the reset signal towards the STi5189/STi5197.

14/160 8149405

STi5197-MBoard, STi5189/97-MB MB676/MB704 processor board

4.3 Clocks

One 30 MHz crystal is available to support the VCXO functionality.

An external clock can also be connected through CN14 on MB676 or CN12 on MB704.

4.4 Interrupts

●

●

●

●

The memory mapped EMI EPLD controls and masks the interrupts. The interrupt sources are:

DVB-CI card scart switch

HDMI from processor board

USB VBUS overcurrent from processor board

For further information on interrupts, please refer to

Appendix I: Hardware configuration guide on page 138

.

4.5 Debug

A standard JTAG connector is provided for stand-alone use or as an alternative to the LVDS connection interface on the peripheral board.

4.6.1

4.6.2

4.6.3

●

●

●

The STi5189/STi5197 provides the following host memory interfaces: local memory interface (LMI) flexible memory interface (FMI)

(a)

SPI Flash memory

Local memory interface (LMI)

The STi5189/STi5197 integrates a 16-bit wide SDR/DDR SDRAM interface. The processor board is fitted with a 64-Mbyte device arranged as 8M x 16-bit x 4 banks.

Flexible memory interface (FMI)

The FMI

(a)

is a general-purpose interface for attaching Flash and peripherals. It is described

in

Section 5.8 on page 22 .

SPI Flash memory interface

The STi5189/STi5197 provides a seamless interface to the serial Flash using the SPI protocol.

Three serial Flash devices are available, one on the processor boards and two on the peripheral board. These are selectable by jumpers. a.

This is not available for the MB704 STi5197 15 x 15 processor board.

8149405 15/160

MB676/MB704 processor board STi5197-MBoard, STi5189/97-MB

4.7 Interfaces

The following interfaces are accessible through connectors on the processor board:

●

●

●

●

●

●

USB2.0

MII/RMII Ethernet (MB704 only)

HDMI

QAM cable tuner

QPSK satellite tuner (MB676 only)

I

2

C

A USB2.0 type A connector and a USB3317 Phy are provided on the processor board.

A 100-pin T&MT connector is also provided on the MB676 to allow an external USB Phy to be connected.

4.7.2 Ethernet

The MB704 provides a header to support an external MII/RMII Ethernet Phy. An on-board

LAN8700 Phy and an RJ45 Ethernet connector are provided on the SD peripheral board.

4.7.3 HDMI

An on-board Silicon Images 9024 HDMI Phy provides an upsampled SD to HD output at resolutions of up to 1080p. A standard HDMI connector is provided.

4.7.4 Tuners

The processor board provides the following tuners:

●

●

QAM cable tuner

QPSK satellite tuner (only available on the MB676)

4.7.5 I

2

C interfaces

There are three I

2

C connectors on the processor board. These are used for the PIO expander, HDMI controller and QPSK debug interface.

The MB676 has an additional LNB controller and the MB704 has an additional connector provided for QAM debug purposes.

16/160 8149405

STi5197-MBoard, STi5189/97-MB MB676/MB704 processor board

4.8 PIO

●

●

PIO signals can be assigned alternative functions. This enables the silicon to be configured for different architectures. Some PIO pins can be programmed as: inputs and outputs alternative functions

A complete list of PIO assignments is available in the STi5197 datasheet (ADCS 8148435).

The PIO functions used by the board are given in Appendix H on page 136

.

Inputs connected to the alternative function input are permanently connected to the input pin. Output signals from a peripheral are only connected when the PIO bit is configured into either push pull or open drain driver, alternative function mode.

Some alternative function signals are available on more than one PIO port.

In addition to the multiplexing on the PIO pins, other pin multiplexing is used to provide different signal options, which depend on the device application.

8149405 17/160

MB762 SD generic peripheral board

5



Note: This peripheral board is used for Revisions A and B of the STi5197-MBoard and

STi5189/97-MB evaluation boards.

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

The main features of the MB762 SD generic peripheral board are: dual RS232 (COM0 and COM1) infrared receiver and transmitter

I

2

C dual smartcard

FMI, which provides access to:

– NAND Flash

– NOR Flash

– ATAPI

DVB-CI transport stream updating EPLDs

SPDIF input and outputs to phono connectors two channel PCM audio outputs to phono connectors

NIM interface

SPI serial Flash

BTSC modulator digital audio (PCM, SPDIF) analog audio video (SD) outputs to phonos and SCART

Ethernet using LAN8700 Phy

A block diagram of the SD generic peripheral board is shown in Figure 4

.

18/160 8149405

STi5197-MBoard, STi5189/97-MB MB762 SD generic peripheral board

Figure 4.

Block diagram of MB762 SD generic peripheral board



TS

2 x smartcards

2 x RS232

(D type)

JTAG

BTSC modulator

ASC

STi5189/STi5197

JTAG

EMI

AV

IR

MII/RMII

Buffer ATAPI

Buffer

Buffer

DVB-CI

I/F

STEM

I/F

NAND

Flash

NOR

Flash

Address decoder

Serial

Flash

Audio block, see


Video block, see


Infrared

RX

Ethernet

The SD generic peripheral board is powered by a +12V DC power socket. Main voltage levels of +5V and +3V3 are derived from this +12V DC input.

Voltage levels of +3V3, +5V and +12V are supplied to the processor board through the board to board connectors.

8149405 19/160

MB762 SD generic peripheral board STi5197-MBoard, STi5189/97-MB

5.2 Resets

Individual reset outputs on the SD generic peripheral board are as follows:

●

●

●

●

●

●

●

MII reset

STEM reset transport stream connector reset

NIM reset

ATAPI reset

DVBCI reset smartcard reset

●

●

●

●

The reset sources for the MB762 are: power-on reset

LVDS JTAG reset front panel reset switch processor board

●

●

●

●

●

●

●

There are also software controlled resets programmable using an FMI EPLD mapped register (only available on the STi5189/97-MB):

NIM transport stream connector

ATAPI

STEM

NOR Flash

DVB-CI

PCMDAC

5.3 Interrupts

●

●

●

●

●

●

The SD generic peripheral board is responsible for multiplexing interrupts from the following sources:

HDMI (processor board)

USB VBUS overcurrent (processor board)

STEM (x2)

ATAPI

DVB-CI

SCART

These interrupts are then multiplexed by the FMI EPLD onto three interrupt lines which go to the STi5189/STi5197 on the processor module.



.

20/160 8149405


5.4


Dual serial RS232

Dual RS232 ports (RS232 COM0 and RS232 COM1) with flow control are provided. RXD,

TXD, RTS and CTS signals are supported with a suitable RS232 convertor chip.

Support for one infrared receiver/transmitter module is provided on the peripheral board with a frequency of 36 KHz.

I

2

C buses are required for:

●

●

●

●

●

●

●

●

● cable and/or satellite tuner with LNB

EEPROM

SCART switch

PIO expander

HDMI

MB762 NIM cards and NIM LNB controller optional transport stream connector optional DVO connector optional PCM audio connector

Three I

2

C interfaces from three separate SSC communications modules within the SoC are supported by the MB762 modular interface. Two of these are available for general use, the other is dedicated to the on-chip QPSK demodulator. Only 2-wire I

2

C is supported. In addition, a separate I

2

C host interface is required for debug access to the QAM cable demodulator from an external initiator, through an I

2

C to STBus interface. This is multiplexed into one of the GPIO banks and is active by default when the chip is reset.

A separate dedicated I

2

C interface is provided from the STi5189/STi5197 for the main control of the tuner(s). Extra debug access is provided on the MB704 Revision B boards with options to connect to an external initiator or one of the other PIO controlled I

2

C buses

The I

2

C connectors use a 2 x 4-way header (pin 1 removed) as used by the +3V3 I

2

C parallel port interface. The connectivity of I

2

C is shown in Figure 5

.

8149405 21/160


Figure 5.

I

2

C connectivity

USB to I

2

C convertor daughter card

Processor board

STi5189/STi5197

SSC2

SSC0

QAM debug port

HDMI

PIO expander

Tuner(s)

LNB


MB762 peripheral board

SCART

EEPROM

NIM/LNB

5.8

Support for dual smartcards is provided on the peripheral board (CN25). The top smartcard

(smartcard 0) supports both ICAM and standard smartcard formats. The bottom smartcard

(smartcard 1) only supports standard smartcard format.

Flexible memory interface (FMI)

●

●

●

●

●

The FMI is a general-purpose interface for attaching Flash and peripherals which support:

NOR Flash

NAND Flash external bus master support through BUSREQ/BUSGNT signals

ATAPI (PIO mode only)

DVB-CI

Up to four banks are available. Each bank has a dedicated strobe timing configuration and chip select signal. The FMI memory map is shown in

Table 2 . For further information, refer

to

Appendix I: Hardware configuration guide on page 138 .

As this mapping is controlled by the EPLD, it is possible to re-map devices to different banks for special requirements.

Table 2.

Bank

Board FMI memory map

Function

Bank 0

(boot area)

Bank 1

Bank 2

Bank 3

32-Mbyte NOR Flash or 4-Gbyte NAND Flash (selectable through jumpers/EPLD)

ATAPI and EPLD

DVB-CI

STEM

22/160 8149405


5.8.1 STEM interface

The STEM FMI board interface is an external 16-bit, general purpose interface. It can be used to plug in additional memory and peripheral devices, and to allow probing of the FMI bus.

Information on FMI support is given in

Section 4.6: Memory interfaces on page 15 .

The FMI system block diagram is shown in Figure 6

.

Figure 6.

FMI system block diagram

Processor board

SoC

FMI


EMI

EPLD

IC21

TTL buffers

STEM

EMI

ATAPI

DVB-CI

NAND

Flash

NOR

Flash

STEM

FMI

8149405 23/160


5.9


DVB-CI and transport stream

A single DVB-CI card is supported on the board. The primary tuner stream leads to TSOUT.

This output is then routed to the DVB-CI slot to provide a decoded CA stream to TSIN.

All transport stream signal are routed through an EPLD to allow routing of any source transport stream signals to any destination transport stream signals, either individually or in parallel. Routing configurations are coded in the EPLD and the options are chosen by the config switches.

The transport stream interface is supported by a single ST-NIM2.1 interface. The ST-NIM2.1 provides power and LNB control circuitry suitable for various tuner NIM modules and the

PI-NIM packet injector board.

The transport stream and DVB-CI block diagram is shown in

Figure 7 .

Figure 7.

Transport stream and DVB-CI block diagram

MB762 peripheral board Processor board

Tuner

ST-NIM

EPLD

Integrated

QAM/QPSK demodulator

STi5189/STi5197

TSIN

TSOUT

Config switches

Software transport stream

24/160 8149405


This board has two EPLDs, these are:

●

●

FMI (IC23) transport stream (IC24)

For more information on the EPLDs, refer to


.

The EPLDs can be updated or programmed remotely. There are two different methods of programming the EPLDs.

● Connection from the PC to an Altera ByteBlaster interface. This interface connects to

the EPLD connector (CN16) through a ribbon cable, see Figure 8

.

● Alternatively the STMC2 is connected directly to the LVDS type G connector (CN2)

using an LVDS cable, see Figure 9

. This is the fastest and easiest method of programming the EPLDs and is described in the ST Micro Connect 2 datasheet

(ADCS 7912386).

Figure 8.

EPLD ByteBlaster programming connectivity

Altera ByteBlaster

TTL connector to EPLD connector

2 x 5-way (CN16)

Figure 9.

EPLD STMC2 programming

EPLD connector (CN16)

ST Micro Connect 2

LVDS cable connects to LVDS port (CN2/CN10) on the MB762

LVDS cable

8149405 25/160


5.11 Audio

The following audio sources are available:

●

●

●

● analog audio

SPDIFout

PCMin

PCMout

Figure 10.

Audio block diagram

Processor board

SPDIF

STi5189/

STi5197

DAC

PCMout

PCMin



SPDIFout

Audio dual phono

SCART switch

DAC

PCMout header

PCMin header

Phono

Audio phono connectors are provided, after being buffered using Op-Amp circuitry.

5.11.2 SPDIFout

The SPDIF output is provided with an RCA/phono socket. The output can be connected to an external decoder and amplifier system.

5.11.3 PCMin

A header on the MB762 can be used to input PCM to the STi5189/STi5197.

5.11.4 PCMout

A PCM DAC is supported by the board with left and right phono outputs located on the rear panel.

26/160 8149405


5.12 Video

Four video DACs are supported by this board. One of these DACs is designed with high-drive capabilities to allow unbuffered connection. The other three DACs require buffering which is done by the SCART switch (IC22).

The high-drive output is connected to both the SCART switch and a phono connector for direct connection to a TV.

The following video configurations are possible:

●

●

●

●

Composite + SVideo (YC)

Composite + Component(YUC)

RGB (+sync)

SVideo + composite1 + composite2

Figure 11.

Video block diagram

Processor board

STi5189/

STi5197

DENC

DVO

HDMI


SCART-TV

SCART switch

Video filters

IDC header

SCART-AUX

CVBS out phono

8149405 27/160

MB829 SD modular validation peripheral board

6



Note: This peripheral board is used for Revisions C and later of the STi5197-MBoard and

STi5189/97-MB evaluation boards.

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

The main features of the SD modular validation peripheral board are: dual RS232 (COM0 and COM1) infrared receiver and transmitter

I

2

C dual smartcard

FMI, which provides access to:

– NAND Flash

– NOR Flash

– ATAPI

DVB-CI transport stream updating EPLDs

SPDIF input and outputs to phono connectors two channel PCM audio outputs to phono connectors

NIM interface

SPI serial Flash digital audio (PCM, SPDIF) analog audio video (SD) outputs to phonos

Ethernet using LAN8700 Phy

A block diagram of the SD modular validation peripheral board is shown in Figure 12 .

28/160 8149405

STi5197-MBoard, STi5189/97-MB MB829 SD modular validation peripheral board

Figure 12.

Block diagram of MB829 SD modular validation peripheral board



2 x smartcards

2 x RS232

(D type)

JTAG

ASC

STi5189/STi5197

JTAG

TS

EMI

AV

IR

MII

Buffer ATAPI

Buffer

DVB-CI

I/F

STEM

I/F

Buffer

NAND

Flash

NOR

Flash

Address decoder

Serial

Flash

Audio block, see


Video block, see


Infrared

RX

Ethernet

The SD modular validation peripheral board is powered by a standard ATX power supply.

The power supply provides the board with +12V, -12V, +5V, -5V, +3V3, +5V standby.

A front panel switch (SW6) is used to switch the power supply on or off.

A signal from the processor module can also turn the power supply on or off. This is connected to the LVDS JTAG debug device, allowing remote power cycling of the board, for validation purposes. This power supply enable signal is isolated by a jumper (J10) to only use the front panel switch.

Voltage levels of +3V3, +5V and +12V are supplied to the processor board through the board to board connectors.

8149405 29/160

MB829 SD modular validation peripheral board STi5197-MBoard, STi5189/97-MB

6.2 Resets

Individual reset outputs on the SD modular validation peripheral board are as follows:

●

●

●

●

●

●

●

MII reset

STEM reset transport stream connector reset

NIM reset

ATAPI reset

DVB-CI reset smartcard reset

●

●

●

●

The reset sources for the MB829 are: power-on reset

LVDS JTAG reset front panel reset switch processor board

●

●

●

●

●

●

●

There are also software controlled resets programmable using an FMI EPLD mapped register (only available on the STi5189/97-MB):

NIM transport stream connector

ATAPI

STEM

NOR Flash

DVB-CI

PCMDAC

6.3 Interrupts

●

●

●

●

●

The SD modular validation peripheral board is responsible for multiplexing interrupts from the following sources:

HDMI (processor board)

USB VBUS overcurrent (processor board)

STEM (x2)

ATAPI

DVB-CI

These interrupts are then multiplexed by the FMI EPLD onto three interrupt lines which go to the STi5189/STi5197 on the processor module.



.

6.4

30/160

Dual serial RS232

Dual RS232 ports (RS232 COM0 and RS232 COM1) with flow control are provided. RXD,

TXD, RTS and CTS signals are supported with a suitable RS232 convertor chip.

8149405


Support for one infrared receiver/transmitter module is provided on the peripheral board with a frequency of 36 KHz.

●

●

●

●

●

●

●

●

I

2

C buses are required for: cable and/or satellite tuner with LNB

EEPROM

PIO expander

HDMI

MB829 NIM cards and NIM LNB controller optional transport stream connector optional DVO connector optional PCM audio connector

Three I

2

C interfaces from three separate SSC communications modules within the SoC are supported by the MB829 modular interface. Two of these are available for general use, the other is dedicated to the on-chip QPSK demodulator. Only 2-wire I

2

C is supported. In addition, a separate I

2

C host interface is required for debug access to the QAM cable demodulator from an external initiator, through an I

2

C to STBus interface. This is multiplexed into one of the GPIO banks and is active by default when the chip is reset.

A separate dedicated I

2

C interface is provided from the STi5189/STi5197 for the main control of the tuner(s). Extra debug access is provided on the MB704 Revision B boards with options to connect to an external initiator or one of the other PIO controlled I

2

C buses

The I

2

C connectors use a 2 x 4-way header (pin 1 removed) as used by the +3V3 I

2

C parallel port interface. The connectivity of I

2

C is shown in Figure 13

.

Figure 13.

I

2

C connectivity


USB to I

2

C convertor daughter card

Processor board

STi5189/STi5197

SSC2

SSC0

QAM debug port

HDMI

EEPROM

PIO expander

Tuner(s)

NIM/LNB

LNB

8149405 31/160

MB829 SD modular validation peripheral board STi5197-MBoard, STi5189/97-MB

Support for dual smartcards is provided on the peripheral board (CN30). The top smartcard

(smartcard 0) supports both ICAM and standard smartcard formats. The bottom smartcard

(smartcard 1) only supports standard smartcard format.

6.8 Flexible memory interface (FMI)

●

●

●

●

●

The FMI is a general-purpose interface for attaching Flash and peripherals which support:

NOR Flash

NAND Flash external bus master support through BUSREQ/BUSGNT signals

ATAPI (PIO mode only)

DVB-CI

Up to four banks are available. Each bank has a dedicated strobe timing configuration and chip select signal. The FMI memory map is shown in

Table 3 . For further information, refer

to

Appendix I: Hardware configuration guide on page 138 .

As this mapping is controlled by the EPLD, it is possible to re-map devices to different banks for special requirements.

Table 3.

Bank

Board FMI memory map

Function

Bank 0

(boot area)

Bank 1

Bank 2

Bank 3

32-Mbyte NOR Flash or 4-Gbyte NAND Flash (selectable through jumpers/EPLD)

ATAPI and EPLD

DVB-CI

STEM

6.8.1 STEM interface

The STEM FMI board interface is an external 16-bit, general purpose interface. It can be used to plug in additional memory and peripheral devices, and to allow probing of the FMI bus.

Information on FMI support is given in

Section 4.6: Memory interfaces on page 15 .

The FMI system block diagram is shown in Figure 14 .

32/160 8149405


Figure 14.

FMI system block diagram


Processor board

SoC

FMI


EMI

EPLD

IC18

TTL buffers

STEM

EMI

ATAPI

DVB-CI

NAND

Flash

NOR

Flash

STEM

FMI

8149405 33/160


6.9


DVB-CI and transport stream

A single DVB-CI card is supported on the board. The primary tuner stream leads to TSOUT.

This output is then routed to the DVB-CI slot to provide a decoded CA stream to TSIN.

All transport stream signal are routed through an EPLD to allow routing of any source transport stream signals to any destination transport stream signals, either individually or in parallel. Routing configurations are coded in the EPLD and the options are chosen by the config switches.

The transport stream interface is supported by a single ST-NIM2.1 interface. The ST-NIM2.1 provides power and LNB control circuitry suitable for various tuner NIM modules and the

PI-NIM packet injector board.

The transport stream and DVB-CI block diagram is shown in

Figure 15 .

Figure 15.

Transport stream and DVB-CI block diagram

MB829 peripheral board Processor board

Tuner

ST-NIM

EPLD

Integrated

QAM/QPSK demodulator

STi5189/STi5197

TSIN

TSOUT

Config switches

Software transport stream

34/160 8149405


This board has two EPLDs, these are:

●

●

FMI (IC18) transport stream (IC19)

For more information on the EPLDs, refer to


.

The EPLDs can be updated or programmed remotely. There are two different methods of programming the EPLDs.

● Connection from the PC to an Altera ByteBlaster interface. This interface connects to

the EPLD connector (CN11) through a ribbon cable, see Figure 16

.

● Alternatively the STMC2 is connected directly to the LVDS type G connector (CN10)

using an LVDS cable, see Figure 17 . This is the fastest and easiest method of

programming the EPLDs and is described in the ST Micro Connect 2 datasheet

(ADCS 7912386).

Figure 16.

EPLD ByteBlaster programming connectivity

Altera ByteBlaster

TTL connector to EPLD connector

2 x 5-way (CN11)

Figure 17.

EPLD STMC2 programming

ST Micro Connect 2

EPLD connector (CN11)

LVDS cable connects to LVDS port (CN10) on the MB829

LVDS cable

8149405 35/160


6.11 Audio

The following audio sources are available:

●

●

●

● analog audio

SPDIFout

PCMin

PCMout

Figure 18.

Audio block diagram

Processor board

SPDIF

STi5189/

STi5197

DAC

PCMout

PCMin



SPDIFout

Audio dual phono

DAC

PCMout header

PCMin header

Phono

Audio phono connectors are provided, after being buffered using Op-Amp circuitry.

6.11.2 SPDIFout

The SPDIF output is provided with an RCA/phono socket. The output can be connected to an external decoder and amplifier system.

6.11.3 PCMin

A header on the MB829 can be used to input PCM to the STi5189/STi5197.

6.11.4 PCMout

A PCM DAC is supported by the board with left and right phono outputs located on the rear panel. A header can also be used to access PCMout directly.

36/160 8149405


6.12 Video

Four video DACs are supported by this board. One of these DACs is designed with high-drive capabilities to allow unbuffered connection. The other three DACs require buffering.

The high-drive output is connected to a phono connector for direct connection to a TV.

The following video configurations are possible:

●

●

●

●

Composite + SVideo (YC)

Composite + Component(YUC)

RGB (+ sync)

SVideo + composite1 + composite2

Figure 19.

Video block diagram

Processor board

STi5189/

STi5197

DENC


HDMI

Video filters

Video buffers

CVBS out phono

RGB out (phono)

Component out

DVO

IDC header

8149405 37/160

MB676/MB704 processor board connectors STi5197-MBoard, STi5189/97-MB

Appendix A MB676/MB704 processor board connectors

This appendix describes the connectors for both the MB676 23 x 23 processor board and the MB704 15 x 15 processor board.

The connector placements on the two processor boards are shown in

Figure 20

and

Figure 21

.

Figure 20.

MB676 23 x 23 processor board top assembly connector layout

JTAG debug connector

USB PHY connector

USB Type A connector

External clock input

Tuner can with integrated satellite tuner

Digital cable tuner

HDMI connector

C165 R180

C166

R181

H5

C168 C167

R183

R116

R119

IC20

R121

TP83

R115

IC16

D1

TP100

C172

R187

L7

R124

C120

L6

C176

C174

L9

R190

R191

IC21

R127 R126

C122

C121

C125

C127

C128

R128

H6

R129

R131

TP71

R22 R23 R24

CN9

J2

C15

R27

IC6

R26 R25

C14

TP30

TP32 J3

R76

R21

TP31

TP33

R78 R77

H3

L1

C129

R85

R87

R88

R86

R89 R90

R82 R84 R83

R93 R92 R91

C29

IC22

C180

C181

D6 L11

XT2

J22

R139

IC10

C182

C136

CN14

C183

C185

L13

R143

R144

IC23

R101

R145

R146

C141

R147

R148 C143

R152

R170

R149

R153

R157

R160

C147

C150

C156

R150

R155

R158

R156

C146 C145

CAN1

IC24

TR3

C155

J25

C109

TR5

R161

R159

J12

R108 R107

XT1

C106 C107

R109

R106

C96

R201

TR4

C190

TR6

TP91

L8 TR2

C157

TP92

C192

C193 D7

R203 C158

R171 R172

R173

R174

R175

J15

R110

C159

C160

IC26

R177

IC27

IC28

IC11

R56

R54

C103

IC12

J6 J5

J7

J9

J8

J10

C62

TP65

C70

C161

R209

C163

C201

H7 C202

R179

R178 C114

C79

H4

R62

CN6

R59

C77

TP67

R51

IC13

C61

R61 R60

CN7

C42

IC2

R42

C54

SW1

R8 R7

R3

R6

R10

R12 R13

R15

R14

CN2

C12

TP17

H1

TP1

TP2

TP3

J27 J16

IC14

R64

R66

R67

H2

ATX power connector

Power ground isolators

I

2

C 1 connector

I

2

C 2 (QPSK) connector

I

2

C 3 connector

Power ground isolator

38/160 8149405

STi5197-MBoard, STi5189/97-MB MB676/MB704 processor board connectors

Figure 21.

MB704 15 x 15 processor board top assembly connector layout

Type A USB

H5

C107

C108

R175

IC17

R180

R181

R182

R183

R184

C114

H6

C115

JTAG UDI debug connector

MII Ethernet connector

C41

R2

R3

R155

IC14

TP79

D1

IC15

R159 R160

J18

CN11

IC8 IC5

R19

IC11

TP53

R64

R65

R66

C43

C44

R59

R60

R61

R62

R63

R32

R33

R37

R38

R39

R40

R42

R44

R45

R46

C144

C17

C75

C76

H3

L1

IC26

IC6

R34

R35

R36

R41

R43

TP107

TP108

TP31 TP30

C148

C45

H1

TP101 ATX power connector

TP102

TP3

TP33

I

2

C 1 connector


Tuner can with integrated QAM cable tuner

External clock input

QAM I

2

C connector

HDMI connector

C79

C80

TP22

C84

C86

C103

TR6

TR4

IC22

C90 R149

XT1

L7

L6

TR5

R215 R216

CN12

J14

D2

CN13

R198

C120

R201

R204 R203

J15

R167

C126

C127

IC18

R208

IC19

IC20

C131

R209

C121

TP80

C132

H7 C133

R168

R152

R169

R170

R171

C105

R153

R154

IC10

J7

J8

J9

C60 J3

J4

J5

J6

TP50

C64

C72 C40

CN5

CN6

H4


C12

TP38

TP4 TP5 TP103

R9 R1

C13

H2

I

2

C 2 (QPSK) connector

I

2

C 3 connector

Note:

A.1.1

Figure 21

shows assembly connector layout for the MB704 revision B board.

Bottom assembly connector layout

On the bottom (solderside) of both boards are two connectors, CN11 and CN12 for the

MB676, and CN8 and CN9 for the MB704. These are used for connecting to the SD peripheral board MB762 (for Revision A and B boards) or MB829 (for Revision C or later boards).

8149405 39/160


The front panel of the processor board is screwed in to the rear panel of the MB762 SD generic peripheral board as shown in

Section B.2: Front and rear panel layout on page 57 .

The MB676 front panel is shown in

Figure 22

and the MB704 front panel is shown in

Figure 23

.

Figure 22.

Display of MB676 23 x 23 processor board front panel

R

MB676 - STi5197 23x23 Processor Board

S/N:

BUILD:

Sat Tuner

Cable Tuner

HDMI

Figure 23.

Display of MB704 15 x 15 processor board front panel

40/160 8149405


A.3 Connectors

The connectors that are fitted on the processor boards are shown in

Table 4 and Table 5

.

Table 4.

Internal connectors

Connector number

Type of connector

MB676

ATX power connector

QPSK I

2

C connector 2

Power GND isolator connector +2V5

CN1

CN2

CN3

Power GND isolator connector +3V3 CPUIO CN4

Power GND isolator connector +2V5 (DDR) CN5

I

2

C connector 1 CN6

QAM I

2

C connector -

I

2

C connector 3 CN7

Power GND isolator connector +1V CPU internal

External USB physical interface connector

Debug connector

CN8

Board to board connectors

External clock generator

MII Ethernet connector

CN9

CN10

CN11

CN12

-

CN14

CN10

-

CN11

CN8

CN9

CN12

CN7

1.

Not available on MB704 Revision A boards.

Table 5.

Front panel external connectors



MB676 MB704

MB704

CN16

(1)

CN5

CN3

CN2

CN4

CN1

CN13

CN6

USB type A connector

HDMI connector

Satellite tuner

Digital cable tuner

CN13

CN15

CN16

IC24

CN14

CN15

-

IC22

Reference

Section A.3.1 on page 42














Reference





8149405 41/160

MB676/MB704 processor board connectors

A.3.1

Note:

ATX power connector


This connector is not present on the MB704 Revision A processor board.

The ATX power connector is CN1 on the MB676 and CN16 on the MB704.

A standard ATX power supply is used to provide different voltage levels to the board. This board-mounted Molex connector is a 20-pin mini-fit jr type.

Figure 24.


1 10

11 20

Viewed from above PCB

Table 6.

Pin

6

7

4

5

1

2

3

8

9

10

ATX power connector pin allocation

Description Pin

+3V3_A

+3V3_B

GND_A

+5V_A

GND_B

+5V_B

GND_C

PW_OK

+5VSB

+12V

14

15

16

17

11

12

13

18

19

20

+3V3_C

-12V

GND_D notPS_ON

GND_E

GND_F

GND_G

-5V

+5V_C

+5V_D

Description

42/160 8149405


A.3.2 I

2

C header connectors

These are 2 x 4-way pin post PTH header connectors. Shroudless, with a pitch of 2.54 mm.

The MB676 has the following I

2

C connectors:

●

●

●

QPSK I

2

C connector 2 (CN2)

I

2

C connector 1 (CN6)

I

2

C 3 connector (CN7)

The MB704 has the following I

2

C connectors:

● I

2

C connector 1 (CN1)

● I

2

C connector 2 (CN5)

● I

2

C connector 3 (CN6)

● on-board QAM I

2

C connector (CN13)

Figure 25.

I

2

C header connectors

7 1

8 2

Table 7.

Pin

5

7

1

3

I

2

C header connectors pin allocation

Description Pin

Removed for polarization

USER1

USER2

USER3

6

8

2

4

VCC

SDA

SCL

GND


Description

8149405 43/160


A.3.3


Power ground isolators

There are four power ground isolators on each processor board.

The MB676 has connectors CN3, CN4, CN5 and CN8. These are identical to connectors

CN3, CN2, CN4, CN10 on the MB704.

Four 6-pin headers. 2 x 3-way, polarized straight header connector with a pitch of 2.54 mm

Figure 26.

Power ground isolator connector

1 5

2 6


Table 8.

Pin

1

2

3

Table 9.

Pin

1

2

3

Power ground isolator pin allocation (CN3)

Description Pin

+2V5

2V5_ANA

GND_BRD

4

5

6

GND_ISOL

+2V5

2V5_ANA

Description

Power ground isolator pin allocation (CN4 on MB676, CN2 on MB704)

Description Pin Description

+3V3

CPUIO

GND_BRD

4

5

6

GND_ISOL

+3V3

CPUIO

Table 10.


Pin Description Pin Description

1

2

3

+2V5 (DDR)

CPULMI

GND_BRD

4

5

6

GND_ISOL

+2V5 (DDR)

CPULMI

Table 11.



1

2

3

+1V

CPUINT

GND_BRD

4

5

6

GND_ISOL

+1V

CPUINT

44/160 8149405


Note: This connector is only present on the MB676 processor board.

This is connector CN9 on the MB676.

A 100-pin connector for use with an external USB PHY.

Figure 27.

External USB physical interface connector

50 1

Viewed from side of PCB

Table 12.

External USB physical interface allocation

Pin Description Pin

25

27

29

31

17

19

21

23

33

35

37

39

9

11

13

15

5

7

1

3

NC

TP69 notRESET_ULPI

NC

ULPI_DATA7_T

ULPI_DATA5_T

NC

26

28

30

32

18

20

22

24

34

36

38

40

10

12

14

16

6

8

2

4

NC

+5V

NC

Description

ULPI_DATA3_T

ULPI_DATA1_T

NC

8149405 45/160


Table 12.

External USB physical interface allocation (continued)


83

85

87

89

91

93

95

97

99

71

73

75

77

79

81

55

57

59

61

63

65

67

69

47

49

51

53

41

43

45

NC

TP29

NC

GND

NC

TP68

NC

ULPI_NXT

NC

ULPI_DATA4_T

ULPI_DATA2_T

NC

NC

ULPI_REFCLK

NC

ULPI_DIR

NC

ULPI_DATA6_T

NC

ULPI_DATA0_T

NC

ULPI_CLK

NC

ULPI_STP_t

NC

84

86

88

90

92

94

72

74

76

78

80

82

96

98

100

56

58

60

62

64

66

68

70

48

50

52

54

42

44

46

46/160 8149405


This connector is CN10 on the MB676 and CN11 on the MB704.

A 20-pin connector provides a debug function.

Figure 28.

Debug connector

19 1

20 2


Table 13.

Debug connector pin allocation

Pin Description

Even pins GND

1 RESERVED

3

5

TRIGOUT

TRIGIN

7

9 notASEBRK

TMS

Pin

11

13

15

17

19

Description

TCK

TDI (data into the board)

TDO (data out of the board) notRST_JTAG notTRST

8149405 47/160


A.3.6


Board to board connectors

These connectors are CN11 and CN12 on the MB676 and CN8 and CN9 on the MB704.

Connection between the processor board and the SD peripheral board is by two Samtec

128-pin connectors.

The connectors interface directly with two Samtec 120-pin connectors on the top surface of the SD generic peripheral board (MB762).

CN11/CN8 (EMI) on the processor board connects to CN29 on the MB762 peripheral board and CN23 on the MB829 peripheral board.

CN12/CN9 (PIO) on the processor board connects to CN30 on the MB762 peripheral board and CN16 on the MB829 peripheral board.

Figure 29.

Board to board connector

2

1

128

127

Note:

Viewed from below PCB

In

Table 14 , shaded cells represent pins that are only available on MB676. They are not

connected on the MB704.

.

Table 14.

Board to board connector CN11/CN8


23

25

27

29

15

17

19

21

11

13

7

9

1

3

5

VID_GND0

VDAC_XOUT

VID_GND1

VDAC_UOUT

VID_GND2

NC

VID_GND3

VDAC_WOUT

VID_GND4

VDAC_VOUT

VID_GND5

EMI_ADDR24

EMI_ADDR23_DVOCLK

FMI_ADDR21_DVODATA1

EMI_ADDR3

24

26

28

30

16

18

20

22

8

10

12

14

2

4

6

Description

AUD_GND0

ADAC_VBG

AUD_GND1

ADAC_AOL

AUD_GND2

NC

AUD_GND3

ADAC_AOR

AUD_GND4

SPDIF

AUD_GND5

FMI_ADDR25

FMI_ADDR5

FMI_ADDR22_DVODATA0

FMI_ADDR20_DVODATA2

48/160 8149405


73

75

77

79

81

83

61

63

65

67

69

71

91

93

95

97

99

85

87

89

45

47

49

51

53

55

57

59

37

39

41

43

31

33

35

EMI_ADDR7 notFMICSC

EMI_ADDR6 notFMICSB notFMICSA_SPICS

FMI_ADDR4

FMI_ADDR10

FMI_ADDR14 notFMIBE1

FMI_ADDR13

FMI_NANDWAIT

FMI_ADDR12

FMI_DATA1

FMI_RDnotWR

FMI_DATA7

FMI_DATA6

FMI_DATA13_DVBCI_CD1

FMI_DATA3

FMI_WAIT

FMI_DATA2

FMI_DATA10

FMI_DATA9

FMI_DATA0

TSOINDATA7

TSOINBITORBYTECLK

TSOINDATA5

TSOINERROR

TSOINDATA3

TSOINDATA1

TS0OUTERROR

TS0OUTBITORBYTECLK

TS0OUTDATA4

TS0OUTDATA6

TS0OUTDATA0

TS0OUTDATA2

Table 14.

Board to board connector CN11/CN8 (continued)

Pin Description Pin Description notFMICSD

FMI_ADDR17_DVODATA4

FMI_ADDR8 notFMIBAA_DVBCILORD

FMI_ADDR18

FMI_ADDR19_DVODATA3

FMI_ADDR9

FMI_ADDR11 notFMIBE0_DVBCILOWR

FMI_ADDR2

FMI_ADDR15

FMI_ADDR16_DVODATA5 notFMIOE

FMI_DATA14_DVBCI2

FMI_DATA15_DVBCI1

FMI_DATA12_DVBCI_RESET

FMI_DATA5

FMI_DATA4 notFMILBA

FMI_DATA11

FMI_ADDR1

FMI_DATA8

NAND_RBN2

TSOINDATA6

TSOINPACKETCLK

TSOINBITORBYTECLKVALID

TSOINDATA4

TSOINDATA0

TSOINDATA2

TS0OUTPACKETCLK

TS0OUTBITORBYTECLKVALID

TS0OUTDATA5

TS0OUTDATA7

TS0OUTDATA1

TS0OUTDATA3

74

76

78

80

82

84

62

64

66

68

70

72

86

88

90

92

94

96

98

100

46

48

50

52

54

56

58

60

38

40

42

44

32

34

36

8149405 49/160


Table 14.


Pin

115

117

119

121

123

125

127

101

103

105

107

109

111

113

Description

NANDCSN2

DCU_TCK

DCU_TDO

DCU_notTRST

AUX_TMS

DCU_notASEBRK

DCU_TRIGGERIN

SPARE4

SPARE6

AUX_TDUP

SCRN1

SCRN3

SCRN5

SCRN7

Pin

116

118

120

122

124

126

128

102

104

106

108

110

112

114

Description

NANDCSN3 notMODULERESETIN

DCU_TDI

DCU_TMS

AUX_TCK

DCU_TRIGGEROUT

DCU_DEBUGMODESEL

SPARE5

SPARE7

AUX_TDDOWN

SCRN2

SCRN4

SCRN6

SCRN8

.

Table 15.

Board to board connector CN12/CN9


19

21

23

25

27

29

31

33

35

7

9

11

1

3

5

13

15

17

+5V

NC

+3V3

NC

+12V

NC

SC0DATAOUT

20

22

24

26

28

30

32

34

36

8

10

12

2

4

6

14

16

18

+5V

NC

+3V3

NC

SC0DATAIN

Description

50/160 8149405


79

81

83

85

87

89

91

93

95

67

69

71

73

75

77

51

53

55

57

59

61

63

65

43

45

47

49

37

39

41

SC0EXTCLK

SPI_DATAIN

SPI_DATAOUT

SPI_CLK

PCMLRCLKIN

ASC3_RXD

SC0VPP

ASC3_TXD

PCMDATAIN

SC0DETECT

SCART2_BI_LED2

DVO_DATA7

OSD_ACTIVE_DVOCLK

DVO_DATA6

SCART1_BI_LED1

IRB_OUT

SC1DATAOUT

IRB_IN

CLK27

INTUP0

SSC0_SCLKINOUT

DVBCI_2

SC1EXTCLK

INTUP1

AUXCLKOUT

FMIFLASHCLK

SC1VPP

INTUP2

HSYNC_EN

DVBCI_CD1

Table 15.


Pin

97

99

101

103

SSC1CLK

Description

ASC3_CTS

ASC3_RTS

PCMSCLKIN

Pin

98

100

102

104

Description

DVODATA3

ASC2RXD

DVODATA4

ASC2TXD

SC1DETECT

SC1DATAIN

HSYNC

DMAREQ1

SC1RESET

LED_DRIVE

SC1CMDVCC

VSYNC

SC0CLK

PCMLRCLKOUT

SC0RESET

FDMAREQ1

PCMDATAOUT

SC0CMDVCC

FDMAREQ0

PCMSCLKOUT

FPRESET

SC1CLK

DVODATA0

DVODATA1

ASC2CTS

DVODATA2

ASC2RTS

KEY_CTRL

VSYNC_EN

DMAREQ0 notRSTOUT_GPIO_LOCAL_

RESET

PCMMCLK

SPI_CS_YC3

SSC0_MTSR_DINOUT

80

82

84

86

88

90

92

94

96

68

70

72

74

76

78

52

54

56

58

60

62

64

66

44

46

48

50

38

40

42

8149405 51/160


Table 15.


Pin

105

107

109

111

113

115

117

119

121

123

125

127

Description

YC2

DVBCI_RESET

INTDOWN0

NANDCSN1

NANDRBN1

+5V

GND

Pin

106

108

110

112

114

116

118

120

122

124

126

128

Description

SSC1DATAINOUT

DVBCI_BUSGNT

DVBCI_BUSREQ

INTDOWN1

NANDRBN3

+5V

GND


Surface mount, single USB2.0 type A connector.

Figure 30.

USB2.0 connector

1 2 3 4

Viewed from front panel

Table 16.

USB2.0 connector pin allocation

Pin Description

1

2

VBUS

DM

Pin

3

4

DP

GND

Description

52/160 8149405



Vertical PCB mounting, SMB socket (male).

Figure 31.

External clock connector

1

2


Table 17.

External clock connector pin allocation


1 CLKIN 2 GND

Description

Note:

Note:

This connector is only present on the MB704 processor board.


Surface mount, vertical male connector. Double row of 20 pins with a pitch of 1.27 mm.

Mates with FFSD connector.

The location of pin 1 on the connector is identified on the same side as the notched blade of the connector.

Figure 32.

MII Ethernet connector

39 1

40 2


Table 18.

MII Ethernet connector pin allocation


9

11

13

15

5

7

1

3 NC

MII_COL

MII_TXD0

MII_TXD2

GMII_TXD4

GMII_TXD6

10

12

14

16

6

8

2

4 NC

MII_CRS

MII_TXD1

MII_TXD3

GMII_TXD5

GMII_TXD7

Description

8149405 53/160


Table 18.

MII Ethernet connector pin allocation (continued)

Pin

23

25

27

29

17

19

21

31

33

35

37

39

NC

MII_TXCLK

MII_RXCLK

MII_RXDV

MII_RXD0

MII_RXD2

GMII_RXD4

GMII_RXD6

NC

MII_MDIO notINT

GMIIMODE

Description Pin

24

26

28

30

18

20

22

32

34

36

38

40

MII_TXEN

NC

MII_RXER

NC

MII_RXD1

MII_RXD3

GMII_RXD5

GMII_RXD7

MII_MDC notRESET

RMIIMODE

NC

Description

54/160

This connector is CN15 on both the MB676 and the MB704.

A male, 19-pin connector.

The high-definition multimedia interface is a trademark of HDMI Licensing, LLC.

Figure 33.

HDMI connector

HDMI

HDMI cable


Table 19.

HDMI connector pin allocation

Pin Description

6

7

4

5

8

1

2

3

TX2P (D2+)

GND (D2S)

TX2N (D2-)

TX1P (D1+)

GND (D1S)

TX1N (D1-)

TX0P (D0+)

GND (D0S)

Pin

14

15

16

17

18

11

12

13

Description

GND (CKS)

CK-

HDMI_CEC (CEC)

NC

SCL

SDA

GND

+5V

8149405


Table 19.

HDMI connector pin allocation

Pin Description

9

10

TX0N (D0-)

CK+

Pin

19

Description

HDMI_HPD (HPG)

Note: This connector is only present on the MB676 processor board.


Vertical PCB mounting, SMB socket (male).

Figure 34.

Satellite tuner

1

2


Table 20.

Satellite tuner pin allocation

Pin Description

1 RF_IN

Pin

2 GND

Description

The digital cable tuner is IC24 on the MB676 and IC22 on the MB704.

The tuner input is fed into the female connector. The male connector provides an output as a loop-through of the input.

Figure 35.

Digital cable tuner

MB676 front panel

GND

MB704 front panel

GND GND

GND

Female

(cable input)

Female

(cable input)

Male

(cable output)

Male

(cable output)

Table 21.

Digital cable tuner pin allocation


Female Input Male


Description

Loop-through

8149405 55/160

MB762 SD generic peripheral board connectors STi5197-MBoard, STi5189/97-MB

Appendix B MB762 SD generic peripheral board connectors

The connector placements on the SD generic peripheral board are shown in

Figure 36 .

Figure 36.

SD generic peripheral board top assembly connector layout

ATAPI connector

PCM I2C connector

DVO connector

HDD power connector

DC socket power connector

Smartcard connectors

STEM EMI connector

PCMCIA card connector

RJ45

Ethernet connector

PIO/PWR connector

LVDS debug connector

RF modulator connector

FMI/TS/AV connector

SPDIF phono connector

CVBS phono connector

L audio DAC phono connector

R audio DAC phono connector

EPLD ByteBlaster connector

TV ouput and AUX input

SCART connectors

PCM output debug connector

L PCM audio phono connector

R PCM audio phono connector

Transport stream connector

NIM connector

Dual RS232 connectors

Ethernet data connector

56/160 8149405

STi5197-MBoard, STi5189/97-MB MB762 SD generic peripheral board connectors

B.2 Front and rear panel layout

The front and rear panels of the SD generic peripheral board assembly are shown in

Figure 37

and

Figure 38 .

The processor board panel (see

Section A.2 on page 40

) screws into the rear panel of the

SD generic peripheral board.

Figure 37.

Front panel assembly

Figure 38.

Rear panel assembly

Processor board panel

8149405 57/160


B.3 Connectors

The connectors that are fitted on the MB762 SD generic peripheral board are shown in

Table 22

,


.

Table 22.



NIM connector

HDD power connector

PCM audio output debug connector

Transport stream connector

Digital video output connector

JTAG EPLD debug connector (ByteBlaster)

PCM input connector

Smartcard 1 header connector


High density logic probe pattern connector

ATAPI connector

+3V3 I

2

C blaster connector

Ethernet MII connector

STEM EMI connector



CN18

CN19

CN20

CN21

CN23

CN24

CN26

CN29

CN30

CN10

CN11

CN12

CN14

CN15

CN16

CN17

Reference

Section B.3.5 on page 63















Table 23.



DVB-CI card slot connector

Dual smartcard interface connector

Ethernet RJ45 connector

Dual RS232 (1 male and 1 female) connectors

Table 24.

Rear panel external connectors


CN22

CN25

CN27

CN28

Reference






DC power socket connector




Left audio DAC phono connector


CN1

CN2

CN3

CN4

CN5

Reference






58/160 8149405


B.3.1

MB762 SD generic peripheral board connectors

Table 24.

Rear panel external connectors (continued)



Right audio DAC phono connector

TV output and AUX input SCART connectors

Left PCM audio phono connector

Right PCM audio phono connector

RF antenna and TV connector

CN6

CN7

CN8

CN9

IC11

Reference






DC power socket CN1

A +12V DC, 2.5 A input jack socket connector from RS electronics.

For DC use only.

Figure 39.

DC power socket

2

1

Viewed from rear panel

Table 25.

DC power socket pin allocation

Pin Description

1 GND

1.

Male jack connector pin.

Pin

2

(1)

+VIN

Description

8149405 59/160


B.3.2 LVDS debug type G connector CN2

A 68-pin connector for debug functions.

Figure 40.

LVDS debug type G connector

34


1

60/160

68 35


Table 26.

LVDS debug type G connector pin allocation


13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

21

22

23

24

25

17

18

19

20

LVDS_SPAREIN+

LVDS_EPLD_TDI+

LVDS_TRIGIN+

LVDS_EPLD_TMS+

LVDS_USERIN+

LVDS_EPLD_TCK+

LVDS_TMS+

LVDS_EPLD_TDO+

LVDS_USEROUT+

LVDS_EPLD_SPARE1+

LVDS_TRIGOUT+

LVDS_EPLD_SPARE2+

LVDS_TDO+

LVDS_EPLD_SPARE3+

GND

LVDSBUF_notEN

+5V_LVDS

LVDS_CLKOUT+

GND

LVDS_CLKIN+

GND

LVDS_TDI+

LVDS_MODE_SEL+

LVDS_notRESET+

47

48

49

50

43

44

45

46

39

40

41

42

35

36

37

38

55

56

57

58

59

51

52

53

54

Description

LVDS_SPAREIN-

LVDS_EPLD_TDI-

LVDS_TRIGIN-

LVDS_EPLD_TMS-

LVDS_USERIN-

LVDS_EPLD_TCK-

LVDS_TMS-

LVDS_EPLD_TDO-

LVDS_USEROUT-

LVDS_EPLD_SPARE1-

LVDS_TRIGOUT-

LVDS_EPLD_SPARE2-

LVDS_TDO-

LVDS_EPLD_SPARE3-

GND

+5V_LVDS

LVDS_CLKOUT-

GND

LVDS_CLKIN-

GND

LVDS_TDI-

LVDS_MODE_SEL-

LVDS_notRESET-

8149405


B.3.3


Table 26.

LVDS debug type G connector pin allocation (continued)


29

30

31

32

26

27

28

33

34

NC

LVDS_notTRST+

NC

GND

63

64

65

66

60

61

62

67

68

NC

LVDS_notTRST-

NC

GND

Video and audio phono connectors CN3 to CN6, CN8 and CN9

These phono connectors output video or audio signals. Pin 2 is always grounded and the other phono output pin 1 differs, depending on whether the phono is a video or an audio

connector. More information is given in Table 27 .

Figure 41.

Video and audio phono connectors

1

2


Table 27.

Video and audio phono connector pin allocation

Connector Pin 1

CN3 SPDIF phono

CN4 CVBS phono

CN5 left audio DAC phono

CN6 right audio DAC phono

CN8 left PCM audio phono

CN9 right PCM audio phono

SPDIFOUT

CVBS_DALC

LOUT_TV

ROUT_TV

AOUT_L

AOUT_R

GND

Pin 2

8149405 61/160


B.3.4


Dual SCART connectors CN7

SCART-TV supports upstream to TV and SCART-AUX supports downstream to VCR.

Figure 42.

Dual SCART connectors

20 18 16 14 12 10 8 6 4 2 Shield

19 17 15 13 11 9

20 18 16 14 12 10 8

7

6

5

4

3

2

1

SCART-TV

Shield

SCART-AUX

19 17 15 13 11 9 7 5 3 1


Table 28.

Dual SCART connector pin allocation


11

13

7

9

1

3

5

15

17

19

AUDIO_OUT_R

AUDIO_OUT_L

BLUE_GND

BLUE

GREEN_GND

GREEN

RED_GND

RED

VIDEO_GND

VIDEO_OUT

8

10

12

14

2

4

6

16

18

20

Description

AUDIO_IN_R

AUDIO_GND

AUDIO_IN_L

FUNCTION_SWITCH

Reserved 1

Reserved 2

COMM_GND

BLANKING

BLANKING_GND

VIDEO_IN

62/160 8149405


B.3.5


NIM connector CN10

One 84-pin connector. The connector is made up from two separate female connectors:

●

● a SAMTEC 28-pin a SAMTEC 54-pin

The two connectors are arranged, and the pins are numbered, as shown in Figure 43 .

Pins 15 and 57 are not available.

Figure 43.

NIM connector

42

15

16 14 1

84

RSM-127-02-xx

58

57

56 43

RSM-114-02-xx


Table 29.

NIM connector pin allocation

Pin Description

LNBRF

GNDA1

GNDA2

GNDA3

LNBSUPPLY5V

GNDA4

GNDA5

GNDA6

VCC3V3A

GNDA7

GNDA8

VCORE_A1

ANALOG5V

VTUNE32V

Key3

DISEQCRX

ADDRESS0

DISEQCTX

OP1

OP0

12

13

14

15

16

17

18

19

20

6

7

4

5

8

9

10

11

1

2

3

Pin

54

55

56

57

58

59

60

61

62

46

47

48

49

50

51

52

53

43

44

45

Description

Key1

VCORESEL_COM

VCORESEL_1V2

VCORESEL_1V0

RESERVED1

RESERVED2

SRX

DRX

ITX

QTX

ETX

VCORE_A2

CTX

OOB_RESERVED

Key4

RESERVED3

ADDRESS1

RESERVED4

RESERVED5

RESERVED6

8149405 63/160


Table 29.

NIM connector pin allocation (continued)


28

29

30

31

32

33

34

35

24

25

26

27

21

22

23

39

40

41

42

36

37

38

OP2

GNDD1

VCORE_D1

PACKETCLK

BYTECLKVALID

BYTECLK

ERROR

GNDD2

VCORE_D2

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

GNDD3

VCC3V3D

SCL

SDA notRESET

70

71

72

73

74

75

76

77

66

67

68

69

63

64

65

81

82

83

84

78

79

80

Description

RESERVED7

GNDD4

VCORE_D3

PACKETCLK_2

BYTECLKVALID_2

BYTECLK_2

ERROR_2

GNDD5

VCORE_D4

DATA7_2

DATA6_2

DATA5_2

DATA4_2

DATA3_2

DATA2_2

DATA1_2

DATA0_2

GNDD6

RESERVED8

SCL_2

SDA_2

Key2

64/160 8149405


B.3.6


HDD power connector CN11

An auxiliary 4-pin power connector is used to provide power to the HDD.

Figure 44.

HDD power connector

B.3.7

1 4


Table 30.

HDD power connector pin allocation


1

3

+12V

GND

2

4

GND

+5V

PCM audio output debug connector CN12

A 2 x 8-way, 16-pin connector provides PCM audio debug output.

Figure 45.

PCM audio output debug connector

15 1

Description

16 2


Table 31.

PCM audio output debug connector pin allocation


Even pins GND

1

3

TP27

PCMDACLRCLK

5

7

PCMDACSCLK

PCMDACDATA

9

11

13

15

Description

PCMDACPCMCLK

TP24

+5V

TP22

8149405 65/160


A 20-pin connector provides transport stream data output.

Figure 46.

Transport stream data connector

19 1

20 2


Table 32.

Transport stream data connector pin allocation


9

11

13

15

5

7

1

3

17

19

SDA notRST

DATA0

DATA2

DATA4

DATA5

DATA7

TSERROR

TSVALID

TSPACKETCLK

10

12

14

16

18

20

6

8

2

4

SCL

NC

DATA1

DATA3

NC

DATA6

NC

TSCLK

NC

AS1

Description

66/160 8149405


A 26-pin, surface mount, vertical male connector. Double row of 13 pins, 1.27 mm pitch with polarity.

Figure 47.

DVO connector

25

1

26

2


Table 33.

DVO connector pin allocation

Pin Description

9

11

13

15

5

7

1

3

17

19

21

23

25

DVODATA0

DVODATA1

DVODATA2

DVODATA3

GND

DVODATA4

GND

DVODATA5

DVODATA6

DVODATA7

GND

DVOHSYNC

DVOVSYNC

Pin

10

12

14

16

6

8

2

4

18

20

22

24

26

NC

GND

DVOCLK

GND

+3V3

I2CSCLDVO

NC

I2CSDADVO

+5V

Description

8149405 67/160


A 10-pin connector, provides a JTAG standard debug ByteBlaster interface. A 2 x 5-way vertical terminal strip, surface mount, shrouded pin header connector, with an alignment pin pitch of 2.54 mm.

Figure 48.

JTAG debug (ByteBlaster) connector

9 1

10 2


Table 34.

JTAG debug (ByteBlaster) connector pin allocation


1

3

5

7

9

DCCLK_TCK

CONFDONE_TD0 notCONFIG_TMS notSTATUS_NC

DATA0_TDI

8

10

2

4

6

GND1

VCC

NC_AUXTD0

NC_notTRST

GND2

B.3.11 PCM audio input connector CN17

A 2 x 8-way, 16-pin connector provides PCM audio input.

Figure 49.

PCM audio input connector

15 1

16 2


Table 35.

PCM audio input connector pin allocation


Even pins GND

1

3

TP77

PCMLRCLKIN

5

7

PCMSCLKIN

PCMDATAIN

9

11

13

15

Description

PCMCLK

I2CSCLPCMIN

TP43

I2CSDAPCMIN

68/160 8149405


B.3.12 Smartcard header data connectors CN18/CN19

Two 8-pin vertical post PTH header connectors provide smartcard data.

Figure 50.

Smartcard header data connector

8 1


Table 36.

Smartcard header data connector pin allocation

Pin Description

(1)

Pin

1

2

SC n DATAOUT

SC n DATAIN

3

4

SC

SC n n

EXTCLK

CLK

1.

Where n =0 for CN19 and n =1 for CN18.

7

8

5

6

Description

SC n RESET

SC n CMDVCC

SC n VPP

SC n DETECT

A 27-channel, Tektronix P6960 series high-density logic probe land pattern.

Figure 51.

P6960 series logic probe land pattern

A27 A1

B27 B1


Table 37.

P6960 series logic probe land pattern pin allocation

Pin row A Description Pin row B Description

7

8

5

6

9

3

4

1

2

BUFF_DVBDATA3

BUFF_DVBDATA5

GND

BUFF_DVBDATA7

BUFF_DVBADDR10

GND

TP110 (CK1+)

TP111 (CK1-)

GND

7

8

5

6

9

3

4

1

2

GND

BUFF_DVBDATA4

BUFF_DVBDATA6

GND notDVBCE notDVBIOOE

GND

BUFF_DVBADDR11 notDVBIORD

8149405 69/160


Table 37.

P6960 series logic probe land pattern pin allocation (continued)


17

18

19

20

21

22

23

24

25

26

27

13

14

15

16

10

11

12

BUFF_DVBADDR9

BUFF_DVBADDR8

GND

BUFF_DVBADDR14 notDVBINTR

GND

BUFF_DVBADDR7 notDVBRESET

GND notDVBWAIT

BUFF_DVBADDR4

GND

BUFF_DVBADDR3 notDVBREG

GND

BUFF_DVBADDR0

BUFF_DVBDATA1

GND

17

18

19

20

21

22

23

24

25

26

27

13

14

15

16

10

11

12

GND notDVBIOWR

BUFF_DVBADDR13

GND notDVBIOWE

BUFF_DVBADDR12

GND

BUFF_DVBADDR6

BUFF_DVBADDR5

GND

TP116 (CK2-)

TP117 (CK2+)

GND

BUFF_DVBADDR2

BUFF_DVBADDR1

GND

BUFF_DVBDATA0

BUFF_DVBDATA2

70/160 8149405


B.3.14 ATAPI connector CN21

A 2 x 20-way, 40-pin connector provides ATAPI data.

Figure 52.

ATAPI connector

39 1

40 2

Viewed from above PCB notRESET

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

GND

DMARQ notDIOW notDIOR

IORDY notDMACK

INTRQ

DA1

DA0 notCS0 notDASP

Table 38.

ATAPI connector pin allocation

Pin Description

23

25

27

29

15

17

19

21

31

33

35

37

39

11

13

7

9

1

3

5

Pin

24

26

28

30

16

18

20

22

32

34

36

38

40

8

10

12

14

2

4

6

GND

DD8

DD9

DD10

DD11

DD12

DD13

DD14

DD15

Reserved

Description

GND

SPSYNC_CSEL

GND notIOCS16 notPDIAG

DA2 notCS1

GND

8149405 71/160


B.3.15 DVB-CI connector CN22

A 68-pin DVB-CI connector. Single DVB-CI connector, supports type I, II cards. Single port, right angle, top mount, through hole, 68-pin, with eject (right side).

Figure 53.

DVB-CI connector

34 1

68 35


A8

A13

A14 notWE notIREQ

VCC1

VPP1

TS_IN_VAL

TS_IN_CLK

A12

A7

A6

A5

NC

DATA3

DATA4

DATA5

DATA6

DATA7 notCE1

NC notOE

A11

A9

Table 39.

DVB-CI connector pin allocation

Pin Description

21

22

23

24

18

19

20

12

13

14

15

16

17

6

7

8

9

10

11

1

2

3

4

5

Pin

55

56

57

58

52

53

54

46

47

48

49

50

51

40

41

42

43

44

45

35

36

37

38

39

Description

NC notCD1

TS_OUT_DATA3

TS_OUT_DATA4

TS_OUT_DATA5

TS_OUT_DATA6

TS_OUT_DATA7 notCE2

NC notIORD notIOWR

TS_IN_STRT

TS_IN_DATA0

TS_IN_DATA1

TS_IN_DATA2

TS_IN_DATA3

VCC0

VPP0

TS_IN_DATA4

TS_IN_DATA5

TS_IN_DATA6

TS_IN_DATA7

TS_OUT_CLK

CARD_RESET

72/160 8149405


Table 39.

DVB-CI connector pin allocation (continued)

Pin

28

29

30

31

25

26

27

32

33

34

A4

A3

A2

A1

A0

DATA0

DATA1

DATA2 notIOIS16

NC

Description Pin

62

63

64

65

59

60

61

66

67

68

Description notWAIT

NC notREG

TS_OUT_VAL

TS_IN_STRT

TS_OUT_DATA0

TS_OUT_DATA1

TS_OUT_DATA2 notCD2

NC

An 8-pin header provides I

2

C interfaces.

Figure 54.

+3V3 I

2

C blaster connector

4

8

1

5


Table 40.

I

2

C connector pin allocation

Pin Description

1

2

3


VCC

USER1

(1)

4 SDA

1.

Connected to NIM reset.

Pin

5

6

7

8

USER2

(1)

SCL

USER3

(1)

GND

Description

8149405 73/160


A 40-pin connector provides Ethernet data output.

Figure 55.

Ethernet MII data connector

39 1

40 2


Table 41.

Ethernet MII data connector pin allocation


GND GND

25

27

29

31

17

19

21

23

33

35

37

39

9

11

13

15

5

7

1

3

+3V3

MII_COL

MII_TXD0

MII_TXD2

GMII_TXD4 (NC)

GMII_TXD6 (NC)

GND

MII_TXCLK

MII_RXCLK

MII_RX_DV

MII_RXD0

MII_RXD2

GMII_RXD4 (NC)

GMII_RXD6 (NC)

GND

MII_MDIO notINT

GMII_MODE

26

28

30

32

18

20

22

24

34

36

38

40

10

12

14

16

6

8

2

4

+5V

Description

MII_CRS

MII_TXD1

MII_TXD3

GMII_TXD5 (NC)

GMII_TXD7 (NC)

MII_TX_EN

GND

MII_RX_ER

GND

MII_RXD1

MII_RXD3

GMII_RXD5 (NC)

GMII_RXD7 (NC)

MII_MDC notRESET

RMII_MODE

GND

74/160 8149405


B.3.18 Smartcard sockets CN25

Two 10-pin smartcard sockets. Dual smartcard connector, friction contacts, through hole, normally closed detection switch.

Figure 56.

Smartcard socket

15

5

1

11

4

14 9 10

18

19 20

8

Indicates pins 11-20 of bottom smartcard

(smartcard 1)

Top smartcard viewed from above PCB

Table 42.

Smartcard socket pin allocation

Pin Description

9

10

7

8

5

6

3

4

1

2

GNDC

SC0VPP

IO

AUX2

VCC

RST

CLK

AUX1

GNDC

PRES/notPRES

Pin

15

16

17

18

11

12

13

14

19

20

Description

GNDC

SC1VPP

IO

AUX2

VCC

RST

CLK

AUX1

GNDC

PRES/notPRES

8149405 75/160


B.3.19 STEM EMI CN26

A 140-pin surface mount board to board connector plug.

Figure 57.

STEM EMI connector


140 71

76/160

70 1


Table 43.

STEM EMI connector pin allocation


12

13

14

15

10

11

8

9

6

7

4

5

1

2

3

21

22

23

24

25

16

17

18

19

20 notBS 71

SDRAM_CLK 72

SDRAM_CLKEN 73

MEZZ_PRESENT0

GND

DACK2

DACK0

74

75

76

77

DRAK0

DREQ0

GND

MEMWAIT

+3V3 (VCC)

MEMGRANTED notINTR0

GND

82

83

84

85

78

79

80

81

FLASH_CLK

GND notWR

GND notCS0

GND

A25

A23

+3V3 (VCC)

A21

91

92

93

94

95

86

87

88

89

90

Description notFRAME notCAS notRESET

MEZZ_PRESENT1

GND

DACK3

DACK1

DRAK1

DREQ1

GND

AUX_CLK

+3V3 (VCC)

MEMREQ notINTR1

GND

FBAA

GND notOE

GND notCS1

GND

A24

A22

+3V3 (VCC)

A20

8149405


47

48

49

50

51

52

41

42

43

44

45

46

56

57

58

59

60

53

54

55

33

34

35

36

37

38

39

40

29

30

31

32

26

27

28 notBE1

GND

D31 (NC)

D29 (NC)

GND

D27 (NC)

D25 (NC)

GND

D23 (NC)

D21 (NC)

GND

D19 (NC)

D17 (NC)

GND

D15

D13

GND

D11

D9

GND

A19

GND

A17

A15

+3V3 (VCC)

A13

A11

GND

A9

A7

+3V3 (VCC)

A5

A3

GND

A1_notBE3

Table 43.

STEM EMI connector pin allocation (continued)

Pin Description Pin notBE0

GND

D30 (NC)

D28 (NC)

+5V VCC

D26 (NC)

D24 (NC)

GND

D22 (NC)

D20 (NC)

+5V VCC

D18 (NC)

D16 (NC)

GND

D14

D12

+5V VCC

D10

D8

GND

A18

GND

A16

A14

+3V3 (VCC)

A12

A10

GND

A8

A6

+3V3 (VCC)

A4

A2

GND

A0_notBE2

Description

117

118

119

120

121

122

111

112

113

114

115

116

123

124

125

126

127

128

129

130

103

104

105

106

107

108

109

110

96

97

98

99

100

101

102

8149405 77/160


Table 43.


Pin

64

65

66

67

61

62

63

68

69

70

D7

D5

GND

D3

D1

GND

MPX_CLK

GND

+12 V (VCC)

Description Pin

131

132

133

134

135

136

137

138

139

140

Description

D6

D4

+5V VCC

D2

D0

GND

ALE_notRAS

GND

+12 V (VCC)

An RJ45 connector provides a 10/100 BaseT Ethernet physical layer (PHY) interface.

Figure 58.

Ethernet connector

Ethernet

LED2 LED1

78/160


Table 44.

Ethernet connector pin allocation


1

2

3

4

5

6

MDI_2CT

+2V5_GMII

MDI_2-

MDIC_N

MDI_2+

MDIC_P

MDI_1+

MDIB_P

MDI_1-

MDIB_N

MDI_1CT

+2V5_GMII

7

8

9

10

11

12

MDI_3CT

+2V5_GMII

MDI_3+

MDID_P

MDI_3-

MDID_N

MDI_0-

MDIA_N

MDI_0+

MDIA_P

MDI_0CT

+2V5_GMII

Description

LED1 indicates Ethernet activity. LED2 indicates 100Base Tx Ethernet protocol.

8149405


●

●

●

●

LED output functions are user selectable. Up to two LED functions at one time. The LED output functions are: activity full duplex

10BASE T or 100BASE TX Ethernet transmit protocol transmit, receive

Figure 59.

RS232 connectors

1 5

COM1

Female

5

6 9

1

COM0

Male

9 6

Table 45.

RS232 connector pin allocation

Pin Description

1

2

3

4

5

NC

RX

TX

NC

GND

Pin

6

7

8

9

NC

RTS

CTS

NC


Description

8149405 79/160


B.3.22 EMI and PIO peripheral to processor board connectors CN29/CN30

Connection between the SD generic peripheral board and processor board is by two

Samtec 2 x 120-pin connectors.

These connectors interface directly with two Samtec 2 x 128-pin connectors on the bottom surface of the processor board.

Connector CN29 on the peripheral board connects to either CN11 on the MB676 or CN8 on the MB704.


Figure 60.

SD generic peripheral board to processor board connector

80/160

2

1

120

119


.

Table 46.

Peripheral board to processor board EMI connector CN29


23

25

27

29

15

17

19

21

31

33

35

11

13

7

9

1

3

5

VIDGND0

VDAC_XOUT

VIDGND1

VDAC_UOUT

VIDGND2

NC

VIDGND3

VDAC_WOUT

VIDGND4

VDAC_VOUT

VIDGND5

FMIADDR24

FMIADDR23_DVOCLK

FMIADDR21_DVODATA1

FMIADDR3

FMIADDR7 notFMICSC

FMIADDR6

24

26

28

30

16

18

20

22

32

34

36

8

10

12

14

2

4

6

AUDGND0

ADAC_VBG

AUDGND1

ADAC_AOL

AUDGND2

NC

AUDGND3

ADAC_AOR

AUDGND4

SPDIF

AUDGND5

FMIADDR25

FMIADDR5

FMIADDR22_DVODATA0

FMIADDR20_DVODATA2 notFMICSD

FMIADDR17_DVODATA4

FMIADDR8

8149405


Table 46.

Peripheral board to processor board EMI connector CN29 (continued)


37

77

79

81

83

85

87

65

67

69

71

73

75

53

55

57

59

61

63

45

47

49

51

39

41

43

89

91

93

95

97 notFMICSB notFMICSA_SPICS

FMIADDR4

FMIADDR10

FMIADDR14 notFMIBE1

FMIADDR13

FMINANDWAIT

FMIADDR12

FMIDATA1

FMIRDnotWR

FMIDATA7

FMIDATA6

FMIDATA13_DVBCICD1

FMIDATA3

FMIWAIT

FMIDATA2

FMIDATA10

FMIDATA9

FMIDATA0

TS0INDATA7

TS0INBITORBYTECLK

TS0INDATA5

TS0INERROR

TS0INDATA3

TS0INDATA1

TS0OUTERROR_SC0CLK_

SC0FSCLK0

TS0OUTBITORBYTECLK_

SC0DATAOUT_SSC0DATAINOUT

TS0OUTDATA4_SC0DETECT

TS0OUTDATA6_SC0CMDVCC_

ASC0CTS_SC0notSETVCC

TS0OUTDATA0_SC1POWER_

TV0DENC_ASC1CTS

38

78

80

82

84

86

88

66

68

70

72

74

76

54

56

58

60

62

64

46

48

50

52

40

42

44

90

92

94

96

98 notFMIBAA_DVBCIIORD_

FMIRDnotWR2

FMIADDR18

FMIADDR19_DVODATA3

FMIADDR9

FMIADDR11 notFMIBE0_DVBCIIOWR

FMIADDR2

FMIADDR15

FMIADDR16_DVODATA5 notFMIOE

FMIDATA14_DVBCI2

FMIDATA15_DVBCI1

FMIDATA12_DVBCIRESET

FMIDATA5

FMIDATA4 notFMILBA

FMIDATA11

FMIADDR1

FMIDATA8

NANDRBN2

TS0INDATA6

TS0INPACKETCLK

TS0INBITORBYTECLKVALID

TS0INDATA4

TS0INDATA0

TS0INDATA2

TS0OUTPACKETCLK_

SC0DATAIN_SSC1MRSTDINOUT

TS0OUTBITORBYTECLKVALID_

SC0EXTCLK_IRBPPMOUT

TS0OUTDATA5_SC0DIR_

SC0notSETVPP

TS0OUTDATA7_SC0RESET_

ASC0RTS


VSYNC_ASC1RTS

8149405 81/160


Table 46.



99

101

103

105

107

109

111

113

115

117

119

TS0OUTDATA2_SC1CLK_HSYNC

NANDSCN2

DCU_TCK

DCU_TDO

DCU_notTRST

AUX_TMS

DCU_notASEBRK

DCU_TRIGGERIN

SPARE4

SPARE6

AUX_TDUP

100

102

104

106

108

110

112

114

116

118

120

TS0OUTDATA3_SC1DATAINOUT_

PIXCLK

NANDSCN3 notMODULERESETIN

DCU_TDI

DCU_TMS

AUX_TCK

DCU_TRIGGEROUT

DCU_DEBUGMODESEL

SPARE5

SPARE7

AUX_TDDOWN

.

Table 47.

Peripheral board to processor board PIO connector CN30


23

25

27

29

31

33

35

37

39

11

13

15

17

19

21

1

3

5

7

9

+5V

NC

+3V3

NC

+12V

NC

SC0DATAOUT

SC0EXTCLK

SPI_DATAIN

24

26

28

30

32

34

36

38

40

12

14

16

18

20

22

6

8

10

2

4

+5V

NC

+3V3

NC

SC0DATAIN

SC0CLK

PCMLRCLKOUT

82/160 8149405


Table 47.

Peripheral board to processor board PIO connector CN30 (continued)


47

49

51

53

55

41

43

45

57

59

61

63

65

67

69

71

85

87

89

91

93

95

73

75

77

79

81

83

97

99

101

SPI_DATAOUT

SPI_CLK

PCMLRCLKIN

ASC3RXD

SC0VPP

ASC3TXD

PCMDATAIN

SC0DETECT

SCART_2_BILED2

DVODATA7

OSD_ACTIVE_DVOCLK

DVODATA6

SCART_1_BILED1

IRB_OUT

SC1DATAOUT

IRB_IN

CLK27

INTUP0

SSC0_SCLKINOUT

GPIO_DVBCI_2

SC1EXTCLK

INTUP1

AUXCLKOUT

FMIFLASHCLK

SC1VPP

INTUP2

HSYNCEN

DVBCI_CD1

SSC1CLK

ASC3CTS

ASC3RTS

86

88

90

92

94

96

74

76

78

80

82

84

98

100

102

48

50

52

54

56

42

44

46

58

60

62

64

66

68

70

72

SC0RESET

FDMAREQ1

PCMDATAOUT

SC0CMDVCC

FDMAREQ0

PCMSCLKOUT

FPRESET

SC1CLK

SEVEN_SEG_DISPLAY4_

DVODATA0

SEVEN_SEG_DISPLAY3_

DVODATA1

ASC2CTS

SEVEN_SEG_DISPLAY2_

DVODATA2

ASC2RTS

SEVEN_SEG_DISPLAY1_

DVODATA3

ASC2RXD

SEVEN_SEG_DISPLAY0_

DVODATA4

ASC2TXD

SC1DETECT

SC1DATAIN

HSYNC

DMAREQ1

SC1RESET

LED_DRIVE

SC1CMDVCC

VSYNC

KEY_CTRL

VSYNCEN

DMAREQ0 notRSTOUT_LOCAL_RESET

PCMMCLK

SPI_CS_YC3

8149405 83/160


Table 47.



103

105

107

109

111

113

115

117

119

PCMSCLKIN

YC2

DVBCI_RESET

INTDOWN0

NANDCSN1

NANDRBN1

+5V

104

106

108

110

112

114

116

118

120

SSC0_MTSR_DINOUT

SSC1DATAINOUT

DVBCI_BUSGNT

DVBCI_BUSREQ

INTDOWN1

NANDRBN3

+5V

B.3.23 RF modulator connector IC11

This BTSC RF modulator is the interface between NTSC-M, PAL-M system modulator and a television. The RF modulator has two female connectors.

Figure 61.

RF modulator connector

GND GND

1 2


Table 48.

RF modulator connector pin allocation


1 RF_OUTPUT 2

Description

ANTENNA_IN

84/160 8149405

STi5197-MBoard, STi5189/97-MB MB829 SD modular validation peripheral board connectors

Appendix C MB829 SD modular validation peripheral board connectors

The connector placements on the SD modular validation peripheral board are shown in

Figure 62

.

Figure 62.

SD modular validation peripheral board top assembly connector layout

Dual smartcard connector

ATAPI header

STEM EMI connector

PCMCIA card connector

RJ45 Ethernet connector

ATX power connector

PCM header

DVO header

PCM audio debug

SW6

R302

TP164

R305

IC45

TP165

C304

TP137

C257

C259

LD14

R306

TP166

R307

C264

C271

R279

R281

R283

LD16

LD17

R310

TR8

R284

TR9 C279

R313

TR10

R285

R314

R315

H15

R263

C270

C274

R264

R266

R267

R269

R271

C278

R273

R275

H13

C249

R256

CN27

IC39 IC38

TP116 C218

IC30

C219

R175

C197

TR4

R218

IC40

TR5

IC33

TP79

TP80

H11

TP81

TP64

R152

C178

TP62 TP61 TP59 TP60

CN15

TP63 TP38

R151

TP39

R153

R154

IC24

TP65

R157

H7

C1

CN14

C91

C139 C93

L10

R88

R89

R90

C90

CN13

C92

TP4

TP1

H1

C2

L1

C11

C3

R2

TP5

IC1

R6

R7

TP6

CN1

C14

H2

CN2

C15

CN16

R97 C17 CN3

C227

R224

C231

IC34

IC2

J19

TP160

C285

C283

C286

R286

R287

R288

C288

R292 R293

R296

C292 IC51

C295

C298

R298

C299

C300

C301

R299

LD12

R300

LD13

C302

IC44

R247

R248

R249

C248 R250

TP132 TP131

TP163

L22

C303

R257

IC41

C250

TR6

R259

C235

C252

TP134 TP135

TR7

TP117

C255

C256

C258

C260

TP136

J14

TP119

R234

TP118

R235

C261

C263

C262

C265

C267

C266

R262

C269

C268

C272

C273 C275

R265

R268

R270

C276

C277

R272

R274

R278

R280

R282

H14

TP159

TP122

TP123

TP124

TP125

TP126

TP127

TP128

TP130

C242

C243

R239

C244

R243

R177

CN17

D1

C21 CN4

R8

CN5

J18

CN18

TP120 TP82

R178

R179

C238 CN19

CN6

L11

C106

C25

TP129

C241

R236

TP83

TP121

R237 TP84

R238

TP85

R181

R182

R183

TP86

TP87

TP89

J11

R186

TP133

C200

R202

R180

R184

TP88

TP90

R185

CN20

R100

CN21

R103

CN22

R105

C108

R101

R102

R104

TP25

L12

C27

TP40

R106

R107

CN23

CN7

CN8

R9

TR1

C28

C30

R10

R11

TR2

R12

C29

CN9

IC35

J12

TP91

TP92

TP93

TP94

TP96

TP98

TP99

TP100

R188

TP95

R189

TP97

TP101

R190

R191

TP102

TP103

R192

H12

R161

H8

C155

C156

C157

R127

R128

R159

R160

R162

J9

R130

R110

C112

C113

C114

C115

IC4

C37

R27

TR3

R14

R16

R19

R20

C34

R21

R22

C35

TP8 R23

TP9 R26

C36

R24

R25

C38

TP10

R28

R30

TP11

TP12

TP14

TP15

TP16

TP17

TP18

R15

R18

H3

R17

IC3

IC5

IC6

R29 C39

IC7

TP13

R32

R33

R31

R34

C40

R35

R37

R36

R38

IC8

C41

C42

C43

L3

IC9

C44

LD1

C45

H4

R197

R193

R194

C204

C209

R195

R196

C210

R201

TP114

TP115

R199

R200

C211

C212

C213

C214

TP78

R165

C182

TP73

IC22

TP72 TP68 TP67 TP66 TP70 TP71 TP69 TP52

C161

R137

R138

R139

R140

TP74

C183

TP46 TP45 TP43 TP44 TP42 TP30

TP47 TP51 TP50 TP49 TP48

J6

TP56

TP55

TP54

TP53

TP75

C186

R163

TP76

TP77

H9 C162

C163

C216

J13

TP168

TP167 R169

L16

C190

J7

IC28

R170

R172

C170

R146

R147

C173

H10

C175

TP58

R115 R114 R113 R112 R111

C119

C120

C121

J2

SW1

SW2

SW3

SW4

CN11

TP19 TP7

SW5

IC20

C124

TP20

R58

C49

R65

C50

J3

R66

C52

R68

C51

C54

R70

C55

J4

R72 C57 C58

CN24

C166

C168

L14

TP57

TP37

C60 CN25

TP32 TP33 TP31

C64

L5 L6

LD10

R117

TP34 TP35

C65

R118

C66

TP36 TP24 TP23

R75

C67

C69

C73 C70

C75

C72

C76

C68

C71

C74 R120 R119 R121 CN26

C137

R77

R78

R81

C81

TP22

C77

R80

TP21

C78

C138

C88 H6

C48

PCM audio output phono

Audio DAC output phono

CVBS output phono

RBG video output phonos

SPDIF output phono


STMC2 LVDS connector

EPLD ByteBlaster connector

Dual RS232 connector

Transport stream headers

NIM connector

8149405 85/160

MB829 SD modular validation peripheral board connectors STi5197-MBoard, STi5189/97-MB

C.2 Connectors

The connectors that are fitted on the MB829 SD modular validation peripheral board are

shown in Table 49

,

Table 50

and Table 51

.

Table 49.



JTAG EPLD debug connector (ByteBlaster)

PCM audio debug connector

Digital video output connector

PCM header connector


Debug transport stream connector

Control and data transport stream connector

NIM2.1 connector

ATX power connector



ATAPI connector

STEM EMI connector


I

2

C blaster connector


Ethernet MII connector

Table 50.



CN25

CN26

CN27

CN28

CN29

CN31

CN11

CN13

CN14

CN15

CN16

CN23

CN24

CN32

CN33

CN35

CN36

CN37

Reference

Section C.2.3 on page 89


















Dual smartcard connector

DVB-CI card slot connector

Ethernet RJ45 connector


CN30

CN34

CN38

Reference




86/160 8149405


C.2.1

MB829 SD modular validation peripheral board connectors

Table 51.

Rear panel external connectors


Left PCM audio phono connector

Right PCM audio phono connector

Left audio DAC phono connector

Right audio DAC phono connector


Red video output phono

Blue video output phono

Green video output phono



Dual RS232 (1 male and 1 female) connectors


CN1

CN2

CN3

CN4

CN5

CN6

CN7

CN8

CN9

CN10

CN12

Reference












Video and audio phono connectors CN1 to CN9

These phono connectors output video or audio signals. Pin 2 is always grounded and the other phono output pin 1 differs, depending on whether the phono is a video or an audio

connector. More information is given in Table 52 .

Figure 63.

Video and audio phono connectors

1

2


Table 52.

Video and audio phono connector pin allocation

Connector Pin 1

CN1 left PCM audio phono

CN2 right PCM audio phono

CN3 left audio DAC phono

CN4 right audio DAC phono

CN5 CVBS phono

CN6 Red video output phono

CN7 Blue video output phono

CN8 Green video output phono

CN9 SPDIF phono

AOUT_L

AOUT_R

LOUT_TV

ROUT_TV

CVBS_DALC

OUT1

OUT2

OUT3

SPDIFOUT

GND

Pin 2

8149405 87/160


C.2.2 LVDS debug type G connector CN10

A 68-pin connector for debug functions.

Figure 64.

LVDS debug type G connector

34


1

88/160

68 35


Table 53.

LVDS debug type G connector pin allocation


13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

21

22

23

24

25

17

18

19

20

LVDS_SPAREIN+

LVDS_EPLD_TDI+

LVDS_TRIGIN+

LVDS_EPLD_TMS+

LVDS_USERIN+

LVDS_EPLD_TCK+

LVDS_TMS+

LVDS_EPLD_TDO+

LVDS_USEROUT+

LVDS_EPLD_SPARE1+

LVDS_TRIGOUT+

LVDS_EPLD_SPARE2+

LVDS_TDO+

LVDS_EPLD_SPARE3+

GND

LVDSBUF_notEN

+5V_LVDS

LVDS_CLKOUT+

GND

LVDS_CLKIN+

GND

LVDS_TDI+

LVDS_MODE_SEL+

LVDS_notRESET+

47

48

49

50

43

44

45

46

39

40

41

42

35

36

37

38

55

56

57

58

59

51

52

53

54

Description

LVDS_SPAREIN-

LVDS_EPLD_TDI-

LVDS_TRIGIN-

LVDS_EPLD_TMS-

LVDS_USERIN-

LVDS_EPLD_TCK-

LVDS_TMS-

LVDS_EPLD_TDO-

LVDS_USEROUT-

LVDS_EPLD_SPARE1-

LVDS_TRIGOUT-

LVDS_EPLD_SPARE2-

LVDS_TDO-

LVDS_EPLD_SPARE3-

GND

+5V_LVDS

LVDS_CLKOUT-

GND

LVDS_CLKIN-

GND

LVDS_TDI-

LVDS_MODE_SEL-

LVDS_notRESET-

8149405


Table 53.

LVDS debug type G connector pin allocation (continued)


29

30

31

32

26

27

28

33

34

NC

LVDS_notTRST+

NC

GND

63

64

65

66

60

61

62

67

68

NC

LVDS_notTRST-

NC

GND

A 10-pin connector, provides a JTAG standard debug ByteBlaster interface. A 2 x 5-way vertical terminal strip, surface mount, shrouded pin header connector, with an alignment pin pitch of 2.54 mm.

Figure 65.

JTAG debug (ByteBlaster) connector

9 1

10 2


Table 54.

JTAG debug (ByteBlaster) connector pin allocation


5

7

1

3

9

DCCLK_TCK

CONFDONE_TD0 notCONFIG_TMS notSTATUS_NC

DATA0_TDI

6

8

2

4

10

GND1

VCC

NC_AUXTD0

NC_notTRST

GND2

8149405 89/160


C.2.5

Figure 66.

RS232 connectors

1 5

COM1

Female

5

6 9

1

COM0

Male

9 6


Table 55.

RS232 connector pin allocation

Pin Description

1

2

3

4

5

NC

RX

TX

NC

GND

Pin

6

7

8

9

NC

RTS

CTS

NC

PCM audio output debug connector CN13

A 2 x 8-way, 16-pin connector provides PCM audio debug output.

Figure 67.

PCM audio output debug connector

15 1

Description

90/160

16 2


Table 56.

PCM audio output debug connector pin allocation


Even pins GND

1

3

TP27

PCMDACLRCLK

5

7

PCMDACSCLK

PCMDACDATA

9

11

13

15

Description

PCMDACPCMCLK

TP24

+5V

TP22

8149405


A 26-pin, surface mount, vertical male connector. Double row of 13 pins, 1.27 mm pitch with polarity.

Figure 68.

DVO connector

25

1

26

2


Table 57.

DVO connector pin allocation

Pin Description

9

11

13

15

5

7

1

3

17

19

21

23

25

DVODATA0

DVODATA1

DVODATA2

DVODATA3

GND

DVODATA4

GND

DVODATA5

DVODATA6

DVODATA7

GND

DVOHSYNC

DVOVSYNC

Pin

10

12

14

16

6

8

2

4

18

20

22

24

26

NC

GND

DVOCLK

GND

+3V3

I2CSCLDVO

NC

I2CSDADVO

+5V

Description

8149405 91/160


C.2.7 PCM audio input connector CN15

A 2 x 8-way, 16-pin connector provides PCM audio input.

Figure 69.

PCM audio input connector

15 1


C.2.8

16 2


Table 58.

PCM audio input connector pin allocation


Even pins GND

1 TP77

3

5

7

PCMLRCLKIN

PCMSCLKIN

PCMDATAIN

9

11

13

15

Description

PCMCLK

I2CSCLPCMIN

TP43

I2CSDAPCMIN

EMI and PIO peripheral to processor board connectors CN16/CN23

Connection between the SD modular validation peripheral board and processor board is by two Samtec 2 x 120-pin connectors.

These connectors interface directly with two Samtec 2 x 128-pin connectors on the bottom surface of the processor board.



Figure 70.

SD modular validation peripheral board to processor board connector

2

1

120

119


92/160 8149405


.

Table 59.

Peripheral board to processor board PIO connector CN16


47

49

51

53

55

35

37

39

41

43

45

23

25

27

29

31

33

15

17

19

21

11

13

7

9

1

3

5

57

59

61

63

65

+5V

NC

+3V3

NC

+12V

NC

SC0DATAOUT

SC0EXTCLK

SPI_DATAIN

SPI_DATAOUT

SPI_CLK

PCMLRCLKIN

ASC3RXD

SC0VPP

ASC3TXD

PCMDATAIN

SC0DETECT

SCART_2_BILED2

DVODATA7

OSD_ACTIVE_DVOCLK

DVODATA6

SCART_1_BILED1

58

60

62

64

66

+5V

NC

+3V3

NC

SC0DATAIN

SC0CLK

PCMLRCLKOUT

SC0RESET

FDMAREQ1

PCMDATAOUT

SC0CMDVCC

FDMAREQ0

PCMSCLKOUT

FPRESET

SC1CLK

SEVEN_SEG_DISPLAY4_

DVODATA0

SEVEN_SEG_DISPLAY3_

DVODATA1

ASC2CTS

SEVEN_SEG_DISPLAY2_

DVODATA2

ASC2RTS

48

50

52

54

56

36

38

40

42

44

46

24

26

28

30

32

34

16

18

20

22

8

10

12

14

2

4

6

8149405 93/160


Table 59.



67

69

71

93

95

97

99

101

103

81

83

85

87

89

91

73

75

77

79

105

107

109

111

113

115

117

119

IRB_OUT

SC1DATAOUT

IRB_IN

CLK27

INTUP0

SSC0_SCLKINOUT

GPIO_DVBCI_2

SC1EXTCLK

INTUP1

AUXCLKOUT

FMIFLASHCLK

SC1VPP

INTUP2

HSYNCEN

DVBCI_CD1

SSC1CLK

ASC3CTS

ASC3RTS

PCMSCLKIN

YC2

DVBCI_RESET

INTDOWN0

NANDCSN1

NANDRBN1

+5V

68

70

72

94

96

98

100

102

104

82

84

86

88

90

92

74

76

78

80

106

108

110

112

114

116

118

120

SEVEN_SEG_DISPLAY1_

DVODATA3

ASC2RXD

SEVEN_SEG_DISPLAY0_

DVODATA4

ASC2TXD

SC1DETECT

SC1DATAIN

HSYNC

DMAREQ1

SC1RESET

LED_DRIVE

SC1CMDVCC

VSYNC

KEY_CTRL

VSYNCEN

DMAREQ0 notRSTOUT_LOCAL_RESET

PCMMCLK

SPI_CS_YC3

SSC0_MTSR_DINOUT

SSC1DATAINOUT

DVBCI_BUSGNT

DVBCI_BUSREQ

INTDOWN1

NANDRBN3

+5V

.

Table 60.

Peripheral board to processor board EMI connector CN23


5

7

1

3

VIDGND0

VDAC_XOUT

VIDGND1

VDAC_UOUT

6

8

2

4

AUDGND0

ADAC_VBG

AUDGND1

ADAC_AOL

94/160 8149405


Table 60.



23

25

27

29

31

33

35

15

17

19

21

9

11

13

37

49

51

53

55

57

59

39

41

43

45

47

67

69

71

73

75

61

63

65

VIDGND2

NC

VIDGND3

VDAC_WOUT

VIDGND4

VDAC_VOUT

VIDGND5

FMIADDR24

FMIADDR23_DVOCLK

FMIADDR21_DVODATA1

FMIADDR3

FMIADDR7 notFMICSC

FMIADDR6 notFMICSB notFMICSA_SPICS

FMIADDR4

FMIADDR10

FMIADDR14 notFMIBE1

FMIADDR13

FMINANDWAIT

FMIADDR12

FMIDATA1

FMIRDnotWR

FMIDATA7

FMIDATA6

FMIDATA13_DVBCICD1

FMIDATA3

FMIWAIT

FMIDATA2

FMIDATA10

FMIDATA9

FMIDATA0

50

52

54

56

58

60

40

42

44

46

48

68

70

72

74

76

62

64

66

24

26

28

30

32

34

36

16

18

20

22

10

12

14

38

AUDGND2

NC

AUDGND3

ADAC_AOR

AUDGND4

SPDIF

AUDGND5

FMIADDR25

FMIADDR5

FMIADDR22_DVODATA0

FMIADDR20_DVODATA2 notFMICSD

FMIADDR17_DVODATA4

FMIADDR8 notFMIBAA_DVBCIIORD_

FMIRDnotWR2

FMIADDR18

FMIADDR19_DVODATA3

FMIADDR9

FMIADDR11 notFMIBE0_DVBCIIOWR

FMIADDR2

FMIADDR15

FMIADDR16_DVODATA5 notFMIOE

FMIDATA14_DVBCI2

FMIDATA15_DVBCI1

FMIDATA12_DVBCIRESET

FMIDATA5

FMIDATA4 notFMILBA

FMIDATA11

FMIADDR1

FMIDATA8

NANDRBN2

8149405 95/160


Table 60.



83

85

87

77

79

81

89

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

TS0INDATA7

TS0INBITORBYTECLK

TS0INDATA5

TS0INERROR

TS0INDATA3

TS0INDATA1

TS0OUTERROR_SC0CLK_

SC0FSCLK0

TS0OUTBITORBYTECLK_

SC0DATAOUT_SSC0DATAINOUT

TS0OUTDATA4_SC0DETECT

TS0OUTDATA6_SC0CMDVCC_

ASC0CTS_SC0notSETVCC

TS0OUTDATA0_SC1POWER_

TV0DENC_ASC1CTS

TS0OUTDATA2_SC1CLK_HSYNC

NANDSCN2

DCU_TCK

DCU_TDO

DCU_notTRST

AUX_TMS

DCU_notASEBRK

DCU_TRIGGERIN

SPARE4

SPARE6

AUX_TDUP

102

104

106

108

110

112

114

116

118

120

84

86

88

78

80

82

90

92

94

96

98

100

TS0INDATA6

TS0INPACKETCLK

TS0INBITORBYTECLKVALID

TS0INDATA4

TS0INDATA0

TS0INDATA2

TS0OUTPACKETCLK_

SC0DATAIN_SSC1MRSTDINOUT

TS0OUTBITORBYTECLKVALID_

SC0EXTCLK_IRBPPMOUT

TS0OUTDATA5_SC0DIR_

SC0notSETVPP


ASC0RTS


VSYNC_ASC1RTS

TS0OUTDATA3_SC1DATAINOUT_

PIXCLK

NANDSCN3 notMODULERESETIN

DCU_TDI

DCU_TMS

AUX_TCK

DCU_TRIGGEROUT

DCU_DEBUGMODESEL

SPARE5

SPARE7

AUX_TDDOWN

96/160 8149405


C.2.9


Transport stream connectors CN24/CN25

Two 20-pin connectors provides transport stream data output.

CN24 is the debug transport stream, CN25 is control and data and is shared with the NIM transport stream.

Figure 71.

Transport stream data connector

19 1

20 2


Table 61.

Transport stream data connector pin allocation


9

11

13

15

5

7

1

3

17

19

SDA notRST

DATA0

DATA2

DATA4

DATA5

DATA7

TSERROR

TSVALID

TSPACKETCLK

10

12

14

16

18

20

6

8

2

4

SCL

NC

DATA1

DATA3

NC

DATA6

NC

TSCLK

NC

AS1

Description

8149405 97/160


C.2.10 NIM connector CN26

One 84-pin connector. The connector is made up from two separate female connectors:

●

● a SAMTEC 28-pin a SAMTEC 54-pin

The two connectors are arranged, and the pins are numbered, as shown in Figure 72 .

Pins 15 and 57 are not available.

Figure 72.

NIM connector

42

15

16 14 1

84 58

57

56 43


Table 62.

NIM connector pin allocation

Pin Description

LNBRF

GNDA1

GNDA2

GNDA3

LNBSUPPLY5V

GNDA4

GNDA5

GNDA6

VCC3V3A

GNDA7

GNDA8

VCORE_A1

ANALOG5V

VTUNE32V

Key3

DISEQCRX

ADDRESS0

DISEQCTX

OP1

OP0

12

13

14

15

16

17

18

19

20

6

7

4

5

8

9

10

11

1

2

3

Pin

54

55

56

57

58

59

60

61

62

46

47

48

49

50

51

52

53

43

44

45

Description

Key1

VCORESEL_COM

VCORESEL_1V2

VCORESEL_1V0

RESERVED1

RESERVED2

SRX

DRX

ITX

QTX

ETX

VCORE_A2

CTX

OOB_RESERVED

Key4

RESERVED3

ADDRESS1

RESERVED4

RESERVED5

RESERVED6

98/160 8149405


Table 62.

NIM connector pin allocation (continued)


28

29

30

31

32

33

34

35

24

25

26

27

21

22

23

39

40

41

42

36

37

38

OP2

GNDD1

VCORE_D1

PACKETCLK

BYTECLKVALID

BYTECLK

ERROR

GNDD2

VCORE_D2

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

GNDD3

VCC3V3D

SCL

SDA notRESET

70

71

72

73

74

75

76

77

66

67

68

69

63

64

65

81

82

83

84

78

79

80

Description

RESERVED7

GNDD4

VCORE_D3

PACKETCLK_2

BYTECLKVALID_2

BYTECLK_2

ERROR_2

GNDD5

VCORE_D4

DATA7_2

DATA6_2

DATA5_2

DATA4_2

DATA3_2

DATA2_2

DATA1_2

DATA0_2

GNDD6

RESERVED8

SCL_2

SDA_2

Key2

8149405 99/160


C.2.11 ATX power connector CN27

A standard ATX power supply is used to provide different voltage levels to the board. This board-mounted Molex connector is a 20-pin mini-fit jr type.

Figure 73.


1 10

11 20


Table 63.

ATX power connector pin allocation


6

7

4

5

1

2

3

8

9

10

+3V3_A

+3V3_B

GND_A

+5V_A

GND_B

+5V_B

GND_C

PW_OK

+5VSB

+12V

14

15

16

17

11

12

13

18

19

20

+3V3_C

-12V

GND_D notPS_ON

GND_E

GND_F

GND_G

-5V

+5V_C

+5V_D

Description

100/160 8149405


C.2.12 Smartcard header data connectors CN28/CN29

Two 8-pin vertical post PTH header connectors provide smartcard data.

Figure 74.

Smartcard header data connector

8 1


Table 64.

Smartcard header data connector pin allocation

Pin Description

(1)

Pin

1

2

SC n DATAOUT

SC n DATAIN

3

4

SC

SC n n

EXTCLK

CLK

1.

Where n =0 for CN29 and n =1 for CN28.

7

8

5

6

Description

SC n RESET

SC n CMDVCC

SC n VPP

SC n DETECT

C.2.13 Smartcard sockets CN30

Two 10-pin smartcard sockets. Dual smartcard connector, friction contacts, through hole, normally closed detection switch.

Figure 75.

Smartcard socket

15

5

1

11

4

14 9 10

18

19 20

8

Indicates pins 11-20 of bottom smartcard

(smartcard 1)

Top smartcard viewed from above PCB

Table 65.

Smartcard socket pin allocation

Pin Description

3

4

1

2

5

6

GNDC

SC0VPP

IO

AUX2

VCC

RST

Pin

11

12

13

14

15

16

GNDC

SC1VPP

IO

AUX2

VCC

RST

Description

8149405 101/160


Table 65.

Smartcard socket pin allocation (continued)

Pin

7

8

9

10

Description

CLK

AUX1

GNDC

PRES/notPRES

Pin

17

18

19

20

Description

CLK

AUX1

GNDC

PRES/notPRES

C.2.14 ATAPI connector CN31

A 2 x 20-way, 40-pin connector provides ATAPI data.

Figure 76.

ATAPI connector

39 1

102/160

40 2


Table 66.

ATAPI connector pin allocation

Pin Description notRESET

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

GND

DMARQ notDIOW notDIOR

IORDY notDMACK

INTRQ

DA1

DA0

23

25

27

29

15

17

19

21

31

33

35

11

13

7

9

1

3

5

Pin

24

26

28

30

16

18

20

22

32

34

36

8

10

12

14

2

4

6

GND

DD8

DD9

DD10

DD11

DD12

DD13

DD14

DD15

Reserved

Description

GND

SPSYNC_CSEL

GND notIOCS16 notPDIAG

DA2

8149405


Table 66.

ATAPI connector pin allocation (continued)


37

39 notCS0 notDASP

38

40 notCS1

GND

Description

C.2.15 STEM EMI CN32

A 140-pin surface mount board to board connector plug.

Figure 77.

STEM EMI connector

140 71

70 1


Table 67.

STEM EMI connector pin allocation


10

11

8

9

12

13

14

15

6

7

4

5

1

2

3

16

17

18

19

20 notBS 71

SDRAM_CLK 72

SDRAM_CLKEN 73

MEZZ_PRESENT0

GND

DACK2

DACK0

74

75

76

77

DRAK0

DREQ0

GND

MEMWAIT

+3V3 (VCC)

MEMGRANTED notINTR0

GND

78

79

80

81

82

83

84

85

FLASH_CLK

GND notWR

GND notCS0

86

87

88

89

90

Description notFRAME notCAS notRESET

MEZZ_PRESENT1

GND

DACK3

DACK1

DRAK1

DREQ1

GND

AUX_CLK

+3V3 (VCC)

MEMREQ notINTR1

GND

FBAA

GND notOE

GND notCS1

8149405 103/160


42

43

44

45

46

47

36

37

38

39

40

41

51

52

53

54

55

48

49

50

28

29

30

31

32

33

34

35

24

25

26

27

21

22

23

GND

D23 (NC)

D21 (NC)

GND

D19 (NC)

D17 (NC)

GND

D15

+3V3 (VCC)

A5

A3

GND

A1_notBE3 notBE1

GND

D31 (NC)

D29 (NC)

GND

D27 (NC)

D25 (NC)

GND

A25

A23

+3V3 (VCC)

A21

A19

GND

A17

A15

+3V3 (VCC)

A13

A11

GND

A9

A7

Table 67.



GND

D22 (NC)

D20 (NC)

+5V VCC

D18 (NC)

D16 (NC)

GND

D14

+3V3 (VCC)

A4

A2

GND

A0_notBE2 notBE0

GND

D30 (NC)

D28 (NC)

+5V VCC

D26 (NC)

D24 (NC)

GND

A24

A22

+3V3 (VCC)

A20

A18

GND

A16

A14

+3V3 (VCC)

A12

A10

GND

A8

A6

Description

112

113

114

115

116

117

106

107

108

109

110

111

118

119

120

121

122

123

124

125

98

99

100

101

102

103

104

105

94

95

96

97

91

92

93

104/160 8149405


Table 67.


Pin

63

64

65

66

67

68

69

70

59

60

61

62

56

57

58

D13

GND

D11

D9

GND

D7

D5

GND

D3

D1

GND

MPX_CLK

GND

+12 V (VCC)

Description Pin

133

134

135

136

137

138

139

140

126

127

128

129

130

131

132

Description

D12

+5V VCC

D10

D8

GND

D6

D4

+5V VCC

D2

D0

GND

ALE_notRAS

GND

+12 V (VCC)

8149405 105/160


106/160

A 27-channel, Tektronix P6960 series high-density logic probe land pattern.

Figure 78.

P6960 series logic probe land pattern

A27 A1

B27 B1


Table 68.

P6960 series logic probe land pattern pin allocation


BUFF_DVBDATA3

BUFF_DVBDATA5

GND

BUFF_DVBDATA7

BUFF_DVBADDR10

GND

TP110 (CK1+)

TP111 (CK1-)

GND

BUFF_DVBADDR9

BUFF_DVBADDR8

GND

BUFF_DVBADDR14 notDVBINTR

GND

BUFF_DVBADDR7 notDVBRESET

GND notDVBWAIT

BUFF_DVBADDR4

GND

BUFF_DVBADDR3 notDVBREG

GND

BUFF_DVBADDR0

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

21

22

23

24

25

17

18

19

20

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

21

22

23

24

25

17

18

19

20

GND

BUFF_DVBDATA4

BUFF_DVBDATA6

GND notDVBCE notDVBIOOE

GND

BUFF_DVBADDR11 notDVBIORD

GND notDVBIOWR

BUFF_DVBADDR13

GND notDVBIOWE

BUFF_DVBADDR12

GND

BUFF_DVBADDR6

BUFF_DVBADDR5

GND

TP116 (CK2-)

TP117 (CK2+)

GND

BUFF_DVBADDR2

BUFF_DVBADDR1

GND

8149405


Table 68.

P6960 series logic probe land pattern pin allocation (continued)


26

27

BUFF_DVBDATA1

GND

26

27

BUFF_DVBDATA0

BUFF_DVBDATA2

C.2.17 DVB-CI connector CN34

A 68-pin DVB-CI connector. Single DVB-CI connector, supports type I, II cards. Single port, right angle, top mount, through hole, 68-pin, with eject (right side).

Figure 79.

DVB-CI connector

34 1

68 35


Table 69.

DVB-CI connector pin allocation

Pin Description

NC

DATA3

DATA4

DATA5

DATA6

DATA7 notCE1

NC notOE

A11

A9

A8

A13

A14 notWE notIREQ

VCC1

VPP1

TS_IN_VAL

13

14

15

16

17

10

11

12

18

19

4

5

6

1

2

3

7

8

9

Pin

47

48

49

50

51

44

45

46

52

53

38

39

40

35

36

37

41

42

43

Description

NC notCD1

TS_OUT_DATA3

TS_OUT_DATA4

TS_OUT_DATA5

TS_OUT_DATA6

TS_OUT_DATA7 notCE2

NC notIORD notIOWR

TS_IN_STRT

TS_IN_DATA0

TS_IN_DATA1

TS_IN_DATA2

TS_IN_DATA3

VCC0

VPP0

TS_IN_DATA4

8149405 107/160


Table 69.

DVB-CI connector pin allocation (continued)

Pin

27

28

29

30

31

32

33

34

23

24

25

26

20

21

22

A6

A5

A4

A3

TS_IN_CLK

A12

A7

A2

A1

A0

DATA0

DATA1

DATA2 notIOIS16

NC

Description Pin

61

62

63

64

65

66

67

68

57

58

59

60

54

55

56

Description

TS_IN_DATA5

TS_IN_DATA6

TS_IN_DATA7

TS_OUT_CLK

CARD_RESET notWAIT

NC notREG

TS_OUT_VAL

TS_IN_STRT

TS_OUT_DATA0

TS_OUT_DATA1

TS_OUT_DATA2 notCD2

NC

C.2.18 I

2

C blaster connector CN35

An 8-pin header provides I

2

C interfaces.

Figure 80.

I

2

C blaster connector

4 1

8 5


Table 70.

I

2

C connector pin allocation

Pin Description

1

2

3

4


VCC

USER1

(1)

SDA

1.

Connected to NIM reset.

Pin

7

8

5

6

USER2

(1)

SCL

USER3

(1)

GND

Description

108/160 8149405


A 40-pin connector provides Ethernet data output.

Figure 81.

Ethernet MII data connector

39 1

40 2


Table 71.

Ethernet MII data connector pin allocation


GND GND

25

27

29

31

17

19

21

23

33

35

37

39

9

11

13

15

5

7

1

3

+3V3

MII_COL

MII_TXD0

MII_TXD2

GMII_TXD4 (NC)

GMII_TXD6 (NC)

GND

MII_TXCLK

MII_RXCLK

MII_RX_DV

MII_RXD0

MII_RXD2

GMII_RXD4 (NC)

GMII_RXD6 (NC)

GND

MII_MDIO notINT

GMII_MODE

26

28

30

32

18

20

22

24

34

36

38

40

10

12

14

16

6

8

2

4

+5V

Description

MII_CRS

MII_TXD1

MII_TXD3

GMII_TXD5 (NC)

GMII_TXD7 (NC)

MII_TX_EN

GND

MII_RX_ER

GND

MII_RXD1

MII_RXD3

GMII_RXD5 (NC)

GMII_RXD7 (NC)

MII_MDC notRESET

RMII_MODE

GND

8149405 109/160


An RJ45 connector provides a 10/100 BaseT Ethernet physical layer (PHY) interface.

Figure 82.

Ethernet connector

LED1 LED2


Table 72.

Ethernet connector pin allocation


1

2

3

4

5

6

MDI_2CT

+2V5_GMII

MDI_2-

MDIC_N

MDI_2+

MDIC_P

MDI_1+

MDIB_P

MDI_1-

MDIB_N

MDI_1CT

+2V5_GMII

7

8

9

10

11

12

MDI_3CT

+2V5_GMII

MDI_3+

MDID_P

MDI_3-

MDID_N

MDI_0-

MDIA_N

MDI_0+

MDIA_P

MDI_0CT

+2V5_GMII

Description

LED1 indicates Ethernet activity. LED2 indicates 100Base Tx Ethernet protocol.

●

●

●

●

LED output functions are user selectable. Up to two LED functions at one time. The LED output functions are: activity full duplex

10BASE T or 100BASE TX Ethernet transmit protocol transmit, receive

110/160 8149405

STi5197-MBoard, STi5189/97-MB MB676 23 x 23 processor board jumpers, option resistors and

Appendix D MB676 23 x 23 processor board jumpers, option resistors and switches

●

●

●

This appendix contains the following sections:

Section D.1: Jumpers

Section D.2: Option resistors on page 116

Section D.3: Switches on page 117

D.1 Jumpers

The MB676 processor board includes the jumpers listed in

Table 73 . The default

configuration layout of the jumpers can be seen in Figure 83 on page 115 .

Table 73.

Jumper settings

Jumper Description

J1

J2

A

ATX power supply remote power on.

On = ATX power supply (if connected) turned on

Off = ATX power off

Ground test point.

Reset out to MB762/MB829.

On = enabled

Off = isolated

B

C

D

Reserved

J3

J4

E

F

G

H

USB VBUS overcurrent detect to Int2 isolator.

On = enabled

Off = isolated

Reserved

Reset from MB762/MB829.

On = enabled

Off = disabled

FMI Flash clock isolator.

On = enabled

Off = isolated

+8V audio power supply isolator.

On = enabled

Off = isolated

Default

Off

Do not fit

On

Do not fit

Off

Do not fit

On

On

8149405 111/160

MB676 23 x 23 processor board jumpers, option resistors and switches

Table 73.

Jumper settings (continued)


J5

J6

J7

J8

F

G

H

A

B

C

H

A

B

C

D

E

D

E

F

G

H

B

C

H

A

D

E

F

G

F

G

D

E

A

B

C

PIO4_5 SC1CMDVCC isolator.

PIO4_5 DVODATA5 isolator.

PIO4_2 SC1EXTCLK isolator.


PIO3_7 DVOCLK isolator.

PIO3_2 SSC1DATAINOUT isolator.

PIO0_6 SC0VPP isolator.

PIO0_5 SC0CMDVCC isolator.

PIO0_2 SC0EXTCLK isolator.

PIO0_0 SC0DATAOUT isolator.

PIO1_3 ASC2RXD isolator.

AUXCLKOUT isolator.

PIO2_5 IRB_IN isolator.

PIO2_5 ASC3_RTS isolator.

PIO2_2 ASC3_CTS isolator.

PIO2_2 PCMSCLKOUT isolator.

PIO0_3 SC0CLK isolator.

PIO0_1 SC0DATAIN isolator.

PIO1_2 ASC2TXD isolator.

PIO1_5 ASC2CTS isolator.

PIO1_5 CLK27 isolator.

PIO2_1 ASC3_RXD isolator.

PIO2_1 PCMLRCLKOUT isolator.

PIO2_1 BILED2 isolator.


PIO4_6 SC1VPP isolator.

PIO4_3 SC1CLK isolator.


PIO4_0 SC1DATAOUT isolator.


PIO3_4 INTUP1 isolator.

PIO3_4 HSYNC isolator.

On = enabled

Off = isolated

On = enabled

Off = isolated

On = enabled

Off = isolated

On = enabled

Off = isolated

STi5197-MBoard,

Default

On

On

On

On

112/160 8149405


Table 73.



J9

J10

J11

J12

J13

J14

J15

C

D

E

F

G

A

B

E

F

G

H

B

C

H

A

D

F

G

D

E

A

B

C

H

PIO0_4 SC0RESET isolator.

PIO0_7 SC0DETECT isolator.

PIO1_1 FDMAREQ1 isolator.

PIO1_4 ASC2RTS isolator.

PIO2_0 PCMDATAOUT isolator.

PIO2_0 ASC3_TXD isolator.

PIO2_0 BILED1 isolator.

PIO1_0 FDMAREQ0 isolator.

PIO4_7 SC1DETECT isolator.


PIO4_4 SC1RESET isolator.


PIO4_1 SC1DATAIN isolator.


PIO3_3 SSC1CLK isolator.

On = enabled

Off = isolated

On = enabled

Off = isolated

PIO3_3 VSYNCEN isolator.

1V supply.

1-2 = variable by R4

2-3 = fixed

Main clock source.

1-2 = on-board crystal

2-3 = other source selected by J24

Isolator for analog 1V0 power to front end tuner.

Isolator for analog 2V5 power to front end tuner.

PIO2_6 PCMDATAIN isolator.

QAM_POW_IN to PIO2_7 isolator

PIO2_7 PCMLRCLKIN isolator.

PIO2_7 IRB_OUT isolator.

PIO2_7 FPRESET isolator.

On = enabled

Off = isolated


PIO3_0 VSYNC isolator.

Interrupt 0 loopback.

On = loopback for standalone use

Off = MB762/MB829 connected

Default

On

On

2-3

1-2

On

On

On

Off

On

Off

8149405 113/160


Table 73.



J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

A

G

H

E

F

B

C

D

A

B

PIO3_6 MB762/MB829 Front Panel LED isolator.

PIO3_6 DVBCI_BUSGNT isolator.

PIO2_4 PCMSCLKIN isolator.


PIO1_6 I

2

C bus SCL isolator.

PIO1_6 SSC0_SCLKINOUT isolator.

PIO1_7 I

2

C bus SDA isolator.

PIO1_7 SSC0_MTSR_DINOUT isolator.

On = enabled

Off = isolated

USB3317 +1V8 source select.

1-2 = voltage regulator

2-3 = low cost diode option

USB3317 reset.

1-2 = device disabled (held in reset)

2-3 = normal operation

USB3317 clock source select.

4-5 = AuxClock

5-6 = on-board crystal oscillator

PROCSPIDATAOUT isolator.

On = enabled

Off = isolated

PROCSPIDATAIN isolator.

On = enabled

Off = isolated

PROCSPICLK ISOLATOR.

On = enabled

Off = isolated

Serial Flash device select.

1-2 = on-board Atmel AT45

2-3 = MB762/MB829 serial Flash

TMU clock.

1-2 = pull down

2-3 = pull up

Alternate clock source.

1-2 = external clock from CN14

2-3 = FE_CLKOUT

1.0V source.

2-3 = from on-chip regulator

1-2 = from board regulator

Ground test point

STi5197-MBoard,

Default

On

1-2

2-3

5-6

On

On

On

1-2

Do not fit

1-2

1-2

Do not fit

114/160 8149405


Table 73.



J27

F

G

D

E

H

A

B

C

PIO3_2 DVBCI_CD1 isolator.

PIO3_5 DVBCI_BUSREQ isolator.

PIO3_5 HSYNCEN isolator.

PIO2_3 PCMMCLK isolator.

PIO3_3 DVBCI_RESET isolator.

NANDCSn1 isolator.

NANDRBn1 isolator.

NANDRBn3 isolator.

Figure 83.

Default configurations of the jumpers

Not fitted Do not fit Fitted

On = enabled

Off = isolated

1

1-2

2 3

Default

On

1

2-3

2 3

A 1-2, 2-3

B 4-5, 5-6

A B

1 4

2 5

3 6

1

Not fitted

2 3

Jumper can be fitted to pin 1, 2 or 3

(whichever is most convenient)

8149405 115/160

MB676 23 x 23 processor board jumpers, option resistors and switches STi5197-MBoard,

The MB676 processor board includes the resistors listed in Table 74

. The default

configuration layout of the resistors can be seen in Figure 84 .

Table 74.

Option resistor settings

Resistor

R3

R6

R10

R27

Description

I

2

C PIO expander address A2 select.

1-2 = pull up

2-3 = pull down

I

2


1-2 = pull up

2-3 = pull down

I

2


1-2 = pull up

2-3 = pull down

USB TMT connector resert sense

1-2 = inverted

2-3 = non-inverted

R77

R109

R169

R171

R173

R190

R209

FMI mode select: FMI boot bank size 1. Must be high.

SYS_CLOCKOSC load capacitor pull up/down select.

1-2 = +2V5_ANA

2-3 = Ground

DCT70700 Tuner CAS.

1-2 = +5V_ANA_CAB

2-3 = GND

HDMI HSYNC select.

1-2 = use embedded

2-3 = use SoC HSYNC

HDMI VSYNC select.

1-2 = use embedded

2-3 = use SoC VSYNC

LNBH23 I2C address select pin.

1-2 = high

2-3 = low

HDMI SII9024 I

2

C address select.

1-2 = pull high

2-3 = pull low

Default

1-2

2-3

1-2

2-3

1-2

116/160 8149405


Figure 84.

Default configurations of the resistors

1-2 2-3

D.3 Switches

The MB676 processor board has a number of switches that control many aspects of the board operation. Information on the switches is given in

Table 75 . A quad switch is shown in

Figure 85

.

Table 75.

Option switch settings

Switch

SW1

SW2

SW3

-

1

2

3

4

1

2

3

4

Description

Board master reset push button

Resets all devices on MB676 and MB762/MB829, sends reset to the SoC.

FMIADDR[20]. NAND Flash address type.

0(On) = Long addressing

1(Off) = Short addressing

FMIADDR[22:21]. Boot mode.

00(On,On) = Parallel NOR, 01(ON,OFF)=NAND,

10(Off,On) = Serial

11(Off,Off) = Reserved

FMIADDR[23]. Reset period.

0(On) = 200 ms stretch

1(Off) = Normal

FMIADDR[1]. Boot bank size.

0(On) = 16-bit

1(Off) = 8-bit

FMIADDR[3]. NAND Flash offset remap.

0(On) = Reserved

1(Off) = Remap

FMIADDR[18]. Serial Flash type.

0(On) = Older Atmel devices

1(Off) = All other devices

FMIADDR[19]. NAND Flash page type.

0(On) = Small

1(Off) = Large

Default

N/A

On (0)

On (0)

Off (1)

On (0)

Off (1)

On (0)

8149405 117/160


Figure 85.

Configuration switch options

STi5197-MBoard,

Note: In

Figure 85 , switches 1 and 2 are OFF and switches 3 and 4 are ON.

118/160 8149405


Appendix E MB704 15 x 15 processor board jumpers, option resistors and switches

●

●

●


Section E.1: Jumpers

Section E.2: Option resistors on page 123

Section E.3: Switches on page 124

E.1 Jumpers

The MB704 processor board includes the jumpers listed in

Table 76 . The default

configuration layout of the jumpers can be seen in Figure 86 on page 122 .

Table 76.

Jumper settings


J1

J2

J3

J4

A

D

E

F

G

H

A

B

C

B

C

D

E

F

G

H

1V supply

1-2 = variable by R4

2-3 = fixed

Reset to MB762/MB829

On = enabled

Off = disabled

DVBCI_BUSGNT / PIO3_6 isolator

PCM_SCLKIN / PIO2_4 isolator

INTUP2 / PIO3_1 isolator

SSC0_SCLK for MB704 / PIO1_6 isolator

SSC0_SCLK for MB762/MB829 /

PIO1_6 isolator

SSC0_DINOUT for MB704 / PIO1_7 isolator

SSC0_DINOUT for MB762/MB829 /

PIO1_7 isolator

Ground test point

SC1 detect / PIO4_7 isolator

DVO_DATA7 / PIO4_7 isolator

SC1_CMDVCC / PIO4_5 isolator

PIO4_5 isolator

SC1_CLK / PIO4_3 isolator


SC1_DATAIN / PIO4_1 isolator


On = enabled

Off = isolated

On = enabled

Off = isolated

Default

2-3

On

Do not fit

On

8149405 119/160


Table 76.



J5

J6

J7

J8

G

H

D

E

F

A

B

C

C

D

E

F

G

H

B

F

H

A

G

H

A

B

F

G

D

E

A

B

C


SC1_VPP / PIO4_6 isolator

SC1_RESET / PIO4_4 isolator


SC1_EXTCLK / PIO4_2 isolator


SC1_DATAOUT / PIO4_0 isolator


PCM_MCLK / PIO2_3 isolator

MB762/MB829 reset out

DVBCI_CD1 / PIO3_2 isolator

SSC1_DATAINOUT / PIO3_2 isolator

VSYNC_EN / PIO3_2 isolator

DVBCI_RESET / PIO3_3 isolator

SSC1_CLK / PIO3_3 isolator

VSYNC / PIO3_0 isolator

SC0_RESET / PIO0_4 isolator

SC0_DETECT / PIO0_7 isolator

SC0_EXTCLK / PIO0_2 isolator

ASC2_RXD / PIO1_3 isolator

FDMA_REQ1 / PIO1_1 isolator

DVO_CLK / PIO3_7 isolator

SC0_VPP / PIO0_6 isolator

SC0_CMDVCC / PIO0_5 isolator

SC0_CLK / PIO0_3 isolator

ASC2_TXD / PIO1_2 isolator

SC0_DATAIN / PIO0_1 isolator

ASC2_CTS / PIO1_5 isolator

CLK27 / PIO1_5 isolator

On = enabled

Off = isolated

On = enabled

Off = isolated

On = enabled

Off = isolated

On = enabled

Off = isolated

STi5197-MBoard,

Default

On

On

On

On

120/160 8149405


Table 76.



J9

J10

J11

J12

J13

J14

E

F

G

H

A

B

C

D

F

G

H

A

B

C

D

E

INTUP1 / PIO3_4 isolator

HSYNC / PIO3_6 isolator

FMI_FLASHCLK / FMI Flash clock isolator

HSYNC_EN / PIO3_5 isolator

GPIO_DVBCI_BUSREQ / PIO3_5 isolator

SC0_DATAOUT / PIO0_0 isolator

ASC2_RTS / PIO1_4 isolator

AUX_CLKOUT isolator

Serial Flash device select

1-2 = on-board ATMEL

2-3 = MB762/MB829 serial Flash

8 Volt audio power supply isolator

1V source

1-2 = from board regulator

2-3 = from on-chip regulator

Main clock source

1-2 = on board crystal

2-3 = external clock through CN12

ASC3_TXD / PIO2_0

PCM_DATAOUT / PIO2_0

IRB_IN / PIO2_5 isolator

ASC3_RTS / PIO2_5 isolator

PCM_DATAIN / PIO2_6 isolator

PCM_LRCLKIN / PIO2_7 isolator

IRB_OUT / PIO2_7 isolator

FP_RESET / PIO2_7 isolator

On = enabled

Off = isolated

On = enabled

Off = isolated

Default

On

2-3

On

1-2

1-2

On

8149405 121/160


Table 76.



J15

J16

J17

J18

J19

J20

J21

J22

D

E

F

A

B

C

G

H

ASC3_RXD / PIO2_1

PCM_LRCLKOUT / PIO2_1

FDMA_REQ0 / PIO1_0

ASC3_CTS / PIO2_2

PCM_LRCLKOUT / PIO2_2

INTUP0 / PIO3_0

Interrupt 0 loopback (HDMI)

On = loopback for standalone use

Off = through MB762/MB829 EPLD

QAM POWER_IN

On = connect to PIO3_0

Off = disabled

Ground test point

USB3317 1V8 source select

1-2 = voltage regulator

2-3 = low cost diode option

TMU clock

1-2 = pull up

2-3 = pull down

PROC_SPI_DATAIN isolator

PROC_SPI_DATAOUT isolator

PROC_SPI_CLK isolator

USB3317 clock source select

1-2 = auxillary clock

2-3 = on-board crystal oscillator

On = enabled

Off = isolated

On = enabled

Off = isolated

Figure 86.


Not fitted Do not fit Fitted 1

1-2

2 3

Default

On

Do not fit

Off

Do not fit

1-2

Do not fit

On

2-3

1

2-3

2 3

1

Not fitted

2 3

Jumper can be fitted to pin 1, 2 or 3

(whichever is most convenient)

122/160 8149405


The MB704 processor board includes the resistors listed in Table 77

. The default

configuration layout of the resistors can be seen in Figure 87 .

Table 77.


Resistor Description

R20

R21

R22

R144

R194

R202

R204

R209

I

2


1-2 = pull up

2-3 = pull down

I

2


1-2 = pull up

2-3 = pull down

I

2


1-2 = pull up

2-3 = pull down

SYS_CLOCKOSC load capacitor pull up/down select.

1-2 = +2V5_ANA

2-3 = Ground

DCT70701 tuner CAS.

1-2 = +5V_ANA

2-3 = Ground

HDMI HSYNC select.

1-2 = use embedded

2-3 = use SoC HSYNC

HDMI VSYNC select.

1-2 = use embedded

2-3 = use SoC VSYNC

HDMI SII9024 I

2

C address select.

1-2 = pull high

2-3 = pull low

Default

1-2

2-3

1-2

Figure 87.


1-2 2-3

8149405 123/160


E.3 Switches

The MB704 processor board has only one option switch setting which is shown in Table 78 .

There is no default configuration.

Table 78.


Switch

SW1

Description

Board master reset button, resets all devices on MB704 and MB762/MB829, sends reset to SoC.

Default

N/A

124/160 8149405

STi5197-MBoard, STi5189/97-MB MB762 SD generic peripheral board jumpers, option resistors

Appendix F MB762 SD generic peripheral board jumpers, option resistors and switches

●

●

●


Section F.1: Jumpers

Section F.2: Option resistors on page 127

Section F.3: Switches on page 128

F.1 Jumpers

The MB762 SD generic peripheral board includes the jumpers listed in Table 79 . The default

configuration layouts of the jumpers are shown in

Figure 88

.

Table 79.

Jumper settings


J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

A

B

12V power

External connection to drive power on/off

Include processor module in EPLD JTAG chain

On = bypass module

Off = include module EPLDs in JTAG chain

5V power

NIM VCORE remote/local sense select

On = sense controlled by MB762

Off = sense controlled by NIM

Ground

CVBS routing

1-2 = through SCART switch to SCART

2-3 = through buffer to phono

Ground

SPI EEPROM CS source select

1-2 = EPLD_notSPICS

2-3 = PIO_SPICS

SPI EEPROM select

4-5 = M25P80

5-6 = M25P32

NAND Flash write protect

On (0) = protected

Off (1) = unprotected

3V power J11

J12

J13

Ground

Default

Do not fit

On

Do not fit

On

Do not fit

1-2

Do not fit

2-3

4-5

Off

Do not fit

8149405 125/160

MB762 SD generic peripheral board jumpers, option resistors and switches STi5197-MBoard,

Table 79.



J14

J15

J16

J17

J18

J19

J20

J21

J22

ATAPI not DASP isolation jumper

12V power

3V power

5V power

Ethernet PHY clock select

1-2 = crystal

2-3 = MII PHY clock

Ground

Enable RS232 port 0

On = enabled

Off = disabled

Enable RS232 port 1

On = enabled

Off = disabled

IR input enable

On = disabled

Off = enabled

Figure 88.



1-2

2 3

Default

On

Do not fit

2-3

Do not fit

On

Off

1

2-3

2 3

A 1-2, 2-3

B 4-5, 5-6

A B

1 4

2 5

3 6

126/160 8149405


The MB762 SD generic peripheral board includes the resistors listed in

Table 80 . The

default configuration layouts of the resistors are shown in

Figure 89

.

Table 80.



R82

R86

R90

R108

R109

R110

R135

R142

R176

R178

R179

R180

SMUTE pull up/down select

1-2 = pull up

2-3 = pull down

NIM I

2

C address 1 select

1-2 = high

2-3 = low

NIM I

2

C address 2 select

1-2 = high

2-3 = low

I

2

C EEPROM address E1 select

1-2 = pull up

2-3 = pull down

I

2


1-2 = pull up

2-3 = pull down

I

2


1-2 = pull up

2-3 = pull down

Transport stream I

2

C address select

1-2 = high

2-3 = low

CVBS buffer/direct select

1-2 = unbuffered

2-3 = buffered

NANDWAIT1 pull up/down select

1-2 = pull up

2-3 = pull down


1-2 = pull up

2-3 = pull down


1-2 = pull up

2-3 = pull down


1-2 = pull up

2-3 = pull down

Default

1-2

2-3

1-2

8149405 127/160

MB762 SD generic peripheral board jumpers, option resistors and switches STi5197-MBoard,

Table 80.

Option resistor settings (continued)


R213

LNBH23 I

2

C address select

1-2 = high

2-3 = low

R258

R269

R286

Smartcard 0 presence detect active state select

1-2 = notPRES

2-3 = PRES


1-2 = notPRES

2-3 = PRES

ATAPI interrupt active high or low pull up/down select

1-2 = pull down

2-3 = pull up

Figure 89.


Default

1-2

2-3

1-2

1-2 2-3

F.3 Switches

The MB762 SD generic peripheral board has a number of switches that control many

aspects of the board operation. Information on the switches is given in Table 81

. A quad

switch is shown in Figure 90 .

Table 81.


Switch

SW1

SW2

3

4

1

2

3

4

1

2

Description

FMI EPLD config (7:4) switch


Default

On

On

128/160 8149405


Table 81.

Option switch settings (continued)

Switch Description

SW3

SW4

SW5

2

3

4

1

1

2

3

2

3

4

1

4


Transport stream EPLD config (3:0) switch


SW6

SW7

SW8

SW9

SW10

Front panel reset push button

Front panel user push button

Figure 90.


Default

On

On

On

N/A

Note: In


8149405 129/160

MB829 SD modular validation peripheral board jumpers, option resistors and switches STi5197-

Appendix G MB829 SD modular validation peripheral board jumpers, option resistors and switches

●

●

●


Section G.1: Jumpers

Section G.2: Option resistors on page 132

Section G.3: Switches on page 133

G.1 Jumpers

The MB829 SD modular validation peripheral board includes the jumpers listed in Table 82 .

The default configuration layouts of the jumpers are shown in

Figure 91 .

Table 82.

Jumper settings


J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

A

B

5V power

Include processor module in EPLD JTAG chain

1-2 = Include module EPLDs in JTAG chain

2-3 = Bypass module

Enable RS232 port 0

On = enabled

Off = disabled

Enable RS232 port 1

On = enabled

Off = disabled

NIM VCORE remote/local sense select

On = sense controlled by MB829

Off = sense controlled by NIM

Ground

Ground

SPI EEPROM CS source select

1-2 = EPLD_notSPICS

2-3 = PIO_SPICS

SPI EEPROM select

1-2 = M25P80

2-3 = M25P32

NAND Flash write protect.

On (0) = protected

Off (1) = unprotected

Enable/disable remote power On/Off

On = enabled

Off = disabled, uses SW6 only

Default

Do not fit

2-3

On

Do not fit

2A-3A

2B-3B

Off

On

130/160 8149405

STi5197-MBoard, STi5189/97-MB MB829 SD modular validation peripheral board jumpers, option

Table 82.



J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

ATAPI notDASP isolation jumper

Ground

+12V power

Ground

Ground

5V power

12V power

3V power

3V power

IR input enable

On = disabled

Off = enabled

Figure 91.



1-2

2 3

Default

On

Do not fit

Off

1

2-3

2 3

A 1-2, 2-3

B 4-5, 5-6

A B

1 4

2 5

3 6

8149405 131/160


The MB829 SD modular validation peripheral board includes the resistors listed in

Table 83 .

The default configuration layouts of the resistors are shown in

Figure 92

.

Table 83.



R6

R69

R71

R75

R79

R82

R83

R84

R137

R138

R139

R140

SMUTE pull up/down select

1-2 = pull up

2-3 = pull down

Transport stream header (CN24) I

2

C address select

1-2 = high

2-3 = low

Transport stream header (CN25) I

2

C address select

1-2 = high

2-3 = low

NIM I

2

C address 1 select

1-2 = high

2-3 = low

NIM I

2

C address 2 select

1-2 = high

2-3 = low

I

2


1-2 = pull up

2-3 = pull down

I

2


1-2 = pull up

2-3 = pull down

I

2


1-2 = pull up

2-3 = pull down

NandWait1 pull up/down select

1-2 = pull up

2-3 = pull down


1-2 = pull up

2-3 = pull down


1-2 = pull up

2-3 = pull down


1-2 = pull up

2-3 = pull down

Default

1-2

2-3

1-2

2-3

1-2

132/160 8149405


Table 83.

Option resistor settings (continued)


R169

LNBH23 I

2

C address select

1-2 = high

2-3 = low

R208

R222

R240


1-2 = notPRES

2-3 = PRES


1-2 = notPRES

2-3 = PRES

ATAPI interrupt active high or low pull up/down

1-2 = pull down

2-3 = pull up

Figure 92.


Default

1-2

2-3

1-2

1-2 2-3

G.3 Switches

The MB829 SD modular validation peripheral board has a number of switches that control many aspects of the board operation. Information on the switches is given in

Table 84

. A quad switch is shown in

Figure 93

.

Table 84.


Switch

SW1

1

2

3

4

Description


Config4 - SPI_notHOLD.

On = Active, Off = Inactive

Config5 - SPI_notPROT.

On = Active, Off = Inactive

Config6 - Smartcard 0 reset invert.

Off = Invert, On = No invert

Config7 - Smartcard 0 data link.

Off=data in + out linked.

Default

On

8149405 133/160


Table 84.

Option switch settings (continued)

Switch Description

SW2

SW3

SW4

SW5

SW6

SW7

1

2

3

4

1

1

2

3

4

2

3

4

1

2

3

4


Config8 - Smartcard 0 voltage.

On = 3V, Off = 5V

Config9 - Smartcard 1 reset invert.

Off = Invert, On = No invert

Config10 - Smartcard 1 data link.

Off = data in + out linked.

Config11 - Smartcard 1 voltage.

On = 3V, Off = 5V


Config0 - NOR/NAND boot select.

On = NOR, Off = NAND

Config1 - DACmode(0)

Config2 - DACmode(1)

Config3 - Unused


TS mode software/switch controlled.

On = software, Off = Switch

Unused.

Unused.

Serial data input swap.

On = D0/D7 swapped, Off = No swap


TS Mode(0)

TS Mode(1)

TS Mode(2)

TS Mode(3)

Front panel power On/Off push button

Front panel reset push button

Default

On

On

Off

On

On

Off

On

N/A

134/160 8149405


Figure 93.


Note: In


8149405 135/160

PIO alternate functions

Appendix H PIO alternate functions


The following tables show the PIO alternate functions used by the board for PIO0 to PIO4.

A complete list of PIO assignments is in the STi5197 datasheet (ADCS 8148435).

Table 85.

PIO functions for PIO0

Bit Function Alternate function 1

0

1

SC0_DATAOUT/

ASC0_TXD

SC0_DATAIN/

ASC0_RXD

2 SC0_CG_EXTCLK

3 SC0_CG_CLK

4 SC0_RESET

5 SC0_COMD_VCC

6 SC0_DIR/ASC0_notOE

7 SC0_DETECT

Alternate function 2 Alternate function 3

ICAM_SC0_C4_DINOUT

ICAM_SC0_C7_DINOUT

ICAM_SC0_C8_DINOUT

ICAM_SC0_CG_CLK

ICAM_SC0_RESET

ICAM_SC0_notSETVCC

ICAM_SC0_notSETVPP

ICAM_SC0_DETECT

Table 86.



6

7

4

5

2

3

0 QPSK_I2C_CLOCK_IN

1

QPSK_I2C_DATA_

INPUT

ASC2_TXD

ASC2_RXD

ASC2_RTS

ASC2_CTS

Alternate function 2

SSC0_SCLKINOUT

SSC0_MTSR_DINOUT


136/160 8149405

STi5197-MBoard, STi5189/97-MB PIO alternate functions

Table 87.



0

1

2

5

6

3 GPIO/DVBCI_RESET

4 GPIO/DVBCI_CD1

7

ASC3_TXD

ASC3_RXD

ASC3_CTS

ASC3_RTS

IRB_PPM_OUT


PCM_DATAOUT

PCM_LRCLKOUT

PCM_SCLKOUT

PCM_MCLK

PCM_SCLKIN

IRB_PPM_IN

PCM_DATAIN

PCM_LRCLKIN


Table 88.


Bit Function

0

1 GPIO

(2)


EXTINT0

(1)

EXTINT2

2

3

4

5 GPIO/DVBCI_BUS_REQ

6 GPIO/DVBCI_BUS_GNT

7

SSC2_MTSR_DINOUT

SSC2_SCLKINOUT

EXTINT1

DVO output clock


PAD_VSYNC

PAD_VSYNC_EN

PAD_HSYNC

PAD_HSYNC_EN


1.

EXTINT0 is used for HDMI interrupt.

2.

GPIO is used for USB VBUS overcurrent detect. A wire modification may be required on some MB704 board variants if this feature is required.

Table 89.


Bit Function Alternate function 1 Alternate function 3

0 DVO_DATA

1 DVO_DATA

2 DVO_DATA

3 DVO_DATA

4 DVO_DATA

5 DVO_DATA

6 DVO_DATA

7 DVO_DATA


SC1_DATAINOUT/

ASC1_TXD

ASC1_RXD

SC1_CG_EXTCLK/

ASC1_RTS

SC1_CG_CLK

SC1_RESET

SC1_COMD_VCC

SC1_DIR/ASC1_notOE

SC1_DETECT

8149405 137/160

Hardware configuration guide STi5197-MBoard, STi5189/97-MB

Appendix I Hardware configuration guide

The MB829 and MB762 peripheral boards have two EPLD devices. These split the board

functions into two parts, FMI (see Section I.1

) and transport stream (see Section I.2 on page

147 ).

●

●

●

●

●

●

●

●

●

●

For the FMI, an Altera EPM3256AQC208-7N EPLD device is used. This is IC23 on the

MB762, or IC18 on the MB829. This device controls:

FMI memory devices: NAND, NOR and STEM audio modes (PCM DAC)

DVBCI modes

ATAPI peripheral device resets

TS EPLD software modes configuration switch inputs smartcard

SPI control interrupts

For the transport stream, an Altera EPM3256ATC144-10N EPLD device is used. This is

IC24 on the MB762, or IC19 on the MB829. This device controls the transport stream MUX and Ethernet modes.

This section provides information on the FMI EPLD. It includes:

●

●

●

Section I.1.1: FMI decoding

Section I.1.2: FMI EPLD register map on page 139

Section I.1.3: FMI EPLD register descriptions on page 140

Note:

Table 90

details the FMI address decoding map for the FMI EPLD.

There is no FMI present on the MB704.

Table 90.

FMI address decoding for FMI EPLD

FMI bank Address

Bank 0 (FMI_CSA)

Bank 1 (FMI_CSB)

Bank 2 (FMI_CSC)

0xA0000000 - 0xA23FFFFF

0xA2400000 - 0xA24FFFFF

0xA2500000 - 0xA27FFFFF

0xA2800000 - 0xA3FFFFFF


Mapping

NOR/NAND Flash

FMI EPLD registers

ATAPI device

Reserved

DVBCI

138/160 8149405

STi5197-MBoard, STi5189/97-MB Hardware configuration guide

Table 90.

FMI address decoding for FMI EPLD (continued)

FMI bank Address

Bank 3 (FMI_CSD)

0xA5000000 - 0xA5BFFFFF

0xA5C00000 - 0xA5DFFFFF

0xA5E00000 - 0xA5FFFFFF


Reserved

STEM 0

STEM 1

Reserved

Mapping

I.1.2 FMI EPLD register map

In addition to basic control logic, the FMI EPLD has a set of registers mapped to a region of

FMI memory to allow software control of various functions. A summary of these registers is

given in Table 91 and more detail is provided in

Section I.1.3 on page 140

.

These registers are only available on systems using an MB676 processor board.

Note:

Table 91.

FMI EPLD registers

Register Description Address

Ident

Test

Switch0

Switch1

Reset

Smartcard

Stores EPLD version number

Test register

Status of external mode switches

Status of external mode switches

Individual reset of peripheral devices

Controls smartcard hardware settings

0xA2400000 Ident

0xA2408000 0xC3

0xA2410000 Ext

(1)

0xA2418000 Ext

(1)

0xA2420000 0x00

0xA2428000 Ext

(1)

DVBCI control

TS EPLD

Misc control

Controls DVBCI functions

Controls various functions in the Transport EPLD

Controls miscellaneous functions

0xA2448000

0xA2438000

0xA2440000

0x00

0x00

0x00

SPI control

Audio control

Controls SPI functions

Controls audio functions

0xA2448000 0x00

0xA2450000 Ext

(1)

Address control

Allows FMI address bits 25:24 to be set. For use with NOR

Flash (bit 24 only) or STEM interface.

0xA2458000 0x00

Interrupt status Shows status of incoming peripheral interrupts

(2)

0xA2480000 Ext

(1)

Interrupt mask Masks various interrupts 0xA2488000 0x00

SCART interrupt

Sets interrupt priority (maps to 1 of 3 hardware interrupt lines)

(3)

0xA2490000 0x00

DVBCI interrupt Sets interrupt priority (maps to 1 of 3 hardware interrupt lines) 0xA2498000 0x00

ATAPI interrupt Sets interrupt priority (maps to 1 of 3 hardware interrupt lines) 0xA24A0000 0x00

STEM0 interrupt Sets interrupt priority (maps to 1 of 3 hardware interrupt lines) 0xA24A8000 0x00

STEM1 interrupt Sets interrupt priority (maps to 1 of 3 hardware interrupt lines) 0xA24B0000 0x00

Down2 interrupt


(4)

0xA24B8000 0x00

Reset RW

RW

RW

RW

RW

RW

RO

RW

RO

RO

RW

RW

RW

RO

RW

RW

RW

RW

RW

RW

RW

8149405 139/160


Table 91.

FMI EPLD registers (continued)

Register Description Address Reset RW

Down1 interrupt

Down0 interrupt


(2)

Sets interrupt priority (maps to 1 of 3 hardware interrupt lines). This is the HDMI interrupt from the processor module.

0xA24C0000 0x00

0xA24C8000 0x00

1.

A reset value of “Ext” denotes a register whose initial value at reset depends on the logic status of device signals or switch/jumper settings.

2.

This register is not implemented on the MB762.

3.

This register is not implemented on the MB829.

4.

This register is not currently implemented on either the MB762 or MB829.

RW

RW

I.1.3 FMI EPLD register descriptions

Ident register

This read-only ident register contains both the board revision (3 bits) and EPLD revision

(5 bits).

Table 92.

Ident register bits

Data bit

D(7:5)

D(4:0)

Register description

Board revision: 000 = A, 001 = B, and so on.

EPLD revision: 00000 = 00, 00001 = 01, 00010 = 02, and so on.

Test register

This read/write register is used to test EMI accesses. It resets to 0x55. When written to, it returns the inverse value of the write.

Table 93.

Test register bits

Data bit

D(7:0)


Reads inverse value of what is written

Value at reset

11000011 bin

Switch0 register

This read-only register gives the status of switches SW1 and SW3.

See

Table 116: MB762/MB829 mode switches on page 153

for switch functions.

Table 94.

Switch 0 register bits

Data bit Register description

D7

D6

D5

D4

SW1-4 switch position. 0 = ON, 1 = OFF




Value at reset

SW1-4

SW1-3

SW1-2

SW1-1

140/160 8149405


Table 94.

Switch 0 register bits (continued)


D3

D2

D1

D0





Hardware configuration guide

Value at reset

SW3-4

SW3-3

SW3-2

SW3-1

Switch1 register

This read-only register gives the status of switch SW2.

See

Table 116: MB762/MB829 mode switches on page 153

for switch functions.

Table 95.

Switch 1 register bits


D[7:4]

D3

D2

D1

D0

Reserved





Value at reset

0000 bin

SW3-4

SW3-3

SW3-2

SW3-1

Reset register

This read/write register allows individual peripheral devices to be reset.

The corresponding reset active low output to the device is the inverse of the register bit.

Writing a “1” to the corresponding bit holds the device in reset. Writing a “0” brings the device out of reset. The default value is “0”, that is, all devices active.

All devices are held in reset during an EPLD reset or power on reset.

Table 96.

Reset register bits

Data bit

D7

D6

D5

D4

D3

D2

D1

D0

Register description Value at reset

MB762 reserved, MB829 TSEPLD_notRESET.

0

PCMDAC_notRESET. Reset to AK43881 audio DAC.

0

DVB_notRESET. 0

NORFLASH_notRESET.

0

STEM_notRESET.

ATAPI_notRESET.

0

0

TSCONN_notRESET.

NIM_notRESET.

0

0

8149405 141/160


Smartcard register

This read/write register allows various different smartcard hardware configurations to be set by software.

Table 97.

Smartcard register bits


D7

D6

D5

D4

D3

D2

D1

D0

Reserved

Smartcard B 5Vnot3V. 1 = 5V, 0 = 3V.

Smartcard B data link

1=data in and data out bridged. 0= not bridged.

Smartcard B reset invert. 1=inverted, 0=not inverted

Reserved

Smartcard A 5Vnot3V. 1 = 5V, 0 = 3V.

Smartcard A data link.

1=data in and data out bridged. 0= not bridged.

Smartcard A reset invert. 1=inverted, 0=not inverted

Value at reset

0

SW2-4

SW2-3

SW2-2

0

SW2-1

SW1-4

SW1-3

DVBCI control register

This read/write register allows DVBCI control signals to be set up by software.

Table 98.

DVBCI control bits

Data bit

D[7:5]

D4

D3

D2

D1

D0


Reserved

DVBCI address and data buffer enable. 1= enabled, 0=disabled

DVB_VCC3EN

DVB_VCC5EN

DVB_EN1

DVB_EN0

Value at reset

000 bin

0

0

0

0

0

TS EPLD register

This read/write register controls different modes for the transport EPLD.

See

Section I.2: Transport stream EPLD on page 147

for definition of TSMode bits.

Table 99.

TS EPLD register bits


D[7:5]

D4

D[3:0]

Reserved

NOR or NAND Flash select: 0 = NOR Flash, 1 = NAND Flash

TSMODE[3:0]

Value at reset

000 bin

SW3-1

0000bin

142/160 8149405


Note:


Misc control register

Table 100.

Misc control register bits


D[7:5]

D4

D3

D2

D1

D0

Reserved

BTSC modulator loop control (MB762 only).

LVDS spare 3 (MB762 only)

LVDS spare 2

LVDS spare 1

NOR Flash VPEN signal. 1= enabled, 0= disabled

Value at reset

000 bin

SW3-4

0

0

0

0

SPI control register

This read/write register allows SPI control signals to be set up by software.

The board jumper settings may need to be changed to allow this register control of the serial

Flash devices.

Table 101.

SPI control register bits


D[7:3]

D2

D1

D0

Reserved

SPI_notPROT

SPI_notHOLD

SPI_notEPLDCS

Value at reset

00000 bin

SW1-2

SW1-1

0

Audio control register

This read/write register allows various different audio configurations to be set up by software.

The reset value is dependant on the settings of SW3-2 and SW3-3.

●

●

When both switches are ON, the default value is 0x0B (00001011 bin).

For any other combination of switch settings, the default value is 0x04 (00000100 bin).

Section I.6: Audio on page 155 provides more details.

Table 102.

Audio control register bits


D[7:5]

D4

D3

D2

D1

D0

Reserved

Audio DAC DEM signal

Audio DAC ACKS signal

Audio DAC SMUTE signal

Audio DAC DIF1 signal

Audio DAC DIF0 signal

Value at reset

000 bin

SW3-3, SW3-2

SW3-3, SW3-2

SW3-3, SW3-2

SW3-3, SW3-2

SW3-3, SW3-2

8149405 143/160


Address control register

This read/write register allows FMI address bits [25:24] to be controlled by software.

Table 103.

Address control register bits


D[7:2]

D1

D0

Reserved

FMI address bit 25

FMI address bit 24

Value at reset

000000

0

0

Note:

Interrupt status register

This read-only register allows the status of the various peripheral interrupt inputs to the

EPLD to be read by software.

The value in the register is the inverse of the actual incoming interrupt signal.

Table 104.

Interrupt status register bits


D7

D6

D5

D4

D3

D2

D1

D0

SCART interrupt

DVBCI interrupt

ATAPI interrupt

STEM1 interrupt

STEM0 interrupt

INTDOWN2

(1)

INTDOWN1

(2)

INTDOWN0 HDMI interrupt from processor module.

1.

Not implemented.

2.

Not available on the MB762.

Value at reset

0

0

0

0

0

0

0

0

Interrupt mask register

This read/write register allows individual interrupts to be enabled by software. Setting the corresponding bit to “1” enables that interrupt. Setting the bit to “0” disables the interrupt. All interrupts are disabled by default.

Table 105.

Interrupt mask register bits


D7

D6

D5

D4

D3

SCART interrupt (active low)

DVBCI interrupt (active low)

ATAPI interrupt (active low)

STEM1 interrupt (active low)

STEM0 interrupt (active low)

Value at reset

0

0

0

0

0

144/160 8149405


Note:


Table 105.

Interrupt mask register bits (continued)

Data bit

D2

D1

D0


INTDOWN2 (active high)

(1)

INTDOWN1 (active high)

(2)

INTDOWN0 (active low). HDMI interrupt from processor module.

1.

Not implemented.

2.

Not available on the MB762.

SCART interrupt priority register

This read/write register sets which INTUP[n] maps to this interrupt.

This is available on MB762 only.

Table 106.

SCART interrupt priority register bits


D[7:2]

D[1:0]

Reserved

00 = map to INTUP0

01 = map to INTUP1

10 = map to INTUP2

11= reserved (maps to nothing).

DVBCI interrupt priority register


Table 107.

DVBCI interrupt priority register bits


D[7:2]

D[1:0]

Reserved

00 = map to INTUP0

01 = map to INTUP1

10 = map to INTUP2


ATAPI interrupt priority register


Table 108.

ATAPI interrupt priority register bits


D[7:2]

D[1:0]

Reserved

00 = map to INTUP0

01 = map to INTUP1

10 = map to INTUP2


Value at reset

0

0

0

Value at reset

000000 bin

00 bin

Value at reset

000000 bin

00 bin

Value at reset

000000 bin

00 bin

8149405 145/160


STEM0 interrupt priority register


Table 109.

STEM0 interrupt priority register bits


D[7:2]

D[1:0]

Reserved

00 = map to INTUP0

01 = map to INTUP1

10 = map to INTUP2


Value at reset

000000 bin

00 bin

STEM1 interrupt priority register


Table 110.

STEM1 interrupt priority register bits


D[7:2]

D[1:0]

Reserved

00 = map to INTUP0

01 = map to INTUP1

10 = map to INTUP2


Up2 interrupt priority register


Table 111.

Up2 Interrupt priority register bits


D[7:2]

D[1:0]

Reserved

00 = map to INTUP0

01 = map to INTUP1

10 = map to INTUP2




Table 112.

Up1 interrupt priority register bits


D[7:2]

D[1:0]

Reserved

00 = map to INTUP0

01 = map to INTUP1

10 = map to INTUP2


Value at reset

000000 bin

00 bin

Value at reset

000000 bin

00 bin

Value at reset

000000 bin

00 bin

146/160 8149405




Table 113.

Up0 interrupt priority register bits


D[7:2]

D[1:0]

Reserved

00 = map to INTUP0

01 = map to INTUP1

10 = map to INTUP2


Value at reset

000000 bin

00 bin

I.2 Transport stream EPLD

Ethernet and transport stream are shared functions on the same pins. Figure 94 is a block

diagram of the transport stream and Ethernet subsystem.

Figure 94.

Transport stream and Ethernet MUXing overview

Config switches

Peripheral board

(STi5197/89)

FMI

Address S/W

Decode Config

TS EPLD

Ethernet

LAN8700

TS Out

NIM

TS In

DVBCI

CableCARD

Debug TS header

(MB829)

The different modes of operation are handled by the transport stream EPLD (TS EPLD) and

are selectable using switch SW5 or using software. Table 114 details the different mode bit

and switch settings.

To set the mode bits using switch SW5, SW4-1 should be set to the OFF position.

To set the mode bits using software, SW4-1 should be set to the ON position.

Setting the mode bits using software is only possible with an MB676 processor module, as the MB704 module (STi5197 15x15) does not have FMI. The mode bits are set by a software write through an FMI access to the TS EPLD register using the FMI EPLD.

The different modes are illustrated in

Section I.2.1

.

8149405 147/160


Table 114.

TS mode/Ethernet selection

Mode

SW5-4 or bit3

SW5-3 or bit2

SW5-2 or bit1

SW5-1 or bit0

0000

0001

0010

0011

0100

1001

1010

OFF (0)

OFF (0)

OFF (0)

OFF (0)

OFF (0)

ON (1)

ON (1)

OFF (0)

OFF (0)

OFF (0)

OFF (0)

ON (1)

OFF (0)

OFF (0)

OFF (0)

OFF (0)

ON (1)

ON (1)

OFF (0)

OFF (0)

ON (1)

Description

OFF (0) TSOUT to TSIN loopback

ON (1) TSOUT to TSIN through DVBCI

OFF (0) NIM to TSIN

ON (1) NIM to TSIN through DVBCI

OFF (0) NIM to TSIN and TSOUT

ON (1) MII Ethernet mode and serial TSin

OFF (0) RMII Ethernet mode and parallel TSin

I.2.1 TS mode descriptions

Mode 0000 - TSout to TSin loopback

TS mode register = 0x00, SW5 = OFF OFF OFF OFF.

Figure 95.

TSout to TSin loopback

Peripheral board

(STi5197/89)

Debug TS header

(MB829)

TS Out

TS EPLD

Ethernet

LAN8700

NIM

TS In

DVBCI

CableCARD

148/160 8149405


Mode 0001 - TSout to TSin through DVBCI

TS mode register = 0x01, SW5 = OFF OFF OFF ON.

Figure 96.

TSout to TSin through DVBCI

Peripheral board

(STi5197/89)

Debug TS header

(MB829)

TS Out

TS EPLD


Ethernet

LAN8700

NIM

TS In

DVBCI

CableCARD

Mode 0010 - NIM to TSin

TS mode register = 0x02, SW5 = OFF OFF ON OFF.

Figure 97.

NIM to TSin

Peripheral board

(STi5197/89)

Debug TS header

(MB829)

TS Out

TS EPLD

Ethernet

LAN8700

NIM

TS In

DVBCI

CableCARD

8149405 149/160


Mode 0011 - NIM to TSin through DVBCI

TS mode register = 0x03, SW5 = OFF OFF ON ON.

Figure 98.

NIM to TSin through DVBCI

Peripheral board

(STi5197/89)

Debug TS header

(MB829)

TS Out

TS EPLD


Ethernet

LAN8700

NIM

TS In

DVBCI

CableCARD

Mode 0100 - NIM to TSin and TSout

TS mode register = 0x04, SW5 = OFF ON OFF OFF.

Figure 99.

NIM to TSin and TSout

Peripheral board

(STi5197/89)

Debug TS header

(MB829)

TS Out

TS EPLD

Ethernet

LAN8700

NIM

TS In

DVBCI

CableCARD

150/160 8149405


Mode 1001 - MII Ethernet and serial TSin

TS mode register = 0x09, SW5 = ON OFF OFF ON.

Figure 100. MII Ethernet and serial TSin

Peripheral board

(STi5197/89)

Debug TS header

(MB829)

TS Out

TS EPLD


Ethernet

LAN8700

NIM

TS In

DVBCI

CableCARD

Mode 1010 - RMII Ethernet and Parallel TSin

TS mode register = 0x0A, SW5 = ON OFF ON OFF.

Figure 101. RMI Ethernet and parallel TSin

Peripheral board

(STi5197/89)

Debug TS header

(MB829)

TS Out

TS EPLD

Ethernet

LAN8700

NIM

TS In

DVBCI

CableCARD

8149405 151/160


I.3


EPLD programming instructions

The EPLDs can be programmed using two different methods:

● LVDS connector from the ST Micro Connect 2

This is the simplest, and more commonly used, method. The LVDS host interface connection can be used to program the EPLD chain using an STMC2 and the associated software. The connector is CN2 for the MB762, or CN10 for the MB829.

See

Section I.3.1: Programming EPLDs using the LVDS connection

.

● Altera ByteBlaster interface

An Altera ByteBlaster/ByteBlaster II cable is connected to the parallel port of the PC and the JTAG chain connector on the board, CN16 on the MB762 or CN11 on the

MB829. The programming is done using the Quartus programmer tool installed on the

PC. See Section I.3.2: JTAG chain setup for use with ByteBlaster connector

CN16/CN11 for the programmer setup.

I.3.2

Note:

●

●

●

The following are required to program EPLDs using the LVDS connection:

ST Micro Connect 2 with LVDS to LVDS cable

ST Micro Connection software R1.2.1 or higher

JBC programming file ( .jbc

file)

To program the EPLDs, run the command: epldprog --convertor STMC_Type_G <STMC2 name> <board> .jbc

JTAG chain setup for use with ByteBlaster connector CN16/CN11

To program the EPLDs using the Altera ByteBlaster interface, a ByteBlaster or ByteBlasterII cable can be used.

In the Quartus programmer tool, DEVICE_1 and DEVICE_2 must be setup as follows:

DEVICE_1: EPLD device type (EPM3256AQ208)

( source_disk \ source_dir \fmi_epld.pof

)

DEVICE_2: EPLD device type (EPM3256ATC144)

( source_disk\source_dir \ts_epld.pof

)

When using the .jbc

programming file, there is only a single file which holds the JTAG chain sequence as well as the programming information for each of the three EPLDs.

152/160 8149405


I.4

Note:


General mode switch settings


detail the board switch options.

The MB704 does not have any option switches.

Table 115.

MB676 mode switches

Switch Function

SW2-1

SW2-2

NAND Flash address type.

SW2-3

Boot mode. Select processor boot device.

SW2-4

SW3-1

SW3-2

SW3-3

SW3-4

Reset period.

Boot device width.

NAND Flash offset remap.

Serial Flash type.

NAND Flash page size.

On (0) Off (1)

Long addressing Short addressing

SW2-2 On, SW2-3 On = NOR

SW2-2 On, SW2-3 Off = SPI

SW2-2 Off, SW2-3 On = NAND

SW2-2 Off, SW2-3 Off = MPX

200 ms stretch Normal

16-bit

Reserved

Older Atmel only

Small

8-bit

Remap

ST + other Atmel

Large

SW1-4

SW2-1

SW2-2

SW2-3

SW2-4

SW3-1

SW3-2

SW3-3

SW3-4

SW4-1

SW4-2

SW4-3

SW4-4

Table 116.

MB762/MB829 mode switches

Switch Function

SW1-1

SW1-2

SW1-3

SPI_notHOLD

SPI_notPROT

Smartcard 0 reset invert

On (0)

Hold active/asserted

Write protect

No reset inversion

Smartcard 0 data link

Smartcard 0 voltage

Smartcard 1 reset invert

Smartcard 1 data link

Smartcard 1 voltage

Flash device select

No data out/in link

3 volts

No reset inversion

No data out/in link

3 volts

NOR

Audio DAC mode. See

Section I.6: Audio on page 155

RF modulator loop control (MB762 only)

TSmode control

Unused

Unused

Serial data input swap

LoopCtrl = low

TS EPLD register

NIM D7 linked to

STi5197 D0

Off (1)

Inactive/deasserted

Read/write allowed

Reset inverted

Data out linked to data in

5 volts

Reset inverted

Data out linked to data in

5 volts

NAND

LoopCtrl = high

SW5

NIM serial data from D0

8149405 153/160


Table 116.

MB762/MB829 mode switches (continued)

Switch Function On (0)

SW5-1

SW5-2

SW5-3

SW5-4

Off (1)

TS Mode. See

Section I.2.1: TS mode descriptions on page 148

for details.

I.5 Video

On the MB762, video out is available through:

●

●

SCART as composite video or RGB a single phono connector (CN4) as composite video

The jumper J7 selects the routing of the composite out (CVBS) video signal.

Figure 102. MB762 video diagram

Processor board

XOUT

CVBS

Jumper

Filter options

CVBS

Phono

SCART Out

UOUT

VOUT

WOUT

Red / C

Green / Y

Blue

STV6417

SCART switch

SCART In

RF modulator

(BTSC)

On the MB829, the SCART switch and BTSC modulator have been removed, see

Figure 103 . CN5 has the CVBS output, and CN6, CN7 and CN8 are used for RGB or

component video out.

154/160 8149405


Figure 103. MB829 video diagram

Processor board

XOUT

CVBS


Filter options

CVBS

CVBS phono

UOUT

VOUT

WOUT

Red / C

Green / Y

Blue

Video buffer

I.6 Audio

Two default audio mode settings can be set using a combination of SW3-2 and SW3-3.

When SW3-2 and SW3-3 are both ON:

●

●

●

Audio register default value = 0x0B (00001011 bin)

I2S mode, de-emphasis off, audio mode, mute disabled

DEM = 0, ACKS = 1, SMUTE = 0, DIF1 = 1, DIF0 = 1

●

●

For any other combination of SW3-2 and SW3-3:

Audio register default value = 0x04 (00000100 bin)

DEM = 0, ACKS = 0, SMUTE = 1, DIF0 = 0, DIF0 = 0

Other settings can be achieved by writing a value directly to the Audio Control register

For a full description of the settings, see the STi5197 datasheet (ADCS 8148435) and

STi5197 programming manual (ADCS 8148435).

Red/Cr phono

Green/Y phono

Blue/Cb phono

8149405 155/160


●

●

●

Three SPI serial Flash devices are available, one on the processor board and two on the peripheral board. These are:

Atmel AT45DB321 32-Mbit on the processor board

ST M25P80 8-Mbit on the peripheral board

ST M25P32 32-Mbit on the peripheral board

Figure 104 shows the routing of the SPI chip select through jumpers, to control which device

is active. Jumpers Ja, Jb and Jc are detailed in

Table 117

.

Figure 104. MB704/MB829 SPI Flash devices: chip select configuration

Processor board (MB704)

STi5197

SPI_notCS

Ja

EPLD control

Peripheral board

M25P80

Jb Jc

AT45

M25P32

Table 117.

SPI_notCS selection jumpers

Jumper Function Board reference

Ja

Jb

Jc

Select AT45 device or peripheral board devices

MB704 J10

Peripheral board SPI_notCS source select

Peripheral board serial device select

MB829 J8-A

MB829 J8-B

Setting

1-2 = AT45

2-3 = Peripheral board

1-2 = notCS from EPLD

2-3 = notCS from the processor board

1-2 = M25P80 device

2-3 = M25P32 device

156/160 8149405


I.8 I

2

C devices

The I

2

C connectivity for the boards is described in

Section 5.6: Serial I

2

C buses on page 21

.

Table 118 shows an example of the I

2

C bus devices and addresses for the MB704 processor with MB762 peripheral boards system.

Note: The SCART device is not present on the MB829.

Table 118.

I

2

C bus devices and addresses

Device

PCF8575 PIO expander (MB704)

SII9024 HDMI encoder (MB704)

NIM socket (MB762)

LNBH23 (MB762)

Bus

SSC0

SSC0

SSC0

SSC0

STi5197 internal QAM decoder (MB704) QAM

DCT7070x QAM demodulator (MB704)

I

2

C EEPROM

STV6417 SCART switch

QAM

SSC1

SSC1

Default address

0x4E/4F

0x76/0x77

0xC4/0xC5

0x7E/0x7F

Varies

0x16/0x17

0x38/0x39

0xC0/0xC1

0xA0/0xA1

0x96/0x97

Possible addresses

0x40 - 0x4F

0x76/77, 0x72/73

0xC4/C5, 0xC0/C1

0x7E/7F, 0x7A/7B

Device dependant

0x16/17, 0x14/15

See STi5197 datasheet

(ADCS 8148435)

0xC0/C1, OxC6/C7

0xA0 - 0xAF

0x96/0x97

8149405 157/160

Glossary

Appendix J Glossary

MCM

MII

NIM

PCI

PCMCIA

RMII

SATA

SD

STEM

TS

UART

VHDCI

EPLD

FPGA

HD

HDMI

LMI

LVDS

MAFE

Mbs

ATAPI

ATX

BGA

BTSC

CVBS

DAA

EMI


Advanced technology attachment packet interface

Advanced technology extended (motherboard type)

Ball grid array (type of integrated circuit)

Broadcast television systems comittee (multichannel television surround)

Composite video blanking synchronization

Direct access arrangement

External memory interface

Electrically programmable logic device

Field programmable gate array

High definition

High definition multimedia interface/high-density multichip interconnect

Local memory interface

Low voltage differential signalling

Modem analog front end

Megabits per second

Multi chip module

Media independent interface

Network interface module

Peripheral component interconnect

Peripheral component microchannel interconnect architecture

Reduced media independent interface

Serial advanced technology attachment (hard disk interface)

Standard definition

Set top expansion module

Transport stream

Universal asynchronous receiver-transmitter

Very high density cable interconnect

158/160 8149405


Revision history

Revision history

Table 119.

Document revision history

Date Revision

16-Jun-2009

21-May-2009

14-Jan-2009

15-Dec-2008

D

C

B

A

Changes

Added information to Appendix I: Hardware configuration guide on page 138

.

Updated throughout for Revision C and later boards. Added details of the MB829 peripheral board.

Added:

–

Chapter 6: MB829 SD modular validation peripheral board on page 28

–

Appendix C: MB829 SD modular validation peripheral board connectors on page 85

–

Appendix G: MB829 SD modular validation peripheral board jumpers, option resistors and switches on page 130

Updated Section 2.1: Equipment and software on page 10

.

Corrected system requirements in Chapter 2: System overview on page 9 .

Replaced incorrect mention of DCU with JTAG in

Chapter 3 , Figure 2 on page 11

and Chapter 5

, Figure 4 on page 19

.

Added the warning to

Chapter 4: MB676/MB704 processor board on page 13

.

Updated Figure 5: I

2

C connectivity on page 22 .

Updated smartcard descriptions in Section 5.7: Smartcard slots on page 22

.

Added Appendix I: Hardware configuration guide on page 138 (information will be completed when available).

Initial release

8149405 159/160


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160/160 8149405

STMicroelectronics Evaluation boards for low-cost SD TV decoder using the STi5189/STi5197 SoC Datasheet

Evaluation boards for low-cost SD TV decoder using the STi5189/STi5197 SoC

Contents

1 Introduction

4 MB676/MB704 processor board

5

MB762 SD generic peripheral board

6

MB829 SD modular validation peripheral board

Appendix A MB676/MB704 processor board connectors

Appendix B MB762 SD generic peripheral board connectors

Appendix C MB829 SD modular validation peripheral board connectors

Appendix D MB676 23 x 23 processor board jumpers, option resistors and switches

Appendix E MB704 15 x 15 processor board jumpers, option resistors and switches

Appendix F MB762 SD generic peripheral board jumpers, option resistors and switches

Appendix G MB829 SD modular validation peripheral board jumpers, option resistors and switches

Appendix H PIO alternate functions

Appendix I Hardware configuration guide

Ident register

Test register

Switch0 register

Switch1 register

Reset register

Smartcard register

DVBCI control register

TS EPLD register

Misc control register

SPI control register

Audio control register

Address control register

Interrupt status register

Interrupt mask register

SCART interrupt priority register

DVBCI interrupt priority register

ATAPI interrupt priority register

STEM0 interrupt priority register

STEM1 interrupt priority register

Up2 interrupt priority register

Up1 interrupt priority register

Up0 interrupt priority register

Mode 0000 - TSout to TSin loopback

Mode 0001 - TSout to TSin through DVBCI

Mode 0010 - NIM to TSin

Mode 0011 - NIM to TSin through DVBCI

Mode 0100 - NIM to TSin and TSout

Mode 1001 - MII Ethernet and serial TSin

Mode 1010 - RMII Ethernet and Parallel TSin

2

Appendix J Glossary

Revision history

Key Features

Related manuals

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ST

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SUPERH ST40 SYSTEM ARCHITECTURE VOLUME 3: VIDEODEVICES

Tri-M Systems

TCB1000 Series

Frequently Answers and Questions

What interfaces are supported by the device?

What types of memory does the device have?

What are the power requirements of the device?

What operating systems does the device support?

What is the purpose of the device?

Table of contents