advertisement
RX8/RX11 floppy disk system maintenance manual
L....------digital equipment corporation. maynard. massachusetts-----......I
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RX8/RX11 floppy· disk ,ystem ma i
ntenance:;}manual
EK-RXOI-MM-002
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digital equipment corporation · maynard. massachusetl;s
5179,15
Copyright © 1975,1976 by Digital Equipment Corporation
The
material. in this manual. is for informational purposes and
is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility foriuty errors which may appear in this manual.
Printed in U.s.A.
Ist Edition, May 1975
2nd Printing (Rev), September 1975
3rd Printing, July 1976
4th Printing (Rev), December 1976
( c
(
The
following
are
,trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystem-l0
DECSYSTEM-20
DECtape
DEeUS·
DIGITAL
M{\SSBUS
PDP
RSTS
TYPESET-8
TYPESET-II
UNIBUS
(
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CHAPTER 2
2,3.4
2.3.5
2.4
2.4.1
2.4.2
2.4.3
2.4.3.1
2.4.3.2
2.4.4
2.5
2.5.1
2.5.2
2.5.3
2.5.3.1
2.5.3.2
2.~.4
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2jj
CHAPTER 1
1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.3
1.3.1
1.3.2
1.3.3
1.3.3.1
1.3.3.2
1.3.3.3
1.3.3.4
1.4
1.5
'1.6
CONTENTS
Page
GENERAL INFORMATION
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . .
PHYSICAL DESCRIPTION . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . 1-1
Rx8E/RXll Interfaces . . . . . . . . . . . . . . . . . • . . . . . . . . . . • • . . 1·2
Microprogrammed Controll~r . . . . . . . . . . • . . . . . . .
0 • • •
Read/Write Electronics . . . . . . . . . . . . . . . . . . . . . . . . ~ ,
•
0
•
,
•
•
•
•
•
•
• •
• •
1·2
1
~2
Electro·Mechanical Drive . . . , . . . . . . . . . . . . . " . . . . . . . . . . . . , 1·2
Power Supply . . . • . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . 1·3
SYSTEMS COMPATIBILITY . . . . . . . . . . . . . . . • . . , . • . . , . . . . . . . . 1·3
Media • . . . . . . . • . . . . , . . . . . . . . . . . . . . . " . . . . . . . , . , . 1·3
Recording Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1·10
Header Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . • • . . 1·10
Data Field Description . . . . . . . . . . . , • . . . • • . . . . . . , . . . . . HI
Track Usage . . . . . . • . . , . . . . , . . . . . . . . . • . . • , . . . • . • 1·11
CRC Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . 1·12
APPLICABLE INSTRUCTION MANUALS . . . . . . . . . . . , . . . , . . . " . , . . 1·12
CONFIGURATION . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . • 1·12
SPECIFICATIONS . . . . . . , . . ' . . . . . . . . . . . . ~ . . . . ' • . . . . . . , . . . . 1·13
INSTALLATION
AND
OPERATION
PURPOSE AND ORGANIZATION . . . . . . . . . . . . . . . , . . ' . . , . . . . . . . , 2·1
SITE PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . 2·1
Space . . . . . . . . . . . . . . , . . . . . . . , . . , . . . . , . . • • . . . . . o .
2·1
Cabling . . . . . .' . . . . , . . , . . , . . . . . . . . . . . . . , . . , • . . . . . . . 2·1
AC Power . . . . , . . . . . . . . . . . . . . . . . . . . . , . . . . . . ~ . • ,
' !
2·1
Fire and Safety Precautions ; . . . . . . . . . ' . , . . . . . . .
0 , • • • • • • • • •
2·2
ENVIRONMENTAL CONSIDERATIONS . . . . . . . . . . . . . . . . . . , . , . . • . , 2·2
General . . . . . . . . . . . . . . . . . . . , . • , . , . . . . . , . . . • •
0 • . . ,
2·2
Temperature, Relative Humidity . . . . . . . . . • . . . . . . . . . . . . . . • . . . 2·3
Heat Dissipation . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . " . , . . 2-4
Radiated Emissions . . . . . . . . . . . . . . . . . . . . , . .
Cleanliness . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . • .
0 • • . ,
2·4
INSTALLATION . . . . . . . . . . . . . . . . . . . . . . • . . . •
• • 0 • , • • • , .
2-4
General . . . . . . . . . . . . . . . . . . . .. . . .
0 • • • • • . . • • • • • , • • • ' 0
2·4
Tools . . . . . . . . . . . . , . , . . . . . . . . . . . . . . . . .
0 • • • • • • , "
2·4
Unpacking and Inspection . . . . . . . , . " . . . . . . . . . , . , . , . . . . , . . 24
Cabinet.Mounted . . . . . . . . . . . • . . . . . . . . . . : . . . . . , . . . . 24
Separate Container . . . . . . . . . . . . . . . . , . . . . . . . . . , . . . , . . ' 2·6
Installation . . . . . . . . . . . . . . . . . . . . . . . , ' , . . . . . , . . . . . . . . 2·6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . .
2-8
Operator Control . . . . . . . . . , . . . . . , . . . . . . . • . • . . . . , . . . . . 2·8
Diskette Handling Practices and Precautions . . . , . . . . , . . . . . . . , . . . . . 2·8
Diskette Storage . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . 2· 12
Short Term (Available for Immediate Use) . . . . . . . . . , . . . . . . . . , .
2~t2
Shipping Diskettes . . . . . . . . . . . , . . . . . . . . . , . . . . . . . . . , . , . 2·12 iii
C
CHAPTER 4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
CHAPTER 3
3.1
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.2.4
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.4
3.4.1
3.4.2
3.4.3
3.5
3.6
CONTENTS (Cont)
Page
RXll INTERFACE PROGRAMMING INFORMATION
REGISTER AND VECTOR ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RXCS - Command and Status (177170) . . . . . . . . . . . . . . . . . . . . . . . 3-2
RXDB - Data Buffer Register (177172) . . . . . . . . . . . . . . . . . . . . . . . . 3-3
RXT A - RX Track Address . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
RXSA - RX Sector Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
RXDB - RX Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
RXES - RX Error and Status . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
FUNCTION CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Fill Buffer (000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Empty Buffer (001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Write Sector (010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Read Sector (all) . . . . . . . . . . . . . . . . . . . . . . . . . . ,. . . . . . . . . 3-6
Read Status (101) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Write Sector with Deleted Data (110) . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Read Error Register Function (111) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Power Fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
PROGRAMMING EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Read Data/Write Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Empty Buffer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Fill Buffer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
RESTRICTIONS AND PROGRAMMING PITFALLS . . . . . . . . . . . . . . . . . . . . 3-11
ERROR RECOVERY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
RX8E INTERFACE PROGRAMMING INFORMATION
DEVICE CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Load Command (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Transfer Data Register (XDR) , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
STR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3·
SER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
SDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
4-3
INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REGISTER DESCRIPTION . . . . . . . . . . . . . .
4-3
. . . . . . . . . . . . . . . . 4-3
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Error Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
RXT A - RX Track Address . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . 4-5
RXSA - RX Sector Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
RXDB - RX Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
RX Error and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
FUNCTION CODE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Fill Buffer (000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Empty Buffer (001) . . . . . . . . .
Write Sector (010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Sector (0 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Status (101) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8
4-9
4-9
(
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(
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CONTENTS (Cont)
4.4.6
4.4.7
4.4.8
4.5
4.5.1
4.5.2
4.5.3
4.6
4.7
CHAPtERS
5.2.2.5
5.2.2.6
5.2.3
5.2.3.1
5.2.3.2
5.2.3.3
5.2.3.4
5.2.3.5
5.2.3.6
5.2.3.7
5.2.3.8
5.2.3.9
5.2.3.10
5.2.3.11
5.2.3.12
5.2.4
5.2.4.1
5.2.4.2
5.2.4.3
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.1.3
5.2.1.4
5.2.1.5
5.2.2
5.2.2.1
5.2.2.2
5.2.2.3
5.2.2.4
Write Deleted Data Sector (110) . .
Read Error Register Function (111)
Power Fail . . . . . . . . . . . . .
PROGRAMMING EXAMPLES . . . . .
Write/Write Deleted Data/Read Functions
Empty Buffer Function . . . . . . . . . .
Fill Buffer Function . . . . . . . . . .
RESTRICTIONS AND PROGRAMMING PITFALLS
ERROR RECOVERY . . . . . . . . . . . . .
THEORY OF OPERATION
OVERALL SYSTEM BLOCK DIAGRAM
Omnibus to RX8E Interface Signals
Unibus to RXII Interface Signals
Interface to pCPU Controller Signals pCPU Controller to Read/Write Electronics Signals
Read/Write Electronics to Drive Signals . . . . .
DETAILED BLOCK DIAGRAM AND LOGIC DISCUSSION
RX8E Interface
Device Select and lOT Decoder
Interrupt Control and Skip Logic
C Line Select Logic . . . . . .
Interface Register . . . . . . .
Sequence and Function Control Logic
RX11 Interface
Address Decoder
Data Path Selection
Interface Register
Sequence and Function Control Logic
Interrupt Control Logic . . . . . . .
Vector Address Generator . . . . . .
Microprogrammed Controller (PCPU) Hardware
Control ROM and Memory Buffer . .
Program Counter and Field Counter
Instruction Decode Logic . . . . . .
Do Pulse Generator . . . . . . . . .
Branch Condition Selector and Control
Scratch Pad Address Register and Scratch Pad
Counter Input Selector, Counter, and Shift Register pCPU Timing Generator . . . . .
Sector Buffer and Address Register
CRC Generator and Checker . .
Data Synchronizer and Separator
Output Circuit . . . . . . . .
Microprogram Instruction Repertoire
DO Instruction . .
Conditional Branch
Wait Branch v
Page
4-9
4-9
4-9
· 4-10
· 4-10
· 4-10
· 4-10
· 4-15
· 4-16
· 5-17
· 5-17
· 5-17
· 5-17
· 5-18
· 5-18
· 5-18
· 5-19
· 5-20
· 5-21
· 5-21
· 5-22
· 5-22
· 5-10
· 5-11
· 5-11
· 5-13
· 5-13
· 5-13
· 5-14
· 5-14
· 5-14
· 5-14
· 5-16
· 5.;16
5-1
5-2
5-3
54
5-6
5-7
5-8
5-8
5-8
5-8
5-8
· 5-10
FigUre No.
1.1
1-2
1·3
1·4
1-S
1·6
1·7
1·8
1·9
1·10
1·11
2·1
2·2
2-3
2-4
2·5
2·6
5.2.4.4
5;2.4.5
5.2.5
5.2.6
5.2.6.1
5.2.6.2
5.2.6.3
5.2.6.4
5.2.7
S.2.7.1
5.2.7.2
5.2.7.3
5.2.7.4
CHAPTER 6
6.1
6.2
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.1.1
6.4.1.2
6.4.2
CONTENTS (Cont)
Page
Open Scratch Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.22
Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.23
Microprogram Flowchart Description . . . . . . . . . . . . . . . . . . . . . . . . . 5.23
Read/Write Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.36
Diskette Position . . . . .'. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.36
Head Read/Write Circuitry . . • . . . : . . . . . . . . . . . . . . . . . . . . . 5.36
Head Load Control and Solenoid Drivers . . . . . . . . . . . . . . . . . . . . 5.36
Stepper Motor Control and Motor Drivers . . . . . . . . . . . . • . . . . . . . 5.36
Mechanical Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . 5.38
Drive Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.39
Spindle Mechanism . . . . . . . . . . . . . .. . . . . . . . . . .. . . .. . . 5.39
POsitioning Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.39
Head Load Mechal1ism . . . ; . . . . . . . . . . . . . . . • . . . . . . . . . . 541
MAINtENANCE .
RECOMMENDED TOOLS AND TEST EQUIPMENT . . . . . . . . . . . . . . . . . . . . 6.1
CUSTOMER CARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1
REMOVAL AND REPLACEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2
Module Replacement . . . . . . . . . . . . : . . . . . . . " . . . . . . . . . . . . .
Drive Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6·2
64
CORRECTIVE MAINTENANCE • . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialize Errors
10 • •
~
• • • • • • • • • • • • II • • • • • • II • • • • • • • • • • • •
6-4
Interface Diagnostic in Memory . . . . . . . . . . . . . . . . . . . . • . . . .
6·4
64
Diagnostics Not in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . .
6·9
KM11 Usage . . . . . . . . . ' . . . . . . . . . . . . . . . . . . . . . . . . . ; .. .
6·9
ILLUSTRA nONS
Title Page
Floppy Disk System Configuration . . . . . . . . . . . . . . . . • . . . . . . . . . . . . 1.2
Front View of the Floppy Disk System . . . . . . . . . . . . . . .
M83S7 Module (RX8E Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
M7846 Module (RXll Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5
Top View of the RXOI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. 1.6
Underside View of Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7
Top View of Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Diskette Media . . . . . . . . . . . '. . . . '. . . . . . . . . . . . . . • . . . . . . . . .. 1.9
Flux Reversal Patterns . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . 1.10
Track Format (Each Track) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10
Sector Format (Each Sector) . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . 1.11
RXOI • • . . . . . . . . . . . . . . . • . . . • . . . . . . . . . . . . . . . . . . . . . . 2.2
Cabinet Layout Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3
RXOl Shipping Restraints . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . 2.5
RXOI Cabinet Mounting Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Cable Routing, BC05L·15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9
(
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(
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{.
Figure No.
5·1
5·2
5·3
54
5·5
5·6
5·7
5-8
5·9
5·10
5·11
5·12
5·13
5·14
5·15
5·16
5.17
5·18
5·19
5·20
5·21
5·22
5·23
5·24
5·25
5·26
6·1
6-2
6·3
3·5
3·6
.3·7
3·8
4·1
4·2
4·3
4-4
4-5
4-6
2·7
3·1
3·2
3·3
34
4·7
4-8
4·9
4·10
ILLUS'tRA nONS (Cont) .
Title
. PlJge
Flexible Diskette Insertion . . . . . . . . . . . . . . .
RXCS Fonnat (RXll) . . . . . . . . . . . . . . . . .
RXTA Format (RX1l) . . . . . . . . . . . .
. . . . . . . . . . .
. . . ~ • • . . • . • . • .
. . . . . . . .
• . 2·11
3·2
. . . . . 3.3
RXSA Format (RXll) . . . . . . . . . . . . . . . . , . . . . . • . • . . 3·3
RXDB Fonnat (RXU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . •. 34·
RXES Fonnat (RXl1) . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . "/ • . . . 34
RXl 1 Write/Write Deleted Data/Read Example . . . . . . . . . • • . . . .• . . 3·9
RXII Empty Buffer Example . . . . . . . . . . . • . . . . . . . . . . . . . . • • ; . • . 3~1O
RXII Fill Buffer Example . . . . . . . . . . . . . . . . . . . . . . . . . . . •
i'. ; • • '.
3-13
LCD Word Fonnat (RX8E) . . . . . . . . . . . . . . . . . . . . . . • . . . • • . . . . • 4·2
Command Register Fonnat (RX8E) . , . . . . , . . . . . . . . . . . . . . . . . . . . . . . 4·3
Error Code Register Fonnat . . . . . . . . . • . . . . . . . • . . . ~ . . . . . . . . • 44
RXTA Format (RX8E) . . . . . . . . . . . " . . • . . , . . . . • • . . . •. • . . . .4·5
RXSA Format (RX8E) . . . . , . . . . . . . . . . . . . . • . . . . . . • . • .4·5
RXDB Fonnat (RX8E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4·6'
RXES Fonnat (RX8E) . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . • . . . , 4-6
RX8E Write/Write Deleted Data/Read Example . . . . . . . . . . . . . • . • • . • . . . . 4·11 .
RX8E Empty Buffer Example . . . . . . . . . . . . . . . . • . . . • . . . . . . . . , . . 4.13
Fill Buffer Example . . . . . . . . . . . . . . . . . . • . . . . . . . . , . . . . . . . . . • 4·14
Bus Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 5·1
Omnibus to RX8E Interface Signals . . . . . . . . . . . . . . • . . . • . . . . . . . . . . 5·2
Unibus to RXll Interface Signals . . . . . . • . . . . . • . • . . . • . . . . . 5·3
Interface to J.lCPU Controller Signals . . . . . . . . . . . . . , . . . • . . . . . • , . . , . 5 4
J.lCPU Controller to Read/Write Electronics Signals . . . . . . . . . . . . . , . . . , . . . S-6
Read/Write Electronics to Drive Signals . . . . . • . . • . . . , . • . . • . . . • . • . . . 5·7
RX8E Interface Block Diagram
RXl1 Interface Block Diagram
. . . . . . . . . . • . . . • . . . . . . • • . . . •. 5·9'
J.lCPU Controller Block Diagram . . . . . . . . . , . . . . . . . . . . . . . . , . . . 5·15
Data and Clock Separation . . . . . . . . . . . . . . . . . . • . . • . . . . . • . . . • . . 5·19
ID Address Mark Data Separation . . . . . . . • . . . . . . . . • . . . • . . . . . . . .
Initialize and Function Decode Flowchart . . . . . . . . • . . , . . . . . . . • . . . . . . 5·24
Empty and Fill Buffer Functions Flowchart . . . . . . . . . . . • • . . . . . . . . . . . • 5.25
Read Sector and Read Status Functions Flowchart . . • • . . • . . • . . • 5·26
Write Sector Function Flowchart . . . . . . . . . . . . . . . . . . . . , . . . . . , . . . 5·28
FINDTR Subroutine Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . 5·29
FINDHD and GETDAM Subroutines Flowchart . . . . . . . . . . . . . . . . . . . . . . . 5·30
HDRCOM, BDSRT, BADHDRRoutines Flowchart . . . • • . . , . • . . . • ' . , . . . . 5.32
DELAY, FINDSE, WRTOS, GETWRD Subroutines Flowchart . . . , . . . . . . . . . . . 5~33
STEPHD. W AITRN, MAGCOM Subroutines Flowchart . . . . . . . . . . . • . . • • • . . 5·34
DIFand CHKRDY Subroutine Flowchart . . . . . . . . . . . . • . . . . . . • , . . 5·35
Read/Write Electronics Block Diagram . . . . . . . . . . • . . . . . , . . • . . . . . . . . 5·37
Disk Drive Mechanical System . . . . . . . . . . . . . . . . . • . . . . . • . . . ; . . . . 5·38
Drive Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . $-39
Centering Cone and Drive Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . 5-40
PositiOning Mechanism . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . 540
RXOI. Rear View . . . . . . . . . . . . . . • . . . . . . . . . . . . • . , . . . . . . . . . . . 6·2
Troubleshooting Flow . . . . . . . . . . . . . . . . . . . . . . ; . . . . • . . 6-5
BC05L-15 Cable . . . . • . . . . . . . . . . . . . . . . . . . . . . • . . . • . . . ~ . •. 6·7
Figure No.
:
..
,
6,.4
6-5
6-6
6-7
ILLl~STRATIONS (Coot)
Title
RX8 Status Routine
RXll Status Routine
, KM 11 Maintenance Module Inserted ..
KMll Light and Switch Definitions for RXOI
Table No.
TABLES
Title
Interface Code/Jumper Configuration .
Device Code Switch Selection . . . . .
C Line Transfer Control Signals
Recommended Tools and Test Equipment
M7727 Connectors . . . . . . . . . . . . .
• .,.a . . . . .
(
Page
· 6-10
· 6-10
· 6-11
. . . . . . . . 6-12
Page
. 2-10
.. 4-1
. 5-10
6-1
. . . . . 6-3
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CHAPTER 1
GENERAL INFORMATION
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This manual presents information on the installation, operation, programming,· theory of operation, and maintenance of the RX8 or RX11 Floppy Disk System. Chapter 2 (Installation and Operation) should be consulted for unpacking and installation information. Chapter 2 also provides information on the proper care ofthe media and should be read carefully. .
1.1 INTRODUCTION
The RX8 and RXll Floppy Disk Systems consist of an RX01 subsystem and either an RX8E interface for a PDP-8 system or an RX11 interface for a PDP-II system.
The RX01 is a low cost, random access, mass memory device that stores data in ftxedlength blocks on a preformatted, IBM-compatible, flexible diskette. Each drive can store and retrieve up to 256K 8-bit bytes of data
(pDP-ll or PDP-8) or 128K 12-bit words (PDP-8). The RX01 consists of one or two flexible disk drives, a single read/write electronics module, a microprogrammed controller module, and a power supply, enclosed in a rack-mountable, 10-1/2 inch, self-cooled chassis. A cable is included for connection to either a PDP-8 interface module for use. on the PDP-8 Omnibus or a PDP-II interface for use on the PDP-II Unibus.
The RX01 performs implied seeks. Given an absolute sector address, the RX01 locates the desired sector and performs the indicated function, including automatic head position veriftcation and hardware calculation and veriftcation of the Cyclic Redundancy Check (CRC) character. The CRC character that is read and generated is compatible with IBM 3740 equipment.
The RXOI connects to the M8357 Omnibus interface module, which converts the RX01 I/O bus to aPDP-8 family omnibus structure. It controls interrupts to the CPU initiated by the RXOl, controls data interchange between the
RXOland the host CPU, and handles I/O transfers used to test status conditions.
The RXOl connects to the M7846 Unibus interface module, which converts the RX01 I/O bus to aPDP-ll Unibus structure. It controls interrupts to the CPU initiated by the RX01, decodes Unibus addresses for register selection, and handles data interchange between the RXOI and the host CPU.
The interface modules are dc powered by their host processor.
1.2 PHYSICAL DESCRIPTION
Acomplete system consists of the follOwing components:
M7726 controller module
M7727 read/write dectronics module
H771A or B power supply
RXOl-CA floppy disk drive (60 Hz, max of 2)
RXOl-CC floppy disk drive (50 Hz, max of 2)
M8357 (RX8E) or M7846 (RX11) interfaces
1-1·
(
All components except the interface are housed in a 10-1/2 in. rack-mountable box. The power supply, M7726 module, and M7727 module are "mounted above the drives. Interconnection from the RXOI to the interface is with a
40-conductor BC05L-15 cable of standard length (15 ft). Figure 1-1 is a configuration drawing of the system, and
Figure 1-2 is a front view of a dual drive system.
DRIVE#O o
DISKETTE
DRIVE
ELECTRONICS
M7727
,.CPU
CONTROLLER
M7726
MB357
OMNIBUS
INTERFACE
M7846
UNIBUS
INTERFACE
U.
N
I
B
U
S o
M
N
I
B
U
S.
DRIVE #1
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CP-1505
Figure 1·1 Floppy Disk System Configuration
1.2.1 RX8E/RXll Interfaces
Interface modules M8357 (RX8E) and M7846(RXll) are both quad modules. The M8357 plugs into an Omnibus slot and allows the RXOl to be" used on the PDP-8 processors. The M7846 plugs into an· SPC (small peripheral controller) slot with any PDP-II processor. Figure 1-3· shows the M8357 module and its major sections. Figure 14 shows the M7846 module and its major sections.
1.2.2 Micl"oprogrammed Controller
.
.
The M7726 microprogrammed controller module is located in the RXOI cabinet as shown in Figure 1-5. The M7726 is hinged on the left side and lifts up for access to the M7727 read/write electronics module.
1.2.3 Read/Write Electronics
The M7727 read/write electronics module is located in the RX01 cabinet as shown in Figure 1-5.
1.2.4 Electro,Mechanical Drive
A maximum of two drives can be attached to the read/write electronics. The electro-mechanical drives are mounted side by side under the read/write electronics board (M7727). Figure 1-6, which is an underside view of the drive, shows the drive motor connected to the spindle by a belt. (This belt and the small pulley are different on the 50 Hz and 60 Hz units; see Paragraph 2.2.3.2 for complete input power modification requirements.) Figure 1-7 is the top
. view showing the electro-mechanical components of the drive.
1-2
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7408-1
Figure 1-2 Front View of the Floppy Disk System
1.2.5 Power Supply
The H771 power supply is mounted at the rear of the RX01 cabinet as shown in Figure 1-5. The H771A is rated at
60 Hz ± 1/2 Hz over a voltage range of 90-132 Vac. The H771C and D are rated at 50 Hz ± 1/2 Hz over four voltage ranges:
90-120 Vac }
100-132 Vac 3.5 A circuit breaker; H771C
180-240 Vac }
200-264 Vac 1.75 A circuit breaker; H77lD
Two power harnesses are provided to adapt the H771C or D to each voltage range. This is not applicable to the
H771A. See Paragraph 2.2.3.2 for complete input power modification requirements.
1.3 SYSTEMS COMPATIBILITY
This section describes the physical, electrical, and logical aspects of IBM compatibility as defmed for data interchange with IBM system 3740 devices.
1.3.1 Media
The media used on the RX8 or RX11 Floppy Disk System is compatible with the IBM 3740 family of equipment and is shown in Figure 1-8.
The "diskette" media was designed by applying tape technology to disk architecture. This resulted in a flexible oxide-on-mylar surface encased in a plastic envelope with a hole for the read/write head, a hole for the drive spindle hub, and a hole for the hard index mark. The envelope is lined with a fiber material that cleans the diskette surface.
The media is supplied to the customer preformatted and pretested.
1-3
(
BC05L-15
INTERFACE
CABLE
CONNECTOR
DEVICE
CODE
SWITCHES
Figure 1-3 M8357 Module (RX8E Interface)
1-4
(
7408-3 c
(
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(
CONNECTOR
FOR THE
BC05L·15
INTERFACE
CABLE
(
PRIORITY
PLUG
RX11
INTERFACE
REGISTER
Figure 14 M7846 Module (RX11 Interface)
7408·4
1·5
M7727
READIWRITE
ELECTRONICS
MODULE
Figure 1-5 Top View of the RXOl
1-6
M7726~CPU
CONTROLLER
MODULE
BC05L-15
INTERFACE
CABLE H771
POWER
SUPPLY
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7408-8
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AC
POWER
CONNECTOR
DC
STEPPER
MOTOR
(
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DRIVE MOTOR DRIVE SPI NDLE
PULLEY
Figure 1-6 Underside View of Drive
7408-5
1·7
READ/WRITE
HEAD
HEAD LOAD
ARM
HELIX
DRIVE
Figure 1-7 Top View of Drive
1-8
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INDEX HOLE
REGISTRATION
HOLE
READ/WRITE
HEAD
APERTURE
Figure 1-8 Diskette Media
7408-2
1·9
1.3.2 Recording Scheme
The recording scheme used is "double frequency." In this method, data is recorded between bits of a constant clock stream. The clock stream consists of a continuous pattern of 1 flux reversal every 4ps (Figure 1-9). A data "one" is indicated by an additional reversal between clocks (i.e., doubling the bit stream frequency; hence the name). A data
''zero'' is indicated by no flux reversal between clocks.
A continuous stream of ones, shown in the bottom waveform in Figure 1-9, would appear as a "2F" bit stream, and a continuous stream of zeros,.shown in the top waveform in Figure 1-9, would appear as a "IF" or fundamental frequency bit stream. c
0 0
0 0
I I
I
I
""4
4~.e<
I
I
I
...
0 0
0
0 0
0
0 0
0
0
0
ALL ZEROS
PATTERN
0
CHANGING
PATTERN
ALL ONES
PATTERN
CP-1506
Figure 1-9 Flux Reversal Patterns
1.3.3 Logical Foimat
The logical format of the RX8 and RX11 Floppy Disk Systems is the same as that used in the IBM 3740.
Data is recordt;:d on only one side of the diskette. This surface is divided into 77 concentric circles or "tracks" numbered 0-76. Each track is divided into 26 sectors numbered 1-26 (Figure 1-10). Each sector contains two major fields: the header field and the data field (Figure 1-11).
LL.E.D. TRANSDUCER OUTPUT
'---H~A~R
0:1-"1
{',..., .--_-' I~X~~
L - - - - - - - - - - - - . . . - - ' - - - - 1 1 1
SECTOR
#26
PRE-INDEX
GAP
01320 BYT ES
SECTOR
#1
SECTOR
#2
SECTOR
#3
T
SOFT INDEX MARK
1 BYTE
. - - - ROTATION
Figure l-lD Track Format (Each Track)
SECTOR
#4 t
CP-1507
1.3.3.1 Header Description - The header field is broken into seven bytes (eight bits/byte) of information and is preceded by a field of zeros for synchronization.
1. Byte No'. 1: ID Address Mark - This is a unique strellill of flux reversals (not a string of data bits) that is decoded by the controller to identify the beginning of the header field.
2. Byte No.2: Track Address - This is the absolute (0-1148) binary track address. Each sector contains track address information to identify its location on 1 of the 77 tracks.
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ADDRESS
MARK
SYNC
FI ELD
ALL "0'5"
33 BYTES
- H lDo
-il>
;: l>
- - i
ID'"
-<l>
- i n
"'" l> o o
-I J.-,
BYTE l
WRITE GATE TURN OFF
FOR WRITE OF PRECEEDING
DATA FIELD
HEADER FIELD DATA FIELD
-
ID •
-<0
-<en"
'"
.
; : 0 l>l>
" , - i
" l >
- 0
HEADER
CRC
2 BYTES
DATA MARK
SYNC FIELD
ALL "0'5"
17 BYTES
",,,, r
'"
'" o l>
~
128,0 BYTES
OF DATA
"BYTES---+I·~-~~I
~
1--6 BYTES
WR ITE GATE TURN ON lFORWRITE OF NEXT
DATA FIELD
ROTATION
Figure 1·11 Sector Format (Each Sector)
DATA eRC
2 BYTES
CP-UOB
3. Byte No.3 - Zeros (one byte)
4. Byte No.4: Sector Address - This is the absolute binary sector address (1-328)' Each sector contains sector address information to identify its circumferential position on a track.
5. Byte No.5 - Zeros (one byte)
6. Bytes No.6 and 7: CRC - This is the Cyclic Redundancy Check character that is calculated for each sector from the first five header bytes using a polynomial division algorithm designed to detect the types of failures most likely to occur with "double frequency" recorded data and the floppy media. The CRC is compatible with IBM 3740 series equipment.
1.3.3.2 Data Field Description - The data field is broken into 131 bytes of information and is preceded by a field of zeros for synchronization and the header field (Figure 1·11).
1. Byte No.1: Data or Deleted Data Address Mark - This is a unique string of flux reversals (not a string of data bits) that is decoded by the controller to identify the beginning of the data field. The deleted data mark is not used during normal operation but the RXOI can identify and write deleted data marks under program control, as required. The deleted data mark is only included in the RX8/RXII system to be IBM compatible. One or the other data address marks precedes each data field.
2. Bytes No. 2-129 - These bytes comprise the data field used to store 128 8·bit bytes of information.
NOTE
Partial data fields are not recorded.
3. Bytes No. 130 and 131 - These bytes comprise the CRC character that is calculated for each sector from the first 129 data field bytes using the industry standard polynomial division algorithm designed to detect the types of failures most likely to occur in double frequency recording on the floppy media.
1.3.3.3 Track Usage In the IBM 3740 system, some tracks are commonly designated for special purposes such as error information, directories, spares, or unused tracks. The RX01 is capable of recreating any system structure through the use of special systems programs, but normal operation will make use of all the available tracks as data tracks. Any special file structures must be accomplished through user software.
1·11
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1.3.3.4 CRC Capability - Each sector has a two·byte header CRC character and a two·byte data CRC character to ensure data integrity. The CRC characters are generated by the hardware during a write operation and checked to ensure all bits were read correctly during a read operation. The CRC character is the same as that used in the IBM
3740 series of equipment. A complete description of CRC generation and checking is presented in Paragraph 5.2.3.
1.4 APPLICABLE INSTRUCTION MANUALS
This manual is designed to be used in conjunction with the RX8/RXll Engineering Drawings. Other documents useful in operating and understanding the RX8/RXll system are:
PDp·ll* Processor Handbook
PDP-ll Peripherals and Interfacing Handbook
PDP-8 Small Computer Handbook
PDP-8A User Manual
1.5 CONFIGURATION
Option number designations are as follows:
PDP-8 Systems
RX8-AA
RX8-AD
RX8-BA
RX8-BD
Single drive system, liS V, 60 Hz
Single drive system, 50 Hz
Dual drive system, 115 V /60 Hz
Dual drive system, 50 Hz
PDP-ll Systems
RXll-AA
RXll-AC
RXll-BA
RXll-BD
Single drive system, 115 V/60 Hz
Single drive system, 50 Hz
Dual drive system, 115 V /60 Hz
Dual drive system, 50 Hz
NOTE
50 Hz versions are available in voltages of 105,115,220,240
Vac by field pluggable conversion. See Paragraph 2.2.3.2 for complete input power modification requirements.
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Appropriate handbook for the particular processor used with the system.
1-12
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1.6 SPECIFICATIONS
S}rstem Reliability
Minimum number of revolutions per track
Seek error rate
Soft read error rate
Hard read error rate
1 million/media (head loaded)
1 in 10 6 seeks
1 in 10 9 bits read
1 in 10 12 bits read
NOTE
The above error rates only apply to media that is properly cared Jor. Seek error and soft read errors are usually attributable to random effects in the head/media interface, such as electrical noise, dirt, or dust. Both are called "soft" errors if the error is recoverable in ten additional tries or less.
"Hard" errors cannot be recovered. Seek error retries should be preceded by an Initialize.
Drive Performance
Capacity
Per diskette
Per track
Per sector
8-bit bytes
256,256 bytes
3,328 bytes
128 bytes
128,128 words
1,664 words
64 words
Data transfer rate
Diskette to controller buffer
Buffer to CPU interface
CPU interface to I/O bus
4 ,us/data bit (250K bps)
2,us/bit (500K bps)
18 ,us/8-bit byte (>50K bytes/sec)
NOTE
PDP-8 interface can operate in 8- or 12-bit modes under software control. The transfer rate is ·23 ,us per 12-bit word
(>40K bytes/sec).
Track-to-track move
Head settle time
Rotational speed
Recording surfaces per disk
Tracks per disk
Sectors per track
Recording technique
Bit density
Track density
Average access
10 ms/track maximum
25 ms maximum
360 rpm ± 2.5%; 166 ms/rev nominal
1
77 (0-76) or (0-1148)
26 (1-26) or (1-328)
Double frequency
3200 bpi at inner track
48 tracks/in.
488 ms, computed as follows:
Seek
(77 tks/2) X 10 ms
Settle Rotate
+ 25 ms + (166 ms/2) = 493 ms
Environmental Characteristics
Temperature
RX01, operating
RXOl, nonoperating
Media, operating
Media, nonoperating
150 to 320 C (590 to 900 F) ambient; maximum temperature gradient = 200 F/hr(ll.1° C/hr)
_350 to +600 C (_300 to +1400 F)
Media temperature. must range before use.
NOTE be within operating temperature
Relative humidity
RXOl, operating 250 C (770 F) maximum wet bulb
20 C (360 F) minimum dew point
20% to 80% relative humidity
RXOI, nonoperating
Media, nonoperating
5% to 98% relative humidity (no condensation)
10% to 80% relative humidity
Magnetic field Media exposed to a magnetic field strength of 50 oersteds or greater may lose data.
Interface modules
Operating temperature
Relative humidity
Maximum wet bulb
Minimum dew point
Electrical
Power consumption
RXOI
. PDP-II interface (M7846}
PDP-8 interface (M8357)
AC power input
50 to 500 C (41 0 to 122°F)
10% to 90%
32 0 C (90 0 F)
2
0
C (36
0 p)
3 A at 24 V (dual), 75W; 5 A at 5 V, 25 W
. Not more than 1.5 A at 5 Vdc
Not mOore than 1.5 A at 5
V
dc
4 Aat 115 Vac
2 Aat 230 Vac
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CHAPTER 2
INSTALLATION AND OPERATION
2.1 PURPOSE AND ORGANIZATION
This chapter provides information on installing and operating the RX8/RX11 Floppy Disk System. This information is organized into four sections as outlined below.
1. Site Preparation - The planning required to make the installation site suitable for operation of the floppy disk system, including space, cabling, and power requirements, and fire and safety precautions.
2. Environmental Considerations - The specific environmental characteristics of the floppy disk systems, i.e., temperature, relative humidity, air conditioning and/or heat dissipation, and cleanliness.
3. Installation - The actual step-by-step process of installing the floppy disk system from unpacking through the preliminary installation checks, power conversion techniques, and acceptance testing.
4. Operation Practices - The recommended practices for using the floppy disk system, handling the media, and shipping and storing the diskettes.
2.2 SITE PREPARATION
2.2.1 Space
The RX01 is a cabinet-mountable unit that may be installed in a standard Digital Equipment Corporation cabinet.
This rack-mountable version is approximately 10-1/2 in. (28 cm) high, 19 in. (48 cm) wide, and 16-1/2 in. (42 cm) deep (Figure 2-1).
Provision should be made for service clearances of apprOximately 22 in. (S6 cm) at the front and rear of the cabinet
(Figure 2-2).
2.2.2 Cabling
The standard interface cable proVided with an RX8/RX11 (BCOSL-1S) is IS ft (4.6 m) in length, and the positioning of the RX01 in relation to the central processor should be planned to take this into consideration. The RX01 should be placed near the control console or keyboard so that the operator will have easy access to load Or unload disks.
The position immediately above the CPU is preferred. The ac power cord will be about 9 ft (2.7 m) long.
2.2.3 AC Power
2.2.3.1 Power Requirements - The RX01 is designed to use either a 60 Hz or a SO Hz power source. The 60 Hz version (RXOI-A) will operate from 90 to 132 Vac, without modifications, and will use less than 4 A operating. The
SO Hz version (RXOI-D) will operate within four voltage ratings and will require field verification/modification to ensure that the correct voltage option is selected. The voltage ranges of90 to 120 Vac and 180 to 240 Vac will use less than 4 A operating. The voltage ranges of 100-132 Vac and 200-264 Vac willuse less than 2 A. Both versions of the RXOI will be required to receive the input power from an ac source (e.g., 861 power control) that is controlled by the system's power switch.
2-1
(FRONT)
I· r ra
Ilumm~lIIlllllllllllllill~IIWI~~lllllllill
l
10.5" ],m)
19"
(48.3 em)
(FRONT VIEW)
17.0"
(43.2 em)
(2)
·1
s
-
-
-
~ -
-
~
-
~
/INSIDE TRACK
IS)
=
"--
•
26.5"
(66.3 em)
SIDE VIEW)
NOTE
Dusl cover attached to cabinet not RXOI.
Figure 2-1 RXO 1
-
CP-1Sl1
2.2.3.2 Input Power Modification Requirements - The 60 Hz version of the RXOI uses the H771A power supply and will operate on 90 to 132 Vac, without modification. To convert to operate on a 50 Hz power source in the field, the H771A supply must be replaced with an H771C or D (Figure 1-5) and the drive motor belt and drive motor pilley must be replaced (Figure 1-6). The 50 Hz version of the RX01 uses either the H771C or D power supply. The H771C operates on a 90-120 Vac or 100-132 Vac power source. The H771D operates on a
180-240 Vac or 200-264 Vac power source. To convert the H771C to the higher voltage ranges or the H771D to the lower voltage ranges, the power harness and circuit breaker must be changed. See Figure 2-3 for appropriate power harness and circuit breaker.
2.2.4· Fire and Safety Precautions
The RX8/RXII Floppy Disk System presents no additional fire or safety hazards to an existing computer syste:qt.
Wiring should be carefully checked, however, to ensure that the capacity is adequate for the added load and for any contemplated expansion.
2.3 ENVIRONMENTAL CONSIDERATIONS
2.3.1 General
The RX8/RXll is capable of efficient operation in computer environments; however, the parameters of the operating environment must be determined by the most restrictive facets of the system, which in this case are the diskettes.
2-2
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J.
(
(
(
18
~3~
(46.35em)
(
(
(
(
~~~O~~~EL
-- ______________
~~!_
__
CABLE ACCESS
I
,-l--~
"
'-/
+
I rl
~
'\~
I
--
+
CASTER SWIVEL
RADIUS 2 13/32"
(6.12 em)
(4) CASTERS looil.I'-----211~16
I
(54.87 em)
-------';'-1.1
I
REMOVABLE
END PANEL
FAN
PORTS
LEVELER
4 PLACES
I I "
!
~~g~ E;:~I~~~D! . I.st om}
L J~
48 7/32"
(122.47em)
30"
(76.2em)
CABIN ET
717/1~
(182 .28em) high
(floor line to cabinet top) ~.CP-1612
Figure 2-2 Cabinet Layout Dimensions
2.3.2 Temperature, Relative Humidity
The operating ambient temperature range of the diskette is 59° to 90° F (15° to 32° C) with a maximum temperature gradient of 20° F/hr (-6.7° C/hr).
The media nonoperating temperature range (storage) is increased to -30° to 125° F (-34.4° to 51.6° C), but care must be taken to ensure that the media has stabilized within the operating temperature range before use. This range will ensure that the media will not be operated above its absolute temperature limit of 125° F.
2-3
(
Humidity control is important in any system because static electricity can cause errors in any CPU with memory.
The RXOI is designed to operate efficiently within a relative humidity range of 20 to 80 percent, with a maximum wet bulb temperature of 77° F (25° C) and a maximum dew point of 36° F (2° C).
2.3.3 Heat Dissipation
The heat dissipation factor for the RXOI Floppy Disk System is less than 225 Btu/hr. By adding this figure to the total heat dissipation for the other system components and then adjusting the result to compensate for such factors as the, number of personnel, the heat radiation from adjoining areas, and sun exposure through windows, the approximate cooling requirements for the system can be determined. It is advisable to allow a safety margin of at least 25 percent above the maximum estimated requirements.
2.3.4 Radiated Emissions
Sources of radiation, such as FM, vehicle ignitions, and radar transmitters located close to the computer' system, may affect the performance of the RX8/RXll Floppy Disk System because of the possible adverse effects magnetic fields can have on diskettes. A magnetic field with an intensity of 50 oersteds or greater might destroy all or some of the information recorded on the diskette.
2.3.5 Cleanliness
Although cleanliness is important in all facets of a computer system, it is particularly important in the case of moving magnetic media, such as the RXOi. Diskettes are not sealed units and are vulnerable to dirt. Such minute obstructions as dust specks or fmgerprint smudges may cause data errors. Therefore, the RXOI should not be subjected to unusually contaminated atmospheres, especially one with abrasive airborne' particles. (Refer to
Paragraph 2.5.2.)
NOTE
Removable media involve use, handling, and maintenance which are beyond DEC's direct control. DEC disclaims responsibility for performance of the equipment when operated with media not meeting DEC specifications or with media not maintained in accordance with procedures approved by
DEC. DEC shall not be liable for damages to the equipment or to media resulting from such operation.
2.4 INSTALLATION
2.4.1 General
The RX8/RXll Floppy Disk System can be shipped in a cabinet as an integral part of a system or in a separate container. If the RXOI is shipped in a cabinet, the cabinet should be positioned in the final installation location before proceeding with the installation.
2.4.2 Tools
Installation of an RX8/RXll Floppy Disk System requires no special tools or equipment. Normal hand tools are all that are necessary. However, a forklift truck or pallet handling equipment may be needed for receiving and installing a cabinet·mounted system.
2.4.3 Unpacking and Inspection
2.4.3.1 Cabinet-Mounted
1. Remove the protective covering over the cabinet.
2. Remove the restraint on the rear door latch and open the door.
2-4
C','
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'i.e)
co
3. ·Remove the two boIts on the cabinet's lower side rails that attach the cabinet to the pallet.
4.
Raise the four levelers at the corners of the cabinet,allowing the cabinet to roll on the casters ..
5.
Carefully roll the cabinet off the pallet; if a forklift is available, it should be used to lift and move the cabinet.
6.
Remove the shipping restraint from the RXOI and save it for possible reuse (Figure 2-3).
7. Slide the RXOI out on the chassis slides and visually inspect for any damage, loose screws, loose wiring, etc.
NOTE
If any shipping damage is found, the customer should be notified at this time so he can contact the carrier, and record the information on the acceptance form.
JUMPER P1 c
SHIPPING
RESTRAINT (RED)
FILTER
POWER PLUGS FILTER
VOLTAGE (Vac)
90-120
100-132
180-240
200-264
POWER HARNESS
70-10696-02
70-10696-01
70-10696-04
70-10696-03
CIRCUIT BREAKER
3.5 A, 12-12301-01
3.5 A, 12-12301-01
1.75 A, 12-12301-00
1.75 A, 12-12301-00
Figure 2-3 RXOl Shipping Restraints
2-5
7436-12
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2.4.3.2 Separate Container
1. Open the carton (Figure 2-4) and remove the corrugated packing pieces.
2. Lift the RX01 out of the carton and remove the plastic shipping bag.
3. Remove the shipping fixtures from both sides of the RX01 and inspect for shipping damage.
4. Attach the inside tracks of the chassis slides provided in the carton to the RX01 (Figure 2-1).
5. Locating the proper holes in the cabinet rails (Figure 2-5), attach the outside tracks to the cabinet.
6. Place the tracks attached to the RX01 inside the extended cabinet tracks and slide the unit in until the tracks lock in the extended position.
7. Locate the RX01 cover in the cabinet above the unit and secure it to the cabinet rails (Figure 2-3).
2.4.4 Installation
1. Loosen the screws securing the upper module (M7726) and swing it up on the hinge.
2. Inspect the wiring and connectors for proper routing and ensure that they are seated correctly.
3. This step is for 50 Hz versions only. Check the power configuration to ensure that the proper power harness and the correct circuit breaker are installed (Figure 2-3).
4. Connect the BC05L-15 cable to the M7726 module and route it through the back of the RXOI (Figure
2-6) to the CPU, then connect it to the interface module (RX8E, M8357; RX11, M7846).
5. Refer to Table 2-1 for correct device code or addressing jumpers.
6. Ensure that power for the system is off.
7. Insert the interface module into the Omnibus (RX8E) or available SPC slot (RXll). (Refer
toPDP-ll
Processor Handbook, Specifications, Chapter 9.)
8. Connect the RX01 ac power cord into a switched power source.
9. Turn the power on, watching for head movement on the drive(s) during the power up, initialize phase.
The head(s) should move ten tracks toward the center and back to track O.
10. Perform the diagnostic in the sequence listed below for the number of passes (time) indicated. If any· errors occur, refer to Chapter 6 for corrective action.
RX8 or RX11 Diagnostic - 2 passes
Data Reliability jExerciser - 3 passes
DECX-8 or DECX-ll 10 minutes
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2-6
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SLIDES
(
ONE PIECE
FOLDER
9905711
PLYWOOD HOLDING
FIXTURE RT. SI DE
9905712-01
DUST
COVER
(
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ONE PIECE
FOLDER
9905714
PLYWOOD HOLDING
FIXTURE LT. SIDE
9905712-00
FLAT WASHER (S)
(1:_.. LOCK WASHER (S)
~~
~SCREW(S)
90- 06076-01
SLOTTED
SHIPPING
CARTON
Figure 2-4 RX8/RXll Unpacking
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2-7
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COVER
SCREWS,
CHASSIS SLIDES
( o o
CP-1594
Figure 2-5 RXOI Cabinet Mounting Information
2.5 OPERATION
2.5.1 Operator Control
The simplicity of the RXOI precludes the necessity of operator controls and indicators. A convenient method of opening the unit for diskette insertion and removal is provided. On each drive is a simple pushbutton, which is compressed to allow the spring-loaded front cover to open. The diskette may be inserted or removed, as shown in
Figure 2-7, with the label up. The front cover will automatically lock when the bar is pushed down.
CAUTION
The drive(s) should not be opened while they are being accessed because data may be incorrectly recorded, resulting in a CRC error when the sector is read.
2.5.2 Diskette Handling Practices and Precautions
To prolong the diskette life and prevent errors when recording or reading, reasonable care should be taken when handling the media. The following handling recommendations should be followed. to prevent unnecessary loss of data or interruptions of system operation.
1. Do not write on the envelope containing the diskette. Write any information on a label prior to affIxing it to the diskette.
2. Paper clips should not be used on the diskette.
3. Do not use writing instruments that leave flakes, such as lead or grease pencils, on the jacket of the media.
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M7727
Figure 2-6 Cable Routing, BC05L-15
2-9
7436-18
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Table 2-1
Interface Code/Jumper Configuration
*670X
671X
672X
673X
674X
675X
676X
677X
RX8E (M83S7)
Device Codes
SWI SW2 SW3 SW4 SWS SW6
ON ON ON OFF OFF OFF
ON ON OFF OFF OFF ON
ON OFF ON OFF ON OFF
ON OFF OFF OFF ON ON
OFF ON ON ON OFF OFF
OFF ON OFF ON OFF ON
OFF OFF ON ON ON OFF
OFF OFF OFF ON ON ON
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RXll (M7846)
BR Priority
BR7 - 54-08782
BR6 - 54-08780
*BR5 - 54-08778
BR4 - 57-08776
*Unibus Address 17717X
A12/W18 - Removed
All/W17 - Removed
AlO/W16 - Removed
A9/W15 - Removed
A8/W14 - Installed
A 7/W13 - Installed
A6/W12 - Removed.
A5/Wll - Removed
A4/WIO - Removed
A3/W9 - Removed
*
Vector Address (264
8 )
V2/Wl - Installed
V3/W2 - Removed
V4/W3 - Installed
V5/W4 - Installed
V6/W5 - Removed
V7/W6 - Installed
V8/W7 - Removed
·Standard
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2-10
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7408-6
Figure 2-7 Flexible Diskette Insertion
4. Do not touch the disk surface exposed in the diskette slot or index hole.
5. Do not clean the disk in any manner.
6. Keep the diskette away from magnets or tools that may have become magnetized. Any disk exposed to a magnetic field may lose information.
7. Do not expose the diskette to a heat source or sunlight.
8. Always return the diskette to the envelope supplied with it to protect. the disk from dust and dirt.
Diskettes not being used should be stored in the file box if possible.
9. When the diskette is in use, protect the empty envelope from liquids, dust, and metallic materials.
10. Do not place heavy items on the diskette.
11. Do not store diskettes on top of computer cabinets or in places where dirt can be blown by fans into the diskette interior.
12. If a diskette has been exposed to temperatures outside of the operating range, allow 5 minutes for thermal stabilization before use. The diskette should be removed from its packaging during this time.
2-11
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2.5.3 Diskette Storage
2.5.3.1 Short Term (Available for Immediate Use)
1. Store diskettes in their envelopes.
2. Store horizontally, in piles of ten or less. If vertical storage is necessary, the diskettes should be supported so that they do not lean or sag, but should not be subjected to compressive forces. Permanent deformation may result from improper storage.
3. Store in an environment similar to that of the operating system; at a minimum, store within the operating environment range.
2.5.3.2 Long Term - When diskettes do not need to be available for immediate use, they should be stored in their original shipping containers within the nonoperating range of the media. '
2.5.4 Shipping Diskettes
Data recorded on disks may be degraded by exposure to any sort of small magnet brought into close contact with the disk surface. If diskettes are to be shipped in the cargo hold of an aircraft, take precautions against possible exposure to magnetic sources. Because physical separation from the magnetic source is the best protection against accidental erasure of a diskette, diskettes should be packed at least 3 in. within the outer box. This separation should be adequate to protect against any magnetic sources . likely to be encountered during transportation, making it generally unnecessary to ship diskettes in specially shielded boxes.
When shipping, be sure to label the package:
DO NOT EXPOSE TO PROLONGED HEAT OR SUNLIGHT.
When received, the carton should be examined for damage. Deformation of the carton should alert the receiver to possible damage of the diskette. The carton should be retained, if it is intact, for storage of the diskette or for future shipping.
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2-12
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CHAPTER
3
RXII INTERFACE
PROGRAMMING INFORMATION
This chapter describes device registers, register and vector address assignments, programming specifications, and programming examples for the RXII interface.
All software control of the RXII is performed by means of two device registers: the RXII Command and Status register (RXCS) and a multipurpose RXII Data Buffer register (RXDB). These registers have been assigned bus addresses and can be read or loaded, with certain exceptions, using any instruction referring to their addresses.
The RX01, which includes the mechanical drive(s), read/write electronics, and pCPU controller, contains all the control circuitry required for implied seeks, automatic head position verification, and calculation and verification of the CRC; it has a buffer large enough to hold one full sector of diskette data (128 8-bit bytes). Information is serially passed between the interface and the RX01.
A typical diskette write sequence, which is initiated by a user program, would occur in two steps:
1. Fill Buffer - A command to fill the buffer is moved into the RXCS. The Go bit (paragraph3.2.1) must be set. The program tests for Transfer Request (TR). When TR is detected, the program moves the first of 128 bytes of data to the RXDB. TR goes false while the byte is moved into the RXOI. The program retests TR and moves another byte of data when TR is true. When the RXOI sector buffer is full, the
Done bit will set, and an interrupt will occur if the program has enabled interrupts.
2.
Write Sector - A command to write the contents of the buffer onto the disk is issued to the RXCS.
Again the Go bit must be set. The program tests TR, and when TR is true, the program moves the desired sector address to the RXDB. TR goes false while the RXOI handles the sector address. The program again waits for TR and moves the desired track address to the RXDB, and again TR is negated.
The RXOI locates the desired track and sector, verifies its location, and writes the contents of the sector buffer onto the diskette. When this is done, an interrupt will occur if the program has enabled interrupts.
A typical diskette read occurs in just the reverse way: first locating and reading a sector into the buffer (Read
Sector) and then unloading the buffer into core (Empty Buffer). In either case, the content of the buffer is not valid if Power Fail or Initialize follows a Fill Buffer or Read Sector function.
3.1 REGISTER AND VECTOR ADDRESSES
The RXCS register is normally assigned Unibus address 177170, and the RXDB register is assigned Unibus address
177172. The normal BR priority level is 5, but it can be changed by insertion of a different priority plug located on the interface module. The vector address is 264.
(
3-1
4
5
6
3.2 REGISTER DESCRIPTION
3.2.1 RXCS - Command and Status (177170)
Loading this register while the RXOI is not busy and with bit 0
=
1 will initiate a function as described below and indicated in Figure 3-1. Bits 0-4 write-only bits.
"15 14
ERROR
I
RX
I
!
INIT
13 12 11
NOT USED
10 09 08 07 06 05 04 03 02 01
TR
I
DONE
\
I
FUNCTION
00
J
[
GO
I
INT
ENB
UNIT
SEL
CP-1509
Figure 3-1 RXCS Format (RXll)
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Bit No.
o
1-3
7
8-13
Description
Go - Initiates a command to RXOI. This is a write-only bit.
Function Select - These bits code one of the eight possible functions described in Paragraph
3.3 and listed below. These are write-only bits.
Code
000
001
010
011
100
101
110
111
Function
Fill Buffer
Empty Buffer
Write Sector
Read Sector
Not used
Read Status
Write Deleted Data Sector
Read Error Register
Unit select - This bit selects one of the two" possible disks for execution of the desired function. This is a write-only bit. Unit 0 is physically the left-hand unit in the rack.
Done - This bit indicates the completion of a function. Done will generate an interrupt when asserted iflnterrupt Enable (RXCS bit 6) is set. This is a read-only bit.
Interrupt Enable - This bit is set by the program to enable an interrupt when the RXOI has completed an operation (Done). The condition of this bit is normally determined at the time a function is initiated. This bit isc1eared by Initialize and is a read/write bit.
Transfer Request - This bit signifies that the RXll needs data or has data available. This is a read-only bit.
Unused
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3-2
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Bit No.
14
Description
RXII Initialize - This bit is set by the program to initialize the RXII without initializing all of the devices on the Unibus. This is a write-only bit.
CAUTION
Loading the lower byte of the RXCS will also load the upper byte of the RXCS.
Upon setting this bit in the RXCS, the RXll will negate Done and move the head position mechanism of drive 1 (if two are. available) to track O. Upon completion of a successful
Initialize, the RX01 will zero the Error and Status register, set Initialize Done, and set RXES _ bit 7 (DRV RDY) if unit 0 is ready. It will also ·read sector 1 of track 1 on drive O.
15 Error - This bit is set by the RXOI to indicate that an error has occurred during an attempt to execute a command. This read-only bit is cleared by the initiation of a new command or an Initialize (paragraph 3.6).
3.2.2 RXDB - Data Buffer Register (177172)
~
This register serves as a general purpose data· path between the RX01 and the interface. It may represent one of four
RX01 registers according to the protocol of the function in progress (paragraph 3.3).
This register is read/write if the RX01 is not fu the process of executing a command; that is, it may be manipulated without affecting the RX01 subsystem. If the RX01 is actively executing a command, this register will only accept data if RXCS bit 7 (TR) is set. In addition, valid data can only be read when TR is set.
CAUTION
Violation of protocol in manipulation of this register may cause permanent data loss.
3.2.2.1 RXTA - RX Track Address (Figure 3-2) This register is loaded to indicate on which of the 115
8 tracks a given function is to operate. It can be addressed only under the protocol of the function in progress (paragraph 3.3).
Bits 8 through 15 are unused and are ignored by the control.
04 03 02 01 00
CP-l~10
Figure 3-2 RXTA Format (RX11)
3.2.2.2 RXSA - RX Sector Address (Figure 3-3) - This register is loaded to indicate on which of the 328 sectors a given function is to operate. It can be addressed only under the protocol of the function in progress (paragraph 3.3).
Bits 8 through 15 are unused and are ignored by the control.
15 14 00 13 12 11
I
NOT USED
10 09 08 07 06 05 04
I
I 0 I 0 I 0 I
03 02 01
~
1-32 8
CP-l51l
Figure 3-3 RXSA Format (RXll)
3-3
(
3.2.2.3 RX:DB - RX Data Buffer (Figure 3-4) - All information transferred to and from the floppy media passes through this register and is addressable only under the protocol of the function in progress (paragraph 3.3).
,"
I
15 14 13 12 11
NOT USED
10 09 08 07 06 05 04 03
I
02 01 00
CP-1512
Figure 34 RXDB Format (RXll)
3.2.2.4 RXES - RX Error and Status (Figure 3-5) - This register contains the current error and status conditions of the drive selt';cted by bit 4 (Unit Select) of the RXCS. This read-only register can be addressed only under the protocol of the function in progress (paragraph 3.3). The RXES is located in the RXDB upon completion of a function.
15 14 13 12 11 10 00
I
CRC
I
NOT USED NOT USED
CP -1513
Figure 3-5 RXES Format (RXll)
RXES bit assignments are:
Bit No.
o
Description
CRC Error - A cyclic redundancy check error was detected as information was retrieved from a data field of the diskette. The RXES is moved to the RXD~, and Error and Done are asserted.
1
2
" Parity Error - A" parity error was detected on command or address information being transferred to the RXOI from the Unibus interface. A parity error indication means that there is a problem in the interface cable between the RXOl and the interface. Upon detection of a parity error, the current function is terminated; the RXES is moved to the
RXDB, and Error and Done are asserted.
Initialize Done - This bit is asserted i~ the RXES to indicate completion of the Initialize routine which can be caused by RXOl power failure, system power failure, or programmable or Unibus Initialize.
3-5
6
Unused
Deleted Data Detected -During data recovery, the identification mark preceding the data field was decoded as a deleted data mark (paragraph 1.3.3).
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34
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Bit No.
7
Description
Drive Ready - This bit is asserted if the unit currently selected exists, is properly supplied with power, has a diskette installed correctly, has its door closed, and has a diskette up to speed.
NOTE 1
The Drive Ready bit is only valid when retrieved via a Read
Status function or at completion of Initialize when it indicates status of drive O.
NOTE 2
If the Error bit was set in the RXCS but Error bits are not set in the RXES, then specific error conditions can be accessed via a Read Error Register function (Paragraph 3.3.7).
3.3 FUNCTION CODES
Following the strict protocol of the individual function, data storage and recovery on the RXll occur with careful manipulation of the RXCS and RXDB registers. The penalty for violation of protocol can be permanent data loss.
A summary of the function codes is presented below:
000
001
010
011
100
101
110
111
Fill Buffer
Empty Buffer
Write Sector
Read Sector
Not used
Read Status
Write Deleted Data Sector
Read Error Register
The following paragraphs describe in detail the programming protocol associated with each function encoded and written into RXCS bits 1-3 if Done is set.
3.3.1 Fill Buffer (000)
This function is used to fill the RXOlbuffer with 128 8-bit bytes of data from the host processor. Fill Buffer is a complete function in itself; the function ends when the buffer has been filled. The contents of the buffer can be written onto the diskette by means of a subsequent Write Sector function, or the contents can be returned to the host processor by an Empty Buffer function.
RXCS bit 4 (Unit Select) does not affect this function, since no diskette drive is involved. When the command has been loaded, RXCS bit 5 (Done) is negated. When the TR bit is asserted, the first. byte of the data may be loaded into the data buffer. The same TR cycle will occur as each byte of data is loaded. The RXOI counts the bytes transferred; it will not accept less than 128 bytes and will ignore those in excess. Any read of the RXDB during the cycle of 128 transfers is ignored by the RX11.
3.3.2 Empty Buffer (001)
This function is used to empty the internal buffer of the 128 data bytes loaded from a previous Read Sector or Fill
Buffer command. This function will ignore RXCSbit 4 (Unit Select) and negate Done.
(
3-5
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When TR sets, the program may unload the first of 128 data bytes from the RXDB. Then the RXll again negates
TR. When TR resets, the second byte of data may be unloaded from the RXDB, which again negates TR. Alternate checks on TR and data transfers from the. RXDB continue until 128 bytes of data have been moved from the RXDB.
Done sets, ending the operation and initiating an interrupt if RXCS bit 6 (Interrupt Enable) is set.
NOTE
The Empty Buffer function does
not
destroy the contents of the sector buffer.
3.3.3 Write Sector (010)
This function is used to locate a desired track and sector and write the sector with the contents of the internal sector buffer. The initiation of this function clears bits 0, 1, and 6 of RXES (CRC Error, Parity Error, and Deleted Data
Detected) and negates Done.
When TR is asserted, the program must move the desired sector address into the RXDB, which will negate TR. When
TR is again asserted, the program must load the desired track address into the RXDB, which will negate TR. If the desired track is not found, the RXll will abort the operation, move the contents of the RXES to the RXDB, set
RXCS bit 15 (Error), assert Done, and initiate an interrupt if RXCS bit 6 (Interrupt Enable) is set.
TR will remain negated while the RXOI attempts to locate the desired sector. If the RXOI is unable to locate the desired sector within two diskette revolutions, the RXll will abort the operation, move the contents of the RXES to the RXDB, set RXCS bit 15 (Error), assert Done, and initiate an interrupt if RXCS bit 6 (Interrupt Enable) is set.
If the desired sector is successfully located, the RXll will write the 128 bytes stored in the internal buffer followed by a 16-bit CRC character that is automatically calculated by the RX01. The RXll ends the function by asserting
Done and initiating an interrupt if RXCS bit 6 (Interrupt Enable) is set.
NOTE 1
The contents of the sector buffer are not valid data after a power loss has been detected by the RXOI. The Write Sector function, however, will be accepted as a valid function, and the random contents of the buffer will be written, followed by a valid CRe.
NOTE 2
The Write Sector function does
not
destroy the contents of the sector buffer.
3.3.4 Read Sector (011)
This function is used to locate a desired track and sector and transfer the contents of the data field to the pCPU controller sector buffer. The initiation of this function clears bits 0, 1, and 6 of RXES (CRC Error, Parity Error,
Deleted Data Detected) and negates Done.
When TR is asserted, the program must load the desired sector address into the RXDB, which will negate TR. When
TR is again asserted, the program must load the desired track address into theRXDB, which will negate TR.
If the desired track is not found, the RXll will abort the operation, move the contents of the RXES to the RXDB, set RXCS bit 15 (Error), assert Done, and initiate an interrupt if RXCS bit 6 (Interrupt Enable) is set.
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3-6
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TR and Done wl11 remain negated while the RXOI attempts to locate the desired track and
~ector.
If the RXOI is unable to locate the desired sector within two diskette revolutions after locating the presumably correct track, the
RXll will abort the operation, move the contents of the RXES to tlie RXDB, set RXCS bit 15 (EiTor), assert Done, and initiate an interrupt if RXCS bit 6 (Interrupt Enable) is set.
If the desired sector is successfully located, the control will attempt to locate a standard data address mark or a deleted data address mark. If either mark is properly located, the control will read data from the sector into the sector buffer.
If the deleted data address mark was detected, the control will assert RXES bit 6 (DD). As data enters the sector buffer, a CRC is computed, based on the data field and CRC bytes previously recorded. A non-zero residue indicates that a read error has occurred; The control sets RXES bit 0 (CRC Error) and RXCS bit 15 (Error). The RXll ends the operation by moving the contents of the RXES to the RXDB, sets Done, and initiates an interrupt if RXCS bit 6
(Interrupt Enable) is set.
3.3.5 Read Status (101)
The RXll will negate RXCS bit 5 (Done) and begin to assemble the current contents of the RXES into the RXDB.
RXES bit 7 (Drive Ready) will reflect the status of the drive selected by RXCS bit 4 (Unit Select) at the time the function was given. All other RXES bits will reflect the conditions created by the last command. RXES may be sampled when RXCS bit 5 (Done) is again asserted. An interrupt will occur if RXCS bit 6 (Interrupt Enable) is set.
RXES bits are defined in Paragraph 3.2.2.
NOTE
The average time for this function is 250 ms. Excessive use of this function will result in substantially reduced throughput.
3.3.6 Write Sector with Deleted Data (110)
This operation is identical to function 010 (Write Sector) with the exception that a deleted data address mark precedes the data field instead of a standard data address mark (paragraph 1.3.3.2).
3.3.7 Read Error Register Function (111)
The Read Error Register function can be used to retrieve explicit error information provided by the J.lCPU controller upon detection of the general error bit. The function is initiated, and bits 0~6 of the RXES are cleared. Out is asserted and Done is negated. The controller then generates the appropriate number of shift pulses to transfer the specific error code to the Interface register and completes the function by asserting Done. The Inte:rface register can now be read and the error code interrogated to determine the type of failure that occurred (paragraph 3.6).
NOTE
Care should be exercised in use of this function since, under certain conditions, erroneous error information may result
(Paragraph 3.5).
3.3.8 Power Fail
There is no actual function code associated with Power Fail. When the RXOI senses a loss of power, it will unload the head and abort all controller action. All status signals are invalid while power is low.
When the RXOI senses the return of power, it will remove Done and begin a sequence to:
1. Move drive 1 head position mechanism to track O.
2. Clear any active error bits.
3-7
(
3. Read sector 1 of track 1 of drive 0 into the sector buffer.
4. SetRXES bit 02 (Initialize Done) (paragraph 3.2.2.4) after which Done is again asserted.
5. Set Drive Ready of the RXES"according to the status of drive O.
There is no guarantee that information being written at the time of a power failure will be retrievable. However, all other information on the diskette will remain unaltered.
Amethod of aborting a function is through the use of RXCS bit 14 (RXll Initialize). Another method is through the use of the system Initialize signal that is generated by the PDP-II RESET instruction, the console START key, or system power failure. "
3.4 PROGRAMMING EXAMPLES
3.4.1 Read Data/Write Data
Figure 3-6 presents a program for implementing a Write, Write Deleted Data, or a Read ftinction, depending on the function code that is used. The first instructions set up the error retry courtters, PTRY, CTRY, and STRY. The instruction RETRY moves the command word for a Write, Write Deleted Data, or Read into the RXCS.
The set of three instructions beginning at the label 1$ moves the sector address to the RXll after TransferRequest
(TR), which is bit 7, has been set. The three instructions beginning at the label 2$ move the track address to the
RXll after TR has been set. The group of instructions beginning at the label 3$ looks for the Done flag to set and checks for errors.
An error condition, indicated by bit 15 setting, is checked beginning at ERFLAG. If bit 0 is set, a CRC error has occurred, and a branch is made to CRCER. If bit 1 is set, a parity error has occurred, and a branch is made to
PARER. If neither of the above bits is set, a seek error is assumed to have occurred and a branch is made to
SEEKER, where the system is initialized. In the case pf a Write function, the sector buffer is refilled by a IMP to
FILLBUF. In the case of a Read function, a JMP is made to EMPBUFF.
In each of the PAR, CRC, and SEEK routines, the command sequence is retried ten times by decrementing the respective retry counter. If an error persists after ten tries, it is a hard error. The retry counters can be set up to retry as many times
as
desired.
NOTE
A Fill Buffer function is performed before a Write function, and an Empty Buffer function is performed after a Read function.
3.4.2 Empty Buffer Function
Figure 3-7 shows a program for implementing an Empty Buffer function. The first instruction sets the number of error retries to ten. The address of the memory buffer is placed. in register RO, and the Empty Buffer command is placed in the RXCS. Existence of a parity error is checked starting at instruction 3$. If a parity error is detected, the
Empty Buffer command is loaded again. If an error persists for ten retries, the error is considered hard.
(
(
(
3-8
(
(
(
(
\
(
6
7
8
9
1
2
3
4
,
41
42
43
44
45
46
47
4B
49
511
51
52
24
25
26
27
28
29
311
31
32
33
34
35
36
37
38
39
411
1m
11
12
13
14
15
16 SSIIUI
17 II II I19S6
18 111111114
19
211
21
22
23
11111111311
1111111134
111111936
1111111144
11l1li1151
111111152
1111l1li611
1111111166
11111111711
111111974
111111076
54
55
56
57
58
59
60
61
62 IISIIUII
63 111111136
64 1III1I1U
65 111111116
66
67
68
69
711
71
72
73
74
75 1111111211
76 IIIIU24
77 IIIIU26
7B
79
811
81
82
83
84
85
B6
87 110e1311
88 111111134
89 111111136
91
92
93
94
95
96
97
98
99 II IIU 411
11111
1111
1112
1113
1114
1115
1116
1117 IIIIU46
1118 IIIIU52
1119 111111154
1771711
177172
177172
177172
177172
1112767
1112767
1112767
111'767
1111177'
116767 lU767
111117"
116767
1132767
11111774
1111'767
1111111111
II~IIIIIIII
1132767
1101414
032767
111114114
011'267
IIIIiJ36
II II lIB II II
11115267
11111332
11111111011
1112767
1111'267
IIIIiJ23
11111191111
1777711
1777711
1777711
1771211
111111262
1111113211
II lIB 314
1111113111
,
,
.JoBS
~Xll
~XU/RXI1 FLExIBLE DISKETTE
STANDARO DEVICE ADORESS AND VECTO~ AODRESS
RXCS'177171
Rxoa'177172
RXShl17172
COMMAND ST nus REG liTER
DATA BurrER REG lITER
SECTOR ADDRESS REG !STU
RXTA'117172
,
;
~~E w~m~w ~~!T~ s
O~L.mgR~=~! ~G o~X:~:~E
A
~r Imo~R~~~C~~H~EmmTS
OF mmM
,
START I
,
MOV
HOV
MOV
'-11.
,-u.
pTRV
CTRV
STRV
TRACK AOORUS REG liTER
ERROR ITnus REGIITtR
; PAR I TV REay COUNTER
; CRC RtTRY COUNTER
• SEEK RETRY COUNTER
;WRITE. WRITE DELETED OATA. OR RUO
• B I T5 4 THRU 1 OF PROGRAM L.oCAT I ON COMMAND OONTA I N THE FUNCTI ON
,
,
,
4 •
3
1 MEANS UNIT 1 ( • I MUNI UNIT
THRU l i S THE COMMAND (
MOV COMHAND. RXCS
4 •
I)
WRITE. 14 • WRITE OEL.ETtO OATA.
; WA I T FOR THE TRANSFEH REQUEST FL.AG THEN TRANSFER THE 'ECTOR ADDRESS
6 • RtAO)
; UNlT • ,(WRITE. WRITE OEL.ET~O DATA. OR READ)
177112
TSTB RX.CS
BEQ 11
Move SECTOR. RXSA
•
TRA~SFER THE TRACK ADDRESS
TSTB RXCS eEQ 21
Mova TRACK. RXTA
1771112
I
~Sl BIT _DONE9IT.
BEQ 31
TST RXCS
BNE ERFLAG
HHT
RXCS
; THE ERROR nAG IS
; sn
I THE CONTENTS OF THE HXES IS THE ERRoR STATU'
.IF THE RXES BITS 1 ANO ~ •
• tr THE RXES BIT ~ • 1 THEN
; IF THE RXES Bn 1 • • THEN
;
;
ERFL.AD I BIT '3. RXES
BEQ SEEK
BIT
'2.
BEQ CRC
RXES
THEN SOM!: TYPE OF SEEK ERRoR OCCURtD
CRC ERROR HAS OCCURtO
PARITY tRROR HAS OCCUREO
TEST FOR CRC AND PAR ITY ERRORS
NOT A PARITY OR CRC CMUSTl BE A SEEK
TEST FOR PARITY ERROR
NOT A PAR I TY ERROR C
;A PARITY ERROR HAS OCCUREO
;
,
L.OCATlO~ " ~TRY "
,AND RETRY THE· COMMAND· UNTIL. THE PARITY ERROR RECOVERS
•
• DR UNTIL. THE pTRY COUNTER OVER'L.OWS To
•
INC PTRY
BNE RETRY
HAL. T
RETRY THE COMMAND
HARD PAR I TV ERROR
,A CRC ERROR HAS oCCUHEO
;
,
• AND RETRY THE COMMAND UNTIL. THE CRC tRRDR RECoVER'
117~22
CRC I INC CTRY
BNE RETRY
HAl. T
RETRY THE COMMAND
,
IS SET
ITHE ERROR IS CNOTl A PARITY ERROR A~D I ' eNoTl A CRC [RRDR
I
,
I (STATE or Rxes 91 TS
;
AND 1 AR[ e)
MOV flNIT. RXCS INlTIAL.IIE sEEK; · lANO RETRY THE COMMAND UNTIL. THE SEEK ERROR RECoVERS
I
,
INC STRY
BNE RETRY
HAL T
RETRY THE COMMAND
HARD nEK ERROR
Figure 3·6 RXII Write/Write Deleted Data/Read Example
3·9
( lU
161
162
163
164 8~1242 ~127'7 177770 11115.
165 0~1251 a12701 00S342
166 101254 016767 001054 17.716
167
168
169
17~
171
172
173
174
175
176 111262 10'767 176722
177 118266 111114
178 811271 132767 0~1041 176672
179 111276 111771 lBI
181
182
183
184
185 001301 01'767 176664 lB6 111314 001101
187 ~~1316 001100 lBB lB9
191
19.1
192
193
194
195 111311 01'267 ~a1112
196 1~1314 0113"
197 300316 000101
198
199
201
201
202
203 011321 116730 17~646
204 001324 0017'6
206
207
208 010326 000000
219 311331 ~allli
211 001332 O~0100
2tl
212
213
214
215
216 0~1334 001101
217
218
219
22S 011336 00110~
221
222
223
224 011341 001100
225
226
227
22B
229
231
231
232
001140
040111
000342
000,42
001101
I
ITHE rO~~OWING IS A PROGRAMHING EXAH~~E or P~OTOCO~ REQUIRED TO
IEMpTY TilE SECTOR aurrER or 121 8-81T BYTES
I
EENTRYI MOV
ESETUPI HOV
HOV
_-u. pTRY nurrER. HI!.
COMHAND. Rxes
8 T~YS TO EMpTY THE lECTOR BurrER
PROHGRAHS OATA Bur'E~
ISSUE THE COMMAND
I
IWAIT rOR A TRANSPER REQUEST r~AG anDRE TRANsrERRING DATA To THE PROG~AMS
I
IDATA BurrER rRaN THE RXll SECTOR Bur'ER
I
IWAIT
I
IpllleR
I
E~OOPI rOR A DONE P~AC To INDICATE THE COHp~ETloN 0' THE EH~TY BUrrER COMMANP
TO TESTIN G THE ERROR r~AG
TSTB Rxes
HMI EMPTY alT _DONEBIT. Rxes aEQ E~OOP
TEST rOR T~ANsrER REQUEST 'LAG
INE Ir TRA~srER REQUEST '~AG IS SET
TEIT rOR DONE r~'G lEa UNTI~ 'HE DONE rLAC lETS
I
ITHE DONE rLAG IS SET
I
ITEST rOR ANY ERRORS (ON~Y ERRoR poSSI'~E IS A PARITY ERROR I
,
TST RXCS aNE 11
HA~T
I
NO E~RORI - OK COM~~[TE
I INcrEMENT AND TEST THE PARITY ERROR RET~Y P~OGRAM ~OCATloN • ~TRY "
I lAND RETRY THE CoMMAND UNTI~ THE ERROR RECOVERS
I lOR UNTI~ THE PTRY CUNTER oVERr~oWs TO I
I
15:
,
,
INC PTRY
SNE ESETUP
HALT
'~AG Is SET
RETRY TO EMPTY THE SECTO~ BurfER
~ARD PARITY ERROR
ITRANSfER OATA TO THE PROGRAM DATA BUrrER r~OM THE RXI1 SECTOR BurfER
I
EMPTYI (RI,+
SR ELOOP
ITHE rO~~OWING 3 PROGHAM ~OCATIONS ARE TWE ERROR RETRY COUNTERS
I
PTRy: 0
CTRy; I
, a
I PARITY ERRDR RETRY COUNTER
1
CRC ER~OR RETRy COUNTER
I SEEK E~ROR RETRY COUNTER
,PROGRAM ~OCATION " COMMAND" CONTAINS ~WE COMMA~D TO aE IssUED VIA THE LCD lOT
I
IWRITE (4)' WRITE DELETED DATA (141. O. ~EAD
(6).
OR EMPTY BurrER (21
I
COMMAND I ; 4. 14. 6. OR 2 • (CO BIT 1 • 11
I
'PROGRAM ~OeATION " SECTOR" CONTAINS THE SECTOR ADDREIS (1 TO 32 oeTA~1
I
SECTORI I!
1
1 TO 3. OCTAL
I
'PROGRAM ~OCATION " TRACK • CONTAINS TWE TRACK ADDRESS (I TO 114 OCTA~I
I
TRACK I I ; I TO 114 OCTA~
I
IpROGRAM EQUIVA~ENTS
I
DONEBIT.41
INIT·41IU
BUrrER-.
•• aurrER+201
.ENO
Figure 3-7 RXll Empty Buffer Example
(
(
(
3-10
(
(
(
(
If no error is indicated, the program looks for the Transfer Request (TR) flag to set. The Error flag is retested if TR is not set. Once TR sets, a byte is moved from the RXII sector buffer to the core locations of BUFFER. The process continues until the sector buffer is empty and the Done bit is set.
3.4.3 Fill Buffer Function
Figure 3-8 presents a program to implement a Fill Buffer function. It is very similar to the Empty Buffer example.
3.5 RESTRICTIONS AND PROGRAMMING PITFALLS
A set of restrictions and programming pitfalls for the RXll is presented below.
I. Depending on how much data handling is done by the program between sectors, the minimum interleave of two sectors may be used, but to be safe a three-sector interleave is recommended.
2. If an error occurs and the program executes a Read Error Register function (111), a parity error may occur for that command. The error status would not be for the error in which the Read Error Register function was originally required.
3. The DRY SEL RDY bit is present only at the time of a Read Status function (101) for both drives, and after an Initialize, depending on the status of drive O.
4. It is not required to load the Drive Select bit into the RXCS when the command is Fill Buffer (000) or
Empty Buffer (010).
5.
Sector Addressing: 1-26 (No sector 0)
Track Addressing: 0-76
6. A power failure causing the recalibration of the drives will result in a Done condition, the same as fmishing reading a sector. However, during a power failure, RXES bit 2 (Initialize Done) will set.
Checking this bit will indicate a power fail condition.
7. Excessive usage of the Read Status function (101) will result in drastically decreased throughput, because a Read Status function requires between one and two diskette revolutions or about 250 ms to complete.
3.6 ERROR RECOVERY
There are two error indications given by the RXII system. The Read Status function (paragraph 3.3.5) will assemble the current contents of the RXES (paragraph 3.2.2), which can be sampled to determine errors. The Read Error
Register function (paragraph 3.3.7) can also be used to retrieve explicit error information. The RXll Interface register can be interrogated to determine the type of failure that occurred.
A list of error codes is presented on the following page.
NOTE
A Read Status function is not necessary if the DRY RDY bit is not going to be interrogated, because the RXES is in the
Interface register at the completion of every function.
(
3-11
(
Octal
Code
0010
0020
0030
0040
0050
0060
0070
0110
0120
0130
0140
0150
0160
0170
0200
0210
. Error Code Meaning
Drive 0 failed to see home on Initialize.
Drive 1 failed to see home on Initialize.
Found home when stepping out 10 tracks for INIT.
Tried to access a track greater than 77.
Home was found before desired track was reached.
Self-diagnostic error.
Desired sector could not be found after looking at 52 headers (2 revolutions).
More than 40 fJS and no SEP clock seen.
A preamble could not be found.
Preamble found but no I/O mark found within allowable time span.
eRe
error on what we thought was a header.
The header track address of a good header does not compare with the desired track.
Too many tries for an IDAM (identifies header).
Data AM not found in allotted time.
eRe
error on reading the sector from the disk. No code appears in the ERREG.
All parity errors.
(
..
( c
3-12
(
(
(
(
137
138
139
141
141
142
143
144
145
146
147
148
149
151
151
152
153
154
155
156
157
158
119
121
121
122
123
124
125
126
127
128
129
131
131
132
111
112
113
114
115
116
117
118
133
134
135
136
, rO~~OWING IS A ~HOGRAMMING EXAM'~E or T~E PROTOCO~ REQUIRED TO
IrI~L THE SECTOR SUfrER WITH 128 a-S!T BYTES
1
I NOTE: THE DATA To rI~~ THE SECTO~ BurrER CAN BE ASSEMBLEO IN CORE IN THE
I EVEN ADDRESSES BYTES 0' 12a WO~D' OR IN BOTH BYTES or 64 WORDS
I
080156 012767 177773 010142 fENTRY: HOV _'10, PTRY ell164 012701 000342 ell17S 016767 ~01140 176712
SETUPI
,
HOV _BUfrER, H0
HOV COMMAND, Rxes e
TRYS TO 'ILL THE SECTOR BurfER
'ROGRAMS DATA BurrER
ISSUE THE COMMANO
IWAIT rOR A TRANSfER REQUEST r~AQ BErORE TRANsrERRING DATA rRoM THE ~ROGRAMS
ISS176 10,767 176766
0012e2 ee1414
100204 e32767 0~0041 1767'6
IU212 0U771
I
,
IWAIT rOR A DONE rLAT TO INDICATE THE COMPLETION
I
IPRloR TO TESTING THE ERROR r~AG
I
LOOPI TSTB Rxes tlMl rILL
BIT _DONEBIT, RXCS
SEa LOOP
or
THE r!LL BurrER COMMAND
TEST rOR T_ANsrER REQUEST r~AG
IEQ Ir TRANsrER REQUEST f~AG SET
TEST rOR TWE DONt r~AG
BEQ UNTI~ THE DONE r~AQ SETS
I
,THE DoNE ,LAG IS SET
I
ITEST FOR ANY ERRORS (oN~Y ERROR PoSSI!~E IS A ~ARITY ERROR)
~aa214
~0"222 e0,767 17615~
U022~ 01U~1
3e0800
000224 005267 03~~76 a31230 a01355
0a11232 a0allell
0011234 113067 176732
1101l24~ 31111756
,
,
.
TST RXCS
SNt 1$
HA~T
UNTI~
; NO t~RORS • OK COM'~ETE
R£T~Y P~OGRAM ~OCATIoN
THE ERROR RECoVERS lOR UNTI~ THE PTRY COUNTER OVERFLOWS TO
• ~TRY •
I lS: INC PTRY
SNE SETUP
HALT
RETRY TO F!~L THE SECTOR BurrER
~ARO ~ARITY ERROR
I
,THE TRANSFER REQUEST r~AG IS SET
I
ITRANSfER CATA fROM THE PROGRAMS OATA BurfER TO THE RX01 SECTOR BurfER
I rIL~: MOVB
SR
'(RIl)+,
LOOP
RXDS ; PROGRAMS DATA surFER IS 64 woRes IN ~ENGTH
Figure 3-8 RXll Fill Buffer Example
3-13
(
(
(
(
CHAPTER 4
RX8E INTE·RF ACE
PROGRAMMING INFORMATION
The RX8E interface allows two modes of data transfer: 8-bit word length and 12-bit word length. In the 12-bit mode, 64 words are written in a diskette sector, thus requiring two sectors to store one page of information. The diskette capacity in this mode is 128,128 12-bit words (1,001 pages). In the 8-bit transfer mode, 128 8-bitwords are written in each sector. Disk capacity is 256,256 8-bit words, which is a 33 percent increase in disk capacity over the 12-bit mode. Eight-bit mode must be used for generatiIig IBM-compatible diskettes, since 12-bit mode does not fully pack the sectors with data. The hardware puts in the extra Os. Data transfer requests occur 23 IlS after the previous request was serviced for 12-bit mode (I8 IlS for 8-bit mode ).There is no maximum time between the transfer request from the RXOI and servicing of that request by the host processor. This allows the data transfer to and from the RXOI to be interrupted without loss of data.
4.1 DEVICE CODES
. The eight possible device codes that can be assigned to the interface are 70-77. These device codes define address locations of a specific device and allow up to eight RX8E interfaces to be used on a single PDP-8. These multiple device codes are also shared with other devices. Depending on what other devices are on the system, the RX8E device code can be selected to avoid conflicts. (Refer to the PDP-8 Small Computer Handbook for specific device codes.)
The device codes are selected by switches according to Table 4-1. These switches control AC bits 6-8, while AC bits
3-5 are fixed at 1 s. The device code is initially selected to be 70. Switches 7 and 8 are not connected and will not affect the device selection code. The switches are all located on a single DIP switch package that is located on the
M8357 RX8E interface board.
Table 4-1
Device Code Switch Selection
Device
Code
73
72
71
70
77
76
75
74
SI S2 S3 S4 S5 S6 S7 S8
0 0 0 1 1 1 X X
0 0
1
1 1 0 X X
0 1 0 1 0 1 X X
0 1 1 1 0 0 X X
1 0 0 0 I 1 X X
1 0 1 0 1 0 X X
1 1 0
0 0 1 X X
1 1 1
0 0 0 X X
o
(OFF) 1 (ON). c::::J SI c:::J S2 c::::J S3 c::::J S4 c:J S5 c::::J S6 c:J S7 c::::J S8
(
4-1
(
4.2 INSTRUCTION SET
The RX8E instruction set is listed below and described in the following paragraphs. lOT
67xO
67xl
67x2
67x3
67x4
67xS
67x6
67x7
Mnemonic
LCD
XDR
STR
SER
SDN
INTR
INIT
Description
No Operation
Load Command, Clear AC
Transfer Data Register
Skip on Transfer Request Flag, Clear Flag
Skip on Error Flag, Clear Flag
Skip on Done Flag, Clear Flag
Enable or Disable Disk Interrupts
Initialize Controller and Interface
4.2.1 Load Command (LCD) - 67xl
This command transfers the contents of the AC to the Interface register and clears the AC. The RXOI begins to execute the function specIfied in AC 8, 9, and lOon the drive specified by AC 7. A new function cannot be initiated unless the RXOI has completed the previous function. The command word is defined as shown in Figure 4-1.
00 01 02 03 04 05 06 07 08 09 10 11
", c
DRV
SEL.
FUNCTION
8/12
NOT
USED
CP-l~14
Figure 4-1 LCD Word Format (RX8E)
The command word is described in greater detail in Paragraph 4.3.1.
4.2.2 Transfer Data Register (XDR)- 67x2
With the Maintenance flip-flop cleared, this instruction operates as follows. A word is transferred between the AC and the Interface register. The direction of the transfer is governed by the RX01, and the length of the word transferred is governed by the mode selected (8-bit or 12-bit). When Done is negated, executing this instruction indicates to the RX01:
1. That the last data word supplied by the RXOI has been accepted by the PDP-8, and the RXOI can proceed, or
2. That the data or address word requested by the RXOI has been provided by the PDP-8, and the RXOI can proceed. '
A data transfer (XDR) from the AC always leaves the AC unchanged. If operation is in 8-bit mode, AC 0-3 are transferred to the Interface register but are ignored by the RX01. Transfers into the AC are 12-bit jam transfers when in 12-bit mode. When in 8-bit mode, the 8-bit word is ORed into AC 4-11, and AC 0-3 remain unchanged.
When the RXOI is done, this instruction can be used to transfer the RXES status word from the Interface register to the AC. The selected mode controls this transfer as indicated above.
(
(
'.
~:
(
4-2
(
(
( c
4.2.3 STR - 67x3
This instruction causes the next instruction to be skipped if the Transfer Request (TR) flag has been set by RXOI and clears the flag. The TR flag should be tested prior to transferring data or address words with the XDR instruction to ensure the data or address has been received or transferred, or after an LCD instruction to ensure the command is in the Interface register. In cases where an XDR follows an LCD, the TR flag needs to be tested only once between the two instructions. (See programming example in Paragraph 4.5.1.)
4.2.4 SER - 67x4
This instruction causes the next instruction to be skipped if the Error flag has been set by an error condition in the
RXOl and clears the flag. An error also causes the Done flag to be set (paragraph 4.3.6).
4.2.5 SDN - 67xS
This instruction causes the next instruction to be skipped if the Done flag has been set by the RXOI indicating the completion of a function or detection of an error condition. If the Done flag is set, it is cleared by the SDN instruction. This flag will interrupt if interrupts are enabled.
4.2.6 INTR - 67x6
This instruction enables interrupts by the Done flag if AC 11 = I. It disables interrupts if AC 11 = O.
4.2.7 INIT - 67x7
The instruction initializes the RXOI by moving the head position mechanism of drive 1 (if drive 1 is available) to track O. It reads track 1, sector 1 of drive O. It zeros the Error and Status register and sets Done upon successful completion of Initialize. Up to 1.8 seconds may elapse before the RXOl returns to the Done state. Initialize can be generated programmably or by the Omnibus Initialize.
4.3 REGISTER DESCRIPTION
Only one physical register (the Interface register) exists in the RX8E, but it may represent one of the six RXOI registers described in the follOwing paragraphs, according to the protocol of the function in progress.
4.3.1 Command Register (Figure 4-2)
The command is loaded into the Interface register by the LCD instruction (paragraph 4.2.1). c
00 01 02 03 04 05 06 07 08 09 10 11
FUNCTION
8/12 DRV
SEL
Figure 4-2 Command Register Format (RX8E)
NOT
USED
CP-1514
4-3
(
The function codes (bits 8, 9, 10) are summarized below and described in Paragraph 4.4.
Code
000
001
010 all
100
101
110
111
Function
Fill Buffer
Empty Buffer
Write Sector
Read Sector
Not used
Read Status
Write Deleted Data Sector
Read Error Register
The DRV SEL bit (bit 7) selects one of the two drives upon which the function will be performed:
AC7=0
AC 7= 1
Select drive
a
Select drive 1
The 8/12 bit (bit 5) selects the length of the data word.
AC 5
= a
AC 5 = 1
Twelve-bit mode selected
Eight-bit mode selected
The RX8E will initialize into 12-bit mode.
4.3_2 Error Code Register (Figure 4-3)
Specific error codes can be accessed by use of the Rear Error Register function (111) (paragraph 4.4.7). The specific octal error codes are given in Paragraph 4.7.
00 01
02 03 04 05 06 07 08 09 10 11
(
(
)-
'---_~~~-----'J\~-------~~------------'
NOT USED ERROR CODE
CP-1515
Figure4-3 Error Code Register Format
The Maintenance bit (M bit) can be used to diagnose the RX8E interface under off-line and on-line conditions. The off-line condition exists when the BC05L-15 cable is disconnected from the RXO 1; the on-line condition exists when the cable is connected to the RXOl.
If an LCD lOT (I/O Transfer) is issued with AC 4 = 1, the Maintenance flip-flop is set. When the Maintenance flip-flop is set, the assertion of RUN on following XDR instructions is inhibited, and all data register transfers (XDR) are forced into the AC. The Maintenance bit allows the Interface register to be written and read for maintenance checks. The Maintenance flip-flop is cleared by Initialize or by an LCD lOT with AC 4 = O.
The following paragraphs describe more explicitly how to use the Maintenance bit in an off-line mode.
The contents of the interface buffer cannot be guaranteed immediately following the first LCD lOT, which sets the
Maintenance flip-flop. However, successive LCD lOTs will guarantee the contents of the Interface register. The contents of the Interface register can then be verified by using the XDR lOT to transfer those contents into the AC. (
(
4-4
(
(
(
In addition, the Maintenance flip-flop directly sets the Skip flags, which will remain set as long as the Maintenance flip-flop is set. Skipping in these flags as long as the Maintenance flip-flop is set will not clear the flags. Setting and then clearing the Maintenance flip-flop will leave the Skip flags in a set condition. The skip lOTs can then be issued to determine whether or not a large portion of the interface skip logic is working correctly.
The Maintenance flip-flop can also be used to determine if the interface is capable of generating an interrupt on the
Omnibus. The Maintenance flip-flop is set, thus causing the Done flag to set. The Interrupt Enable flip-flop can be set by issuing an INTR lOT with AC bit 11
=
1. The combination of Done and Interrupt Enable should generate an interrupt.
The Maintenance flip-flop can also be used to test the INIT lOT. The Maintenance flip-flop is set and cleared to generate the flags, and INIT lOT is then executed. If execution of INIT lOT is internally successful, all of the flags and the Interrupt Enable flip-flop should be cleared if they were previously set.
In the on-line mode, use of the Maintenance bit should be restricted to writing and reading the Interface register.
The same procedure described to write and read the Interface register in the off-line mode should be implemented in the on-line mode. Additional testing of the RX8E in the on-line mode should reference the appropriate circuit schematics. Exiting from the on-line Maintenance bit mode should be finalized by an initialize to the RXOI.
4.3.3 RXT A - RX Track Address (Figure 4-4)
This register is loaded to indicate on which of the 77 tracks a given function is to operate. It can be addressed only under the protocol of the function in progress (paragraph 4.4). Bits 0 through 3 are unused and are ignored by the control.
II 00 02 03 01
I I I I
0
NOT USED
04 05 06 07 08 09 10
0-1148
I
CP-1516
I
I
Figure 44 RXTA Format (RX8E)
4.3.4 RXSA - RX Sector Address (Figure 4-5)
This register is loaded to indicate on which of the 26 sectors a given function is to operate. It can be addressed only under the protocol of the function in progress (Paragraph 4.4). Bits 0 through 3 are unused and are ignored by the control.
02 03 04 05 06
...
I
00 01
NOT USED
07 08 09
1- 32 8
10 II
CP-1517
Figure 4-5 RXSA Format (RX8E)
(
4-5
4.3.5 RXDB - RX Data Buffer (Figure 4-6)
All information transferred to and from the floppy media passes through this register and is addressable only under the protocol of the function in progress. The length of data transfer is either 8 or 12 bits, depending on the state of bit 5 of the Command register when the LCD lOT is issued (paragraph 4.3.1).
(
00 01 02 03 04 05 06 07 08 09 10 11
1281T
MOOE ONLY
8 or 12 BIT
MODE
CP-1518
Figure 4-6 RXDB Format (RX8E)
4.3.6 RX Error and Status (Figure 4-7)
The RXES contains the current error and status conditions of the selected drive. This read-only register can be accessed by the Read Status function (101). The RXES is also available in the Interface register upon completion of any function. The RXES is accessed by the XDR instruction. The meaning of the error bits is given below. c
Bit No.
11
10
9
00 01 02 05 03 04
I
DRV
RDY
J
DD
.....
NOT USED
06 07
.....
NOT USED
08
J
I ID
09 10 11
PAR
I
CRC
I
CP-1519
Figure 4-7 RXES Format (RX8E)
Description
CRC Error - The cyclic redundancy check at the end of the header or data field has indicated an error. The header or data must be considered invalid; it is suggested that the data transfer be retried up to ten times, as most data errors are recoverable (soft). (See
Chapter 6).
Parity Error - When status bit 10 = 1, a parity error has been detected on command and address information being transferred to the RX01 pCPU controller from the RX8E interface. Upon detection of a parity error, the current function is terminated, the RXES status word is moved to the Interface register, and the Error and Done flags are set. The function can be retried to determine if the parity error is a soft or hard error. A parity error indication means that there is a problem in the interface cable between the RX01 and the interface.
Initialize Done - This bit indicates completion of the Initialize routine. It can be asserted due to RX01 power failure, system power failure, or programmable or bus Initialize. This bit is not available within the RXES from a Read Status function.
(
(
(
4-6
(
(
( c
Bit No.
5
4
Description
Deleted Data (DD) - In the course of reading data, a deleted. data mark was detected in the identification field. The data following will be collected .and transferred nqrmally, as the deleted data mark has no further significance within the RX01. Any alteration of mes or actual deletion of data due to this mark must be accomplished by user software. This bit will be set if a successful or unsuccessful Write Deleted Data function is performed.
Drive Ready - This bit is asserted if the unit currently selected exists, is properly supplied with power, has a diskette nlstalled properly, has its door closed, and has a diskette up to speed.
NOTE 1
This bit is only valid for either drive when retrieved via a Read
Status function or for drive 0 upon completion of an Initialize.
NOTE 2
If the Error bit was set in the RXCS but Error bits are not set in the RXES, then specific error conditions can be accessed via a Read Error Register function.
4.4 FUNCTION CODE DESCRIPTION
RX8E functions are initiated by means of the Load Command lOT (LCD). The Done flag should be tested and cleared with the SDN instruction in order to verify that the RX8E is in the Done state prior to issuing the LCD instruction. Upon receiving an LCD instruction while in the Done state, the RX8E enters the Not Done state while the command is decoded. Each of the eight functions summarized below requires that a strict protocol be followed for the successful transfer of data, status, and address information. The protocol for each function is described in the following sections, and a summary table is presented below.
Octal
0
2
4
6
10
12
14
16
AC
8 9 10
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
. Function
Fill Buffer
Empty Buffer
Write Sector
Read Sector
Not Used
Read Status
Write Deleted Data Sector
Read Error Register
NOTE
AC bit 11 is assumed to be 0 in the above o.ctal codes, since
AC bit 11 can be 0 or 1.
4.4.1 Fill Buffer (000)
This function is used to load the RXOl sector buffer from the host processor with 64 12-bit words if in 12-bit mode or 128 8-bit words if in 8-bit mode. This instruction only loads the sector buffer. In order to complete the transfer to the diskette, another function, Write Sector, must be performed. The buffer may also be read back by means of the Empty Buffer function in order to verify the data.
4-7
(
Upon decoding the Fill Buffer function, the RX01 will set the Transfer Request (TR) flag, signaling a request for the first data word. The TR flag must be tested and cleared by the host processor with the STR instructions prior to each successive XDR lOT (paragraph 4.2.3). The data word can then be transferred to the Interface register by means of the XDR lOT. The RX01 next moves the data word from the Interface register to the sector buffer and sets the TR flag as a request for the next data word. The sequence above is repeated until the sector buffer has been loaded (64 data transfers for 12-bit mode or 128 data transfers for 8-bit mode). After the 64 th (or 128th) word has been loaded into the sector buffer, the RXES is moved to the Interface register, and the RX01 sets the Done flag to indicate the completion of the function. It is, therefore, unnecessary for the host processor to keep a count of the data transfers. Any XDR commands after Done is set will result in the RXES status word being loaded in the AC.
The sector huffer must be completely loaded before the RX8E will set Done and recognize a new command. An interrupt would now occur if Interrupt Enable were set.
4.4.2 Empty Buffer (001)
This function moves the contents of the sector buffer to the host processor. Upon decoding this function, RXES bits
10 and 11 (parity Error and CRC Error) are cleared, and the TR flag is set with the first data word in the Interface register. This TR flag signifies the request for a data transfer from the RX8E to the host processor. The flag must be tested and cleared, then the word can be moved to the AC by an XDR command. The direction of the transfer for an XDR command is controlled by the RX01. The TR flag is set again with the next word in the Interface register.
The above sequence is repeated until 64 words (128 bytes if 8-bit mode) have been transferred, thus emptying the sector buffer. The Done flag is then set after the RXES is moved in the Interface register to indicate the end of the function. An interrupt would now occur. if Interrupt Enable were set.
NOTE
The Empty Buffer function does
not
destroy the contents of the sector buffer.
4.4.3 Write Sector (010)
This function transfers the contents of the sector buffer to a specific track and sector on the diskette. Upon decoding this function, the RX8E clears bits 10 and 11 (parity Error and CRC Error) of the RXES and sets the TR flag, signifying a request for the sector address. The TR flag must be tested and cleared before the binary sector address can be loaded into the Interface register by means of the XDR command. The sector address must be within the limits 1-328.
The TR flag is set, signifying a request for the track address. The TR flag must be tested and cleared, then the binary track address may be loaded into the Interface register by means of the XDR command. The track address must be within the limits 0-1148.
The RXOI tests the supplied track address to determine if it is within the allowable limits. If it is not, the RXES is moved to the Interface register, the Error and Done flags are set, and the function is terminated.
If the track address is legal, the RX01 moves the head of the selected drive to the selected track, locates the requested sector, transfers the contents of the sector buffer and a CRC character to that sector, and sets Done. Any errors encountered in the seek operation will cause the function to cease, the RXES to be loaded into the Interface register, and the Error and Done flags to be set. If no errors are encountered, the RXES is loaded into the Interface register and only the Done flag is set.
NOTE
The Write Sector function does
not
destroy the contents of the sector buffer.
.(/
.
(
( t,
(
4-8
(
(
(
4.4.4 Read Sector (011)
This function moves a sector of data from a specified track and sector to the sector buffer. Upon decoding this function, the RX8E clears RXES bits 5, 10, 11 (Deleted Data, Parity Error, CRC Error) and sets the TR flag, signifying the request for the sector address. The flag must be tested and cleared. The sector address is then loaded into the Interface register by means of the XDR command. The TR flag is set, signifying a request for the track address. The flag is tested and cleared by the host processor, and the track address is then loaded into the Interface register by an XDR command. The legality of the track address is checked by the RX01. If illegal, the Error and
Done flags are set with the RXES moved to the Interface register, and the function is terminated. Otherwise, the
RXOI moves the head to the specified track, locates the specified sector, transfers the data to the sector buffer, computes and checks CRC for the data. If no errors occur, the Done flag is set with the RXES in the Interface register. If an error occurs anytime during the execution of the function, the function is terminated by setting the
Error and Done flags with RXES in the Interface register. A detection of CRC error results inRXES bit II being set.
If a deleted data mark was encountered at the beginning of the desired data field, RXES bit 5 is set.
4.4.5 Read Status (l 01)
Upon decoding this function, the RXOI moves theRXES to the RX8E Interface register and sets the Done flag. The
RXES can then be read by the Transfer Data Register command (XDR). The bits are defmed in Paragraph 4.3.6.
NOTE
The average time for this function is 250 ms. Excessive use of this function will result in substantially reduced throughput.
4.4.6 Write Deleted Data Sector (110)
This function is identical to the Write Data function except that a deleted data mark is written prior to the data field rather than the normal data mark (paragraph 1.3.3.2). RXES bit 5 (Deleted Data) will be set in the RX8E Interface register upon completion of the function. .
4.4.7 Read Error Register Function (111)
The Read Error Register function can be used to retrieve explicit error information upon detection of the Error flag.
Upon receiving this function, the RXOI moves an error code to the Interface register and sets Done. The Interface register can then be read via an XDR command and the code interrogated to determine which type of failure
·occurred (paragraph 4.7).
NOTE
Care should be exercised in use of this function because, under certain conditions, erroneous error information may result
(paragraph 4.6).
4.4.8 Power Fail
There is no actual function code associated with Power Fail. When the RXOI senses a loss of power, it will unload the head and abort all controller action. All status signals are invalid while power is low.
When the RXOI senses the return of power, it will remove Done and begin a sequerice to:
1. Move drive I head position mechanism to track O.
2. Clear any active error bits.
3. Read sector I of track I of drive O.
4. Set Initialize Done bit of the RXES, after which Done is again asserted.
4-9
(
There is no guarantee that information being written at the time of a power failure will be retrievable. However, all other information on the diskette will remain unaltered.
A method of aborting an incomplete function is with the INIT lOT (paragraph 4.2.7).
4.5 PROGRAMMING EXAMPLES
4.5.1 Write/Write Deleted Data/Read Functions
Figure 4·8 presents a program for implementing a Write, Write Deleted Data, or a Read function with interrupts turned off (lOF). The first three steps preset the PTRY, CTRY, and STRY retry counters, which are set at ten retries but can be changed to any number. Starting at RETRY, the program tests for 8- or 12-bit mode, type of function, and drive. Once the command is loaded, the program waits in a loop for the controller to respond with
Transfer Request (TR). When TR is set, the sector address is loaded and the AC is cleared. The program loops while waiting for the controller to respond with another TR. When TR is reset, the track address is loaded, and the AC is cleared again. The program loops to wait for the Done condition.
When the Done flag is set, the program checks for an error condition, indicated by the Error flag being set. If the
AC = 0000, then the error is a seek error; if bit 10 of the AC is set, the error is a parity error; and if bit 11 of the AC is set, the error is a CRC error. Error status from the RXES is saved and tested to determine the error (paragraph
4.3.6). The RXES will not include the Select Drive Ready bit. If a parity error is detected, the program increments and tests the PTRY retry counter. If a parity error persists after ten tries, it is considered a hard error. If ten retries have not occurred, a branch is made to RETRY and the sequence repeated.
If the Parity Error bit of the RXES is not set, then the program tests to see if the CRC Error bit is set. If a CRC error is detected, the program increments and tests the CTRY retry counter. If a CRC error persists after ten retries, it is considered a hard error. If ten retries have not occurred, a branch is made to RETRY and the sequence repeated.
A seek error is assumed if neither a CRC nor a parity error is detected. An Initialize (lNIT) instruction is performed
(paragraph 4.2.7). During a Write or Write Deleted Data function, the sector buffer must be refilled, because INIT will cause sector 1 of track 1 of drive 0 to be read, which will destroy the previous contents of the sector buffer. The instruction sequence for a Fill Buffer function is not included in Figure 4-8, but is presented in Figure 4-10. After the system has been initialized, the program increments and tests the STRY retry counter. If a seek error persists after ten tries, it is considered a hard error. If ten retries have not occurred, a branch is made to RETRY and the sequence repeated.
4.5.2 Empty Buffer Function
Figure 4-9 shows a program for implementing an Empty Buffer function with interrupts turned off (IOF). The first instruction sets the number of retries at ten. A 2 is set in the AC to indicate an Empty Buffer command, and the command is loaded. When TR is set, the program jumps to EMPTY to transfer a word to the BUFFER location. A jump is made back to loop to wait for another TR. This process continues until either 64 words or 128 bytes have been emptied from the sector buffer. When Done is set, the program tests to see if the Error bit is set. If the Error bit is set, the program retries ten times. If the error persists, a hard parity error is assumed, indicating a problem in the interface cable.
4.5.3 Fill Buffer Function
Figure 4-10 presents a program to implement a Fill Buffer function. It is very similar to the Empty Buffer example.
(
(
(
(
4-10
(
( c~
(
(
1
2
3
4
5
6
7
8
9
1~
11
12
13
14
15
16
17
18
19
2~
21
22
23
24
25
44
45
46
47
48
49
5~
51
52
26
27
28
29
3~
31
32
33
34
35
36
37
38
39
4~
41
42
43
62
63
64
65
66
67
68
69
78
79
8~
81
82
83
84
85
86
87
88
89
7~
71
72
73
74
75
76
77
90
91
92
93
94
95
96
97
98
53
54
55
56
57
58
59
6~
61
6701
6702
67ZJ
6704
6705
6706
6797
0209 1254
0231 3255
02~2 1254
9203 32'6
9204 12,4 mz~5 3257
0206 1269
92m7 1261
9219 1262
~211 6701
9212 6703
9213 5212
9214 1263
1215 6702
~216 7299
0217 6703
0220 '217
0221 1264
9222 67~2
9223 729~
0224 6705
0225 5224
0226 6794
9227 74~2
0230 6702
0231 3265
9232 7305
9233 0265
9234 76'9
0235 5241
9236 2255
9237 '296
9240 74~2
0241 7Je1
1242 ~265
9243 76'~
9244 '2'0
I~ROGRAMHING
EXAHnES ro~
THE RX8/RX01 fLEXIBLE OISKETTE
I
/THE rOLLoWING ARE RX01 lOT CODE DEfiNITIONS
I
/THE STANDARD lOT DEVICE CODE IS 679·
I
LCD=67U
XDR'67n
STR'6703
IIOT TO LOAD THE COMMAND, lAC) IS THE COMMAND
IIOT TO LOAD OR READ THE TRANSrER REGISTER
IIOT TO SKIP ON.A TRANSrER REQUEST fLAG
SER'6704
SDN'67U
INTR'6706
INIT=6707
II
IIOT TO SKIP ON THE DONE nAG
I lAC) = 0 INT[RRU~T ENABLE 0'1'1 lAC) • 1 MEANS ON
1I0T TO INITULIAE THE RXS/RXll SUBSYSTEM
I
/THE fOLLOWING IS A PROGRAMMING EXAMPLE or THE PROTOCOL
~EQUIREO
I
/TO WRiTE, WRITE DELETED DATA, OR READ AT 'ECTOR "5" (THE CONTENTS or PROGRAM
I
ILOCATION SECTOR) or TRACK "T" ITHE CONTENTS or PROGRAM LOCATION TRACK)
I liN 8 OR 12 BIT MODE
I
START, TAO
~CA
TAD
~CA
TAO
~CA
KM10
PTRy
KMU
CTRY
KMU
STRY
I
IWRITE, WRITE OELETED DATA, OR READ
I
RETRY, TAD MODE
TAD COMMAND
I .10
I~ARITY RETRV COUNTER
ICRC . REHY COUNTER
ISEEK RETRY COUNTER
TAD UNIT
LCD
19 Ir U.SIT, 100 I ' a.BIT
I 4 I ' WAITE, 14 IF WRITE OE~ETED
IDATA, O~ 6 II' READ
I 0 I ' UN IT ~, 20 \I' UN I T 1
IIOT "Xl TO LOAD THE COMMAND
I
IWAIT rOR THE TRANSI'ER REQUEST FLAG THEN TRANSFER THE SECTOR ADDRESS
I
STR
JMP ,·1
TAD SECTOR
XOR
CLA
Ii0T 67U To
IWAIT I'OR TRANS'ER REQUEST 'LAG
I 1 TO 3Z(OCTAL)
/I oT TO ~OAD SECTOR
ICLA BECAUSE lOT XDR DOESN'T
I
IWA IT rOR THE TRANSI'ER REQUEST fLAG THEN TRANSFER THE TRACK ADDRESS
I
STR
JMP ,.1
TAD TRACK
XDR
CLA
/lOT 67X3 TO
IWAIT 'OR TRANSFER REQUEST
I 0 TO 11410CTAL)
1I0T TO LOAD TRACK
ICLA BECAUSE lOT XOR DOESN'T
/THE SECTOR AND TRACK ADDRESSES HAVE; aEEN TRANSFERRi:D TO THE RX01 VIA THE XDR lOT
I
IWAIT rOR THE OONE FLAG AND CHECK FOR ANY ERRORI
I
IIF THE FUNCTION HAS
COM~LETED
SUCCESSFULLY INa ERROR r~AG)
THEN HALT
I
SON
JMP ,.1
SER
H~ T
II OT 6'X' TO
IWA I T
/I
'O~
DONE FLAG
I OK • COMPLETED
I
ITHE ERROR rLAG IS SET
I
/THE CONTENTS OF THE TRANSfER REGISTER IS THE ERROR STATUS
I
II f TRANSfER REG I STER BITS 10, AND 11 • 0 THEN SOME rvPE or SEEK ERROR HAS OCCURED,
IIr TRANSFER REGISTER BIT 11 • 1 THEN CRC ERROR HAS OCCUREO,
III' TRANsrER REGISTER BIT 10 • 1 THEN PARITY ERROR HAS OCCURED
I
XOR
~CA ASTATUS
CLio CLA lAC RAL
AND ASTATUS
SNA CLA·
JMP TCRe;
I~ET CONTENT! or TR (ERROR STATUS) lANe SAVE
I 2
IT EST FOR PARITY ERROR
ISKIP II' PARITY tRROR
INOT A PARITY ERROR· MAYBE CRC
I
IA ~ARITY ERROR HAS OCCUREO
I
!INCREMENT ANO TEST THE PARITY ERROR· RETRY COUNTER PROGRAM LOCATION" PrAY"
I lAND RETRY THE" COMMAND" UNTIL THE PARITY ERROR RECOVUS
I lOR UNTIL THE PTRY COUNTER OVERfLOWS TO 0
I
IU PTRY
JMP RETRY
HLT
IRETRY THE COMMAND
IHARO PARITY ERROR
I
/THE
I
/TEST
I
TCRC,
ERROR FLAG IS SET BUT THE ERROR IS NOT A PARITY ERROR fOR A CRC ERROR
CLio CLA lAC
AND ASTATUS
SNA CLA
JMP SEEK
I 1
!TEST rOR A CRC tRROR
ISKIP I ' A C~C ERROR
INOT A CRC • MUST BE A SEEK
Figure 4-8 RX8E Write/Write Deleted Data/Read Example (Sheet 1 of 2)
4·11
(
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
130
131
132
133
134
135
136
137
138
139
140
141
168
169
170
171
172
173
119
120
121
122
123
124
125
126
127
128
129
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
024' 2256
0246 5206
0247 7402
0250 6707
0251 22'7
0252 5206
0253 7402
0254 7770
0255 0000
0256 0000
0251 0000
0263 0000
0264 0000
IA CRC .ERROR HAS DCCURED
I
~INCREMENT
AND TEST THE CRC ERROR RETRY
COUNTE~
PROGRAM ,OCATION " CTRY " lAND RETRY THE COMMAND UNTI, THE CRC ERROR RECOVERS
I lOR UNTI, THE CTRY COUNT!:R OVERF,OWS TO 0
I
IS! CTRY
JMP RETRY
HL.T
IRETRY T~E COMMAND
IHARO CRC ERROR
I
!THE ERROR F,AG I S SET
I
ITHE ERROR IS tNOTJ A PARITY ERROR ANC IS tNOTl A CRC ERROR
I
ITHEREFORE IS MUST BE A SEEK ERROR
I
I (CONH;NTS OF THE TRANSFER REGISTER ~ITS U. ANO 11
I
01
I
SEEK. INIT nOT 67X7 TO INITlI,IAt
I
/INCREMENT AND TEST THE. SEeK ERRoR RETRY COUNTER PROGRAM ,OCHION " STRY "
I lAND RETRY THE COMMAND UNTIL. THE SEEK ERROR RECOVERS
I lOR UNT I, THE CTRY COUNTER OVERFLOWS TO 0
I
IS! STRY
JMP RETRY
HL.T
IRE TRY T~e: COMMAND
IHARO SEtK ERROR
/THE FO"OWING PROGRAM ,OCATIONS ARE REFERENCED WITHIN T~IS [XAMP,t
I
KMU.
I
/THE FO"OW I NG 3 PROGRAM ,OCAT IONS ARE THE ERRoR RETRY COUNTERS
I
PTRY.
CTRy.
STRY.
IPAR I TY £RRO~ RETRY COUNTER
ICRe ERROR RETRy COUNTER
ISEEK ERROR RETRY COUNTER
I
IPROGRAM ,OCATION .. MOOE " CONTAINS A 0 IF 12-e1T MODE. OR
ICONTAINS A U0 IF 8-BIT MODE
I fIODE.
I
IPROGRAM ,OCATION " COMMANO .. CONTAINS THE COMMAND TO BE ISSUE:D VIA THE ,CO lOT
I
IWRITE (4), WRITE DE:LETED DATA (14). OR REAO (6). OR EMPTY SUFFER (2)
I
COMMAND.
I
I 4. 14. OR •• OR
IPRDGRAM ,OCATloN .. UNIT" CONTAINS THE UNIT OESIGNATION
I
IUNIT
I'
(01. OR UNIT 1 (2~1
UNIT.
I
Ie.
OR 20
IPRQGRAM ,OCATION .. SECTOR" CONTAINS THE SECTOR ADORESS (1 TO 32 OCTA,)
I
SECTOR. ~ liTO 32 OCTAL
I
IPROGRAM ,OCATION .. TRACK" CONTAINS THE TRACK AODR.SS (! TO 114 OCTA"
I
TRACK. I e
TO 114 OCTA,
I
IPROGRAM ,0CHloN .. AS TAT US " CONTAINS THE CONHNTS or
T~E TRANSFER REGISTER
I
IAT THE OETECTION OF AN ERROR (ERROR F,AG • 1) WHICH CORRESPONDS TO THE
I
IERROR STATUS
I
I • 0 IF SEEK [RROR. 1 IF CRC ERROR. ~ IF ~ARITY ERROR
I
ASTATUS, ISTATUS U ERROR
Figure 4-8 RX8E Write/Write Deleted Data/Read Example (Sheet 2 of 2)
(
(
(
(
4-12
(
(
259
26B
261
262
263
264
265
25B
251
252
253
254
255
256
257
258
266
267
268
269
27B
271
272
273
274
275
276
277
278
279
238
239
24B
241
242
243
244
245
246
247
248
249
228
229
23B
231
232
233
234
235
236
237
28B
281
282
283
284
285 m312 125~
B313 3255
B314 1377
B31' 3~U
11316 126B
B317 1261
113221 67U
B321 6703
B322 74U
B323 '333
11324 67U
1l32' 5274
11326 67214
11327 74112
113321 22"
11331 5314
8332 74212
11333 67U
B334 3418
B335 '321
11377 11377
Il~U
ITHE rO~LOWING IS A PROGRAMMING EXAMPLE Or PROTOCO~ REQUIRED TO
I
IEMPTY THE SECTOR BurrER or 64 12-BIT WORDS (12 BIT MODEl, o~
I
IEMPTY THE SECTOR BUrrER or 128 8-BIT BYTES (8 BIT MODE)
I
EENTRY, TAO
DCA
ESETUP, TAO
DCA
TAO
TAO
LCD
KMU
PTRy
(BUrrER-l)
Ale
MODE
COMMAND
I
IPARITY CRRO_ RETRV COUNTER
IPROGRAMS OAT. Bur'ER
IAUTO INDEX REGISTER lB
I e
I "
2
IIOT fRYS TO tMPTY THE SECTOR BUrrER tr 12-9tT, leB tr I 91T
MEANS EM.TY BU,rER
TO tssur THE COMMAND
IWAIT rOR A TRANsrER REQUEST r~AG BEroRE TAANsrERRING DATA TO THE PROGRAMS
I
IDATA BurrER FROM THE RXlll SECTOR BurrER
I
IWAIT rOR A DONE rLAG TO INDICATE THE COMPLETION 0' THE EMPTY BurrER COMMAND PRIOR TO
I
ITESTING THE ERROR rLAG
I
[LOOP, STR
SKP
JMP
SDN
EMPTY
JMP '~LOUP
ITEST rOR TR 'LAG
ITR NOT lET, TEST 'OR gONE
ITR r~AG
ITEST rOA
SET
DO~E r~AQ
INOT TA, OR OONE VET r~AG
I
ITHE DONE 'LAG IS SET
I
ITEST roR ANY [RRORS CONLY ERROR POSSIBLE IS A PARITV tRROR)
I
SER
HLT
ITEST rOA THE ERROR rLAG
INO ERAOAS • OK
I
IINCREMENT AND TES~ THE PARITV ERRoR RETRY PROGRAM LOCATio." PTRV "
I lAND RETRY THE COMMAND UNTI~ THE ERROR RECOVERS
I lOR UNTIL THE PTRY COUNTER OVERFLOWS TO 0
I lSI PTRY
JM"
HLT
EStruP IRE TRY TO EM_TY THE SECTOR BUf'ER
IHARD 'AAITY ERROR
I
ITHE TRANS'ER REQUEST rLAG IS SET
I
!TRANSFER DATA TO THE PROGRAMS DATA BurF'ER ,ROM THE RXU SECTOR Bu,rE.R
I
EMPTY, XOR
DCA I AU
JMP ELOOP
IrROM THe RX0~ SECTOR BurrER
ITO THE PROGRAMS DATA BurrER
ILOOP UNTIL THE DONE fLAG SETS
PACE
ITHE ,aLLOWING PROGRAM LOCATIONS ARE RESERVED rOR THE PROGRAMS DATA BurrER
I
BUFTER, Il
*BUFrER+200 s
Figure 4-9 RX8E Empty Buffer Example
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4-13
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174
175
176
177
178
179
180
181
191
192
193
194
195
196
197
198
199
200
182
183
184
185
186
187
188
189
190
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
0010
0266 1254
0267 3255
027~ 1377
0271 3010
0272 1260
0273 6701
0274 6703
0275 7410
0276 5306
0277 6705
0300 5274
0301 6704
0302 7402
0303 22"
0304 5270
030' 7402
0306 1410
0307 6702
0310 7200
0H1 5274
ITHE rO~~OWINQ IS A PROGRAMMING EXAMP"E OF PROToeo" REQUIRED TO
I
IFILL THE SECTOR BurrER WITH 64 12-BIT WOROS (12 BIT MODE). OR
I
IFILL THE SECTOR BUFrER WITH 128 6-BIT BYTES (8 BIT MOOE)
I
A10'10
I rENTRY. TAO KM10
DCA PTRy
SETUP. TAO (BUrrtR-1)
DCA Ali!
TAO
LCD
MoDE
1
ITESTING T~E ERROR FLAG
I
LOOP. STR
SKP
JM~
SON
JM~
I B TRYS TO riLL THE SECTOR BurrER
IPARITY £RRO~ RETRy COUNTER
IPROGRAMI DATA BurFER
IAUTa INCEX REGISTER 10
I "
IIOT
!r U·SIT. U0 IF' 8 SIT
TO ISSUE THE COMMAND
I
IWAIT FOR A TRANSFER REQUEST FLAG BErORE TRANsrERRING DATA rROM THE PROGRAMS
I
IDATA BurFER TO THE RX01 SECTOR BurFEH
I
IWAIT FOR A DONE FLAG TO INDICATE THE COMP,ETION or
THE rlL, BUFFER COMMANO PRIOR TO
ITEST roR TR FLAG
IT~ NOT SET. TEST rOR DONE "AG
ITR ,"AG SET
IT£5T rOR DONE "AG
INOT TR. OR CONE YET
1
ITHE DONE r,AG IS SET
1
ITEST rOR ANY ERRORS (ON,Y ERROR POSSIB,E IS A PARITY ERROR)
I
IT£5T rOR THE ERROR F~AG
INO ERRORS - OK
I
IINCREMENT AND TEST THE PARITY ERROR RETRY PROGRAM ,OCATloN " PTRY "
I lAND RETRY THE COMMAND UNTI" THE ERROR RECOVERS
/ lOR UNTI" THE PTRY COUNTER OVERFLOWS TO Z
1 lSI PTRy
JMP SETUP
H"T
I
ITHE TRANSrER REQUEST F"AG IS SET
IRETRY TO
IHARO
FI~"
~A~ITY
THE SECTOR BurrER
ERROR
I
ITRANSFER OATA FROM THE PROGRAMS OATA BUFrER TO THE RX01 SECTOR BU,rER
I
FILL. TAO I Al~
XDR
C"A
JHP "Oop
IVIA AUTO INDEX REGISTtR 10
ITO THE RX01 SECTOR BurFER
10,A BECAUSE lOT XOR DOESN'T
I,OOP UNTIL THE OONE r~AG SETS
Figure 4·10 Fill Buffer Example
(
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4·14
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• . .
4.6 RESTRICTIONS AND PROGRAMMING PITFALLS
A set of 11 restrictions and programming pitfalls for the RX8E is presented below.
1. When performing the following sequence of instructions, interrupts must be off.
[ ~~~
- - - - - - - - . ,
SDN
JMP
(done)
(fIll or empty buffer)
If interrupts are not off, the following sequence of events will occur. Assume interrupts are enabled and the RX8E issues an interrupt request just before the SDN instruction. The SDN instruction will be executed as the last legal instruction before the processor takes over. However, since the Done flag is cleared by the SDN instruction, the processor will not find the device that issued the interrupt.
2.
The program must issue an SER instruction to test for errors following an SDN instruction.
3. For maximum data throughput for consecutive writes or reads in 8-bit mode, interleave every three sectors; in 12-bit mode, interleave every two sectors. (This of course depends on program overhead.)
4. When issuing the lOT XDR at the end of a function to test the status, the instruction AND 377 must be given, because the most significant bits (0-3) contain part of the previous command word.
5.
If an error occurs and the program executes a Read Error Register function (111) (paragraph 4.4.7), a parity error may occur for that command. The error code coming back would not be for the original error in which the Read Error Register function was issued, but for the parity error resulting from the
Read Error Register function. Therefore, check for parity error with the Read Status function (101) before checking for errors with the Read Error Register function (111).
6. The SEL DRV RDY bit is present only at the time of the Read Status function (101) for either drive, or at completion of an Initialize for drive O.
7. It is not necessary to load the Drive Select bit into the command word when the command is Fill Buffer
(000) or Empty Buffer (001).
8. Sector Addressing: 1-26 or 1-328 (No sector 0)
Track Addressing: 0-76 or 1-1148
9. If a Read Error Register function (111) is desired, the program must perform this function before a
Read Status function (101), because the content of the Error register is always mo.dified by a Read
Status function.
10. The instructions STR, SDN, SER also clear the respective flags after testing, so that the software must store these flags if future reference to them is needed after performing one of these instructions.
11. Excessive use of the Read Status function (101) will result in drastically decreased throughput, because a
Read Status function requires between one and two diskette revolutions or about 250 ms to complete.
4-15
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Octal
Code
0010
0020
0030
0040
0050
0060
0070
0110
0120
0130
0140
0150
0160
0170
0200
0210
4.7 ERROR RECOVERY
There are two error indications given by the RX8E system. The Read Status function (paragraph 4.4,5) will assemble the current contents of the RXES (paragraph 4.3.6), which can be sampled to determine errors. The Read Error
Register function (paragraph 4.4.7) can also be used to retrieve explicit error information.
The results of the Read Status function or the Read Error Register function are in the Interface register when Done sets, indicating the completion of the function. The XDR lOT must be issued to transfer the contents of the
Interface register to the PDP-8's AC.
NOTE
A Read Status function is not necessary if the DRV RDY bit is not going to be interrogated, because the RXES is in the
Interface register at the completion of every function.
The error codes for the Read Error Register function are presented below.
Error Code Meaning
Drive 0 failed to see home on Initialize.
Drive 1 failed to see home on Initialize.
Found home when stepping out 10 tracks for INIT.
Tried to access a track greater than 77.
Home was found before desired track was reached.
Self-diagn ostic error.
Desired sector could not be found after looking at 52 headers (2 revolutions).
More than 40 ps and no SEP clock seen.
A preamble could not be found.
Preamble found but no I/O mark found within allowable time span.
CRC error on what we thought was a header.
The header track address of a good header does not compare with the desired track.
Too many tries for an IDAM (identifies header).
Data AM not found in allotted time.
CRC error on reading the sector from the disk. No code appears in the ERREG.
All parity errors.
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4-16
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C'HAPTER 5
THEORY OF OPERATION
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This chapter presents a discussion of the hardware and pCPU firmware of the RXII and RX8 Floppy Disk Systems.
This information, combined with the programming information and functional descriptions contained in Chapters 3 and 4, should give the reader a complete knowledge of the theory of operation of the RXII and RX8 Floppy Disk
Systems.
The first section of this chapter describes the overall system block diagram and the signals that interconnect each of the blocks. The second section presents a detailed block diagram and logic discussion of each of the system blocks.
The pCPU microprogram is discussed in Paragraphs 5.2.4 and 5.2.5.
5.1 OVERALL SYSTEM BLOCK DIAGRAM
The floppy disk system consists offour elements (Figure 5-1):
1. Drive mechanics, which includes actuators and transducers (up to two per controller)
2. Read/write electronics, which translates power levels between drive mechanics and control logic
3. Microprogrammed controller, which includes all control logic.
4. Bus interface, which translates between host processor bus protocol (Unibus or Omnibus) and RXOI data bus
(
DISK DRIVE
INTERFACE
READ/WRITE
ELECTRONICS
RXOI
DATA BUS
"CPU
CONTROLLER
OR o
M
N
1
B
U
S
.RXII
INTE.RFACE
U
N
I
B
U
S
CP-1520
Figure 5-1 Bus Structure
5-1
There are three levels of data transmission in the floppy disk system (Figure 5-1):
1. Unibus for PDP-II or Omnibus for PDP-8 for data transmission between bus interface and host processor
2.
RXOI data bus for data transmission between the RXOI J./CPU controller and the bus interface
_ 3. The disk drive interface for data and control information transmission between the read/write electronics and the RXOI J./CPU controller.
Signals between the read/write electronics and mechanical drive are analog signals used to control head motion and sense diskette motion and position. The sections. which follow describe the signals used in the three levels of data transmission and the analog signals between the read/write electronics and mechanical drive. '
5.1.1 Omnibus to RX8E Interface Signals
The RX8E interface communicates with the PDP-8 Omnibus via the signals shown in Figure 5-2 and described below. These signals are further explained in the PDP-8 Small Computer Handbook.
4
"-
./ l'
RX8E
INTERFACE
/
"-
(
A
A
"
DATA BUS (12)
MEMORY DATA BUS (9)
TP3 H
TP4 H
INTERNAL I/O L
SKIP L
INT RQST L
CO.C1
INIT H lIO PAUSE
0
M
N
I
B
U
S
~ ?
CP-1521
Figure 5-2 Omnibus to RX8E Interface Signals
DATA BUS - Twelve parallel bits of data are transferred along a bidirectional bus for both input and output data between the AC register in the processor and the Interface register in the RX8E interface.
MEMORY DATA BUS - This signal provides I/O transfer (lOT) instructions from memory to the RX8E interface.
1P3 H, TP4 H - These signals are used to clear the flag and clock the Interface register of the RX8E interface in transferring data along the data bus.
INTERNAL I/O L - This signal is grounded by the RX8E interface selector decoder to inhibit decoding any internal
Omnibus I/O transfer (lOT) instructions. Failure to ground this line will result in long lOT timing.
SKIP L An lOT checks the flag for a ONE state. If the flag is set, SKIP L is asserted and the address of the program counter (PC) plus one is loaded into the Central Processor Memory Address (CPMA) register to implement a skip.
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5-2
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INT RQST L - This signal is part of the interrupt structure of the Omnibus. It is the method by which the RX8E interface signals the processor that it has data to be serviced.
CO, C1 - Signals CO and C1 determine the type of transfer between the RX8E interface and the processor. These signals control the data path within the processor and determine if data is to be placed on the data bus or received from the data bus. They are also used to develop the necessary load control signals required to load either the accumulator (AC) or the program counter (PC) in the processor.
INIT H - INIT H is a signal used to clear all flags in the RX8E interface and initialize the RXOl.
I/O PAUSE L - This signal is used to gate the RX8E select and operation codes into the programmed I/O interface of the PDP-8 decoders.
5.1.2 Unibus to RX11 Interface Signals
The RX11 interface communicates with the PDP-II Unibus via the signals shown in Figure 5-3 and described below.
These signals are further explained in the PDP-11 Peripherals Handbook.
RXI1
INT ERFACE
/'
ADDRESS SIGNAL (18)
"\r
/
"-
"'I
DATA SIGNAL (16)
MSYN L
SSYN L
NPR L
CI L
INIT
INTR L
SACK L
BBSY L
BR (7:4)
BG(7:4)
~ l\..,
,/
~
/
"
U
N
I
B
U
S i"
;,
~
CP-1522
Figure 5-3 Unibus to RX11 Interface Signals
ADDRESS (A Lines) - The 18 address lines are used by the CPU to select the device register addresses of the RX11, which are 177170 (RXCS) and 177172 (RXDB).
DATA (D Lines) - The 16 parallel data lines are used to transfer information in and out of the RX11 interface.
MSYN L - This signal is the master synchronization control signal that is initiated by the RX11 when it has control of the Unibus for data transmission.
SSYN L - This signal is the slave synchronization control signal that is initiated by the RX11 in response to an
MSYN L signal from the processor or another device that has control of the Unibus and is about to send data to the
RXl1.
5-3
Co c'
NPR L This signal from the processor will inhibit the RXll interface from issuing a bus grant.
NOTE
The RXII is not an NPR device.
Cl L - This bus signal is coded by the master device to control the slave in Data In mode (passing data to the
Unibus) if it is negated and Data Out mode (passing data from the Unibus) if it is asserted.
INIT L - This is the signal asserted by the processor when the START key on the console is depressed, when a
RESET instruction is executed, or when the power fail sequence occurs. This signal will initialize the RXll system.
INTR L - This signal is asserted by the RXll when it has bus control during an interrupt sequence. It directs the processor to go to interrupt service routine.
SACK L - This signal is sent by the RXll to the processor in acknowledgment of ynibus control being transferred to it. This signal inhibits further bus grants by the processor.
BBSY L - This is the signal sent by the RXll when asserting master control of the Unibus. This signal follows the
SACK L signal.
BR (7:4) - These four priority bus request lines are used by the RXll to request bus mastership. Each device of the same priority level passes a grant signal to the next device on the line, unless it has requested bus control; in this case, the requesting device blocks the signal from the following devices and assumes bus control.
BG (7:4) - These are four priority bus grant lines corresponding to the four request lines. The processor uses them to respond to a specific bus request.
5.1.3 Interface to pCPU Controller Signals
The pCPU controller and RX8E or RXll interface communicate via the signals shown in Figure 54 and described below.
/LCPU
CONTROLLER
DATA L
DONE L
TRANSFER REQUEST L
SHIFT L
OUT L
ERROR L
RUN L
INIT L
12 BIT L
RXBE
OR
RXII
INTERFACE
(RXBE ONLY)
CP -1523
Figure 54 Interface to pCPU Controller Signals
INIT L - The RXOl will negate DONE L and move the head position mechanism of drive 1 (if it exists) to track O.
The RXOI will also read sector 1 of track 1 of drive 0 and then assert DONE L without error upon successful completion of the function.
DONE L Asserted low, DONE L indicates that there is no RXOI function in progress. Initiating any function will cause DONE L to go false for the duration of that function. Attempting to initiate any function other than Initialize while DONE L is false is illegal and may result in an error.
54
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RUN L - RUN L initiates communication between interface and controller. RUN L, asserted while DONE L is true, passes a command from interface to controller serially. DONE L will go false until the command has been executed
(or until Initialize is asserted). RUN L, asserted while DONE L is false, signals transfer of data to or from the controller. All control lines to the controller must be stable 75 ns before RUN L is asserted.
OUT L OUT L signals the direction in which the RXOI is prepared to transfer data. When OUT L is asserted, the direction of transfer is from controller to interface. When OUT L is negated, the direction is from interface to controller. OUT L is never asserted while DONE L is true, and OUT L is negated by Initialize.
TRANSFER REQUEST L (TR L) The TR L line, with RUN L and OUT L, forms a bidirectional handshake set.
On transfers from controller to interface (OUT L asserted), TR L going true indicates that the next data element has been transferred to the Interface register. The transfer of the following data element will be initiated by asserting
RUN L. This will negate TR L until the new data element has been assembled in the interface.
On transfers from interface to controller (OUT L negated), TR asserted indicates that the controller is prepared to accept the next element of data. The arrival of the new data element will be signaled by assertion of RUN L.
Assertion of RUN L while TR L is negated is an error.
DATA L DATA L is a bidirectional line for transfer of data to and from the controller. A parity bit is appended to the serial data stream by the interface when the direction of the data transfer is into the controller. The controller will interrogate the parity bit for validity.
SHIFT L The SHIFT L pulse strobes information to or from the controller bit-by-bit.
1. Interface to Controller Transfer - The transfer of either commands or data words begins with assertion of RUN L. Following the assertion of RUN L, DONE L or TR L will be negated and a number of SHIFT
L pulses will occur. The number depends on the length of the data element to be passed. The first bit of data (or command) must be stable when RUN L is asserted. The SHIFT L pulse width is 200 ns nominal.
SHIFT L pulses will not occur more often than every 400 ns. Subsequent bits of data may be brought up on the trailing edge of SHIFT L. DONE L or TR L will be reasserted following the last SHIFT L pulse.
2. Controller to Interface Transfer - The assertion of TR L indicates the controllers readiness to transfer data. Assertion of RUN L will negate TR L and initiate a train of SHIFT L pulses. The data is to be sampled on the leading edge of SHIFT L and is valid only while SHIFT L is asserted. TR L will be reasserted at the end of each element of data. DONE L will be asserted following transfer of the last element of data in a block.
12 BIT L - This signal is asserted by the interface to controller and determines the number of shift pulses generated by the controller for each byte transferred.
Signal 12 BIT L asserted will produce 12 SHIFT L pulses for data transfer between the interface and controller upon the assertion of RUN L. Signal 12 BIT L negated will produce eight SHIFT L pulses for data transfer between the interface and controller upon the assertion of RUN L. This line must remain asserted throughout the entire data transfer. When data is transferred, the most significant bit is transferred first.
NOTE
Signal 12 BIT L is only asserted by the RX8E interface for
PDP-8 12-bit words. It is
never
asserted by the RXll interface.
ERROR L - This is an error summary bit generated by the controller that sets when any error is detected
(Paragraphs 3.2.1 and 4.3.6). The detection of ERROR L stops all controller action and asserts DONE L and the
Error flag. This line is cleared by INIT L or the initiation of a new function.
5-5
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5.1.4 pCPU Controller to Read/Write Electronics Signals
The pCPU controller and read/write electronics communicate via the signals shown in Figure 5-5 and described below.
R/W
ELECTRON ICS
WRiTE GATE H
ERASE GATE H
LOW CUR H
LD HD H
WRITE DATA H
HD STEP H
HD DIR OUT H
SEL TRK 0 H
SELINDEXH
RAW DATA L
SEL 1 H
DC LO L fL
CPU
CONTROLLER
CP -1524
Figure 5-5 pCPU Controller to Read/Write Electronics Signals
LOW CUR H - This signal is asserted by the controller to select the lower of two write current levels when operating on a track above 43. As the head moves closer to the center of the disk, the bit density increases as linear velocity decreases, necessitating a reduction in write current.
WRITE DATA H This signal conveys the complete data stream to the read/write electronics at TTL logic levels.
Each transition on this line results in a flux reversal on the disk.
In general, the pattern will be one clock transition every 4 ps with an intervening transition between two successive clocks to represent a data one and no intervening transition to represent a data zero. It should be noted that the data content of this stream cannot be inferred from its instantaneous logic level, but only from the pattern of its transitions (Paragraph 1.3.2).
RA W DATA L - This signal conveys the complete data stream recovered from the diskette at TTL logic levels. It includes a regular pattern of clock transitions which the controller will separate from the data transitions. As above, the data content is in the pattern of transitions rather than the absolute level at any instant of time (paragraph
1.3.2).
SEL 1 H -This signal uniquely selects one of the two possible diskette drives. The assertion of this line will select logical drive 1 for use. Unit 0 is physically the left-hand unit in the rack.
WRITE GATE H - This signal is asserted by the controller to enable the selected write drivers. This level must be asserted prior to the beginning of the data field to be written and is negated after the last bit of the data field. This timing is completely under microprogram control.
ERASE GATE H - This signal is used in conjunction with WRITE GATE H to enable the tunnel erase drivers. It is asserted and negated after the assertion of WRITE GATE H, with timing determined by the microprogrammed controller.
LD HD H This signal is asserted by the controller to hold the media against the selected head.
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5-6
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HD STEP L - This signal is asserted twice by the controller to change head position by one track in a direction determined by signal HD DIR OUT H. The maximum step rate is 10 ms per step. Minimum pulse width is 200 ns.
HD DIR OUT H - This signal determines the direction in which the head will move in response to an HD STEP L signal. If HD DIR OUT H is unasserted, the heads will travel toward the center of the disk (IN), increasing the track address. If HD STEP L is asserted when HD DIR OUT H is asserted, the heads will travel toward the outside edge of the disk (OUT), decreasing the track address.
SEL TRK 0 H This signal is asserted by the selected drive to indicate that its head is positioned over track O.
SEL INDEX H - This signal is asserted by the selected drive to indicate that the hard index hole has been detected.
This occurs once per revolution and is used by the control to time operations and detect "up to speed." This pulse is
400 ps minimum width.
DC LO L - This signal is asserted by an Initialize signal from the controller to the drives.
5.1.5 Read/Write Electronics to Drive Signals
The read/write electronics and drive(s) communicate through five sets of signals per drive as shown in Figure 5-6 and described below. The plug designations for the cabling are also shown in Figure 5-6.
DRIVE
0
HEAD
INDEX
TRACK 00
HEA D STEP PER
HE AD lOAD SOlENO I D
P3
P6
P7
P4
P5
READ/WRITE
ELECTRON ICS
DRIVE
1
HEAD
INDEX
TRACK 00
HEAD STEPPER
HEAD lOAD SOLENOID
P3
P6
P7
P4
P5
CP-1525
Figure 5-6 Read/Write Electronics to Drive Signals
HEAD - This is an analog signal to and from the drive head.
INDEX This is a set of signals connected to a LED-phototransistor pair which locates the index hole for determination of diskette rotational position and speed.
TRACK 00 - This is a set of signals connected to a LED-phototransistor pair, which indicates positioning at track O.
HEAD STEPPER - This signalis output from the read/write electronics, which moves the head from track to track.
HEAD LOAD SOLENOID - These signals activate a solenoid to load the head onto the diskette during a read/write operation. The head is unloaded from the diskette to reduce diskette wear when not performing a read/write operation.
5-7
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5.2 DETAILED BLOCK DIAGRAM AND LOGIC DISCUSSION
This section presents a detailed block diagram and logic discussion of each of the system blocks of Paragraph 5.1 and a discussion of the pCPU instruction set and microprogram. The logic discussion makes references to the engineering drawings included in the RXll and RX8 Print Sets, which are separate docurnents.
5.2.1 RX8E Interface
Figure 5-7 presents a block diagram of the RX8E interface. The page references in the following discussion are from the RX8 Print Set, which is a separate document.
5.2.1.1 Device Select and lOT Decoder - The Device Select and lOT Decoder Logic, shown on page D2, decodes
RX8E instructions from the memory data bus and generates signals to the Interrupt Control and Skip Logic, the C line Control Logic, and the Sequence and Function Control Logic. Device selection codes are determined by the switch configuration with relation to the state of MD6, MD7, and MD8. When the correct code for the RX8E is input to the Device Select Logic on MD03 L to MD08 L and I/O PAUSE L is asserted, MD09 L to MDll L are decoded by the 7442 decoder, and signal INTERNAL I/O L is asserted on the Omnibus. I/O PAUSE L is present anytime an lOT instruction is being executed by the program. INTERNAL I/O L prevents the processor from executing other I/O transfers (lOTs) while this instruction is being executed.
The 7442 is a BCD to decimal decoder. All Os applied to inputs A, B, and C (C is MSB) will cause pin 1, which is unused, to be asserted low. An input of 001 (C is MSB) will cause signal LCD lOT L to be asserted. An input of 010
(decimal 2) will cause XFER lOT L to be asserted. Therefore, for each function code input on MD09 L to MDll L, only one of the output lines of the 7442 will be asserted. The function codes are further explained in Paragraph 4.4.
5.2.1.2 Interrupt Control and Skip Logic - The Interrupt Control Logic, shown on page D2, asserts the BUS INT
RQST L signal on the Omnibus. Bit 11 of the data bus must be set and an INTERRUPT lOT L must be decoded by the RX8E to set the Interrupt Enable flip-flop. The combination of the Interrupt Enable and Buffered Done flip-flops will assert BUS INT RQST L. Setting the Buffered Done flip-flop indicates that no RXOI function is currently in progress.
The Skip Logic implements the three lOT commands Skip on Transfer Request Flag (STR), Skip on Error Flag
(SER), and Skip on Done Flag (SDN) as described in Paragraph 4.2.
NOTE
When using these instructions, the respective flags are cleared after they are tested (paragraph 4.6).
Signal SKIP L will be asserted if any of the above instructions are decoded by the lOT decoder and the respective flag has been asserted by the RXOl.
The RX8E asserts the RX8E flags by causing a positive transition on the clock inputs of flip-flops XFER REQ, ERR, and DONE. The signal MAINT (1) L will directly set the Skip flags to allow the Skip lOTs to assert the BUS SKIP L signal when decoded by the lOT decoder.
5.2.1.3 C Line Select Logic - The C Line Select Logic (page D3) controls the direction of data flow between the processor AC and the data bus and determines whether or not the AC is cleared upon completion of the transfer.
CO L will be asserted during an LCD (Load Command) instruction when signal LCD lOT L is asserted. Assertion of
Cl L requires XFER lOT H to be asserted and either MAINT (1) L or B DONE L to be asserted or WRT H to be negated. Data transfers occur under the control of the C bits according to Table 5-1.
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Figure 5-7 RX8E Interface Block Diagram
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Output AC to data bus; AC unchanged.
Output AC to data bus; AC cleared.
Input AC ORed with peripheral data
Jam input data bus to AC.
CO
H
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H
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H
Table 5-1
C Line Transfer Control Signals
Action Required by RX8E Interface
Load data bus into buffer.
H
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L
Load data bus into buffer. Ground
co.
Gate peripheral data to data bus.
Ground Cl.
Gate peripheral data to data bus.
Ground
co
and C 1.
Action by Processor
Transfers ACto data bus. AC remains unchanged.
Transfers AC to data bus and clears AC.
AC ORed with peripheral data.
Transfers data bus to AC register.
5.2.1.4 Interface Register - The Interface register shown on page D3 is made up of three 8271 4-bit shift registers.
This register temporarily stores data during transfers from the Omnibus to the RXOI pCPU controller or during transfers from the RXOI pCPU controller to the Omnibus.
During a data transfer from the Omnibus (Fill Buffer), the 12 parallel data lines to the register are enabled by signal
RX8SEL L from the Device Select Logic. Data is parallel loaded into the register when signals ENB BUFF LOAD L and CLK BUFF L are asserted. In shifting data out of the register serially for transmiSsion to the pCPU controller,
ENB BUFF LOAD L must be negated. Signal CLK BUFF L from the Sequence and Function Control Logic clocks data out of the buffer (paragraph 5.2.1.5).
During data transfer to the Omnibus (Empty Buffer), serial data from the pCPU controller is shifted into the buffer.
ENB BUFF LOAD L must be negated while CLK BUFF L supplies the clock pulses. The parallel data is enabled from the outputs of the register when MAINT (1) H, RD H, or B DONE H is asserted, and when XFER lOT Lis asserted as decoded by the lOT decoder. Only eight bits of data will be output if signal 8/12 (0) H is low; otherwise,
12 bits will be transmitted.
5.2.1.5 Sequence and Function Control Logic - The Sequence and Function Control Logic shown on pages D2 and
D3 performs six distinct functions:
1. Controls loading and shifting of the Interface register to and from the pCPU controller.
2. Senses 8- or 12-bit mode and outputs RX 12 BIT L.
3. Senses maintenance conditions.
4. Generates INIT L signal to the pCPU controller.
5. Generates RUN L signal to the pCPU controller.
6. Generates a parity bit for the serial bit stream to the RXOl.
Interface register operation is controlled by signals ENB BUFF LOAD L and CLK BUFF L generated by the
Sequence and Function Control Logic. To assert ENB BUFF LOAD L, signal RX OUT L cannot be asserted and either RX TRANSFER REQUEST L or RX DONE L must be asserted.
5-10
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In parallel data entry to the buffer, CLK BUFF L will be asserted if any of the following conditions hold:
1. ENB BUFF LOAD L is asserted.
2. Either LCD or XDR instructions are being performed.
3. Signal BUS TP3 H is asserted.
In serial data entry to the buffer, the CLK BUFF L pulses are derived from the RX SHIFT L pulses from the pCPU controller.
The 8/12 flip-flop will set and signal 8/12 (1) H will be asserted if BUS DATA 5 L is asserted during a Load
Command (LCD) operation. Signal 8/12 (1) H is used to control whether 8 or 12 bits of data are transferred to or from the Omnibus and whether 8 or 12 bits of data are transferred between the RX8E and the pCPU controller.
The MAINT flip-flop will set, and signal MAINT (1) H will be asserted if BUS DATA 4 L is asserted during a LCD operation. Signal MAINT (1) H is used to allow parallel writing and reading of the Interface register from the
Omnibus. It is also used to assert signal RUN L and C Line Control signals.
An Initialize signal to the pCPU controller (RX INIT L) is generated either by a BUS INIT H signal from the
Omnibus or an INIT lOT L decoded from the lOT decoder.
The RUN L signal, which is used to initiate communication between the interface and pCPU controller, is asserted by setting the Run flip-flop. This flip-flop is clocked either in Command Transfer mode when LCD lOT H is asserted or Data Transfer mode to or from the pCPU controller when XFER lOT H is asserted. (RUN L cannot be asserted if
DONE L is asserted.) RX BUSY Land INIT L must both be highfor a RUN L signal to be asserted. Assertion of either RX BUSY L or INIT L will clear the Run flip-flop.
5.2.2 RXll Interface
A block diagram of the RX11 interface is shown in Figure 5-8. In the following discussion, it is assumed that the reader is familiar with Unibus operations as described in the PDP-ll Peripherals and Interfacing Handbook. Page references are to the RX11 Print Set, which is a separate document.
5.2.2.1 Address Decoder - The address decoder determines whether its associatt:d RX11 is being addressed and whether control information or data is being transferred.
The hardware on page 02 is a combinational logic network that decodes two discrete addresses assigned to the
RX11. Address bits (17:13) must always be asserted to satisfy the decoder. The state of address bits A (12:03) is determined by the placement of jumpers A12 through A3 on the board. For each of these bits, one 8242 exclusive-NOR gate is used. Insertion of a jumper for a particular bit position stores a 0 on one leg of the 8242, so that a 1 appearing on the other leg causes the output to go low. This is a mismatch condition which is met when the associated address bit is a 1. When both legs match (1s or Os on both), the output is high. The output of these 12 gates are wire-ORed and applied to pin 9 of the 7400 NAND gate. Pin 10 of this gate receives the NANDed signal of
A (17: 13) and BUS MSYN. Pin 8, the output of this gate, is signal REG SELECT L and is asserted when the proper
Unibus addresses are decoded.
The states of ~ddress bits A02 and A01 and REG SELECT L are used to produce signals D2 SELECT 00 H or D2
SELECT 02 H. The state of A01 determines which of the mutually exclusive signals, D2 SELECT 00 H or D2
SELECT 02 H, is generated. If BUS A01 L is asserted, D2 SELECT 02 H is asserted. If BUS A01 L is negated, D2
SELECT 00 H is asserted. These signals, in turn, allow access to the RXCS register as in the case of D2 SELECT 00
H asserted, or to the RXDB register as in the case of D2 SELECT 02 H asserted. (Refer to Paragraph 3.2 for register descriptions. )
5-11
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5.2.2.2 Data Path Selection - Data Path Selection Logic is shown on pages D2 and D3. Signal BUS C1 L from the
Unibus controls whether Data Out or Data In operation is to be executed. Assertion of BUS C 1 L indicates Data Out
(from Unibus), and negation of BUS C 1 L indicates Data In (to Unibus). Signals D2 OUT H and its complement D2
IN H from page D2 are derived from BUS C 1 L and are input to the rest of the Data Path Selection Logic on page
D3. With BUS Cl L negated and D2 SELECT 02 H asserted, all eight bits from the data buffer are enabled through the 8838 bus transceivers. With BUS C1 L negated and D2 SELECT 00 H asserted, only lines BUS D04 through BUS
D07, providing control and status information (RXCS), are enabled. With BUS C1 L asserted, none of the 8838s are enabled, and data is being input from the Unibus on lines BUS DOO through BUS. D07.
The 74157 multiplexer controls passage of status and control information (RXCS) in the form of signals D3 DONE
H, D3 INT ENB (1) H, and D3 TRANSFER REQUEST H from the Sequence and Function Control Logic or passage of data from the Read/Write Data Buffer register (RXDB). If D2 SELECT 02 H is asserted, then data is output from the 74157. If D2 SELECT 02 H is negated, then control information (RXCS) is output from the 74157.
5.2.2.3 Interface Register - The Interface register is a 74199 eight-bit, parallel load, shift register shown on page
D3. Data transfer through the register can take place from the Unibus to the pCPU controller or from the pCPU controller to the Unibus.
In data transfer to the RXII from the Unibus, parallel data is loaded into the register when D3 RX BUSY H is negated and D3 LOAD H is asserted. Data is serially shifted in the register from QA to QH by the D3 B SHIFT H signal derived from the pCPU controller when D3 RX BUSY H is asserted. Serial data is shifted to the Sequence and
Function Control Logic, which transmits data to the pCPU controller (paragraph 5.2.2.4).
Data is assembled in a serial fashion for parallel transfer on the Unibus. Serial data is input at D3 B SER DATA H and shifted by D3 B SHIFT H when D3 RX BUSY H is asserted and D3 LOAD H is negated. The eight bits of parallel data appearing at the output of the buffer are input to the Data Path Selection Logic for transmission to the
Unibus.
5.2.2.4 Sequence and Function Control Logic - The Sequence and Function Control Logic schematics are shown on page D3 and in the lower left-hand corner of page D2. This portion of the RXll interface provides key signals to control the Interface register and the Interrupt Control Logic as shown in Figure 5-8. Operation of this circuitry is controlled by signals from the pCPU controller and D2 SELECT 00 H and D2 SELECT 02 H from the address decoder.
Signals RX TRANSFER REQUEST L, RX OUT L, RX DONE L, and RX RUN L control data transfer between the interface and the pCPU controller. The RX RUN L signal from the RX11 interface initiates communication between the EXl1 interface and the pCPU controller. The Run flip-flop is set in passing either a command from interface to controller or data between interface and controller. Run asserted while Done is true passes a command from interface to controller. Run asserted while Done is false signals transfer of data to or from the controller.
Once a particular function has been decoded by the pCPU controller, it requests a data transfer by assertion of RX
TRANSFER REQUEST L. The access of the RXDB in the RXII interface sets the Run flip-flop and thereby asserts
RX RUN L. The Run flip-flop is cleared either by assertion of D2 B INIT H or RX BUSY H. RX BUSY H is asserted when both RX TRANSFER REQUEST L and RX DONE L are negated. Assertion of RX BUSY H also allows the
Interface register to shift serially in communicating between pCPU controller and interface.
RX OUT L from the pCPU controller determines in which direction the data transfer is about to take place. When
RX OUT L is asserted, the direction of data transfer is from controller to interface. When RX OUT L is negated, the direction of data transfer is from interface to controller.
On transfers from controller to interface, assertion of RX TRANSFER REQUEST L indicates that the next data element has been assembled in the RXDB. Transfer of the next data element is initiated by RX RUN L. On transfers from interface to controller, assertion of RX TRANSFER REQUEST L indicates that the controller is prepared to accept the next element of data. Arrival of the next data element will be signaled by assertion of RX RUN L.
5-13
The three signals D3 DONE H, D3 INT ENB (1) H, and D3 TRANSFER REQUEST H from the Sequence and
Function Control Logic to the Data Path Selection Logic represent the three bits that may be read in the Control and Status (RXCS) register. A functional programming description of this register is given in Paragraph 3.3.
During serial data transfer from the RXDB, a 8281 binary counter and a 74HI06 JK flip·flop are used to count eight bits of data and to append the parity bit to the data element.
An error indication from the pCPU controller results in assertion of RX ERROR L. This indication is passed to the
Unibus when a read from the RXCS to the Unibus is performed. When this occurs, signal BUS DIS L is asserted.
5.2.2.5 Interrupt Control Logic - The Interrupt Control Logic, shown on page D2, is a combinational logic network that receives and generates the control signals required for the RXll to become bus master. With signals D3
DONE Hand D3 INT ENB H both asserted, D2 BUS REQUEST L will be generated if the SACK and BBSY flip·flops are not set. The D2 BUS REQUEST L signal is routed to the appropriate bus request line (normally BR5) through the priority plug shown on page D3. Etch on the plug selects both request and grant lines. When the bus grant signal is generated by the processor, it is routed via the priority plug and becomes signal D3 BG IN H. This signal clocks the GRANT flip·flop and the SACK flip·flop. The SACK flip·flop is set because the RXll had requested bus mastership. The SACK flip·flop is cleared and the BBSY flip·flop set when BUS BBSY L, BUS SSYN
L, and D3 BG IN H are negated on the Unibus. Thus the BUS BBSY L signal will be asserted again by the RXll, which is now bus master. The BBSY signal is inverted and applied to the vector address generator, generating the
BUS INTR L signal and the vector address of 264.
5.2.2.6 Vector Address Generator - The vector address generator, shown on page D2, consists of eight bus drivers that are used to generate a vector address and the BUS INTR L signals. When BUS BBSY L is asserted by the RXll, the inputs to the bus drivers are active. Seven drivers are connected to the Unibus data lines D (08:02) via jumpers.
The placement of these jumpers determines the vector address.
5.2.3 Microprogrammed Controller (pCPU) Hardware - A block diagram of the pCPU controller is shown in Figure
5·9. The controller is a hardware microprocessor controlled by a ROM with 1536 eight·bit words; the ROM contains the microprogram. This section discusses the various parts of the hardware while Paragraph 5.2.5 discusses the microprogram.
5.2.3.1 Control ROM and Memory Buffer The heart of the controller is the ROM, which contains the microprogram shown on page D6. All control and processing activities executed by the RXOI are controlled by the microcode sequences stored within the ROM. The ROM is divided into six fields, each with a storage capacity of 256 eight·bit words. Sequencing through the ROM microcode is accomplished by updating the contents of the program counter (PC) every 200 ns. The eight bits from the PC indicate the address of the next instruction to be executed.
The eight·bit instruction addressed by the PC is loaded into the memory buffer on assertion of LD MB + CLK PC L.
Each instruction consists of three fields that are sampled by the pCPU logic circuits to allow processing action appropriate to the instruction to be taken. The three fields can be defined as follows:
07
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04 01 00 06 05 03 02
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5.2.3.4 Do Pulse Generator - Detection of a Do instruction by the instruction decoder and assertion of signal TP3
L will enable the Do pulse generator (page D5), which is a 74154 decoder. The function select bits determine which of the outputs is asserted. All outputs supply clocking to various flip-flops, counters, and shift registers, depending on the function select bits. If the select field is 0000, signal CLK lOB 0 is asserted; if the select'field is 0001, signal
CLK lOB 1 is asserted; etc.
5.2.3.5 Branch Condition Selector and Control - The 74150 branch condition selector (page D8) is always enabled during a Branch instruction. The function select field determines which data line is selected for input to the Branch
Control Logic. The output signals from the Branch Control Logic, PC LOAD EN L and LD MB + CLK PC L, are used to either increment the program counter or load in a new address. LD MB
+
CLK PC L is also used to load the memory buffer.
The C1 bit, which the firmware has converted to data, is compared with the output of the branch condition selector.
If the conditions match, the PC LOAD EN Land LD MB + CLK PC L signals are enabled; The WBR CLK CNTR L signal is asserted when a WBRinstruction is decoded by the instruction decoder.
5.2.3.6 Scratch Pad Address Register and Scratch Pad - During execution of an Open Scratch Pad instruction, the function select field contains an address in the Scratch Pad. The four-bit function select field is input to the Scratch
Pad Address register (page D3), which consists of four D-type flip-flops. The function select field appears at the output of this register upon assertion of the CLK SP ADDR REG L signal generated by the instruction decoder.
The Scratch Pad (page D3) itself consists of two 7489s (64-bit read/write memory), capable of storing 16 eight-bit words. Data from the shift register is written into the address indicated by the Scratch Pad Address register when LD
SCRATCH PAD L. is asserted. Reading occurs when this signal is negated. Data read out is input to the Counter
Input Selector Logic.
5.2.3.7 Counter Input Selector, Counter, and Shift Register - The counter input selector, counter, and shift register (page D3) act as buffering circuitry for information flow in and out of the Scratch Pad. Signals CO and CI control operation of this logic.
The counter input selector consists of two 8266 multiplexers that select eight parallel bits from either the ROM or the Scratch Pad, depending on the state of CO(1) H. If CO(1) H is asserted, the Scratch Pad datais selected; ifCO(1)
H is negated, the ROM data is selected. The state of CO is determined by the low order bit of the instruction code from the memory buffer .
The outputs of the counter input selector are presented to both the program counter and the counter. During execution of a Jump instruction and Branch instruction when the branch conditions are met, a new address is loaded
,into the program counter. The control field of the instruction will determine the source of the new address. If the source is the ROM, the address is in the location following the instruction. If the source is the Scratch Pad, some previous calculation was performed to determine the new address.
The counter is made up of two 74161 synchronous four-bit counters. The output of the counter input selector 'is loaded in the counter if signal C1(1) H is negated. If CI(1) H is asserted,the counter increments upon detection of signal CLK CNTR L. During execution of a DO instruction, the Do pulse generator supplies the clocking signal if the select field is correct. An overflow condition, indicated by all Is in the counter, is detected by assertion of signal
CNTR OVFLW H, which is input to the branch condition selector.
Data output from the Scratch Pad counter is loaded into the shift regsiter if CO(1) L is asserted and C1(1) H is negated. Data appears at the outputs after the positive transition of the clock input CLK SR L. When CO(1) Land
CI(1) H are asserted, data from the data separator is serially shifted into the shift register by signal CLK SR L.
Therefore, input to the Scratch Pad is either by way of serial data from the data separator or parallel data from the counter. The data from the data separator originates from the read/write electronics during access from the diskette.
SRMSB, the MSB of the shift register, is exclusive-ORed with data [SEP DATA (1) L] and a missing clock indication
[MIS CLK (1) L] from the data separator for input to the branch condition selector. SRMSB (1) H alone is also presented to the branch condition selector.
5-17
Bits can be shifted into the shift register via CLK SR L, CO, and Cl. Signal SR LOAD H is asserted when CO(1) L is asserted and C1(1) H is negated, allowing the shift register to be parallel loaded from the counter. With CO(1) Hand
C1(1) H both asserted, SEP DATA from the data synchronizer and separator is serially input to the shift register. If
CO(1) L is negated, Is and Os from the C1(1) H bit stream are loaded into the shift register. In summary, CO determines shift or load of the shift register; C1 and SEP DATA are two serial bit streams.
Cl CO
0 0 Shift Zero
0 1 Load Shift Register
1 0 Shift One
1 1 Shift SEP DATA
5.2.3.8 J./CPU Timing Generator - The J./CPU timing generator, shown on page D7; produces signals 1P3 and 1P4, which are used as timing signals for the rest of the J./CPU controller. The 74H74 flip-flops are used as a wraparound shift register to derive 1P3 and 1P4 from the 20 MHz oscillator. 1P3 and 1P4 are 5 MHz signals with a pulse width of 50 ns. In normal operation, a recirculating 1 bit in this shift register causes TP3 to occur before 1P4. Inputs to the maintenance module connector and signal INIT + PC L control operation of this shift register.
5.2.3.9 Sector Buffer and Address Register - The 2102 sector buffer, which is a 1024-bit MOS RAM, and the address register, composed of three 74161 synchronous four-bit counters, is shown on page D4. The address register is used as a loop counter for the microprogram as well as an address register for the sector buffer. The ten LSB inputs to the register are grounded, and the upper two MSB inputs are connected to signal CO(1) L.
When used as a loop counter or an address register, C1(l) H is negated and the ten LSB bits of the register are zero.
With C1(l) H asserted, the count is incremented by signal CLK BAR L, which occurs once per disk data bit. If CO(1)
L is asserted, the two MSB bits are also zero-, enabling the counter to count 4096 clocks before the SEC BUF
OVFLW H signal is asserted. If CO(1) L is negated, the two MSB bits are one, enabling the counter to count only
1024 clocks before the SEC BUF OVFLW H signal is asserted.
Reading or writing is controlled by a flip-flop. If CO(1) H is asserted and CLK SEC BUF L is asserted, the write enable line to the 2102 is asserted by setting the flip-flop. The CLK SEC BUF L signal is asserted twice per bit, once to set the flip-flop and -once again to clear it. It is cleared when CO(1) H is negated and the second CLK SEC BUF L pulse is asserted. Data to be written in the sector buffer is contained in signal SEP DATA (1) L from the read/write electronics while reading from the diskette; the data is contained in signal DATA I L from the interface while writing on the diskette. '
In reading data out of the sector buffer, the write enable line is negated, and the serial data stream appears at SEC
BUF OUT (1) H as the Buffer Address register is incremented.
5.2.3.10 CRC Generator and Checker - Each sector has a two-byte CRC character for the header field and another two-byte CRC character for the data field (Figure 1-11). The CRC generator and checker shown on page D7 produces the CRC character to be written on the diskette and checks the CRC character read from the diskette. A
16-bit shift register with properly placed exclusive-OR gates implements the polynomial divide algorithm. The CLK
CRC L signal clocks the shift register so that the entire header field or data field is divided by a selected CRC divisor which is 215 + 212 + 25 + 1. The mathematical expression for this operation is: ao2n + ... +a
3
2 3 + a222 + a121 + ao2°
215 + 212 + 25 + 1 where a = coefficient of the bit position n
=
number of bit positions in the data block
5-18
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( fu writing data on the diskette, each bit is shifted through the CRC generator. This data stream appears on signal
C1(1) L and is produced by the firmware. Signal CO(1) L negated will enable this data stream to the CRC register.
Mter the data field has been written, the CRC register contains the remainder of the division, which is the two-byte
CRC character that is written after the data field.
During a read operation, the data stream from the data synchronizer and separator, SEP DATA (1) L, is enabled to the CRC register. This data stream is manipulated in the same way as in the write operation. When the CRC character on the diskette is encountered, it is shifted into the CRC generator as if it is part of the data stream. If all the data and CRC bits that were previously written on the diskette are retrieved, the CRC register, which contains the remainder of the division, should be zero. The contents of this register are input to the condition selector, where the firmware checks to see that the register contents are all zero.
5.2.3.11 Data Synchronizer and Separator - The data synchronizer and separator (page 04) separates clocking information from data, identifies missing clocks, and synchronizes the clock to the data. Clocking and data are mixed in the output data stream (paragraph l.3.2). In the read/write electronics, one-shots set to produce 200 ns pulses for each transition convert the flux reversal signals to a series of pulses as shown in Figure 5-10. The clock pulses can be separated from the 1 data pulses as shown. If no data pulse occurs between two clock pulses, a 0 bit is indicated. Notice that there is a clock pulse every 4 /-IS.
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FLUX
REVERSAL
STREAM
RAW DATA
I I I c 0 C I C
I I I
I I
I I I
O C I C I C O C I C
I o
C 0
SEP CLOCK
I
~~---L~--4-~~se-c--~--~--~~~~--~---L---
SEP DATA
MIS ClK
CP-15~9
Figure 5-10 Data and Clock Separation
The data synchronizer and separator produces three outputs: separated clock (SEP CLK), separated data (SEP
DATA), and missing clock (MIS CLK). SEP DATA is one bit position delayed from the flux reversal stream. In the example shown in Figure 5-10, there are no missing clock indications because the RAW DATA stream does have a clock pulse every 4 /-IS. The MIS CLK indication is used in locating the ID address mark of the sector header field and the data or deleted data mark of the sector data field. (See Figure 1-9.) Each of these data marks is a unique sequence of data and missing clocks that the microprogram identifies by examining the data synchronizer and separator circuit.
Figure 5-11 is the ID address mark which contains missing clocks. Since clocks must occur every 4/-1s, the missing clocks can be identified· as C. SEP CLK output will include clock pulses that are separated by 6 /-IS and will be out of synchronization with the real clock pulses. SEP DATA will indicate a 1 bit when a data pulse exists between SEP
CLK pulses; it will indicate a 0 where there is no data pulse. As in the first case, SEP DATA is delayed by one clock period. MIS CLK is also delayed by one clock period and occurs when SEP CLK pulses occur more than 5 /-IS apart.
5-19
(
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...
.;.-
.... "'
...
"",\ .'~"'''''. -~~,,,_~,n'~'~_"~_"_"""'~'"_'''M'''''''''~''".rl
Mis t't:K
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The
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~§
tlatl\syllenranlZ'er lruffi a
a~i l'ill.~e,.
IlhM Ween 'mV>i'iteid OOWfi
t~,
m't\tCiti'3Il%-.
~n,&FtYonize
"Th'e
€iK
~
vMia if it OO'euts after tW\:) tWe 'data ru tile
~iO
MHz 'Cl'0d{,.tiIe.§EP r>ATAout:pUt t:I:'elaYe'd
b~
oite
'8j~P
ctK ehlckpeffe'iiappear8 at tll'e !0ufp\i\; '6t tB.'e
twOaue~d
tie
m~
:ENf~
t,nH
si%n~
aNd
~leik
WINe with
.
~3~
separator pUi§e) it
% t
MIS
BW31I. is p1lir%
&7~1~3
'counters, Whfeh are p?e%'et to a g'iven 'ComH ahd 'crocked hy tire
~o
MHz
~lb'ck
after
Ie
11 signal from
reik
¥ m'e
1.4Hloo.ni.·~·~n~p)
us'es tWb
'data is
lli~
3118 timet pfoauit:ed wlleh the :5 willen i tS hit IiH
MH:z;1We tiffifug wifrcl'ow* a MrS
ebK~
nre logic is Shown on page Di1L The timing
Wih~ows
Me etrry
eretre~
occurs
br ii
clell:f:S
~s
tosepafute data from
b~tween
3 ahd 5
'Of these 'counters is
ps Hilma \Talld used to daeks. If clear tlte714Hl'D3 flip"flbp; Tli'e a cl'ocK
fiip~fleps
puis'e occUrs two pulse;
it
withhi istlte
Mitt
to p.fovide timing follow1ng 1'48748 tmer issues!! 'carry tbci:ear tire 74H st1tteof the;3
{us tffii'eh
'The foiloWing
i
03,SEP
fiip~ftop
elK
is s¥htftronlzes
~,.l3~
U Ou¥pu\ €i\ICult ::::.
'OO.lput~uffer,i1WerFae'e
"The uUtput 'circuit %il'Own b'iipage D5 eons'ists oftftelnteifaeet/tlrive
OUtput
oUffer; ar-i"e bus'tlH'Veit\ 'ar-skbus gating) 11:£1(1 iWdex sfITchrt>niZeh signals 'eLk rOSG to -ctlK rom! from
Wte ltd
pul~
JgeWeWtftor
1ilJ:ie
u~'(\
'00
te¥O'ck tlti(; :fi-ipJtl'Ol's
in
tlre futerta'eel/'drive outpUt bUffer-. The
ili"tetfad~
bus 'drivers
%\\I(\m'e aiYi
.,U~
ga'timg
meuu~ul
t()
'sYgital%
%Te
'outputs t\¥e
initerr~e
i(o We m'Sfemi()Yei. m
<A
t'6
~re
lire turt'wer appropnafe i'e'Il'<WVVRte
'cOO1binatYons 'Of
'ei~ewoniC's.
'e){pla:nati'On
~gnai:s
from tile ihterfuce,rtinve output bUffer
{OBiQ :selects tfte 'Output bus
'Oftlre'S'e sign'M's is
.giiV'e:fl
fo in Paragrapb.sS·. which the ri}st of the JGB
L3 m'rdSJ..4.
'that
'fit~ ~ve
'output WuWef
IcYonsi'Sl~
DRv Wit
~2\fA" ~RV
'oT lli:re'e
Rip:.-ftbp~~
if Uti,;
UNn\
:iili.'ii
HD. LB, Wnicll r€StyeetN'ely ptO'duee
'sigwaIs
;s,Eli fl, i1Wcl. DRV' B0t19" '(6 t11'e fea'd/wTiteei'i:'ct'r'6nles.
'The
f'liaex i~1tTUni[C'S·.
We
'S¥fielwonmf 'Conm.;sifs
'me
!ftip'~ifr6ipS
%S'k'ettea bytrl1e i1re re\e:are:a
ff¥Sft
'or
fwo ltlip_i frops use'd an'(\BYN INDEX
~o~¥ichr0nize
,(i)
'W3after m'e 'sEL \NoB""
H is negated
'a:s'Seft10n
tIre by
:SEt INDEX H the
~bo ptli~~
~slgn:ai
from·
!geneftihW·. :SYN
'aTl'di'rlput to the b.fan<eh 'conditi'on tlte l'ead!Jwrlte iNOO,x
'seteef0f.. n)
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'J>
5 .. 2.4 MitiroprQ,gram Ins~ru:cijoo Rep,er(oire - The firmware within the ~Ql Rea4~-~\y Metnory (l~P¥) ~l'~Q,ys five 4iffer~ot i,nstruction types to i1;nplement the various con~rol s,eq\1~n.~~ u,sec;l, to pxoceS.s e!ich funct~oo c91;\e,.
Regardless of type, an instruction is made up of eigllt b:~s lWd con.tains tl11;:ee fielqs. as, l;leI9W:
[
0,7 o~
I . r'
Q5 0,4
I r
SELECT fIEl.~
03,
INSTRUCTION
COj)E
FIELO
02 Q\
,
'
C,ONTROL
Fi~i..D
CP-l!!t2,
The RXOI J.!CPU controller distinguishes l;letween the different instruction. types 1:>,y the qontent of 11\e code field. The select field is used to <iefme subfunctions of a
~ng1.1;l instruct.oo
'tyPtl~
Th:is.
fie\"
inst~ction. i~, ~s9 1.l~.e~ foX addressing locations in fu,e I-/CPU Scratch Pad memory. The control fi
e
14 ~lows for 8tm f\1rt1wr
4 e
fin.Won of
the
instmction purpose and, in One case, ~erves to. distinguish between WO instructions having the swne instmction
6.e14
c04e. The five l:!asiy inst:rllctions exec:utable by the J.!CfU controller are: '
1. DO instruction
2. Conditional Branch
3, Wait Branch
4.
Open Scratch Pad
5.
Jump
5.2,4.1 DO Instruction - The most frequently executed I-/CPU fiimware instrucqQn j~ $(;1 fOrmat is:
PO
instrqctiQn. Its
07 o~
I NSTR!)t:;TlON
COD~
FIELD
05 Q4
I
SELECT
FIELD
0,3 O? 01 go
CQNTROL
~I~LO
Through use of different fUfl(ltiop ~elect codes, the lin~s going to both th\l interface to/from the interface for the Empty/fill Buffer function !/.n4 writjng 4ata bits ontq the cfi~ function. Furtlte:rmore, the l!1l<l
DO instruc:tipn i~ u~e4 to lllIsert/pegate qliQ1Y of the in~¢fface the read/write ell:!ctrop.ics, !hI:!
PO
fn~t!'Uctipn i~ msp u§ep in
fqr
$ifting 4ata
14e
DO instruction is USI:!<l for function
~coding, pllrity checking, wti~
PRe
bit~
$ectQf fie~1i generation/detection, and numerous h()usel<eepirig functiqns inhegmt ip. the varipll~
fl{Jp1J
cOntroller Se!llleIlCe~.
It.
complete breakdown of all DO instruction supfllnctions is given in the RX~/~ll Prillt ~ets,
5.2.4.2 Conditional Branch - The Conditional Branch instruction is used to sample status conditions within the
RXOI. On detection of a given condition, a branch to another area of the ROM occurs. The format of the
Conditional Branch instruction is given below:
07 06 05 04 03 02 01 00
INSTRUCTION CODE
FIELD
BEl NG SAMPLED
~'
0- BRANCH ADDRESS
TAKEN FROM ROM
1 BRANCH ADDRESS
TAKEN FROM OPEN
SCRATCH PAD
0BRANCH WHEN
CONDITION IS FALSE
1 BRANCH WHEN
CONDITION IS TRUE
CP-1534
Many conditions are sampled by the Conditional Branch instruction; examples are 12-bit mode, drive ready, read/write head located at track zero, and two index pulses have occurred. A complete breakdown of all Conditional
Branch subfunctions is given in the RX8/RXll Print Sets.
5.2.4.3 Wait Branch - The Wait Branch instruction is similar to the Conditional Branch instruction; the difference is that the Wait Branch instruction is used to stall pCPU controller operations until a given condition becomes true.
The format of the Wait Branch instruction is given below:
07 06 05 04 03 02 01 00
INSTRUCTION CODE
FIELD
~\
DEFINES CONDITION
BEING SAMPLED
0BRANCH ADDRESS
TAKEN FROM ROM
1 BRANCH ADDRESS
TAKEN FROM OPEN
SCRATCH PAD
0BRANCH WHEN
CONDITION IS FALSE
1 BRANCH WHEN
CONDITION IS TRUE
CP-1535
A breakdown of all Wait Branch subfunctions is given in the RX8/RXll Print Sets.
5.2.4.4 Open Scratch Pad - TIle Open Scratch Pad instruction is used to address (select) any of 16 locations in the pCPU controller prior to executing a read/write operation. The format of the Open Scratch Pad instruction is given below:
07 06 05 .04 03 02 01 00
(
(
(-
(
MUST
BE
ZERO
CP-1536 (
5-22
FILL BUFR
SHIFlj SR, INSERT 0
TWICE [CLEAR SRI
(CNTR) + 1 - TEMPA
[lNCR BYTE CN.TI o
BIT MODE
INCREMENT SEC
BUFR ADDR
(CNTR) + 1 ~
DPENEDSP
[INCREMENT
BYTE CDUNTI
CNTR ==OVFLW
CNTR '" DVFLW
I
INn1IALlZE SEC
BUI;! ADDR TO 0
INCREMENT SEC
BUF ADDR FOR
12 BIT MODE
SELECT SECTOR
BUFFER AS
DATASQURCE
DATA DIR = IN
CNTR '" OVFL
CNTR =OVFLW
CNTR -OVFL
CNTR,* OVFLW
CNTR "" OVFLW
CNTR =OVFLW
RUN =T RUN= F
12 BIT MODE OBIT MODE
DATA DIR = OUT
~
DATA DIR = IN
NOTES,
All numerals are decimal unless subscripted.
LEGEND
I I
INDICATES CALL
TO SUBROUTINE t )
( )
BEGINNING OF
A SUBROUTINE
BRANCH TO OR
BEGINNING OF
A ROUTINE l
ACTIONS
CP·1545
Figure 5-13 Empty and Fill Buffer Functions Flowchart
5-25
READ
NOTES:
All numerals are decimal unless subscripted.
LEGEND
I
C )
( )
I
INDICATES CAll
TO SUBROUTINE
BEGINNING OF
A SUBROUTINE
BRANCH TO OR
BEGINNING OF
A ROUTINE
ACTIONS
BUFFR ADDRESS
SEP ClK' F
SEP elK = T
WAIT 96p.s
[TO PASS WRITE
TURN ON SPLASH
AREA[
SEC BUF ADDR
'*
OVFLW SEC BUF ADDR - OVFlW
SEP elK = F SEPClK -T
CNTR
'*
OVFLW
OPEN TEMP D
[FOR SOFT UNIT
SElECTI
END AROUND
SHIFT OF DRV
ROY BIT
FLAG -ZERO
SHIFT SR, INSERT 1
[SET DEL DATA
BITI
O-CNTR
[UNIT 1 SDFT
UNIT SEL BITI FLAG - ONE
SHIFT SR, INSERT 0
[ClR DEL DATA
BITI
FLAG - 0 FLAG - 1
END AROUND
SHIFT OF NEXT
5SR BITS
-16-CNTR
[BIT COUNT FOR
CRC CHECKI
CRC 16- 0
0- CRe
[BRING UP NEXT
CRC BITI
(CNTR)
+
CNTR
[INCREMENT BIT
COUNTI
CNTR '" OVFlW CNTR - OVFlW
SHIFTSR,INSERTO
[ClR CRC ERROR
BITOF STATI
(SR) OPENED SP
[RESTORE STATI
200&
-+
CNTR
[ERROR CODE FOR
DATA CRC ERRORI
(CNTR) SP
[STORE SOFT UNIT
SEL BITI
SHIFT OF 5
BITS IN SR
SHIFTSR,INSERTO
[CLR INIT DONE
BITI
END AROUND
SHIFT OF lAST TWO
STAT BITS IN SR
(SR) OPENED SP
[RESTORE STATI
CP·1647
Figure 5-14 Read Sector and Read Status Functions Flowchart
5-26
~"
,~
.\
( \
,/"""\ .~
.1'
-
.~.
VI
W
-...J
TO
DRIVES
DKO
OK'
DKO
DKI
DKO HEAD
...
<
DK1 HEAD
~
,(
~
DKO
INDEX
SENSOR
IDKO INDX H
J
DK1
INDEX
SENSOR
I
I DK1 INDX H
DKO
TRACK
SENSOR
I
DKO TRK 0 H
I
OK 1
TRACK
SENSOR lDK1 TRK 0 H
J
......
I I
74157
DATA
SELECTOR
DKO
HEAD LOAD
DK1
HEAD LOAD
DKO
...
<
"
~
STEPPER
~ <
DK1
STEPPER
"
A <
"
SEL TRK 0 H
SEL INDX H
SEL OK 0 H
HEAD WRITE
CURRENT
AMPLIFIERS ~
HEAD READ
CURRENT
AMPLIFIERS
HEAD
LOAD
CONTROL
SEL OK 1 H
INIT L
LOAD HEAD H
STEPPER
MOTOR
CONTROL
AND
DRIVERS
SELDK1H
INIT L
SEL DKO H
DC LO L
STEP L
OUT H
Figure 5-22 Read/Write Electronics Block Diagram
ABOVE TK 43H
WT GATE H
ERASE H
WT DATA H
DC LO L
HEAD WRITE
CONTROL
SEL OK 0 H
.A PEAK
DETECTOR
TO jOCPU
CONTROL
SEL OK 1 H
RAW DATAL
CP-1692 qJ
S.2.7
Mechanical Drive
The mechanical drive consists of four major parts:
1. Drive mechanism
2. Spindle mechanism
3. Positidning mechanism
4. Head load mechanism
The 'corirplete mechatiical structurebf the drive is shown in Figure 5-23, and each section is described in the fdUowingparagfaphs.
(
(
DISK
HE'ADLOAD
ACTUATOR
RE~D/WRITE
HEAD
HEAD
"CARRIAGE
HELIX
STEPPER
MOr,OR
(
( iOiSK
"'DRIYE
,'MiOT,OR
CP-H3B
FigUre 5-23 Disk Drive Mechanical System
(
( j,~,7,J ,Qr~v~ M~gh,!Jnj!!m
"" Th@
~ftY~ sY~!~I1}~m\1!4~§ r(;)mtt@n~4!,§~(i)H@ me¥.@ffi@fl! Y§m~ ll§W~~;~hi!~ m9!RI
~WgtIH;l ~g m~tgn with-~I). ~ ~~pgml~ prima!'Y INwer gf
tll-«::
gg1}!mll-~r gf pfitr1mpp)V@r1!p,pU~1!t~pn·
§¥s,!em
.
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,..
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,§eJy§
A~g~lin~ fM1 !§ ffl9Wlt~4
9fl Pfl@
~p.g
J?11Il~r §9M~§Wg !g
!4!l
~tbpr!!lfll~ ,gf
pf
tP!:l
4py~
meter
m~f!:
Be!!!H9l}
·@f
tb,@t~Jf@He j~
!h!:
?fffi'},!i.\C?! JJ¥
mgtgr~!l:ft: 'fAAggy~ pw!~r ~m! ~@H ~·f~ ~E}h~€1!,~ ~9f !!~f
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b~!t er
9Q
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~9sjti9n, th~
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GP~§ 4i&~Il~!l~e§ .:t)l~!li$eH~ fr()Hltll~!lp,ye, }'iIiJ~p'IHlm~.
. .. ' .
'fo }9!l~ ,!lm.sl5.~tte" t~e, J,>p~rat.9r .inser~.~ :~4ef).ppp¥ ~t~e,tte, ·.~~Pf,e,.~s..e!!
49,wp,Pfl
~
Jo'~~ pl~t§ jIl~e pwe,r!lJing
IIto4e,·
,s~e,·tiroe" (figyre,5-~?),
'f'he,
ct:ll t
e,ringc911e,
.
1lime,$~GE1Y lJIl~
.
·t·9
:Pl1~ j..ql!d:R~It,e,fI,I14
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J~<;l ?J~e, :is J>iv<;lt,e,d t0~e~9~~ .;p,p,s.i
t i o
Jl
I tg~9·e,l).Je,r~ fR~e, . :~t;l\ttg~~.e ~t:\9l?W ,:I~JS.~e,,!~ ~sp.Pt.~t'J: ,~~ t:t?pr9~Il;~lJ ~~ m~ .fr()m.tl;l,t::f:~~y~OWf!. P9I)i~iop., .!l~e,I1·tffip~9QI!e,:~'fcp~9,e,:J .~s, .~lht~WP1tj£.~Y ,is;!W~~: ~
!l~Yice,tlle,1}e,~p~4,~14e ,9e,J.\l;te,riP;~§P'V')? w~jc::;h ~jps. ~1l4e, ,!p:f!.@r ,,4~~~~~!;()~ .~,e :,5]!j§!s~ti!~:~~.~
,w
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aij~~m.~,
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<wltis@.
~~n~;~j~ :!r~\::~
,9
,~~j;11;S· ·~§t~t);l:SA~~,e*t Jo,t1;t.e.~q,1').:t,I:gl;l;~r fqrm,.~t~ :,~rec.:~:P~,~t!9~.iI!!~.·
{iE'Jlit@
,G9:J;l~J;.~' ~~',{l:~
~~~PiPlljl!\§~s 'J9;P,~kti.(;w ,:t.l;t.e.jY~lfi.~~ #9,t%l:t);te,Y!J:rr.elili
t ,t.r~*~.Q,
;;,1 y.~w 1t~~S~·
(
(
I.
EXPANDER S.PRING
. - - - - CENTERING CONE i
~+__
CENTERING CONE
EXPANDER
SPINDLE DRIVE
HUB
(
I
I
CP-1575
.
Figure 5-25 Centering Cone and Drive Hub
READ/WRITE
HEAD
FIXED WAY
FRONT
BEARING
MOUNT
Figure 5-26 Positioning Mechanism
5-40
TRACK 00
TRANSDUCER
CARRAGE
ASSEMBLY
HEAD LOAD
ARM
, .....
~ ~
MOTOR
HELIX DRIVE
CP-1576
( c---
(
(
The stepper motor includes four pairs of quadrature windings. In detent, current flows in one winding and maintains the rotor in electro-magnetic detent. For positioning, one or more step pulses are sequentially applied to quadrature windings, causing an imbalance in the electro-'Inagnetic field. Consequently, the stepper motor rotor revolves through detent positions until the step pulses are halted. The rotor then locks in that position. The sequence in which the stepper motor quadrature windings are pulsed dictates rotational direction and, subsequently, higher or lower track addressing from a relative position.
5.2.7.4 Head Load Mechanism - The head load mechanism is basically a relay driver and a solenoid. When activated by signal LD HD from the controller, the spring-loaded head load pad is released and rests in parallel alignment with the floppy diskette surface. Part of the casting provides the lower alignment dimensional surface, while the head load solenoid bar provides the upper alignment surface.
In the load position, the read/write head tang rides between these two alignment surfaces and keeps the read/write head in contact with the diskette surface. The load pad is located behind the read/write head and holds the floppy diskette flat against the lower alignment block.
To minimize diskette surface and head wear, the head is automatically disabled by the controller if no new command has been issued within 48 ms. Head settling time is 20 ms.
(
541
(
(
CHAPTER 6
MAINTEN ANCE
6.1 RECOMMENDED TOOLS AND TEST EQUlPMENT
Tahle 6·1 lists the recommended tools and test equipment [or maintenance of the RX8/RXll 'Floppy Disk Sy;stem.
Equipment
Multimeter
Tabie,6·1
Recommended Tools and Test Equipl1lent
Manufacturer and Model/Part No.
Triplett 310 or Simpson 360
Tektronix 453 Oscilloscope
Oscilloscope Prohes,
Voltage (Xl 0, two required)
TektronixP60ro
Field Service Tool Kit
Head Cleaning Kit
(includes TEXpadsand wand)
DEC 29·18303
DEC2U)0007
DEC 29·19557
DEC 29·19558
RX8/RXl1 Service Kit
DEC·O-LOG DEeEeo logand"computeron~1ineSYIiLOpsis
6.2 CUSTOMER ,CARE
A:lthough there 1sno scheduled preventive maintenance, there ,are two tasks that
,sh!)uld
be performe,dcon ,an as.,neededhasis.
1. Clean lheexteriorof the RXOI withadamp;Cioth,using,e1therasoll!vtion .oLnomJihrasi:ve,cleanerDrmild soap.
1. Examine the air filter (Figure :6·1) and clean fheelementasnecessary.Usewaterand,amiild'Soap" drying thoroughly . before 'rein.s,talling.
(
6·1
(
JUMPER P1
(
SHIPPING
RESTRAINT IRED)
FILTER
POWER PLUGS
Figure 6·1 RXO 1, Rear View
FILTER
7436·12
6.3 REMOVAL AND REPLACEMENT
The following steps define the procedures for replacing the subassemblies of the RX8/RXll Floppy Disk System.
6.3.1 Module Replacement
Floppy Disk Controller, M7726 (Figure 6·6)
1. Remove power from the RXOL
2. Unscrew the two captive screws on the right side of the module and raise the module to the servicing position.
3. Remove the plugs in connectors 11, 12, and J4.
4. Lower the module and remove the three screws holding the module onto the hinge.
5. Remove the module and remove the two captive screws.
6. To install a module, insert the two captive screws removed from the original module and perform the reverse of the steps 1-5.
(
J
(
6·2
(
(
(
(
Read/Write Control, M7727 (Figure 6-6)
1. Remove power from the RXOl.
2. Raise the floppy disk control module to the servicing position.
3. Remove the plugs from connectors on the module, ensuring that they do not drop into the drive.
4. Remove the six screws holding the module to the frame and remove the module.
5. To install a M7727, replace the screws and plugs removed in steps 3 and 4, ensuring that they are reinstalled into the correct connector (Table 6-2).
Connector
11
12
DKO(P3)
DKO(P4)
DKO(P5)
DK0(P6)
DKO(P7)
DKO(P8)
DKl(P3)
DKl(P4)
DK1(P5)
DK1(P6)
DK1(P7)
DK1(P8)
*Not used.
Table 6-2
M7727 Connectors
Description
Disk drive interface cable
Power from H771 power supply
Head cable
Stepper motor
Head load solenoid
Index signal
Track 0 signal
Write protect*
Head cable
Stepper motor
Head load solenoid
Index signal .
Track 0 signal
Write protect*
H771 Power Supply Regulator, 70-10718 (Figure 6-6)
1. With the power off, remove the plug from the regulator.
2. Unscrew the leads going to the capacitors, checking with the H771 prints to ensure that the wiring matches the prints.
3. Remove the plugs from the M7726 and M7727.
4. Remove the six screws holding the regulator to the power supply chassis.
5. Replace the regulator by performing the reverse of steps 1-4.
6-3
6.3.2 Drive Placement (Figure 6-6)
1. With the power removed, remove the power plug
in
the rear of the drive (Figure 6-1).
2.
Remove the plugs for this drive (Table
6-2),
3. Loosen the
six
screws holding the drive to the chassis.
4.
While holding the drive, remove the SCrews from the four corners.
5.
Carefully remove the two remaining screws without allowing the drive to drop down.
6. Slowly lower the drive, guiding the wiring
as
the drive
is
lowered.
7.
To install a drive, place the two center screws
in
the holes
in
the chassis.
8. Raise the drive; guiding the wiring through the hole.
9.
With the drive centered, start the two screws carefully sO as not to cross.thread them. Do not tighten these screws
all
the way.
10.
Start the remaining screws; being careful not to cross-thread them.
11.
Tighten aU screws.
12.
Insert
the
plugs
listed
in Table
6·2.
13.
Insert the power plug.
6.4
CORIU~CTIVE
MAINTENANCE
Figure
6.2,
Sheet
1,
illustrates the method to
be
used when correcting a fault in the
RX8/RXll
system. The proper use of
the KMll
module is described in Paragraph 6.4.2.
6.4.1 Errors
6.4.1.1 Interface Diagnostic in Memory
=
Use Figure 6·2, Sheet 2.
( c c: t-'
(
6·4
(
(
(
(
(
Figure 6-3 SCb5L-15 Cabie (Reversed) (Sheet 1 of 2)
7436-1
(
Figure 6-3 BC05L-15 Cable (Correctly Inserted) (Sheet 2 of 2)
7436-16
(
( i;
c-- ·
(
6-8
(
(
(
(
}
6.4.1.2" Diagnostics Not in Memory - Since the RX8/RXll may be the only input'd!Nice for a system, there may not be a way to input the diagnostics into the system. In that event, the following routines
(Figur~s
64 and 6-5) and the use of the Initialize Diagnostic Routine residing in the controller's firmware may aid in the repair of the floppy disk "
1. Load the following routines (Figures 6-4 and 6-5) into main memory .. '
2. Starting at location 200 (RX8) or 1000 (RXll), initiate the program.
'I.
3. Examine the status locations for failure information.
ESTAT,Rl
DSTAT,RO
EREG,R2
DRSTAT
4. A good pass with a media installed in drive 0 will be:
ESTAT/Os
DSTAT/4
8 or 104
8
EREG/Os
DRSTAT/204
8 or 304
8
5. Neither the read/write controller module nor the drives will cause the program to continuously loop on the first check of the Done flip-flop.
6. If the program halts at any location other than the halt at the end of the program, the controller or interface module could be at fault.
7. If the program halts at the end of the program with the following status, the controller is most likely at fault.
ESTAT/4s
DSTAT/Os
EREG/60s
DRSTAT/X
8. All other valid error status will probably be caused by the read/write controller module, the drive, or the floppy disk controller module. It should be noted that a Read Sector is not performed on drive 1; therefore, it is possible for a fault to inhibit reading on both drives without reporting that information.
6.4.2 KMll Usage
The KMl1 maintenance module may be used to single-step through a routine in the floppy controller's firmware. It should be noted that at times the controller will be accessing a signal produced from the media; in this case, the
KMll cannot single-step the microprogram. For the correct method of inserting the KMl1, refer to Figure 6-6. The representation of the lights and use of the switches is shown in Figure 6-7. To start a functional routine, the command must be issued from the central processor.
(
6-9
6771
6772
6774
6775
6777
0200
0200 6775
0201 5200
0202 6774
0203 5207
0204 6772
0205 3227
0206 5211
0207 6772
0210 3226
0211 1225
0212 6771
0213 6775
0214 5213
0215 6774
0216 7410
0217 7402
0220 6772
0221 3230
0222 7402
0223 6777
0224 5200
0225 0016
0226 0000
0227 0000
0230 0000
IRxa STATUS ROUTINE
LCD=6771
XDR=6772
SER=6774
SDN=6775
INIT=6777
*0200
SON
JMP .-1
SER
Jr4P .+4
XDP
DCA ERSTAT
JMP .+3
XDR
DCA DNSTAT
TAil ROE REG
LCD
SON
JMP .-1
SER
SKP
HLT
RDEREG.
DNSTAT.
ERSTAT.
EREG.
XDR
DCA EREG
HLT
INIT
JMP 200
0016
0
0
0
$
ISKIP ON DONE FLAG
IWAIT FOR FLAG
ISKIP ON ERROR FLAG
IBRANCH ON NO ERROR
ITRANSFER DATA - RXOI STATUS TO AC
IS AVE IN LOCATION ERROR STATUS
IA~ANCH OVER THIS HASH
ITRANSFER DATA ~XOI STATUS TO AC
ISAVE IN LOCATION DONE STATUS
IGET READ ERROR REGISTER COMMAND
ILOAD THE COMMAND REGISTER
ISKIP ON DONE FLAG
IWAIT rOR DONE FLAG
ISI<IP ON ERROR
IUNCONDITIONAL SKIP
IFATAL ERROR - FAILURE TO EXECUTE
- IA "READ ERROR REG" COMMAND
ITRANSFER DATA - RXOI ERROR REG TO AC
ISAVE IN LOCATION ERROR REG
IREPLACE WITH NOP (7000) TO LOOP
IINITiALIZE RX01·
ILOOP
Figure 6-4 RX8 Status Routine
001000
001006
001010
001014
001016
001022
001030
001036
001040
001044
001046
177170
177172
000000
000001
000002
001000
032767 000040
001774
005767 176154
100424
010067 176150
012767 000017
032767 000040
001774
,005767 176124
100001
000000
001050
001054
001056
001064
001066
001072
016702
000000
012767
000745
016701
000753
000001
176116
040001
176100
:PXll STATUS ROUTINE
:RO = STATUS REG IF DONE COMES UP
:Rl = STATUS REG IF DONE COMES UP
RXCS=I77170
& NO ERROR FLAG
& ERROR FLAG
:R2 = RXOI ERROR REGISTER CONTENTS (S~ECIFIC ERROR CODE)
RXDB=177172
RO=%O
Rl=%!
R2=%2
.=1000
176162 START: BIT #40.RXCS
BEO START
TST RXCS
BMI INITER
MOV RO.RXDB
176140 READ: MOV U 7. RXCS
176132 READ1: BIT #40.RXCS
AEO READI
TST RXCS
BPL READ2
HALT
READ2: MOV RXIlB.R2
HALT
:TEST DONE BIT
:WAIT FOR DONE
:TEST ERROR BIT (MSB)
:BRANCH TO INITER ON INITIALIZE ERROR
;PUT DONE STATUS IN RO
; ISSUE READ ERROR REG COMMAND & GO BIT
;TEST DONE BIT
;WAIT FOR DONE
;TEST ERROR BIT (MSB)
:BRANCH TO READ2 IF NO ERROR
;FATAL ERROR - ERROR OCCURED
:IN "READ ERROR REG", COMMAND
:PUT SPECIFIC ERROR CODE IN R2_
:NORMAL HALT - REPLACE WITH NOP (240) TO LOOP
176104
INITER:
MOV #40001.RXCS
BR START
MOV RXDB.RI
BR READ
.END
;ISSUE RXOI INITIALIZE
;START OVER
;PUT ERROS STATUS IN RI
:GO READ ERROR REGISTER
& GO BIT
Figure 6-5 RXll Status Routine
(
(
( l
6-10
(
(
Figure 6-6 KMII Maintenance Module Inserted
6-11
7436-8
(
RUN
ENAB
0
ERROR
HLT
0
CONTINUE
0
UNUSED
0
HALT
CI
I
I
J
INSTI
CO
, ,
I
I
INSTO
I
I
FIELD
,
I
1
I
I
I
PROGRAM COUNTER
I
,
I I
COUN TER
SELECT FIELD
. I
I
I I I
PC7'
I
PCO
I
CP-1543
Switch
RUNENAB
CONTINUE
ERRORHLT
Function
ON: M7726 Clock
OFF: Maint. Clock Pulses (Continue)
ON: Advance Controller Firmware Once
OFF: -
ON: Halt Controller When Error Detected
OFF: Do Not Halt On Error Condition.
Lights
HALT
INST 1 and 0
SELECTFLD
CO and Cl
FIELD
PROGRAM COUNTER (0-7)
COUNTER (0-7)
Function
Firmware Halted
Instruction Bits
Selects 1 of 16 Conditions (Depends on Instruction)
Control Functions (Depends on Instruction)
ROM Field
(Halted) Address + 1 of Instruction Displayed
Displays Contents of Counter Register
Figure 6·7 KM 11 light and Switch Definitions for RXO 1
(
(
(
(
6·12
(
(
(
(
Voltage
+5Vdc
+9.5 Vdc
+24 Vdc
-5Vdc
+10 Vac
+24 Vac
Table 6-3
Power Supply Output Voltages
Tolerance Measured At
PI-4
P2-4 .;;;; +5.25 Vdc
Ripple';;;; 200 mV (P-p)
~+9.0Vdc
.;;;; +10.3 Vdc
Ripple';;;; 2.0 V (p-p)
P2-7
Pl-l
.;;;; +28.0Vdc
Ripple';;;; 1.2 V (P-p)
PI-6
.;;;; -5.6 Vdc
Ripple';;;; 200 mV (p-p)
11-1,3
11-2,4
NOTE
This table should be used in conjunction with the DC Power
Checks perfonned with Figure 6-2, Sheet 1.
(
6-13
(
(
(
(
(
I
I
I
I
I
I
I
I
I
I
>.14
I~
!:
I~
o
I~
,8
RX8/RXll FLOPPY DISK SYSTEM
MAINTENANCE MANUAL
EK-RXOl-MM-002
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Tel!,ptton ... (08)42 1339
'i06i
Tell'~ 790·8282<)
DRISBIINE
1.13 l.",rhhl>rrit Sir"",
SpflnQ
Br<sh;ln .. r",lcp hon"
'000
790 40616
CANBERRII
27 CollI" St
Fyshw , r;" ACT 2609 Atlstr",ll"
Telephone (061}·9'>9073
MElBOIJRNE sn Pa,k St'''f"'t Sn"t'" M"lbou"w , VlctO"iI 320',
Austrill'n
T(,I('phonf' (03}6Cfl:>fl88 Tei". 790·30700
PERTH
643 M"".,)' Str ... "t
West P(rth , Wl's!""n AIISI,~I", 6(XY,
Tc!"phonr (0CI?PI49
Q
1 Telex 700g2140
SYDNEY
PO Bo> 491 . Cro,",s Nl'st
N SW !\"Slfill!i1 ;>osr,
T"If'nho"" (O?) 419 ?'./is TI'If'
<
;90 20740
NEW ZEALANO
Dalltal (qlllpmrnt COrPOrMlon Ltri
AUCKLAND
Holton HCIIIs!!
. 430 Oul'!'n Street BOll 2 471
Auckland New Z(,illand
T!.'I!.'phone 75533
WEST
REGIONAL O FFICE '
310 Soquel Way . Sunny .. ate Cal ifornia 9 40B6
Telephone (0408)·135-9200 Da taphone 4Q8..735· 182Q
A RIZONA
Phoenlll
4358 East Broadway Road. PhoeniX. Aflzona 85040
Telephone (602)·26S-3488 Dataphone 602-268·7371
C ALIFORNIA
Santa Ana
2110 S Anne Street. Santa Ana. CalifornIa 92 ~
Telephone (71 4)979 ·2460 Dataphone 7 14-979·7850
San Diego
6154 MISSion Go rge Road
SUi te 110. San Diego. Califo rnia
Telephone (7 14) ·2!!(}..7880/7970 Dalaphone 7 14-280--7825
San FranCISCo
1400 T erra Bella. Mountam Vi ew . Caillornia 94O«l
Telephone ( 415 }-964-6200 Dalaphone 4 15964-1436
Oalliand
7850 Edgewater Drive, Oakland, California 94621
Telephone { 41 5},635-545J/7830 Dataphone· 415-562 ·21 60
West los Angeles
1510 Cotner Avenue. los Ang eles. Cali fornia 90025
Telephone (213)· 479 ·379 1/4318 Dataphone 2t3<l 78·5626
COLO RADO
7901 E. Bellevue Avenue
SUIte S. Englewood. Colo rado 80 110
Telephone (303)·710·6150 Dataphone :Jl3·77o6628
NEW MEXICO
Albuquerque
10200 Menulil N E . Albuquerque. New Mexico 87112
Telephone (505)·296,5411/50128 Dataphone 505·29<1·2330
OREGON
Portland
SUIte 168
53 19 S W Westgate Drive. Porlland, O r egon 97221
Telephone. (503}·297-37 61/3765
UTAH
Salt lllke C,ly
429 lawn Dale Drive. SaIl Lalle City. U tah 6 4115
Telephone (801}4874669 Dalaphone 801· 467·0535
WASHINGTO N
Bellevue
13401 N E Bellevue, Redmond Aoad. ~ui te 111
Bellevue. WliShingtOn 98005
Telephone (206)·5454058/4.55
· 5404 Da taphone 206-7 47·3754
JAPAN
Digital EquIpment Corpora tion In ternational
Ko wa BuHding No 16 Annell. First Floor
9·20 Ak uliki I· Chome
M if\ al o-Ku . To~o 107 l epen
Talephone 58e · 2771 T e l ex
Alkel Trading Co .
126428 ltd ( sales only)
KOl!llo-Kalklln B l dg
No 18·1 " N i sh ishimbas h i IChome
Min{llo ·Ku . Tokyo . Japan
T"lephbne 59152 46 Telell ' 781·4208
PUERTO RI CO
DiQ'tal EQuipment CorpOf~!lon De PUNtO RICO
407 del ParQue Slreet
Santurce Puerto RICO 00912
Telephone (809)·]23-8068/67 Telell 385·90$
ARGENTINA
BUENOS AIRES
Cousin SA
V,rrey del P!no. 4071 Buenos A'H!S
Telephone 523185 Telex Ot2·2284
BRAZIL
RIO DE JA NEIRO GB
AmbrleJl: 5 A
Rua C~ara. 104 2 e 3 anda res ZC 29
A,o De JaneirO G B
Telephone 264-7<106/0461/7625
S AO P AULO
Ambflell SA
Aua T upl. S35
Sao Paulo SP
Tel~phone 52-780611870, 51..()912
PORTO ALEGRE RS
AUil Co ronel Vlcen le 4 2 1/101
POflo Alegre AS
Tel!'phone2 4 7 411
CHILE
SANTI AGO
CoaSIn Chile Ltda (sales only)
Casltla 14588, Correo IS.
Telephone 396713 Cable COACHll
INDIA
BO MBAY
Hlndltron Computf'fS Pv! Ltd
69/A, l JllQmohandas Marg
60mba y·6(WB} IndIa
Telephone 38·1615 36· 5344
Cable TEKHIND
T ele~ 0 11 ·2594 Plenty
MEXICO
MEXICO CITY
Me"'te!! 5 A
Eugenla408DePIO' 1
Aodo Poslal 12·1012
Mex,co I t · DF
T('lephone (905) ~09·10
PHILIPPINES
MANilA
5tanfo rri Compllter Coroo ratlon p 0 Bo~ 1608
416 DlIsmllrlflllS SI Manila
Telephone 496896 Telell 7 42 ·0352
VENEZUELA
CARACAS
CoaSln C A
Apartildo S09J9
Silbana Gr,1nde No 1 CMaCi,lS 105
Telephone ]2·8662 72·9637
Cable I N$TAUVEN printed in U .
SA
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