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AJ\11-386 BIOS PLUS
USER MANUAL
American Mega trends Inc.
4025 Pleasantdale Road, Ste 320
Atlanta, Ga - 30340
Ph. (404) 263 8181
Fax. ( 404) 263 9381
ATARI
AT:..Rl Comp::\:?; t.r:.::!:
Technologl�7'2�"'�;
Julius-Kon�Gn-�:, ....
3300 eraunschwelg
ToL: 05 31 / 50 00 17
Table Of Contents
Section I
Installing the AMI-386 BIOS .
- Memory Test Bypass
CMOS Setup .
.
.
.
Summary of Set-up .
When does the BIOS prompt you to run Set-up? .
Errors Reported By AMI-BIOS
Appendix B & Figures
Overview . . . . . .
Hard Disk Diagnostics
Floppy Diagnostics . .
Keyboard Diagnostics
Video Diagnostics . .
Miscellaneous Diagnostics.
Append.ix A
Section 2
JO
12
16
18
19
20
21
8
23
6
7
3
3
4
2
Section 1
1.0 BIOS Overview
This guide explains how to : a) Install the AMI-386 BIOS .
b) Use the built-in Set-up Procedure.
-c) Select the Clock Speed / Wait States through the Keyboard.
d) Interpret the errors reported by the AMI-BIOS.
e) Use the 3 1/2" floppy drive support effectively.
2.0 Installing the AMI-386 BIOS
Skip this paragraph if the BIOS is already plugged on the MotherBoard.
Before you begin the installation ensure the following: i ) The Board is powered down. ii) ROM's are susceptible to static electricity. So observe the following precautions when you handle a ROM: a) Unpack the ROM's on a ground connected anti-static mat.
b) Wear an anti-static wristband, grounded at the same point as the anti-static mat.
(A cheaper solution is to use a sheet of conductive aluminium foil grouded through a l Mega-ohm resistor instead of an anti-static mat. Similarly, a strip of conductive aluminium foil wrapped around the wrist and grounded through a I Megaohm resistor will serve the purpose of a wrist band.)
Ensure that the ODD & EVEN BIOS go into their respective sockets.
3.0 Starting Up The System
Power up the system and wait for the BIOS to show up the BIOS activity on the screen.
4.0 Memory Test Bypass
The BIOS performs diagnostics of the system and displays the size of the memory being tested.
Note that you can bypass the memory test by pressing the <ESC> key.
This option would be quite useful when the memory. on the system is quite large. You should hit the <ESC> key when the message Press <ESC> Key to bypass MEMORY test appears on the screen.
Also note the Ref. number at the bottom of the screen. Make a note of this number before you call Customer Support at AMI for assistance with the BIOS.
3
5.0 CMOS Setup
Immediately after the memory and cache test, you will get the following prompt on the screen :
Press <DEL> key to run SETUP Utility
Hit <DEL> key to get into the Setup Mode. Note that <DEL> key will get
· you into ,the set-up mode only when the message :
Press <DEL> key to run SETUP Utility, is displayed on the screen.
If you hit <DEL> key the following message appears on the screen:
WANT TO RUN SETUP UTILITY (Y/N)?
If you hit <Y> or <y> and the <ENTER> key you have the Setup screen.
5.0.1 Time/Date Setup
The Setup screen looks like below :
CM O S S E T U P
Curret date is : XX-XX-XXXX
Enter new date (MM-DD-YYYY)?
To this question you would have to enter the date in the format shown on the screen.
If you feel that the current date should remain unchanged, you would just have to hit the <ENTER> key. In such a case the new date is set to the same value as the current date.
The next question you have on the screen is:
Current time is :XX:XX:XX
Enter new time (HH:MM:SS)?
To this question you key in the time in the format defined. Press
<ENTER> key alone if the current time is right.
As soon as you have done this the BIOS shows you the type of the display on your system.
After that, the setup takes two differet paths depending upon the CMOS being initialized or uninitialized.
4
5.0.2 CMOS Initialized
Under these conditions you would see the foliowing messages :
Fixed disk drive C type
- Fixed disk drive D type
: X (if installed else Not Installed.)
: X (if installed else Not Installed.)
Diskette drive A is 3 1/2"
Diskette drive B is Double Sided (Other options as above)
Base Memory Size is : XXX KB
Expansion memory size is : XXXX KB
Are these options correct (Y /N)?
Note that the information about Drive A indicates 3 1/2", as CMOS had been set earlier to reflect this status. If on the contrary, CMOS had been set for a 1.2 MB drive, the message in place of 3-1 /2" it would be High
Capacity.
If you feel that the information displayed above is right, hit <Y> and the
<ENTER> key to proceed to system boot with the new information.
5.0.3 CMOS Uninitialised
5.0.3.1 Disk DriYe Type Definition
In this case you would have to enter the type of the· fixed Drive C in response to the message :
.... WARNING ••••
Entering the wrong disk drive TYPE causes improper operation of the disk.
If disk not installed press <RETURN>
For disk TYPE details press <ESC>
Enter disk drive C type (1-47)?
Note that the disk type details are only a key stroke a way. Hit <ESC> key to find for yourself. You could always come back by hitting <ESC> again.
Refer to Appendix B for drive details.
Once you have convinced yourself about the drive type enter the appropr iate number and hit <ENTER>.
You would then be asked to enter the type of the disk Drive D. The proc edure for doing this is the same as that for Drive C. Remember if you do
5
not have disk Drive D on your system, you just have to hit the <ENTER> key.
6.0 Floppy Drive Type Definition
Diskette drive A is 3 1/2" (Y /N)?
- The above question is asked if the drive has been found to have 80 tracks.
Since a drive with 80 tracks could either be a
- high capacity i.e l .2 MB drive
- or 3 1/2" i.e 720 KB drive, you would have to answer this question.
By entering <N> or <D> you can select the high capacity drive. Alternative ly enter <Y> or <y> to select a 720 KB drive. This question could come up for the case of drive B as well provided it has been detected as a 80 track drive by the BIOS.
If you hit the <ENTER> key alone, the BIOS assumes the drive to be a 1.2
MB drive.
At this point you have entered all the information the BIOS requires for starting up the system.
BIOS detects a few details by itself, e.g. the diskette drive type in case of a 360 KB drive as shown below:
Diskette drive B is : Double Sided (Other options as above)
Base Memory Size is :
Expansion memory size is :
XXX
KB
XXXX
KB
Are these options correct (Y /N)?
If you are convinced at this stage that all the information you have entered upto this point is right, hit <Y> or <y> key followed by <ENTER> key.
When you do this the BIOS goes all over again to boot up the system with the information specified.
However, if you would like to modify some information, then you should hit either <N> or <o> key followed by enter. You would now go through the setup all over again.
7.0 Summary of Set-up
The Set-up screen thus requires you to set a) Date.
b) Time.
c) Hard Disk Type For Drive C (if present).
d) Hard Disk Type For Drive D (if present).
The Set-up procedure also automatically detects the following: a) Type Of Display Card.
b) Size Of Real Memory.
6
c) Size of Memory beyond I MB.
d) Presence of 360 kb floppy drives.
e) Presence of a 80287.
Also. if a second Hard Disk drive is physically connected but the CMOS nqt set for this Drive D, the BIOS informs you about the same and gives is
- you a chance to configure the drive through SETUP.
Having setup the CMOS. the BIOS runs through the diagnostics again, tests the memory, sets up the devices configured and proceeds to boot.
Note that the Set-up option is available even after a soft reset.
8.0 When does the BIOS prompt you to run Set-up?
The BIOS prompts you to run Set-up under the following conditions a) CMOS options not set.
b) Display Configuration Mismatch.
c) Memory Size mismatch.
d) Hard Disk Set-up error.
e) CMOS battery is low.
f) An additional hard disk presence is detected.
9.0 Selecting Clock Speed/Wait States
AMI-BIOS allows you to change Clock Speeds and Wait States through the keyboard at any time. Following are the key combinations and their mean ings :-
1.
Kev Combinations
<CNTRL><AL T><+>
2. <CNTRL><AL T><->
Meaning
Switch to high speed.
Switch to low speed.
3. <CNTRL><LSHIFT><ALT><+> Switch to zero Wait state.
4. <CNTRL><LSHIFT><ALT><-> Switch to one Wait state.
10.0 Errors Reported By AMI-BIOS
AMI-BIOS performs various diagnostic tests at . the time the system is powe red up. Whenever an error is encountered during these tests, either you hear a few short beeps or see an error display on your monitor. If the error occurs before the display device is initialised the system reports the error by giving a number of short beeps.
If the error is FATAL then system halts after reporting the FATAL error.
If the error is NON-FAT AL the process continues after reporting the NON
-FAT AL error.
7
10.0.1 Fatal Errors
Beep Count Meaning
I
2
3
4
5
6
7
8
9
DRAM refresh failure .
Parity Circuit failure.
Base 64KB RAM failure.
System Timer failure.
Processor Failure.
Keyboard Controller - Gate A20 error.
Virtual Mode Exception Error.
Display Memory R/W Test Failure. (*)
ROM-BIOS CheckSum Failure.
(*) Non-Fatal Error.
10.0.2 Error Messages
Fa ta 1 Errors
1.
Channel - 2 of Timer Not functional.
2.
Stray Interrupt sensed in controller.
3.
Interrupt controller #2 not functional.
Non-Fatal Errors l.
Keyboard Error.
2.
Keyboard/Interface Error.
3.
CMOS battery state low.
4.
CMOS system options not set.
5.
CMOS checksum failure.
6.
CMOS memory size mismatch.
7.
CMOS system time and date not set.
8.
CMOS display configuration mismatch.
9.
Display setting not proper.
10. Keyboard is locked ..... Unlock it.
11. Floppy disk controller failure.
12. Hard disk unit O error.
13. Hard disk unit 1 error.
14. Hard disk unit O failure.
15. Hard disk unit l failure.
16. Hard disk unit I is not defined in CMOS.
17. Cache Memory Bad - Do Not Enable Cache.
11.0 Use of 3 1/2" Support Effectively
DOS 3.20 provides support for support from the ROM BIOS. provides the necessary support.
3 1/2" drives. For this
AMI-BIOS release date purpose it needs
12/03/86 onwards
The 3 1/2" drive can be fre::ly configured as Drive A or Drive B with this
8
BIOS. Thus it is possible to boot off directly from a
3 1/2" drive.
Earlier versions of DOS would require the use of DRIVER.SYS to provide the necessary support.
- A few points would have to be kept in mind when you use the
3 1/2" drive and a 1.2 MB together. Ensure that when you perform the
Setup you define the drives correctly. Incorrect definition could make the drive unusable.
The table below describes the valid combinations on a AT:
CMOS Status Physical Drive Status Functional
1.2 MB 1.2 MB
3 1/2" 3 1/2"
Undefined 1.2 MB YES
YES
YES
The re maining combinations are invalid. bin a tions before you call us for help.
Please make a note of these com-
Should you feel that you need assistance with the BIOS at any stage, call
AMI Tech. Support at (404) 263-8181.
9
Section - 2
1.0. Overview
A:tvll-386 BIOS PLUS provides the following in a ROM : a) Field proven extensively used A:tvU-386 BIOS.
b) Built-in CMOS setup utility with support for 47 Disk drive types, 3 1/2"
Floppy Disk drives
&
Enhanced Keyboard.
c) A Diagnostics program - superior to the IBM Advanced
Diagnostics - with special enhancements & a user-friendly interface.
d) A Built-in Calendar.
This portion of the manual explains how to use the Diagnostics program alone.
386 BIOS PLUS plug these ROMs that the DTP icate 256K Chips. comes in 256K ROM chips. Hence make sure that when vou
Switch on the Svstem Board is set to ind
2.0 Selecting The Diagnostics Option
Hit the <DEL> key on the numeric keypad when you see the following mes sage at the time of system startup:
Press <DEL>
Key to run SETUP or DIAG
The above message is seen on the 4th line of the screen.
Hitting <DEL> key brings the following message after a few seconds on the screen
Want to run SETUP or DIAG (Y /N)?
If you answer <Y> or <Y> followed by <ENTER> then you would be asked to select either Setup or Diagnostics as shown below:
SETUP or DIAG (1/2)?
Hit < l> to use the built-in SETUP option.
Hit <2> to use the Advanced Diagnostics option.
10
3.0 Diagnostics Menu
Note the following in the Diagnostics Opening Menu : a)
°
The Guide Line in Reverse Video specifying the usage of the Cursor
Keys, <ENTER> & <ESC> key. b) The Configuration of the system in the "Devices Present" box.
c) The Real Time Clock ticking away at the right hand top corner of the screen.
d) Diagnostics Options Line - Hard Disk, Floppy, Keyboard, Video & Misce llaneous Diagnostics.
e) Hard Disk Diagnostics Options Window - detailing the various disk diagnostics that are available.
hard f) Note that the Block Cursor is on the Hard Disk & the first under hard disk diagnostics - Hard Disk Format.
option
4.0 Key Conventions
Use the Left & Right arrow keys to move in the Diagnostics Options Line.
Use the Up & Down arrow keys to move within a Diagnostics Options Win dow.
Use the <ENTER> key to select the option in the Diagnostics Options Win dow.
Use <ESC> key to abort & return to previous menu.
5.0 Diagnostics Options Window
The individual diagnostics options are as below :
1. Hard Disk options.
2. Floppy Disk drive options.
1. Keyboard options.
4. Video options.
5. Miscellaneous options.
J J
Hard Disk Diagnostics
1.0 Using Hard Disk Options
The Hard Disk options discussed below fall in two categories :
-a) Destructive Operation lost.
- b) Non-destructive Operation undisturbed.
The data on the Hard Disk is
The data on the Hard Disk is
The list below gives the various Hard Disk Options & the category they fall in : a) Hard Disk Format b) Auto Interleave c) Media Analysis d) Performance Test e) Seek Test f) Read/Verify Test g) Check Test Cylinder
Dc:structi ve Operation.
Destructive Operation.
Destructive Operation.
Non-destructive Operation.
Non-destructive Operation.
Non-destructive Operation.
Data on the Test Cylinder alone is lost.
All the options under Hard Disk Diagnostics require more or less the follo wing inputs: a) Disk Drive b) Drive Type c) Interleave Factor d) Bad Track List e) Start Cylinder f) End Cylinder g) Start Head h) End Head
All the above input fields have a default value. Thus a user need not nece ssarily key-in all the inputs.
We shall discuss the inputs required & their meaning for Hard Disk Format
Option. This discussion can however be extended for the rest of the Hard
Disk Options.
2.0 Hard Disk Format Option - (Destructive Operation)
Figs 6 & 7 reflect the various screens the user goes thru' when this option is selected.
Note that in case of a single drive System the disk drive for the operation is assumed to be drive C.
12
a) Drive Tvpe Definition
The default value for the drive type is the SETUP value set during the
CMOS setup.
However if the drive was not set during CMOS Setup, the user now has an
-option of setting the drive to be one among the 46 standard
Disk drive types.
Note that all the information about the drive unfolds when the disk drive type is being chosen.
If the disk drive type does not fall within the 46 standard disk types, use the USER option to define your own parameters for the drive.
Note that this USER definition is valid only as long as the Diagnostics is in effect. This feature is provided for you to test a disk drive, the definition for which is not available in the ROM b) Interleave Factor
Choose an optimum interleave factor. Ref er to the Appendix • A for details on how to decide on an Optimum interleave.
The default value for the interleave factor is 3. c) Mark B:id Tr:icks
If the manufacturer has defined certain bad patches on the .,disk, enter <Y> to this question.
The user then goes into a menu which allows for complete editing of the bad track list.
Exit Bad track entry by hitting <ESC> or selecting the Save And Exit op tion. Note the usage of <ESC> key here.
The default answer for this question is <N>. d) Cvlinder Number
Enter the Start & End Cylinder Number if you want to override the defau lts.
The same is true for Start & End Head number.
The default value for the start Cylinder & Head is O and that of the End cylinder & head is the value of the maximum cylinder & head respectively.
13
e) Proceed
If all the entries are correct, you could hit <Y>. Else you could say <N> & go over all the entries again.
The default answer is <N>. f) Warning
If you had hit <Y> to the previous question, you get a WARNING message .
You could proceed to format if you are absoulutely sure about the informa tion you have entered upto this point. g) Activitv Screen
PLUS then proceeds to format the Hard Disk with the specified parameters.
While it is formatting PLUS displays the Operation in progress, the Cylinder
& Head No. that is being formatted.
You could always hit <ESC> key to abort the format operation.
2.0 Auto Interleave Option - (Destructive Operation)
This is the most powerful feature which enables you to get the peak per formance out of your Hard Disk.
With this feature you need not speculate about the value of the Interleave
Factor. PLUS is entrusted with the job of finding the optimum Interleave value by a trial & error method & formatting the Hard Disk with this value.
Discover the big advantage with this feature.
3.0 Media Analysis Option - (Destructive Operation)
Media analysis performs the following operations on the Hard Disk:
- Preformats the Hard Disk with specified parameters like Format Option.
- Analysis the surface of the Hard Disk for any errors & makes a note of them.
- Marks the Bad Patches.
This takes quite some time & for best results this test should run uninter rupted.
The parameters required for this are to be inputted rn the same way like the Format Option.
14
a) Drive Tvpe Definition
The default value for the drive type is the SETUP value set during the
CMOS setup.
However if the drive was not set during CMOS Setup, the user now has an
-option of setting the drive to be one among the 46 standard Disk drive types.
Note that all the information about the drive unfolds when the disk drive type is being chosen.
If the disk drive type does not fall within the 46 standard disk types, use the USER option to define your own parameters for the drive.
Note that this USER definition is valid only as long as the Diagnostics is in effect. This feature is provided for you to test a disk drive, the definition for which is not available in the ROM b) Interleave Factor
Choose an optimum interleave factor. Ref er to the Appendix - A for details on how to decide on an Optimum interleave.
The default value for the interleave factor is 3. c) M:.1rk Bad Tracks
If the manufacturer has defined certain bad patches on the disk, enter <Y> to this question.
The user then goes into a menu which allows for complete editing of the bad track list.
Exit Bad track entry by hitting <ESC> or selecting the Save And Exit op tion. Note the usage of <ESC> key here.
The default answer for this question is <N>. d) Cvlinder Number
Enter the Start & End Cylinder Number if you want to override the defau lts.
The same is true for Start & End Head number.
The default value for the start Cylinder & Head is O and that of the End cylinder & head is the value of the maximum cylinder & head respectively.
13
e) Proceed
If all the entries are correct, you could hit <Y>. Else you could say <N> & go over all the entries again.
The default answer is <N>. f) Warning
If you had hit <Y> to the previous question, you get a WARNING message .
You could proceed to format if you are absoulutely sure about the informa tion you have entered upto this point. g) Activitv Screen
PLUS then proceeds to format the Hard Disk with the specified parameters.
While it is formatting
& Head No. that
PLUS displays the Operation in progress, the Cylinder is being formatted.
You could always hit <ESC> key to abort the format operation.
2.0 Auto Interleave Option - (Destructive Operation)
This is the most powerful feature which enables you to get the peak per formance out of your Hard Disk.
With this feature you need not speculate about the value of the Interleave
Factor. PLUS is entrusted with the job of finding the optimum Interleave value by a trial & error method & formatting the Hard Disk with this value.
Discover the big advantage with this feature.
3.0 Media Analysis Option - (Destructive Operation)
Media analysis performs the following operations on the Hard Disk:
- Preformats the Hard Disk with specified parameters like Format Option.
- Analysis the surface of the Hard Disk for any errors & makes a note of them.
- Marks the Bad Patches.
This takes quite some time & for best results this test should run uninter rupted.
The parameters required for this are to be inputted in the same way like the Format Option.
14
4.0 Performance Test - (Non-Destructive Operation)
This test enables the user to check out his disk performance. The critical factor in deciding the disk performance is the Interleave Factor. Changing the Interleave factor can bring about drastic changes in Disk Performance.
-This test determines the Data Transfer Rate & the Track to Track Seek time. Data Transfer Rate is measured in the units Kilobytes/Second & the
· Track to Track seek time in milliseconds.
Higher value for Data transfer rate implies a better disk performance & lower value of track to track seek time indicates a better disk.
Refer to Appendix A for more on Interleave Factor & how to choose the same for best Disk Performance.
5.0 Seek Test - (Non-Destructive Operation)
This test checks the seek capability of the HardDisk on the specified Cylin der & Head range. First a sequential seek is performed & then a random seek is performed.
Any errors during this test are reported.
6.0 Read/Verify Test - (Non-Destructive Operation)
This test performs sequential & random read & verify operation on the specified Cylinder,Head range.
7.0 Force Bad Tracks - (Destructive Operation)
This operation enables an User to define a set of tracks as bad. Certain specific applications require this option.
15
Floppy Diagnostics
All the options under floppy diagnostics require more or less the require the _following inputs : a) Drive No.
b) Start Track No.
c) End Track No.
As in the case of hard disk the list below gives the effect of each of the diskette tests : a) Diskette Format b) Speed Test c) Random R/W Test d) Sequential R/W Test
- Destructive.
- Non-destructive.
- Destructive.
- Destructive.
e) Disk Change Line Test - Non-destructive.
1.0 Diskette Format - (Destructive)
This test allows an user to check out the NEC 765 controller's abilities to format a diskette.
The user need not be bothered about the drive or the diskette in the drive.
PLUS automatically determines the best way a diskette can be formatted for reliability. e.g. In case of a l.2MB drive the user need not specify whether the diskette to be formatted is 1.2 MB or 360 KB capacity. PLUS finds the most reliable format automatically.
Note that this test does not write a DOS format on the diskette.
2.0 Drive Speed Test - (Non-destructive)
This test determines the speed of rotation of the drive. Please note that the following are the allowable speeds for the various drives : a) 1.2 MB drive -360 rpm for a 1.2 Mb diskette in it.
-300 rpm for a 360 Kb diskette in it.
b) 360 KB drive -300 rpm.
c) 720 KB drive -300 rpm.
Allow for a tolerance of I% on all the speeds.
Ensure that the diskette is formatted before performing this test.
16
3.0 Random Read/Write Test - (Destructive)
This test performs a random read/write operation on the diskette & thus checks out the random seek capability of the drive.
-Again ensure that the diskette is formatted before performing this test.
4.0 Sequential Read/Write Test - (Destructive)
This test performs a Sequential read/write operation & checks out the se quential seek, read & write capability of the drive.
This test requires a formatted diskette.
5.0 Disk Change Line Test - (Non-destructive)
This test is valid only for drives with the disk change line feature namely
- 1.2 Mb drive
- 720 Kb or 3 1/2" drive.
This test checks whether the status of the disk change line changes when the diskette is removed/inserted in the drive.
This test requires a for matted diskette.
17
Keyboard Diagnostics
There are two types of diagnostics performed on the keyboard/keyboard controller.
"They are : a) Controller Test.
b) Scan/ ASCII Code Test.
1.0 Controller Test
This test exercises the keyboard controller & the keyboard status flags & takes about 2 minutes. Any error resulting from this test is reported.
Observe the CAPS, NUM & SCROLL LED's going on & off during the course of this test. ·
2.0 Scan / ASCII Code Test
Upon invoking this test a keyboard layout is shown on the screen. This keyboard layout might not necessarily correspond with your keyboard.
The objective of this test is to determine whether the keys depressed match with their scan code.
Thus every time a key is depressed the scan code & the ASCII code of the key is shown.
Use <CNTRL><BREAK> key to abort this test.
Function keys 11 & 12 in an Enhanced keyboard cannot be checked out by this test.
18
Video Diagnostics
Video diagnostics includes the following : a) Sync Test l:>) Adapter Test c) Attribute Test
-memory.
d) 80 x 25 Display Test the display adapter.
- Checks the Sync capability.
- Performs test on the Display Memory.
- Checks the attributes of the Display
- Checks the 80 x 25 character set of
The video diagnostics requires very little input & the results can be visually observed.
19
Miscellaneous Diagnostics
This includes the following tests :
-a) Serial Communication Port Test.
b) Printer Port Test.
1.0 Serial Communication Port Test
This test requires a special RS-232C connector to be plugged on port.
The details of this connector are as below :
- RD & TD Shorted.
- DSR & DTR Shorted.
- CTS & RTS Shorted.
This test exercises t�e port for different :
- Baud Rates
- 7 Bit
I
8 Bit &
- Odd / Even Parity
The results of the test are shown on the screen. to the
2.0 Printer Port Test
This test writes a pattern on the Printer & the results are the Printer. observed on
20
Appendix A
1.0 Interleave Factor - What is it ?
To· understand the meaning of shall take you thru' an analogy. when we finish the analogy.
Interleave associated with Hard Disks, we
We hope we have made the meaning clear
Consider the game of a roulette where a round table 1s set in motion & people wait for the motion to stop on their lucky number.
We shall add a slight twist to this game.
Assume we have 17 sectors on the roulette round table & that we have 17 coins numbered & stacked up in the order l thru' 17 with coin 1 at the top.
We shall now set the round table in motion at a reasonable speed & give ourselves the task of placing the coin from the stack pile on every sector taking the minimum time and remaining static at one place during the cou rse of the game.
Assume you have placed coin 1 in a certain sector. By the time you pick up the next coin & place it, the immediate sector following coin I would have passed you. So what you would then do, is to place it on the sector just passing by.
Thus after placing the coins in all the sectors, you should stop the roulette table & look at coins numbers in the contiguous sectors.
You are sure to find that they are not in an increasing order. You soon realise that this disorder is due to the fact that the game requires you to place all the coins in minimum time.
If you had wanted the coins in an order, you would have had to wait for at least 17 revolutions before placing all the coins.
The average number of contiguous sectors between a sector occupied by coin 'n' & by coin 'n+ l' can be termed as Interleave factor.
In this analogy the Hard Disk is the roulette table in motion at a constant speed of 3600 rpm & the person can be visualised as the head & the related data transfer hardware.
Information is organised in sectors & the sectors are accesed by their num bers. Thus using a specific interleave to number the sectors helps in achie ving a data tansfer rate change.
21
For a Hard disk with factory specified access times, the only factor in the control of the user is the Interleave factor.
We realise this & we have the Auto Interleave feature which does exactly this.
Thus it is important that the value chosen gives the best performance.
2-22
22
Appendix -B
Please turn over for Appendix - B.
2-23 23
---------------------------------------------------
Type Cylinders Heads Write-precomp Landing-zone
5
6
7
8
1
2
3
4
306
615
615
940
940
615
4
4
6
8
128
300
300
512
512
305
615
615
940
10 ?viB
21 MB
31 MB
64 ?viB
48 MB
21 MB
31 MB
3111B
11
12
900
820
855
855
5
7
8
7
8
5
15
3
0
4
5
7
NONE
128
NONE
000
ALL CYLS.
300
NONE
512
300
511
733
901
820
855
319
733
000
21 MB
36 11B
51 MB
21 11B
44 MB
00 MB 15
16
17
18
000
612
977
977
19 1024
20
733
733
23
24
306
925
40
41
42
43
44
45
46
29
30
823
918
31
32
1024
33
34
35
1024
612
36
37
1024
615
987
987
820
977
981
830
000
7
5
4
7
300
ALL CYLS.
ALL CYLS.
NONE
977
1023
925
925
754
699
823
918
1024
1024
58 MB
61 MB
72MB
46 MB
72 MB
1vfl3
71 MB
55
5
2
8
3
7
6
5
5
7
IO
15
00
NONE
987
987
977
512
1024
1024
615
987
918
10 MB
80 MB
71 MB
42 MB
25 MB
60 MB
42 MB
50 MB
72 MB
115 MB
---------------------------------------------------
2-24
24
AMl-386XT SERIES-4 MANUAL
American Megatrends, Inc.
Ph. (404) 263-8181
4025 Pleasantdale Road
Suite 350, Atlanta, GA 30340
CONTENTS
Section - 1
Section - 2
Section - 3 _
Section - 4
Section - 5
Section - 6
Introduction to The Manual
Unpacking and Installation
BIOS Overview
System Overview
Technical Specifications
I/0 Channel & Connector Specifications
Advanced ROM Diagnostics
Important Notice
AMI is not responsible for any errors or omissions in writing this manual. AMI reserves the right to change, modify or append any part or section of this manual at any time.
Introduction to The Manual
Section - 1 It is essential to go through this section and follow the instructions for proper installation of the board.
Section - 2
Section - 3
Section - 4
Section - 5
Section - 6
It is essential to go through this section to familiarize yourself with the AMI-386 BIOS.
You are advised to go through this section to familiarize yourself with the motherboard.
You may skip this section unless you need detailed technical information. All port descriptions required for personalized software developement are given in this section.
You may skip this section if you are familiar with the IBM A T 1 I/0 Channel and Connector
Specifications.
Read this section to get the information about the built-in Advanced Diagnostics features.
1 IBM AT is a registered trademark of International Business
Machine Corporation.
SECTION - 1
Unpacking ar:id Installation
1.1 Unpacking the AMT-386XT Motherboard
Your AMI=:386XT motherboard contains sensitive components, which can be easily damaged by static electricity. electroni:::
In this section, we describe the precautions you should take. while unpacking, as well as during installation. It is very important that the instructions be followed correctly, to avoid static damage, and to success[ ully install the board.
1) The motherboard should be left in its original packing until the time when it is to be installed.
2) Unpacking and installation should be done on a ground connected anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.
( A cheaper solution is to use a sheet of conductive aluminum foil grounded through a 1 Mega-ohm resistor, instead of the anti-static mat. Similarly, a strip of conductive aluminum foil wrapped round the wrist and grounded through a 1 Mega-ohm resister will serve the purpose of a wrist-band. )
Inspect the cardboard carton for obvious damage. In case damage is detected, call us, we are ready to help you.
Inside the carton, the card is packed in an anti-static bag, and sandwiched between sheets of sponge. Remove the sponge and lift out the anti-static bag with the card. Extract the card and place it ONLY ON A GROUNDED ANTI-STATIC SURFACE component side up.
Save the original packing materials, in case the card has to be shipped again. Shipping it in any other type of packing may damage the card.
Again inspect the card for damage. Press down all the ICs mounted on sockets to make sure they are properly seated.
DO NOT APPLY POWER TO THE BOARD IF IT HAS BEEN
DAMAGED.
You are now ready to install your AMI-386XT motherboard.
1-1
Section 1
Mounting the Motherboard in the chassis.
Before attempting to mount the board in the chassis, take a look at
Fig.I to aquaint yourself with the locations of stand-offs and mounting screws. ( Stand-offs and mounting screws are supplied with the chassis and NOT WITH THE MOTHERBOARD. )
Note: The· mounting hole pattern on interchangable with that of the IBM assumed that the chassis is designed motherboard mounting.1
AMI-386XT motherboard is
AT /XT motherboard. It is for standard IBM AT /XT
CAUTION: During mounting and installation static protection is to be maintained as during unpacking.
Place the chassis on the anti-static mat and remove the cover.
Take the plastic clips, nylon stand-offs and screws, for mounting the motherboard, and keep them separate. ( Look into the chassis manufacturers booklet for instructions. )
The chassis has to be connected to ground to a void static damage to the board, while mounting. To ground the chassis, connect an alligator clip with a wire lead to any unpainted part of the chassis.
Ground the other end of the lead at the same point as the mat and the wristband. Rotate the chassis so that the front is to your right and the rear to your left. The side facing you is where the motherboard is to be mounted and the power supply will be mounted on the far side.
Take the four nylon stand-offs and provided for them in the motherboard side. The stand-offs will lock in place. push them into the holes see Fig. I ) from the solder
On the chassis, locate the slots where the stand-offs go in. Now, hold the motherboard ( component side up ) with the edge with three stand-offs towards you, and the edge with no stand-offs, away from you. ( The edge connectors on the motherboard, for the adaptor cards, should be on your left.) Carefully slide the board into the chassis, making sure that the stand-offs go into the slots provided for them ( see Fig. II ). If the stand-offs are properly locked, the board should not slide right or left ( forwards
1 IBM
AT
Machine Corporation.
1-2 is a registered trademark of International Business
Section 1 and backwards with respect to the chassis ) and should be level with the chassis. The far edge of the board should fit into the slots in the plastic clips. In c2se the board is not sitting proper! y,
SLIDE IT OUT COMPLETELY and try again.
Now, put fhe two motherboard mounting screws in the holes provided for them ( Fig. I ) and tighten them. ( You may have to shift the board slightly to align the screw mounting holes on the motherboard with those on the chassis. )
Now that the motherboard is p:.operly mounted, the connectors have to be put in and the option jumpers and DIP switches set to your requirement.
Figure III gives you the positions of jumpers and the DIP switches on the describes the options that can be selected. the connectors, the option card. The following table
NOTE: The options are factory set to the default selections and these options are indicated in the table by underscoring.
1.3 List of Jumper Options and Switch Settings for AMI-386XT
J l: TURBO LED
J2: 2 pin BERG strip
When shorted gives hard rese� to the system
J 4: 3 pin single in line .
Short 1-2 if using 32K X 8 EPROMs (eg. 27256)
Short 2-3 if using 16K X 8 or SK X 8 EPROM's (eg '.1.7128 or 2764)
J 19: 4 pin single-in-line BERG
Speaker Connector
J20: 5 pin single-in-line BERG
Keyboard Lock Connector
J21: 4 pin single-in-line BERG
Battery Connector for RTC/CMOS
J22: 5 pin DIN socket
Keyboard Connector
J23-28: 62 pin I/0 Connectors
J31-34: 36 pin I/0 Connectors
1-3
Section 1
139: 80 pin 1/0 Connector for 32 bit memory
PS8-9: 6 pin Power Supply Connectors
SW: 5 bit slide switch
5
4
3
2
.Video adapter card option
Power on system clock frequency
Numeric processor option
5 l 2k to 640k cache on/off option
On board EGA BIOS option
J-4
Sec1ion I
SWl
ON-BOARD EGA BIOS OPTION
ON/OFF EPROM MAP DESCRIPTION
ON OCOOOO-OC7FFF On Board EGA BIOS enabled(32 bit
OFOOOO-OFFFFF access)
OFF OEOOOO-OFFFFF BIOS On EGA Card selected(8 bit access)
SW2
512K TO 640K CACHE ON/OFF OPTION
ON/OFF DESCRIPTION
ON
.OFF
If 512KB below lMB option is selected in 32bit memory card then 512KB to 640KB memory on the
1/0 expansion BUS will be cached if present
If 512KB below lMB option is selected in the 32bit memory card then 512KB to 640KB memory on the
1/0 expansion BUS will not be cached. All other memory will be cached.
SW3
80387 NUMERIC PROCESSOR PRESENT /NOT PRESENT
OPTION
ON/OFF DESCRIPTION
ON
OFF
Numeric coprocessor physically not present on the board. This switch should always be on when the numeric processor is not present.
80 387 is physic2lly present on the board.
1-5
Section 1
SW4
POWER-ON SYSTEM CLOCK FREQUENCY SELECTION
ON/OFF D�SCRIPTION
ON
OFF
·POWER ON System clock frequency
However the clock can be changed to is 6�1Hz.
16 MHz using keyboard clock switching option.
POWER ON System clock frequency is l 61v1Hz
SW5
VIDEO ADAPTER CARD OPTION
ON/OFF VIDEO ADAPTER CARD
ON
OFF
COLOR GRAPHICS CARD
MONOCHROME DISPLAY ADAPTER
C35: Variable Capacitor
The system board has a variable capacitor. Its purpose is to adjust the 14.31818 1v1Hz oscillator (OSC) signal that is used to obtain the color burst signal required for color televisions.
MEMORY BOARD SWITCH SETTING
SWITCH OPTION ST A TE DESCRIPTION
SWl
SW2
SW3
BANK SELECT ON
OFF
MEMORY SIZE ON
BELOW l MB OFF
384KB MEMORY ON
ABOVE lMB OR OFF
211B
Two 32bit memory bank present
One 32bit memory bank present
640K below
512K below IMB
Enable
Disable
1-6
SECTION 2
BIOS Overview
This guide explains how to : a) Install the AMF-386 BIOS on the AMI-386 Motherboard.
b) Use the buift�in Set-up Procedure.
c) Select the Clock Speed / Wait States through the Keyboard.
d) Interpret the errors reported by the AMI-BIOS.
e) Use the 3 1/2" floppy drive support effectively.
2.A Installing the AMI-386 BIOS
Skip this paragraph if the BIOS is already plugged on the A1v1l-386XT
Board.
Before you begin the installation ensure the following: i ) The Board is powered down. ii) ROM's are susceptible to static electricity. So observe· the following precautions when you handle a ROM : a) Unpack the ROM's on a ground connected anti-static mat.
b) Wear an anti-static wristband, grounded at the same point as the anti-static mat.
(A cheaper solution is to use a sheet of conductive aluminium foil grouded through a I Mega-ohm resistor instead of an anti-static mat. Similarly, a strip of conductive aluminium foil wrapped around the wrist and grounded through a I Megaohm resister will serve the purpose of a wrist band.)
Now follow the steps below:
- Unpack the ROM's and identify the Labels 386-0, 386-1, 386-2 and 386-3.
- Locate the IC Sockets U70, U7 l, U72 and U73 on the 386
Motherboard.
- Plug in the following order :
- ROM with label 386-0 in U70 socket,
- ROM with label 386-1 in U71 socket,
- ROM with label 386-2 in U72 socket,
- ROM with label 386-3 in U73 socket.
When you do these make sure that the notch on the ROM is facing 2w2y from the I/0 connector.
2-1
Section 2
2.A.l Starting Up The System
Follow the procedure recommended in Section 1 of the Hardware manual.
Power up the system and wait for the BIOS to show up the BIOS activity on the screen.
2.A.2 Memory Test Bypass
The BIOS performs diagnostics of the system and displays the size of the memory being tested.
Note that you can bypass the memory test by pressing the <ESC> key.
This option would be quite useful when the memory on the system is quite large. You should hit the <ESC> key when the message Press <ESC> Key to bypass MEMORY test appears on the screen.
Also note the Ref. number at the bottom of the screen. Make a note of this number before you call Customer Support at AMI for assistance with the BIOS.
Cache Test
The 386-BIOS as a part of its diagnostics tests the cache memory. The
BIOS also displays the size and status of the cache memory on the screen.
This display can be seen on the second line just past the memory size display.
The size of the cache memory is usually 64 KB. In case the cache memory is found bad then the BIOS alarms the user with the following message:
CACHE MEMORY BAD - DO NOT ENABLE CACHE
Refer to Section
The discussion on section 3.1.
2.C for more in for ma rion about enabling/disabling cache.
the advantages of cache can be found in the Hardware
2.B CMOS Setup
Immediately after the memory and cache test, you will get the following prompt on the screen :
Press <DEL> key to run SETUP Utility
2-2
Section 2
Hit <DEL> key to get into the Setup, Mode. Note that <DEL> key will get you into the set-up mode only when the message :
Press <DEL> key to run SETUP Utility, is displayed on the screen.
If you hit <DEL> key the following message appears on the screen:·
WANT TO RU� StTUP UTILITY (Y /N)?
If you hit <Y> or <y> and the <ENTER> key you have the Setup screen.
2.B.l Time/Date Setup
The Setup screen looks like below :
CMOS S E T U P
Curret date is : XX-XX-XXXX
Enter new date (MM-DD-YYYY)?
To this question you would have to enter the date in the format shown on the screen.
If you feel that the current date should remain unchanged, you would just have to hit the <ENTER> key. In such a case the new date is set to the same value as the current date.
The next question you have on the screen is:
Current time is :XX:XX:XX
Enter new time (HH:MM:SS)?
To this question you key in the time rn the format defined.
<ENTER> key alone if the current time is right.
Press
As soon as you have done this the BIOS shows you the type of the display on your system.
After that, the setup takes two differet paths depending upon the CMOS being initialized or uninitialized.
2-3
Section 2
2.B.2 CMOS Initialized
Under these conditions you would see the following messages :
Fixed disk drive C type
Fixed disk drive .D": type
: X (if installed else Not Installed.)
: X
(if installed else Not Installed.)
Diskette drive A is 3 1/2"
Diskette drive B is Double Sided (Other options as above)
Base Memory Size is :
Expansion memory size is :
XXX
KB
XXXX
KB
Are these options correct (Y /N)?
Note that the information about Drive A indicates 3 1/2", as CMOS had been set earlier to reflect this status. If on the contrary, CMOS had been set for a 1.2 MB drive, the message in place of 3-1/2" it would be High
Capacity.
If you feel that the information displayed above is right, hit <Y> and the
<ENTER> key to proceed to system boot with the new information.
2.B.3 CMOS Uninitialised
2.B.3.1 Disk Drive Type Definition
In this case you would have to enter the type of the fixed Drive C rn response to the message :
****
WARNING
****
Entering the wrong disk drive TYPE causes improper operation of the disk.
If disk not installed press <RETURN>
For disk TYPE details press <ESC>
Enter disk drive C type (l-47)?
Note that the disk type details are only a key stroke away. Hit <ESC> key to find for yourself. You could always come back by hitting <ESC> again.
Once you have convinced yourself about the drive type enter the appropr iate number and hit <ENTER>.
You would then be asked to enter the type of the disk Drive D. The proc edure for doing this is the same as that for Drive C. Remember if you do not have disk Drive D on your system, you just have to hit the <ENTER>
2-4
key. Section 2
2-5
Section 2
---------------------------------------------------
---------------------------------------------------
9
10
11
12
13
14
5
6
7
8
3
4
1
2
I7
18
19
000
612
977
977
306
615
615 ·-:
940
940
615
462
733
900
820
855
855
22
23
26
27
925
925
754
754
699
823
30
31
918
32
;) .)
1024
34
35
612
36 1024
6
4
8
5
15
3
8
7
7
11
15
5
4
4
5
7
5
4
4
5
7
7
7
9
7 l l
128
300
300
512
512
512
300
ALL CYLS.
ALL CYLS.
NONE
NOKE
128
733
000
663
977
977
1023
732
732
733
336
925
754
754
_.,
918
1024
305
615
615
940
940
615
511
733
901
820
855
855
1024
6i2
10 MB
56 MB
72 MB
46 MB
71 MB
55
98 MB
133 MB
38
39
42
44
977
981
7
6
5
5
9
8
8
3
7
10
15
00
820
977 977
981
830
830
---------------------------------------------------
10 MB
21 MB
31 MB
64 MB
48 MB
21 MB
31 MB
115 MB
21 MB
36 MB
51 MB
21 MB
44 MB
00 MB
21 :MB
42 MB
58 MB
61 MB
31 MB
42 MB
2-6
Section 2
Diskette drive A is 3 1/2" (Y /N)?
The above question is asked if the drive has been found to have 80 tracks.
Since a drive with 80 tracks could either be a
- high capacity i.e 1.2 MB drive
- or 3 I /2" i.e · 720 KB drive, you would have to answer this question.
By entering <N> or <n> you can select the high capacity drive. Alternative ly enter <Y> o r <y> to select a 720 KB drive. This question could come up for the case of drive B as well provided it has been detected as a 80 track drive by the BIOS.
If you hit the <ENTER> key alone, the BIOS assumes the drive to be a 1.2
MB drive.
At this point you have entered all the information the BIOS requires for starting up the system.
BIOS detects a few details by itself, e.g. the diskette drive type in case of a 360 KB drive as shown below:
Diskette drive B is : Double Sided (Other options as above)
Base Memory Size is : XXX KB
Expan�ion memory size is : XXXX KB
Are these options correct (Y /N)?
If you are convinced at this stage that all the information you have entered upto this point is right, hit <Y> or <y> key followed by <ENTER> key.
When you do this the BIOS goes all over again to boot up the system with the information specified.
However, if you would like to modify some information, then you sJ-.ould hit either <N> or <n> key followed by enter. You would now go through the setup all over again.
2.B.4 Summarv of Set-up
The Set-up screen thus requires you to set a) Date.
b) Time.
c) Hard Disk Type For Drive C (if present).
d) Hard Disk Type For Drive D (if present).
2-7
Section 2
The Set-up procedure also automatically detects the fallowing: a) Type Of Display Card.
b) Size Of Real Memory.
c) Size of Memory beyond l MB.
d) Presence of 360 kb floppy drives.
e) Presence of a 88387.
Also, if a second Hard Disk drive is physically connected but the CMOS is not set for this Drive D, the BIOS informs you about the same and gives you a chance to configure the drive through SETUP.
Having setup the CMOS, the BIOS runs through the diagnostics again, tests the memory, sets up the devices configured and proceeds to boot.
Note that the Set-up option is available even after a soft reset.
2.B.5 When does the BIOS prompt vou to run Set-up?
The BIOS prompts you to run Set-up under the following conditions : a) CMOS options not set.
b) Display Configuration Mismatch.
c) Memory Size mismatch.
d) Hard Disk Set-up error.
e) CMOS battery is low.
f) An additional hard disk presence is detected.
2.C Selecting Clock Sneed/Wait States
AMI-BIOS allows you to change Clock Speeds and Wait States through the keyboard at any time. Following are the key combinations and their mean mgs :-
Kev Combinations
1. <CNTRL><AL T><-;.>
Meaning
Switch to 16Mhz, 0 Wait State -
Block Cursor indicates the switch over.
2. <CNTRL><ALT><-> Switch to 6Mhz, 1 Wait State -
Double-line Cursor indicates the switch over.
3. <CNTRL><ALT><L-SHIFT><+> Select Zero ·wait State.(Enable
Cache) - only at J 6MHz.
4. <CNTRL><ALT><L-SHIFT><-> Select One Wait State.(Disable
Cache)
At the time of diagnostics the BIOS tests the cache memory. If the cache test fails, the
BIOS does not allow the user to enable cache through the key combination.
2-8
Sec1ion 2
2.C.l Default Settings for Clock and Cach.e
Note that the speed of the system after power-on can be set by a DIP switch SW7. The details of the same can be had under Section 1.3. If the switch is on, the system boots up at 6 MHz with the cache disabled. If it is off, the system boots up at 16 :t-.lliz with the cache enabled. If the power-on cache self-test fails, the cache is not enabled, even when the system boots at 16 MHz.
The system returns to this default state after soft reset (warm boo�). Note that during a WARM boot the cache memory is not tested.
2.C.2 Low Level Programs for Clock/Cache Selection
The low level programs discussed below will have to be executed under DOS
DEBUG program. The user should be familiar with low level programming before he/she attempts the programs given below. a) Port Definitions : Clock and cache are selected using the fallowing i/o ports:-
CLOCK selection port Address : 0461H
CACHE selection port Address : 0460H
Bit Map : In case of both the ports mentioned above the LSB status (Least
Significant Bit· i.e BIT 0) determines the selection. The remaining 7 bits i.e
BIT l thru BIT 7 are don't care.
B7 B6 BS B4 B3 B2 Bl BO
X X X X X X X LSB
Port 461 LSB: 0 -> 6 MHz
1 -> 16 MHz
Port 460 LSB: 0 -> Disable cache
1 -> Enable cache b) Selecting High or 16 MHz Speed: Under DEBUG prompt - enter the fol lowing command:
-0 461,1 <ENTER> c) Selecting Low or 6 MHz Speed: Under DEBUG prompt - enter the following command:
-0 461,0 <ENTER> d) Status Of Clock: Under DEBUG prompt - enter the following command:
-I 461 <ENTER>
2-9
Section 2 xx
In response the port status clock speed can be found.
6 MHz. is returned in XX. Looking at the LSB the
If the LSB is set the speed is 16:rvfHz else it is e) Enabling the �ache: Enable CACHE using the low level command shown below only after confirming that the cache is good. The As described earlier, the cache status is displayed by the BIOS after power-on.
Under DEBUG prompt enter the following command:
-0 460 l<ENTER> f) Disabling the Cache: Under DEBUG prompt enter the following command:
-0 460 O<ENTER> g) Status Of Cache: Under DEBUG prompt - enter the following command: xx
In response the port status is returned in XX. Looking at the LSB the cache status can be found. If the LSB is set the cache is enabled else it is disabled.
2.D Errors Reported Bv AMI-BIOS
AMI-BIOS performs various diagnostic tests at the time the system is powe red up. Whenever an error is encountered during these tests, either you hear a few short beeps or see an error display on your monitor. If the error occurs before the display device is initialised the system reports the error by giving a number of short beeps.
If the error is FAT AL then system halts after reporting the FAT AL error.
If the error is NON-FATAL the process continues after reporting the NON
-FATAL error.
2-10
Section 2
Fatal Errors
Beep Count Meaning
1
2
DRAM::refresh failure .
Pari�y Circuit failure.
3 Base 64KB RAM failure.
4 System Timer failure.
5 Processor Failure.
6 Keyboard Controller - Gate A20 error.
7 Virtual Mode Exception Error.
8
9
Display Memory R/W Test Failure. (*)
ROM-BIOS CheckSum Failure.
(*) Non-Fatal Error.
Error Messages
Fatal Errors l.
Channel - 2 of Timer Not functional.
2. Stray Interrupt sensed in controller.
3.
Interrupt controller #2 not functional.
Non-Fatal Errors
1. Keyboard Error.
2.
Keyboard/Interface Error.
3.
CMOS battery state low.
4.
CMOS system options not set.
5. CMOS checksum failure.
6.
CMOS memory size mismatch.
7.
CMOS system time and date not set.
8.
CMOS display configuration mismatch.
9.
Display setting not proper.
10. Keyboard is locked ..... Unlock it.
11. Floppy disk controller failure.
12. Hard disk unit O error.
13. Hard disk unit 1 error.
14. Hard disk unit O failure.
15. Hard disk unit I failure.
16. Hard disk unit 1 is not defined in CMOS.
17. Cache Memory Bad - Do Not Enable Cache.
2.E Use of 3 1 /2" Support Effecth·elv
DOS 3.20 provides support for support from the ROM BIOS. provides the necessary support.
3 1/2" drives. For this
AMI-BIOS release date purpose
12/03/86 it needs onwards
2-11
· Section 2
The 3 1/2" drive can be freely configured as Drive A or Drive B with ,his
BIOS. Thus it is possible to boot off direc't!y from a
3 I /2" drive.
Earlier versions of DOS would require the use of DRIVER.SYS to provide the necessary s�pport.
A few points would have to be kept in mind when you use the
3 1/2" drive and a 1.2 MB together. Ensure that when you perform the
Setup you define the drives correctly. Incorrect definition could make the drive unusable.
The table below describes the valid combinations on a AT:
CMOS Status Physical Drive Status Functional
1.2 MB
3 1/2"
1.2 MB
3 1/2"
Undefined 1.2 MB YES
YES
YES
The remaining corn bin a tions are in valid. binations before you call us for help.
Please make a note of these com-
2-12
SECTION 3
System Overview
3.1 Description
The system \)Oard is approximately 8.5 by 13 inches large sca1e integration (VLSI) technology. It has features:
*
80386 Microprocessor and uses very the following
* 16 MHz System Clock
*
Optional 80387 Numeric Coprocessor (6/16MHz)
*
System support function:
-7 Channel Direct Memory Access (DMA)
-16 level interrupt
-Three programmable timers
-System clock
* User selectable 64KB/128KB read only memory (ROM) subsystem
*
64KB Cache Memory which caches 16MB memory address space
*
User selectable synchronized system board clock switching option for reducing the processor clock frequency to 6MHz
*
8MHz I/0 bus timing compatibility at 16MHz board operation
* Speaker attachment
* Complementary Metal Oxide Semiconductor (CMOS) RAM to maintain system configuration
* Real-Time clock
*
Battery backup for CMOS configuration table and Real-Time
Clock
* Keyboard attachment
*
8.5 by 13 inch board:Extended XT 1 form-factor
* 6 input/output (1/0) slots:
- 4 with a 62 + 36 pin card-edge socket
- l with only the 62-pin card-edge socket
- l 32bit memory slot
3-1
Section 3
3.2 The Microprocessor
The 80386 is a high performance 32-bit microprocessor designed for
Multitasking ·: operating systems. The processor can address up to
4-Gigabytes of physical memory and 64-Terabytes (1-Terabyte = 1-K
Gigabyte) of virtual memory (this design limits the physical address to 16:MB). It has integrated memory management and protection architecture which includes address translation registers, advanced multitasking hardware and protection mechanism to support operating systems. In addition, it is object code compatible with
8086 family of microprocessor. The 80386 has built-in features to support coprocessors, DMA and interrupts (both maskable and non-maskable). It has two modes of operation: Real address mode and Protected virtual address mode.
In real address mode it operates as a fast 8086 with 32-bit extension if desired. In Protected mode, software can perform a task switch into tasks designated as virtual 8086 mode tasks. The virtual 8086 tasks can be isolated and protected from one another by the use of paging and I/0 permission bit map.
3.3 Svstem Performance
Clock Speed
The AMI-386XT can operate at 16MHz, which results rn a clock cycle time of 62.5ns. It can run at two different clock rates. The lower clock speed is normally 6 or 8MHz. For convenience, we shall assume this speed to be 6MHz throughout the rest of this manual. If the oscillator U 111 on the board is l 6MHz instead of
12MHz, all the 6MHz timing will have to be reduced by 25%.
Similarly, if Y 1 is something other than 32MHz, the l 6MHz timings will have to be appropriately rated.
The switch SW-4 determines the initial clock frequency after power-on. Refer to Section 1.3 for details. The clock speed can be switched at any time when the machine is operating. Refer to
Section 2.C for details.
The 80387 Numeric processor runs at the processor clo2k frequency.
Data Access: Bus Width
The 80386 microprocessor supports two types of accesses: Memory, and Input/Output. Each type of access can be 32-, 24-, 16- or
8-bit wide. The memory and I/0 devices are 32, 16 or 8 bit wide.
The AMI-386 allows any type of access to a device of any width.
If necessary, the hardware will split a 80386 bus cycle into a
3-2
Section 3 number of (upto 32 / 8 = 4) cycles to allow access to a l 6- or
8-bit device. All the on-board' devices in the memory space is organized 32-bit wide. These include the on-board DRAM, the high-speed Cache memory and the EPROM containing the BIOS. All the on-board I/0 devices are 8-bit wide, with the exception of the
80387 math c(;lprocessor which is a 32-bit device.
The AMl-386XT can support 16- and 8-bit memory and I/0 devices on the I/0 slots.
The m�mory space from address OCOOOO thru OC7FFF is reserved for I/0 slot ROM Most often, only the EGA BIOS
(OCOOOO-OC3FFF), which is accessed through a 8-bit bus, is located in this area. The slow execution of this device driver makes the video I/0 sluggish. The AMJ-386 provides the option of mapping this space into the 32 bit system board EPROM The board is shipped with the A:tvfi EGA compatible BIOS in the system board
EPROM, which maps into the required memory space if SWI is ON.
Refer to Section 1.3 for SWl setting. This improves the video r;o speed, since the EGA BIOS can now be accessed through a 32-bit bus. When SWl is ON, there should not be any I/0 slot 16-bit memory in the address space OCOOOO thru OC7FFF. Also, any I/0 slot 8-bit memory in that space will be automatically disabled.
Cache and DRAM access
In 80386, a zero wait-state bus cycle requires two clock cycles.
The required number of clock cycles increases by one with every wait-state introduced m the access. memory read operations.
Most processor accesses are
To speed up the memory reads, the
AMI-386 incorporates 64KB of 32-bit w10e directly mapped cache, realized with high-speed Static RAM The cache has byte granularity and a page size of 4 bytes and is implemented with a write-tnru algorithm. At 16MHz, with the cache enabled, 81% of data will be available in the cache for memory read operations (this is a statistical value for normal program execution). This improves system speed about twofold, since the cache access requires no wait states, whereas the main memory access would require at least two.
A point to note is that, even the off-board (I/0 slot not 32bit memory slot) memory is cached. Hence most read operations, even from a slow off-board memory, will have no wait states. As a result, the speed and bus width of the expansion memory will hardiy affect the system speed. memory always takes longer to access
However, since an off-board
3-3
Section 3 than the 32 bit memory on the 32bit sfot, it is always a good idea to utilize the 32bit memory to its full capacity before resorting to add-on memory boards. Ref er to Section 1.3 for 32bi t memory switch settings.
Refer to Section. 2.C and 3.7 for information on how to enable and disable the cache.
Data Access: Cycle times
The following table gives the number of wait states and the total bus cycle times for different cases of Cache and on-board DRAM access:-
Access Type
6MHz wait states time
(ns)
16MHz wait states time
(ns)
0
125 Memory Read:
Cache hit
DRAM Read:
Cache disable
DRAM Read:
Cache miss
500
500
2
3
250
312.5
500 2 250
The table below lists the number of wait states and processor access times for on-board EPROM, 1/0 and off-board accesses:-
Access type
16-bit device
8-bit access to 8-bit device
16-bit access to 8-bit device
6MHz wait states
16MHz
(MEMW,IORD) time wait
(ns) states time
(ns)
4
10
500
1000
2000
5
10
22
437.5
750
1500
16MHz
(!vfEMR,I O WR) wait states time
(ns)
6
J 1
500
812.5
24 1625
3-4
Section 3
Refresh Controller and DMA Timing
The refresh controller operates at 6 or' 8 MHz for processor clock of 6 or 16:MI-Iz respectively. Each refresh cycle requires 5 clock cycles to refresh all the DRAM in the sysytem. 256 refresh cycles are required every 4 ms.
The DM.A.: .controller operates at 3 or 4 MHz for CPU clock of 6 or
16 MHz respectively. All DMA transfer bus cycles are 5 clock cycles Jong, which results in a cycle time of 1660 or 1250 ns. l.XT is a registered trademark of IBM Corp.
3-5
SECTION - 4
Technical Specifications
4.1 32bit
DRAM
memory map
MEMORY MEMORY
-------------------------------------------------
OFF OFF OFF 512K
OFF ON OFF 640K
OFF ON ON 640K
ON OFF OFF 512K
ON ON OFF 640K
ON
ON
ON 640K
NIL
Nil
384K
1024K
1024K
1408K
4-1
Section 4
--------------------------------------------------
--------------------------------------------------
OAOOOO 128KB video RAM
Function
Reserved for graphics
- OBFFFF display buff er
ocoooo
- OC7FFF
OC8000
-OCFFFF
32KB of ROM
32KB of ROM
SWI OFF: adapter card
ROM
SWl ON: system board
ROM
Rserved for ROM on I/0 adapter cards
ODOOOO
-ODFFFF
OEOOOO
- OEFFFF
OFOOOO
- OFFFFF
Address from the end of system board memory to
FDFFFF
FEOOOO
- FEFFFF
64KB I/0 expansion
ROM
64KB ROM available on system board if
SW5 is OFF
64KB ROM on the system board
FFOOOO
- FFFFFF
64KB ROM on the system board
Reserved for ROM on
I/0 adapter cards
Duplicate code assignmen t at address
FEOOOO-FEFFFF
Duplicate code assignment at address
FFOOOO-FFFFFF
I/0 channel memory
Duplicate code assignment at address
OEOOOO-OEFFFF
Duplicate code assignment at address
OFOOOO-OFFFFF
4-2
Section 4
4.2 I/0 Address Map
I/0 address hex 000 to OFF are reserved for the system board I/0.
The system board I/0 map is as follows:-
Address Rang-;e Device
000-0IF
020-03F
040-0SF
060-07F
080-09F
OAO-OBF
OCO-ODF
OEO-OFF
460-46F
DMA controller 1, 8237 A-5
Master Interrupt Controller, 8259A
Timer, 8254-2
Real time clock, NMI(non-maskable interrupt) mask and Keyboard Controller (8742)
DMA Page Register, 74LS612
Slave Interrupt Controller, 8259A
DMA Controller 2, 8237A-5
Math Coprocessor
Reserved for cache memory enable and system clock switching
I/0 address hex 100 to 3FF are available on the I/0 channels. The
I/0 slot address map is as follows:-
Address Range Device
IFO-IFF
200-207
278-27F
2F8-2FF
378·37F
380-38F
3A0-3AF
3B0-3BF
3C0-3CF
3D0-3DF
3F0-3F7
3F8-3FF
Fixed Disk
Game I/0
Parallel printer port 2
Serial port 2
Parallel printer port 1
SDLC, bisynchronous 2
Bisynchronous 1
Monochrome display and printer adapter
Enhanced Graphics Display adapter
Color Graphics Monitor adapter
Diskette Controller
Serial port l
4-3
Section 4
4.3 Svstem Timers
The system board has three programmable timer/counters controlled by 8254-2 timer /counter chip. The timer channels, defined as channel O through 2, are used as fallows:-
Channel O
Gate O
Clkin O
Clkout O
Channel
Gate 1
Clkin 1
Clkout 1
System timer
Always enabled
1.190 MHz clock
Interrupt controller IRQ O
Refresh Request Generator
Always enabled
1.190 MHz clock
Dynamic memory refresh request
Channel 2
Gate 2
6IH
Clkin 2
Clkout 2
Tone generation for speaker
Controlled by bit O of I/0 port address
1.190 MHz clock
Audio frequency output to speaker
Note: Channel 1 is program.med as a rate generator of 15 microsec ond period, to refresh all the DRAM in the system.
The output of Channel 2 is logically ANDed with bit l of the 1/0 port at address 61H to further modulate the output. The 8254-2 timer is programmed by the system through port address map is as shown:
40-43H.
The
Address
040
041
042
043
Register Select
Counter O
Counter 1
Counter 2
Control word register
4-4
Section 4
4.4 Svstem Interrupts
The system processor can be interrupted through Nl\11 (non maskable interrupt), as well as, through two 8259A interrupt controllers (CTLRI & CTLR2), which provide 16 levels of system interrupt. -�Any or all interrupt levels, including N·l\11, can be disabled. The following shows the interrupt level assignments in decreasing order of priority:-
---------------------------------------�----------
Nl\11 System board Dynamic Memory parity or I/0 channel Check
IRQ O
IRQ 1
IRQ 2
IRQ 3
IRQ 4 lRQ 5
IRQ 6 lRQ 7
IRQ 8
IRQ 9
IRQ 10
IRQ 11
IRQ 12
IRQ 13
IRQ 14
IRQ 15
Timer Channel O output
Keyboard Controller (output buff er full) interrupt
CTLR 2 interrupt to CTLR 1 for any interrupt on interrupt levels of CTLR 2
Real time clock Interrupt
Vertical retrace interrupt from video display adapter.
Software redirected to
INT OAH (IRQ 2)
Reserved
Reserved
Reserved
Coprocessor Interrupt for any error
Fixed Disk Controller
Reserved
Serial port 2
Serial port 1
Parallel port 2
Diskette Controller
Parallel port 1
The NMI can be disabled by writing into 1/0 port ?OH with bit 7 set and enabled by writing to 1/0 port 70H with bit 7 reset. There are two sources through which NMI can be generated: ( 1) System board dynamic RAM parity failure; (2) error reported by 1/0 channel adapter card through '-I/0 channel check (-IOCHCK) signal'. At power-on, the NMI and I/0-check are disabled. Before
Nl\11 is enabled, following steps should be taken:-
1. Write data in all system board and I/0 adapter memory locations; this will establish good parity at all locations.
4-5
Section 4
2.
Enable system board parity check (write into port 61H with data bit 2 set to zero).
3.
Enable I/0 channel check signal (write into port 61H with data bit 3 set to zero).
Note: All these functions are performed automatically by POST
(Power On Self Test)
The status bits (I/0 port 61H) indicate whether N111 is due to system-board parity check or I/0-check.
4.5 Description of I/0 read/write port 061H
Write port 6IH bit definitions
Bit O
Bit 1
Bit 2
Bit 3
Bit 4-7
Timer channel 2 GATE input control (I = GA TE is enabled)
Timer channel 2 OUTPUT control (] = OUPUT will go to audio speaker)
Enable system board parity check (O = Enable,
1 = Disable)
Enable I/0 channel check (0 = Enable, 1 =
Disable)
Not Used
Read port 6IH bit definitions
Bit O
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
'Timer channel 2 GA TE input control' bit
'Timer Channel 2 OUTPUT control' bit
'enable system board parity check' bit
'enable I/0 channel check' bit
System memory refresh determine signal
(should toggle at a time period of 30 microseconds if refresh happens properly)
Timer channel 2 OUTPUT
I/0 check signal (This bit will be set if there is any 1/0 channel check error)
System board RAM parity check signal
(This bit will be set if there is any system board dynamic memory parity failure)
4.6 Direct Memorv Access (DMA)
The system supports seven DMA channels, using four channels each of two 8237A DM.A.. controllers. DMA controller-I (l/0 address
000-0lFH) handles channel O to 3, which are capable of doing 8 bit data transfers between 8-bit 1/0 adapters and 8- or 16- bit system
4-6
Section 4
4.4 Svstem Interrupts
The system processor can be interrupted through NMI (non maskable interrupt), as well as, through two 8259A interrupt controllers (CTLRI & CTLR2), which provide J 6 levels of system interrupt. ·:Any or all interrupt levels, including NMI, can be disabled. The following shows the interrupt level assignments rn decreasing order of priority:-
-------------------------------------------------
NMI System board Dynamic Memory parity or 1/0 channel Check
IRQ O
IRQ I
IRQ 2
IRQ 3
IRQ 4
IRQ 5
IRQ 6
IRQ 7
IRQ 8
IRQ 9
IRQ JO
IRQ 11
IRQ 12
IRQ 13
IRQ 14
IRQ 15
Timer Channel O output
Keyboard Controller (output buff er full) interrupt
CTLR 2 interrupt to CTLR I for any interrupt on interrupt levels of CTLR 2
Real time clock Interrupt
Vertical retrace interrupt from video display adapter.
Software redirected to
INT OAH (IRQ 2)
Reserved
Reserved
Reserved
Coprocessor Interrupt for any error
Fixed Disk Controller
Reserved
Serial port 2
Serial port 1
Parallel port 2
Diskette Controller
Parallel port 1
The NMI can be disabled by writing into I/0 port 70H with bit 7 set and enabled by writing to I/0 port 70H with bit 7 reset. There are two sources through which NMI can be generated: (!) System board dynamic RAM parity failure; (2) error reported by I/0 channel adapter card through '-I/0 channel check (-IOCHCK) signal'. At power-on, the NMI and 1/0-check are disabled. Before
NMI is enabled, following steps should be taken:-
1. Write data in all system board and I/0 adapter memory locations; this will establish good parity at all locations.
4-5
Section 4
2.
Enable system board parity check (write into port 6IH with data bit 2 set to zero).
3.
Enable 1/0 channel check signal (write into port 61H with data bit 3 set to zero).
Note: All these functions are performed automatically by POST
(Power On Self Test)
The status bits (I/0 port 61H) indicate whether NMl is due to system-board parity check or I/0-check.
4.5 Description of I/0 read/write port 061H
Write port 6IH bit definitions
Bit O
Bit l
Bit 2
Bit 3
Bit 4-7
Timer channel 2 GATE input control (I = GA TE is enabled)
Timer channel 2 OUTPUT control (1 = OUPUT will go to audio speaker)
Enable system board parity check (0 = Enable,
1 = Disable)
Enable I/0 channel check (0 = Enable, I =
Disable)
Not Used
Read port 6IH bit definitions
Bit O
Bit l
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
'Timer channel 2 GATE input control' bit
'Timer Channel 2 OUTPUT control' bit
'enable system board parity check' bit
'enable 1/0 channel check' bit
System memory refresh determine signal
(should toggle at 2 time period of 30 microseconds if refresh happens properly)
Timer channel 2 OUTPUT
1/0 check signal (This bit will be set if there is any I/0 channel check error)
System board RAM parity check signal
(This bit will be set if there is any system board dynamic memory parity failure)
4.6 Direct Memorv Access (OMA}
The system supports seven DMA channels, usrng four channels each of two 8237A DMA controllers. DMA controller-I (I/0 address
000-0lFH) handles channel O to 3, which are capable of doing � bit data transfers between 8-bit 1/0 adapters and 8- or 16- bit system
4-6
Section 4 memory. Each channel can transfer data throughout the 16-megabyte system address space in 64KB blocks.
DMA controller 2 supports channel 4 through 7. Channel 4 is used to cascade DMA Controller I. Channel 5, 6 and 7 support 16 bit data transfer between 16-bit I/0 adapters and 16-bit syste:n memory. · . These channels can transfer data throughout the 16-meg abytes of address space in 128KB blocks. Channels 5, 6 and 7 cannot transfer data on odd byte boundaries.
The following table shows the address generation for the DMA channels. DMA page register supplies upper 8 bits of address for
CTLR l and 7 bits of address for CTLR 2.
----------------------------------------------------
Controller
----------------------------------------------------
1
DMA page register supplied
A23 through Al6
A23 through A 17
DMA controller supplied address
Al 5 through AO
-----------------------------------------------------
For Controller-I, byte high enable (BHE) signal is generated by inverting the signal AO. For Controller- 2, both AO and BHE are forced to logic 'O'.
The fallowing table shows the addresses for the page register:
-------------------------------
Page register I/0 hex address
DMA Channel O
DMA Channel 1
DMA Channel 2
DMA Channel 3
DMA Channel 5
DMA Channel 6
DMA Channel 7
Refresh
087
083
081
082
08B
089
08A
08F
For DMA Channels 5 thru 7, the page register data bits D7 through
Dl are loaded with address A23 thru Al7. Data bit D O of the page registers, for Channels 5 thru 7, is not used. Since DMA Channels
5 thru 7 do 16-bit data transfer, the count registers for these channels have to be loaded with half the transfer byte-count Also, the base address registers have to be loaded with the real address divided by 2.
4-7
Section 4
Following are the register addresses of DMA controllers I and 2:
Command Codes
CHO base and� current address
CHO base ·and current word count
CHI base and current address
CHI base and current word count
CH2 base and current address
CH2 base and current word count
CH3 base and current address
CH3 base and current word count
Read Status register/Write command register
Write request register
Write single mask register bit
Write mode register
Clear byte pointer flip flop
Read temporary register/Write master clear
Clear mask register
Write all mask register bits
000
001
002
003
004
005
006
007
008
Hex address for
CTLR I CTLR 2 oco
OC2
OC4
OC6
OC8
OCA occ
OCE
ODO
009
OOA
OOB
OD2
OD4
OD6 ooc
OD8
OOD ODA
OOE
OOF
ODC
ODE
4.7 I/0 PORTS 460 & 461
Setting data bit-0 on write-port 460 enables cache memory. To disable the cache, this bit has to be reset. The cache is disabled at power-on. At least a 64KB block of cachable RAM should be written into, before enabling the cache for the first time after power-on. If cache fault was reported by the POST, the should not be enabled. Refer to Section 4.9 for detail.
The read/write port 461 decides the processor clock frequency.
Reset data bit O for 6MHz operation
Set data bit O for 16MHz operation
4.8 Real Time Clock/Complementarv Metal Oxide rRTC/CMOS) RAM
Semiconductor
The RTC/CMOS RAM chip is a MOTOROLA MCI 46818. It contains the real time clock and 64 bytes of CMOS RAM The internal clock circuitry uses 14 bytes of RAM and the rest is used to keep system configuration information.
4-8
Section 4
The following table shows the CMOS. RAM addresses:-
Addresses Description
15
16
17
18
19-20
2E-2F
30
31
32
33
34-3F
00-0D
OE
OF
10
11
12
13
14
Real time clock information
Diagnostic status byte
Shutdown status byte
Diskette drive type byte - drives A and B
Reserved
Fixed disk type byte - drives C and D
Reserved
Equipment byte
Low base memory byte
High base memory byte
Low expansion memory byte
High expansion memory byte
Reserved
Two-byte CMOS checksum
Low expansion memory byte
High expansion memory byte
Date century byte
Information flags (set during power on)
Reserved
Note:The 2-byte CMOS checksum is on address 10H-20H.
These bytes can be read/written by first outputting the address to
I/0 port 70H and then by reading/writing data from/to I/0 port
71H.
4-9
4
5
6
7
8
0
1
2
3
9
10
11
12
13
Section 4
REAL TIME CLOCK INFORMATION
I
The fallowing table describes real-tirr.e clock bytes with their addresses:-
Byte Address Function
Seconds
Second alarm
Minutes
Minute alarm
Hours
Hour alarm
Day of week
Date of month
Month
Year
Status Register A
Status Register B
Status Register C
Status Register D
00
01
02
03
04
05
06
07
08
09
OA
OB oc
OD
Note: The built-in setup program of the system BIOS initializes registers A, B, C and D when the time and date are set. Also, interrupt IA is the BIOS interface to read/set the time and date.
The function of the status register bits is as follows:-
Status Register A
Bit 7 Update in Progress (UIP) - A l indicates that an update cycle is in progress or will soon begin. A
O indicates that the time, calender and alarm information in the RAM is fully available to read/write. Writing a I to the SET bit in
Register B inhibits any update cycle and then clears the UIP bit.
Bit 6-Bit 4 22-Stage Divider (DY2-DVO) - The divider selection bits identify which of the three time base frequencies (4.194304 MHz, 1.048576 MHz and
32.768 KHz) is in use. The system initializes the divider selection bits by 010, which selects a
32.768 KHz time base.
Bit 3-Bit O Rate Selection Bits (RS3-RSO) - These bits select the divider output frequency. The system initializes the rate selection bi ts by O 110, which selects a 1.024 KHz square wave output frequency
4-10
Section 4 and a 976.562 microsecond periodic interrupt rate if SQWE and PIE bits of register B are enabled.
Status Register B
Bit 7 SET - A O updates clock functions normally by advancing the counts once-per-second. A l aborts any update cycle in progress and the program can initialize the 14 time and calender bytes without any update occuring in the midst until a O is written to this bit.
Bit 6 Periodic Interrupt Enable (PIE) - This is read/write bit which allows an interrupt to occur at a rate specified by the RS3-RSO bits in
Register A. A 1 enables the interrupt and a O disables it. The system initializes this bit to 0.
Bit 5
Bit 4
Bit
3
Bit 2
Bit 1
Bit O
Alarm Interrupt Enable (AIE) - This read/write bit when set to 1 allows an alarm interrupt to occur. A O disables the interrupt. The system initializes this bit to 0.
Update Ended Interrupt Enable (UIE) - This read/write bit when set enables the update ended interrupt and a O disables it. The system initializes this bit to 0.
Square Wave Enabled (SQWE) - This bit when set to 1, enables a square wave signal at the frequency specified in the rate selection bits
RS3-RSO to appear on the SQW pin. The SQW pin is held low when SQWE bit is set to 0. The system initializes this bit to 0.
Date Mode (DM) - This bit indicates whether time and calender updates are to use binary or BCD formats. This read/write bit, when set to O indicates binary and a 1 indicates BCD. The system initializes this bit to 0.
24/12 - This read/write bit establishes the format of the hour bytes. A 1 indicates the 24-hour mode and a O indicates the 12-hour mode. The system initializes this bit to I.
Daylight Savings Enabled (DSE) - This read/write bit when set to 1, allows the program to enable two special updates. On the last Sunday in
April
4-11
Section 4 the time increments from l:59:59AM to 3:00:00AM
On the last Sunday· in
Octobar when the time first reaches 1:59:59 AM it changes to 1:00:00 AM
These special updates do not occur if DSE bit is set to 0. The system initializes this bit to 0.
Status Register C
Bit 7 Interrupt Request Flag (IRQF)
Bit 6
Bit 5
Bit 4
Periodic Interrupt Flag (PF)
Alarm Interrupt Flag (AF)
Update Ended Interrupt Flag (UF)
Bit 7 -Bit 4 are read only flags which are used by the program to determine the source of interrupts when the AIE, PIE and UIE interrupts are enabled in Register B.
Bit 3 - Bit O
Status Register D
Bit 7 Valid RAM and Time bit (VR T) - It indicates the condition of the contents of the RAM through the power sense (PS) pin. A O appears on the VR T bit if the power sense pin is low which indicates that the real time clock has lost its power
(battery dead). The processor program sets the
VR T bit to 1 when the time and calender are initialized to indicate that the RAM and time are valid.
Bit 6-Bit O
These unused bits are read as O and they cannot be written.
These unused bits are read as O and they cannot be written into.
4-12
Section 4
CMOS RAM CONFIGURATION INFORMATION
The following are the bit definitions for the CMOS configuration bytes (addresses hex OE-3F):-
Diagnostic St�tus Byte (address hex OE)
Bit 7 Real time clock chip power status - A O indicates that the chip has not lost power and a I indicates that the chip has lost power.
Bit 6
Bit 5
Bit
4
Bit 3
Bit 2
Bit I-Bit O
Configuration Record Checksum Status Indicator
- a O indicates that the Checksum is good, and a
1 indicates that it is bad.
Incorrect Configuration Information - This bit is used to check the validity of the content of the equipment byte of the configuration record. A O indicates that the configuration information is valid, and a I indicates it is in valid.
Memory Size Miscompare - A O indicates that the power on diagnostic program check of the system memory size matches with that in the configuration record. A l indicates that the memory size is different.
Fixed Disk Adapter/Drive C Initialization Status
- A O indicates that the fixed disk adapter and drive are functioning properly and the system can attempt to 'boot up'. A 1 indicates that the adapter and/or drive C failed initializtion, which prevents the system from 'boot up'.
Time Status Indicator - A O indicates that the time is valid and a I indicates that the time is invalid.
Reserved.
4-13
Section 4
Shutdown Status Byte (address hex Of)
This byte defines the cause of a processor shutdown. This byte is checked by the · program, when the SYSTEM FLAG (See in Keyboard
Controller description) is set, to determine the cause of the processor shutdown. The following table defines the shutdown byte
-----------------------------------------
-----------------------------------------
0
1
2
3
4
5
6
7
8
Soft Reset or Unexpected shutdown
Shut down after memory size
Shut down after memory test
Shut down with memory error
Shut down with boot loader request
JMP DWORD request (with INT !NIT)
Protected mode test passed
Protected mode test failed
Protected mode test failed
9 Block move shut down request
-----------------------------------------
Diskette Drive Type Byte (address hex 10)
Bit 7-Bit 4 Drive A type:
Bit 3-Bit O
0000
0001
0010 l .2N!B)
0011
0100-
1111
No drive present
Double Sided Diskette Drive (48 TPI,
360KB)
High Capacity Diskette Drive (96 TPI,
3 1/2" Diskette Drive (96 TPI, 720KB)
Reserved
Type of second diskette drive installed:
_The bit definitions are same as above.
4-14
Section 4
Fixed Disk Type Byte (address hex 12)
Bit 7-Bit 4
'
Type of first fixed disk drive installed (drive C):
Bit 3-Bit O
0000 No fixed disk drive is present
0001 through 1110 define type I through type-14,
1111 the list of which is given in table below
Hard Disk type between 16 and 255 is indicated in the extended byte (address hex 19)
Type of second fixed disk drive (drive D):
The bit definitions are same as above, except for
1111 which implies that the Hard Disk type between 16 and 255 is indicated in the extended byte (address hex I A)
Ref er to Section 2.B.3.1 for fixed disk type table.
Equipment Byte (address hex 14)
Bit 7-Bit 6 Total number of diskette drives installed:
00 1 drive
01
IO
11
2 drives
Reserved
Reserved
Bit 5-Bit 4 Primary Display
00 Primary display is other than Color
Graphics Adapter or Monochrome Display adapter.
01
10
Primary display is Color Graphics Adapter in 40 column mode.
Primary display is Color Graphics Adapter in 80 column mode.
11 Primary display is Monochrome Display and Printer Adapter.
Bit 3-Bit 2
Bit 1
Bit O
Not used
Math Coprocessor presence bit:
O Math Coprocessor not installed
Math Coprocessor installed
I
0
Diskette drives are installed
Diskette drives are not installed
4-15
Section 4
High Base Memory Bytes (address hex 15 and 16)
The size of memory below IMB is indicated by the 16-bit word formed by these two bytes (address 16H is the higher byte). The content of this word increments by 40H for every 64 KB ·increment of base memory size. For example, if the system contains 256 KB then confep.t of base memory bytes (15H and 16H together) will be
Ol OOH (content of 16H is OIH and content of 15H is OOH).
Maximum possible size of memory below l MB is 640KB. So the maximum possible value of base memory bytes is 0280H.
Low and High Memory Expansion Bytes (address hex 17 and 18)
The size of memory above lMB is indicated by the 16-bit word formed by these two bytes (address l 8H is the higher byte). In this case also, the content of this word increments by 40H for every 64 KB increment of expansion memory size. So if the content of memory expansion bytes is 0200H (content of l 8H is 02H and content of l 7H is OOH), then the amount of memory above
MB is 512 Kilobytes. Maximum possible value is 3COOH for a maximum of 15 MB of memory above lMB.
Drive C Extended Byte (address hex 19)
Bit 7 - 0 Defines the type of Fixed
Disk
Drive installed
(Drive
C).
00000000 thru 00001111 are reserved.
000 I 0000 thru 1111 l l l l define the types 16 thru
255.
Drive D Extended Byte (Hex lA)
Bit 7 - 0 Definition is the same as Drive C extended byte.
Checksum (address hex 2E and 2F)
Address hex 2E - Low byte of checksum
Address hex 2F - High byte of checksum
Checksum is calculated by adding con ten ts of address I OH through
20H and the low byte of checksum is stored in hex 2E and the high byte in hex 2F.
4-16
Section 4
Low and High Expansion Memory Bytes (address hex 30 and 31)
The size of memory above LMB is indicated by the 16-bit word formed by these two bytes (address 31H is the higher byte), as determined at power-on time. The content of this word increments by 40H for: every 64 KB increment of expansion memory size.
Maximum· _possible value is 3COOH for a maximum of 15 MB of memory above lMB.
Date Century Byte (address hex 32)
Bit 7-Bit O BCD value for the century (BIOS interface to read and set).
Information Flag (address hex 33)
Bit 7 Set if memory is present in address space hex
080000-09FFFF
Bit 6
Bit 5-Bit O
Used by the Setup utility to put out a first user message after initial setup
Reserved
Note: Hex addresses 11, 13, 1B-2D, 34-3F are reserved.
4.9 Kevboard Controller
The keyboard controller is 8742 single chip microcomputer-based and is used to support 386 PC keyboard interface. The controller has the following functions:-
-Receive serial data from the keyboard, check parity of the data and translate it to system scan code, if necessary. Put the received and processed data in to the · data buff er and interrupt processor.
-Execute system commands through the controller command buffer and place the result, if necessary, m the data buff er and interrupt the processor
-Transmit system data, placed in the data buffer, to the keyboard in a serial format with the parity bit inserted. Get the response from the keyboard and report to the system.
-Report any error to the system through status register at the time of data communication with the keyboard.
4-17
Section 4
Receiving data from the keyboard
The keyboard sends data in a 11-bit serial format. The first bit is a start bit (low level) followed by 8 data bits (least significant data bit first), an odd parity bit and a stop bit (high level). · Data sent is synchroni�d with the keyboard clock. Upon receiving a byte of data from the keyboard, the keyboard controller places the data in its one by.te receive-data buffer and disables the keyboard interface until that data is picked up by the system processor. This avoids data overrun. On parity error, the controller requests the keybo ard to re-send the data. If the error is repeated, the controller sets the parity error bit in its status register. Time- out error is indicated by setting the time-au t bit in the status register, if all the 11 bits are not received within 2 milliseconds from start of transmission. In case of either of these errors, hex FF is placed in the receive-data buff er.
Sending data to the keyboard
Data is sent to the keyboard in the same serial format as data received from the keyboard. If the time between request to send and start of transmission is greater than 15 milliseconds, or if the duration of transmission is greater than 2 milliseconds, then the transmit time-out error bit is set in the status register. The keyboard is required to acknowledge every transmission from the controller. If the acknowledgement has parity error, then the controller sets both the parity and transmit time-out error status bits. Also, if the acknowledgement does not . arrive within 25 milliseconds, both the receive and transmit time-out error bits are set. In case of all these errors, hex FE is placed in the data buffer. No retries are made for error at the time of transmitting to the keyboard.
Keyboard Inhibit
The keyboard can be inhibited through keylock jumper J20. When the keyboard is inhibited, although all transmissions from the system to the keyboard will be allowed, the keyboard controller tests all data received from the keyboard. If it is a response to a command sent to the keyboard, then it is placed in the data buffer, otherwise it is ignored.
Keyboard Controller System Interface
The system communicates with the keyboard controller through an input buffer, an output buffer and a status register. The status register can be read through I/0 port 64H. The output buffer can
4-18
Section 4 be read through 1/0 port 60H. The input buff er can be written through both I/0 port 64H and · 60H. When the input buff er is written through 1/0 port 64H, the controller interprets it as a command and if it is written through I/0 port 60H, then the data is interpreted either as a parameter to a command to the controller or a data to be trans- mitted to the keyboard.
Keyboard Controller Status Register Bit definitions
Bit O Output Buff er Full - A O indicates that the keyboard controller's output buff er has no data. When the keyboard controller writes to the output buff er, this bit is set to 1. It returns to 0, when the system reads the output buffer (60H).
Bit 1 Input Buff er Full - A O indicates that the keyboard controller's input buff er (60H or 64H) is empty. When the system writes to the input buffer this bit is set to 1. It gets reset to O when the controller reads the input buffer.
Bit 2 System Flag - The keyboard controller can set this bit to
O or 1 depending on the command from the system. It is set to O after power on reset.
Bit 3 Command/Data - This bit is used by the keyboard controller to determine whether the input buff er contains the command or data. When the system writes to the input buff er through I/0 port 64H, this bit is set to 1. When the system write to the input buff er, this bit is set to 0.
Bit 4 Inhibit Switch - This bit reflects the state of the keyboard inhibit switch. This bit is updated whenever the controller writes to the output buff er. A O indicates that the keyboard is inhibited.
Bit 5 Transmit Time-Out - A 1 indicates that a data transmission from the keyboard controller to the keyboard was not properly completed within the predefined time limit.
Bit 6 Receive Time-Out - A 1 indicates that a data transmission from the keyboard to the keyboard controller was not properly completed within the predefined time limit.
Bit
7 Parity Error - A 1 indicates that the last byte received from the keyboard had a parity error. The keyboard sends data with odd parity.
4-19
Section 4 be read through I/0 port 60H. The input buff er can be written through both 1/0 port 64H and · 60H. When the input buff er is written through I/0 port 64H, the controller interprets it as a command and if it is written through I/0 port 60H, then the data is interpreted either as a parameter to a command to the controller or a data to be trans- mitted to the keyboard.
Keyboard Controller Status Register Bit definitions
Bit O Output Buffer Full - A O indicates that the keyboard controller's output buff er has no data. When the keyboard controller writes to the output buffer, this bit is set to 1. It returns to 0, when the system reads the output buffer (60H).
Bit 1 Input Buffer Full - A O indicates that the keyboard controller's input buffer (60H or 64H) is empty. When the system writes to the input buff er this bit is set to 1. It gets reset to O when the controller reads the input buff er.
Bit 2 System Flag - The keyboard controller can set this bit to
O or I depending on the command from the system. It is set to O after power on reset.
Bit 3 Command/Data - This bit is used by the keyboard controller to determine whether the input buffer contains the command or data. When the system writes to the input buff er through I/0 port 64H, this bit is set to l. When the system write to the input buff er, this bit is set to 0.
Bit 4 Inhibit Switch - This bit reflects the state of the keyboard inhibit switch. This bit is updated whenever the controller writes to the output buff er. A O indicates that the keyboard is inhibited.
Bit 5 Transmit Time-Out - A 1 indicates that a data transmission from the keyboard controller to the keyboard was not properly completed within the predefined time limit.
Bit 6 Receive Time-Out - A 1 indicates that a data transmission from the keyboard to the keyboard controller was not properly completed within the predefined time limit.
Bit 7 Parity Error - A l indicates that the last byte received from the keyboard had a parity error. The keyboard sends data with odd parity.
4-19
Section 4
Keyboard Controller 1/0 ports
The keyboard controller has two 8-bit 1/0 ports one of which is used as an input port and the other as an output port. The following tables show bit definitions for the I/0 ports and test input ports.
Input Port Definitions
Bit 0-Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Undefined
RAM on the system board
O=Total 256 KB of on-board RAM
1=512 KB or greater on-board RAM
Undefined
Display type switch
O=Primary display is color graphics adapter
!=Primary display is monochrome display adapter
Keyboard inhibit switch
O=Keyboard inhibited l=Keyboard not inhibited
Output Port Definitions
Bit O
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Reset to the system processor (software should keep it l for the system Processor to work)
Gate address 20 of system processor
0: The system processoR address 20 is inhibited on the system bus. Address 20 will remain zero for any system processor bus cycle* l * The system processor address 20 is not inhibited on the system bus.
Undefined
Undefined
Output buff er full interrupt to the system
Input buffer full
Keyboard clock (output)
Keyboard data (output)
System Commands to Keyboard Controller(I/0 address 64H)
20 Read keyboard controller's command byte - The controller sends its current command byte to its output buffer.
60 Write keyboard controller's command byte - The next byte of data supplied by the system is the controller's command byte, which is written to 1/0 address Hex 60.
4-20
Section 4
AE
CO
DO
Enable Keyboard Interface - This command enables the keyboard interface and also .clears bit 4 of the controller's command byte.
Read Input Port - This commands the keyboard controller · to r�ad the input port and place the data in the output buffer.
Read Output Port - This commands the keyboard controller to read the output port and place the data in the output buff er.
Dl Write Output Port - This command is used to write the data given through I/0 address 60H to the output port.
Ensure that the output port bit O is not written as it is connected to the reset of the system processor.
EO Read Test Inputs - Upon receiving this command the controller reads its TO and Tl inputs and places the data in the output buff er. Data bit O represents TO and bit l represents Tl.
FO-FF Pulse output port - Bit O through 3 of output port can be pulsed for approximately 6 microseconds by this comm.and.
Bit O through 3 of this command indicates which bits of the output port are to be pulsed. A O indicates that the bit is to be pulsed and a l indicates that the bit is to be kept unmodified. Note that bit O of the output port is connected to the reset of the system wicroprocessor. So the processor can be reset by pulsing tr.is bit.
Keyboard controller Keyboard Interface
The keyboard controller communicates with the keyboard over a clock line (bit 6 of the output port) and a data iine (bit 7 of the output pon). The keyboard controller reads the data line through a test input Tl and the clock line through a test input TO. For any type of data transmission with the keyboa.d, the keyboard clock is used. Data is made available after the r.!sing edge of the clock and is sampled on the falling edge. The hardware protocol for communication with keyboard is given below.
When the keyboard wants to send data, it first checks the clock line for a l::..igh levd(the keyboard controller car. prevent the keyboard from sending data by driving the clock line low through bit 6 of the output port). If the clock and data lines are high(i.e enabled), th: keyboard sends the data. Otherwise it stores data in its own buffer.
4-22
Section 4
The keyboard checks the state of the clock line at an interval of
60 microseconds, in order to sense wheather the keyboard con troller intends to send data. When the keyboard controller wants to send data, it forces the clock line low for more than 60 microseconds and then releases it with the data line low. This low data is accept�d by the keyboard as a start bit(request to send) and it star.ts docking the data in. After the tenth bit, the keyboard forces the data line low for one clock period (the stop bit). This action informs the keyboard controller that the keyboard has received its data.
I.IBM PC and AT are registered trademark of IBM Corporation
4-23
SECTION - 5
1/0 Channel and Conrector Specifications
5.1 I/0 Channel Features
The l/0 channel supports:-
*
24-bit memory addresses to access 16 megabytes of memory address space
* I/0 address space hex I 00 to hex 3FF
*
Selection of data accesses (either 8- or 16-bit)
* 11 levels of interrupts (IRQ3-IRQ7, IRQ9-IRQ12, IRQ14, IRQ15)
*
'I/0 channel check' to generate Nlvil
*
7 DMA channels (Channel 0-3 for 8 bit data transfer and channel
5-7 for 16 bit data transfer)
*
I/0 wait state generation
*
Open-bus structure (allowing multiple microprocessors to share the system's resources, including memory)
*
Refresh of system memory from channel microprocessors
There are 6 62-pin (J23-J28), 4 36-pin (J3 l-J34) and I 80 pin edge connector sockets for 1/0 channel adapter cards. In two positions, the 36-pin connector is not present. These positions can support only 62-pin I/0 bus adapters.
5-1
Section 5
5.2 I/0 Channel Pin Assignment
The following figures summarize pin assignments for the I/0 channel connectors:-
---------�-------------------------
I/0 Pin Signal Name I/0
A 9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A l
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A 17
A 18
A 19
A 20
A 21
A 22
A 23
A 24
A 25
A 26
A 27
A 28
A 29
A 30
SA14
SA13
SA12
SAI l
SAlO
SA9
SA8
SA7
SA6
-I OCH CK
SD7
SD6
SD5
SD4
SD3
SD2
SDI
SDO
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SAS
SA.4
SA3
SA2
SAl
SAO
I/0
I/0
I/0
I/0
I/0
I/0
1/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I
0
I/0
I/0
I/0
I/0
I/0
I
I/0
I/0
I/0
I/0
I/0
I/0
I/0
------------------------------------
5-2
---------------------------------------
I/0 pin I/0
B 25
B 26
B 27
B 28
B 29
B 30
B 31
B 17
B 18
B 19
B 20
B 21
B 22
B 23
B 24
B 9
B 10
B 11
B 12
B 13
B 14
B 15
B 16
B I
B 2
B 3
B 4
B 5
B 6
B 7
B 8
---------------------------------------
GND
RESETDRV
VCC
IRQ9
-5V
DRQ2
-12V
OWS#
+12V
GND
SMEMW#
SMEMR#
IOWR#
IORD#
-DACK3
DRQ3
-DACKl
DRQI
REFRESH#
SYSCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
-DACK2
T/C
BALE
Ground
0
Power
I
Power
I
Power
I
Power
Ground
0
0
I/0
I/0
0
I
0
I
I/0
0
I
I
I
0
0
0
Power
0
Ground
Section 5
5-3
Section 5
I/0 Channel (C-side: J31 through J38)
I/0 Pin
C 1
C2
C3 cs
C6
C7
C8
C9
C 10
C 11
C 12
C 13
C 14
C 15
C 16
C 17
C 18
Signal Name
SBHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
1v1EMR#
1v1EMW#
SD08
SD09
SDIO
SDll
SD12
SD13
SD14
SD15
I/0 Pin
D 9
D 10
D 11
D 12
D 13
D 14
D 15
D 16
D 17
D 18
D l
D 2
D 3
D 4
D 5
D 6
D 7
D 8
I/0 Channel (D-Side: 131 Through J38)
Signal Name
MCS16#
IOCS16#
IRQlO
IRQll
IRQ12
IRQ15
IRQ14
-DACKO
DRQO
-DACK5
DRQ5
-DACK6
DRQ6
-DACK7
DRQ7
VCC
-MA STER
GND
I/0
0
I
0
I
I
I
I
0
I
I
I
I
I
0
I
Power
I
Ground
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
5-4
Section 5
5.3 I/0 Channel signal description
The following is a description of the system board I/0 channel signals. All signal lines are TTL compatible. The I/0 adapter boards should be designed with a maximum of two (LS) Low-power
Schottky loads per line.
SAO-SA19· (I/0)
These address bits are used to address system memory and 1/0 devices. These lines, alongwith LA 17 through LA23, allow_ upto
16MB of memory access. SAO through SA19 are gated on the system bus when 'BALE' is high and latched on the falling edge of
'BALE'. These signals are driven by system board microprocessor or DMA controller. They can also be driven by other bus masters residing on the 1/0 channel, by activating the '-MASTER' signal.
LAI 7-LA23 (I/0)
These signals are used to address memory and 1/0 devices within the system. They are not latched, and are valid only when 'BALE' is high. These signals do not remain valid throughout the whole processor cycle. Their purpose is to generate memory decodes for l wait state memory cycles. These decodes should be latched by
I/0 adapters on the falling edge of 'BALE'. These signals may be. driven by other _ microprocessors or DMA controllers, residing on the I/0 channel, by activating the '-MASTER' signal.
SBHE (I/0)
'Byte high enable', when low, indicates a transfer of data on the upper byte of the 16-bit data bus (SD8 through SD15). Sixteen bit devices use this signal to condition the data bus buffers connected to SD8 through SD 15.
SDO-SD15 (I/0)
These are data bus signals O through 15 for memory and I/0 devices on the 1/0 adapter cards. SDO is the least significant and
SD15 is the most significant bit. All communications to 8-bit devices on the 1/0 channel should be · through SDO to SD7. For
16-bit devices on I/0 channel SDO through SD15 is used. 32- or
24-bit transfers, as well as misaligned 16-bit ones, from the 80386 are split up into two cycles of 16 bit or less. The data is gated to the appropriate part of the 32-bit processor data bus. Similarly, 16 bit transfers to 8-bit devices will be again converted into two 8-bit transfers with SD8 to SD 15 gated to SDO to SD7 whenever nece ssary.
BALE (Buffered ALE) (0)
'Address latch enable' is used to latch valid addresses and memory decodes on the system board. To the I/0 channel, it indicates a valid CPU address. When used with AEN, it indicates a valid DMA address. Microprocessor addresses SAO to SA19 are gated when
5-5
Section 5
BALE is high and are latched with the falling edge of BALE. BALE is forced high when the system processor goes to hold state, so that the address and memory decode latches become flow-through.
RESETDRV (0)
This active high signal is used to reset or initialize system logic at power-up, du�ing hard reset or a low line-voltage.
SYSCLK (0)
For system board running at 6 or 16 MHz, the time period of this clock is 167 or 125 nanoseconds respectively. At 6 MHz, this is the inverse of the CLK output from 82384. At 16 MHz, it is CLK divided by two. This clock has a 50% duty cycle and is synchron ous with the microprocessor clock. This signal should only be used for synchronization. It is not intended for uses requiring a fixed frequency.
-IOCHCK (I)
This signal is used by the I/0 adapter channel cards to report any fatal error (e.g, parity error information on 1/0 channel memory cards or error on I/0 devices ).
IOCHRDY (I)
'I/0 channel ready' is used by memory or I/0 devices to extend memory or I/0 cycles. A slow device, requiring more than the bus cycle time provided by the system board, should pull IOCHRDY low
(not active) immediately after detecting valid address .together with
Read or Write command. Machine cycles are extented by an integral number of SYSCLK cycles (e.g, 167 ns at 6 MHz). This signal should not be held low for more than 2.5 microseconds.
IRQ3-IRQ7, IRQ9-IRQ12 and IRQ14 to IRQ15 (I)
These positive edge triggered Interrupt Requests are used by l/0 channel adapter cards, to indicate to the microprocessor that it requires attention. The interrupt requests are prioritized. The priority is as shown, in decreasing order: IRQ9 through IRQ12,
IRQ14, IRQ15 and IRQ3 through IRQ7. An interrupt request is generated by raising an IRQ line from low to high. The line must be held high until the processor acknowledges the interrupt request
(Interrupt service routine). IRQO-IRQ2, IRQ8 and IRQ 13 are used by the system board.
IORD# (I/0)
'I/0 read', an active low signal, instructs the selected I/0 device to drive its data onto the data bus. This signal may be driven by the system microprocessor, system board DMA controllers, or by a microprocessor or DMA controller resident on the 1/0 channel.
5-6
Section 5
IOWR# (I/0)
'I/0 write', an active low signal, instructs the selected 1/0 device to read data from the data bus. . It may be driven by the system microprocessor, system board DMA controllers, or by a microproce ssor or DMA controller resident on the I/0 channel.
SMEMR# (0),. MEMR# (l/0)
These signals instruct the memory devices to drive data onto the data bus. · Both of these signals are active low. S11EMR# signal is generated for any read in low l:M:B of memory space, and can be driven by the system board microprocessor and DMA controllers only. M.EMR# is active in all memory read cycles and can be driven by any microprocessor or DMA controller in the system.
SMEMR# is generated from MEMR# qualified with the decode of the low lMB of memory. There is one exception. When SWI is
ON, SMEMR# is not generated for address OCOOOO thru OC7FFF.
When a microprocessor or a DMA controller, on the I/0 channel, wants to drive the MEMR# signal, ii must drive the address lines valid at least one SYSCLK period before driving MEMR# active.
These signals, both active low, instruct the memory devices to store the data present on the data bus. MEMW# signal is active in all memory write cycles and can be driven by any microprocessor or DMA controller in the system. SMEMW# signal is active in all memory write cycles in low lMB of memory space. It is generated from MEMW# signal, qualified with the decode of the low lMB of memory. This has one exception. When SWl is ON, SMEMW# is not generated for address OCOOOO thru OC7FFF. S11EMW# can only be driven by the system board microprocessor and DMA controllers.
When a microprocessor or a DMA controller, on the I/0 channel, wants to drive the MEMW# signal, it must drive the address lines valid at least one SYSCLK period before driving MEMW# active.
DRQO-DRQ3 and DRQ5-DRQ7 (I)
DMA requests O through 3 and 5 through 7 are asynchronous, active high, channel requests. They are used by peripheral devices and I/0 channel microprocessors, to gain DMA service or control of the system. An I/0 channel microprocessor can gain control of the system by activating a DMA request line, and then activating
-MASTER signal after getting D:M.A acknowledge (DACK) signc.l.
The D:M.A request lines are prioritized with DRQO having the highest priority and DRQ7 having the lowest. A D:M.A request is generated by bringing the DRQ line to an active (high) level and keeping it active until the corresponding DACK signal goes active.
DRQO-DRQ3 are used for 8-bit data transfers between 8-bit I/0 device and 8/16-bit memory device. DRQ5-DRQ7 are used for
16-bit data transfer between 16-bit I/0 device and 16-bit memory device. DRQ4 is used in the system board for cascading the two
DMA controllers, and is not available on the 1/0 channel.
5.7
· Section 5
-DACKO to-DACK3 and -DACKS to -DACK7 (0)
DMA acknowledge signals O through 3 and 5 acknowledge requests on the corresponding
They are active low.
through 7 are used to
DMA request lines.
REFRESH# (I/0)
This activ.e lbw signal is used to indicate a dynamic memory refresh cycle and -can be driven by any microprocessor on the I/0 channel.
This signal is generated after every 15 microseconds.
AEN (0)
'Address enable', high active, signal is used to degate the micropro cessor and other devices from the 1/0 channel, to enable DMA transfers to take place. When this signal is active, the DMA controller has the control of address bus, data bus, memory control
(SME1v1R#, SMEMW#, :tv:tEMR#, MEMW#) and I/0 control (!ORD#,
IOWR#) signals.
T/C (0)
'Terminal count', normally low, provides a pulse when any DMA channel reaches the terminal count.
-MASTER (I)
This signal is used by a microprocessor or DMA controller residing on the I/0 channel to gain control of the system bus. The procedure to gain control of the system bus is as follows:-
-Issue a DRQ to a DMA channel in cascade mode.
-Upon receiving a -DACK, pull the -MASTER signal low to gain control of the system address, data and control lines.
-After -MASTER is low, the I/0 microprocessor should wait at least one SYSCLK period before driving the address and data lines and two SYSCLK period before driving the control lines
(ME1v1R#, MEMW#, IORD#, IOWR#).
If -MASTER signal is held low for more than 15 microseconds, system memory data may be lost due to lack of refresh. The I/0 microprocessor (in control) can take care of this by activating the
REFRESH# signal.
MCS16# (I)
'-MEM 16 chip select' indicates to the system board whether the present data transfer is a 16-bit 1 wait-state memory cycle (true at
6 MHz system board . operation). At 16 MHz the number of wait states is increased, to allow at least 500ns for the machine cycle.
It must be derived from decoding address LAI 7 through LA23.
'MCS l6#' is an active low signal and should be driven with an open collector or tri-state driver capable of sinking 20mA.
5-8
<
Section 5
IOCS16# (I)
'-I/0 16 bit chip select' signals to the system board that the present l/0 data transfer is a 16-bit I/0 cycle, requiring at least
375ns. This active low signal is derived from an address decode, and should be driven with an open collector or tri-state driver capable of sin:king 20 mA. osc (0)
'Oscillator' is a 14.31818 MHz clock with a duty cycle of 50%. _ This signal is not synchronous with SYSCLK. This signal is used in
Color Graphics Adapter card.
OWS# (I)
'0-wait state' signal is used to tell the system microprocessor that the present bus cycle can be completed without i'nserting any additional wait states at 6 MHz. In order to run a memory cycle on a 16-bit memory device, without wait states, OWS# signal should be derived from an address decode gated with a read or write command (also MCS16# signal has to be activated). At 16 MHz, a minimum cycle time of 330ns is assured. In order to run a memory cycle to an 8-bit device with a minimum of 2-wait states, OWS# should be driven active one system clock after the read or write command is active, gated with the address decode for the device.
Memory read or write commands to an 8-bit device are active on the falling edge of SYSCLK. At 6 l'V1Hz, the machine cycle is terminated at the end of the CLK cycle, if OWS# is sampled low in the middle of the CLK cycle. At 16 MHz, for a 8-bit cycle, the machine cycle is terminated 2 CLK cycles afte.r OWS# is sampled low. For a 16 bit cycle, a cycle time of 250ns is guaranteed.
OWS# is an active low signal and should be driven with an open collector or tri-state driver capable of sinking 20mA.
5-9
1
2
3
4
5
6
4
5
6
1
2
3
Section 5
5.4 Connectors
The system board contains following connectors:
* Two po,".er-§upply connectors (PSS, PS9)
Pin assignments are as follows:-
Pin Assignments Connector
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VCC
VCC vcc
PS8
PS9
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Pin
1
2
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Hard reset
Ground
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Pin Assignments
1
2
3
4
6V de
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4
5
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Pin Assignments
Keyboard clock
Keyboard data
Not used
Ground
VCC
The pin
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Pin
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2
3
4
5
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LED power
Key
Ground
Keyboard Inhibit
Ground
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Pin Assignments l
2
3
4
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Key
Ground
VCC
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Pin Assignment
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