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ARM-based Embedded MPU
SAM9X35
DATASHEET
Description
The SAM9X35 is a highly-integrated 400 MHz ARM926EJ-S™ embedded MPU, featuring an extensive peripheral set and high bandwidth architecture for industrial applications that require refined user interfaces and high-speed communication.
The SAM9X35 features a graphics LCD controller with 4-layer overlay and 2D acceleration (picture-in-picture, alpha-blending, scaling, rotation, color conversion), and a 10-bit ADC that supports 4- or 5-wire resistive touchscreen panels.
Networking/connectivity peripherals include two 2.0A/B compatible Controller Area
Network (CAN) interfaces and an IEEE Std 802.3-compatible 10/100Mbps Ethernet
MAC. Multiple communication interfaces include a soft modem supporting exclusively the Conexant SmartDAA line driver, HS USB Device and Host, FS USB Host, two HS
SDCard/SDIO/MMC interfaces, USARTs, SPIs, I2S, TWIs and 10-bit ADC.
The 10-layer bus matrix associated with 2 x 8 central DMA channels as well as dedicated DMAs to support the high-speed connectivity peripherals ensure uninterrupted data transfer with minimum processor overhead.
The External Bus Interface incorporates controllers for 4-bank and 8-bank
DDR2/LPDDR, SDRAM/LPSDRAM, static memories, and specific circuitry for
MLC/SLC NAND Flash with integrated ECC.
The SAM9X35 is available in a 217-ball BGA package with 0.8 mm ball pitch.
11055E–ATARM–10-Mar-2014
1.
Features
Core
ARM926EJ-S™ ARM ® Thumb ® Processor running at up to 400 MHz @ 1.0V +/- 10%
16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
Memories
One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash, SDCard, DataFlash ® or serial DataFlash. Programmable order.
One 32-Kbyte internal SRAM, single-cycle access at system speed
High Bandwidth Multi-port DDR2 Controller
32-bit External Bus Interface supporting 4-bank and 8-bank DDR2/LPDDR, SDR/LPSDR, Static Memories
MLC/SLC 8-bit NAND Controller, with up to 24-bit Programmable Multi-bit Error Correcting Code (PMECC)
System running at up to 133 MHz
Power-on Reset Cells, Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and
Real Time Clock
Boot Mode Select Option, Remap Command
Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator
One PLL for the system and one PLL at 480 MHz optimized for USB High Speed
Twelve 32-bit-layer AHB Bus Matrix for large Bandwidth transfers
Dual Peripheral Bridge with dedicated programmable clock for best performance
Two dual port 8-channel DMA Controllers
Advanced Interrupt Controller and Debug Unit
Two Programmable External Clock Signals
Low Power Mode
Shut Down Controller with four 32-bit Battery Backup Registers
Clock Generator and Power Management Controller
Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
Peripherals
LCD Controller with overlay, alpha-blending, rotation, scaling and color conversion
USB Device High Speed, USB Host High Speed and USB Host Full Speed with dedicated On-Chip
Transceiver
One 10/100 Mbps Ethernet MAC Controller
Two High Speed Memory Card Hosts
Two CAN Controllers
Two Master/Slave Serial Peripheral Interface
Two 3-channel 32-bit Timer/Counters
One Synchronous Serial Controller
One 4-channel 16-bit PWM Controller
Three Two-wire Interfaces
Three USARTs, two UARTs, one DBGU
One 12-channel 10-bit Touch-Screen Analog-to-Digital Converter
Soft Modem
Write Protected Registers
I/O
Four 32-bit Parallel Input/Output Controllers
105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os
SAM9X35 [DATASHEET]
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2
Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input
Individually Programmable Open-drain, Pull-up and pull-down resistor, Synchronous Output
Package
217-ball BGA, pitch 0.8 mm
SAM9X35 [DATASHEET]
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2.
Block Diagram
Figure 2-1. SAM9X35 Block Diagram
A0/NBS0 D0-D15
A1/NBS2/NWR2/DQM2
A16/BA0 A2-A15, A19 NCS1/SDCS NCS0 A18/BA2 A17/BA1 NWR0/NWE NRD NWR1/NBS1 NWR3/NBS3/DQM3 SDCK, #SDCK, SDCKE
A10
WE, SD
RAS
, CAS
DQM[0..1] SD DQS[0..1]
AIT
NW A20-A25 D16-D31 NCS2, NCS3, NCS4, NCS5 NANDOE, NAND
ALE, NANDCLE
WE
NAND NANDCS
PIO
,HHSDMB
,HFSDMB
A,
A,
,LCDHSYNC
A T23
V
VSYNC
A T0-LCDD LCD
LCDPCK
LCDD
LCDDISP
ETXEN
REFCK
ERX0-ERX1
ETX0-ETX1
EMDIO
EMDC
ERXER-CRCSD
LDDEN,LCDPWM
DHSDP/HHSDP
DHSDM/HHSDMA
DFSDM/HFSDMA
DFSDP/HFSDP
HHSDPB
HFSDPB
AGSEL
JT
BMS
TCK
TMS
TDO
TDI
RTCK
HFSDPC
HFSDMC
NTRST
VBG
PIO
TST
PCK0-PCK1
FIQ IRQ
DTXD DRXD
XIN
XOUT XIN32
XOUT32
WKUP
SHDN
U
NRST
VDDB
VDDCORE
A3
A
MCI1_CK
MISO
MOSI
NPCS3
SPCK
NPCS2
NPCS1
NPCS0
MISO
MOSI
SPCK
RK
RF
RD
TF
TK
TD
NPCS0
NPCS1
NPCS3
NPCS2
A
A3
MCI0_CK
MCI0_CD
MCI1_CD
A0-MCI0_D
A0-MCI1_D
DIBP
DIBN
TWD0-TWD2
TWCK0-TWCK2
CANRX0-CANRX1
CANTX0-CANTX1
MCI1_D
MCI0_D
PWM0-PWM3
AD1UR
AD0UL
AD2LL
AD3LR
AD11
VREF
AD4PI
ANA
ANA
VDD
AD
GND
AD5-GP
TSADTRG
A5
A0-TIO
TIOB0-TIOB5
TIO
GP
TCLK0-TCLK5
TS0-2
R
SCK0-2
RDX0-2
TXD0-2
CTS0-2
URDX0-URDX1
UTXD0-UTXD1
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3.
Signal Description
gives details on the signal names classified by peripheral.
Table 3-1.
Signal Description List
Signal Name Function
XIN
Clocks, Oscillators and PLLs
Main Oscillator Input
XOUT
XIN32
XOUT32
VBG
PCK0–PCK1
Main Oscillator Output
Slow Clock Oscillator Input
Slow Clock Oscillator Output
Bias Voltage Reference for USB
SHDN
WKUP
Programmable Clock Output
Shutdown, Wakeup Logic
Shut-Down Control
Wake-Up Input
ICE and JTAG
TCK
TDI
TDO
TMS
JTAGSEL
RTCK
Test Clock
Test Data In
Test Data Out
Test Mode Select
JTAG Selection
Return Test Clock
Reset/Test
NRST
TST
NTRST
BMS
DRXD
DTXD
IRQ
FIQ
PA0–PA31
PB0–PB18
PC0–PC31
PD0–PD21
Microcontroller Reset
Test Mode Select
Test Reset Signal
Boot Mode Select
Debug Receive Data
Debug Unit - DBGU
Debug Transmit Data
Advanced Interrupt Controller - AIC
External Interrupt Input
Fast Interrupt Input
PIO Controller - PIOA - PIOB - PIOC - PIOD
Parallel IO Controller A
Parallel IO Controller B
Parallel IO Controller C
Parallel IO Controller D
Input
Input
Output
Input
Input
Output
I/O
Input
Input
Input
Type
Input
Output
Input
Output
Analog
Output
Output
Input
Input
Output
Input
Input
I/O
I/O
I/O
I/O
Active Level
Low
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Table 3-1.
Signal Description List (Continued)
Signal Name Function
D0–D15
D16–D31
A0–A25
NWAIT
NCS0–NCS5
NWR0–NWR3
NRD
NWE
NBS0–NBS3
NFD0–NFD16
NANDCS
NANDOE
NANDWE
SDCK,#SDCK
SDCKE
SDCS
BA[0..2]
SDWE
RAS-CAS
SDA10
DQS[0..1]
DQM[0..3]
MCI0_CK, MCI1_CK
MCI0_CDA, MCI1_CDA
MCI0_DA0–MCI0_DA3
MCI1_DA0–MCI1_DA3
SCKx
TXDx
RXDx
RTSx
CTSx
Type
External Bus Interface - EBI
Data Bus
Data Bus
Address Bus
External Wait Signal
Static Memory Controller - SMC
Chip Select Lines
I/O
I/O
Output
Input
Write Signal
Read Signal
Write Enable
Byte Mask Signal
NAND Flash I/O
NAND Flash Support
NAND Flash Chip Select
NAND Flash Output Enable
Output
Output
Output
Output
Output
I/O
Output
Output
Output NAND Flash Write Enable
DDR2/SDRAM/LPDDR Controller
DDR2/SDRAM Differential Clock
DDR2/SDRAM Clock Enable
DDR2/SDRAM Controller Chip Select
Bank Select
DDR2/SDRAM Write Enable
Row and Column Signal
SDRAM Address 10 Line
Data Strobe
Write Data Mask
High Speed MultiMedia Card Interface - HSMCI0–1
Multimedia Card Clock
Multimedia Card Slot Command
Multimedia Card 0 Slot A Data
Multimedia Card 1 Slot A Data
I/O
I/O
I/O
I/O
Universal Synchronous Asynchronous Receiver Transmitter - USARTx
USARTx Serial Clock I/O
USARTx Transmit Data
USARTx Receive Data
Output
Input
USARTx Request To Send
USARTx Clear To Send
Output
Input
Output
Output
Output
Output
Output
Output
Output
I/O
Output
Active Level
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
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HFSDPA
HFSDMA
HHSDPA
HHSDMA
HFSDPB
HFSDMB
HHSDPB
HHSDMB
HFSDMC
HFSDPC
RK
TF
RF
TD
RD
TK
Table 3-1.
Signal Description List (Continued)
Signal Name Function
Universal Asynchronous Receiver Transmitter - UARTx
UTXDx
URXDx
UARTx Transmit Data
UARTx Receive Data
Synchronous Serial Controller - SSC
SSC Transmit Data
SSC Receive Data
SSC Transmit Clock
SSC Receive Clock
SSC Transmit Frame Sync
SSC Receive Frame Sync
Timer/Counter - TCx x=0..5
TCLKx
TIOAx
TIOBx
SPIx_MISO
SPIx_MOSI
SPIx_SPCK
SPIx_NPCS0
SPIx_NPCS1–SPIx_NPCS3
TWDx
TWCKx
PWM0–PWM3
TC Channel x External Clock Input
TC Channel x I/O Line A
TC Channel x I/O Line B
Serial Peripheral Interface - SPIx
Master In Slave Out
Master Out Slave In
SPI Serial Clock
SPI Peripheral Chip Select 0
SPI Peripheral Chip Select
Two-Wire Interface - TWIx
Two-wire Serial Data
Two-wire Serial Clock
Pulse Width Modulation Controller - PWMC
Pulse Width Modulation Output
USB Host High Speed Port - UHPHS
USB Host Port A Full Speed Data +
USB Host Port A Full Speed Data -
USB Host Port A High Speed Data +
USB Host Port A High Speed Data -
USB Host Port B Full Speed Data +
USB Host Port B Full Speed Data -
USB Host Port B High Speed Data +
USB Host Port B High Speed Data -
USB Host Port C Full Speed Data -
USB Host Port C Full Speed Data +
Type
Output
Input
Output
Input
I/O
I/O
I/O
I/O
Input
I/O
I/O
I/O
I/O
I/O
I/O
Output
I/O
I/O
Output
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Active Level
Low
Low
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Table 3-1.
Signal Description List (Continued)
Signal Name Function
USB Device High Speed Port - UDPHS
DFSDM
DFSDP
DHSDM
DHSDP
USB Device Full Speed Data -
USB Device Full Speed Data +
USB Device High Speed Data -
USB Device High Speed Data +
RMII Ethernet 10/100 - EMAC
Transmit Clock or Reference Clock REFCK
ETXEN
ETX0–ETX1
CRSDV
ERX0–ERX1
ERXER
EMDC
EMDIO
Transmit Enable
Transmit Data
Receive Data Valid
Receive Data
Receive Error
Management Data Clock
Management Data Input/Output
LCD Controller - LCDC
LCDDAT 0–23
LCDVSYNC
LCDHSYNC
LCDPCK
LCDDEN
LCDPWM
LCDDISP
LCD Data Bus
LCD Vertical Synchronization
LCD Horizontal Synchronization
LCD Pixel Clock
LCD Data Enable
LCD Contrast Control
LCD Display Enable
Analog-to-Digital Converter - ADC
Top/Upper Left Channel AD0
XP_UL
AD1
XM_UR
AD2
YP_LL
AD3
YM_SENSE
AD4
LR
AD5–AD11
ADTRG
ADVREF
CANRXx
CANTXx
Bottom/Upper Right Channel
Right/Lower Left Channel
Left/Sense Channel
Lower Right Channel
7 Analog Inputs
ADC Trigger
ADC Reference
CAN input
CAN output
CAN Controller - CANx
Soft Modem - SMD
DIBN
DIBP
Soft Modem Signal
Soft Modem Signal
Analog
Analog
Analog
Analog
Analog
Analog
Input
Analog
Output
Output
Output
Output
Output
Output
Output
Input
Output
Output
Input
Input
Input
Output
I/O
Type
Analog
Analog
Analog
Analog
Input
Output
I/O
I/O
Active Level
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4.
Package and Pinout
The SAM9X35 is available in 217-ball BGA package.
4.1
Overview of the 217-ball BGA Package
Figure 4-1 shows the orientation of the 217-ball BGA Package.
Figure 4-1. Orientation of the 217-ball BGA Package
TOP VIEW
17
16
15
14
13
12
11
10
9
8
4
3
2
1
7
6
5
A B C D E F G H J K L M N P R T U
BALL A1
4.2
I/O Description
Table 4-1.
SAM9X35 I/O Type Description
I/O Type
GPIO
Voltage Range
1.65–3.6V
GPIO_CLK
GPIO_CLK2
GPIO_ANA
EBI
1.65–3.6V
1.65–3.6V
3.0–3.6V
1.65–1.95V, 3.0–3.6V
EBI_O
EBI_CLK
RSTJTAG
SYSC
VBG
USBFS
USBHS
CLOCK
DIB
1.65–1.95V, 3.0–3.6V
1.65–1.95V, 3.0–3.6V
3.0–3.6V
1.65–3.6V
0.9–1.1V
3.0–3.6V
3.0–3.6V
1.65–3.6V
3.0–3.6V
I
I/O
I/O
I/O
I/O
Analog
I
Pull-up
Switchable
Switchable
Switchable
Switchable
Switchable
Reset State
Reset State
Reset State
Pull-down
Switchable
Switchable
Switchable
Switchable
Reset State
Reset State
Reset State
Schmitt Trigger
Switchable
Switchable
Switchable
Switchable
Reset State
Reset State
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When “Reset State” is mentioned, the configuration is defined by the “Reset State” column of the Pin Description table.
Table 4-2.
SAM9X35 I/O Type Assignment and Frequency
I/O Type
I/O Frequency
(MHz)
Charge Load
(pF) Output Current
GPIO
GPIO_CLK
GPIO_CLK2
GPIO_ANA
40
54
75
25
10
10
10
10
Signal Name
All PIO lines except GPIO_CLK, GPIO_CLK2, and GPIO_ANA
MCI0CK, MCI1CK, SPI0SPCK, SPI1SPCK, EMACx_ETXCK
16 mA, 40 mA (peak) ADx, GPADx
EBI
EBI_O
EBI_CLK
RSTJTAG
SYSC
VBG
USBFS
USBHS
CLOCK
DIB
133
66
133
10
0.25
0.25
12
480
50
25
50 (3.3V)
30 (1.8V)
50 (3.3V)
30 (1.8V)
10
10
10
10
10
10
50
25
All data lines (Input/output)
All address and control lines (output only) except EBI_CLK
CK, #CK
NRST, NTRST, BMS, TCK, TDI, TMS, TDO, RTCK
WKUP, SHDN, JTAGSEL, TST, SHDN
VBG
HFSDPA, HFSDPB/DFSDP, HFSDPC, HFSDMA,
HFSDMB/DFSDM, HFSDMC
HHSDPA, HHSDPB/DHSDP, HHSDMA, HHSDMB/DHSDM
XIN, XOUT, XIN32, XOUT32
DIBN, DIBP
4.2.1
Reset State
In the tables that follow, the column “Reset State” indicates the reset state of the line with mnemonics.
“PIO” “/” signal
Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned, the PIO Line is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released.
“I”/“O”
Indicates whether the signal is input or output state.
“PU”/ “PD”
Indicates whether Pull-Up, Pull-Down or nothing is enabled.
“ST”
Indicates if Schmitt Trigger is enabled.
Note: Example: The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is configured as an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”. That means PIO Input with
Pull-Up. PD15 reset state is “A20, O, PD” which means output address line 20 with Pull-Down.
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Ball Power Rail I/O Type
L3 VDDIOP0 GPIO
P1 VDDIOP0
L4 VDDIOP0
N4 VDDIOP0
T3 VDDIOP0
R1 VDDIOP0
GPIO
GPIO
GPIO
GPIO
GPIO
R4 VDDIOP0
R3 VDDIOP0
P4 VDDIOP0
U3 VDDIOP0
T1 VDDIOP0
GPIO
GPIO
GPIO
GPIO
GPIO
U1 VDDIOP0
T2 VDDIOP0
GPIO
GPIO
T4 VDDIOP0 GPIO_CLK
U2 VDDIOP0 GPIO
U4 VDDIOP0 GPIO
P5 VDDIOP0 GPIO
R5 VDDIOP0 GPIO_CLK
U5 VDDIOP0
T5 VDDIOP0
U6 VDDIOP0
GPIO
GPIO
GPIO
T6 VDDIOP0
R6 VDDIOP0
GPIO
GPIO
U7 VDDIOP0 GPIO_CLK
T7 VDDIOP0 GPIO
T8 VDDIOP0 GPIO
R7 VDDIOP0
P8 VDDIOP0
U8 VDDIOP0
R9 VDDIOP0
R8 VDDIOP0
U9 VDDIOP0
D3 VDDANA
D4 VDDANA
D2 VDDANA
E4 VDDANA
D1 VDDANA GPIO_CLK
E3 VDDANA GPIO
B3 VDDANA GPIO_ANA
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PA31
PB0
PB1
PB2
PB3
PA26
PA27
PA28
PA29
PA30
PA21
PA22
PA23
PA24
PA25
PA16
PA17
PA18
PA19
PA20
PB4
PB5
PB6
PA11
PA12
PA13
PA14
PA15
PA6
PA7
PA8
PA9
PA10
Signal
PA0
PA1
PA2
PA3
PA4
PA5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Dir
I/O
I/O
I/O
I/O
I/O
I/O
4.3
217-ball BGA Package Pinout
Table 4-3.
Pin Description BGA217
Primary Alternate
Signal
AD7
Dir
I
TCLK2
TIOB0
TIOB1
TIOB2
TWD0
TWCK0
ERX0
ERX1
ERXER
ERXDV
MCI0_CDA
MCI0_CK
MCI0_DA1
MCI0_DA2
MCI0_DA3
TIOA0
TIOA1
TIOA2
TCLK0
TCLK1
ETXCK
EMDIO
EMDC
Signal
TXD0
RXD0
RTS0
CTS0
SCK0
TXD1
RXD1
TXD2
RXD2
DRXD
DTXD
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
MCI0_DA0
PIO Peripheral A
I
I
O
I
I
I
I/O
I/O
I/O
I/O
I
I/O
O
I/O
I/O
I/O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
O
Dir
O
I
O
I
I/O
O
O
O
I
I/O
O
I/O
O
O
I
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
TK
TF
TD
RD
RK
RF
SPI1_NPCS3
SPI1_NPCS2
RTS2
CTS2
SCK2
SPI0_NPCS3
TWD2
TWCK2
PIO Peripheral B
Signal
SPI1_NPCS1
SPI0_NPCS2
MCI1_DA1
MCI1_DA2
MCI1_DA3
CANTX1
CANRX1
SPI0_NPCS1
SPI1_NPCS0
CANRX0
CANTX0
MCI1_DA0
MCI1_CDA
MCI1_CK
I/O
I/O
I/O
I
O
I/O
I
O
Dir
O
O
I/O
I/O
I/O
O
PIO Peripheral C
Signal
Reset State
Dir
Signal, Dir, PU,
PD, ST
PIO, I, PU, ST
ETX0
ETX1
PIO, I, PU, ST
O PIO, I, PU, ST
O PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
EMDC
ETXEN
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
O PIO, I, PU, ST
O PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
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Ball Power Rail I/O Type
C2 VDDANA GPIO_ANA
C5 VDDANA GPIO_ANA
C1 VDDANA GPIO_ANA
B2 VDDANA GPIO_ANA
A3 VDDANA GPIO_ANA
B4 VDDANA GPIO_ANA
A2 VDDANA GPIO_ANA
C4 VDDANA GPIO_ANA
C3 VDDANA GPIO_ANA
A1 VDDANA GPIO_ANA
B1 VDDANA GPIO_ANA
D5 VDDANA
E2 VDDIOP1
F4 VDDIOP1
F3 VDDIOP1
H2 VDDIOP1
GPIO
GPIO
GPIO
GPIO
GPIO
E1 VDDIOP1
G4 VDDIOP1
F2 VDDIOP1
F1 VDDIOP1
G1 VDDIOP1
G3 VDDIOP1
G2 VDDIOP1
H3 VDDIOP1
J3 VDDIOP1
L2 VDDIOP1
H1 VDDIOP1 GPIO
J2 VDDIOP1 GPIO_CLK
J1 VDDIOP1
L1 VDDIOP1
K2 VDDIOP1
GPIO
GPIO
GPIO
N3 VDDIOP1
K1 VDDIOP1
M3 VDDIOP1
P3 VDDIOP1
J4 VDDIOP1
GPIO
GPIO
GPIO
GPIO
GPIO
K3 VDDIOP1
M2 VDDIOP1
P2 VDDIOP1
M1 VDDIOP1
K4 VDDIOP1
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PC19
PC20
PC21
PC22
PC23
PC14
PC15
PC16
PC17
PC18
PC24
PC25
PC26
PC27
PC28
PC9
PC10
PC11
PC12
PC13
PC4
PC5
PC6
PC7
PC8
PB18
PC0
PC1
PC2
PC3
PB13
PB14
PB15
PB16
PB17
Signal
PB7
PB8
PB9
PB10
PB11
PB12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Dir
I/O
I/O
I/O
I/O
I/O
I/O
Table 4-3.
Pin Description BGA217 (Continued)
Primary Alternate
Signal
AD8
AD9
AD10
AD11
AD0
AD1
AD2
AD3
AD4
AD5
AD6
I
I
I
I
I
Dir
I
I
I
I
I
I
LCDDAT9
LCDDAT10
LCDDAT11
LCDDAT12
LCDDAT13
LCDDAT14
LCDDAT15
LCDDAT16
LCDDAT17
LCDDAT18
IRQ
LCDDAT0
LCDDAT1
LCDDAT2
LCDDAT3
LCDDAT4
LCDDAT5
LCDDAT6
LCDDAT7
LCDDAT8
LCDDAT19
LCDDAT20
LCDDAT21
LCDDAT22
LCDDAT23
LCDDISP
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
O
O
O
O
O
O
O
PIO Peripheral A
Signal
ETXEN
ETX0
ETX1
LCDPWM
LCDVSYNC
LCDHSYNC
Dir
O
O
O
O
O
O
PIO Peripheral B
Signal
PCK1
PCK0
PWM0
PWM1
PWM2
PWM3
ADTRG
I
I
I
O
O
O
O
O
O
Dir
URXD0
PWM0
PWM1
TIOA5
TIOB5
TCLK5
PCK0
UTXD1
URXD1
PWM0
TWD1
TWCK1
TIOA3
TIOB3
TCLK3
TIOA4
TIOB4
TCLK4
UTXD0
PIO Peripheral C
Signal
Reset State
Dir
Signal, Dir, PU,
PD, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
I/O PIO, I, PU, ST
O PIO, I, PU, ST
I/O PIO, I, PU, ST
I/O PIO, I, PU, ST
I
I
PIO, I, PU, ST
I/O PIO, I, PU, ST
I/O PIO, I, PU, ST
PIO, I, PU, ST
O PIO, I, PU, ST
I PIO, I, PU, ST
O PIO, I, PU, ST
O PIO, I, PU, ST
I/O PIO, I, PU, ST
I/O PIO, I, PU, ST
PWM1
PWM2
PWM3
I
I
PIO, I, PU, ST
O PIO, I, PU, ST
O PIO, I, PU, ST
PIO, I, PU, ST
O PIO, I, PU, ST
O PIO, I, PU, ST
O PIO, I, PU, ST
O PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
RTS1
CTS1
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
O PIO, I, PU, ST
I PIO, I, PU, ST
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
12
M15 VDDNF
L14 VDDNF
M16 VDDNF
L16 VDDNF
L15 VDDNF
K17 VDDNF
J17 VDDNF
K16 VDDNF
J16 VDDNF
D10
D13
F14
VDDIOM
J14
K14
H9
H10
J9
J10
VDDNF
GNDIOM
P7 VDDIOP0
H4 VDDIOP1
M4
P6
GNDIOP
Ball Power Rail I/O Type
N1 VDDIOP1 GPIO_CLK
R2 VDDIOP1 GPIO_CLK2
N2 VDDIOP1 GPIO
P13 VDDNF
R14 VDDNF
R13 VDDNF
EBI
EBI
EBI
P15 VDDNF
P12 VDDNF
P14 VDDNF
N14 VDDNF
R15 VDDNF
M14 VDDNF
N16 VDDNF
N17 VDDNF
N15 VDDNF
K15 VDDNF
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
POWER
POWER
GND
POWER
POWER
GND
B5
B6
VDDBU
GNDBU
C6 VDDANA
D6 GNDANA
R12 VDDPLLA
T13 VDDOSC
POWER
GND
POWER
GND
POWER
POWER
Table 4-3.
Pin Description BGA217 (Continued)
Primary Alternate
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PD8
PD9
PD10
PD11
PD12
PD3
PD4
PD5
PD6
PD7
Signal
PC29
PC30
PC31
PD0
PD1
PD2
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
Signal
PIO Peripheral A
Dir Signal
LCDDEN
LCDPCK
FIQ
NANDOE
NANDWE
A21/NANDALE
A22/NANDCLE
NCS3
NWAIT
D16
D17
D18
D19
D20
D21
D22
D28
D29
D30
D31
D23
D24
D25
D26
D27
O
O
O
O
O
I
O
O
O
O
Dir
O
O
O
O
I
O
O
O
O
O
O
O
O
O
O
PIO Peripheral B
Signal
A20
A23
A24
A25
NCS2
NCS4
NCS5
O
O
O
O
O
O
O
Dir
PIO Peripheral C
Signal
SCK1
Reset State
Dir
Signal, Dir, PU,
PD, ST
I/O PIO, I, PU, ST
PCK1
PIO, I, PU, ST
O PIO, I, PU, ST
PIO, I, PU
PIO, I, PU
A21,O, PD
A22,O, PD
PIO, I, PU
PIO, I, PU
PIO, I, PU
PIO, I, PU
PIO, I, PU
PIO, I, PU
PIO, I, PU
PIO, I, PU
PIO, I, PU
PIO, I, PU
PIO, I, PU
A20, O, PD
A23, O, PD
A24, O, PD
A25, O, PD
PIO, I, PU
PIO, I, PU
PIO, I, PU
VDDIOM
VDDNF
GNDIOM
VDDIOP0
VDDIOP1
GNDIOP
VDDBU
GNDBU
VDDANA
GNDANA
VDDPLLA
VDDOSC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
13
Table 4-3.
Pin Description BGA217 (Continued)
Primary Alternate
Signal
GNDOSC
VDDCORE
GNDCORE
A9
A10
A11
A12
A13
A14
A15
A16
A4
A5
A6
A7
A8
D15
A0
A1
A2
A3
D10
D11
D12
D13
D14
D5
D6
D7
D8
D9
VDDUTMII
VDDUTMIC
GNDUTMI
D0
D1
D2
D3
D4
G17 VDDIOM
G16 VDDIOM
F17 VDDIOM
E17 VDDIOM
F16 VDDIOM
G15 VDDIOM
G14 VDDIOM
F15 VDDIOM
D17 VDDIOM
C17 VDDIOM
E16 VDDIOM
D16 VDDIOM
C16 VDDIOM
Ball Power Rail I/O Type
U13 GNDOSC GND
H14
K8
K9
VDDCORE
H8
J8
K10
GNDCORE
POWER
GND
U16 VDDUTMII POWER
T17 VDDUTMIC POWER
T16 GNDUTMI GND
D14 VDDIOM
D15 VDDIOM
A16 VDDIOM
B16 VDDIOM
A17 VDDIOM
B15 VDDIOM
C14 VDDIOM
B14 VDDIOM
A15 VDDIOM
C15 VDDIOM
D12 VDDIOM
C13 VDDIOM
A14 VDDIOM
B13 VDDIOM
A13 VDDIOM
C12 VDDIOM
J15 VDDIOM
H16 VDDIOM
H15 VDDIOM
H17 VDDIOM
EBI
EBI_O
EBI_O
EBI_O
EBI_O
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI_O
EBI_O
EBI_O
EBI_O
EBI_O
EBI_O
EBI_O
EBI_O
EBI_O
EBI_O
EBI_O
EBI_O
EBI_O
Dir
I
I
I
Signal
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
O NBS0 O
O NBS2/DQM/NWR2 O
BA0 O
Dir
PIO Peripheral A
Signal Dir
PIO Peripheral B
Signal Dir
PIO Peripheral C
Signal
Reset State
Dir
Signal, Dir, PU,
PD, ST
I
I
I
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
I
I
I
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
14
Ball Power Rail I/O Type
B17 VDDIOM EBI_O
E15 VDDIOM
E14 VDDIOM
B9 VDDIOM
B8 VDDIOM
D9 VDDIOM
EBI_O
EBI_O
EBI_O
EBI_O
EBI_O
C9 VDDIOM
C7 VDDIOM
A8 VDDIOM
D11 VDDIOM
C11 VDDIOM
B12 VDDIOM
B11 VDDIOM
C10 VDDIOM
A12 VDDIOM
C8 VDDIOM
EBI_O
EBI_O
EBI_O
EBI_CLK
EBI_CLK
EBI_O
EBI_O
EBI_O
EBI_O
EBI_O
A10 VDDIOM
B10 VDDIOM
A11 VDDIOM
A9 VDDIOM
A4 VDDANA
U17 VDDUTMIC
T14 VDDUTMII
T15 VDDUTMII
U14 VDDUTMII
U15 VDDUTMII
R16 VDDUTMII
P16 VDDUTMII
R17 VDDUTMII
P17 VDDUTMII
L17 VDDUTMII
M17 VDDUTMII
R11 VDDIOP0
P11 VDDIOP0
A7 VDDBU
D8 VDDBU
P9 VDDIOP0 RSTJTAG
D7 VDDBU SYSC
B7 VDDBU SYSC
U10 VDDIOP0 RSTJTAG
T9 VDDIOP0 RSTJTAG
EBI_O
EBI_O
EBI
EBI
POWER
VBG
USBFS
USBFS
USBHS
USBHS
USBFS
USBFS
USBHS
USBHS
USBFS
USBFS
DIB
DIB
SYSC
SYSC
HFSDPB
HFSDMB
HHSDPB
HHSDMB
HFSDPC
HFSDMC
DIBN
DIBP
WKUP
SHDN
DQM0
DQM1
DQS0
DQS1
ADVREF
VBG
HFSDPA
HFSDMA
HHSDPA
HHSDMA
BMS
JTAGSEL
TST
TCK
TDI
NWR0
NWR1
NWR3
SDCK
#SDCK
SDCKE
RAS
CAS
SDWE
SDA10
Signal
A17
A18
A19
NCS0
NCS1
NRD
I/O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
O
O
I/O
I/O
I
O
O
O
O
O
O
O
O
O
O
Dir
O
O
O
O
O
O
Table 4-3.
Pin Description BGA217 (Continued)
Primary Alternate
Signal
BA1
BA2
SDCS
NWRE
NBS1
NBS3/DQM3
DFSDP
DFSDM
DHSDP
DHSDM
O
O
O
I/O
I/O
I/O
I/O
Dir
O
O
O
PIO Peripheral A
Signal Dir
PIO Peripheral B
Signal Dir
PIO Peripheral C
Signal
Reset State
Dir
Signal, Dir, PU,
PD, ST
O, PD
O, PD
O, PD
O, PU
O, PU
O, PU
O, PU
O, PU
O, PU
O, PU
O, PU
O, PU
O, PU
O, PU
O
O
O, PD
O, PU
O, PU
I, ST
O
O, PD
O, PD
O, PD
O, PD
O, PD
I
O, PD
O, PD
O, PD
O, PD
O, PU
O, PU
O, PD
O, PD
I
I, PD, ST
I, PD
I, PD, ST
I, ST
I, ST
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
15
Table 4-3.
Pin Description BGA217 (Continued)
Primary Alternate
Ball Power Rail I/O Type
T10 VDDIOP0 RSTJTAG
U11 VDDIOP0 RSTJTAG
R10 VDDIOP0 RSTJTAG
P10 VDDIOP0 RSTJTAG
T11 VDDIOP0 RSTJTAG
A6 VDDBU CLOCK
A5 VDDBU
T12 VDDOSC
U12 VDDOSC
CLOCK
CLOCK
CLOCK
Signal
TDO
TMS
RTCK
NRST
NTRST
XIN32
XOUT32
XIN
XOUT
Dir
O
I
O
I/O
I
I
O
I
O
Signal Dir
PIO Peripheral A
Signal Dir
PIO Peripheral B
Signal Dir
PIO Peripheral C
Signal
Reset State
Dir
Signal, Dir, PU,
PD, ST
O
I, ST
O
I, PU, ST
I, PU, ST
I
O
I
O
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
16
5.
Power Considerations
5.1
Power Supplies
The SAM9X35 has several types of power supply pins.
Table 5-1.
SAM9X35 Power Supplies
Name Voltage Range, nominal Powers
VDDCORE 0.9–1.1V, 1.0V
ARM core, internal memories, internal peripherals and part of the system controller.
VDDIOM
VDDNF
VDDIOP0
VDDIOP1
VDDBU
1.65–1.95V, 1.8V
3.0–3.6V, 3.3V
1.65–1.95V, 1.8V
3.0–3.6V, 3.3V
1.65–3.6V
1.65–3.6V
1.65–3.6V
VDDUTMIC 0.9–1.1V, 1.0V
VDDUTMII 3.0–3.6V, 3.3V
VDDPLLA
VDDOSC
0.9–1.1V, 1.0V
1.65–3.6V
External Memory Interface I/O lines
NAND Flash I/O and control, D16–D31 and multiplexed SMC lines
A part of Peripheral I/O lines (1)
A part of Peripheral I/O lines (1)
The Slow Clock oscillator, the internal 32 kHz RC oscillator and backup part of the System Controller
The USB transceiver core logic
The USB transceiver interface
The PLLA and PLLUTMI cells
The Main Oscillator cells
VDDANA 3.0–3.6V, 3.3V
The Analog-to-Digital Converter
Note:
for more details.
Associated
Ground
GNDCORE
GNDIOM
GNDIOM
GNDIOP
GNDIOP
GNDBU
GNDUTMI
GNDUTMI
GNDOSC
GNDOSC
GNDANA
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
17
6.
Memories
Figure 6-1. SAM9X35 Memory Mapping
Address Memory Space
0x0000 0000
Internal Memories 256 Mbytes
0x0FFF FFFF
0x1000 0000
EBI
Chip Select 0 256 Mbytes
0x1FFF FFFF
0x2000 0000
EBI
Chip Select 1
DDR2/LPDDR
SDR/LPSDR
256 Mbytes
0x2FFF FFFF
0x3000 0000
EBI
Chip Select 2
256 Mbytes
0x3FFF FFFF
0x4000 0000
EBI
Chip Select 3
NAND Flash
256 Mbytes
0x4FFF FFFF
0x5000 0000
EBI
Chip Select 4
256 Mbytes
0x5FFF FFFF
0x6000 0000
EBI
Chip Select 5
256 Mbytes
0x6FFF FFFF
0x7000 0000
Undefined
(Abort)
1,792 Mbytes
Notes:
(1) Can be ROM, EBI1_NCS0 or SRAM depending on BMS and REMAP
0xF800 4000
0xF800 8000
0xF800 C000
0xF801 0000
0xF801 4000
0xF801 8000
0xF801 C000
0xF802 0000
0xF802 4000
0xF802 8000
0xF802 C000
0xF803 0000
0xF803 4000
0xF000 0000
0xF000 4000
0xF000 8000
0xF000 C000
0xF001 0000
0xF001 4000
Peripheral Mapping
SPI0
SPI1
HSMCI0
HSMCI1
SSC
Reserved
0xF800 0000
CAN0
CAN1
TC0, TC1, TC2
TC3, TC4, TC5
TWI0
TWI1
TWI2
USART0
USART1
USART2
Reserved
EMAC
Reserved
0xF803 8000
0xF803 C000
0xF804 0000
0xF804 4000
0xF804 8000
0xF804 C000
0xF805 0000
PWMC
LCDC
UDPHS
UART0
UART1
Reserved
TSADC
0xEFFF FFFF
0xF000 0000
Reserved
Internal Peripherals 256 Mbytes
0xFFFF FFFF
0xFFFF C000
0xFFFF FFFF
SYSC
0x0000 0000
Internal Memory Mapping
Boot Memory (1) 1 Mbyte
0x0010 0000
ROM 1 Mbyte
0x0020 0000
0x0030 0000
Undefined
(Abort)
1 Mbyte
SRAM 1 Mbyte
0x0040 0000
SMD 1 Mbyte
0x0050 0000
UDPHS RAM 1 Mbyte
0x0060 0000
UHP OHCI
1 Mbyte
0x0070 0000
UHP EHCI 1 Mbyte
0x0080 0000
Undefined
(Abort)
0x0FFF FFFF
System Controller Mapping
0xFFFF C000
Reserved
0xFFFF DE00
0xFFFF E000
0xFFFF E600
0xFFFF E800
0xFFFF EA00
0xFFFF EC00
0xFFFF EE00
0xFFFF F000
0xFFFF F200
0xFFFF F400
0xFFFF F600
0xFFFF F800
0xFFFF FA00
0xFFFF FC00
0xFFFF FE00
0xFFFF FE10
0xFFFF FE20
0xFFFF FE30
0xFFFF FE40
0xFFFF FE50
0xFFFF FE54
0xFFFF FE60
0xFFFF FE70
0xFFFF FEB0
0xFFFF FEC0
0xFFFF FFFF
512 bytes
512 bytes
512 bytes
512 bytes
512 bytes
512 bytes
16 bytes
16 bytes
16 bytes
16 bytes
16 bytes
4 bytes
12 bytes
16 bytes
16 bytes
MATRIX
PMECC
PMERRLOC
DDR2/LPDDR
SDR/LPSDR
SMC
DMAC0
DMAC1
AIC
DBGU
PIOA
PIOB
PIOC
PIOD
PMC
RSTC
SHDC
Reserved
PIT
WDT
SCKC_CR
BSC_CR
GPBR
Reserved
RTC
Reserved
512 bytes
1536 bytes
512 bytes
512 bytes
512 bytes
512 bytes
512 bytes
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
18
6.1
Memory Mapping
A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features.
Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. Banks 1 to 6 are directed to the EBI that associates these banks to the external chip selects, EBI_NCS0 to EBI_NCS5. Bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master requesting such an access.
6.2
Embedded Memories
6.2.1
Internal SRAM
The SAM9X35 embeds a total of 32 Kbytes of high-speed SRAM.
After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000.
After Remap, the SRAM also becomes available at address 0x0.
6.2.2
Internal ROM
The SAM9X35 embeds an Internal ROM, which contains the SAM-BA ® program.
At any time, the ROM is mapped at address 0x0010 0000. It is also accessible at address 0x0 (BMS = 1) after the reset and before the Remap Command.
6.3
External Memories
6.3.1
External Bus Interface
Integrates three External Memory Controllers:
Static Memory Controller
DDR2/SDRAM Controller
MLC NAND Flash ECC Controller
Additional logic for NAND Flash and CompactFlash ®
Up to 26-bit Address Bus (up to 64 MBytes linear per chip select)
Up to 6 chip selects, Configurable Assignment:
Static Memory Controller on NCS0, NCS1, NCS2, NCS3, NCS4, NCS5
DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1
Optional NAND Flash support on NCS3
6.3.2
Static Memory Controller
8-bit, 16-bit, or 32-bit Data Bus
Multiple Access Modes supported
Byte Write or Byte Select Lines
Asynchronous read in Page Mode supported (4- up to 16-byte page size)
Multiple device adaptability
Control signals programmable setup, pulse and hold time for each Memory Bank
Multiple Wait State Management
Programmable Wait State Generation
External Wait Request
Programmable Data Float Time
Slow Clock mode supported
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6.3.3
DDR2SDR Controller
Supports 4-bank and 8-bank DDR2, LPDDR, SDR and LPSDR
Numerous Configurations Supported
2K, 4K, 8K, 16K Row Address Memory Parts
SDRAM with 8 Internal Banks
SDR-SDRAM with 32-bit Data Path
DDR2/LPDDR with 16-bit Data Path
One Chip Select for SDRAM Device (256 Mbyte Address Space)
Programming Facilities
Multibank Ping-pong Access (Up to 8 Banks Opened at Same Time = Reduces Average Latency of
Transactions)
Timing Parameters Specified by Software
Automatic Refresh Operation, Refresh Rate is Programmable
Automatic Update of DS, TCR and PASR Parameters (LPSDR)
Energy-saving Capabilities
Self-refresh, Power-down and Deep Power Modes Supported
SDRAM Power-up Initialization by Software
CAS Latency of 2, 3 Supported
Auto Precharge Command Not Used
SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported
Clock Frequency Change in Precharge Power-down Mode Not Supported
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7.
System Controller
The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc.
The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories.
The System Controller’s peripherals are all mapped within the highest 16 Kbytes of address space, between addresses
0xFFFF_C000 and 0xFFFF_FFFF.
However, all the registers of System Controller are mapped on the top of the address space. All the registers of the
System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of
±
4 Kbytes.
shows the System Controller block diagram.
shows the mapping of the User Interface of the System Controller peripherals.
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Figure 7-1. SAM9X35 System Controller Block Diagram
System Controller irq fiq periph_irq[2..30] pit_irq wdt_irq dbgu_irq pmc_irq rstc_irq
MCK periph_nreset dbgu_rxd
MCK debug periph_nreset
SLCK debug idle proc_nreset
Advanced
Interrupt
Controller
NRST
VDDBU
VDDCORE
POR por_ntrst jtag_nreset int
VDDCORE Powered por_ntrst
Debug
Unit dbgu_irq dbgu_txd
Periodic
Interval
Timer pit_irq
Watchdog
Timer wdt_fault
WDRPROC wdt_irq
Reset
Controller rstc_irq periph_nreset proc_nreset backup_nreset
VDDBU Powered
VDDBU
POR
SLCK
SLCK backup_nreset
SLCK
Real-Time
Clock rtc_irq rtc_alarm
SHDN
WKUP
XIN32
XOUT32
XIN
XOUT
PA0-PA31
PB0-PB18
PC0-PC31
PD0-PD21 backup_nreset rtc_alarm
32K RC
OSC
SLOW
CLOCK
OSC SCKC_CR
SLCK
12M RC
OSC int
MAINCK
12MHz
MAIN OSC
UPLL
PLLA periph_nreset periph_nreset periph_clk[2..3] dbgu_rxd
Shut-Down
Controller
BSC_CR
UPLLCK
PLLACK
Power
Management
Controller
PIO
Controllers
4 General-purpose
Backup Registers periph_clk[2..30] pck[0-1]
UHP48M
UHP12M
PCK
MCK
DDRCK
LCD Pixel clock pmc_irq idle
SMDCK = periph_clk[4] periph_irq[2..3] irq fiq dbgu_txd nirq nfiq ntrst
ARM926EJ-S proc_nreset
PCK debug jtag_nreset
MCK periph_nreset
UPLLCK
UHP48M
UHP12M periph_nreset periph_irq[23]
USB High Speed
Host Port
UPLLCK periph_nreset periph_irq[22]
USB High Speed
Device Port
SMDCK periph_nreset periph_irq[4]
SMD
Software Modem periph_clk[5..30] periph_nreset periph_irq[5..30] in out enable
Boundary Scan
TAP Controller
Bus Matrix
Embedded
Peripherals
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7.1
Chip Identification
Chip ID: 0x819A_05A1
Chip ID Extension: 2
JTAG ID: 0x05B2_F03F
ARM926 TAP ID: 0x0792_603F
7.2
Backup Section
The SAM9X35 features a Backup Section that embeds:
RC Oscillator
Slow Clock Oscillator
Real Time Counter (RTC)
Shutdown Controller
4 Backup Registers
Slow Clock Controller Configuration Register (SCKC_CR)
Boot Sequence Configuration Register (BSC_CR)
A part of the Reset Controller (RSTC)
This section is powered by the VDDBU rail.
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8.
Peripherals
8.1
Peripheral Mapping
As shown in
, the Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xF000_0000 and 0xFFFF_C000.
Each User Peripheral is allocated 16 Kbytes of address space.
13
14
15
16
9
10
11
12
6
7
4
5
2
3
21
22
23
24
25
17
18
19
20
8.2
Peripheral Identifiers
peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power
Management Controller.
Table 8-1.
Peripheral Identifiers
Instance ID Instance Name Instance Description
0 AIC Advanced Interrupt Controller
1 SYS System Controller Interrupt
External interrupt Wired-OR interrupt
FIQ
DBGU, PMC, SYSC, PMECC,
PMERRLOC, RTSC, SHDC, PIT
WDT, RTC
PIOA,PIOB
PIOC,PIOD
SMD
USART0
USART1
USART2
TWI0
TWI1
TWI2
HSMCI0
SPI0
SPI1
UART0
UART1
TC0,TC1
PWM
ADC
DMAC0
DMAC1
UHPHS
UDPHS
EMAC
LCDC
Parallel I/O Controller A and B
Parallel I/O Controller C and D
SMD Soft Modem
USART 0
USART 1
USART 2
Two-Wire Interface 0
Two-Wire Interface 1
Two-Wire Interface 2
High Speed Multimedia Card Interface 0
Serial Peripheral Interface 0
Serial Peripheral Interface 1
UART 0
UART 1
Timer Counter 0,1,2,3,4,5
Pulse Width Modulation Controller
ADC Controller
DMA Controller 0
DMA Controller 1
USB Host High Speed
USB Device High Speed
Ethernet MAC
LCD Controller
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Table 8-1.
Peripheral Identifiers (Continued)
Instance ID Instance Name Instance Description
26 HSMCI1 High Speed Multimedia Card Interface 1
28
29
30
31
SSC
CAN0
CAN1
AIC
Synchronous Serial Controller
CAN Controller 0
CAN Controller 1
Advanced Interrupt Controller
External interrupt Wired-OR interrupt
IRQ
8.3
Peripheral Signal Multiplexing on I/O Lines
The SAM9X35 features four PIO Controllers (PIOA, PIOB, PIOC and PIOD) which multiplex the I/O lines of the peripheral set.
Each PIO Controller controls 32 lines, 19 lines, 32 lines and 22 lines respectively for PIOA, PIOB, PIOC and PIOD. Each
to see the PIO assignments.
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9.
ARM926EJ-S
™
9.1
Description
The ARM926EJ-S processor is a member of the ARM9 ™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features.
The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Java-powered wireless and embedded devices. It includes an enhanced multiplier design for improved
DSP performance.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug.
The ARM926EJ-S provides a complete high performance processor subsystem, including:
an ARM9EJ-S ™ integer core
a Memory Management Unit (MMU) separate instruction and data AMBA AHB bus interfaces
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9.2
Embedded Characteristics
ARM9EJ-S ™ Based on ARM ® Architecture v5TEJ with Jazelle Technology
Three Instruction Sets
ARM ® High-performance 32-bit Instruction Set
Thumb ® High Code Density 16-bit Instruction Set
Jazelle ® 8-bit Instruction Set
5-Stage Pipeline Architecture when Jazelle is not Used
Fetch (F)
Decode (D)
Execute (E)
Memory (M)
Writeback (W)
6-Stage Pipeline when Jazelle is Used
Fetch
Jazelle/Decode (Two Cycles)
Execute
Memory
Writeback
ICache and DCache
Virtually-addressed 4-way Set Associative Caches
8 Words per Line
Critical-word First Cache Refilling
Write-though and Write-back Operation for DCache Only
Pseudo-random or Round-robin Replacement
Cache Lockdown Registers
Cache Maintenance
Write Buffer
16-word Data Buffer
4-address Address Buffer
Software Control Drain
DCache Write-back Buffer
8 Data Word Entries
One Address Entry
Software Control Drain
Memory Management Unit (MMU)
Access Permission for Sections
Access Permission for Large Pages and Small Pages
16 Embedded Domains
64 Entry Instruction TLB and 64 Entry Data TLB
Memory Access
8-bit, 16-bit, and 32-bit Data Types
Separate AMBA AHB Buses for Both the 32-bit Data Interface and the 32-bit Instructions Interface
Bus Interface Unit
Arbitrates and Schedules AHB Requests
Enables Multi-layer AHB to be Implemented
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Increases Overall Bus Bandwidth
Makes System Architecture Mode Flexible
9.3
Block Diagram
Figure 9-1. ARM926EJ-S Internal Functional Block Diagram
External Coprocessors
CP15 System
Configuration
Coprocessor
External
Coprocessor
Interface
ETM9
Trace Port
Interface
DTCM
Interface
Write Data
Read
Data
ARM9EJ-S
Processor Core
Instruction
Fetches
Data
Address
Data TLB
Instruction
Address
MMU
Instruction
TLB
Data TCM
Data
Address
Instruction
Address
Data Cache
AHB Interface and
Write Buffer
AMBA AHB
ITCM
Interface
Instruction TCM
Instruction
Cache
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9.4
ARM9EJ-S Processor
9.4.1
ARM9EJ-S Operating States
The ARM9EJ-S processor can operate in three different states, each with a specific instruction set:
ARM state: 32-bit, word-aligned ARM instructions.
THUMB state: 16-bit, halfword-aligned Thumb instructions.
Jazelle state: variable length, byte-aligned Jazelle instructions.
In Jazelle state, all instruction Fetches are in words.
9.4.2
Switching State
The operating state of the ARM9EJ-S core can be switched between:
ARM state and THUMB state using the BX and BLX instructions, and loads to the PC
ARM state and Jazelle state using the BXJ instruction
All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler.
9.4.3
Instruction Pipelines
The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor.
A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch, Decode, Execute,
Memory and Writeback stages.
A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles),
Execute, Memory and Writeback stages.
9.4.4
Memory Access
The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to fourbyte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary.
Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S control logic automatically detects these cases and stalls the core or forward data.
9.4.5
Jazelle Technology
The Jazelle technology enables direct and efficient execution of Java byte codes on ARM processors, providing high performance for the next generation of Java-powered wireless and embedded devices.
The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java mode will appear as another state: instead of executing ARM or Thumb instructions, it executes Java byte codes. The
Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of
ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode.
Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte codes, whether in hardware or in software.
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9.4.6
ARM9EJ-S Operating Modes
In all states, there are seven operation modes:
User mode is the usual ARM program execution state. It is used for executing most application programs
Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process
Interrupt (IRQ) mode is used for general-purpose interrupt handling
Supervisor mode is a protected mode for the operating system
Abort mode is entered after a data or instruction prefetch abort
System mode is a privileged user mode for the operating system
Undefined mode is entered when an undefined instruction exception occurs
Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources.
9.4.7
ARM9EJ-S Registers
The ARM9EJ-S core has a total of 37 registers.
31 general-purpose 32-bit registers
6 32-bit status registers
shows all the registers in all modes.
Table 9-1.
ARM9TDMI Modes and Registers Layout
User and System Mode Supervisor Mode Abort Mode Undefined Mode
R0
R1
R0
R1
R0
R1
R0
R1
R2
R3
R4
R5
R2
R3
R4
R5
R2
R3
R4
R5
R2
R3
R4
R5
R10
R11
R12
R13
R6
R7
R8
R9
R14
PC
R6
R7
R8
R9
R10
R11
R12
R13_SVC
R14_SVC
PC
R6
R7
R8
R9
R10
R11
R12
R13_ABORT
R14_ABORT
PC
R6
R7
R8
R9
R10
R11
R12
R13_UNDEF
R14_UNDEF
PC
Interrupt Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_IRQ
R14_IRQ
PC
Fast Interrupt Mode
R0
R1
R2
R3
R4
R5
R6
R7
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
PC
CPSR CPSR
SPSR_SVC
CPSR
SPSR_ABO
RT
CPSR
SPSR_UNDEF
CPSR
SPSR_IRQ
CPSR
SPSR_FIQ
Mode-specific banked registers
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The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current
Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed.
Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains condition code flags and the current mode bits.
In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another register called
Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode.
In all modes and due to a software agreement, register r13 is used as stack pointer.
The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which defines:
Constraints on the use of registers
Stack conventions
Argument passing and result return
For more details, refer to ARM Software Development Kit.
The Thumb state register set is a subset of the ARM state set. The programmer has direct access to:
Eight general-purpose registers r0-r7
Stack pointer, SP
Link register, LR (ARM r14)
PC
CPSR
There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S
Technical Reference Manual, revision r1p2 page 2-12).
9.4.7.1 Status Registers
The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers:
Hold information about the most recently performed ALU operation
Control the enabling and disabling of interrupts
Set the processor operation mode
Figure 9-2. Status Register Format
31 30 29 28 27
N Z C V Q
24
J Reserved
7 6 5
I F T Mode
0
Jazelle state bit
Reserved
Sticky Overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
Mode bits
Thumb state bit
FIQ disable
IRQ disable
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Figure 9-2 shows the status register format, where:
N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD,
QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations.
The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag.
The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where:
J = 0: The processor is in ARM or Thumb state, depending on the T bit
J = 1: The processor is in Jazelle state.
Mode: five bits to encode the current processor mode
9.4.7.2 Exceptions
Exception Types and Priorities
The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privileged mode. The types of exceptions are:
Fast interrupt (FIQ)
Normal interrupt (IRQ)
Data and Prefetched aborts (Abort)
Undefined instruction (Undefined)
Software interrupt and Reset (Supervisor)
When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state.
More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to the following priority order:
Reset (highest priority)
Data Abort
FIQ
IRQ
Prefetch Abort
BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority)
The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive.
Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection.
Exception Modes and Handling
Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral.
When handling an ARM exception, the ARM9EJ-S core performs the following operations:
1.
Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been entered. When the exception entry is from:
ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15)
+ 4 or PC + 8 depending on the exception).
THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or
PC + 8 depending on the exception) that causes the program to resume from the correct place on return.
2.
Copies the CPSR into the appropriate SPSR.
3.
Forces the CPSR mode bits to a value that depends on the exception.
4.
Forces the PC to fetch the next instruction from the relevant exception vector.
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The register r13 is also banked across exception modes to provide each exception handler with private stack pointer.
The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions.
When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR.
The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching.
The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a
Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place.
The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the Prefetch
Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort.
A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place.
9.4.8
ARM Instruction Set Overview
The ARM instruction set is divided into:
Branch instructions
Data processing instructions
Status register transfer instructions
Load and Store instructions
Coprocessor instructions
Exception-generating instructions
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]).
For further details, see the ARM Technical Reference Manual.
gives the ARM instruction mnemonic list.
Table 9-2.
ARM Instruction Mnemonic List
Mnemonic Operation
MOV
ADD
SUB
RSB
CMP
TST
AND
EOR
MUL
SMULL
SMLAL
MSR
B
Move
Add
Subtract
Reverse Subtract
Compare
Test
Logical AND
Logical Exclusive OR
Multiply
Sign Long Multiply
Signed Long Multiply
Accumulate
Move to Status Register
Branch
Mnemonic
MVN
ADC
SBC
RSC
CMN
TEQ
BIC
ORR
MLA
UMULL
UMLAL
MRS
BL
Operation
Move Not
Add with Carry
Subtract with Carry
Reverse Subtract with Carry
Compare Negated
Test Equivalence
Bit Clear
Logical (inclusive) OR
Multiply Accumulate
Unsigned Long Multiply
Unsigned Long Multiply
Accumulate
Move From Status Register
Branch and Link
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Table 9-2.
ARM Instruction Mnemonic List (Continued)
Mnemonic Operation Mnemonic
BX
LDR
LDRSH
LDRSB
LDRH
LDRB
LDRBT
LDRT
LDM
SWP
MCR
LDC
CDP
Branch and Exchange
Load Word
Load Signed Halfword
Load Signed Byte
Load Half Word
Load Byte
Load Register Byte with
Translation
Load Register with
Translation
Load Multiple
Swap Word
Move To Coprocessor
Load To Coprocessor
Coprocessor Data
Processing
SWI
STR
STRH
STRB
STRBT
STRT
STM
SWPB
MRC
STC
Operation
Software Interrupt
Store Word
Store Half Word
Store Byte
Store Register Byte with
Translation
Store Register with
Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
9.4.9
New ARM Instruction Set
Table 9-3.
New ARM Instruction Mnemonic List
Mnemonic Operation Mnemonic
BXJ
Branch and exchange to
Java
MRRC
BLX
Branch, Link and exchange MCR2
SMLAxy
SMLAL
SMLAWy
SMULxy
SMULWy
QADD
QDADD
QSUB
QDSUB
Signed Multiply Accumulate
16 * 16 bit
Signed Multiply Accumulate
Long
Signed Multiply Accumulate
32 * 16 bit
Signed Multiply 16 * 16 bit
Signed Multiply 32 * 16 bit
Saturated Add
Saturated Add with Double
Saturated subtract
Saturated Subtract with double
MCRR
CDP2
BKPT
PLD
STRD
STC2
LDRD
LDC2
CLZ
Operation
Move double from coprocessor
Alternative move of ARM reg to coprocessor
Move double to coprocessor
Alternative Coprocessor
Data Processing
Breakpoint
Soft Preload, Memory prepare to load from address
Store Double
Alternative Store from
Coprocessor
Load Double
Alternative Load to
Coprocessor
Count Leading Zeroes
Notes: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
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9.4.10 Thumb Instruction Set Overview
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Branch instructions
Data processing instructions
Load and Store instructions
Load and Store multiple instructions
Exception-generating instruction
Table 5 shows the Thumb instruction set, for further details, see the ARM Technical Reference Manual.
gives the Thumb instruction mnemonic list.
Table 9-4.
Thumb Instruction Mnemonic List
Mnemonic Operation
ASR
MUL
B
BX
LDR
LDRH
LDRB
LDRSH
MOV
ADD
SUB
CMP
TST
AND
EOR
LSL
LDMIA
PUSH
BCC
Move
Add
Subtract
Compare
Test
Logical AND
Logical Exclusive OR
Logical Shift Left
Arithmetic Shift Right
Multiply
Branch
Branch and Exchange
Load Word
Load Half Word
Load Byte
Load Signed Halfword
Load Multiple
Push Register to stack
Conditional Branch
Mnemonic Operation
ROR
BLX
BL
SWI
STR
STRH
STRB
LDRSB
MVN
ADC
SBC
CMN
NEG
BIC
ORR
LSR
STMIA
POP
BKPT
Move Not
Add with Carry
Subtract with Carry
Compare Negated
Negate
Bit Clear
Logical (inclusive) OR
Logical Shift Right
Rotate Right
Branch, Link, and Exchange
Branch and Link
Software Interrupt
Store Word
Store Half Word
Store Byte
Load Signed Byte
Store Multiple
Pop Register from stack
Breakpoint
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9.5
CP15 Coprocessor
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below:
ARM9EJ-S
Caches (ICache, DCache and write buffer)
TCM
MMU
Other system options
To control these features, CP15 provides 16 additional registers. See Table 9-5
.
Table 9-5.
CP15 Registers
Register
0
0
0
Name
ID Code
Cache type
1
2
Control
Translation Table Base
6
7
4 Reserved
5
5
Instruction fault status
Fault Address
Cache Operations
8
9
9
TLB operations
TCM region
TLB lockdown 10
11
12
13
13
Reserved
Reserved
FCSE PID
14 Reserved
Read/Write
Read/Unpredictable
Read/Unpredictable
Read/Unpredictable
Read/write
Read/write
Read/write
None
Read/write
Read/write
Read/write
Read/Write
Unpredictable/Write
Read/write
Read/write
Read/write
None
None
Read/write
Read/Write
None
Read/Write
Notes: 1. Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field.
2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field.
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9.5.1
CP15 Registers Access
CP15 registers can only be accessed in privileged mode by:
MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15.
MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register.
Other instructions like CDP, LDC, STC can cause an undefined instruction exception.
The assembler code for these instructions is:
MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
The MCR, MRC instructions bit pattern is shown below:
31 30 cond
29 28 27
1
19
26
1
18
25
1
17
24
0
16 23 22 opcode_1
14
21 20
L
12
CRn
15
Rd
13 11
1
3
10
1
2
9
1
1
8
1
0 7 6 opcode_2
5 4
1 CRm
• CRm[3:0]: Specified Coprocessor Action
Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior.
• opcode_2[7:5]
Determines specific coprocessor operation code. By default, set to 0.
• Rd[15:12]: ARM Register
Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable.
• CRn[19:16]: Coprocessor Register
Determines the destination coprocessor register.
• L: Instruction Bit
0 = MCR instruction
1 = MRC instruction
• opcode_1[23:20]: Coprocessor Code
Defines the coprocessor specific code. Value is c15 for CP15.
• cond [31:28]: Condition
For more details, see Chapter 2 in ARM926EJ-S TRM.
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9.6
Memory Management Unit (MMU)
The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS, WindowsCE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations.
The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast
Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that correspond to the virtual address.
The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table.
The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny pages.
Table 7 shows the different attributes of each page in the physical memory.
Table 9-6.
Mapping Details
Mapping Name Mapping Size
Section
Large Page
1M byte
64K bytes
Small Page
Tiny Page
4K bytes
1K byte
Access Permission By
Section
4 separated subpages
4 separated subpages
Tiny Page
Subpage Size
-
16K bytes
-
1K byte
The MMU consists of:
Access control logic
Translation Look-aside Buffer (TLB)
Translation table walk hardware
9.6.1
Access Control Logic
The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are used to qualify the access or whether they should be ignored.
The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page).
9.6.2
Translation Look-aside Buffer (TLB)
The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modified Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort.
If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory.
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9.6.3
Translation Table Walk Hardware
The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB.
The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access.
There are three sizes of page-mapped accesses and one size of section-mapped access. Page-mapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A sectionmapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.
9.6.4
MMU Faults
The MMU generates an abort on the following types of faults:
Alignment faults (for data accesses only)
Translation faults
Domain faults
Permission faults
The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. It also retains the status of faults generated by instruction fetches in the instruction fault status register.
The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S
Technical Reference Manual.
9.7
Caches and Write Buffer
The ARM926EJ-S contains a 16KB Instruction Cache (ICache), a 16KB Data Cache (DCache), and a write buffer.
Although the ICache and DCache share common features, each still has some specific mechanisms.
The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified
Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and
DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement.
A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping.
This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line.
The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and
CP15 register 9 (cache lockdown).
9.7.1
Instruction Cache (ICache)
The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit.
When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating.
When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page
4-4 in ARM926EJ-S TRM).
On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset.
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9.7.2
Data Cache (DCache) and Write Buffer
ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are closely connected.
9.7.2.1 DCache
The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks.
Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating every time a context switch occurs.
The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing modified lines back to external memory. This means that the MMU is not involved in write-back operations.
Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory.
DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page
4-5 in ARM926EJ-S TRM).
The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables.
The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines.
The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table.
9.7.2.2 Write Buffer
The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and write-back region. It also allows to avoid stalling the processor when writes to external memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed (typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks.
DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page descriptor within the MMU translation tables.
Write-though Operation
When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory.
Write-back Operation
When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory.
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9.8
Bus Interface Unit
The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture.
The multi-master bus architecture has a number of benefits:
It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture.
Each AHB layer becomes simple because it only has one master, so no arbitration or master-to-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions.
The arbitration becomes effective when more than one master wants to access the same slave simultaneously.
9.8.1
Supported Transfers
The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words.
Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that the Atmel bus is
AHB-Lite protocol compliant, hence it does not support split and retry requests.
Table 8 gives an overview of the supported transfers and different kinds of transactions they are used for.
Table 9-7.
Supported Transfers
HBurst[2:0] Description
SINGLE
INCR4
INCR8
WRAP8
Single transfer
Single transfer of word, half word, or byte:
data write (NCNB, NCB, WT, or WB that has missed in DCache) data read (NCNB or NCB)
NC instruction fetch (prefetched and non-prefetched) page table walk read
Four-word incrementing burst
Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB,
NCB, WT, or WB write.
Eight-word incrementing burst Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write.
Eight-word wrapping burst Cache linefill
9.8.2
Thumb Instruction Fetches
All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the
ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.
9.8.3
Address Alignment
The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries.
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10.
Debug and Test
10.1 Description
The SAM9X35 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit
Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug
Communication Channel.
A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment.
10.2 Embedded Characteristics
ARM926 Real-time In-circuit Emulator
Two real-time Watchpoint Units
Two Independent Registers: Debug Control Register and Debug Status Register
Test Access Port Accessible through JTAG Protocol
Debug Communications Channel
Debug Unit
Two-pin UART
Debug Communication Channel Interrupt Handling
Chip ID Register
IEEE1149.1 JTAG Boundary-scan on All Digital Pins
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10.3 Block Diagram
Figure 10-1. Debug and Test Block Diagram
Boundary
Port
ICE/JTAG
TAP
Reset and
Test
TMS
TCK
TDI
NTRST
JTAGSEL
TDO
RTCK
POR
TST
ARM9EJ-S ICE-RT
ARM926EJ-S
DMA
TAP: Test Access Port
DBGU
DTXD
DRXD
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10.4 Application Examples
10.4.1 Debug Environment
functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface.
Figure 10-2. Application Debug and Trace Environment Example
Host Debugger
ICE/JTAG
Interface
ICE/JTAG
Connector
SAM9
RS232
Connector
SAM9-based Application Board
Terminal
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10.4.2 Test Environment
shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the
“board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain.
Figure 10-3. Application Test Environment Example
Test Adaptor
Tester
JTAG
Interface
ICE/JTAG
Connector
Chip n Chip 2
SAM9
Chip 1
SAM9-based Application Board In Test
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10.5 Debug and Test Pin Description
Table 10-1. Debug and Test Pin List
Pin Name Function
NRST
TST
Reset/Test
Microcontroller Reset
Test Mode Select
ICE and JTAG
NTRST
TCK
TDI
TDO
Test Reset Signal
Test Clock
Test Data In
Test Data Out
TMS
RTCK
JTAGSEL
DRXD
DTXD
Test Mode Select
Returned Test Clock
JTAG Selection
Debug Unit
Debug Receive Data
Debug Transmit Data
Type
Input/Output
Input
Active Level
Low
High
Low Input
Input
Input
Output
Input
Output
Input
Input
Output
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10.6 Functional Description
10.6.1 Test Pin
One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test.
10.6.2 EmbeddedICE ™
The ARM9EJ-S EmbeddedICE-RT ™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system.
There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of the
EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port.
EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed.
For further details on the EmbeddedICE-RT, see the ARM document:
ARM9EJ-S Technical Reference Manual (DDI 0222A).
10.6.3 JTAG Signal Description
TMS is the Test Mode Select input which controls the transitions of the test interface state machine.
TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction
Register, or other data registers).
TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit.
NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods.
TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on ARM926EJ-S cores is
1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768
kHz slow clock.
RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators.
From some ICE Interface probes, this return signal can be used to synchronize the TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE
Mode and not in boundary scan mode.
10.6.4 Debug Unit
The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum.
The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface.
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A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration.
The device Debug Unit Chip ID value is 0x819A_05A1 on 32-bit width.
For further details on the Debug Unit, see the Debug Unit section.
10.6.5 IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
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10.6.6 JTAG ID Code Register
Access: Read-only
31 30
VERSION
29
23 22 21
15
7
28 27
20
PART NUMBER
19
14
PART NUMBER
13
6
12 11
5 4
MANUFACTURER IDENTITY
3
• VERSION[31:28]: Product Version Number
Set to 0x0.
• PART NUMBER[27:12]: Product Part Number
Product part Number is 0x5B2F
• MANUFACTURER IDENTITY[11:1]
Set to 0x01F.
Bit[0] required by IEEE Std. 1149.1.
Set to 0x1.
JTAG ID Code value is 0x05B2_F03F.
26
PART NUMBER
25
18 17
10 9
MANUFACTURER IDENTITY
2 1
8
0
1
24
16
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11.
Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed thanks to the BMS pin. This allows the user to layout the ROM or an external memory to 0x0. The sampling of the BMS pin is done at reset.
If BMS is detected at 0 , the controller boots on the memory connected to Chip Select 0 of the External Bus Interface.
In this boot mode, the chip starts with its default parameters (all registers in their reset state), including as follows:
The main clock is the on-chip 12 MHz RC oscillator
The Static Memory Controller is configured with its default parameters
The user software in the external memory performs a complete configuration:
Enable the 32768 Hz oscillator if best accuracy is needed
Program the PMC (main oscillator enable or bypass mode)
Program and Start the PLL
Reprogram the SMC setup, cycle, hold, mode timing registers for EBI CS0, to adapt them to the new clock
Switch the system clock to the new value
If BMS is detected at 1 , the boot memory is the embedded ROM and the Boot Program described below is executed.
(
) .
11.1 ROM Code
The ROM Code is a boot program contained in the embedded ROM. It is also called “First level bootloader”.
The ROM Code performs several steps:
Basic chip initialization: XTal or external clock frequency detection
Attempt to retrieve a valid code from external non-volatile memories (NVM)
Execution of a monitor called SAM-BA Monitor, in case no valid application has been found on any NVM
11.2 Flow Diagram
The ROM Code implements the algorithm shown below in
Figure 11-1. ROM Code Algorithm Flow Diagram
Chip Setup
Valid boot code found in one
NVM
No
SAM-BA Monitor
Yes
Copy and run it in internal SRAM
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11.3 Chip Setup
At boot start-up, the processor clock (PCK) and the master clock (MCK) source is the 12 MHz Fast RC Oscillator.
Initialization follows the steps described below:
1.
Stack setup for ARM supervisor mode.
2.
Main Oscillator Detection: the Main Clock is switched to the 32 kHz RC oscillator to allow external clock frequency to be measured. Then the Main Oscillator is enabled and set in bypass mode. If the MOSCSELS bit rises, an external clock is connected, and the next step is Main Clock Selection (3) .
If not, the bypass mode is cleared to attempt external quartz detection. This detection is successful when the MOSCXTS and MOSCSELS bits rise, else the 12 MHz Fast RC internal oscillator is used as the Main Clock.
3.
Main Clock Selection : the Master Clock source is switched from the Slow Clock to the Main Oscillator without prescaler. The PMC Status Register is polled to wait for MCK Ready. PCK and MCK are now the Main Clock.
4.
C variable initialization: non zero-initialized data is initialized in the RAM (copy from ROM to RAM). Zero-initialized data is set to 0 in the RAM.
5.
PLLA initialization : PLLA is configured to get a PCK at 96 MHz and an MCK at 48 MHz. If an external clock or crystal frequency running at 12 MHz is found, then the PLLA is configured to allow communication on the USB link for the SAM-BA Monitor; else the Main Clock is switched to the internal 12 MHz Fast RC, but USB will not be activated..
Table 11-1. External Clock and Crystal Frequencies allowed for Boot Sequence (in MHz)
Boot Sequence
Boot on External Memories
SAM-BA Monitor through DBGU
≤ 4
Yes
Yes
12
Yes
Yes
≥ 28
Yes
Yes
SAM-BA Monitor through USB No Yes No
Note that if the clock frequency is provided not at 12 MHz but between 4 and 28 MHz, it is considered by the ROM Code as the 12 MHz clock frequency, and the PLL settings are configured accordingly.
11.4 NVM Boot
11.4.1 NVM Boot Sequence
The boot sequence on external memory devices can be controlled using the Boot Sequence Configuration Register
(BSC_CR). The 3 LSBs of the BSC_CR are available to control the sequence. See the “Boot Sequence Controller
(BSC)” section for more details.
The user can then choose to bypass some steps shown in
Figure 11-2 “NVM Bootloader Sequence Diagram”
according to the BSC_CR Value.
6
7
4
5
2
3
0
1
Table 11-2. Boot Sequence Configuration Register Values
BOOT Value
SPI0 NPCS0 SDCard
NAND
Flash SPI0 NPCS1 TWI EEPROM
Y
Y
Y
Y
Y
-
-
-
Y
Y
-
-
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
-
SAM-BA
Monitor
Y
Y
Y
Y
Y
Y
Y
Y
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Figure 11-2. NVM Bootloader Sequence Diagram
Device
Setup
SPI0 CS0 Flash Boot
Yes Copy from
SPI Flash to SRAM
No
SD Card Boot
Yes Copy from
SD Card to SRAM
No
NAND Flash Boot
Yes Copy from
NAND Flash to SRAM
No
SPI0 CS1 Flash Boot
Yes Copy from
SPI Flash to SRAM
No
TWI EEPROM Boot
Yes Copy from
TWI EEPROM to SRAM
No
SAM-BA
Monitor
Run
Run
Run
Run
Run
SPI Flash Bootloader
SD Card Bootloader
NAND Flash Bootloader
SPI Flash Bootloader
TWI EEPROM Bootloader
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11.4.2 NVM Bootloader Program Description
Figure 11-3. NVM Bootloader Program Diagram
Start
Initialize NVM
Initialization OK ?
Yes
Valid code detection in NVM
No
Restore the reset values for the peripherals and
Jump to next boot solution
NVM contains valid code
No
Yes
Copy the valid code from external NVM to internal SRAM.
Restore the reset values for the peripherals.
Perform the REMAP and set the PC to 0 to jump to the downloaded application
End
The NVM bootloader program first initializes the PIOs related to the NVM device. Then it configures the right peripheral depending on the NVM and tries to access this memory. If the initialization fails, it restores the reset values for the PIO and the peripheral and then tries the same operations on the next NVM of the sequence.
If the initialization is successful, the NVM bootloader program reads the beginning of the NVM and determines if the NVM contains valid code.
If the NVM does not contain valid code, the NVM bootloader program restores the reset value for the peripherals and then tries the same operations on the next NVM of the sequence.
If valid code is found, this code is loaded from NVM into internal SRAM and executed by branching at address
0x0000_0000 after remap. This code may be the application code or a second-level bootloader. All the calls to functions are PC relative and do not use absolute addresses.
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Figure 11-4. Remap Action after Download Completion
0x0000_0000
REMAP
Internal
ROM
0x0010_0000
Internal
ROM
0x0030_0000
Internal
SRAM
0x0000_0000
Internal
SRAM
0x0010_0000
Internal
ROM
0x0030_0000
Internal
SRAM
11.4.3 Valid Code Detection
There are two kinds of valid code detection.
11.4.3.1 ARM Exception Vectors Check
The NVM bootloader program reads and analyzes the first 28 bytes corresponding to the first seven ARM exception vectors. Except for the sixth vector, these bytes must implement the ARM instructions for either branch or load PC with
PC relative addressing.
Figure 11-5. LDR Opcode
31 28 27 24 23 20 19
1 1 1 0 0 1 I P U 1 W 0 Rn
16 15
Rd
12 11
Offset
0
Figure 11-6. B Opcode
31 28 27 24 23
1 1 1 0 1 0 1 0
0
O set (24 bits)
Unconditional instruction: 0xE for bits 31 to 28
Load PC with PC relative addressing instruction:
Rn = Rd = PC = 0xF
I==0 (12-bit immediate value)
P==1 (pre-indexed)
U offset added (U==1) or subtracted (U==0)
W==1
The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with the user’s own vector. This information is described below.
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Figure 11-7. Structure of the ARM Vector 6
31
Size of the code to download in bytes
0
The value has to be smaller than 24 kbytes. This size is the internal SRAM size minus the stack size used by the ROM
Code at the end of the internal SRAM.
Example
An example of valid vectors follows:
00 ea000006
04
08 eafffffe ea00002f
0c
10
14
18 eafffffe eafffffe
00001234 eafffffe
B0x20
B0x04
B_main
B0x0c
B0x10
B0x14 <- Code size = 4660 bytes
B0x18
11.4.3.2 boot.bin File Check
This method is the one used on FAT formatted SDCard. The boot program must be a file named “ boot.bin
” written in the root directory of the filesystem. Its size must not exceed the maximum size allowed: 24 kbytes (0x6000).
11.4.4 Detailed Memory Boot Procedures
11.4.4.1 NAND Flash Boot: NAND Flash Detection
After NAND Flash interface configuration, a reset command is sent to the memory.
The Boot Program first tries to find valid software on a NAND Flash device connected to EBI CS3, with data lines connected to D0-D7, then on NAND Flash connected to D16-D23. Hardware ECC detection and correction are provided by the PMECC peripheral (refer to the PMECC section in the datasheet for more information).
The Boot Program is able to retrieve NAND Flash parameters and ECC requirements using two methods as follows:
the detection of a specific header written at the beginning of the first page of NAND Flash, or
through the ONFI parameters for ONFI compliant memories.
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Figure 11-8. Boot NAND Flash Download
S t a rt
Initi a lize NAND Fl as h interf a ce
S end Re s et comm a nd
Fir s t p a ge cont a in s v a lid he a der
No
NAND Fl as h i s ONFI Compli a nt
No
Ye s Ye s
Re a d NAND Fl as h a nd PMECC p a r a meter s
from the he a der
Re a d NAND Fl as h a nd PMECC p a r a meter s
from the ONFI
Copy the v a lid code from extern a l NVM to intern a l S RAM.
Re s tore the re s et v a l u e s for the peripher a l s .
Perform the REMAP a nd s et the PC to 0 to j u mp to the downlo a ded a pplic a tion
End
Re s tore the re s et v a l u e s for the peripher a l s a nd
J u mp to next b oot ab le memory
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NAND Flash Specific Header Detection
This is the first method used to determine NAND Flash parameters. After Initialization and Reset command, the Boot
Program reads the first page without ECC check, to determine if the NAND parameter header is present. The header is made of 52 times the same 32-bit word (for redundancy reasons) which must contain NAND and PMECC parameters used to correctly perform the read of the rest of the data in the NAND. This 32-bit word is described below:
31
23
15
7
30 29 28 key
22 21 eccOffset
20
14 eccBitReq
6 spareSize
13
5
12
4
• usePmecc: Use PMECC
0 = Do not use PMECC to detect and correct the data.
1 = Use PMECC to detect and correct the data.
27
-
19
11
3
26
18
10 spareSize
2 nbSectorPerPage
25 eccOffset
17 sectorSize
24
16
9 8
1 0 usePmecc
• nbSectorPerPage: Number of sectors per page
• spareSize: Size of the spare zone in bytes
• eccBitReq: Number of ECC bits required
• sectorSize: Size of the ECC sector
0 = for 512 bytes.
1 = for 1024 bytes per sector.
Other value for future use.
• eccOffset: Offset of the first ECC byte in the spare zone
A value below 2 is not allowed and will be considered as 2.
• key: value 0xC must be written here to validate the content of the whole word.
If the header is valid, the Boot Program will continue with the detection of valid code.
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ONFI 2.2 Parameters
In case no valid header has been found, the Boot Program will check if the NAND Flash is ONFI compliant, sending a
Read Id command (0x90) with 0x20 as parameter for the address. If the NAND Flash is ONFI compliant, the Boot
Program retrieves the following parameters with the help of the Get Parameter Page command:
Number of bytes per page (byte 80)
Number of bytes in spare zone (byte 84)
Number of ECC bit correction required (byte 112)
ECC sector size: by default set to 512 bytes, or 1024 bytes if the ECC bit capability above is 0xFF
By default, ONFI NAND Flash detection will turn ON the usePmecc parameter, and ECC correction algorithm is automatically activated.
Once the Boot Program retrieves the parameter, using one of the two methods described above, it will read the first page again, with or without ECC, depending on the usePmecc parameter. Then it looks for a valid code programmed just after the header offset 0xD0. If the code is valid, the program is copied at the beginning of the internal SRAM.
Note: Booting on 16-bit NAND Flash is not possible, only 8-bit NAND Flash memories are supported.
11.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction
NAND Flash boot procedure uses PMECC to detect and correct errors during NAND Flash read operations in two cases:
when the usePmecc flag is set in the specific NAND header. If the flag is not set, no ECC correction is performed during NAND Flash page read.
when the NAND Flash has been detected using ONFI parameters.
The ROM code embeds the software used in the process of ECC detection/correction: the Galois Field tables, and the function PMECC_CorrectionAlgo(). The user does not need to embedd it in other software.
This function can be called by user software when PMECC status returns errors after a read page command.
Its address can be retrieved by reading the third vector of the ROM Code interrupt vector table, at address 0x100008.
The API of this function is: unsigned int PMECC_CorrectionAlgo(AT91PS_PMECC pPMECC,
AT91PS_PMERRLOC pPMERRLOC,
PMECC_paramDesc_struct *PMECC_desc,
unsigned int PMECC_status,
unsigned int pageBuffer) pPMECC : pointer to the PMECC base address, pPMERRLOC : pointer to the PMERRLOC base address,
PMECC_desc : pointer to the PMECC descriptor,
PMECC_status : the status returned by the read of PMECCISR register; pageBuffer : address of the buffer containing the page to be corrected.
The PMECC descriptor structure is: typedef struct _PMECC_paramDesc_struct {
unsigned int pageSize;
unsigned int spareSize;
unsigned int sectorSize; // 0 for 512, 1 for 1024 bytes
unsigned int errBitNbrCapability;
unsigned int eccSizeByte;
unsigned int eccStartAddr;
unsigned int eccEndAddr;
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unsigned int nandWR;
unsigned int spareEna;
unsigned int modeAuto;
unsigned int clkCtrl;
unsigned int interrupt;
int tt;
int mm;
int nn;
short *alpha_to;
short *index_of;
short partialSyn[100];
short si[100];
/* sigma table */
short smu[TT_MAX + 2][2 * TT_MAX + 1];
/* polynom order */
short lmu[TT_MAX + 1];
} PMECC_paramDesc_struct;
The Galois field tables are mapped in the ROM just after the ROM code, as described in
below:
Figure 11-9. Galois Field Table Mapping
0x0010_0000
ROM Code
0x0010_8000
0x0011_0000
Galois field tables for
512-byte sectors correction
Galois field tables for
1024-byte sectors correction
For a full description and an example of how to use the PMECC detection and correction feature, refer to the software package dedicated to this device on Atmel’s web site.
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11.4.4.3 SD Card Boot
The SD Card bootloader uses MCI0. It looks for a “ boot.bin
” file in the root directory of a FAT12/16/32 formatted SD
Card.
Supported SD Card Devices
SD Card Boot supports all SD Card memories compliant with SD Memory Card Specification V2.0. This includes SDHC cards.
11.4.4.4 SPI Flash Boot
Two kinds of SPI Flash are supported: SPI Serial Flash and SPI DataFlash.
The SPI Flash bootloader tries to boot on SPI0 Chip Select 0, first looking for SPI Serial Flash, and then for SPI
DataFlash.
It uses only one valid code detection: analysis of ARM exception vectors.
The SPI Flash read is done by means of a Continuous Read command from address 0x0. This command is 0xE8 for
DataFlash and 0x0B for Serial Flash devices.
Supported DataFlash Devices
The SPI Flash Boot program supports all Atmel DataFlash devices.
Table 11-3. DataFlash Device
Device
AT45DB011
AT45DB021
AT45DB041
AT45DB081
AT45DB161
AT45DB321
AT45DB642
Density
1 Mbit
2 Mbits
4 Mbits
8 Mbits
16 Mbits
32 Mbits
64 Mbits
Page Size (bytes)
264
264
264
264
528
528
1056
Number of Pages
512
1024
2048
4096
4096
8192
8192
Supported Serial Flash Devices
The SPI Flash Boot program supports all SPI Serial Flash devices responding correctly at both Get Status and
Continuous Read commands.
11.4.4.5 TWI EEPROM Boot
The TWI EEPROM Bootloader uses the TWI0. It uses only one valid code detection. It analyzes the ARM exception vectors.
Supported TWI EEPROM Devices
TWI EEPROM Boot supports all I 2 C-compatible TWI EEPROM memories using 7-bit device address 0x50.
11.4.5 Hardware and Software Constraints
The NVM drivers use several PIOs in peripheral mode to communicate with external memory devices. Care must be taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and electrical conflicts between output pins used by the NVM drivers and the connected devices may occur.
To assure correct functionality, it is recommended to plug in critical devices to other pins not used by NVM.
sequence for a period of less than 1 second if no correct boot program is found.
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Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state.
Table 11-4. PIO Driven during Boot Program Execution
NVM Bootloader Peripheral
EBI CS3 SMC
EBI CS3 SMC
Pin
NANDOE
NANDWE
NAND
EBI CS3 SMC
EBI CS3 SMC
EBI CS3 SMC
NANDCS
NAND ALE
NAND CLE
SD Card
EBI CS3 SMC
MCI0
MCI0
MCI0
MCI0
Cmd/Addr/Data
MCI0_CK
MCI0_D0
MCI0_D1
MCI0_D2
SPI Flash
TWI0 EEPROM
SAM-BA Monitor
MCI0
SPI0
SPI0
SPI0
SPI0
SPI0
TWI0
TWI0
DBGU
DBGU
MCI0_D3
MISO
SPCK
NPCS0
NPCS1
TWD0
TWCK0
DRXD
DTXD
PIOA20
MOSI PIOA10
PIOA11
PIOA13
PIOA14
PIOA7
PIOA30
PIOA31
PIOA9
PIOA10
PIO Line
PIOD0
PIOD1
PIOD4
A21
A22
D[16:0]
PIOA17
PIOA15
PIOA18
PIOA19
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11.5 SAM-BA Monitor
If no valid code has been found in NVM during the NVM bootloader sequence, the SAM-BA Monitor program is launched.
The SAM-BA Monitor principle is to:
Initialize DBGU and USB
Check if USB Device enumeration has occurred
Check if characters have been received on the DBGU
Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as
.
Figure 11-10.SAM-BA Monitor Diagram
No valid code in NVM
Init DBGU and USB
No
No
USB Enumeration
Successful ?
Yes
Run monitor
Wait for command on the USB link
Character(s) received on DBGU ?
Yes
Run monitor
Wait for command on the DBGU link
11.5.1 Command List
R
G
V w
S h
W
Table 11-5. Commands Available through the SAM-BA Monitor
Command
N
Action set Normal mode
Argument(s)
No argument o
H
T
O set Terminal mode write a byte read a byte write a half word
No argument
Address, Value#
Address,#
Address, Value# read a half word write a word read a word send a file receive a file go display version
Address,#
Address, Value#
Address,#
Address,#
Address, NbOfBytes#
Address#
No argument
Example
N #
T #
O 200001,CA# o 200001,#
H 200002,CAFE# h 200002,#
W 200000,CAFEDECA# w 200000,#
S 200000,#
R 200000,1234#
G 200200#
V #
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Mode commands:
Normal mode configures SAM-BA Monitor to send / receive data in binary format,
Terminal mode configures SAM-BA Monitor to send / receive data in ascii format.
Write commands: Write a byte ( O ), a halfword ( H ) or a word ( W ) to the target.
Address : Address in hexadecimal.
Value : Byte, halfword or word to write in hexadecimal.
Output : ‘>’
Read commands: Read a byte ( o ), a halfword ( h ) or a word ( w ) from the target.
Address : Address in hexadecimal.
Output : The byte, halfword or word read in hexadecimal followed by ‘>’
Send a file ( S ): Send a file to a specified address.
Address : Address in hexadecimal.
Output : ‘>’
Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution.
Receive a file ( R ): Receive data into a file from a specified address
Address : Address in hexadecimal.
NbOfBytes : Number of bytes in hexadecimal to receive.
Output : ‘>’
Go ( G ): Jump to a specified address and execute the code.
Address : Address to jump in hexadecimal.
Output : ‘>’once returned from the program execution. If the executed program does not handle the link register at its entry and does not return, the prompt will not be displayed.
Get Version ( V ): Return the Boot Program version.
Output : version, date and time of ROM code followed by ‘>’.
11.5.2 DBGU Serial Port
Communication is performed through the DBGU serial port initialized to 115,200 Baud, 8 bits of data, no parity, 1 stop bit.
11.5.2.1 Supported External Crystal/External Clocks
The SAM-BA Monitor supports a frequency of 12 MHz to allow DBGU communication for both external crystal and external clock.
11.5.2.2 Xmodem Protocol
The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory in order to work.
The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC16 to guarantee detection of a maximum bit error.
Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like:
<SOH><blk #><255-blk #><--128 data bytes--><checksum> in which:
<SOH> = 01 hex
<blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)
<255-blk #> = 1’s complement of the blk#.
<checksum> = 2 bytes CRC16
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Figure 11-11 shows a transmission using this protocol.
Figure 11-11.Xmodem Transfer Example
Host
C
SOH 01 FE Data[128] CRC CRC
ACK
SOH 02 FD Data[128] CRC CRC
ACK
SOH 03 FC Data[100] CRC CRC
ACK
EOT
ACK
Device
11.5.3 USB Device Port
11.5.3.1 Supported External Crystal / External Clocks
The only frequency supported by SAM-BA Monitor to allow USB communication is a 12 MHz crystal or external clock.
11.5.3.2 USB Class
The device uses the USB Communication Device Class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows ® , from Windows 98SE ® to
Windows XP ® . The CDC document, available at www.usb.org
, describes how to implement devices such as ISDN modems and virtual COM ports.
The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID.
11.5.3.3 Enumeration Process
The USB protocol is a master/slave protocol. The host starts the enumeration, sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification.
Table 11-6. Handled Standard Requests
Request
GET_DESCRIPTOR
Definition
Returns the current device configuration value.
SET_ADDRESS
SET_CONFIGURATION
GET_CONFIGURATION
GET_STATUS
SET_FEATURE
CLEAR_FEATURE
Sets the device address for all future device access.
Sets the device configuration.
Returns the current device configuration value.
Returns status for the specified recipient.
Used to set or enable a specific feature.
Used to clear or disable a specific feature.
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The device also handles some class requests defined in the CDC class.
Table 11-7. Handled Class Requests
Request
SET_LINE_CODING
GET_LINE_CODING
SET_CONTROL_LINE_STATE
Definition
Configures DTE rate, stop bits, parity and number of character bits.
Requests current DTE rate, stop bits, parity and number of character bits.
RS-232 signal used to tell the DCE device the DTE device is now present.
Unhandled requests are STALLed.
11.5.3.4 Communication Endpoints
There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte
Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the host through endpoint 1. If required, the message is split by the host into several data payloads by the host driver.
If the command requires a response, the host can send IN transactions to pick up the response.
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12.
Boot Sequence Controller (BSC)
12.1 Description
The System Controller embeds a Boot Sequence Configuration Register to save timeout delays on boot. The boot sequence is programmable through the Boot Sequence Configuration Register (BSC_CR).
This register is powered by VDDBU, the modification is saved and applied after the next reset. The register is taking
Factory Value in case of battery removing.
This register is programmable with user programs or SAM-BA and it is key-protected.
12.2 Embedded Characteristics
VDDBU powered register
12.3 Product Dependencies
Product-dependent order
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12.4 Boot Sequence Controller (BSC) User Interface
Table 12-1. Register Mapping
Offset Register
0x0 Boot Sequence Configuration Register
Name
BSC_CR
Access
Read-write
Reset
–
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12.4.1 Boot Sequence Configuration Register
Name:
Address:
Access:
Factory Value:
31
BSC_CR
0xFFFFFE54
Read-write
0x0000_0000
30 29 28
BOOTKEY
27
23 22 21 20
BOOTKEY
19
15
–
7
14
–
6
13
–
5
12
–
4
11
–
3
BOOT
26
18
10
–
2
25
17
9
–
1
• BOOT: Boot Media Sequence
This value is defined in the product-dependent ROM code. It is only written if BOOTKEY carries the valid value.
Please refer to the “NVM Boot Sequence” section of this datasheet for details on BOOT value.
• BOOTKEY
0x6683 (BSC_KEY): Valid key to write the BSC_CR register; it needs to be written at the same time as the BOOT field.
Other values disable the write access. This key field is write-only.
24
16
8
–
0
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13.
Advanced Interrupt Controller (AIC)
13.1 Description
The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts.
The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor.
Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's pins.
The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated.
Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive-edge or negative-edge triggered or high-level or low-level sensitive.
The fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt.
13.2 Embedded Characteristics
Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM ® Processor
Thirty-two Individually Maskable and Vectored Interrupt Sources
Source 0 is Reserved for the Fast Interrupt Input (FIQ)
Source 1 is Reserved for System Peripherals
Source 2 to Source 31 Control up to Thirty Embedded Peripheral Interrupts or External Interrupts
Programmable Edge-triggered or Level-sensitive Internal Sources
Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive External Sources
8-level Priority Controller
Drives the Normal Interrupt of the Processor
Handles Priority of the Interrupt Sources 1 to 31
Higher Priority Interrupts Can Be Served During Service of Lower Priority Interrupt
Vectoring
Optimizes Interrupt Service Routine Branch and Execution
One 32-bit Vector Register per Interrupt Source
Interrupt Vector Register Reads the Corresponding Current Interrupt Vector
Protect Mode
Easy Debugging by Preventing Automatic Operations when Protect Models Are Enabled
Fast Forcing
Permits Redirecting any Normal Interrupt Source to the Fast Interrupt of the Processor
General Interrupt Mask
Provides Processor Synchronization on Events Without Triggering an Interrupt
Write Protected Registers
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13.3 Block Diagram
Figure 13-1. Block Diagram
FIQ
IRQ0-IRQn
Embedded
Peripheral
AIC
Up to
Thirty-two
Sources
ARM
Processor nFIQ nIRQ
APB
13.4 Application Block Diagram
Figure 13-2. Description of the Application Block
Standalone
Applications OS Drivers
OS-based Applications
RTOS Drivers
Hard Real Time Tasks
General OS Interrupt Handler
Advanced Interrupt Controller
Embedded Peripherals
External Peripherals
(External Interrupts)
13.5 AIC Detailed Block Diagram
Figure 13-3. AIC Detailed Block Diagram
FIQ
PIO
Controller
IRQ0-IRQn
PIOIRQ
Embedded
Peripherals
External
Source
Input
Stage
Advanced Interrupt Controller
Fast
Interrupt
Controller
Fast
Forcing
Interrupt
Priority
Controller Internal
Source
Input
Stage
User Interface
ARM
Processor nFIQ nIRQ
Processor
Clock
Power
Management
Controller
Wake Up
APB
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13.6 I/O Line Description
Table 13-1. I/O Line Description
Pin Name
FIQ
IRQ0 - IRQn
13.7 Product Dependencies
Pin Description
Fast Interrupt
Interrupt 0 - Interrupt n
Type
Input
Input
13.7.1 I/O Lines
The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path.
Table 13-2. I/O Lines
Instance
AIC
AIC
Signal
FIQ
IRQ
I/O Line
PC31
PB18
Peripheral
A
A
13.7.2 Power Management
The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the
Advanced Interrupt Controller behavior.
The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the ARM processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without asserting the interrupt line of the processor, thus providing synchronization of the processor on an event.
13.7.3 Interrupt Sources
The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0 cannot be used.
The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system peripheral interrupt lines. When a system interrupt occurs, the service routine must first distinguish the cause of the interrupt. This is performed by reading successively the status registers of the above mentioned system peripherals.
The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller.
The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO
Controller interrupt lines are connected to the Interrupt Sources 2 to 31.
The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31.
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13.8 Functional Description
13.8.1 Interrupt Source Control
13.8.1.1 Interrupt Source Mode
The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source.
The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user.
The external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in positive edge-triggered or negative edge-triggered modes.
13.8.1.2 Interrupt Source Enabling
Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers;
AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register). This set of registers conducts enabling or disabling in one instruction. The interrupt mask can be read in the AIC_IMR register. A disabled interrupt does not affect servicing of other interrupts.
13.8.1.3 Interrupt Clearing and Setting
All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clearing or setting interrupt sources programmed in levelsensitive mode has no effect.
The clear operation is perfunctory, as the software must perform an action to reinitialize the “memorization” circuitry activated when the source is programmed in edge-triggered mode. However, the set operation is available for auto-test or software debug purposes. It can also be used to execute an AIC-implementation of a software interrupt.
The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is affected by this operation. (
) The automatic clear reduces the operations required by the interrupt service routine entry code
to reading the AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing
)
The automatic clear of the interrupt source 0 is performed when AIC_FVR is read.
13.8.1.4 Interrupt Status
For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR
(Interrupt Mask Register). AIC_IPR enables the actual activity of the sources, whether masked or not.
The AIC_ISR register reads the number of the current interrupt (see
“Priority Controller” on page 75 ) and the register
AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor.
Each status referred to above can be used to optimize the interrupt handling of the systems.
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Figure 13-4. Internal Interrupt Source Input Stage
Source i
AIC_SMRI
(SRCTYPE)
Level/
Edge
AIC_IPR
AIC_IMR
Edge
Detector
Set Clear
Fast Interrupt Controller or
Priority Controller
AIC_IECR
FF
AIC_ISCR
AIC_ICCR
AIC_IDCR
Figure 13-5. External Interrupt Source Input Stage
High/Low
AIC_SMRi
SRCTYPE
Level/
Edge
Source i
AIC_IPR
AIC_IMR
Fast Interrupt Controller
or
Priority Controller
AIC_IECR
Pos./Neg.
Edge
Detector
Set Clear
FF
AIC_IDCR AIC_ISCR
AIC_ICCR
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13.8.2 Interrupt Latencies
Global interrupt latencies depend on several parameters, including:
The time the software masks the interrupts.
Occurrence, either at the processor level or at the AIC level.
The execution time of the instruction in progress when the interrupt occurs.
The treatment of higher priority interrupts and the resynchronization of the hardware signals.
This section addresses only the hardware resynchronizations. It gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress.
The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources.
Figure 13-6. External Interrupt Edge Triggered Source
MCK
IRQ or FIQ
(Positive Edge)
IRQ or FIQ
(Negative Edge) nIRQ
Maximum IRQ Latency = 4 Cycles nFIQ
Maximum FIQ Latency = 4 Cycles
Figure 13-7. External Interrupt Level Sensitive Source
MCK
IRQ or FIQ
(High Level)
IRQ or FIQ
(Low Level) nIRQ
Maximum IRQ
Latency = 3 Cycles nFIQ
Maximum FIQ
Latency = 3 cycles
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Figure 13-8. Internal Interrupt Edge Triggered Source
MCK nIRQ
Maximum IRQ Latency = 4.5 Cycles
Peripheral Interrupt
Becomes Active
Figure 13-9. Internal Interrupt Level Sensitive Source
MCK nIRQ
Maximum IRQ Latency = 3.5 Cycles
Peripheral Interrupt
Becomes Active
13.8.3 Normal Interrupt
13.8.3.1 Priority Controller
An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast Forcing).
Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest.
As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR (Source Mode Register), the nIRQ line is asserted. As a new interrupt condition might have happened on other interrupt sources since the nIRQ has been asserted, the priority controller determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software.
The current priority level is defined as the priority level of the current interrupt.
If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the lowest interrupt source number is serviced first.
The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the exit point of the interrupt handling.
13.8.3.2 Interrupt Nesting
The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level.
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When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is reasserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the AIC_EOICR is written.
The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels.
13.8.3.3 Interrupt Vectoring
The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1 to
AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the current interrupt is returned.
This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as
AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address
0x0000 0018 through the following instruction:
LDR PC,[PC,# -&F20]
When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler.
This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt.
However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operating system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system’s general interrupt handler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system.
13.8.3.4 Interrupt Handlers
This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and the associated status bits.
It is assumed that:
1.
The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled.
2.
The instruction at the ARM interrupt exception vector address is required to work with the vectoring
LDR PC, [PC, # -&F20]
When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows:
1.
The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register
(R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four.
2.
The ARM core enters Interrupt mode, if it has not already done so.
3.
When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in
AIC_IVR. Reading the AIC_IVR has the following effects:
Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt.
De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ.
Automatically clears the interrupt, if it has been programmed to be edge-triggered.
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Pushes the current level and the current interrupt number on to the stack.
Returns the value written in the AIC_SVR corresponding to the current interrupt.
4.
The previous step has the effect of branching to the corresponding interrupt service routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction
SUB
PC, LR, #4
may be used.
5.
Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re-assertion of the nIRQ to be taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt occurs.
6.
The interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the end. During this phase, an interrupt of higher priority than the current level will restart the sequence from step 1.
Note: If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase.
7.
The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner.
8.
The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted, but the interrupt sequence does not immediately start because the “I” bit is set in the core. SPSR_irq is restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq.
Note: The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked).
13.8.4 Fast Interrupt
13.8.4.1 Fast Interrupt Source
The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO
Controller.
13.8.4.2 Fast Interrupt Control
The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the
AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The field SRCTYPE of
AIC_SMR0 enables programming the fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive
Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command
Register) respectively enables and disables the fast interrupt. The bit 0 of AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled.
13.8.4.3 Fast Interrupt Vectoring
The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The value written into this register is returned when the processor reads AIC_FVR (Fast Vector Register). This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM fast interrupt vector at address 0x0000 001C through the following instruction:
LDR PC,[PC,# -&F20]
When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus branching the execution on the fast interrupt handler. It also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode.
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13.8.4.4 Fast Interrupt Handlers
This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and associated status bits.
Assuming that:
1.
The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled.
2.
The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt:
LDR PC, [PC, # -&F20]
3.
The user does not need nested fast interrupts.
When nFIQ is asserted, if the bit “F” of CPSR is 0, the sequence is:
1.
The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register
(R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address
0x20, the ARM core adjusts R14_fiq, decrementing it by four.
2.
The ARM core enters FIQ mode.
3.
When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in
AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt, if it has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor.
4.
The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed.
5.
The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0.
6.
Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction
SUB PC,
LR, #4
for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the
SPSR.
Note: The “F” bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked).
Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector 0x1C.
This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning of the handler operation. However, this method saves the execution of a branch instruction.
13.8.4.5 Fast Forcing
The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller.
Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing
Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register
(AIC_FFSR) that controls the feature for each internal or external interrupt source.
When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages.
When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority handler.
If the interrupt source is programmed in level-sensitive mode and an active level is sampled, Fast Forcing results in the assertion of the nFIQ line to the core.
If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results in the assertion of the nFIQ line to the core.
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The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Register (AIC_IPR).
The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0 (AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR).
All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edgetriggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are cleared independently and thus lost interrupts are prevented.
The read of AIC_IVR does not clear the source that has the fast forcing feature enabled.
The source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt sources.
Figure 13-10.Fast Forcing
Source 0
_
FIQ
AIC_IPR
Input Stage
Automatic Clear AIC_IMR nFIQ
Source n
Input Stage
Automatic Clear
Read FVR if Fast Forcing is disabled on Sources 1 to 31.
AIC_FFSR
AIC_IPR
AIC_IMR
Priority
Manager nIRQ
Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n.
13.8.5 Protect Mode
The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations.
This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the
ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR. This has undesirable consequences:
If an enabled interrupt with a higher priority than the current one is pending, it is stacked.
If there is no enabled pending interrupt, the spurious vector is returned.
In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state.
This is avoided by using the Protect Mode. Writing PROT in AIC_DCR (Debug Control Register) at 0x1 enables the
Protect Mode.
When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the
AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written.
An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context.
To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC:
1.
Calculates active interrupt (higher than current or spurious).
2.
Determines and returns the vector of the active interrupt.
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3.
Memorizes the interrupt.
4.
Pushes the current priority level onto the internal stack.
5.
Acknowledges the interrupt.
However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written.
Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code.
13.8.6 Spurious Interrupt
The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when:
An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time.
An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.)
An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source.
The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register). The programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt.
13.8.7 General Interrupt Mask
The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. It is strongly recommended to use this mask with caution.
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13.9 Write Protection Registers
To prevent any single software error that may corrupt AIC behavior, the registers listed below can be write-protected by
setting the WPEN bit in the AIC Write Protect Mode Register (AIC_WPMR).
(AIC_WPSR) is set and the WPVSRC field indicates in which register the write access has been attempted.
The WPVS flag is automatically reset after reading the AIC Write Protect Status Register.
The protected registers are:
“AIC Source Mode Register” on page 83
“AIC Source Vector Register” on page 84
“AIC Spurious Interrupt Vector Register” on page 96
“AIC Debug Control Register” on page 97
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13.10 Advanced Interrupt Controller (AIC) User Interface
13.10.1 Base Address
The AIC is mapped at the address 0xFFFFF000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only a
±
4-Kbyte offset.
Table 13-3. Register Mapping
Offset
0x00
0x04
---
0x7C
0x80
0x84
---
0xFC
0x100
0x104
0x108
0x10C
0x110
0x114
0x118 - 0x11C
0x120
0x124
0x128
0x12C
0x130
0x134
0x138
0x13C
0x140
0x144
0x148
0x14C - 0x1E0
0x1E4
0x1E8
0x1EC - 0x1FC
Register
Source Mode Register 0
Source Mode Register 1
---
Source Mode Register 31
Source Vector Register 0
Source Vector Register 1
---
Source Vector Register 31
Interrupt Vector Register
FIQ Interrupt Vector Register
Interrupt Status Register
Interrupt Pending Register (2)
Interrupt Mask Register
Core Interrupt Status Register
Reserved
Interrupt Enable Command Register
Interrupt Disable Command Register
Interrupt Clear Command Register
Interrupt Set Command Register
End of Interrupt Command Register
Spurious Interrupt Vector Register
Debug Control Register
Reserved
Fast Forcing Enable Register (2)
Fast Forcing Disable Register (2)
Fast Forcing Status Register
Reserved
Write Protect Mode Register
Write Protect Status Register
Reserved
---
AIC_IECR
AIC_IDCR
AIC_ICCR
AIC_ISCR
AIC_EOICR
AIC_SPU
AIC_DCR
---
AIC_FFER
AIC_FFDR
AIC_FFSR
---
AIC_WPMR
AIC_WPSR
Name
AIC_SMR0
AIC_SMR1
---
AIC_SMR31
AIC_SVR0
AIC_SVR1
---
AIC_SVR31
AIC_IVR
AIC_FVR
AIC_ISR
AIC_IPR
AIC_IMR
AIC_CISR
0x0
0x0
---
---
---
---
---
---
---
0x0
---
0x0
0x0
---
0x0
0x0
0x0
0x0
0x0
0x0
---
---
Reset
0x0
0x0
---
0x0
0x0
0x0
Notes: 1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending.
2. PID2...PID31 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet.
---
Write-only
Write-only
Write-only
Write-only
Write-only
Read-write
Read-write
---
Write-only
Write-only
Read-only
---
Read-write
Read-only
Access
Read-write
Read-write
---
Read-write
Read-write
Read-write
---
Read-write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
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13.10.2 AIC Source Mode Register
Name:
Address:
Access
Reset:
AIC_SMR0..AIC_SMR31
0xFFFFF000
Read-write
0x0
15
–
7
–
31
–
23
–
14
–
6
30
–
22
–
SRCTYPE
13
–
5
29
–
21
–
12
–
4
–
28
–
20
–
11
–
3
–
27
–
19
–
10
–
2
26
–
18
–
This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register
• PRIOR: Priority Level
The priority level is programmable from 0 (lowest priority) to 7 (highest priority).
The priority level is not used for the FIQ in the related SMR register AIC_SMR0.
• SRCTYPE: Interrupt Source Type
The active level or edge is not programmable for the internal interrupt sources.
Value
0x0
0x1
0x2
0x3
Name
INT_LEVEL_SENSITIVE
INT_EDGE_TRIGGERED
EXT_HIGH_LEVEL
EXT_POSITIVE_EDGE
Description
High level Sensitive for internal source
Low level Sensitive for external source
Positive edge triggered for internal source
Negative edge triggered for external source
High level Sensitive for internal source
High level Sensitive for external source
Positive edge triggered for internal source
Positive edge triggered for external source
25
–
17
–
9
–
1
PRIOR
8
–
0
24
–
16
–
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13.10.3 AIC Source Vector Register
Name:
Address:
Access:
AIC_SVR0..AIC_SVR31
0xFFFFF080
Read-write
Reset: 0x0
31 30 29 28 27 26
VECTOR
23 22 21 20 19 18
VECTOR
15 14 13 12 11 10
VECTOR
7 6 5 4 3 2
VECTOR
This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register
25
17
9
1
• VECTOR: Source Vector
The user may store in these registers the addresses of the corresponding handler for each interrupt source.
8
0
24
16
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13.10.4 AIC Interrupt Vector Register
Name: AIC_IVR
Address:
Access:
0xFFFFF100
Read-only
Reset: 0x0
31 30 29 28 27 26 25 24
IRQV
23 22 21 20 19 18 17 16
IRQV
15 14 13 12 11 10 9 8
IRQV
7 6 5 4 3 2 1 0
IRQV
• IRQV: Interrupt Vector Register
The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt.
The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read.
When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU.
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13.10.5 AIC FIQ Vector Register
Name: AIC_FVR
Address:
Access:
0xFFFFF104
Read-only
Reset: 0x0
31 30 29 28 27 26 25 24
FIQV
23 22 21 20 19 18 17 16
FIQV
15 14 13 12 11 10 9 8
FIQV
7 6 5 4 3 2 1 0
FIQV
• FIQV: FIQ Vector Register
The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU.
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13.10.6 AIC Interrupt Status Register
Name: AIC_ISR
Address:
Access:
0xFFFFF108
Read-only
Reset: 0x0
15
–
7
–
31
–
23
–
14
–
6
–
30
–
22
–
13
–
5
–
29
–
21
–
12
–
4
28
–
20
–
• IRQID: Current Interrupt Identifier
The Interrupt Status Register returns the current interrupt source number.
11
–
3
27
–
19
–
26
–
18
–
10
–
2
IRQID
9
–
1
25
–
17
–
8
–
0
24
–
16
–
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13.10.7 AIC Interrupt Pending Register
Name: AIC_IPR
Address:
Access:
0xFFFFF10C
Read-only
Reset: 0x0
31
PID31
23
PID23
15
PID15
7
PID7
30
PID30
22
PID22
14
PID14
6
PID6
29
PID29
21
PID21
13
PID13
5
PID5
• FIQ, SYS, PID2-PID31: Interrupt Pending
0 = Corresponding interrupt is not pending.
1 = Corresponding interrupt is pending.
28
PID28
20
PID20
12
PID12
4
PID4
27
PID27
19
PID19
11
PID11
3
PID3
26
PID26
18
PID18
10
PID10
2
PID2
25
PID25
17
PID17
9
PID9
1
SYS
24
PID24
16
PID16
8
PID8
0
FIQ
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13.10.8 AIC Interrupt Mask Register
Name:
Address:
Access:
AIC_IMR
0xFFFFF110
Read-only
Reset: 0x0
31
PID31
23
PID23
15
PID15
7
PID7
30
PID30
22
PID22
14
PID14
6
PID6
29
PID29
21
PID21
13
PID13
5
PID5
• FIQ, SYS, PID2-PID31: Interrupt Mask
0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.
28
PID28
20
PID20
12
PID12
4
PID4
27
PID27
19
PID19
11
PID11
3
PID3
26
PID26
18
PID18
10
PID10
2
PID2
25
PID25
17
PID17
9
PID9
1
SYS
24
PID24
16
PID16
8
PID8
0
FIQ
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13.10.9 AIC Core Interrupt Status Register
Name: AIC_CISR
Address:
Access:
0xFFFFF114
Read-only
Reset: 0x0
15
–
7
–
31
–
23
–
14
–
6
–
30
–
22
–
13
–
5
–
29
–
21
–
• NFIQ: NFIQ Status
0 = nFIQ line is deactivated.
1 = nFIQ line is active.
• NIRQ: NIRQ Status
0 = nIRQ line is deactivated.
1 = nIRQ line is active.
12
–
4
–
28
–
20
–
11
–
3
–
27
–
19
–
10
–
2
–
26
–
18
–
9
–
1
NIRQ
25
–
17
–
8
–
0
NFIQ
24
–
16
–
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13.10.10 AIC Interrupt Enable Command Register
Name: AIC_IECR
Address: 0xFFFFF120
Access: Write-only
31
PID31
23
PID23
15
PID15
7
PID7
30
PID30
22
PID22
14
PID14
6
PID6
29
PID29
21
PID21
13
PID13
5
PID5
28
PID28
20
PID20
12
PID12
4
PID4
• FIQ, SYS, PID2-PID31: Interrupt Enable
0 = No effect.
1 = Enables corresponding interrupt.
27
PID27
19
PID19
11
PID11
3
PID3
26
PID26
18
PID18
10
PID10
2
PID2
25
PID25
17
PID17
9
PID9
1
SYS
24
PID24
16
PID16
8
PID8
0
FIQ
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13.10.11 AIC Interrupt Disable Command Register
Name: AIC_IDCR
Address: 0xFFFFF124
Access: Write-only
31
PID31
23
PID23
15
PID15
7
PID7
30
PID30
22
PID22
14
PID14
6
PID6
29
PID29
21
PID21
13
PID13
5
PID5
28
PID28
20
PID20
12
PID12
4
PID4
• FIQ, SYS, PID2-PID31: Interrupt Disable
0 = No effect.
1 = Disables corresponding interrupt.
27
PID27
19
PID19
11
PID11
3
PID3
26
PID26
18
PID18
10
PID10
2
PID2
25
PID25
17
PID17
9
PID9
1
SYS
24
PID24
16
PID16
8
PID8
0
FIQ
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13.10.12 AIC Interrupt Clear Command Register
Name:
Address:
Access:
AIC_ICCR
0xFFFFF128
Write-only
31
PID31
23
PID23
15
PID15
7
PID7
30
PID30
22
PID22
14
PID14
6
PID6
29
PID29
21
PID21
13
PID13
5
PID5
28
PID28
20
PID20
12
PID12
4
PID4
• FIQ, SYS, PID2-PID31: Interrupt Clear
0 = No effect.
1 = Clears corresponding interrupt.
27
PID27
19
PID19
11
PID11
3
PID3
26
PID26
18
PID18
10
PID10
2
PID2
25
PID25
17
PID17
9
PID9
1
SYS
24
PID24
16
PID16
8
PID8
0
FIQ
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13.10.13 AIC Interrupt Set Command Register
Name: AIC_ISCR
Address: 0xFFFFF12C
Access: Write-only
31
PID31
23
PID23
15
PID15
7
PID7
30
PID30
22
PID22
14
PID14
6
PID6
29
PID29
21
PID21
13
PID13
5
PID5
28
PID28
20
PID20
12
PID12
4
PID4
• FIQ, SYS, PID2-PID31: Interrupt Set
0 = No effect.
1 = Sets corresponding interrupt.
27
PID27
19
PID19
11
PID11
3
PID3
26
PID26
18
PID18
10
PID10
2
PID2
25
PID25
17
PID17
9
PID9
1
SYS
24
PID24
16
PID16
8
PID8
0
FIQ
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13.10.14 AIC End of Interrupt Command Register
Name:
Address:
Access:
AIC_EOICR
0xFFFFF130
Write-only
15
–
7
–
31
–
23
–
14
–
6
–
30
–
22
–
13
–
5
–
29
–
21
–
12
–
4
–
28
–
20
–
11
–
3
–
27
–
19
–
10
–
2
–
26
–
18
–
1
–
9
–
25
–
17
–
0
–
8
–
24
–
16
–
The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment.
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13.10.15 AIC Spurious Interrupt Vector Register
Name:
Address:
Access:
AIC_SPU
0xFFFFF134
Read-write
Reset: 0x0
31 30 29 28 27 26
SIVR
23 22 21 20 19 18
SIVR
15 14 13 12 11 10
SIVR
7 6 5 4 3 2
SIVR
This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register
25
17
9
1
24
16
8
0
• SIVR: Spurious Interrupt Vector Register
The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.
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13.10.16 AIC Debug Control Register
Name:
Address:
Access:
AIC_DCR
0xFFFFF138
Read-write
Reset: 0x0
15
–
7
–
31
–
23
–
14
–
6
–
30
–
22
–
13
–
5
–
29
–
21
–
12
–
4
–
28
–
20
–
11
–
3
–
27
–
19
–
10
–
2
–
26
–
18
–
This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register
• PROT: Protection Mode
0 = The Protection Mode is disabled.
1 = The Protection Mode is enabled.
• GMSK: General Mask
0 = The nIRQ and nFIQ lines are normally controlled by the AIC.
1 = The nIRQ and nFIQ lines are tied to their inactive state.
25
–
17
–
9
–
1
GMSK
24
–
16
–
8
–
0
PROT
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13.10.17 AIC Fast Forcing Enable Register
Name:
Address:
Access:
AIC_FFER
0xFFFFF140
Write-only
31
PID31
23
PID23
15
PID15
7
PID7
30
PID30
22
PID22
14
PID14
6
PID6
29
PID29
21
PID21
13
PID13
5
PID5
28
PID28
20
PID20
12
PID12
4
PID4
• SYS, PID2-PID31: Fast Forcing Enable
0 = No effect.
1 = Enables the fast forcing feature on the corresponding interrupt.
27
PID27
19
PID19
11
PID11
3
PID3
26
PID26
18
PID18
10
PID10
2
PID2
25
PID25
17
PID17
9
PID9
1
SYS
24
PID24
16
PID16
8
PID8
0
–
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13.10.18 AIC Fast Forcing Disable Register
Name:
Address:
Access:
AIC_FFDR
0xFFFFF144
Write-only
31
PID31
23
PID23
15
PID15
7
PID7
30
PID30
22
PID22
14
PID14
6
PID6
29
PID29
21
PID21
13
PID13
5
PID5
28
PID28
20
PID20
12
PID12
4
PID4
• SYS, PID2-PID31: Fast Forcing Disable
0 = No effect.
1 = Disables the Fast Forcing feature on the corresponding interrupt.
27
PID27
19
PID19
11
PID11
3
PID3
26
PID26
18
PID18
10
PID10
2
PID2
25
PID25
17
PID17
9
PID9
1
SYS
24
PID24
16
PID16
8
PID8
0
–
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13.10.19 AIC Fast Forcing Status Register
Name:
Address:
Access:
AIC_FFSR
0xFFFFF148
Read-only
31
PID31
23
PID23
15
PID15
7
PID7
30
PID30
22
PID22
14
PID14
6
PID6
29
PID29
21
PID21
13
PID13
5
PID5
28
PID28
20
PID20
12
PID12
4
PID4
• SYS, PID2-PID31: Fast Forcing Status
0 = The Fast Forcing feature is disabled on the corresponding interrupt.
1 = The Fast Forcing feature is enabled on the corresponding interrupt.
27
PID27
19
PID19
11
PID11
3
PID3
26
PID26
18
PID18
10
PID10
2
PID2
25
PID25
17
PID17
9
PID9
1
SYS
24
PID24
16
PID16
8
PID8
0
–
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13.10.20 AIC Write Protect Mode Register
Name:
Address:
Access:
Reset:
AIC_WPMR
0xFFFFF1E4
Read-write
See
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
7
—
6
—
5
—
4
—
3
—
2
—
1
—
0
WPEN
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x414943 ("AIC" in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x414943 ("AIC" in ASCII).
Protects the registers:
•
“AIC Source Mode Register” on page 83
•
“AIC Source Vector Register” on page 84
•
“AIC Spurious Interrupt Vector Register” on page 96
•
“AIC Debug Control Register” on page 97
• WPKEY: Write Protect KEY
Should be written at value 0x414943 ("AIC" in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
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13.10.21 AIC Write Protect Status Register
Name:
Address:
Access:
Reset:
AIC_WPSR
0xFFFFF1E8
Read-only
See
31
—
30
—
29
—
23
15
22
14
21
13
28
—
27
—
20
WPVSRC
19
12
WPVSRC
11
4
—
3
—
26
—
18
10
25
—
17
9
24
—
16
8
7
—
6
—
5
—
2
—
1
—
0
WPVS
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the AIC_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the AIC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted.
Note: Reading AIC_WPSR automatically clears all fields.
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14.
Reset Controller (RSTC)
14.1 Description
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last.
The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets.
14.2 Embedded Characteristics
Manages All Resets of the System, Including
External Devices Through the NRST Pin
Processor Reset
Peripheral Set Reset
Backed-up Peripheral Reset
Based on 2 Embedded Power-on Reset Cells
Reset Source Status
Status of the Last Reset
Either General Reset, Wake-up Reset, Software Reset, User Reset, Watchdog Reset
External Reset Signal Shaping
AMBA ™ -compliant Interface
Interfaces to the ARM ® Advanced Peripheral Bus
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14.3 Block Diagram
Figure 14-1. Reset Controller Block Diagram
Main Supply
POR
Backup Supply
POR
NRST
Reset Controller
Startup
Counter user_reset nrst_out
NRST
Manager exter_nreset
Reset
State
Manager
WDRPROC wd_fault
SLCK rstc_irq proc_nreset periph_nreset backup_neset
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14.4 Functional Description
14.4.1 Reset Controller Overview
The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow
Clock and generates the following reset signals:
proc_nreset: Processor reset line. It also resets the Watchdog Timer.
backup_nreset: Affects all the peripherals powered by VDDBU.
periph_nreset: Affects the whole set of embedded peripherals.
nrst_out: Drives the NRST pin.
These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset
State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets.
The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical
Characteristics section of the product documentation.
The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with
VDDBU, so that its configuration is saved as long as VDDBU is on.
14.4.2 NRST Manager
After power-up, NRST is an output during the ERSTL time defined in the RSTC. When ERSTL elapsed, the pin behaves as an input and all the system is held in reset if NRST is tied to GND by an external signal.
The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager.
Figure 14-2 shows the block diagram of the NRST Manager.
Figure 14-2. NRST Manager
RSTC_SR
URSTS
NRSTL user_reset
NRST RSTC_MR
ERSTL nrst_out
External Reset Timer exter_nreset
14.4.2.1 NRST Signal
The NRST Manager handles the NRST input line asynchronously. When the line is low, a User Reset is immediately reported to the Reset State Manager. When the NRST goes from low to high, the internal reset is synchronized with the
Slow Clock to provide a safe internal de-assertion of reset.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.
14.4.2.2 NRST External Reset Control
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration,
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named EXTERNAL_RESET_LENGTH, lasts 2 (ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset.
As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator.
14.4.3 BMS Sampling
The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge.
Figure 14-3. BMS Sampling
SLCK
Core Supply
POR output
BMS Signal
XXX
BMS sampling delay
= 3 cycles
H or L proc_nreset
14.4.4 Reset States
The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released.
14.4.4.1 General Reset
A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock
Oscillator startup time.
After this time, the processor clock is released at Slow Clock and all the other signals remain valid for 3 cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General
Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0.
When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if the
Main Supply POR Cell does not report a Main Supply shutdown.
VDDBU only activates the backup_nreset signal.
The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output).
Figure 14-4 shows how the General Reset affects the reset signals.
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Figure 14-4. General Reset State
SLCK
MCK
Backup Supply
POR output
Main Supply
POR output backup_nreset proc_nreset
RSTTYP periph_nreset
NRST
(nrst_out)
Startup Time
XXX
Processor Startup
0x0 = General Reset
Any
Freq.
XXX
EXTERNAL RESET LENGTH
= 2 cycles
BMS Sampling
14.4.4.2 Wake-up Reset
The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on
Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on the requirements of the
ARM processor.
At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a
Wake-up Reset.
The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable.
When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the Main Supply POR.
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Figure 14-5. Wake-up Reset
S LCK
MCK
M a in Su pply
POR o u tp u t ba ck u p_nre s et proc_nre s et
R S TTYP periph_nre s et
NR S T
(nr s t_o u t)
Re s ynch.
2 cycle s
Proce ss or S t a rt u p
XXX
EXTERNAL RE S ET LENGTH
= 4 cycle s (ER S TL = 1)
0x1 = W a keUp Re s et
Any
Fre q .
XXX
14.4.4.3 User Reset
The User Reset is entered when a low level is detected on the NRST pin When a falling edge occurs on NRST (reset activation), internal reset lines are immediately asserted.
The Processor Reset and the Peripheral Reset are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset.
The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises.
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Figure 14-6. User Reset State
SLCK
MCK
Any
Freq.
NRST
Resynch.
2 cycles
Processor Startup proc_nreset
RSTTYP Any periph_nreset
XXX 0x4 = User Reset
NRST
(nrst_out)
>= EXTERNAL RESET LENGTH
14.4.4.4 Software Reset
The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1:
PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
Except for Debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and
PROCRST set both at 1 simultaneously.)
EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode
Register (RSTC_MR).
The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock
(MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status
Register (RSTC_SR). Other Software Resets are not reported in RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status
Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect.
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Figure 14-7. Software Reset
SLCK
MCK
Write RSTC_CR
Any
Freq.
proc_nreset if PROCRST=1
RSTTYP periph_nreset if PERRST=1
NRST
(nrst_out) if EXTRST=1
SRCMP in RSTC_SR
Any
Resynch.
1 to 2 cycles
Processor Startup
= 3 cycles
XXX
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
0x3 = Software Reset
14.4.4.5 Watchdog Reset
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:
If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a
User Reset state.
If WDRPROC = 1, only the processor reset is asserted.
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if
WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset and the Watchdog is enabled by default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.
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Figure 14-8. Watchdog Reset
SLCK
MCK
Any
Freq.
wd_fault
Processor Startup
= 3 cycles proc_nreset
RSTTYP periph_nreset
Any XXX 0x2 = Watchdog Reset
Only if
WDRPROC = 0
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
14.4.5 Reset State Priorities
The Reset State Manager manages the following priorities between the different reset sources, given in descending order:
Backup Reset
Wake-up Reset
User Reset
Watchdog Reset
Software Reset
Particular cases are listed below:
When in User Reset:
A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.
A software reset is impossible, since the processor reset is being activated.
When in Software Reset:
A watchdog event has priority over the current state.
The NRST has no effect.
When in Watchdog Reset:
The processor reset is active and so a Software Reset cannot be programmed.
A User Reset cannot be entered.
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14.4.6 Reset Controller Status Register
The Reset Controller status register (RSTC_SR) provides several status fields:
RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge.
URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see
Figure 14-9 ). Reading the RSTC_SR status register
resets the URSTS bit.
Figure 14-9. Reset Controller Status and Interrupt
MCK
Peripheral Access read
RSTC_SR
2 cycle resynchronization
2 cycle resynchronization
NRST
NRSTL
URSTS rstc_irq if (URSTEN = 0) and
(URSTIEN = 1)
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14.5 Reset Controller (RSTC) User Interface
Table 14-1. Register Mapping
Offset Register Name
0x00 Control Register RSTC_CR
0x04
0x08
Note:
Access
Write-only
Reset
-
Status Register
Mode Register
RSTC_SR
RSTC_MR
Read-only
Read-write
0x0000_0001
-
0x0000_0000
0x0000_0000
The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply.
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14.5.1 Reset Controller Control Register
Name:
Address:
Access:
RSTC_CR
0xFFFFFE00
Write-only
31 30 29 28 27 26
KEY
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
20
–
12
–
4
–
19
–
11
–
3
EXTRST
18
–
10
–
2
PERRST
• PROCRST: Processor Reset
0 = No effect.
1 = If KEY is correct, resets the processor.
• PERRST: Peripheral Reset
0 = No effect.
1 = If KEY is correct, resets the peripherals.
• EXTRST: External Reset
0 = No effect.
1 = If KEY is correct, asserts the NRST pin and resets the processor and the peripherals.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
25
17
–
9
1
–
24
16
–
8
–
0
PROCRST
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0
0
0
0
1
14.5.2 Reset Controller Status Register
Name:
Address:
Access:
RSTC_SR
0xFFFFFE04
Read-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
0
1
0
1
0
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
2
–
• URSTS: User Reset Status
0 = No high-to-low edge on NRST happened since the last read of RSTC_SR.
1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
• RSTTYP: Reset Type
Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
RSTTYP
0
0
1
1
0
Reset Type
General Reset
Wake Up Reset
Watchdog Reset
Software Reset
User Reset
Comments
Both VDDCORE and VDDBU rising
VDDCORE rising
Watchdog fault occurred
Processor reset required by the software
NRST pin detected low
25
–
17
SRCMP
9
RSTTYP
1
–
24
–
16
NRSTL
8
0
URSTS
• NRSTL: NRST Pin Level
Registers the NRST Pin Level at Master Clock (MCK).
• SRCMP: Software Reset Command in Progress
0 = No software command is being performed by the reset controller. The reset controller is ready for a software command.
1 = A software reset command is being performed by the reset controller. The reset controller is busy.
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14.5.3 Reset Controller Mode Register
Name:
Address:
Access:
RSTC_MR
0xFFFFFE08
Read-write
31 30 29 28 27 26 25 24
KEY
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
20
–
12
–
4
–
19
–
11
3
–
18
–
10
ERSTL
17
–
9
2
–
1
–
16
–
8
0
–
• ERSTL: External Reset Length
This field defines the external reset length. The external reset is asserted during a time of 2 (ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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15.
Real-time Clock (RTC)
15.1 Description
The Real-time Clock (RTC) peripheral is designed for very low power consumption.
It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus.
The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or
12-hour mode with an AM/PM indicator.
Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/year/century.
15.2 Embedded Characteristics
Ultra Low Power Consumption
Full Asynchronous Design
Gregorian Calendar up to 2099
Programmable Periodic Interrupt
Valid Time and Date Programmation Check
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15.3 Block Diagram
Figure 15-1. RTC Block Diagram
Slow Clock: SLCK 32768 Divider
Bus Interface Bus Interface
Time Date
Entry
Control
Interrupt
Control
RTC Interrupt
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15.4 Product Dependencies
15.4.1 Power Management
The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior.
15.4.2 Interrupt
Within the System Controller, the RTC interrupt is OR-wired with all the other module interrupts.
Only one System Controller interrupt line is connected on one of the internal sources of the interrupt controller.
RTC interrupt requires the interrupt controller to be programmed first.
When a System Controller interrupt occurs, the service routine must first determine the cause of the interrupt. This is done by reading each status register of the System Controller peripherals successively.
15.5 Functional Description
The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds.
The valid year range is 1900 to 2099 in Gregorian mode, a two-hundred-year calendar.
The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator.
Corrections for leap years are included (all years divisible by 4 being leap years). This is correct up to the year 2099.
15.5.1 Reference Clock
The reference clock is Slow Clock (SLCK). It can be driven internally or by an external 32.768 kHz crystal.
During low power modes of the processor, the oscillator runs and power consumption is critical. The crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy.
15.5.2 Timing
The RTC is updated in real time at one-second intervals in normal mode for the counters of seconds, at one-minute intervals for the counter of minutes and so on.
Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the
RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required.
15.5.3 Alarm
The RTC has five programmable fields: month, date, hours, minutes and seconds.
Each of these fields can be enabled or disabled to match the alarm condition:
If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second.
If only the “seconds” field is enabled, then an alarm is generated every minute.
Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days.
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15.5.4 Error Checking when Programming
Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured.
If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is done for the alarm.
The following checks are performed:
1.
Century (check if it is in range 19 - 20)
2.
Year (BCD entry check)
3.
Date (check range 01 - 31)
4.
Month (check if it is in BCD range 01 - 12, check validity regarding “date”)
5.
Day (check range 1 - 7)
6.
Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is not set if RTC is set in 24hour mode; in 12-hour mode check range 01 - 12)
7.
Minute (check BCD and range 00 - 59)
8.
Second (check BCD and range 00 - 59)
Note: If the 12-hour mode is selected by means of the RTC_MR register, a 12-hour value can be programmed and the returned value on RTC_TIMR will be the corresponding 24-hour value. The entry control checks the value of the
AM/PM indicator (bit 22 of RTC_TIMR register) to determine the range to be checked.
15.5.5 Updating Time/Calendar
To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the
Control Register. Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month, date, day).
Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status Register. Once the bit reads 1, it is mandatory to clear this flag by writing the corresponding bit in RTC_SCCR. The user can now write to the appropriate
Time and Calendar register.
Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control
When entering programming mode of the calendar fields, the time fields remain enabled. When entering the programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the calendar logic circuity (downstream for low-power considerations). It is highly recommended to prepare all the fields to be updated before entering programming mode. In successive update operations, the user must wait at least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these bits again. This is done by waiting for the SEC flag in the Status Register before setting UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared.
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Figure 15-2. Update Sequence
Begin
Prep
a
re TIme or C
a
lend
a
r Field
s
S
et UPDTIM
a
nd/or UPDCAL
b
it(
s
) in RTC_CR
Re
a
d RTC_
S
R
ACKUPD
= 1 ?
No
Ye
s
Cle
a
r ACKUPD
b
it in RTC_
S
CCR
Polling or
IRQ (if en
ab
led)
Upd
a
te Time
a
nd/or C
a
lend
a
r v
a
l
u
e
s
in
RTC_TIMR/RTC_CALR
Cle
a
r UPDTIM
a
nd/or UPDCAL
b
it in
RTC_CR
End
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15.6
Real-time Clock (RTC) User Interface
Table 15-1. Register Mapping
Offset Register Name
0x00 Control Register RTC_CR
0x04
0x08
0x0C
0x10
Mode Register
Time Register
Calendar Register
Time Alarm Register
RTC_MR
RTC_TIMR
RTC_CALR
RTC_TIMALR
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30–0xC4
Calendar Alarm Register
Status Register
Status Clear Command Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Valid Entry Register
Reserved Register
RTC_CALALR
RTC_SR
RTC_SCCR
RTC_IER
RTC_IDR
RTC_IMR
RTC_VER
–
0xC8–0xF8
0xFC
Note:
Reserved Register
Reserved Register
–
–
If an offset is not listed in the table, it must be considered as reserved.
Access
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
Write-only
Write-only
Write-only
Read-only
Read-only
–
–
–
Reset
0x0
0x0
0x0
0x01210720
0x0
0x01010000
0x0
–
–
–
0x0
0x0
–
–
–
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15.6.1 RTC Control Register
Name: RTC_CR
Address: 0xFFFFFEB0
Access: Read-write
31
–
30
–
23
–
15
–
7
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
24
–
17
CALEVSEL
16
9 8
TIMEVSEL
1
UPDCAL
0
UPDTIM
• UPDTIM: Update Request Time Register
0 = No effect.
1 = Stops the RTC time counting.
Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the Status Register.
• UPDCAL: Update Request Calendar Register
0 = No effect.
1 = Stops the RTC calendar counting.
Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set.
• TIMEVSEL: Time Event Selection
The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL.
Value
0
1
2
3
Name
MINUTE
HOUR
MIDNIGHT
NOON
Description
Minute change
Hour change
Every day at midnight
Every day at noon
• CALEVSEL: Calendar Event Selection
The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL
Value
0
1
2
3
Name
WEEK
MONTH
YEAR
–
Description
Week change (every Monday at time 00:00:00)
Month change (every 01 of each month at time 00:00:00)
Year change (every January 1 at time 00:00:00)
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15.6.2 RTC Mode Register
Name: RTC_MR
Address: 0xFFFFFEB4
Access: Read-write
31
–
30
–
23
–
15
–
7
–
22
–
14
–
6
–
• HRMOD: 12-/24-hour Mode
0 = 24-hour mode is selected.
1 = 12-hour mode is selected.
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
HRMOD
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15.6.3 RTC Time Register
Name: RTC_TIMR
Address: 0xFFFFFEB8
Access: Read-write
31
–
30
–
23
–
15
–
7
–
22
AMPM
14
6
29
–
21
13
5
28
–
20
12
4
• SEC: Current Second
The range that can be set is 0 - 59 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• MIN: Current Minute
The range that can be set is 0 - 59 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
27
–
19
11
MIN
3
SEC
HOUR
26
–
18
10
2
• HOUR: Current Hour
The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode.
• AMPM: Ante Meridiem Post Meridiem Indicator
This bit is the AM/PM indicator in 12-hour mode.
0 = AM.
1 = PM.
All non-significant bits read zero.
25
–
17
9
1
24
–
16
8
0
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15.6.4 RTC Calendar Register
Name: RTC_CALR
Address: 0xFFFFFEBC
Access: Read-write
31
–
30
–
23
15
22
DAY
14
29
21
13
28
20
12
27
19
11
YEAR
7
–
6 5 4
• CENT: Current Century
The range that can be set is 19 - 20 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• YEAR: Current Year
The range that can be set is 00 - 99 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
3
CENT
DATE
26
18
MONTH
10
2
25
17
9
1
• MONTH: Current Month
The range that can be set is 01 - 12 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• DAY: Current Day in Current Week
The range that can be set is 1 - 7 (BCD).
The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter.
• DATE: Current Day in Current Month
The range that can be set is 01 - 31 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
24
16
8
0
All non-significant bits read zero.
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15.6.5 RTC Time Alarm Register
Name: RTC_TIMALR
Address: 0xFFFFFEC0
Access: Read-write
31
–
30
–
29
–
23
HOUREN
15
MINEN
7
SECEN
22
AMPM
14
6
21
13
5
28
–
20
12
4
27
–
19
11
MIN
3
SEC
• SEC: Second Alarm
This field is the alarm field corresponding to the BCD-coded second counter.
HOUR
26
–
18
10
2
• SECEN: Second Alarm Enable
0 = The second-matching alarm is disabled.
1 = The second-matching alarm is enabled.
• MIN: Minute Alarm
This field is the alarm field corresponding to the BCD-coded minute counter.
• MINEN: Minute Alarm Enable
0 = The minute-matching alarm is disabled.
1 = The minute-matching alarm is enabled.
• HOUR: Hour Alarm
This field is the alarm field corresponding to the BCD-coded hour counter.
• AMPM: AM/PM Indicator
This field is the alarm field corresponding to the BCD-coded hour counter.
• HOUREN: Hour Alarm Enable
0 = The hour-matching alarm is disabled.
1 = The hour-matching alarm is enabled.
25
–
17
9
1
24
–
16
8
0
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15.6.6 RTC Calendar Alarm Register
Name: RTC_CALALR
Address: 0xFFFFFEC4
Access: Read-write
31
DATEEN
30
–
29
23
MTHEN
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
20
12
–
4
–
27
19
11
–
3
–
• MONTH: Month Alarm
This field is the alarm field corresponding to the BCD-coded month counter.
DATE
26
18
MONTH
10
–
2
–
• MTHEN: Month Alarm Enable
0 = The month-matching alarm is disabled.
1 = The month-matching alarm is enabled.
• DATE: Date Alarm
This field is the alarm field corresponding to the BCD-coded date counter.
• DATEEN: Date Alarm Enable
0 = The date-matching alarm is disabled.
1 = The date-matching alarm is enabled.
25
17
1
–
9
–
24
16
0
–
8
–
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15.6.7 RTC Status Register
Name: RTC_SR
Address: 0xFFFFFEC8
Access: Read-only
31
–
30
–
23
–
15
–
7
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
CALEV
• ACKUPD: Acknowledge for Update
0 (FREERUN) = Time and calendar registers cannot be updated.
1 (UPDATE) = Time and calendar registers can be updated.
• ALARM: Alarm Flag
0 (NO_ALARMEVENT) = No alarm matching condition occurred.
1 (ALARMEVENT) = An alarm matching condition has occurred.
27
–
19
–
11
–
3
TIMEV
26
–
18
–
10
–
2
SEC
25
–
17
–
9
–
1
ALARM
24
–
16
–
8
–
0
ACKUPD
• SEC: Second Event
0 (NO_SECEVENT) = No second event has occurred since the last clear.
1 (SECEVENT) = At least one second event has occurred since the last clear.
• TIMEV: Time Event
0 (NO_TIMEVENT) = No time event has occurred since the last clear.
1 (TIMEVENT) = At least one time event has occurred since the last clear.
The time event is selected in the TIMEVSEL field in RTC_CR (Control Register) and can be any one of the following events: minute change, hour change, noon, midnight (day change).
• CALEV: Calendar Event
0 (NO_CALEVENT) = No calendar event has occurred since the last clear.
1 (CALEVENT) = At least one calendar event has occurred since the last clear.
The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change.
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15.6.8 RTC Status Clear Command Register
Name: RTC_SCCR
Address: 0xFFFFFECC
Access: Write-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
–
4
CALCLR
• ACKCLR: Acknowledge Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• ALRCLR: Alarm Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
27
–
19
–
11
–
3
TIMCLR
• SECCLR: Second Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• TIMCLR: Time Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• CALCLR: Calendar Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
26
–
18
–
10
–
2
SECCLR
25
–
17
–
9
–
1
ALRCLR
24
–
16
–
8
–
0
ACKCLR
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15.6.9 RTC Interrupt Enable Register
Name: RTC_IER
Address: 0xFFFFFED0
Access: Write-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
• ACKEN: Acknowledge Update Interrupt Enable
0 = No effect.
1 = The acknowledge for update interrupt is enabled.
• ALREN: Alarm Interrupt Enable
0 = No effect.
1 = The alarm interrupt is enabled.
28
–
20
–
12
–
4
CALEN
• SECEN: Second Event Interrupt Enable
0 = No effect.
1 = The second periodic interrupt is enabled.
• TIMEN: Time Event Interrupt Enable
0 = No effect.
1 = The selected time event interrupt is enabled.
• CALEN: Calendar Event Interrupt Enable
0 = No effect.
1 = The selected calendar event interrupt is enabled.
27
–
19
–
11
–
3
TIMEN
26
–
18
–
10
–
2
SECEN
25
–
17
–
9
–
1
ALREN
24
–
16
–
8
–
0
ACKEN
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15.6.10 RTC Interrupt Disable Register
Name: RTC_IDR
Address: 0xFFFFFED4
Access: Write-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
• ACKDIS: Acknowledge Update Interrupt Disable
0 = No effect.
1 = The acknowledge for update interrupt is disabled.
• ALRDIS: Alarm Interrupt Disable
0 = No effect.
1 = The alarm interrupt is disabled.
28
–
20
–
12
–
4
CALDIS
• SECDIS: Second Event Interrupt Disable
0 = No effect.
1 = The second periodic interrupt is disabled.
• TIMDIS: Time Event Interrupt Disable
0 = No effect.
1 = The selected time event interrupt is disabled.
• CALDIS: Calendar Event Interrupt Disable
0 = No effect.
1 = The selected calendar event interrupt is disabled.
27
–
19
–
11
–
3
TIMDIS
26
–
18
–
10
–
2
SECDIS
25
–
17
–
9
–
1
ALRDIS
24
–
16
–
8
–
0
ACKDIS
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15.6.11 RTC Interrupt Mask Register
Name: RTC_IMR
Address: 0xFFFFFED8
Access: Read-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
• ACK: Acknowledge Update Interrupt Mask
0 = The acknowledge for update interrupt is disabled.
1 = The acknowledge for update interrupt is enabled.
• ALR: Alarm Interrupt Mask
0 = The alarm interrupt is disabled.
1 = The alarm interrupt is enabled.
28
–
20
–
12
–
4
CAL
• SEC: Second Event Interrupt Mask
0 = The second periodic interrupt is disabled.
1 = The second periodic interrupt is enabled.
• TIM: Time Event Interrupt Mask
0 = The selected time event interrupt is disabled.
1 = The selected time event interrupt is enabled.
• CAL: Calendar Event Interrupt Mask
0 = The selected calendar event interrupt is disabled.
1 = The selected calendar event interrupt is enabled.
27
–
19
–
11
–
3
TIM
26
–
18
–
10
–
2
SEC
25
–
17
–
9
–
1
ALR
24
–
16
–
8
–
0
ACK
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15.6.12 RTC Valid Entry Register
Name: RTC_VER
Address: 0xFFFFFEDC
Access: Read-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
NVCALALR
• NVTIM: Non-valid Time
0 = No invalid data has been detected in RTC_TIMR (Time Register).
1 = RTC_TIMR has contained invalid data since it was last programmed.
• NVCAL: Non-valid Calendar
0 = No invalid data has been detected in RTC_CALR (Calendar Register).
1 = RTC_CALR has contained invalid data since it was last programmed.
• NVTIMALR: Non-valid Time Alarm
0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register).
1 = RTC_TIMALR has contained invalid data since it was last programmed.
• NVCALALR: Non-valid Calendar Alarm
0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register).
1 = RTC_CALALR has contained invalid data since it was last programmed.
26
–
18
–
10
–
2
NVTIMALR
25
–
17
–
9
–
1
NVCAL
24
–
16
–
8
–
0
NVTIM
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16.
Periodic Interval Timer (PIT)
16.1 Description
The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time.
16.2 Embedded Characteristics
20-bit Programmable Counter plus 12-bit Interval Counter
Reset-on-read Feature
Both Counters Work on Master Clock/16
Real Time OS or Linux ® /WinCE ® compliant tick generator
AMBA ™ -compliant Interface
Interfaces to the ARM Advanced Peripheral Bus
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16.3 Block Diagram
Figure 16-1. Periodic Interval Timer
PIT_MR
PIV
=
MCK
Prescaler
MCK/16
0
0 1
20-bit
Counter
CPIV
CPIV
PIT_PIVR
PIT_PIIR
0
0 1
12-bit
Adder
PIT_SR set
PITS reset
PIT_MR
PITIEN pit_irq read PIT_PIVR
PICNT
PICNT
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16.4 Functional Description
The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems.
The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit
CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16.
The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode
Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval
Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR).
Writing a new PIV value in PIT_MR does not reset/restart the counters.
When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR.
When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR.
The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0.
illustrates the PIT counting. After the PIT Enable bit is reset
(PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the
PITEN is set again.
The PIT is stopped when the core enters debug state.
Figure 16-2. Enabling/Disabling PIT with PITEN
APB cycle APB cycle
MCK
15 restarts MCK Prescaler
MCK Prescaler 0
PITEN
0 1 PIV - 1 PIV 0
1
CPIV
PICNT
PITS (PIT_SR)
APB Interface
0
1 0 read PIT_PIVR
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16.5 Periodic Interval Timer (PIT) User Interface
Table 16-1. Register Mapping
Offset Register Name
0x00
0x04
Mode Register
Status Register
PIT_MR
PIT_SR
0x08
0x0C
Periodic Interval Value Register
Periodic Interval Image Register
PIT_PIVR
PIT_PIIR
Access
Read-write
Read-only
Read-only
Read-only
Reset
0x000F_FFFF
0x0000_0000
0x0000_0000
0x0000_0000
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16.5.1 Periodic Interval Timer Mode Register
Name:
Address:
Access:
PIT_MR
0xFFFFFE30
Read-write
31
–
30
–
29
–
23
–
15
22
–
14
21
–
13
28
–
20
–
12
27
–
19
11
26
–
18
10
PIV
25
PITIEN
17
9
24
PITEN
16
8
PIV
7 6 5 4 3 2 1 0
PIV
• PIV: Periodic Interval Value
Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).
• PITEN: Period Interval Timer Enabled
0 = The Periodic Interval Timer is disabled when the PIV value is reached.
1 = The Periodic Interval Timer is enabled.
• PITIEN: Periodic Interval Timer Interrupt Enable
0 = The bit PITS in PIT_SR has no effect on interrupt.
1 = The bit PITS in PIT_SR asserts interrupt.
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16.5.2 Periodic Interval Timer Status Register
Name:
Address:
Access:
PIT_SR
0xFFFFFE34
Read-only
31
–
30
–
29
–
28
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
• PITS: Periodic Interval Timer Status
0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR.
1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
PITS
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16.5.3 Periodic Interval Timer Value Register
Name:
Address:
Access:
PIT_PIVR
0xFFFFFE38
Read-only
31 30 29 28 27 26
PICNT
23 22 21 20 19 18
PICNT
15 14 13 12 11 10
CPIV
7 6 5 4 3
CPIV
Reading this register clears PITS in PIT_SR.
• CPIV: Current Periodic Interval Value
Returns the current value of the periodic interval timer.
• PICNT: Periodic Interval Counter
Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
2
CPIV
25
17
9
1
8
0
24
16
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16.5.4 Periodic Interval Timer Image Register
Name:
Address:
Access:
PIT_PIIR
0xFFFFFE3C
Read-only
31 30 29 28 27 26
PICNT
23 22 21 20 19 18
PICNT
15 14 13 12 11 10
CPIV
7 6 5 4 3
CPIV
• CPIV: Current Periodic Interval Value
Returns the current value of the periodic interval timer.
• PICNT: Periodic Interval Counter
Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
2
CPIV
25
17
9
1
8
0
24
16
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17.
Watchdog Timer (WDT)
17.1 Description
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a
12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode.
17.2 Embedded Characteristics
12-bit Key-protected Programmable Counter
Provides Reset or Interrupt Signals to the System
Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
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17.3 Block Diagram
Figure 17-1. Watchdog Timer Block Diagram
WDT_CR
WDRSTT write WDT_MR
WDT_MR
WDV reload
1 0
WDT_MR
WDD
<= WDD
12-bit Down
Counter
Current
Value
= 0 set
WDUNF reset read WDT_SR or reset set
WDERR reset reload
1/128 SLCK
WDT_MR
WDRSTEN wdt_fault
(to Reset Controller) wdt_int
WDFIEN
WDT_MR
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17.4 Functional Description
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset.
The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode
Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default Watchdog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires.
If the watchdog is restarted by writing into the WDT_CR register, the WDT_MR register must not be programmed during a period of time of 3 slow clock periods following the WDT_CR write access. In any case, programming a new value in the WDT_MR register automatically initiates a restart instruction.
The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the
WDT_MR register reloads the timer with the newly programmed mode parameters.
In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writing the
Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately reloaded from
WDT_MR and restarted, and the Slow Clock 128 divider is reset and restarted. The WDT_CR register is write-protected.
As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode Register (WDT_MR). Moreover, the bit
WDUNF is set in the Watchdog Status Register (WDT_SR).
To prevent a software deadlock that continuously triggers the Watchdog, the reload of the Watchdog must occur while the Watchdog counter is within a window between 0 and WDD, WDD is defined in the WatchDog Mode Register
WDT_MR.
Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the “wdt_fault” signal to the Reset
Controller is asserted.
Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error.
This is the default configuration on reset (the WDD and WDV values are equal).
The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit
WDFIEN is set in the mode register. The signal “wdt_fault” to the reset controller causes a Watchdog reset if the
WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset.
If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted.
Writing the WDT_MR reloads and restarts the down counter.
While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.
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Figure 17-2. Watchdog Behavior
Watchdog Error
FFF
WDV
Forbidden
Window
WDD
Permitted
Window
0
Watchdog
Fault
Normal behavior
WDT_CR = WDRSTT
Watchdog Underflow if WDRSTEN is 1 if WDRSTEN is 0
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17.5 Watchdog Timer (WDT) User Interface
Table 17-1. Register Mapping
Offset Register Name
0x00 Control Register WDT_CR
0x04
0x08
Mode Register
Status Register
WDT_MR
WDT_SR
Access
Write-only
Read-write Once
Read-only
Reset
-
0x3FFF_2FFF
0x0000_0000
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17.5.1 Watchdog Timer Control Register
Name:
Address:
Access:
WDT_CR
0xFFFFFE40
Write-only
31 30 29 28 27 26
KEY
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
20
–
12
–
4
–
19
–
11
–
3
–
• WDRSTT: Watchdog Restart
0: No effect.
1: Restarts the Watchdog.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
18
–
10
–
2
–
25
17
–
9
–
1
–
24
16
–
8
–
0
WDRSTT
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17.5.2 Watchdog Timer Mode Register
Name:
Address:
Access:
WDT_MR
0xFFFFFE44
Read-write Once
31 30 29
WDIDLEHLT
28
WDDBGHLT
23 22 21
15
WDDIS
7
14
WDRPROC
6
13
WDRSTEN
5
27
20 19
WDD
12
WDFIEN
4
WDV
11
3
26
18
10
2
WDD
WDV
25
17
9
1
• WDV: Watchdog Counter Value
Defines the value loaded in the 12-bit Watchdog Counter.
• WDFIEN: Watchdog Fault Interrupt Enable
0: A Watchdog fault (underflow or error) has no effect on interrupt.
1: A Watchdog fault (underflow or error) asserts interrupt.
• WDRSTEN: Watchdog Reset Enable
0: A Watchdog fault (underflow or error) has no effect on the resets.
1: A Watchdog fault (underflow or error) triggers a Watchdog reset.
• WDRPROC: Watchdog Reset Processor
0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets.
1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.
• WDD: Watchdog Delta Value
Defines the permitted range for reloading the Watchdog Timer.
If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer.
If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.
• WDDBGHLT: Watchdog Debug Halt
0: The Watchdog runs when the processor is in debug state.
1: The Watchdog stops when the processor is in debug state.
• WDIDLEHLT: Watchdog Idle Halt
0: The Watchdog runs when the system is in idle mode.
1: The Watchdog stops when the system is in idle state.
• WDDIS: Watchdog Disable
0: Enables the Watchdog Timer.
1: Disables the Watchdog Timer.
24
16
8
0
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17.5.3 Watchdog Timer Status Register
Name:
Address:
Access:
WDT_SR
0xFFFFFE48
Read-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
12
–
4
–
28
–
20
–
11
–
3
–
27
–
19
–
10
–
2
–
26
–
18
–
25
–
17
–
9
–
1
WDERR
24
–
16
–
8
–
0
WDUNF
• WDUNF: Watchdog Underflow
0: No Watchdog underflow occurred since the last read of WDT_SR.
1: At least one Watchdog underflow occurred since the last read of WDT_SR.
• WDERR: Watchdog Error
0: No Watchdog error occurred since the last read of WDT_SR.
1: At least one Watchdog error occurred since the last read of WDT_SR.
Note: The WDD and WDV values must not be modified within a period of time of 3 slow clock periods following a restart of the watchdog performed by means of a write access in the WDT_CR register, else the watchdog may trigger an end of period earlier than expected.
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18.
Shutdown Controller (SHDWC)
18.1 Description
The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines.
18.2 Embedded Characteristics
Shutdown and Wake-up Logic
Software Assertion of the SHDW Output Pin
Programmable De-assertion from the WKUP Input Pins
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18.3 Block Diagram
Figure 18-1. Shutdown Controller Block Diagram
Shutdown Controller
SHDW_MR
CPTWK0
WKMODE0
WKUP0 read SHDW_SR reset
WAKEUP0 set
SHDW_SR
SLCK
RTC Alarm
RTTWKEN SHDW_MR read SHDW_SR reset
RTCWK SHDW_SR set
SHDW_CR
SHDW
Wake-up
Shutdown
Output
Controller
Shutdown
SHDN
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18.4 I/O Lines Description
Table 18-1. I/O Lines Description
Name Description
WKUP0
SHDN
Wake-up 0 input
Shutdown output
Type
Input
Output
18.5 Product Dependencies
18.5.1 Power Management
The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Controller has no effect on the behavior of the Shutdown Controller.
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18.6 Functional Description
The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages wake-up input pins and one output pin, SHDN.
A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies of the system, and especially VDDCORE and/or VDDIO. The wake-up inputs (WKUP0) connect to any pushbuttons or signal that wake up the system.
The software is able to control the pin SHDN by writing the Shutdown Control Register (SHDW_CR) with the bit SHDW at
1. The shutdown is taken into account only 2 slow clock cycles after the write of SHDW_CR. This register is passwordprotected and so the value written should contain the correct key for the command to be taken into account. As a result, the system should be powered down.
A level change on WKUP0 is used as wake-up. Wake-up is configured in the Shutdown Mode Register (SHDW_MR).
The transition detector can be programmed to detect either a positive or negative transition or any level change on
WKUP0. The detection can also be disabled. Programming is performed by defining WKMODE0.
Moreover, a debouncing circuit can be programmed for WKUP0. The debouncing circuit filters pulses on WKUP0 shorter than the programmed number of 16 SLCK cycles in CPTWK0 of the SHDW_MR register. If the programmed level change is detected on a pin, a counter starts. When the counter reaches the value programmed in the corresponding field, CPTWK0, the SHDN pin is released. If a new input change is detected before the counter reaches the corresponding value, the counter is stopped and cleared. WAKEUP0 of the Status Register (SHDW_SR) reports the detection of the programmed events on WKUP0 with a reset after the read of SHDW_SR.
The Shutdown Controller can be programmed so as to activate the wake-up using the RTC alarm (the detection of the rising edge of the RTC alarm is synchronized with SLCK). This is done by writing the SHDW_MR register using the
RTCWKEN field. When enabled, the detection of the RTC alarm is reported in the RTCWK bit of the SHDW_SR Status register. It is reset after the read of SHDW_SR. When using the RTC alarm to wake up the system, the user must ensure that the RTC alarm status flag is cleared before shutting down the system.Otherwise, no rising edge of the status flag may be detected and the wake-up fails fail.
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18.7 Shutdown Controller (SHDWC) User Interface
Table 18-2. Register Mapping
Offset Register Name
0x00
0x04
0x08
Shutdown Control Register
Shutdown Mode Register
Shutdown Status Register
SHDW_CR
SHDW_MR
SHDW_SR
Access
Write-only
Read-write
Read-only
Reset
-
0x0000_0003
0x0000_0000
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18.7.1 Shutdown Control Register
Name:
Address:
Access:
SHDW_CR
0xFFFFFE10
Write-only
31 30 29 28 27 26
KEY
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
20
–
12
–
4
–
19
–
11
–
3
–
18
–
10
–
2
–
• SHDW: Shutdown Command
0 = No effect.
1 = If KEY is correct, asserts the SHDN pin.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
25
17
–
9
–
1
–
24
16
–
8
–
0
SHDW
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18.7.2 Shutdown Mode Register
Name:
Address:
Access:
SHDW_MR
0xFFFFFE14
Read/Write
31
–
30
–
29
–
23
–
15
7
22
–
14
–
6
CPTWK0
5
21
–
13
28
–
20
–
12
4
27
–
19
–
11
–
3
–
• WKMODE0: Wake-up Mode 0
1
1
0
0
WKMODE[1:0]
0
1
0
1
Wake-up Input Transition Selection
None. No detection is performed on the wake-up input
Low to high level
High to low level
Both levels change
26
–
18
–
10
–
2
–
25
–
17
RTCWKEN
9
–
1
WKMODE0
0
24
–
16
–
8
• CPTWK0: Counter on Wake-up 0
Defines the number of 16 Slow Clock cycles, the level detection on the corresponding input pin shall last before the wake-up event occurs. Because of the internal synchronization of WKUP0, the SHDN pin is released
(CPTWK x 16 + 1) Slow Clock cycles after the event on WKUP.
• RTCWKEN: Real-time Clock Wake-up Enable
0 = The RTC Alarm signal has no effect on the Shutdown Controller.
1 = The RTC Alarm signal forces the de-assertion of the SHDN pin.
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18.7.3 Shutdown Status Register
Name:
Address:
Access:
SHDW_SR
0xFFFFFE18
Read-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
RTCWK
9
–
1
–
• WAKEUP0: Wake-up 0 Status
0 = No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.
1 = At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.
• RTCWK: Real-time Clock Wake-up
0 = No wake-up alarm from the RTC occurred since the last read of SHDW_SR.
1 = At least one wake-up alarm from the RTC occurred since the last read of SHDW_SR.
24
–
16
–
8
–
0
WAKEUP0
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19.
General Purpose Backup Registers (GPBR)
19.1 Description
The System Controller embeds Four General-purpose Backup Registers.
19.2 Embedded Characteristics
Four 32-bit General Purpose Backup Registers
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19.3 General Purpose Backup Registers (GPBR) User Interface
Table 19-1. Register Mapping
Offset Register
0x0 General Purpose Backup Register 0
...
0xc
...
General Purpose Backup Register 3
Name
SYS_GPBR0
...
SYS_GPBR3
19.3.1 General Purpose Backup Register x
Name:
Address:
Access:
SYS_GPBRx
0xFFFFFE60
Read-write
31 30 29
23
15
7
22
14
6
21
13
5
28
GPBR_VALUE
27
20
GPBR_VALUE
19
12
GPBR_VALUE
11
4
GPBR_VALUE
3
• GPBR_VALUE: Value of GPBR x
26
18
10
2
Access
Read-write
...
Read-write
Reset
–
...
–
25
17
9
1
24
16
8
0
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20.
Slow Clock Controller (SCKC)
20.1 Description
The System Controller embeds a Slow Clock Controller.
The slow clock can be generated either by an external 32768 Hz crystal oscillator or by the on-chip 32 kHz RC oscillator.
The 32768 Hz crystal oscillator can be bypassed by setting the OSC32BYP bit to accept an external slow clock on
XIN32.
The internal 32 kHz RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1, respectively, RCEN bit and
OSC32EN bit in the System Controller user interface. The OSCSEL command selects the slow clock source.
20.2 Embedded Characteristics
32 kHz RC Oscillator or 32768 Hz Crystal Oscillator Selector
VDDBU Powered
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20.3 Block Diagram
Figure 20-1. Block Diagram
RCEN
On Chip
RC OSC
Slow Clock
SLCK
XIN32
XOUT32
Slow Clock
Oscillator
OSCSEL
OSC32EN
OSC32BYP
RCEN, OSC32EN, OSCSEL and OSC32BYP bits are located in the Slow Clock Configuration Register (SCKC_CR) located at the address 0xFFFFFE50 in the backed up part of the System Controller and, thus, they are preserved while
VDDBU is present.
After a VDDBU power on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSCSEL = 0, allowing the system to start on the internal 32 kHz RC oscillator.
The programmer controls the slow clock switching by software and so must take precautions during the switching phase.
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20.3.1 Switch from Internal 32 kHz RC Oscillator to 32768 Hz Crystal Oscillator
To switch from the internal 32 kHz RC oscillator to the 32768 Hz crystal oscillator, the programmer must execute the following sequence:
Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power
Management Controller.
Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1.
Wait 32768 Hz Startup Time for clock stabilization (software loop).
Switch from internal 32 kHz RC oscillator to 32768 Hz oscillator by setting the bit OSCSEL to 1.
Wait 5 slow clock cycles for internal resynchronization.
Disable the 32 kHz RC oscillator by setting the bit RCEN to 0.
20.3.2 Bypass the 32768 Hz Oscillator
The following steps must be added to bypass the 32768 Hz oscillator:
An external clock must be connected on XIN32.
Enable the bypass path OSC32BYP bit set to 1.
Disable the 32768 Hz oscillator by setting the OSC32EN bit to 0.
20.3.3 Switch from 32768 Hz Crystal Oscillator to Internal 32 kHz RC Oscillator
The same procedure must be followed to switch from the 32768 Hz crystal oscillator to the internal 32 kHz RC oscillator:
Switch the master clock to a source different from slow clock (PLL or Main Oscillator).
Enable the internal 32 kHz RC oscillator for low power by setting the bit RCEN to 1
Wait internal 32 kHz RC Startup Time for clock stabilization (software loop).
Switch from 32768 Hz oscillator to internal RC by setting the bit OSCSEL to 0.
Wait 5 slow clock cycles for internal resynchronization.
Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0.
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20.4 Slow Clock Configuration (SCKC) User Interface
Table 20-1. Register Mapping
Offset Register
0x0 Slow Clock Configuration Register
Name
SCKC_CR
Access Reset
Read-write 0x0000_0001
20.4.1 Slow Clock Configuration Register
Name:
Address:
Access:
Reset:
31
–
SCKC_CR
0xFFFFFE50
Read-write
0x0000_0001
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
12
–
4
–
28
–
20
–
• RCEN: Internal 32 kHz RC Oscillator
0: 32 kHz RC oscillator is disabled.
1: 32 kHz RC oscillator is enabled.
• OSC32EN: 32768 Hz Oscillator
0: 32768 Hz oscillator is disabled.
1: 32768 Hz oscillator is enabled.
• OSC32BYP: 32768Hz Oscillator Bypass
0: 32768 Hz oscillator is not bypassed.
1: 32768 Hz oscillator is bypassed, accept an external slow clock on XIN32.
• OSCSEL: Slow Clock Selector
0 (RC): Slow clock is internal 32 kHz RC oscillator.
1 (XTAL): Slow clock is 32768 Hz oscillator.
27
–
19
–
11
–
3
OSCSEL
26
–
18
–
10
–
2
OSC32BYP
25
–
17
–
9
–
1
OSC32EN
8
–
0
RCEN
24
–
16
–
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21.
Clock Generator (CKGR)
21.1 Description
22.13 ”Power Management Controller (PMC) User Interface”
. However, the Clock Generator registers are named
CKGR_.
21.2 Embedded Characteristics
The Clock Generator is made up of:
A Low Power 32768 Hz Slow Clock Oscillator with bypass mode
A Low Power RC Oscillator
A 12 to 16 MHz Crystal Oscillator, which can be bypassed (12 MHz needed in case of USB)
A Fast RC Oscillator, at 12 MHz.
A 480 MHz UTMI PLL providing a clock for the USB High Speed Device Controller
A 400 to 800 MHz programmable PLL (input from 8 to 16 MHz), capable of providing the clock MCK to the processor and to the peripherals.
It provides the following clocks:
SLCK, the Slow Clock, which is the only permanent clock within the system
MAINCK is the output of the Main Clock Oscillator selection: either Crystal Oscillator or 12 MHz Fast RC Oscillator
PLLACK is the output of the Divider and 400 to 800 MHz programmable PLL (PLLA)
UPLLCK is the output of the 480 MHz UTMI PLL (UPLL)
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21.3 CKGR Block Diagram
Figure 21-1. Clock Generator Block Diagram
XIN32
XOUT32
XIN
XOUT
Clock Generator
On Chip
32K RC OSC
Slow Clock
Oscillator
On Chip
12M RC OSC
12M Main
Oscillator
UPLL
PLLA and
Divider
Status Control
Power
Management
Controller
UPLLCK
PLLA Clock
PLLACK
RCEN
Slow Clock
SLCK
OSCSEL
OSC32EN
OSC32BYP
MOSCRCEN
MOSCSEL
Main Clock
MAINCK
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21.4 Slow Clock Selection
The slow clock can be generated either by an external 32768 Hz crystal or by the on-chip 32 kHz RC oscillator.
The 32768 Hz crystal oscillator can be bypassed by setting the OSC32BYP bit to accept an external slow clock on
XIN32.
The internal 32 kHz RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1, respectively, the RCEN bit and the OSC32EN bit in the System Controller user interface. The OSCSEL command selects the slow clock source.
Figure 21-2. Slow Clock
Clock Generator
RCEN
On Chip
RC OSC
Slow Clock
SLCK
XIN32
XOUT32
Slow Clock
Oscillator
OSCSEL
OSC32EN
OSC32BYP
RCEN, OSC32EN,OSCSEL and OSC32BYP bits are located in the Slow Clock Control Register (SCKCR) located at address 0xFFFFFE50 in the backed up part of the System Controller and so are preserved while VDDBU is present.
After a VDDBU power on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSCSEL = 0, BYPASS = 0, allowing the system to start on the internal 32 kHz RC oscillator.
The programmer controls the slow clock switching by software and so must take precautions during the switching phase.
21.4.1 Switch from Internal 32 kHz RC Oscillator to the 32768 Hz Crystal
To switch from internal 32 kHz RC oscillator to the 32768 Hz crystal, the programmer must execute the following sequence:
Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power
Management Controller.
Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1.
Wait 32768 Hz Startup Time for clock stabilization (software loop).
Switch from internal 32 kHz RC to 32768 Hz oscillator by setting the bit OSCSEL to 1.
Wait 5 slow clock cycles for internal resynchronization.
Disable the 32 kHz RC oscillator by setting the bit RCEN to 0.
Switch the master clock back to the slow clock domain
21.4.2 Bypass the 32768 Hz Oscillator
The following step must be added to bypass the 32768 Hz Oscillator.
An external clock must be connected on XIN32.
Enable the bypass path OSC32BYP bit set to 1.
Disable the 32768 Hz oscillator by setting the OSC32EN bit to 0.
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21.4.3 Switch from the 32768 Hz Crystal to Internal 32 kHz RC Oscillator
The same procedure must be followed to switch from a 32768 Hz crystal to the internal 32 kHz RC oscillator.
Switch the master clock to a source different from slow clock (PLL or Main Oscillator).
Enable the internal 32 kHz RC oscillator for low power by setting the bit RCEN to 1
Wait internal 32 kHz RC Startup Time for clock stabilization (software loop).
Switch from 32768 Hz oscillator to internal RC by setting the bit OSCSEL to 0.
Wait 5 slow clock cycles for internal resynchronization.
Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0.
Switch the master clock back to the slow clock domain
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21.4.4 Slow Clock Configuration Register
Name:
Address:
Access:
Reset Value:
31
–
SCKCR
0xFFFFFE50
Read-write
0x0000_0001
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
• RCEN: Internal 32 kHz RC
0: 32 kHz RC is disabled
1: 32 kHz RC is enabled
• OSC32EN: 32768 Hz oscillator
0: 32768 Hz oscillator is disabled
1: 32768 Hz oscillator is enabled
• OSC32BYP: 32768 Hz oscillator bypass
0: 32768 Hz oscillator is not bypassed
1: 32768 Hz oscillator is bypassed, accept an external slow clock on XIN32
• OSCSEL: Slow clock selector
0: Slow clock is internal 32 kHz RC
1: Slow clock is 32768 Hz oscillator
27
–
19
–
11
–
3
OSCSEL
26
–
18
–
10
–
2
OSC32BYP
25
–
17
–
9
–
1
OSC32EN
24
–
16
–
8
–
0
RCEN
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21.5 Main Clock
Figure 21-3. Main Clock Block Diagram
MOSCRCEN MOSCRCF
12 MHz
Fast RC
Oscillator
MOSCRCS
MOSCSEL
1
MOSCXTEN
0
XIN
XOUT
3-20 MHz
Crystal
Oscillator
SLCK
Slow Clock
MOSCXTCNT
3-20 MHz Crystal
Oscillator
Counter
MOSCXTS
MOSCRCEN
MOSCXTEN
MOSCSEL
Main Clock
Frequency
Counter
MAINF
MAINRDY
The Main Clock has two sources:
12 MHz Fast RC Oscillator which starts very quickly and is used at startup
12 to 16 MHz Crystal Oscillator, which can be bypassed
MOSCSELS
MAINCK
Main Clock
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21.6 Main Clock Selection
The main clock can be generated either by an external 12 MHz crystal oscillator or by the on-chip 12 MHz RC oscillator.
This fast RC oscillator allows the processor to start or restart in a few microseconds when 12 MHz internal RC is selected.
The 12 MHz crystal oscillator can be bypassed by setting the MOSCXTBY bit to accept an external main clock on XIN.
Figure 21-4. Main Clock Selection
MOSCRCEN
On Chip
12M RC OSC
Main Clock
XIN
XOUT
Main Clock
Oscillator
MOSCSEL
MOSCXTEN
MOSCXTBY
MOSCRCEN, MOSCXTEN, MOSCSEL and MOSCXTBY bits are located in the PMC Clock Generator Main Oscillator
Register (CKGR_MOR).
After a VDDBU power on reset, the default configuration is MOSCRCEN = 1, MOSCXTEN = 0 and MOSCSEL = 0, the
12 MHz RC oscillator is started as Main clock.
21.6.1 Fast wake-up
To speed up the wake-up phase, the system boots on 12 MHz RC (Main Clock). This allows the user to perform system configuration (PLL, DDR2, etc.) at 12 MHz instead of 32 kHz during 12 MHz oscillator start-up.
Figure 21-5. PMC Startup
12 MHz RC
Extern a l M a in Cock
M a in Su pply
POR o u tp u t
12 MHz RC
S y s tem s t a rt s on 3 2 kHz RC
RCEN = 1
O S C 3 2EN = 0
O S C S EL = 0
MO S CRCEN = 1
MO S CXTEN = 0
MO S C S EL = 0
PMC_MCKR = 1
S t a rt u p Time i
W a it MO S CRC S = 1
S y s tem s witche s on M a in Clock to s peedu p the b oot
S y s tem i s r u nning a t 12 MHz
Extern s s
MO t a
S a l o s cill rted for b a
CXTEN = 1
MO S C S EL = 0 tor etter a cc u r a
Cry s t a l S t a rt u p Time cy
W a it MO S CXT S = 1
U s er s witche s on extern a l o s cill a tor
MO S C S EL=1
W a it while MO S C S EL S =1
S y s tem i s r u nnning on 12 MHz Cry s t a l
PLL c a n b e us ed
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21.6.2 Switch from Internal 12 MHz RC Oscillator to the 12 MHz Crystal
For USB operations an external 12 MHz crystal is required for better accuracy.
The programmer controls the main clock switching by software and so must take precautions during the switching phase.
To switch from internal 12 MHz RC oscillator to the 12 MHz crystal, the programmer must execute the following sequence:
Enable the 12 MHz oscillator by setting the bit MOSCXTEN to 1.
Wait that the 12 MHz oscillator status bit MOSCXTS is 1.
Switch from internal 12 MHz RC oscillator to the 12 MHz oscillator by setting the bit MOSCSEL to 1.
If not the bit MOSCSEL is set to 0 by the PMC.
Disable the 12 MHz RC oscillator by setting the bit MOSCRCEN to 0.
21.6.3 Bypass the 12 MHz Oscillator
Following step must be added to bypass the 12 MHz Oscillator.
An external clock must be connected on XIN.
Enable the bypass path MOSCXTBY bit set to 1.
Disable the 12 MHz oscillator by setting the bit MOSCXTEN to 0.
21.6.4 Switch from the 12 MHz Crystal to Internal 12 MHz RC Oscillator
The same procedure must be followed to switch from a 12 MHz crystal to the internal 12 MHz RC oscillator.
Enable the internal 12 MHz RC oscillator for low power by setting the bit MOSCRCEN to 1
Wait internal 12 MHz RC Startup Time for clock stabilization (software loop).
Switch from 12 MHz oscillator to internal 12 MHz RC oscillator by setting the bit MOSCSEL to 0.
Disable the 12 MHz oscillator by setting the bit MOSCXTEN to 0.
21.6.5 12 MHz Fast RC Oscillator
After reset, the 12 MHz Fast RC Oscillator is enabled and it is selected as the source of MCK. MCK is the default clock selected to start up the system.
Please refer to the “DC Characteristics” section of the product datasheet.
The software can disable or enable the 12 MHz Fast RC Oscillator with the MOSCRCEN bit in the Clock Generator Main
Oscillator Register (CKGR_MOR).
When disabling the Main Clock by clearing the MOSCRCEN bit in CKGR_MOR, the MOSCRCS bit in the Power
Management Controller Status Register (PMC_SR) is automatically cleared, indicating the Main Clock is off.
Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger an interrupt to the processor.
21.6.6 12 to 16 MHz Crystal Oscillator
After reset, the 12 to 16 MHz Crystal Oscillator is disabled and it is not selected as the source of MAINCK.
The user can select the 12 to 16 MHz crystal oscillator to be the source of MAINCK, as it provides a more accurate frequency. The software enables or disables the main oscillator so as to reduce power consumption by clearing the
MOSCXTEN bit in the Main Oscillator Register (CKGR_MOR).
When disabling the main oscillator by clearing the MOSCXTEN bit in CKGR_MOR, the MOSCXTS bit in PMC_SR is automatically cleared, indicating the Main Clock is off.
When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillator. This startup time depends on the crystal frequency connected to the oscillator.
When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to enable the main oscillator, the
MOSCXTS bit in the Power Management Controller Status Register (PMC_SR) is cleared and the counter starts
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counting down on the slow clock divided by 8 from the MOSCXTCNT value. Since the MOSCXTCNT value is coded with
8 bits, the maximum startup time is about 62 ms.
When the counter reaches 0, the MOSCXTS bit is set, indicating that the main clock is valid. Setting the MOSCXTS bit in
PMC_IMR can trigger an interrupt to the processor.
21.6.7 Main Clock Oscillator Selection
The user can select either the 12 MHz Fast RC Oscillator or the 12 to 16 MHz Crystal Oscillator to be the source of Main
Clock.
The advantage of the 12 MHz Fast RC Oscillator is to have fast startup time, this is why it is selected by default (to start up the system) and when entering in Wait Mode.
The advantage of the 12 to 16 MHz Crystal Oscillator is that it is very accurate.
The selection is made by writing the MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of the Main
Clock source is glitch free, so there is no need to run out of SLCK, PLLACK or UPLLCK in order to change the selection.
The MOSCSELS bit of the Power Management Controller Status Register (PMC_SR) allows knowing when the switch sequence is done.
Setting the MOSCSELS bit in PMC_IMR can trigger an interrupt to the processor.
21.6.8 Main Clock Frequency Counter
The device features a Main Clock frequency counter that provides the frequency of the Main Clock.
The Main Clock frequency counter is reset and starts incrementing at the Main Clock speed after the next rising edge of the Slow Clock in the following cases:
When the 12 MHz Fast RC Oscillator clock is selected as the source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCRCS bit is set)
When the 12 to 16 MHz Crystal Oscillator is selected as the source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit is set)
When the Main Clock Oscillator selection is modified
Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main Clock Frequency Register
(CKGR_MCFR) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the 12 MHz Fast RC
Oscillator or 12 to 16 MHz Crystal Oscillator can be determined.
21.7 Divider and PLLA Block
The PLLA embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect the PLLA minimum input frequency when programming the divider.
Figure 21-6 shows the block diagram of the divider and PLLA block.
Figure 21-6. Divider and PLLA Block Diagram
DIVA MULA OUTA PLLADIV2
MAINCK Divider PLLA
/1 or /2
Divider
PLLACK
SLCK
PLLACOUNT
PLLA
Counter
LOCKA
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21.7.1 Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
The PLLA allows multiplication of the divider’s outputs. The PLLA clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIVA and MULA. The factor applied to the source signal frequency is (MULA + 1)/DIVA. When MULA is written to 0, the PLLA is disabled and its power consumption is saved.
Re-enabling the PLLA can be performed by writing a value higher than 0 in the MUL field.
Whenever the PLLA is re-enabled or one of its parameters is changed, the LOCKA bit in PMC_SR is automatically cleared. The values written in the PLLACOUNT field in CKGR_PLLAR are loaded in the PLLA counter. The PLLA counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the
PLLA transient time into the PLLACOUNT field.
The PLLA clock can be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR register.
21.8 UTMI Phase Lock Loop Programming
The source clock of the UTMI PLL is the Main Clock MAINCK. When the 12 MHz Fast RC Oscillator is selected as the source of MAINCK, the 12 MHz frequency must also be selected because the UTMI PLL multiplier contains a built-in multiplier of x 40 to obtain the USB High Speed 480 MHz.
A 12 MHz crystal is needed to use the USB.
Figure 21-7. UTMI PLL Block Diagram
UPLLEN
MAINCK UTMI PLL UPLLCK
SLCK
UPLLCOUNT
UTMI PLL
Counter
LOCKU
Whenever the UTMI PLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UTMI PLL counter. The UTMI PLL counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0. At this time, the LOCKU bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the UTMI PLL transient time into the PLLCOUNT field.
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22.
Power Management Controller (PMC)
22.1 Description
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Core.
22.2 Embedded Characteristics
The Power Management Controller provides all the clock signals to the system.
PMC input clocks:
UPLLCK : From UTMI PLL
PLLACK : From PLLA
SLCK: slow clock from external 32 kHz oscillator or internal 32 kHz RC oscillator
MAINCK: Main Clock from external 12 MHz oscillator or internal 12 MHz RC Oscillator
PMC output clocks:
Processor Clock PCK.
Master Clock MCK, in particular to the Matrix, the memory interfaces, the peripheral bridge. The divider can be 2,
3 or 4.
Each peripheral embeds its own divider, programmable in the PMC User Interface.
133 MHz DDR clock
Note: DDR clock is not available when Master Clock (MCK) equals Processor Clock (PCK).
LCD pixel clock that can use DDR clock or MCK, the choice is done in the LCD user interface.
USB Host EHCI High speed clock (UPLLCK)
USB OHCI clocks (UHP48M and UHP12M)
Two programmable clock outputs: PCK0 and PCK1
SMD clock
This allows software control of five flexible operating modes:
Normal Mode, processor and peripherals running at a programmable frequency
Idle Mode, processor stopped waiting for an interrupt
Slow Clock Mode, processor and peripherals running at low frequency
Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt
Backup Mode, Main Power Supplies off, VDDBU powered by a battery
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22.3 Master Clock Controller
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs.
The Master Clock Controller is made up of a clock selector and a prescaler. It also contains a Master Clock divider which allows the processor clock to be faster than the Master Clock.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock
Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done.
Figure 22-1. Master Clock Controller
PMC_MCKR
CSS
SLCK
MAINCK
PLLACK
UPLLCK
PMC_MCKR
PRES
Master Clock
Prescaler
MCK
To the Processor
Clock Controller (PCK)
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22.4 Block Diagram
Figure 22-2. General Clock Block Diagram
PLLACK
U S B S
U S BDIV+1
/4
UHP4 8 M
UHP12M
U S B
OHCI
U S B
EHCI
UPLLCK
MAINCK
S LCK
Pre s c a ler
/1,/2,/ 3 ,/4,...,/64
M as ter Clock Controller
Divider
X /1 /1.5 /2
/1 /2 / 3 /4
Proce ss
Clock or
Controller
/2
PCK int
DDRCK
2x MCK
MCK
Peripher a l s
Clock Controller
ON/OFF
Divider Periph_clk[..]
S LCK
MAINCK
UPLLCK
Pre s c a ler
/1,/2,/4,...,/64
ON/OFF
Progr a mm ab le Clock Controller pck[..]
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22.5 Processor Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The
Processor Idle Mode is achieved by disabling the Processor Clock and entering Wait for Interrupt Mode. The Processor
Clock is automatically re-enabled by any enabled fast or normal interrupt, or by reset of the product.
Note: The ARM Wait for Interrupt mode is entered by means of CP15 coprocessor operation. Refer to the Atmel application note, Optimizing Power Consumption for AT91SAM9261-based Systems , lit. number 6217.
When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus.
22.6 USB Device and Host Clocks
The USB Device and Host High Speed ports clocks are controlled by the UDPHS and UHPHS bits in PMC_PCER. To save power on this peripheral when they are is not used, the user can set these bits in PMC_PCDR. The UDPHS and
UHPHS bits in PMC_PCR give the activity of these clocks.
The PMC also provides the clocks UHP48M and UHP12M to the USB Host OHCI. The USB Host OHCI clocks are controlled by the UHP bit in PMC_SCER. To save power on this peripheral when it is not used, the user can set the UHP bit in PMC_SCDR. The UHP bit in PMC_SCSR gives the activity of this clock. The USB host OHCI requires both the
12/48 MHz signal and the Master Clock. USBDIV field in PMC_USB register is to be programmed to 9 (division by 10) for normal operations.
To save more power consumption the user can stop UTMI PLL, in this case USB high-speed operations are not possible.
Nevertheless, as the USB OHCI Input clock can be selected with USBS bit (PLLA or UTMI PLL) in PMC_USB register,
OHCI full-speed operation remain possible.
The user must program the USB OHCI Input Clock and the USBDIV divider in PMC_USB register to generate a 48 MHz and a 12 MHz signal with an accuracy of
±
0.25%.
22.7 LP-DDR/DDR2 Clock
The Power Management Controller controls the clocks of the DDR memory.
The DDR clock can be enabled and disabled with DDRCK bit respectively in PMC_SCER and PMC_SDER registers. At reset DDR clock is disabled to save power consumption.
In the case MDIV = ‘00’, (PCK = MCK) and DDRCK clock is not available.
If Input clock is PLLACK/PLLADIV2 the DDR Controller can drive DDR2 and LP-DDR at up to 133 MHz with MDIV = ‘11’.
To save PLLA power consumption, the user can choose UPLLCK an Input clock for the system. In this case the DDR
Controller can drive LD-DDR at up to 120 MHz.
22.8 Software Modem Clock
The Power Management Controller controls the clocks of the Software Modem.
SMDCK is a division of UPLL or PLLA.
22.9 Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by means of the Peripheral Clock
Controller. The user can individually enable and disable the clock on the peripherals and select a division factor from
MCK. This is done through the Peripheral Control Register (PMC_PCR).
In order to save power consumption, the division factor can be 1, 2, 4 or 8. PMC_PCR is a register that features a command and acts like a mailbox. To write the division factor on a particular peripheral, the user needs to write a WRITE
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command, the peripheral ID and the chosen division factor. To read the current division factor on a particular peripheral, the user just needs to write the READ command and the peripheral ID.
Code Example to select divider 8 for peripheral 2 and enable its clock: write_register(PMC_PCR,0x010031002)
Code Example to read the divider of peripheral 4: write_register(PMC_PCR,0x00000004) read_register(PMC_PCR)
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system.
The bit number within the Peripheral Control registers is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral.
22.10 Programmable Clock Output Controller
The PMC controls 2 signals to be output on external pins PCKx. Each signal can be independently programmed via the
PMC_PCKx registers.
PCKx can be independently selected between the Slow clock, the Master Clock, the PLLACK/PLLADIV2, the UTMI PLL output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and
PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR
(System Clock Status Register).
Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been programmed in the Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed.
22.11 Programming Sequence
1.
Enabling the 12 MHz Main Oscillator:
The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in the
CKGR_MOR register.
Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to MOSCS has been enabled in the PMC_IER register.
2.
Setting PLLA and divider:
All parameters needed to configure PLLA and the divider are located in the CKGR_PLLAR register.
The DIVA field is used to control the divider itself. A value between 0 and 255 can be programmed. Divider output is divider input divided by DIVA parameter. By default DIVA parameter is set to 0 which means that divider is turned off.
The OUTA field is used to select the PLLA output frequency range.
The MULA field is the PLLA multiplier factor. This parameter can be programmed between 0 and 254. If MULA is set to 0, PLLA will be turned off, otherwise the PLLA output frequency is PLLA input frequency multiplied by
(MULA + 1).
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The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR register after CKGR_PLLAR register has been written.
Once the PMC_PLLAR register has been written, the user must wait for the LOCKA bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCKA has been enabled in the PMC_IER register. All parameters in CKGR_PLLAR can be programmed in a single write operation. If at some stage one of the following parameters, MULA, DIVA is modified, LOCKA bit will go low to indicate that PLLA is not ready yet. When PLLA is locked, LOCKA will be set again.
The user is constrained to wait for LOCKA bit to be set before using the PLLA output clock.
Code Example: write_register(CKGR_PLLAR,0x00040805)
If PLLA and divider are enabled, the PLLA input clock is the main clock. PLLA output clock is PLLA input clock multiplied by 5. Once CKGR_PLLAR has been written, LOCKA bit will be set after eight slow clock cycles.
3.
Setting Bias and High Speed PLL (UPLL) for UTMI
The UTMI PLL is enabled by setting the UPLLEN field in the CKGR_UCKR register. The UTMI Bias must is enabled by setting the BIASEN field in the CKGR_UCKR register in the same time. In some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the PLLCOUNT field in the
CKGR_UCKR register.
Once this register has been correctly configured, the user must wait for LOCKU field in the PMC_SR register to be set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCKU has been enabled in the PMC_IER register.
4.
Selection of Master Clock and Processor Clock
The Master Clock and the Processor Clock are configurable via the PMC_MCKR register.
The CSS field is used to select the clock source of the Master Clock and Processor Clock dividers. By default, the selected clock source is slow clock.
The PRES field is used to control the Master/Processor Clock prescaler. The user can choose between different values (1, 2, 4, 8, 16, 32, 64). Prescaler output is the selected clock source divided by PRES parameter. By default, PRES parameter is set to 1 which means that the input clock of the Master Clock and Processor Clock dividers is equal to slow clock.
The MDIV field is used to control the Master Clock divider. It is possible to choose between different values (0, 1,
2, 3). The Master Clock output is Master/Processor Clock Prescaler output divided by 1, 2, 4 or 3, depending on the value programmed in MDIV.
The PLLADIV2 field is used to control the PLLA Clock divider. It is possible to choose between different values (0,
1). The PMC PLLA Clock input is divided by 1 or 2, depending on the value programmed in PLLADIV2.
By default, MDIV and PLLLADIV2 are set to 0, which indicates that Processor Clock is equal to the Master Clock.
Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER register.
The PMC_MCKR register must not be programmed in a single write operation. The preferred programming sequence for the PMC_MCKR register is as follows:
If a new value for CSS field corresponds to PLLA Clock,
Program the PRES field in the PMC_MCKR register.
Wait for the MCKRDY bit to be set in the PMC_SR register.
Program the CSS field in the PMC_MCKR register.
Wait for the MCKRDY bit to be set in the PMC_SR register.
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If a new value for CSS field corresponds to Main Clock or Slow Clock,
Program the CSS field in the PMC_MCKR register.
Wait for the MCKRDY bit to be set in the PMC_SR register.
Program the PRES field in the PMC_MCKR register.
Wait for the MCKRDY bit to be set in the PMC_SR register.
If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks.
Note: IF PLLA clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLAR, the MCKRDY flag will go low while PLLA is unlocked. Once PLLA is locked again, LOCK goes high and
MCKRDY is set.
While PLLA is unlocked, the Master Clock selection is automatically changed to Main Clock. For further information, see
. “Clock Switching Waveforms” on page 183 .
Code Example: write_register(PMC_MCKR,0x00000001) wait (MCKRDY=1) write_register(PMC_MCKR,0x00000011) wait (MCKRDY=1)
The Master Clock is main clock divided by 16.
The Processor Clock is the Master Clock.
5.
Selection of Programmable clocks
Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR.
Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, 2 programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication as to which Programmable clock is enabled. By default all Programmable clocks are disabled.
PMC_PCKx registers are used to configure programmable clocks.
The CSS and CSSMCK fields are used to select the programmable clock divider source. Five clock options are available: main clock, slow clock, master clock, PLLACK, UPLLCK. By default, the clock source selected is slow clock.
The PRES field is used to control the programmable clock prescaler. It is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By default, the PRES parameter is set to 1 which means that master clock is equal to slow clock.
Once the PMC_PCKx register has been programmed, The corresponding programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write operation.
If the CSS and PRES parameters are to be modified, the corresponding programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the programmable clock and wait for the PCKRDYx bit to be set.
Code Example: write_register(PMC_PCK0,0x00000015)
Programmable clock 0 is main clock divided by 32.
6.
Enabling Peripheral Clocks
Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCER and PMC_PCDR.
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Depending on the system used, 19 peripheral clocks can be enabled or disabled. The PMC_PCR provides a clear view as to which peripheral clock is enabled.
Note: Each enabled peripheral clock corresponds to Master Clock.
Code Examples: write_register(PMC_PCER,0x00000110)
Peripheral clocks 4 and 8 are enabled. write_register(PMC_PCDR,0x00000010)
Peripheral clock 4 is disabled.
22.12 Clock Switching Details
22.12.1 Master Clock Switching Timings
give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of
64 clock cycles of the new selected clock has to be added.
Table 22-1. Clock Switching Timings (Worst Case)
Fro m Main Clock
To
SLCK PLL Clock
Main
Clock
–
4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
3 x PLL Clock +
5 x SLCK
SLCK
PLL Clock
0.5 x Main Clock +
4.5 x SLCK
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
–
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
Notes: 1. PLL designates either the PLLA or the UPLL Clock.
2. PLLCOUNT designates either PLLACOUNT or UPLLCOUNT.
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
Table 22-2. Clock Switching Timings between Two PLLs (Worst Case)
Fro m PLLA Clock
To
PLLA Clock
UPLL
Clock
2.5 x PLLA Clock +
4 x SLCK +
PLLACOUNT x SLCK
3 x UPLL Clock +
4 x SLCK +
1.5 x UPLL Clock
UPLL Clock
3 x PLLA Clock +
4 x SLCK +
1.5 x PLLA Clock
2.5 x UPLL Clock +
4 x SLCK +
UPLLCOUNT x SLCK
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22.12.2 Clock Switching Waveforms
Figure 22-3. Switch Master Clock from Slow Clock to PLL Clock
Slow Clock
PLL Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
Figure 22-4. Switch Master Clock from Main Clock to Slow Clock
Slow Clock
Main Clock
MCKRDY
Master Clock
Write PMC_MCKR
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Figure 22-5. Change PLLA Programming
Slow Clock
PLLA Clock
LOCKA
MCKRDY
Master Clock
Write CKGR_PLLAR
Figure 22-6. Programmable Clock Output Programming
PLL Clock
PCKRDY
PCKx Output
Slow Clock
Write PMC_PCKx
Write PMC_SCER
PLL Clock is selected
PCKx is enabled
Write PMC_SCDR PCKx is disabled
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22.13 Power Management Controller (PMC) User Interface
Table 22-3. Register Mapping
Offset Register
0x0000 System Clock Enable Register
0x0004
0x0008
0x0010
0x0014
System Clock Disable Register
System Clock Status Register
Peripheral Clock Enable Register
Peripheral Clock Disable Register
0x0018 Peripheral Clock Status Register
0x000C - 0x0018 Reserved
0x001C
0x0020
UTMI Clock Register
Main Oscillator Register
0x0024
0x0028
0x002C
0x0030
Main Clock Frequency Register
PLLA Register
Reserved
Master Clock Register
0x0034
0x0038
0x003C
0x0040
Reserved
USB Clock Register
Soft Modem Clock Register
Programmable Clock 0 Register
0x0044 Programmable Clock 1 Register
0x0048 - 0x005C Reserved
0x0060
0x0064
Interrupt Enable Register
Interrupt Disable Register
0x0068
0x006C
Status Register
Interrupt Mask Register
0x0070 - 0x0078 Reserved
0x0080 PLL Charge Pump Current Register
0x0084-0x00E0
0x00E4
0x00E8
0x00EC-0x0108
0x010C
Reserved
Write Protect Mode Register
Write Protect Status Register
Reserved
Peripheral Control Register
–
PMC_USB
PMC_SMD
PMC_PCK0
PMC_PCK1
–
PMC_IER
PMC_IDR
PMC_SR
PMC_IMR
–
PMC_PLLICPR
–
PMC_WPMR
PMC_WPSR
–
PMC_PCR
Name
PMC_SCER
PMC_SCDR
PMC_SCSR
PMC _PCER
PMC_PCDR
PMC_PCSR
–
CKGR_UCKR
CKGR_MOR
CKGR_MCFR
CKGR_PLLAR
–
PMC_MCKR
–
Read-write
Read-write
Read-write
Read-write
–
Write-only
Write-only
Read-only
Read-only
–
Write-only
–
Read-write
Read-only
–
Read-write
Access
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
–
Read-write
Read-write
Read-only
Read-write
–
Read-write
–
0x0000_0001
–
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
–
N.A.
N.A.
0x0001_0008
0x0000_0000
–
0x0100_0100
–
0x0000_0000
0x0000_0000
–
0x0000_0000
Reset
N.A.
N.A.
0x0000_0005
N.A.
–
0x0000_0000
–
0x1020_0000
0x0000_0008
0x0000_0000
0x0000_3F00
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
185
22.13.1 PMC System Clock Enable Register
Name:
Address:
Access:
PMC_SCER
0xFFFFFC00
Write-only
31
–
30
–
29
–
23
–
15
–
7
UDP
22
–
14
–
6
UHP
21
–
13
–
5
–
28
–
20
–
12
–
4
SMDCK
• DDRCK: DDR Clock Enable
0 = No effect.
1 = Enables the DDR clock.
• LCDCK: LCD Clock Enable
0 = No effect.
1 = Enables the LCD clock.
• SMDCK: SMD Clock Enable
0 = No effect.
1 = Enables the soft modem clock.
• UHP: USB Host OHCI Clocks Enable
0 = No effect.
1 = Enables the UHP48M and UHP12M OHCI clocks.
• UDP: USB Device Clock Enable
0 = No effect.
1 = Enables the USB Device clock.
• PCKx: Programmable Clock x Output Enable
0 = No effect.
1 = Enables the corresponding Programmable Clock output.
27
–
19
–
11
–
3
LCDCK
26
–
18
–
10
–
2
DDRCK
25
–
17
–
9
PCK1
1
–
24
–
16
–
8
PCK0
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
186
22.13.2 PMC System Clock Disable Register
Name:
Address:
Access:
PMC_SCDR
0xFFFFFC04
Write-only
31
–
30
–
29
–
23
–
15
–
7
UDP
22
–
14
–
6
UHP
21
–
13
–
5
–
28
–
20
–
12
–
4
SMDCK
27
–
19
–
11
–
3
LCDCK
• PCK: Processor Clock Disable
0 = No effect.
1 = Disables the Processor clock. This is used to enter the processor in Idle Mode.
• DDRCK: DDR Clock Disable
0 = No effect.
1 = Disables the DDR clock.
26
–
18
–
10
–
2
DDRCK
• LCDCK: LCD Clock Enable
0 = No effect.
1 = Enables the LCD clock.
• SMDCK: SMD Clock Disable
0 = No effect.
1 = Disables the soft modem clock.
• UHP: USB Host OHCI Clock Disable
0 = No effect.
1 = Disables the UHP48M and UHP12M OHCI clocks.
• UDP: USB Device Clock Enable
0 = No effect.
1 = Disables the USB Device clock.
• PCKx: Programmable Clock x Output Disable
0 = No effect.
1 = Disables the corresponding Programmable Clock output.
25
–
17
–
9
PCK1
1
–
24
–
16
–
8
PCK0
0
PCK
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
187
22.13.3 PMC System Clock Status Register
Name:
Address:
Access:
PMC_SCSR
0xFFFFFC08
Read-only
31
–
30
–
29
–
23
–
15
–
7
UDP
22
–
14
–
6
UHP
21
–
13
–
5
–
28
–
20
–
12
–
4
SMDCK
• PCK: Processor Clock Status
0 = The Processor clock is disabled.
1 = The Processor clock is enabled.
• DDRCK: DDR Clock Status
0 = The DDR clock is disabled.
1 = The DDR clock is enabled.
• LCDCK: LCD Clock Enable
0 = No effect.
1 = Enables the LCD clock.
• SMDCK: SMD Clock Status
0 = The soft modem clock is disabled.
1 = The soft modem clock is enabled.
• UHP: USB Host Port Clock Status
0 = The UHP48M and UHP12M OHCI clocks are disabled.
1 = The UHP48M and UHP12M OHCI clocks are enabled.
• UDP: USB Device Port Clock Status
0 = The USB Device clock is disabled.
1 = The USB Device clock is enabled.
• PCKx: Programmable Clock x Output Status
0 = The corresponding Programmable Clock output is disabled.
1 = The corresponding Programmable Clock output is enabled.
27
–
19
–
11
–
3
LCDCK
26
–
18
–
10
–
2
DDRCK
25
–
17
–
9
PCK1
1
–
24
–
16
–
8
PCK0
0
PCK
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
188
22.13.4 PMC Peripheral Clock Enable Register
Name:
Address:
Access:
PMC_PCER
0xFFFFFC10
Write-only
31
PID31
30
PID30
29
PID29
28
PID28
23
PID23
15
PID15
7
PID7
22
PID22
14
PID14
6
PID6
21
PID21
13
PID13
5
PID5
20
PID20
12
PID12
4
PID4
27
PID27
19
PID19
11
PID11
3
PID3
26
PID26
18
PID18
10
PID10
2
PID2
25
PID25
17
PID17
9
PID9
1
-
24
PID24
16
PID16
8
PID8
0
-
• PIDx: Peripheral Clock x Enable
0 = No effect.
1 = Enables the corresponding peripheral clock.
Notes: 1. PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
2. Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
189
22.13.5 PMC Peripheral Clock Disable Register
Name:
Address:
Access:
PMC_PCDR
0xFFFFFC14
Write-only
31
PID31
30
PID30
29
PID29
28
PID28
23
PID23
15
PID15
7
PID7
22
PID22
14
PID14
6
PID6
21
PID21
13
PID13
5
PID5
20
PID20
12
PID12
4
PID4
27
PID27
19
PID19
11
PID11
3
PID3
26
PID26
18
PID18
10
PID10
2
PID2
25
PID25
17
PID17
9
PID9
1
-
• PIDx: Peripheral Clock x Disable
0 = No effect.
1 = Disables the corresponding peripheral clock.
Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
24
PID24
16
PID16
8
PID8
0
-
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
190
22.13.6 PMC Peripheral Clock Status Register
Name:
Address:
Access:
PMC_PCSR
0xFFFFFC18
Read-only
31
PID31
30
PID30
29
PID29
28
PID28
23
PID23
15
PID15
7
PID7
22
PID22
14
PID14
6
PID6
21
PID21
13
PID13
5
PID5
20
PID20
12
PID12
4
PID4
27
PID27
19
PID19
11
PID11
3
PID3
26
PID26
18
PID18
10
PID10
2
PID2
25
PID25
17
PID17
9
PID9
1
–
• PIDx: Peripheral Clock x Status
0 = The corresponding peripheral clock is disabled.
1 = The corresponding peripheral clock is enabled.
Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
24
PID24
16
PID16
8
PID8
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
191
22.13.7 PMC UTMI Clock Configuration Register
Name:
Address:
Access:
CKGR_UCKR
0xFFFFFC1C
Read-write
31 30
BIASCOUNT
29 28
23 20
15
–
7
–
22
UPLLCOUNT
21
14
–
6
–
13
–
5
–
12
–
4
–
27
–
19
–
11
–
3
–
• UPLLEN: UTMI PLL Enable
0 = The UTMI PLL is disabled.
1 = The UTMI PLL is enabled.
When UPLLEN is set, the LOCKU flag is set once the UTMI PLL startup time is achieved.
• UPLLCOUNT: UTMI PLL Start-up Time
Specifies the number of Slow Clock cycles multiplied by 8 for the UTMI PLL start-up time.
• BIASEN: UTMI BIAS Enable
0 = The UTMI BIAS is disabled.
1 = The UTMI BIAS is enabled.
• BIASCOUNT: UTMI BIAS Start-up Time
Specifies the number of Slow Clock cycles for the UTMI BIAS start-up time.
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
BIASEN
16
UPLLEN
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
192
22.13.8 PMC Clock Generator Main Oscillator Register
Name:
Address:
Access:
CKGR_MOR
0xFFFFFC20
Read-write
31
–
30
–
29
–
28
–
23
15
7
–
22
14
6
–
21
13
5
–
20
27
–
19
KEY
12
MOSCXTST
11
4
–
3
MOSCRCEN
26
–
18
10
2
–
25
CFDEN
17
9
24
MOSCSEL
16
1
MOSCXTBY
0
MOSCXTEN
• KEY: Password
Should be written at value 0x37. Writing any other value in this field aborts the write operation.
• MOSCXTEN: Main Crystal Oscillator Enable
A crystal must be connected between XIN and XOUT.
0 = The Main Crystal Oscillator is disabled.
1 = The Main Crystal Oscillator is enabled. MOSCXTBY must be set to 0.
When MOSCXTEN is set, the MOSCXTS flag is set once the Main Crystal Oscillator startup time is achieved.
• MOSCXTBY: Main Crystal Oscillator Bypass
0 = No effect.
1 = The Main Crystal Oscillator is bypassed. MOSCXTEN must be set to 0. An external clock must be connected on XIN.
When MOSCXTBY is set, the MOSCXTS flag in PMC_SR is automatically set.
Clearing MOSCXTEN and MOSCXTBY bits allows resetting the MOSCXTS flag.
• MOSCRCEN: Main On-Chip RC Oscillator Enable
0 = The Main On-Chip RC Oscillator is disabled.
1 = The Main On-Chip RC Oscillator is enabled.
When MOSCRCEN is set, the MOSCRCS flag is set once the Main On-Chip RC Oscillator startup time is achieved.
• MOSCXTST: Main Crystal Oscillator Start-up Time
Specifies the number of Slow Clock cycles multiplied by 8 for the Main Crystal Oscillator start-up time.
• MOSCSEL: Main Oscillator Selection
0 = The Main On-Chip RC Oscillator is selected.
1 = The Main Crystal Oscillator is selected.
• CFDEN: Clock Failure Detector Enable
0 = The Clock Failure Detector is disabled.
1 = The Clock Failure Detector is enabled.
8
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
193
22.13.9 PMC Clock Generator Main Clock Frequency Register
Name:
Address:
Access:
CKGR_MCFR
0xFFFFFC24
Read-only
31
–
30
–
29
–
28
–
27
–
23
–
15
22
–
14
21
–
13
20
–
12
19
–
11
MAINF
7 6 5 4 3
MAINF
• MAINF: Main Clock Frequency
Gives the number of Main Clock cycles within 16 Slow Clock periods.
• MAINFRDY: Main Clock Ready
0 = MAINF value is not valid or the Main Oscillator is disabled.
1 = The Main Oscillator has been enabled previously and MAINF value is available.
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
MAINFRDY
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
194
22.13.10 PMC Clock Generator PLLA Register
Name:
Address:
Access:
CKGR_PLLAR
0xFFFFFC28
Read-write
31
–
30
–
29
1
28
–
23 22 21 20
27
–
19
26
18
25
MULA
17
MULA
15
7
OUTA
14
6
13
5
12
4
11
PLLACOUNT
10
3 2
9
1
DIVA
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
• DIVA: Divider A
Value
0
1
2 - 255
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIVA.
24
16
8
0
• PLLACOUNT: PLLA Counter
Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• OUTA: PLLA Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Characteristics section of the product datasheet.
• MULA: PLLA Multiplier
0 = The PLLA is deactivated.
1 up to 254 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA+ 1.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
195
22.13.11 PMC Master Clock Register
Name:
Address:
Access:
PMC_MCKR
0xFFFFFC30
Read-write
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
21
–
13
–
5
PRES
• CSS: Master/Processor Clock Source Selection
Value
0
1
Name
SLOW_CLK
MAIN_CLK
2
3
PLLA_CLK
UPLL_CLK
28
–
20
–
12
PLLADIV2
4
27
–
19
–
11
–
3
–
Description
Slow Clock is selected
Main Clock is selected
PLLACK/PLLADIV2 is selected
UPLL Clock is selected
26
–
18
–
10
–
2
–
• PRES: Master/Processor Clock Prescaler
Value
0
Name
CLOCK
5
6
7
3
4
1
2
CLOCK_DIV2
CLOCK_DIV4
CLOCK_DIV8
CLOCK_DIV16
CLOCK_DIV32
CLOCK_DIV64
CLOCK_DIV3
• MDIV: Master Clock Division
Value Name
0 EQ_PCK
1
2
3
PCK_DIV2
PCK_DIV4
PCK_DIV3
Description
Selected clock
Selected clock divided by 2
Selected clock divided by 4
Selected clock divided by 8
Selected clock divided by 16
Selected clock divided by 32
Selected clock divided by 64
Selected clock divided by 3
1
Description
Master Clock is Prescaler Output Clock divided by 1.
Warning: DDRCK is not available.
Master Clock is Prescaler Output Clock divided by 2.
DDRCK is equal to MCK.
Master Clock is Prescaler Output Clock divided by 4.
DDRCK is equal to MCK.
Master Clock is Prescaler Output Clock divided by 3.
DDRCK is equal to MCK.
25
–
17
–
9
MDIV
CSS
• PLLADIV2: PLLA divisor by 2
Value
0
1
Name
NOT_DIV2
DIV2
Description
PLLA clock frequency is divided by 1.
PLLA clock frequency is divided by 2.
24
–
16
–
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
196
22.13.12 PMC USB Clock Register
Name:
Address:
Access:
PMC_USB
0xFFFFFC38
Read-write
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
• USBS: USB OHCI Input Clock Selection
0 = USB Clock Input is PLLA
1 = USB Clock Input is UPLL
• USBDIV: Divider for USB OHCI Clock.
USB Clock is Input clock divided by USBDIV+1
28
–
20
–
12
–
4
–
27
–
19
–
11
3
–
26
–
18
–
10
USBDIV
2
–
25
–
17
–
9
1
–
24
–
16
–
8
0
USBS
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
197
22.13.13 PMC SMD Clock Register
Name:
Address:
Access :
PMC_SMD
0xFFFFFC3C
Read-write
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
• SMDS: SMD input clock selection
0 = SMD Clock Input is PLLA
1 = SMD Clock Input is UPLL
• SMDDIV: Divider for SMD Clock.
SMD Clock is Input clock divided by SMD +1
28
–
20
–
12
4
–
27
–
19
–
11
3
–
26
–
18
–
10
SMDDIV
2
–
25
–
17
–
9
1
–
24
–
16
–
8
0
SMDS
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
198
22.13.14 PMC Programmable Clock Register
Name:
Address:
Access:
PMC_PCKx
0xFFFFFC40
Read-write
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
21
–
13
–
5
PRES
• CSS: Master Clock Source Selection
Value name
2
3
0
1
4
SLOW_CLK
MAIN_CLK
PLLA_CLK
UPLL_CLK
MCK_CLK
• PRES: Programmable Clock Prescaler
Value name
6
7
4
5
2
3
0
1
CLOCK
CLOCK_DIV2
CLOCK_DIV4
CLOCK_DIV8
CLOCK_DIV16
CLOCK_DIV32
CLOCK_DIV64
Reserved
28
–
20
–
12
–
4
27
–
19
–
11
–
3
–
Description
Slow Clock is selected
Main Clock is selected
PLLACK/PLLADIV2 is selected
UPLL Clock is selected
Master Clock is selected
Description
Selected clock
Selected clock divided by 2
Selected clock divided by 4
Selected clock divided by 8
Selected clock divided by 16
Selected clock divided by 32
Selected clock divided by 64
Reserved
26
–
18
–
10
–
2
25
–
17
–
9
–
1
CSS
24
–
16
–
8
–
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
199
22.13.15 PMC Interrupt Enable Register
Name:
Address:
Access:
PMC_IER
0xFFFFFC60
Write-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
LOCKU
21
–
13
–
5
–
28
–
20
–
12
–
4
–
• MOSCXTS: Main Crystal Oscillator Status Interrupt Enable
• LOCKA: PLLA Lock Interrupt Enable
• MCKRDY: Master Clock Ready Interrupt Enable
• LOCKU: UTMI PLL Lock Interrupt Enable
• PCKRDYx: Programmable Clock Ready x Interrupt Enable
• MOSCSELS: Main Oscillator Selection Status Interrupt Enable
• MOSCRCS: Main On-Chip RC Status Interrupt Enable
• CFDEV: Clock Failure Detector Event Interrupt Enable
27
–
19
–
11
–
3
MCKRDY
26
–
18
CFDEV
10
–
2
–
25
–
17
MOSCRCS
9
PCKRDY1
1
LOCKA
24
–
16
MOSCSELS
8
PCKRDY0
0
MOSCXTS
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
200
22.13.16 PMC Interrupt Disable Register
Name:
Address:
Access:
PMC_IDR
0xFFFFFC64
Write-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
LOCKU
21
–
13
–
5
–
28
–
20
–
12
–
4
–
• MOSCXTS: Main Crystal Oscillator Status Interrupt Disable
• LOCKA: PLLA Lock Interrupt Disable
• MCKRDY: Master Clock Ready Interrupt Disable
• LOCKU: UTMI PLL Lock Interrupt Enable
• PCKRDYx: Programmable Clock Ready x Interrupt Disable
• MOSCSELS: Main Oscillator Selection Status Interrupt Disable
• MOSCRCS: Main On-Chip RC Status Interrupt Disable
• CFDEV: Clock Failure Detector Event Interrupt Disable
27
–
19
–
11
–
3
MCKRDY
26
–
18
CFDEV
10
–
2
–
25
–
17
MOSCRCS
9
PCKRDY1
1
LOCKA
24
–
16
MOSCSELS
8
PCKRDY0
0
MOSCXTS
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
201
22.13.17 PMC Status Register
Name:
Address:
Access:
PMC_SR
0xFFFFFC68
Read-only
31
–
30
–
23
–
22
–
15
–
7
OSCSELS
14
–
6
LOCKU
13
–
5
–
29
–
21
–
• MOSCXTS: Main XTAL Oscillator Status
0 = Main XTAL oscillator is not stabilized.
1 = Main XTAL oscillator is stabilized.
• LOCKA: PLLA Lock Status
0 = PLLA is not locked
1 = PLLA is locked.
• MCKRDY: Master Clock Status
0 = Master Clock is not ready.
1 = Master Clock is ready.
• LOCKU: UPLL Clock Status
0 = UPLL Clock is not ready.
1 = UPLL Clock is ready.
• OSCSELS: Slow Clock Oscillator Selection
0 = Internal slow clock RC oscillator is selected.
1 = External slow clock 32 kHz oscillator is selected.
• PCKRDYx: Programmable Clock Ready Status
0 = Programmable Clock x is not ready.
1 = Programmable Clock x is ready.
• MOSCSELS: Main Oscillator Selection Status
0 = Selection is in progress.
1 = Selection is done.
• MOSCRCS: Main On-Chip RC Oscillator Status
0 = Main on-chip RC oscillator is not stabilized.
1 = Main on-chip RC oscillator is stabilized.
12
–
4
–
28
–
20
FOS
27
–
19
CFDS
11
–
3
MCKRDY
26
–
18
CFDEV
10
–
2
–
25
–
17
MOSCRCS
9
PCKRDY1
1
LOCKA
24
–
16
MOSCSELS
8
PCKRDY0
0
MOSCXTS
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
202
• CFDEV: Clock Failure Detector Event
0 = No clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR.
1 = At least one clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR.
• CFDS: Clock Failure Detector Status
0 = A clock failure of the main on-chip RC oscillator clock is not detected.
1 = A clock failure of the main on-chip RC oscillator clock is detected.
• FOS: Clock Failure Detector Fault Output Status
0 = The fault output of the clock failure detector is inactive.
1 = The fault output of the clock failure detector is active.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
203
22.13.18 PMC Interrupt Mask Register
Name:
Address:
Access:
PMC_IMR
0xFFFFFC6C
Read-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
• MOSCXTS: Main Crystal Oscillator Status Interrupt Mask
• LOCKA: PLLA Lock Interrupt Mask
• MCKRDY: Master Clock Ready Interrupt Mask
• PCKRDYx: Programmable Clock Ready x Interrupt Mask
• MOSCSELS: Main Oscillator Selection Status Interrupt Mask
• MOSCRCS: Main On-Chip RC Status Interrupt Mask
• CFDEV: Clock Failure Detector Event Interrupt Mask
27
–
19
–
11
–
3
MCKRDY
26
–
18
CFDEV
10
–
2
–
25
–
17
MOSCRCS
9
PCKRDY1
1
LOCKA
24
–
16
MOSCSELS
8
PCKRDY0
0
MOSCXTS
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22.13.19 PLL Charge Pump Current Register
Name:
Address:
Access:
PMC_PLLICPR
0xFFFFFC80
Write-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
ICPLLA
• ICPLLA: Charge Pump Current
To optimize clock performance, this field must be programmed as specified in “PLL A Characteristics” in the Electrical Characteristics section of the product datasheet.
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22.13.20 PMC Write Protect Mode Register
Name:
Address:
Access:
Reset:
PMC_WPMR
0xFFFFFCE4
Read-write
See
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
7
—
6
—
5
—
4
—
3
—
2
—
1
—
0
WPEN
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
Protects the registers:
•
“PMC System Clock Enable Register” on page 186
•
“PMC System Clock Disable Register” on page 187
•
“PMC Clock Generator Main Clock Frequency Register” on page 194
•
“PMC Clock Generator PLLA Register” on page 195
•
“PMC Master Clock Register” on page 196
•
“PMC USB Clock Register” on page 197
•
“PMC Programmable Clock Register” on page 199
•
“PLL Charge Pump Current Register” on page 205
• WPKEY: Write Protect KEY
Should be written at value 0x504D43 (“PMC” in ASCII). Writing any other value in this field aborts the write operation of the
WPEN bit. Always reads as 0.
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22.13.21 PMC Write Protect Status Register
Name:
Address:
Access:
Reset:
PMC_WPSR
0xFFFFFCE8
Read-only
See
31
—
30
—
29
—
23
15
22
14
21
13
28
—
27
—
20
WPVSRC
19
12
WPVSRC
11
4
—
3
—
26
—
18
10
25
—
17
9
24
—
16
8
7
—
6
—
5
—
2
—
1
—
0
WPVS
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the PMC_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the PMC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted.
Reading PMC_WPSR automatically clears all fields.
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22.13.22 PMC Peripheral Control Register
Name:
Address:
Access:
PMC_PCR
0xFFFFFD0C
Read-write
31
—
30
—
29
—
23
—
22
—
21
—
15
—
7
—
14
—
6
—
13
—
5
28
EN
20
—
12
CMD
4
11
—
3
27
—
19
—
10
—
2
26
—
18
—
9
—
1
25
—
17
DIV
8
—
0
24
—
16
PID
• PID: Peripheral ID
Only the following Peripheral IDs can have a DIV value other than 0: PID2, PID3, PID5 to PID11, PID13 to PID19, PID28 to
PID30.
PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
• CMD: Command
0: Read mode
1: Write mode
• DIV: Divisor Value
Value
0
1
2
3
Name
PERIPH_DIV_MCK
PERIPH_DIV2_MCK
PERIPH_DIV4_MCK
PERIPH_DIV8_MCK
Description
Peripheral clock is MCK
Peripheral clock is MCK/2
Peripheral clock is MCK/4
Peripheral clock is MCK/8
• EN: Enable
0: Selected Peripheral clock is disabled
1: Selected Peripheral clock is enabled
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23.
Parallel Input/Output (PIO) Controller
23.1 Description
The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product.
Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
Each I/O line of the PIO Controller features:
An input change interrupt enabling level change detection on any I/O line.
Additional Interrupt modes enabling rising edge, falling edge, low level or high level detection on any I/O line.
A glitch filter providing rejection of glitches lower than one-half of PIO clock cycle.
A debouncing filter providing rejection of unwanted pulses from key or push button operations.
Multi-drive capability similar to an open drain I/O line.
Control of the pull-up and pull-down of the I/O line.
Input visibility and output control.
The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.
23.2 Embedded Characteristics
Up to 32 Programmable I/O Lines
Fully Programmable through Set/Clear Registers
Multiplexing of Four Peripheral Functions per I/O Line
For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)
Input Change Interrupt
Programmable Glitch Filter
Programmable Debouncing Filter
Multi-drive Option Enables Driving in Open Drain
Programmable Pull Up on Each I/O Line
Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time
Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low Level or High Level
Lock of the Configuration by the Connected Peripheral
Synchronous Output, Provides Set and Clear of Several I/O lines in a Single Write
Write Protect Registers
Programmable Schmitt Trigger Inputs
Programmable I/O Delay
Programmable I/O Drive
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23.3 Block Diagram
Figure 23-1. Block Diagram
PIO Controller
Interr u pt Controller
PIO Interr u pt
PMC
PIO Clock
D a t a , En ab le
Em b edded
Peripher a l
D a t a , En ab le
Up to 3 2 peripher a l IO s
Up to 3 2 peripher a l IO s
Em b edded
Peripher a l
APB
Figure 23-2. Application Block Diagram
Keyboard Driver Control & Command
Driver
Keyboard Driver
PIO Controller
General Purpose I/Os
On-Chip Peripheral Drivers
On-Chip Peripherals
External Devices
PIN 0
PIN 1
Up to 3 2 pin s
PIN 3 1
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23.4 Product Dependencies
23.4.1 Pin Multiplexing
Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the
PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product.
23.4.2 External Interrupt Lines
The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs.
23.4.3 Power Management
The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled.
However, when the clock is disabled, not all of the features of the PIO Controller are available, including glitch filtering.
Note that the Input Change Interrupt, Interrupt Modes on a programmable event and the read of the pin level require the clock to be validated.
After a hardware reset, the PIO clock is disabled by default.
The user must configure the Power Management Controller before any access to the input line information.
23.4.4 Interrupt Generation
For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers. Using the PIO Controller requires the
Interrupt Controller to be programmed first.
The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.
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23.5 Functional Description
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in
Figure 23-3 . In this description each signal shown represents but one of up to 32 possible indexes.
Figure 23-3. I/O Line Control Logic
PIO_OER[0]
PIO_OSR[0]
PIO_ODR[0]
PIO_PUER[0]
PIO_PUSR[0]
PIO_PUDR[0]
1
Peripheral A Output Enable
Peripheral B Output Enable
Peripheral C Output Enable
Peripheral D Output Enable
PIO_ABCDSR1[0]
PIO_ABCDSR2[0]
Peripheral A Output
Peripheral B Output
Peripheral C Output
Peripheral D Output
00
01
10
11
00
01
10
11
PIO_PER[0]
PIO_PSR[0]
PIO_PDR[0]
0
0
PIO_SODR[0]
PIO_ODSR[0]
PIO_CODR[0]
1
0
PIO_MDER[0]
PIO_MDSR[0]
PIO_MDDR[0]
1
0
1
Pad
Peripheral A Input
Peripheral B Input
Peripheral C Input
Peripheral D Input
PIO Clock
Slow Clock
PIO_SCDR
Clock
Divider
PIO_IFSCER[0]
PIO_IFSCSR[0]
PIO_IFSCDR[0]
0
1
Programmable
Glitch or
Debouncing
Filter
PIO_IFER[0]
PIO_IFSR[0]
PIO_IFDR[0]
PIO_PDSR[0]
0
1
D
DFF
Q D
DFF
Q
Resynchronization
Stage
EVENT
DETECTOR
PIO_IER[0]
PIO_IMR[0]
PIO_IDR[0]
PIO_ISR[31]
PIO_IER[31]
PIO_IMR[31]
PIO_IDR[31]
PIO_ISR[0]
(Up to 32 possible inputs)
PIO Interrupt
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23.5.1 Pull-up and Pull-down Resistor Control
Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable
Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status
Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. The pull-down resistor can be enabled or disabled by writing respectively PIO_PPDER (Pull-down Enable Register) and
PIO_PPDDR (Pull-down Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in
PIO_PPDSR (Pull-down Status Register). Reading a 1 in PIO_PPDSR means the pull-up is disabled and reading a 0 means the pull-down is enabled.
Enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. In this case, the write of
PIO_PPDER for the concerned I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down resistor is still enabled is not possible. In this case, the write of PIO_PUER for the concerned I/O line is discarded.
Control of the pull-up resistor is possible regardless of the configuration of the I/O line.
After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0, and all the pull-downs are disabled, i.e. PIO_PPDSR resets at the value 0xFFFFFFFF.
23.5.2 I/O Line or Peripheral Function Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER
(PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO
Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the
PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers). A value of 1 indicates the pin is controlled by the PIO controller.
If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit.
After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.
23.5.3 Peripheral A or B or C or D Selection
The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is performed by writing PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers).
For each pin:
The corresponding bit at level 0 in PIO_ABCDSR1 and the corresponding bit at level 0 in PIO_ABCDSR2 means peripheral A is selected.
The corresponding bit at level 1 in PIO_ABCDSR1 and the corresponding bit at level 0 in PIO_ABCDSR2 means peripheral B is selected.
The corresponding bit at level 0 in PIO_ABCDSR1 and the corresponding bit at level 1 in PIO_ABCDSR2 means peripheral C is selected.
The corresponding bit at level 1 in PIO_ABCDSR1 and the corresponding bit at level 1 in PIO_ABCDSR2 means peripheral D is selected.
Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are always connected to the pin input.
Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the configuration of the pin.
However, assignment of a pin to a peripheral function requires a write in the peripheral selection registers
(PIO_ABCDSR1 and PIO_ABCDSR2) in addition to a write in PIO_PDR.
After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are 0, thus indicating that all the PIO lines are configured on peripheral
A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.
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23.5.4 Output Control
When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and
PIO_ABCDSR2 (ABCD Select Registers) determines whether the pin is driven or not.
When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing
PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller.
The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR
(Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status
Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller.
Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line.
23.5.5 Synchronous Data Output
Clearing one (or more) PIO line(s) and setting another one (or more) PIO line(s) synchronously cannot be done by using
PIO_SODR and PIO_CODR registers. It requires two successive write operations into two different registers. To overcome this, the PIO Controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output
Data Status Register).Only bits unmasked by PIO_OWSR (Output Write Status Register) are written. The mask bits in
PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR
(Output Write Disable Register).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.
23.5.6 Multi Drive Control (Open Drain)
Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line.
The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable
Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external drivers.
After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
23.5.7 Output Line Timings
shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing
PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set.
Figure 23-4 also shows when the
feedback in PIO_PDSR is available.
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Figure 23-4. Output Line Timings
MCK
Write PIO_SODR
Write PIO_ODSR at 1
Write PIO_CODR
Write PIO_ODSR at 0
PIO_ODSR
APB Access
2 cycles
PIO_PDSR
APB Access
2 cycles
23.5.8 Inputs
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
23.5.9 Input Glitch and Debouncing Filters
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 Master Clock (MCK) and the debouncing filter can filter a pulse of less than 1/2 Period of a Programmable Divided Slow Clock.
The selection between glitch filtering or debounce filtering is done by writing in the registers PIO_IFSCDR (PIO Input
Filter Slow Clock Disable Register) and PIO_IFSCER (PIO Input Filter Slow Clock Enable Register). Writing
PIO_IFSCDR and PIO_IFSCER respectively, sets and clears bits in PIO_IFSCSR.
The current selection status can be checked by reading the register PIO_IFSCSR (Input Filter Slow Clock Status
Register).
If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 Period of Master Clock.
If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 Period of the
Programmable Divided Slow Clock.
For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV field of the PIO_SCDR
(Slow Clock Divider Register)
Tdiv_slclk = ((DIV+1)*2).Tslow_clock
When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 Selected Clock Cycle
(Selected Clock represents MCK or Divided Slow Clock depending on PIO_IFSCDR and PIO_IFSCER programming) is automatically rejected, while a pulse with a duration of 1 Selected Clock (MCK or Divided Slow Clock) cycle or more is accepted. For pulse durations between 1/2 Selected Clock cycle and 1 Selected Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1
Selected Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Selected Clock cycle.
The filters also introduce some latencies, this is illustrated in Figure 23-5 and Figure 23-6
.
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The glitch filters are controlled by the register set: PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter
Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and debouncing filters require that the PIO Controller clock is enabled.
Figure 23-5. Input Glitch Filter Timing
PIO_IFCSR = 0
MCK up to 1.5 cycles
Pin Level
PIO_PDSR if PIO_IFSR = 0
PIO_PDSR if PIO_IFSR = 1
1 cycle 1 cycle 1 cycle
2 cycles up to 2.5 cycles
1 cycle
1 cycle up to 2 cycles
Figure 23-6. Input Debouncing Filter Timing
PIO_IFCSR = 1
Divided Slow Clock
Pin Level
PIO_PDSR if PIO_IFSR = 0 up to 2 cycles Tmck up to 2 cycles Tmck
PIO_PDSR if PIO_IFSR = 1
1 cycle Tdiv_slclk up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk up to 2 cycles Tmck up to 1.5 cycles Tdiv_slclk up to 2 cycles Tmck
23.5.10 Input Edge/Level Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The
Input Edge/Level Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable
Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function.
By default, the interrupt can be generated at any time an edge is detected on the input.
Some additional Interrupt modes can be enabled/disabled by writing in the PIO_AIMER (Additional Interrupt Modes
Enable Register) and PIO_AIMDR (Additional Interrupt Modes Disable Register). The current state of this selection can be read through the PIO_AIMMR (Additional Interrupt Modes Mask Register).
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These Additional Modes are:
Rising Edge Detection
Falling Edge Detection
Low Level Detection
High Level Detection
In order to select an Additional Interrupt Mode:
The type of event detection (Edge or Level) must be selected by writing in the set of registers; PIO_ESR (Edge
Select Register) and PIO_LSR (Level Select Register) which enable respectively, the Edge and Level Detection.
The current status of this selection is accessible through the PIO_ELSR (Edge/Level Status Register).
The Polarity of the event detection (Rising/Falling Edge or High/Low Level) must be selected by writing in the set of registers; PIO_FELLSR (Falling Edge /Low Level Select Register) and PIO_REHLSR (Rising Edge/High Level
Select Register) which allow to select Falling or Rising Edge (if Edge is selected in the PIO_ELSR), Edge or High or Low Level Detection (if Level is selected in the PIO_ELSR). The current status of this selection is accessible through the PIO_FRLHSR (Fall/Rise - Low/High Status Register).
When an input Edge or Level is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the interrupt controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “Level”, the interrupt is generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.
Figure 23-7. Event Detector on Input Lines (Figure represents line 0)
Event Detector
Resynchronized input on line 0
Rising Edge
Detector
1
Falling Edge
Detector
PIO_REHLSR[0]
PIO_FRLHSR[0]
PIO_FELLSR[0]
0
High Level
Detector
1
Low Level
Detector
0
0
1
1
0
Event detection on line 0
PIO_LSR[0]
PIO_ELSR[0]
PIO_ESR[0]
PIO_AIMER[0]
PIO_AIMMR[0]
PIO_AIMDR[0]
Edge
Detector
23.5.10.1Example
If generating an interrupt is required on the following:
Rising edge on PIO line 0
Falling edge on PIO line 1
Rising edge on PIO line 2
Low Level on PIO line 3
High Level on PIO line 4
High Level on PIO line 5
Falling edge on PIO line 6
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Rising edge on PIO line 7
Any edge on the other lines
The configuration required is described below.
23.5.10.2Interrupt Mode Configuration
All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER.
Then the Additional Interrupt Mode is enabled for line 0 to 7 by writing 32’h0000_00FF in PIO_AIMER.
23.5.10.3Edge or Level Detection Configuration
Lines 3, 4 and 5 are configured in Level detection by writing 32’h0000_0038 in PIO_LSR.
The other lines are configured in Edge detection by default, if they have not been previously configured. Otherwise, lines
0, 1, 2, 6 and 7 must be configured in Edge detection by writing 32’h0000_00C7 in PIO_ESR.
23.5.10.4Falling/Rising Edge or Low/High Level Detection Configuration.
Lines 0, 2, 4, 5 and 7 are configured in Rising Edge or High Level detection by writing 32’h0000_00B5 in PIO_REHLSR.
The other lines are configured in Falling Edge or Low Level detection by default, if they have not been previously configured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low Level detection by writing
32’h0000_004A in PIO_FELLSR.
Figure 23-8. Input Change Interrupt Timings if there are no Additional Interrupt Modes
MCK
Pin Level
PIO_ISR
Read PIO_ISR APB Access APB Access
23.5.11 I/O Lines Lock
When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller PWM), it can become locked by the action of this peripheral via an input of the PIO controller. When an I/O line is locked, the write of the corresponding bit in the registers PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER,
PIO_ABCDSR1 and PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime which
I/O line is locked by reading the PIO Lock Status register PIO_LOCKSR. Once an I/O line is locked, the only way to unlock it is to apply a hardware reset to the PIO Controller.
23.5.12 Programmable I/O Delays
The PIO interface consists of a series of signals driven by peripherals or directly by software. The simultaneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines.
In order to reduce the current peak in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, PIO_DELAY.
The additional programmable delays for each supporting range from 0 to 4 ns (Worst Case PVT). The delay can differ between I/Os supporting this feature. Delay can be modified per programming for each I/O. The minimal additional delay that can be programmed on a PAD supporting this feature is 1/16 of the maximum programmable delay.
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Only PADs PA[20:15], PA[13:11] and PA[4:2] can be configured.
When programming 0x0 in fields, no delay is added (reset value) and the propagation delay of the pad buffers is the inherent delay of the pad buffer. When programming 0xF in fields, the propagation delay of the corresponding pad is maximal.
Figure 23-9. Programmable I/O Delays
PIO
PAin[0]
PAout[0]
Programmable Delay Line
DELAY1
PAin[1]
PAout[1]
Programmable Delay Line
DELAY2
PAin[2]
PAout[2]
DELAYx
Programmable Delay Line
23.5.13 Programmable I/O Drive
It is possible to configure the I/O drive for pads PA[20:15], PA[13:11] and PA[4:2]. For any details, refer to the product electrical characteristics.
23.5.14 Programmable Schmitt Trigger
It is possible to configure each input for the Schmitt Trigger. By default the Schmitt trigger is active. Disabling the Schmitt
Trigger is requested when using the QTouch ™ Library.
23.5.15 Write Protection Registers
To prevent any single software error that may corrupt PIO behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “PIO Write Protect Mode Register” (PIO_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Protect Status Register
(PIO_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the PIO Write Protect Mode Register (PIO_WPMR) with the appropriate access key,
WPKEY.
The protected registers are:
“PIO Enable Register” on page 225
“PIO Disable Register” on page 225
“PIO Output Enable Register” on page 226
“PIO Output Disable Register” on page 227
“PIO Input Filter Enable Register” on page 228
“PIO Input Filter Disable Register” on page 228
“PIO Multi-driver Enable Register” on page 233
“PIO Multi-driver Disable Register” on page 234
“PIO Pull Up Disable Register” on page 235
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“PIO Pull Up Enable Register” on page 235
“PIO Peripheral ABCD Select Register 1” on page 237
“PIO Peripheral ABCD Select Register 2” on page 238
“PIO Output Write Enable Register” on page 243
“PIO Output Write Disable Register” on page 243
“PIO Pad Pull Down Disable Register” on page 241
“PIO Pad Pull Down Status Register” on page 242
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23.6 I/O Lines Programming Example
The programing example as shown in Table 23-1
below is used to obtain the following configuration.
4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor
Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor, no pulldown resistor
Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts
Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter
I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor
I/O lines 20 to 23 assigned to peripheral B functions with pull-down resistor
I/O line 24 to 27 assigned to peripheral C with Input Change Interrupt, no pull-up resistor and no pull-down resistor
I/O line 28 to 31 assigned to peripheral D, no pull-up resistor and no pull-down resistor
Table 23-1. Programming Example
Register
PIO_PER
PIO_PDR
PIO_OER
PIO_ODR
PIO_IFER
PIO_IFDR
PIO_SODR
PIO_CODR
PIO_IER
PIO_IDR
PIO_MDER
PIO_MDDR
PIO_PUDR
PIO_PUER
PIO_PPDDR
PIO_PPDER
PIO_ABCDSR1
PIO_ABCDSR2
PIO_OWER
PIO_OWDR
Value to be Written
0x0000_FFFF
0xFFFF_0000
0x0000_00FF
0xFFFF_FF00
0x0000_0F00
0xFFFF_F0FF
0x0000_0000
0x0FFF_FFFF
0x0F00_0F00
0xF0FF_F0FF
0x0000_000F
0xFFFF_FFF0
0xFFF0_00F0
0x000F_FF0F
0xFF0F_FFFF
0x00F0_0000
0xF0F0_0000
0xFF00_0000
0x0000_000F
0x0FFF_ FFF0
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23.7 Parallel Input/Output Controller (PIO) User Interface
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect.
Undefined bits read zero. If the I/O line is notmultiplexed with any peripheral, the I/O line is controlled by the PIO
Controller and PIO_PSR returns 1 systematically.
Table 23-2. Register Mapping
Offset Register
0x0000
0x0004
0x0008
0x000C
PIO Enable Register
PIO Disable Register
PIO Status Register
Reserved
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
Output Enable Register
Output Disable Register
Output Status Register
Reserved
Glitch Input Filter Enable Register
Glitch Input Filter Disable Register
Glitch Input Filter Status Register
Reserved
Set Output Data Register
Clear Output Data Register
Name
PIO_PER
PIO_PDR
PIO_PSR
PIO_OER
PIO_ODR
PIO_OSR
PIO_IFER
PIO_IFDR
PIO_IFSR
PIO_SODR
PIO_CODR
Access
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Reset
–
–
–
–
0x0000 0000
–
–
0x0000 0000
–
0x0038
0x003C
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
0x0060
0x0064
0x0068
0x006C
Output Data Status Register
Pin Data Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Multi-driver Enable Register
Multi-driver Disable Register
Multi-driver Status Register
Reserved
Pull-up Disable Register
Pull-up Enable Register
Pad Pull-up Status Register
Reserved
PIO_ODSR
PIO_PDSR
PIO_IER
PIO_IDR
PIO_IMR
PIO_ISR
PIO_MDER
PIO_MDDR
PIO_MDSR
PIO_PUDR
PIO_PUER
PIO_PUSR
Write-only
Write-only
Read-only
Read-write
Read-only
Write-only
Write-only
Read-only
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
–
–
–
0x00000000
0x00000000
–
–
0x00000000
–
–
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0x00A8
0x00AC
0x00B0
0x00B4
0x00B8
0x00BC
0x00C0
0x00C4
0x00C8
0x00CC
0x00D0
0x00D4
0x00D8
0x00DC
0x00E0
0x00E4
0x00E8
0x00EC to
0x00F8
0x0100
0x0104-
0x010C
0x0110
0x0114
Table 23-2. Register Mapping (Continued)
Offset
0x0070
Register
Peripheral Select Register 1
Peripheral Select Register 2 0x0074
0x0078 to
0x007C
0x0080
Reserved
Input Filter Slow Clock Disable Register
0x0084
0x0088
0x008C
0x0090
0x0094
0x0098
0x009C
0x00A0
0x00A4
Input Filter Slow Clock Enable Register
Input Filter Slow Clock Status Register
Slow Clock Divider Debouncing Register
Pad Pull-down Disable Register
Pad Pull-down Enable Register
Pad Pull-down Status Register
Reserved
Output Write Enable
Output Write Disable
Output Write Status Register
Reserved
Additional Interrupt Modes Enable Register
Additional Interrupt Modes Disables Register
Additional Interrupt Modes Mask Register
Reserved
Edge Select Register
Level Select Register
Edge/Level Status Register
Reserved
Falling Edge/Low Level Select Register
Rising Edge/ High Level Select Register
Fall/Rise - Low/High Status Register
Reserved
Lock Status
Write Protect Mode Register
Write Protect Status Register
Reserved
Schmitt Trigger Register
Reserved
IO Delay Register
I/O Drive Register 1
Name
PIO_ABCDSR1
PIO_ABCDSR2
Access
Read-write
Read-write
Reset
0x00000000
0x00000000
PIO_IFSCDR
PIO_IFSCER
PIO_IFSCSR
PIO_SCDR
PIO_PPDDR
PIO_PPDER
PIO_PPDSR
PIO_OWER
PIO_OWDR
PIO_OWSR
PIO_AIMER
PIO_AIMDR
PIO_AIMMR
PIO_ESR
PIO_LSR
PIO_ELSR
PIO_FELLSR
PIO_REHLSR
PIO_FRLHSR
PIO_LOCKSR
PIO_WPMR
PIO_WPSR
Write-only
Write-only
Read-only
Read-write
Write-only
Write-only
Read-only
–
–
0x00000000
0x00000000
–
–
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read-write
Read-only
0x00000000
0x0
0x0
–
–
0x00000000
–
–
0x00000000
–
–
0x00000000
–
–
0x00000000
PIO_SCHMITT Read-write 0x00000000
PIO_DELAYR
PIO_DRIVER1
Read-write
Read-write
0x00000000
0x00000000
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Table 23-2. Register Mapping (Continued)
Offset
0x0118
Register
I/O Drive Register 2
Name
PIO_DRIVER2
Access
Read-write
Reset
0x00000000
0x011C Reserved
0x0120 to
0x014C
Reserved
Notes: 1. Reset value depends on the product implementation.
Note:
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the
PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred.
If an offset is not listed in the table it must be considered as reserved.
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23.7.1 PIO Enable Register
Name:
Address:
Access:
PIO_PER
0xFFFFF400 (PIOA), 0xFFFFF600 (PIOB), 0xFFFFF800 (PIOC), 0xFFFFFA00 (PIOD)
Write-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: PIO Enable
0: No effect.
1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
23.7.2 PIO Disable Register
Name:
Address:
Access:
PIO_PDR
0xFFFFF404 (PIOA), 0xFFFFF604 (PIOB), 0xFFFFF804 (PIOC), 0xFFFFFA04 (PIOD)
Write-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: PIO Disable
0: No effect.
1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
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23.7.3 PIO Status Register
Name:
Address:
Access:
PIO_PSR
0xFFFFF408 (PIOA), 0xFFFFF608 (PIOB), 0xFFFFF808 (PIOC), 0xFFFFFA08 (PIOD)
Read-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: PIO Status
0: PIO is inactive on the corresponding I/O line (peripheral is active).
1: PIO is active on the corresponding I/O line (peripheral is inactive).
23.7.4 PIO Output Enable Register
Name:
Address:
Access:
PIO_OER
0xFFFFF410 (PIOA), 0xFFFFF610 (PIOB), 0xFFFFF810 (PIOC), 0xFFFFFA10 (PIOD)
Write-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Output Enable
0: No effect.
1: Enables the output on the I/O line.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
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23.7.5 PIO Output Disable Register
Name:
Address:
Access:
PIO_ODR
0xFFFFF414 (PIOA), 0xFFFFF614 (PIOB), 0xFFFFF814 (PIOC), 0xFFFFFA14 (PIOD)
Write-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Output Disable
0: No effect.
1: Disables the output on the I/O line.
23.7.6 PIO Output Status Register
Name:
Address:
Access:
PIO_OSR
0xFFFFF418 (PIOA), 0xFFFFF618 (PIOB), 0xFFFFF818 (PIOC), 0xFFFFFA18 (PIOD)
Read-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
• P0-P31: Output Status
0: The I/O line is a pure input.
1: The I/O line is enabled in output.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
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23.7.7 PIO Input Filter Enable Register
Name:
Address:
Access:
PIO_IFER
0xFFFFF420 (PIOA), 0xFFFFF620 (PIOB), 0xFFFFF820 (PIOC), 0xFFFFFA20 (PIOD)
Write-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Input Filter Enable
0: No effect.
1: Enables the input glitch filter on the I/O line.
23.7.8 PIO Input Filter Disable Register
Name:
Address:
Access:
PIO_IFDR
0xFFFFF424 (PIOA), 0xFFFFF624 (PIOB), 0xFFFFF824 (PIOC), 0xFFFFFA24 (PIOD)
Write-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Input Filter Disable
0: No effect.
1: Disables the input glitch filter on the I/O line.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
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23.7.9 PIO Input Filter Status Register
Name:
Address:
Access:
PIO_IFSR
0xFFFFF428 (PIOA), 0xFFFFF628 (PIOB), 0xFFFFF828 (PIOC), 0xFFFFFA28 (PIOD)
Read-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: Input Filer Status
0: The input glitch filter is disabled on the I/O line.
1: The input glitch filter is enabled on the I/O line.
23.7.10 PIO Set Output Data Register
Name:
Address:
Access:
PIO_SODR
0xFFFFF430 (PIOA), 0xFFFFF630 (PIOB), 0xFFFFF830 (PIOC), 0xFFFFFA30 (PIOD)
Write-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
• P0-P31: Set Output Data
0: No effect.
1: Sets the data to be driven on the I/O line.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
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23.7.11 PIO Clear Output Data Register
Name:
Address:
Access:
PIO_CODR
0xFFFFF434 (PIOA), 0xFFFFF634 (PIOB), 0xFFFFF834 (PIOC), 0xFFFFFA34 (PIOD)
Write-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: Clear Output Data
0: No effect.
1: Clears the data to be driven on the I/O line.
23.7.12 PIO Output Data Status Register
Name:
Address:
Access:
PIO_ODSR
0xFFFFF438 (PIOA), 0xFFFFF638 (PIOB), 0xFFFFF838 (PIOC), 0xFFFFFA38 (PIOD)
Read-only or Read-write
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
• P0-P31: Output Data Status
0: The data to be driven on the I/O line is 0.
1: The data to be driven on the I/O line is 1.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
230
23.7.13 PIO Pin Data Status Register
Name:
Address:
Access:
PIO_PDSR
0xFFFFF43C (PIOA), 0xFFFFF63C (PIOB), 0xFFFFF83C (PIOC), 0xFFFFFA3C (PIOD)
Read-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: Output Data Status
0: The I/O line is at level 0.
1: The I/O line is at level 1.
23.7.14 PIO Interrupt Enable Register
Name:
Address:
Access:
PIO_IER
0xFFFFF440 (PIOA), 0xFFFFF640 (PIOB), 0xFFFFF840 (PIOC), 0xFFFFFA40 (PIOD)
Write-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
• P0-P31: Input Change Interrupt Enable
0: No effect.
1: Enables the Input Change Interrupt on the I/O line.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
SAM9X35 [DATASHEET]
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23.7.15 PIO Interrupt Disable Register
Name:
Address:
Access:
PIO_IDR
0xFFFFF444 (PIOA), 0xFFFFF644 (PIOB), 0xFFFFF844 (PIOC), 0xFFFFFA44 (PIOD)
Write-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: Input Change Interrupt Disable
0: No effect.
1: Disables the Input Change Interrupt on the I/O line.
23.7.16 PIO Interrupt Mask Register
Name:
Address:
Access:
PIO_IMR
0xFFFFF448 (PIOA), 0xFFFFF648 (PIOB), 0xFFFFF848 (PIOC), 0xFFFFFA48 (PIOD)
Read-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
• P0-P31: Input Change Interrupt Mask
0: Input Change Interrupt is disabled on the I/O line.
1: Input Change Interrupt is enabled on the I/O line.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
232
23.7.17 PIO Interrupt Status Register
Name:
Address:
Access:
PIO_ISR
0xFFFFF44C (PIOA), 0xFFFFF64C (PIOB), 0xFFFFF84C (PIOC), 0xFFFFFA4C (PIOD)
Read-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: Input Change Interrupt Status
0: No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
1: At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
23.7.18 PIO Multi-driver Enable Register
Name:
Address:
Access:
PIO_MDER
0xFFFFF450 (PIOA), 0xFFFFF650 (PIOB), 0xFFFFF850 (PIOC), 0xFFFFFA50 (PIOD)
Write-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Multi Drive Enable.
0: No effect.
1: Enables Multi Drive on the I/O line.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
SAM9X35 [DATASHEET]
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23.7.19 PIO Multi-driver Disable Register
Name:
Address:
Access:
PIO_MDDR
0xFFFFF454 (PIOA), 0xFFFFF654 (PIOB), 0xFFFFF854 (PIOC), 0xFFFFFA54 (PIOD)
Write-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Multi Drive Disable.
0: No effect.
1: Disables Multi Drive on the I/O line.
23.7.20 PIO Multi-driver Status Register
Name:
Address:
Access:
PIO_MDSR
0xFFFFF458 (PIOA), 0xFFFFF658 (PIOB), 0xFFFFF858 (PIOC), 0xFFFFFA58 (PIOD)
Read-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
• P0-P31: Multi Drive Status.
0: The Multi Drive is disabled on the I/O line. The pin is driven at high and low level.
1: The Multi Drive is enabled on the I/O line. The pin is driven at low level only.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
SAM9X35 [DATASHEET]
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23.7.21 PIO Pull Up Disable Register
Name:
Address:
Access:
PIO_PUDR
0xFFFFF460 (PIOA), 0xFFFFF660 (PIOB), 0xFFFFF860 (PIOC), 0xFFFFFA60 (PIOD)
Write-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Pull Up Disable.
0: No effect.
1: Disables the pull up resistor on the I/O line.
23.7.22 PIO Pull Up Enable Register
Name:
Address:
Access:
PIO_PUER
0xFFFFF464 (PIOA), 0xFFFFF664 (PIOB), 0xFFFFF864 (PIOC), 0xFFFFFA64 (PIOD)
Write-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Pull Up Enable.
0: No effect.
1: Enables the pull up resistor on the I/O line.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
SAM9X35 [DATASHEET]
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23.7.23 PIO Pull Up Status Register
Name:
Address:
Access:
PIO_PUSR
0xFFFFF468 (PIOA), 0xFFFFF668 (PIOB), 0xFFFFF868 (PIOC), 0xFFFFFA68 (PIOD)
Read-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: Pull Up Status.
0: Pull Up resistor is enabled on the I/O line.
1: Pull Up resistor is disabled on the I/O line.
24
P24
16
P16
8
P8
0
P0
SAM9X35 [DATASHEET]
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23.7.24 PIO Peripheral ABCD Select Register 1
Name:
Access:
PIO_ABCDSR1
Read-write
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
28
P28
20
P20
12
P12
4
P4
27
P27
19
P19
11
P11
3
P3
26
P26
18
P18
10
P10
2
P2
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Peripheral Select.
If the same bit is set to 0 in PIO_ABCDSR2:
0: Assigns the I/O line to the Peripheral A function.
1: Assigns the I/O line to the Peripheral B function.
If the same bit is set to 1 in PIO_ABCDSR2:
0: Assigns the I/O line to the Peripheral C function.
1: Assigns the I/O line to the Peripheral D function.
9
P9
1
P1
25
P25
17
P17
8
P8
0
P0
24
P24
16
P16
SAM9X35 [DATASHEET]
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23.7.25 PIO Peripheral ABCD Select Register 2
Name:
Access:
PIO_ABCDSR2
Read-write
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
28
P28
20
P20
12
P12
4
P4
27
P27
19
P19
11
P11
3
P3
26
P26
18
P18
10
P10
2
P2
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Peripheral Select.
If the same bit is set to 0 in PIO_ABCDSR1:
0: Assigns the I/O line to the Peripheral A function.
1: Assigns the I/O line to the Peripheral C function.
If the same bit is set to 1 in PIO_ABCDSR1:
0: Assigns the I/O line to the Peripheral B function.
1: Assigns the I/O line to the Peripheral D function.
9
P9
1
P1
25
P25
17
P17
8
P8
0
P0
24
P24
16
P16
SAM9X35 [DATASHEET]
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23.7.26 PIO Input Filter Slow Clock Disable Register
Name:
Address:
Access:
PIO_IFSCDR
0xFFFFF480 (PIOA), 0xFFFFF680 (PIOB), 0xFFFFF880 (PIOC), 0xFFFFFA80 (PIOD)
Write-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: PIO Clock Glitch Filtering Select.
0: No Effect.
1: The Glitch Filter is able to filter glitches with a duration < Tmck/2.
23.7.27 PIO Input Filter Slow Clock Enable Register
Name:
Address:
Access:
PIO_IFSCER
0xFFFFF484 (PIOA), 0xFFFFF684 (PIOB), 0xFFFFF884 (PIOC), 0xFFFFFA84 (PIOD)
Write-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
• P0-P31: Debouncing Filtering Select.
0: No Effect.
1: The Debouncing Filter is able to filter pulses with a duration < Tdiv_slclk/2.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
SAM9X35 [DATASHEET]
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23.7.28 PIO Input Filter Slow Clock Status Register
Name:
Address:
Access:
PIO_IFSCSR
0xFFFFF488 (PIOA), 0xFFFFF688 (PIOB), 0xFFFFF888 (PIOC), 0xFFFFFA88 (PIOD)
Read-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: Glitch or Debouncing Filter Selection Status
0: The Glitch Filter is able to filter glitches with a duration < Tmck2.
1: The Debouncing Filter is able to filter pulses with a duration < Tdiv_slclk/2.
23.7.29 PIO Slow Clock Divider Debouncing Register
Name:
Address:
Access:
PIO_SCDR
0xFFFFF48C (PIOA), 0xFFFFF68C (PIOB), 0xFFFFF88C (PIOC), 0xFFFFFA8C (PIOD)
Read-write
31
–
23
–
30
–
22
–
29
–
21
–
28
–
20
–
27
–
19
–
26
–
18
–
25
–
17
–
15
–
7
14
–
6
13
5
12
4
11
3
DIV
10
2
9
1
DIV
• DIVx: Slow Clock Divider Selection for Debouncing
Tdiv_slclk = 2*(DIV+1)*Tslow_clock.
24
P24
16
P16
8
P8
0
P0
24
–
16
–
8
0
SAM9X35 [DATASHEET]
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23.7.30 PIO Pad Pull Down Disable Register
Name:
Address:
Access:
PIO_PPDDR
0xFFFFF490 (PIOA), 0xFFFFF690 (PIOB), 0xFFFFF890 (PIOC), 0xFFFFFA90 (PIOD)
Write-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Pull Down Disable.
0: No effect.
1: Disables the pull down resistor on the I/O line.
23.7.31 PIO Pad Pull Down Enable Register
Name:
Address:
Access:
PIO_PPDER
0xFFFFF494 (PIOA), 0xFFFFF694 (PIOB), 0xFFFFF894 (PIOC), 0xFFFFFA94 (PIOD)
Write-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Pull Down Enable.
0: No effect.
1: Enables the pull down resistor on the I/O line.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
SAM9X35 [DATASHEET]
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23.7.32 PIO Pad Pull Down Status Register
Name:
Address:
Access:
PIO_PPDSR
0xFFFFF498 (PIOA), 0xFFFFF698 (PIOB), 0xFFFFF898 (PIOC), 0xFFFFFA98 (PIOD)
Read-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Pull Down Status.
0: Pull Down resistor is enabled on the I/O line.
1: Pull Down resistor is disabled on the I/O line.
24
P24
16
P16
8
P8
0
P0
SAM9X35 [DATASHEET]
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23.7.33 PIO Output Write Enable Register
Name:
Address:
Access:
PIO_OWER
0xFFFFF4A0 (PIOA), 0xFFFFF6A0 (PIOB), 0xFFFFF8A0 (PIOC), 0xFFFFFAA0 (PIOD)
Write-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Output Write Enable.
0: No effect.
1: Enables writing PIO_ODSR for the I/O line.
23.7.34 PIO Output Write Disable Register
Name:
Address:
Access:
PIO_OWDR
0xFFFFF4A4 (PIOA), 0xFFFFF6A4 (PIOB), 0xFFFFF8A4 (PIOC), 0xFFFFFAA4 (PIOD)
Write-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register”
.
• P0-P31: Output Write Disable.
0: No effect.
1: Disables writing PIO_ODSR for the I/O line.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
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23.7.35 PIO Output Write Status Register
Name:
Address:
Access:
PIO_OWSR
0xFFFFF4A8 (PIOA), 0xFFFFF6A8 (PIOB), 0xFFFFF8A8 (PIOC), 0xFFFFFAA8 (PIOD)
Read-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: Output Write Status.
0: Writing PIO_ODSR does not affect the I/O line.
1: Writing PIO_ODSR affects the I/O line.
23.7.36 PIO Additional Interrupt Modes Enable Register
Name:
Address:
Access:
PIO_AIMER
0xFFFFF4B0 (PIOA), 0xFFFFF6B0 (PIOB), 0xFFFFF8B0 (PIOC), 0xFFFFFAB0 (PIOD)
Write-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
• P0-P31: Additional Interrupt Modes Enable.
0: No effect.
1: The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
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23.7.37 PIO Additional Interrupt Modes Disable Register
Name:
Address:
Access:
PIO_AIMDR
0xFFFFF4B4 (PIOA), 0xFFFFF6B4 (PIOB), 0xFFFFF8B4 (PIOC), 0xFFFFFAB4 (PIOD)
Write-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: Additional Interrupt Modes Disable.
0: No effect.
1: The interrupt mode is set to the default interrupt mode (Both Edge detection).
23.7.38 PIO Additional Interrupt Modes Mask Register
Name:
Address:
Access:
PIO_AIMMR
0xFFFFF4B8 (PIOA), 0xFFFFF6B8 (PIOB), 0xFFFFF8B8 (PIOC), 0xFFFFFAB8 (PIOD)
Read-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
• P0-P31: Peripheral CD Status.
0: The interrupt source is a Both Edge detection event
1: The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
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23.7.39 PIO Edge Select Register
Name:
Address:
Access:
PIO_ESR
0xFFFFF4C0 (PIOA), 0xFFFFF6C0 (PIOB), 0xFFFFF8C0 (PIOC), 0xFFFFFAC0 (PIOD)
Write-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: Edge Interrupt Selection.
0: No effect.
1: The interrupt source is an Edge detection event.
23.7.40 PIO Level Select Register
Name:
Address:
Access:
PIO_LSR
0xFFFFF4C4 (PIOA), 0xFFFFF6C4 (PIOB), 0xFFFFF8C4 (PIOC), 0xFFFFFAC4 (PIOD)
Write-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
• P0-P31: Level Interrupt Selection.
0: No effect.
1: The interrupt source is a Level detection event.
24
P24
16
P16
8
P8
0
P0
8
P8
0
P0
24
P24
16
P16
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23.7.41 PIO Edge/Level Status Register
Name:
Address:
Access:
PIO_ELSR
0xFFFFF4C8 (PIOA), 0xFFFFF6C8 (PIOB), 0xFFFFF8C8 (PIOC), 0xFFFFFAC8 (PIOD)
Read-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: Edge/Level Interrupt source selection.
0: The interrupt source is an Edge detection event.
1: The interrupt source is a Level detection event.
23.7.42 PIO Falling Edge/Low Level Select Register
Name:
Address:
Access:
PIO_FELLSR
0xFFFFF4D0 (PIOA), 0xFFFFF6D0 (PIOB), 0xFFFFF8D0 (PIOC), 0xFFFFFAD0 (PIOD)
Write-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
• P0-P31: Falling Edge/Low Level Interrupt Selection.
0: No effect.
1: The interrupt source is set to a Falling Edge detection or Low Level detection event, depending on PIO_ELSR.
8
P8
0
P0
24
P24
16
P16
24
P24
16
P16
8
P8
0
P0
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23.7.43 PIO Rising Edge/High Level Select Register
Name:
Address:
Access:
PIO_REHLSR
0xFFFFF4D4 (PIOA), 0xFFFFF6D4 (PIOB), 0xFFFFF8D4 (PIOC), 0xFFFFFAD4 (PIOD)
Write-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: Rising Edge /High Level Interrupt Selection.
0: No effect.
1: The interrupt source is set to a Rising Edge detection or High Level detection event, depending on PIO_ELSR.
24
P24
16
P16
8
P8
0
P0
23.7.44 PIO Fall/Rise - Low/High Status Register
Name:
Address:
Access:
PIO_FRLHSR
0xFFFFF4D8 (PIOA), 0xFFFFF6D8 (PIOB), 0xFFFFF8D8 (PIOC), 0xFFFFFAD8 (PIOD)
Read-only
31
P31
23
P23
30
P30
22
P22
29
P29
21
P21
28
P28
20
P20
27
P27
19
P19
26
P26
18
P18
25
P25
17
P17
15
P15
7
P7
14
P14
6
P6
13
P13
5
P5
12
P12
4
P4
11
P11
3
P3
10
P10
2
P2
9
P9
1
P1
• P0-P31: Edge /Level Interrupt Source Selection.
0: The interrupt source is a Falling Edge detection (if PIO_ELSR = 0) or Low Level detection event (if PIO_ELSR = 1).
1: The interrupt source is a Rising Edge detection (if PIO_ELSR = 0) or High Level detection event (if PIO_ELSR = 1).
8
P8
0
P0
24
P24
16
P16
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23.7.45 PIO Lock Status Register
Name:
Address:
Access:
PIO_LOCKSR
0xFFFFF4E0 (PIOA), 0xFFFFF6E0 (PIOB), 0xFFFFF8E0 (PIOC), 0xFFFFFAE0 (PIOD)
Read-only
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
23
P23
15
P15
7
P7
22
P22
14
P14
6
P6
21
P21
13
P13
5
P5
20
P20
12
P12
4
P4
19
P19
11
P11
3
P3
18
P18
10
P10
2
P2
17
P17
9
P9
1
P1
• P0-P31: Lock Status.
0: The I/O line is not locked.
1: The I/O line is locked.
24
P24
16
P16
8
P8
0
P0
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23.7.46 PIO Write Protect Mode Register
Name:
Address:
Access:
Reset:
PIO_WPMR
0xFFFFF4E4 (PIOA), 0xFFFFF6E4 (PIOB), 0xFFFFF8E4 (PIOC), 0xFFFFFAE4 (PIOD)
Read-write
See
31 30 29 28 27 26 25
WPKEY
23 22 21 20 19 18 17
WPKEY
24
16
15 14 13 12 11 10 9 8
WPKEY
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
WPEN
• WPEN: Write Protect Enable
0: Disables the Write Protect if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
1: Enables the Write Protect if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
Protects the registers:
“PIO Enable Register” on page 225
“PIO Disable Register” on page 225
“PIO Output Enable Register” on page 226
“PIO Output Disable Register” on page 227
“PIO Input Filter Enable Register” on page 228
“PIO Input Filter Disable Register” on page 228
“PIO Multi-driver Enable Register” on page 233
“PIO Multi-driver Disable Register” on page 234
“PIO Pull Up Disable Register” on page 235
“PIO Pull Up Enable Register” on page 235
“PIO Peripheral ABCD Select Register 1” on page 237
“PIO Peripheral ABCD Select Register 2” on page 238
“PIO Output Write Enable Register” on page 243
“PIO Output Write Disable Register” on page 243
“PIO Pad Pull Down Disable Register” on page 241
“PIO Pad Pull Down Status Register” on page 242
• WPKEY: Write Protect KEY
Should be written at value 0x50494F (“PIO” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
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23.7.47 PIO Write Protect Status Register
Name:
Address:
Access:
Reset:
PIO_WPSR
0xFFFFF4E8 (PIOA), 0xFFFFF6E8 (PIOB), 0xFFFFF8E8 (PIOC), 0xFFFFFAE8 (PIOD)
Read-only
See
31
–
30
–
29
–
28
–
27
–
26
–
25
–
23 22 21 20
WPVSRC
19 18 17
15 14 13 12
WPVSRC
11 10 9
24
–
16
8
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
WPVS
• WPVS: Write Protect Violation Status
0: No Write Protect Violation has occurred since the last read of the PIO_WPSR register.
1: A Write Protect Violation has occurred since the last read of the PIO_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted.
Note: Reading PIO_WPSR automatically clears all fields.
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23.7.48 PIO Schmitt Trigger Register
Name:
Address:
Access:
Reset:
PIO_SCHMITT
0xFFFFF500 (PIOA), 0xFFFFF700 (PIOB), 0xFFFFF900 (PIOC), 0xFFFFFB00 (PIOD)
Read-write
See
31
SCHMITT31
30
SCHMITT30
29
SCHMITT29
28
SCHMITT28
27
SCHMITT27
26
SCHMITT26
25
SCHMITT25
23
SCHMITT23
22
SCHMITT22
21
SCHMITT21
20
SCHMITT20
19
SCHMITT19
18
SCHMITT18
17
SCHMITT17
15
SCHMITT15
7
SCHMITT7
14
SCHMITT14
6
SCHMITT6
13
SCHMITT13
5
SCHMITT5
12
SCHMITT12
4
SCHMITT4
11
SCHMITT11
3
SCHMITT3
10
SCHMITT10
2
SCHMITT2
9
SCHMITT9
1
SCHMITT1
• SCHMITTx [x=0..31]:
0: Schmitt Trigger is enabled.
1: Schmitt Trigger is disabled.
24
SCHMITT24
16
SCHMITT16
8
SCHMITT8
0
SCHMITT0
23.7.49 PIO I/O Delay Register
Name:
Address:
Access:
Reset:
31
PIO_DELAYR
0xFFFFF510 (PIOA), 0xFFFFF710 (PIOB), 0xFFFFF910 (PIOC), 0xFFFFFB10 (PIOD)
Read-write
See
30 29 28 27 26
Delay7 Delay6
25
23 22 21 20 19 18 17
Delay5 Delay4
15 14 13 12 11 10 9
Delay3 Delay2
7 6 5 4 3 2 1
Delay1 Delay0
• Delay x:
Gives the number of elements in the delay line associated to pad x.
8
0
24
16
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23.7.50 PIO I/O Drive Register 1
Name:
Address:
Access:
Reset:
PIO_DRIVER1
0xFFFFF514 (PIOA), 0xFFFFF714 (PIOB), 0xFFFFF914 (PIOC), 0xFFFFFB14 (PIOD)
Read-write
0x0
31 30 29 28 27 26
LINE15 LINE14 LINE13
25
23 22 21 20 19 18 17
LINE11 LINE10 LINE9
15 14 13 12 11 10 9
LINE12
LINE8
LINE7 LINE6 LINE5 LINE4
7 6 5 4 3 2 1
24
16
8
0
LINE3 LINE2 LINE1 LINE0
• LINEx [x=0..15]: Drive of PIO Line x
1
2
Value
0
3
Name
HI_DRIVE
ME_DRIVE
LO_DRIVE
Description
High drive
Medium drive
Low drive
Reserved
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23.7.51 PIO I/O Drive Register 2
Name:
Address:
Access:
Reset:
PIO_DRIVER2
0xFFFFF518 (PIOA), 0xFFFFF718 (PIOB), 0xFFFFF918 (PIOC), 0xFFFFFB18 (PIOD)
Read-write
0x0
31 30 29 28 27 26
LINE31 LINE30 LINE29
25
23 22 21 20 19 18 17
LINE27 LINE26 LINE25
15 14 13 12 11 10 9
LINE28
LINE24
LINE23 LINE22 LINE21 LINE20
7 6 5 4 3 2 1
24
16
8
0
LINE19 LINE18 LINE17 LINE16
• LINEx [x=16..31]: Drive of PIO line x
1
2
Value
0
3
Name
HI_DRIVE
ME_DRIVE
LO_DRIVE
Description
High drive
Medium drive
Low drive
Reserved
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24.
Debug Unit (DBGU)
24.1 Description
The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARMbased systems.
The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be used stand-alone for general purpose serial communication. Moreover, the association with DMA controller channels permits packet handling for these tasks with processor time reduced to a minimum.
The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the
ARM processor visible to the software. These signals indicate the status of the DCC read and write registers and generate an interrupt to the ARM processor, making possible the handling of the DCC under interrupt control.
Chip Identifier registers permit recognition of the device and its revision. These registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals.
Finally, the Debug Unit features a Force NTRST capability that enables the software to decide whether to prevent access to the system via the In-circuit Emulator. This permits protection of the code, stored in ROM.
24.2 Embedded Characteristics
Composed of two functions
Two-pin UART
Debug Communication Channel (DCC) support
Two-pin UART
Implemented features are 100% compatible with the standard Atmel USART
Independent receiver and transmitter with a common programmable Baud Rate Generator
Even, Odd, Mark or Space Parity Generation
Parity, Framing and Overrun Error Detection
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Support for two DMA channels with connection to receiver and transmitter
Debug Communication Channel Support
Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor’s ICE
Interface
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24.3 Block Diagram
Figure 24-1. Debug Unit Functional Block Diagram
Peripher a l
Bridge
APB
DMA Controller
De
bu
g Unit
Power
M a n a gement
Controller
MCK B au d R a te
Gener a tor
Tr a n s mit
Receive
ARM
Proce ss or nTR S T
COMMRX
COMMTX
DCC
H a ndler
ICE
Acce ss
H a ndler
Power-on
Re s et force_ntr s t
Chip ID
Interr u pt
Control
Table 24-1. Debug Unit Pin Description
Pin Name
DRXD
DTXD
Description
Debug Receive Data
Debug Transmit Data
Figure 24-2. Debug Unit Application Example
Boot Program
Type
Input
Output
Debug Monitor Trace Manager
Debug Unit
Programming Tool
RS232 Drivers
Debug Console Trace Console
P a r a llel
Inp u t/
O u tp u t d b g u _ir q
DTXD
DRXD
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24.4 Product Dependencies
24.4.1 I/O Lines
Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit.
Table 24-2. I/O Lines
Instance
DBGU
DBGU
Signal
DRXD
DTXD
I/O Line
PA9
PA10
Peripheral
A
A
24.4.2 Power Management
Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller.
In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1.
24.4.3 Interrupt Source
Depending on product integration, the Debug Unit interrupt line is connected to one of the interrupt sources of the
Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug Unit.
Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with the real-
. This sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered.
24.5 UART Operations
The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit character handling (with parity).
It has no clock pin.
The Debug Unit's UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible with those of a standard USART.
24.5.1 Baud Rate Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in DBGU_BRGR (Baud Rate
Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud rate is Master Clock divided by (16 x 65536).
Baud Rate =
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Figure 24-3. Baud Rate Generator
CD
CD
MCK 16-bit Counter
OUT
0
>1
1
0
Divide by 16
Baud Rate
Clock
Receiver
Sampling Clock
24.5.2 Receiver
24.5.2.1 Receiver Reset, Enable and Disable
After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation.
The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost.
24.5.2.2 Start Detection and Data Sampling
The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is
7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 24-4. Start Bit Detection
Sampling Clock
DRXD
True Start
Detection
D0
Baud Rate
Clock
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Figure 24-5. Character Reception
Example: 8-bit, parity enabled 1 stop
0.5 bit period
1 bit period
DRXD
Sampling D0 D1
True Start Detection
D2 D3 D4 D5 D6 D7
Parity Bit
Stop Bit
24.5.2.3 Receiver Ready
When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR
(Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read.
Figure 24-6. Receiver Ready
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P S D0 D1 D2 D3 D4 D5 D6 D7 P
RXRDY
Read DBGU_RHR
24.5.2.4 Receiver Overrun
If DBGU_RHR has not been read by the software (or the Peripheral Data Controller or DMA Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1.
Figure 24-7. Receiver Overrun
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY
OVRE
RSTSTA
24.5.2.5 Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field
PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in
DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1.
Figure 24-8. Parity Error
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY
PARE
Wrong Parity Bit
RSTSTA
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24.5.2.6 Receiver Framing Error
When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the
RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1.
Figure 24-9. Receiver Framing Error
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY
FRAME
Stop Bit
Detected at 0
RSTSTA
24.5.3 Transmitter
24.5.3.1 Transmitter Reset, Enable and Disable
After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission.
The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped.
The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters.
24.5.3.2 Transmit Format
The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit.
Figure 24-10.Character Transmission
Example: Parity enabled
Baud Rate
Clock
DTXD
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7 Parity
Bit
Stop
Bit
24.5.3.3 Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty.
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When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed.
Figure 24-11.Transmitter Control
DBGU_THR
Data 0 Data 1
Shift Register
Data 0 Data 1
DTXD
S Data 0 P stop S Data 1 P stop
TXRDY
TXEMPTY
Write Data 0 in DBGU_THR
Write Data 1 in DBGU_THR
24.5.4 DMA Support
Both the receiver and the transmitter of the Debug Unit’s UART are connected to a DMA Controller (DMAC) channel.
The DMA Controller channels are programmed via registers that are mapped within the DMAC user interface.
24.5.5 Test Modes
The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE
(Channel Mode) in the mode register DBGU_MR.
The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the
DTXD line. The transmitter operates normally, but has no effect on the DTXD line.
The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the
DTXD line is held high, as in idle state.
The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission.
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Figure 24-12.Test Modes
Automatic Echo
Receiver RXD
Transmitter
Disabled
TXD
Local Loopback
Receiver
Transmitter
Remote Loopback
Receiver
V
DD
Disabled
Disabled
RXD
Disabled
V
DD
TXD
RXD
Transmitter
Disabled
TXD
24.5.6 Debug Communication Channel Support
The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the
ARM Processor and are driven by the In-circuit Emulator.
The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side.
As a reminder, the following instructions are used to read and write the Debug Communication Channel:
MRC p14, 0, Rd, c1, c0, 0
Returns the debug communication data read register into Rd
MCR p14, 0, Rd, c1, c0, 0
Writes the value in Rd to the debug communication data write register.
The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger.
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24.5.7 Chip Identifier
The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID).
Both registers contain a hard-wired value that is read-only. The first register contains the following fields:
EXT - shows the use of the extension identifier register
NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size
ARCH - identifies the set of embedded peripherals
SRAMSIZ - indicates the size of the embedded SRAM
EPROC - indicates the embedded ARM processor
VERSION - gives the revision of the silicon
The second register is device-dependent and reads 0 if the bit EXT is 0.
24.5.8 ICE Access Prevention
The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface.
Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller.
On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access.
This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible.
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24.6 Debug Unit (DBGU) User Interface
Table 24-3. Register Mapping
Offset Register
0x0000
0x0004
Control Register
Mode Register
0x0008
0x000C
0x0010
0x0014
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Status Register
0x0018
0x001C
Receive Holding Register
Transmit Holding Register
0x0020 Baud Rate Generator Register
0x0024 - 0x003C Reserved
0x0040
0x0044
Chip ID Register
Chip ID Extension Register
0x0048 Force NTRST Register
0x004C - 0x00FC Reserved
Name
DBGU_CR
DBGU_MR
DBGU_IER
DBGU_IDR
DBGU_IMR
DBGU_SR
DBGU_RHR
DBGU_THR
DBGU_BRGR
–
DBGU_CIDR
DBGU_EXID
DBGU_FNR
–
Access Reset
Write-only
Read-write
–
0x0
Write-only
Write-only
Read-only
Read-only
–
–
0x0
–
Read-only
Write-only
Read-write
–
Read-only
Read-only
Read-write
–
–
–
0x0
–
0x0
–
0x0
–
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24.6.1 Debug Unit Control Register
Name:
Address:
Access:
DBGU_CR
0xFFFFF200
Write-only
31
–
30
–
29
–
23
–
15
–
7
TXDIS
22
–
14
–
6
TXEN
21
–
13
–
5
RXDIS
28
–
20
–
12
–
4
RXEN
27
–
19
–
11
–
3
RSTTX
26
–
18
–
10
–
2
RSTRX
• RSTRX: Reset Receiver
0 = No effect.
1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
• RSTTX: Reset Transmitter
0 = No effect.
1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.
25
–
17
–
9
–
1
–
24
–
16
–
8
RSTSTA
0
–
• RXEN: Receiver Enable
0 = No effect.
1 = The receiver is enabled if RXDIS is 0.
• RXDIS: Receiver Disable
0 = No effect.
1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped.
• TXEN: Transmitter Enable
0 = No effect.
1 = The transmitter is enabled if TXDIS is 0.
• TXDIS: Transmitter Disable
0 = No effect.
1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped.
• RSTSTA: Reset Status Bits
0 = No effect.
1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR.
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24.6.2 Debug Unit Mode Register
Name:
Address:
Access:
DBGU_MR
0xFFFFF204
Read-write
31
–
30
–
29
–
23
–
15
22
–
14
7
–
CHMODE
6
–
21
–
13
–
5
–
• PAR: Parity Type
Value
0b000
0b001
0b010
0b011
0b1xx
Name
EVEN
ODD
SPACE
MARK
NONE
• CHMODE: Channel Mode
Value
0b00
0b01
0b10
0b11
Name
NORM
AUTO
LOCLOOP
REMLOOP
Description
Even Parity
Odd Parity
Space: Parity forced to 0
Mark: Parity forced to 1
No Parity
Description
Normal Mode
Automatic Echo
Local Loopback
Remote Loopback
28
–
20
–
12
–
4
–
27
–
19
–
11
3
–
26
–
18
–
10
PAR
2
–
25
–
17
–
9
1
–
24
–
16
–
8
–
0
–
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24.6.3 Debug Unit Interrupt Enable Register
Name:
Address:
Access:
DBGU_IER
0xFFFFF208
Write-only
31
COMMRX
30
COMMTX
29
–
23
–
15
–
7
PARE
22
–
14
–
6
FRAME
21
–
13
–
5
OVRE
• RXRDY: Enable RXRDY Interrupt
• TXRDY: Enable TXRDY Interrupt
• OVRE: Enable Overrun Error Interrupt
• FRAME: Enable Framing Error Interrupt
• PARE: Enable Parity Error Interrupt
• TXEMPTY: Enable TXEMPTY Interrupt
• COMMTX: Enable COMMTX (from ARM) Interrupt
• COMMRX: Enable COMMRX (from ARM) Interrupt
0 = No effect.
1 = Enables the corresponding interrupt.
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
TXEMPTY
1
TXRDY
24
–
16
–
8
–
0
RXRDY
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24.6.4 Debug Unit Interrupt Disable Register
Name:
Address:
Access:
DBGU_IDR
0xFFFFF20C
Write-only
31
COMMRX
30
COMMTX
29
–
23
–
15
–
7
PARE
22
–
14
–
6
FRAME
21
–
13
–
5
OVRE
• RXRDY: Disable RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• OVRE: Disable Overrun Error Interrupt
• FRAME: Disable Framing Error Interrupt
• PARE: Disable Parity Error Interrupt
• TXEMPTY: Disable TXEMPTY Interrupt
• COMMTX: Disable COMMTX (from ARM) Interrupt
• COMMRX: Disable COMMRX (from ARM) Interrupt
0 = No effect.
1 = Disables the corresponding interrupt.
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
TXEMPTY
1
TXRDY
24
–
16
–
8
–
0
RXRDY
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24.6.5 Debug Unit Interrupt Mask Register
Name:
Address:
Access:
DBGU_IMR
0xFFFFF210
Read-only
31
COMMRX
30
COMMTX
29
–
23
–
15
–
7
PARE
22
–
14
–
6
FRAME
21
–
13
–
5
OVRE
• RXRDY: Mask RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• OVRE: Mask Overrun Error Interrupt
• FRAME: Mask Framing Error Interrupt
• PARE: Mask Parity Error Interrupt
• TXEMPTY: Mask TXEMPTY Interrupt
• COMMTX: Mask COMMTX Interrupt
• COMMRX: Mask COMMRX Interrupt
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
TXEMPTY
1
TXRDY
24
–
16
–
8
–
0
RXRDY
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24.6.6 Debug Unit Status Register
Name:
Address:
Access:
DBGU_SR
0xFFFFF214
Read-only
31
COMMRX
30
COMMTX
29
–
23
–
15
–
7
PARE
22
–
14
–
6
FRAME
21
–
13
–
5
OVRE
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
TXEMPTY
1
TXRDY
• RXRDY: Receiver Ready
0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read.
• TXRDY: Transmitter Ready
0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled.
1 = There is no character written to DBGU_THR not yet transferred to the Shift Register.
24
–
16
–
8
–
0
RXRDY
• OVRE: Overrun Error
0 = No overrun error has occurred since the last RSTSTA.
1 = At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
0 = No framing error has occurred since the last RSTSTA.
1 = At least one framing error has occurred since the last RSTSTA.
• PARE: Parity Error
0 = No parity error has occurred since the last RSTSTA.
1 = At least one parity error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty
0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled.
1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter.
• COMMTX: Debug Communication Channel Write Status
0 = COMMTX from the ARM processor is inactive.
1 = COMMTX from the ARM processor is active.
• COMMRX: Debug Communication Channel Read Status
0 = COMMRX from the ARM processor is inactive.
1 = COMMRX from the ARM processor is active.
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24.6.7 Debug Unit Receiver Holding Register
Name:
Address:
Access:
DBGU_RHR
0xFFFFF218
Read-only
31
–
30
–
29
–
23
–
15
–
7
22
–
14
–
6
21
–
13
–
5
28
–
20
–
12
–
4
RXCHR
27
–
19
–
11
–
3
• RXCHR: Received Character
Last received character if RXRDY is set.
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
24.6.8 Debug Unit Transmit Holding Register
Name:
Address:
Access:
DBGU_THR
0xFFFFF21C
Write-only
31
–
30
–
29
–
28
–
23
–
15
–
7
22
–
14
–
6
21
–
13
–
5
20
–
12
–
4
27
–
19
–
11
–
3
TXCHR
• TXCHR: Character to be Transmitted
Next character to be transmitted after the current character if TXRDY is not set.
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
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24.6.9 Debug Unit Baud Rate Generator Register
Name:
Address:
Access:
DBGU_BRGR
0xFFFFF220
Read-write
31
–
30
–
29
–
28
–
23
–
15
22
–
14
21
–
13
20
–
12
7 6 5 4
CD
CD
• CD: Clock Divisor
Value
0
1
2 to 65535
Name
DISABLED
MCK
–
Description
DBGU Disabled
MCK
MCK / (CD x 16)
27
–
19
–
11
3
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
–
8
0
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24.6.10 Debug Unit Chip ID Register
Name:
Address:
Access:
DBGU_CIDR
0xFFFFF240
Read-only
31
EXT
23
15
7
30
22
14
6
EPROC
ARCH
29
NVPTYP
21
13
NVPSIZ2
5
28
20
12
4
• VERSION: Version of the Device
Values depend upon the version of the device.
• EPROC: Embedded Processor
Value
1
2
3
4
5
6
Name
ARM946ES
ARM7TDMI
CM3
ARM920T
ARM926EJS
CA5
Description
ARM946ES
ARM7TDMI
Cortex ® -M3
ARM920T
ARM926EJS
Cortex ® -A5
• NVPSIZ: Nonvolatile Program Memory Size
8
9
10
11
12
5
6
7
Value
0
1
2
3
4
64K
–
128K
–
256K
512K
–
1024K
Name
NONE
8K
16K
32K
–
Description
None
8K bytes
16K bytes
32K bytes
Reserved
64K bytes
Reserved
128K bytes
Reserved
256K bytes
512K bytes
Reserved
1024K bytes
11
3
27
19
26
ARCH
18
SRAMSIZ
10
2
VERSION
NVPSIZ
25
17
9
1
8
0
24
16
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10
11
8
9
12
5
6
7
Value
0
1
2
3
4
Value
13
14
15
Name
–
2048K
–
Description
Reserved
2048K bytes
Reserved
• NVPSIZ2 Second Nonvolatile Program Memory Size
7
8
9
10
4
5
6
Value
0
1
2
3
11
12
13
14
15
128K
–
256K
512K
–
1024K
–
2048K
–
Name
NONE
8K
16K
32K
–
64K
Description
None
8K bytes
16K bytes
32K bytes
Reserved
64K bytes
Reserved
128K bytes
Reserved
256K bytes
512K bytes
Reserved
1024K bytes
Reserved
2048K bytes
Reserved
• SRAMSIZ: Internal SRAM Size
4K
80K
160K
8K
16K
32K
64K
128K
Name
–
1K
2K
6K
112K
Description
Reserved
1K bytes
2K bytes
6K bytes
112K bytes
4K bytes
80K bytes
160K bytes
8K bytes
16K bytes
32K bytes
64K bytes
128K bytes
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Value
13
14
15
Name
256K
96K
512K
• ARCH: Architecture Identifier
0x73
0x75
0x76
0x80
0x81
0x83
0x84
0x85
0x60
0x61
0x63
0x70
0x71
0x72
Value
0x19
0x29
0x34
0x37
0x39
0x3B
0x40
0x42
0x55
Name
AT91SAM9xx
AT91SAM9XExx
AT91x34
CAP7
CAP9
CAP11
AT91x40
AT91x42
AT91x55
AT91SAM7Axx
AT91SAM7AQxx
AT91x63
AT91SAM7Sxx
AT91SAM7XCxx
AT91SAM7SExx
AT91SAM7Lxx
AT91SAM7Xxx
AT91SAM7SLxx
ATSAM3UxC
ATSAM3UxE
ATSAM3AxC
ATSAM3XxC
ATSAM3XxE
0x86
0x88
0x89
0x8A
0x92
0x93
0x94
0x95
0x98
0x99
ATSAM3XxG
ATSAM3SxA
ATSAM3SxB
ATSAM3SxC
AT91x92
ATSAM3NxA
ATSAM3NxB
ATSAM3NxC
ATSAM3SDxA
ATSAM3SDxB
Description
256K bytes
96K bytes
512K bytes
Description
AT91SAM9xx Series
AT91SAM9XExx Series
AT91x34 Series
CAP7 Series
CAP9 Series
CAP11 Series
AT91x40 Series
AT91x42 Series
AT91x55 Series
AT91SAM7Axx Series
AT91SAM7AQxx Series
AT91x63 Series
AT91SAM7Sxx Series
AT91SAM7XCxx Series
AT91SAM7SExx Series
AT91SAM7Lxx Series
AT91SAM7Xxx Series
AT91SAM7SLxx Series
ATSAM3UxC Series (100-pin version)
ATSAM3UxE Series (144-pin version)
ATSAM3AxC Series (100-pin version)
ATSAM3XxC Series (100-pin version)
ATSAM3XxE Series (144-pin version)
ATSAM3XxG Series (208/217-pin version)
ATSAM3SxA Series (48-pin version)
ATSAM3SxB Series (64-pin version)
ATSAM3SxC Series (100-pin version)
AT91x92 Series
ATSAM3NxA Series (48-pin version)
ATSAM3NxB Series (64-pin version)
ATSAM3NxC Series (100-pin version)
ATSAM3SDxA Series (48-pin version)
ATSAM3SDxB Series (64-pin version)
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Value
0x9A
0xA5
0xF0
Name
ATSAM3SDxC
–
AT75Cxx
Description
ATSAM3SDxC Series (100-pin version)
Reserved
AT75Cxx Series
• NVPTYP: Nonvolatile Program Memory Type
Value
0
1
4
2
Name
ROM
ROMLESS
SRAM
FLASH
3 ROM_FLASH
Description
ROM
ROMless or on-chip Flash
SRAM emulating ROM
Embedded Flash Memory
ROM and Embedded Flash Memory
NVPSIZ is ROM size
NVPSIZ2 is Flash size
• EXT: Extension Flag
0 = Chip ID has a single register definition without extension
1 = An extended Chip ID exists.
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24.6.11 Debug Unit Chip ID Extension Register
Name:
Address:
Access:
DBGU_EXID
0xFFFFF244
Read-only
31 30 29 28
23
15
7
22
14
6
21
13
5
20
12
4
EXID
27
19
EXID
11
EXID
3
EXID
• EXID: Chip ID Extension
Reads 0 if the bit EXT in DBGU_CIDR is 0.
10
2
26
18
9
1
25
17
8
0
24
16
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24.6.12 Debug Unit Force NTRST Register
Name:
Address:
Access:
DBGU_FNR
0xFFFFF248
Read-write
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
• FNTRST: Force NTRST
0 = NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal.
1 = NTRST of the ARM processor’s TAP controller is held low.
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
FNTRST
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25.
Bus Matrix (MATRIX)
25.1 Description
The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
The Bus Matrix user interface is compliant with ARM Advanced Peripheral Bus and provides a Chip Configuration User
Interface with Registers that allow the Bus Matrix to support application specific features.
25.2 Embedded Characteristics
12-layer Matrix, handling requests from 11 masters
Programmable Arbitration strategy
Fixed-priority Arbitration
Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master
Burst Management
Breaking with Slot Cycle Limit Support
Undefined Burst Length Support
One Address Decoder provided per Master
Three different slaves may be assigned to each decoded memory area: one for internal ROM boot, one for internal flash boot, one after remap
Boot Mode Select
Non-volatile Boot Memory can be internal ROM or external memory on EBI_NCS0
Selection is made by General purpose NVM bit sampled at reset
Remap Command
Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or External Flash)
Allows Handling of Dynamic Exception Vectors
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25.2.1 Matrix Masters
The Bus Matrix manages 12 masters, which means that each master can perform an access concurrently with others, depending on whether the slave it accesses is available.
Each master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings.
Table 25-1. List of Bus Matrix Masters
Master 0 ARM926 Instruction
Master 1
Master 2 & 3
ARM926 Data
DMA Controller 0
Master 4 & 5
Master 6
Master 7
Master 8
DMA Controller 1
UDP HS DMA
UHP EHCI DMA
UHP OHCI DMA
Master 9
Master 10
Master 11
LCD DMA
EMAC DMA
Reserved
25.2.2 Matrix Slaves
The Bus Matrix manages 10 slaves. Each slave has its own arbiter, thus allowing a different arbitration per slave to be programmed.
Table 25-2. List of Bus Matrix Slaves
Slave 0 Internal SRAM
Slave 1
Slave 2
Internal ROM
Soft Modem (SMD)
USB Device High Speed Dual Port RAM (DPR)
Slave 3
Slave 4
Slave 5
Slave 6
Slave 7
Slave 8
Slave 9
USB Host EHCI registers
USB Host OHCI registers
External Bus Interface
DDR2 port 1
DDR2 port 2
DDR2 port 3
Peripheral Bridge 0
Peripheral Bridge 1
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25.2.3 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “–” in the following table.
Table 25-3. Master to Slave Access
Masters 0 1 2 & 3 4 & 5 10 11
Slaves
0
1
2
3
Internal SRAM
Internal ROM
SMD
USB Device High
Speed DPR
USB Host EHCI registers
USB Host OHCI registers
4
5
External Bus
Interface
6
7
DDR2 Port 1
DDR2 Port 2
DDR2 Port 3
8 Peripheral Bridge 0
9 Peripheral Bridge 1
ARM926
Instr.
X
X
X
ARM926
Data
X
X
X
X
X
X
–
–
X
X
X
X
–
X
–
X
X
DMA 0
X
X
–
–
X
–
X
X
–
X
DMA 1
X
X
X
–
X
–
X
–
X
X
6 7 8 9
USB
Device HS
DMA
USB Host
HS EHCI
USB Host
HS OHCI LCD DMA
X
–
–
X
–
–
X
–
–
X
–
–
–
X
–
–
–
–
–
–
X
–
–
–
–
–
–
X
–
–
–
–
–
–
X
X
–
–
–
–
EMAC
DMA
X
–
–
Reserved
X
–
–
–
X
–
–
–
–
–
–
X
–
–
–
–
–
25.3 Memory Mapping
The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several memory mappings. Each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e., external RAM, internal ROM or internal Flash, etc.) becomes possible.
The Bus Matrix user interface provides the Master Remap Control Register (MATRIX_MRCR), that performs remap action for every master independently.
25.4 Special Bus Granting Mechanism
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from masters.
This mechanism reduces latency at first access of a burst, or single transfer, as long as the slave is free from any other master access, but does not provide any benefit as soon as the slave is continuously accessed by more than one master, since arbitration is pipelined and has no negative effect on the slave bandwidth or access latency.
This bus granting mechanism sets a different default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters:
No default master
Last access master
Fixed default master
To change from one type of default master to another, the Bus Matrix user interface provides the Slave Configuration
Registers, one for every slave, that set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default master type (no
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default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Refer to
Section 25.7.2 “Bus Matrix Slave
.
25.4.1 No Default Master
After the end of the current access, if no other request is pending, the slave is disconnected from all masters.
This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without default master may be used for masters that perform significant bursts or several transfers with no Idle in between, or if the slave bus bandwidth is widely used by one or more masters.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput, irregardless of the number of requesting masters.
25.4.2 Last Access Master
After the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request.
This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other nonprivileged masters still get one latency clock cycle if they want to access the same slave. This technique is useful for masters that mainly perform single accesses or short bursts with some Idle cycles in between.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput irregardless of the number of requesting masters.
25.4.3 Fixed Default Master
After the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike the last access master, the fixed default master does not change unless the user modifies it by software
(FIXED_DEFMSTR field of the related MATRIX_SCFG).
This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave. All requests attempted by the fixed default master do not cause any arbitration latency, whereas other non-privileged masters will get one latency cycle. This technique is useful for a master that mainly performs single accesses or short bursts with Idle cycles in between.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput, irregardless of the number of requesting masters.
25.5 Arbitration
The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e., when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus arbitrating each slave specifically.
The Bus Matrix provides the user with the possibility of choosing between two arbitration types or mixing them for each slave:
1.
Round-robin Arbitration (default)
2.
Fixed Priority Arbitration
The resulting algorithm may be complemented by selecting a default master configuration for each slave.
When re-arbitration is required, specific conditions apply. See
Section 25.5.1 “Arbitration Scheduling” .
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25.5.1 Arbitration Scheduling
Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles:
1.
Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently accessing it.
2.
Single Cycles: When a slave is currently doing a single access.
3.
End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. See
25.5.1.1 “Undefined Length Burst Arbitration”
4.
Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access
is too long and must be broken. See Section 25.5.1.2 “Slot Cycle Limit Arbitration”
25.5.1.1 Undefined Length Burst Arbitration
In order to prevent long AHB burst lengths that can lock the access to the slave for an excessive period of time, the user can trigger the re-arbitration before the end of the incremental bursts. The re-arbitration period can be selected from the following Undefined Length Burst Type (ULBT) possibilities:
1.
Unlimited: no predetermined end of burst is generated. This value enables 1-kbyte burst lengths.
2.
1-beat bursts: predetermined end of burst is generated at each single transfer during the INCR transfer.
3.
4-beat bursts: predetermined end of burst is generated at the end of each 4-beat boundary during INCR transfer.
4.
8-beat bursts: predetermined end of burst is generated at the end of each 8-beat boundary during INCR transfer.
5.
16-beat bursts: predetermined end of burst is generated at the end of each 16-beat boundary during INCR transfer.
6.
32-beat bursts: predetermined end of burst is generated at the end of each 32-beat boundary during INCR transfer.
7.
64-beat bursts: predetermined end of burst is generated at the end of each 64-beat boundary during INCR transfer.
8.
128-beat bursts: predetermined end of burst is generated at the end of each 128-beat boundary during INCR transfer.
Use of undefined length16-beat bursts, or less, is discouraged since this generally decreases significantly overall bus bandwidth due to arbitration and slave latencies at each first access of a burst.
If the master does not permanently and continuously request the same slave or has an intrinsically limited average throughput, the ULBT should be left at its default unlimited value, knowing that the AHB specification natively limits all word bursts to 256 beats and double-word bursts to 128 beats because of its 1 Kbyte address boundaries.
Unless duly needed, the ULBT should be left at its default value of 0 for power saving.
This selection can be done through the ULBT field of the Master Configuration Registers (MATRIX_MCFG).
25.5.1.2 Slot Cycle Limit Arbitration
The Bus Matrix contains specific logic to break long accesses, such as back-to-back undefined length bursts or very long bursts on a very slow slave (e.g., an external low speed memory). At each arbitration time a counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter elapses, the arbiter has the ability to re-arbitrate at the end of the current AHB bus access cycle.
Unless a master has a very tight access latency constraint, which could lead to data overflow or underflow due to a badly undersized internal FIFO with respect to its throughput, the Slot Cycle Limit should be disabled (SLOT_CYCLE = 0) or set to its default maximum value in order not to inefficiently break long bursts performed by some Atmel masters.
However, the Slot Cycle Limit should not be disabled in the particular case of a master capable of accessing the slave by performing back-to-back undefined length bursts shorter than the number of ULBT beats with no Idle cycle in between, since in this case the arbitration could be frozen all along the burst sequence.
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In most cases this feature is not needed and should be disabled for power saving.
Warning: This feature cannot prevent any slave from locking its access indefinitely.
25.5.2 Arbitration Priority Scheme
The bus Matrix arbitration scheme is organized in priority pools.
Round-robin priority is used in the highest and lowest priority pools, whereas fixed level priority is used between priority pools and in the intermediate priority pools.
For each slave, each master is assigned to one of the slave priority pools through the priority registers for slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating master requests, this programmed priority level always takes precedence.
After reset, all the masters belong to the lowest priority pool (MxPR = 0) and are therefore granted bus access in a true round-robin order.
The highest priority pool must be specifically reserved for masters requiring very low access latency. If more than one master belongs to this pool, they will be granted bus access in a biased round-robin manner which allows tight and deterministic maximum access latency from AHB bus requests. At worst, any currently occurring high-priority master request will be granted after the current bus master access has ended and other high priority pool master requests, if any, have been granted once each.
The lowest priority pool shares the remaining bus bandwidth between AHB Masters.
Intermediate priority pools allow fine priority tuning. Typically, a moderately latency-critical master or a bandwidth-only critical master will use such a priority level. The higher the priority level (MxPR value), the higher the master priority.
All combinations of MxPR values are allowed for all masters and slaves. For example some masters might be assigned to the highest priority pool (round-robin) and the remaining masters to the lowest priority pool (round-robin), with no master for intermediate fix priority levels.
If more than one master requests the slave bus, irregardless of the respective masters priorities, no master will be granted the slave bus for two consecutive runs. A master can only get back-to-back grants so long as it is the only requesting master.
25.5.2.1 Fixed Priority Arbitration
Fixed priority arbitration algorithm is the first and only arbitration algorithm applied between masters from distinct priority pools. It is also used in priority pools other than the highest and lowest priority pools (intermediate priority pools).
Fixed priority arbitration allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user in the MxPR field for each master in the Priority Registers, MATRIX_PRAS and MATRIX_PRBS. If two or more master requests are active at the same time, the master with the highest priority
MxPR number is serviced first.
In intermediate priority pools, if two or more master requests with the same priority are active at the same time, the master with the highest number is serviced first.
25.5.2.2 Round-Robin Arbitration
This algorithm is only used in the highest and lowest priority pools. It allows the Bus Matrix arbiters to properly dispatch requests from different masters to the same slave. If two or more master requests are active at the same time in the priority pool, they are serviced in a round-robin increasing master number order.
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25.6 Register Write Protection
To prevent any single software error from corrupting MATRIX behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the “Write Protection Mode Register”
(MATRIX_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the
“Write Protection Status Register”
(MATRIX_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading the MATRIX_WPSR.
The following registers can be write-protected:
“Bus Matrix Master Configuration Registers”
“Bus Matrix Slave Configuration Registers”
“Bus Matrix Priority Registers A For Slaves”
“Bus Matrix Priority Registers B For Slaves”
“Bus Matrix Master Remap Control Register”
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25.7 Bus Matrix (MATRIX) User Interface
Table 25-4. Register Mapping
Offset Register
0x0000 Master Configuration Register 0
0x0004
0x0008
0x000C
0x0010
Master Configuration Register 1
Master Configuration Register 2
Master Configuration Register 3
Master Configuration Register 4
0x0014
0x0018
0x001C
0x0020
Master Configuration Register 5
Master Configuration Register 6
Master Configuration Register 7
Master Configuration Register 8
0x0024
0x0028
Master Configuration Register 9
Master Configuration Register 10
0x002C Reserved
0x0030–0x003C Reserved
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
Slave Configuration Register 0
Slave Configuration Register 1
Slave Configuration Register 2
Slave Configuration Register 3
Slave Configuration Register 4
Slave Configuration Register 5
Slave Configuration Register 6
Slave Configuration Register 7
0x0060
0x0064
Slave Configuration Register 8
Slave Configuration Register 9
0x0068–0x007C Reserved
0x0080 Priority Register A for Slave 0
0x0084
0x0088
0x008C
0x0090
Priority Register B for Slave 0
Priority Register A for Slave 1
Priority Register B for Slave 1
Priority Register A for Slave 2
0x0094
0x0098
0x009C
0x00A0
0x00A4
0x00A8
Priority Register B for Slave 2
Priority Register A for Slave 3
Priority Register B for Slave 3
Priority Register A for Slave 4
Priority Register B for Slave 4
Priority Register A for Slave 5
MATRIX_SCFG0
MATRIX_SCFG1
MATRIX_SCFG2
MATRIX_SCFG3
MATRIX_SCFG4
MATRIX_SCFG5
MATRIX_SCFG6
MATRIX_SCFG7
MATRIX_SCFG8
MATRIX_SCFG9
–
MATRIX_PRAS0
MATRIX_PRBS0
MATRIX_PRAS1
MATRIX_PRBS1
MATRIX_PRAS2
Name
MATRIX_MCFG0
MATRIX_MCFG1
MATRIX_MCFG2
MATRIX_MCFG3
MATRIX_MCFG4
MATRIX_MCFG5
MATRIX_MCFG6
MATRIX_MCFG7
MATRIX_MCFG8
–
–
MATRIX_MCFG9
MATRIX_MCFG10
MATRIX_PRBS2
MATRIX_PRAS3
MATRIX_PRBS3
MATRIX_PRAS4
MATRIX_PRBS4
MATRIX_PRAS5
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
–
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Access
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
–
–
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
0x000001FF
0x000001FF
0x000001FF
0x000001FF
0x000001FF
0x000001FF
0x000001FF
0x000001FF
0x000001FF
0x000001FF
–
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
0x00000001
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
–
–
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
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Table 25-4. Register Mapping (Continued)
Offset
0x00AC
Register
Priority Register B for Slave 5
0x00B0
0x00B4
0x00B8
0x00BC
0x00C0
0x00C4
Priority Register A for Slave 6
Priority Register B for Slave 6
Priority Register A for Slave 7
Priority Register B for Slave 7
Priority Register A for Slave 8
Priority Register B for Slave 8
0x00C8
0x00CC
Priority Register A for Slave 9
Priority Register B for Slave 9
0x00D0–0x00FC Reserved
0x0100 Master Remap Control Register
0x0104–0x011C Reserved
0x0120 EBI Chip Select Assignment Register
0x0124–0x01FC Reserved
0x01E4 Write Protection Mode Register
0x01E8 Write Protection Status Register
Name
MATRIX_PRBS5
MATRIX_PRAS6
MATRIX_PRBS6
MATRIX_PRAS7
MATRIX_PRBS7
MATRIX_PRAS8
MATRIX_PRBS8
MATRIX_PRAS9
MATRIX_PRBS9
–
MATRIX_MRCR
–
CCFG_EBICSA
–
MATRIX_WPMR
MATRIX_WPSR
Access
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
–
Read/Write
–
Read/Write
–
Read/Write
Read-only
Reset
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
–
0x00000000
–
0x00000200
–
0x00000000
0x00000000
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25.7.1 Bus Matrix Master Configuration Registers
Name: MATRIX_MCFG0...MATRIX_MCFG10
Address: 0xFFFFDE00 [0], 0xFFFFDE04 [1], 0xFFFFDE08 [2], 0xFFFFDDEC [3], 0xFFFFDE10 [4], 0xFFFFDE14 [5],
0xFFFFDE18 [6], 0xFFFFDE1C [7], 0xFFFFDE20 [8], 0xFFFFDE24 [9], 0xFFFFDE28 [10]
Access: Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
7
–
6
–
5
–
4
–
3
–
2
This register can only be written if the WPEN bit is cleared in the “Write Protection Mode Register”
.
1
ULBT
8
–
0
• ULBT: Undefined Length Burst Type
0: Unlimited Length Burst
No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle
Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next
AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.
1: Single Access
The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst.
2: 4-beat Burst
The undefined length burst is split into 4-beat bursts, allowing re-arbitration at each 4-beat burst end.
3: 8-beat Burst
The undefined length burst is split into 8-beat bursts, allowing re-arbitration at each 8-beat burst end.
4: 16-beat Burst
The undefined length burst is split into 16-beat bursts, allowing re-arbitration at each 16-beat burst end.
5: 32-beat Burst
The undefined length burst is split into 32-beat bursts, allowing re-arbitration at each 32-beat burst end.
6: 64-beat Burst
The undefined length burst is split into 64-beat bursts, allowing re-arbitration at each 64-beat burst end.
7: 128-beat Burst
The undefined length burst is split into 128-beat bursts, allowing re-arbitration at each 128-beat burst end.
Unless duly needed, the ULBT should be left at its default 0 value for power saving.
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25.7.2 Bus Matrix Slave Configuration Registers
Name: MATRIX_SCFG0...MATRIX_SCFG9
Address: 0xFFFFDE40 [0], 0xFFFFDE44 [1], 0xFFFFDE48 [2], 0xFFFFDE4C [3], 0xFFFFDE50 [4], 0xFFFFDE54 [5],
0xFFFFDE58 [6], 0xFFFFDE5C [7], 0xFFFFDE60 [8], 0xFFFFDE64 [9]
Access: Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21 20 19
FIXED_DEFMSTR
18 17 16
DEFMSTR_TYPE
15
–
14
–
13
–
12
–
11
–
10
–
7 6 5 4
SLOT_CYCLE
3 2
This register can only be written if the WPEN bit is cleared in the “Write Protection Mode Register”
.
9
–
1
8
SLOT_CYCLE
0
• SLOT_CYCLE: Maximum Bus Grant Duration for Masters
When SLOT_CYCLE AHB clock cycles have elapsed since the last arbitration, a new arbitration takes place so as to let another master access this slave. If another master is requesting the slave bus, then the current master burst is broken.
If SLOT_CYCLE = 0, the Slot Cycle Limit feature is disabled and bursts always complete unless broken according to the ULBT.
This limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting for slave access or in the particular case of a master performing back-to-back undefined length bursts indefinitely freezing the arbitration.
This limit must not be too small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. The default maximum value is usually an optimal conservative choice.
In most cases this feature is not needed and should be disabled for power saving. See
Section 25.5.1.2 on page 283 .
• DEFMSTR_TYPE: Default Master Type
0: No Default Master
At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in a one-clock cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.
This results in not having a one-clock cycle latency when the last master tries to access the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.
This results in not having a one-clock cycle latency when the fixed master tries to access the slave again.
• FIXED_DEFMSTR: Fixed Default Master
This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
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25.7.3 Bus Matrix Priority Registers A For Slaves
Name: MATRIX_PRAS0...MATRIX_PRAS9
Address: 0xFFFFDE80 [0], 0xFFFFDE88 [1], 0xFFFFDE90 [2], 0xFFFFDE98 [3], 0xFFFFDEA0 [4], 0xFFFFDEA8 [5],
0xFFFFDEB0 [6], 0xFFFFDEB8 [7], 0xFFFFDEC0 [8], 0xFFFFDEC8 [9]
Access: Read/Write
31
–
30
–
29
M7PR
28 27
–
26
–
25
M6PR
24
23
–
22
–
21
M5PR
20 19
–
18
–
17
M4PR
16
8 15
–
14
–
13
M3PR
12 11
–
10
–
7
–
6
–
5
M1PR
4 3
–
2
–
This register can only be written if the WPEN bit is cleared in the “Write Protection Mode Register”
.
• MxPR: Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
All the masters programmed with the same MxPR value for the slave make up a priority pool.
Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools.
Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2).
See “Arbitration Priority Scheme” on page 284
for details.
9
1
M2PR
M0PR
0
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25.7.4 Bus Matrix Priority Registers B For Slaves
Name: MATRIX_PRBS0...MATRIX_PRBS9
Address: 0xFFFFDE84 [0], 0xFFFFDE8C [1], 0xFFFFDE94 [2], 0xFFFFDE9C [3], 0xFFFFDEA4 [4], 0xFFFFDEAC [5],
0xFFFFDEB4 [6], 0xFFFFDEBC [7], 0xFFFFDEC4 [8], 0xFFFFDECC [9]
Access: Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
8 15
–
14
–
13
–
12
–
11
–
10
–
7
–
6
–
5
M9PR
4 3
–
2
–
This register can only be written if the WPEN bit is cleared in the “Write Protection Mode Register”
.
• MxPR: Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
All the masters programmed with the same MxPR value for the slave make up a priority pool.
Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools.
Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2).
See “Arbitration Priority Scheme” on page 284
for details.
9
1
M10PR
M8PR
0
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25.7.5 Bus Matrix Master Remap Control Register
Name:
Address:
Access:
MATRIX_MRCR
0xFFFFDF00
Read/Write
31
–
30
–
29
–
28
–
23
–
15
–
7
RCB7
22
–
14
–
6
RCB6
21
–
13
–
5
RCB5
20
–
12
–
4
RCB4
11
–
3
RCB3
27
–
19
–
26
–
18
–
10
RCB10
2
RCB2
This register can only be written if the WPEN bit is cleared in the “Write Protection Mode Register”
.
• RCBx: Remap Command Bit for Master x
0: Disable remapped address decoding for the selected Master
1: Enable remapped address decoding for the selected Master
9
RCB9
1
RCB1
25
–
17
–
8
RCB8
0
RCB0
24
–
16
–
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25.7.6 EBI Chip Select Assignment Register
Name:
Address:
Access:
Reset:
CCFG_EBICSA
0xFFFFDF20
Read/Write
0x00000200
31
–
30
–
29
–
28
–
23
–
15
–
22
–
14
–
21
–
13
–
7
–
6
–
5
–
20
–
12
–
4
–
27
–
19
–
11
–
3
EBI_CS3A
26
–
18
–
10
–
2
–
25 24
DDR_MP_EN NFD0_ON_D16
17
EBI_DRIVE
9
EBI_DBPDC
16
–
8
EBI_DBPUC
1
EBI_CS1A
0
–
• EBI_CS1A: EBI Chip Select 1 Assignment
0: EBI Chip Select 1 is assigned to the Static Memory Controller.
1: EBI Chip Select 1 is assigned to the DDR2SDR Controller.
• EBI_CS3A: EBI Chip Select 3 Assignment
0: EBI Chip Select 3 is only assigned to the Static Memory Controller and EBI_NCS3 behaves as defined by the SMC.
1: EBI Chip Select 3 is assigned to the Static Memory Controller and the NAND Flash Logic is activated.
• EBI_DBPUC: EBI Data Bus Pull-Up Configuration
0: EBI D0–D15 Data Bus bits are internally pulled-up to the VDDIOM power supply.
1: EBI D0–D15 Data Bus bits are not internally pulled-up.
• EBI_DBPDC: EBI Data Bus Pull-Down Configuration
0: EBI D0–D15 Data Bus bits are internally pulled-down to the ground.
1: EBI D0–D15 Data Bus bits are not internally pulled-down.
• EBI_DRIVE: EBI I/O Drive Configuration
This allows to avoid overshoots and gives the best performance according to the bus load and external memories.
0: Low drive (default).
1: High drive.
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0
0
1
1
1
• NFD0_ON_D16: NAND Flash Databus Selection
0: NAND Flash I/O are connected to D0–D15 (default).
1: NAND Flash I/O are connected to D16–D31.
NFD0_ON_D16 Signals VDDIOM
NFD0 = D0,..., NFD15 = D15
NFD0 = D0,..., NFD15 = D15
NFD0 = D16,..., NFD15 = D31
NFD0 = D16,..., NFD15 = D31
NFD0 = D16,..., NFD15 = D31
1.8V
3.3V
1.8V
1.8V
3.3V
VDDNF
1.8V
3.3V
1.8V
3.3V
1.8V
External Memory
DDR2 or LP-DDR or LPSDR + NAND Flash 1.8V
32-bit SDRAM + NAND Flash 3.3V
DDR2 or LP-DDR or LPSDR + NAND Flash 1.8V
DDR2 or LP-DDR or LPSDR + NAND Flash 3.3V
16-bit SDR + NAND Flash 1.8V
• DDR_MP_EN: DDR Multi-port Enable
0: DDR Multi-port is disabled (default).
1: DDR Multi-port is enabled, performance is increased. Warning: Use only with NFDO0_ON_D16 = 0. The system behavior is unpredictable if ND0_ON_D16 is set to 1 at the same time.
Note: EBI Chip Select 1 is to be assigned to the DDR2SDR Controller.
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25.7.7 Write Protection Mode Register
Name:
Address:
Access:
MATRIX_WPMR
0xFFFFDFE4
Read/Write
31 30 29
23
15
7
–
22
14
6
–
21
13
5
–
28
WPKEY
27
20
WPKEY
19
12
WPKEY
11
4
–
3
–
26
18
10
2
–
25
17
9
1
–
24
16
8
0
WPEN
• WPEN: Write Protection Enable
0: Disables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
See Section 25.6 “Register Write Protection”
for the list of registers that can be write-protected.
• WPKEY: Write Protection Key
Value Name Description
0x4D4154 PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as
0.
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25.7.8 Write Protection Status Register
Name:
Address:
Access:
MATRIX_WPSR
0xFFFFDFE8
Read-only
31
–
30
–
29
–
23
15
22
14
21
13
28
–
27
–
20
WPVSRC
19
12
WPVSRC
11
4
–
3
–
26
–
18
10
25
–
17
9
24
–
16
8
7
–
6
–
5
–
2
–
1
–
0
WPVS
• WPVS: Write Protection Violation Status
0: No write protection violation has occurred since the last read of the MATRIX_WPSR.
1: A write protection violation has occurred since the last read of the MATRIX_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
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26.
External Bus Interface (EBI)
26.1 Description
The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device.
The Static Memory, DDR, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as
SRAM, PROM, EPROM, EEPROM, Flash, DDR2 and SDRAM. The EBI operates with 1.8V or 3.3V Power Supply
(VDDIOM).
The EBI also supports the NAND Flash protocols via integrated circuitry that greatly reduces the requirements for external components. Furthermore, the EBI handles data transfers with up to six external devices, each assigned to six address spaces defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to six chip select lines (NCS[5:0]) and several control pins that are generally multiplexed between the different external Memory Controllers.
26.2 Embedded Characteristics
Integrates three External Memory Controllers:
Static Memory Controller
DDR2/SDRAM Controller
8-bit NAND Flash ECC Controller
Up to 26-bit Address Bus (up to 64 Mbytes linear per chip select)
Up to 6 chip selects, Configurable Assignment:
Static Memory Controller on NCS0, NCS1, NCS2, NCS3, NCS4, NCS5
DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1
NAND Flash support on NCS3
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26.3 EBI Block Diagram
Figure 26-1. Organization of the External Bus Interface
Bus Matrix
External Bus Interface
AHB
DDR2
LPDDR
SDRAM
Controller
Static
Memory
Controller
MUX
Logic
Address Decoders
NAND Flash
Logic
PMECC
PMERRLOC
Controllers
Chip Select
Assignor
User Interface
D[15:0]
A0/NBS0
A1/NWR2/NBS2/DQM2
A[15:2], A19
A16/BA0
A17/BA1
A18/BA2
NCS0
NCS1/SDCS
NRD
NWR0/NWE
NWR1/NBS1
NWR3/NBS3/DQM3
SDCK, SDCK#, SDCKE
DQM[1:0]
DQS[1:0]
RAS, CAS
SDWE, SDA10
PIO
NCS3/NANDCS
NANDOE
NANDWE
A21/NANDALE
A22/NANDCLE
D[31:16]
A[25:20]
NCS5
NCS4
NCS2
NWAIT
APB
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26.4 I/O Lines Description
Table 26-1. EBI I/O Lines Description
Name Function
EBI_D0–EBI_D31
EBI_A0–EBI_A25
EBI_NWAIT
EBI_NCS0–EBI_NCS5
EBI_NWR0–EBI_NWR3
EBI_NRD
EBI_NWE
EBI_NBS0–EBI_NBS3
EBI_NANDCS
EBI_NANDOE
EBI_NANDWE
EBI_SDCK, EBI_SDCK#
EBI_SDCKE
EBI_SDCS
EBI_BA0–2
EBI_SDWE
EBI_RAS - EBI_CAS
EBI_SDA10
EBI
Data Bus
Address Bus
External Wait Signal
SMC
Chip Select Lines
Write Signals
Read Signal
Write Enable
Byte Mask Signals
EBI for NAND Flash Support
NAND Flash Chip Select Line
NAND Flash Output Enable
NAND Flash Write Enable
DDR2/SDRAM Controller
DDR2/SDRAM Differential Clock
DDR2/SDRAM Clock Enable
DDR2/SDRAM Controller Chip Select Line
Bank Select
DDR2/SDRAM Write Enable
Row and Column Signal
SDRAM Address 10 Line
Type
I/O
Output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Active Level
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment.
details the connections between the two Memory Controllers and the EBI pins.
Table 26-2. EBI Pins and Memory Controllers I/O Lines Connections
EBIx Pins
EBI_NWR1/NBS1/CFIOR
SDRAM I/O Lines
NBS1
EBI_A0/NBS0
EBI_A1/NBS2/NWR2
EBI_A[11:2]
EBI_SDA10
Not Supported
Not Supported
SDRAMC_A[9:0]
SDRAMC_A10
EBI_A12
EBI_A[15:13]
EBI_A[25:16]
EBI_D[31:0]
Not Supported
SDRAMC_A[13:11]
Not Supported
D[31:0]
SMC I/O Lines
NWR1
SMC_A0
SMC_A1
SMC_A[11:2]
Not Supported
SMC_A12
SMC_A[15:13]
SMC_A[25:16]
D[31:0]
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26.5 Application Example
26.5.1 Hardware Interface
details the connections to be applied between the EBI pins and the external devices for each Memory
Controller.
Table 26-3. EBI Pins and External Static Device Connections
Signals:
EBI_
Controller
D0–D7
8-bit
Static Device
D0–D7
2 x 8-bit
Static Devices
D0–D7
Pins of the Interfaced Device
16-bit
Static Device
4 x 8-bit
Static Devices
D0–D7
SMC
D0–D7
D8–D15
D16–D23
A0/NBS0
A1/NWR2/NBS2/DQM2
A23–A25
NCS0
NCS1/DDRSDCS
–
–
–
A0
A1
A[2:22]
A[23:25]
CS
CS
CS
D8–D15
–
–
–
A0
A[1:21]
A[22:24]
CS
CS
CS
D8–D15
–
–
NLB
A0
A[1:21]
A[22:24]
CS
CS
CS
D8–D15
D16–D23
D24–D31
–
A[0:20]
A[21:23]
CS
CS
CS
NCS3/NANDCS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
NRD
NWR0/NWE
OE
WE
OE
OE
WE
OE
NWR1/NBS1 – NUB
NWR3/NBS3/DQM3 – – –
Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes.
2. NWRx enables corresponding byte x writes. (x = 0,1,2 or 3)
3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
5. D24–31 and A20, A23–A25, NCS2, NCS4, NCS5 are multiplexed on PD15–PD31.
2 x 16-bit
Static Devices
D0–D7
D8–15
D16–D23
D24–D31
NLB
NLB
A[0:20]
A[21:23]
CS
CS
CS
CS
CS
CS
OE
WE
NUB
NUB
32-bit
Static Device
D0–D7
D8–15
D16–D23
D24–D31
BE0
BE2
A[0:20]
A[21:23]
CS
CS
CS
CS
CS
CS
OE
WE
BE1
BE3
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Table 26-4. EBI Pins and External Device Connections
Signals:
EBI_
Controller
D0–D15
D16–D31
A0/NBS0
A1/NWR2/NBS2/DQM2
DQM0–DQM1
DQS0–DQS1
A2–A10
A11
SDA10
A12
A13–A14
A15
A16/BA0
A17/BA1
A18/BA2
A19
A20
A21/NANDALE
A22/NANDCLE
A23–A24
A25
NCS0
NCS1/DDRSDCS
NCS2
NCS3/NANDCS
NCS4
NCS5
NANDOE
NANDWE
NRD
NWR0/NWE
NWR1/NBS1
NWR3/NBS3/DQM3
SDCK
Power supply
VDDIOM
VDDNF
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDNF
VDDNF
VDDNF
VDDNF
VDDNF
VDDIOM
VDDIOM
VDDNF
VDDNF
VDDNF
VDDNF
VDDNF
VDDNF
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
–
DDRCS
–
–
–
–
–
–
–
–
–
–
CK
–
–
–
–
BA1
BA2
–
–
DDR2/LPDDR
DDRC
D0–D15
–
–
Pins of the Interfaced Device
SDR/LPSDR
SDRAMC
D0–D15
D16–D31
–
NAND Flash
NFC
NFD0–NFD15
NFD0–NFD15
–
–
DQM0–DQM1
DQS0–DQS1
DQM2
DQM0–DQM1
–
–
–
–
A[0:8]
A9
A10
–
A[11:12]
A13
BA0
A[0:8]
A9
A10
–
A[11:12]
A13
BA0
–
–
–
–
–
–
–
BA1
BA2
–
–
–
–
–
–
–
SDCS
–
–
–
–
–
–
–
–
–
DQM3
CK
–
–
OE
WE
–
–
–
CE
–
–
–
–
–
ALE
CLE
–
–
–
–
–
–
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Table 26-4. EBI Pins and External Device Connections (Continued)
Signals:
EBI_ DDR2/LPDDR
Pins of the Interfaced Device
SDR/LPSDR
Controller
SDCK#
SDCKE
Power supply
VDDIOM
VDDIOM
DDRC
CK#
CKE
SDRAMC
–
CKE
RAS
CAS
SDWE
VDDIOM
VDDIOM
VDDIOM
RAS
CAS
WE
RAS
CAS
WE
NAND Flash
NFC
–
–
–
–
–
Pxx VDDNF – – CE
Pxx VDDNF – – RDY
Note: 1. The switch NFD0_ON_D16 is used to select NAND Flash path on D0–D7 or D16–D23 depending on memory power supplies. This switch is located in the CCFG_EBICSA register in the Bus Matrix.
26.5.2 Product Dependencies
26.5.2.1 I/O Lines
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the
External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller.
26.5.3 Functional Description
The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external memories or peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements:
Static Memory Controller (SMC)
DDR2/SDRAM Controller (DDR2SDRC)
Programmable Multibit ECC Controller (PMECC)
A chip select assignment feature that assigns an AHB address space to the external devices
A multiplex controller circuit that shares the pins between the different Memory Controllers
Programmable NAND Flash support logic
26.5.3.1 Bus Multiplexing
The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float times defined in the Memory Controllers. Furthermore, refresh cycles of the DDR2 and SDRAM are executed independently by the DDR2SDR Controller without delaying the other external Memory Controller accesses.
26.5.3.2 Pull-up and Pull-down Control
The EBI_CSA registers in the Chip Configuration User Interface enable on-chip pull-up and pull-down resistors on data bus lines not multiplexed with the PIO Controller lines. The pull-down resistors are enabled after reset. The bits,
EBIx_DBPUC and EBI_DBPDC, control the pull-up and pull-down resistors on the D0–D15 lines. Pull-up or pull-down resistors on the D16–D31 lines can be performed by programming the appropriate PIO controller.
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26.5.3.3 Drive Level and Delay Control
The EBI I/Os accept two drive levels, HIGH and LOW. This allows to avoid overshoots and give the best performance according to the bus load and external memories.
The slew rates are determined by programming EBI_DRIVE bit in the EBI Chip Select Assignment Register
(CCFG_EBICSA) in the Bus Matrix.
At reset the selected current drive is LOW.
To reduce EMI, programmable delay has been inserted on high-speed lines. The control of these delays is as follows:
EBI (DDR2SDRC\SMC\NAND Flash)
D[15:0] controlled by 2 registers DELAY1 and DELAY2 located in the SMC user interface.
D[0] <=> DELAY1[3:0],
D[1] <=> DELAY1[7:4],...,
D[6] <=> DELAY1[27:24],
D[7] <=> DELAY1[31:28]
D[8] <=> DELAY2[3:0],
D[9] <=> DELAY2[7:4],...,
D[14] <=> DELAY2[27:24],
D[15] <=> DELAY2[31:28]
D[31:16] on PIOD[21:6] controlled by 2 registers, DELAY3 and DELAY4 located in the SMC user interface.
D[16] <=> DELAY3[3:0],
D[17] <=> DELAY3[7:4],...,
...
D[24] <=> DELAY4[3:0]
D[26] <=> DELAY4[11:8]
D[27] <=> DELAY4[15:12]
D[28] <=> DELAY4[19:16]
D[29] <=> DELAY4[23:20]
D[30] <=> DELAY4[27:24]
D[31] <=> DELAY4[31:28]
Note: 1. A20, A23, A24 and A25 are multiplexed with D25, D26, D27 and D28 in PIOD, on PD15, PD16, PD17 and
PD18 lines respectively. Delays applied on these IO lines are common to A20, A23, A24, A25 and D25,
D26, D27, D28 respectively.
A[25:0] , controlled by 4 registers DELAY5, DELAY6, DELAY7 and DELAY8 located in the SMC user interface.
A[0] <=> DELAY5[3:0]
A[1] <=> DELAY5[7:4],...,
...
A[14] <=> DELAY6[27:24]
A[15] <=> DELAY6[31:28]
A[16] <=> DELAY7[3:0]
A[17] <=> DELAY7[7:4]
A[18] <=> DELAY7[11:8] and
A19 <=> DELAY7[15:12]
A21 <=> PD[2] <=> DELAY7[23:20]
A22 <=> PD[3] <=> DELAY7[27:24]
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26.5.3.4 Power supplies
The product embeds a dual power supply for EBI: VDDNF for NAND Flash signals and VDDIOM for others. This makes it possible to use a 1.8V or 3.3V NAND Flash independently of the SDRAM power supply.
The switch NFD0_ON_D16 is used to select the NAND Flash path on D0–D15 or D16–D31 depending on memory power supplies. This switch is located in the CCFG_EBICSA register in the Bus Matrix.
same power supply range (NFD0_ON_D16 = default).
Figure 26-2. NAND Flash and External RAM in Same Power Supply Range (NFD0_ON_D16 = default)
D[15:0]
DDR2 or
LP-DDR or
16-bit LP-SDR (1.8V)
D[15:0]
EBI
A[22:21]
NAND Flash (1.8V)
D[15:0]
ALE
CLE
D[15:0]
D[31:16]
A[22:21]
32bit SDRAM (3.3V)
D[15:0]
D[31:16]
NAND Flash (3.3V)
D[15:0]
ALE
CLE
EBI
not in the same power supply range (NFD0_ON_D16 = 1).
This can be used if the SMC connects to the NAND Flash only. Using this function with another device on the SMC will lead to an unpredictable behavior of that device. In that case, the default value must be selected.
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Figure 26-3. NAND Flash and External RAM Not in Same Power Supply Range (NFD0_ON_D16 = 1)
D[15:0]
DDR2 or
LP-DDR or
16-bit LP-SDR (1.8V)
D[15:0]
EBI
D[31:16]
A[22:21]
NAND Flash (3.3V)
D[15:0]
ALE
CLE
At reset NFD0_ON_D16 = 0 and the NAND Flash bus is connected to D0–D15.
26.5.3.5 Static Memory Controller
For information on the Static Memory Controller, refer to the Static Memory Controller section of this datasheet.
26.5.3.6 DDR2SDRAM Controller
The product embeds a multi-port DDR2SDR Controller. This allows to use three additional ports on DDR2SDRC to lessen the EBI load from a part of DDR2 or LP-DDR accesses. This increases the bandwidth when DDR2 and NAND
Flash devices are used. This feature is NOT compatible with SDR or LP-SDR Memory.
It is controlled by DDR_MP_EN bit in EBI Chip Select Assignment Register.
Figure 26-4. DDR2SDRC Multi-port Enabled (DDR_MP_EN = 1)
DDR2SDRC
Port 3
Port 2
Port 1
DDR2 or LP-DDR
Device
Bus Matrix
Port 0
NAND Flash
Device
EBI
Figure 26-5. DDR2SDRC Multi-port Disabled (DDR_MP_EN = 0)
DDR2SDRC not used not used not used
Bus Matrix
Port 0
(LP-)SDR
Device
NAND Flash
Device
EBI
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26.5.3.7 Programmable Multibit ECC Controller
For information on the PMECC Controller, refer to PMECC and PMERRLOC sections; also refer to Boot Strategies
Section, NAND Flash Boot: PMECC Error Detection and Correction.
26.5.3.8 NAND Flash Support
External Bus Interfaces integrate circuitry that interfaces to NAND Flash devices.
External Bus Interface
The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the
EBI_CSA field in the EBI_CSA Register in the Chip Configuration User Interface to the appropriate value enables the
NAND Flash logic.
For details on this register, refer to the Bus Matrix section. Access to an external NAND Flash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the
NCS3 address space. See Figure 26-6
for more information. For details on these waveforms, refer to the Static Memory
Controller section.
NAND Flash Signals
The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode.
Figure 26-6. NAND Flash Application Example
D[7:0]
A[22:21]
AD[7:0]
ALE
CLE
NCSx/NANDCS
Not Connected
EBI
NAND Flash
NANDOE
NANDWE
NOE
NWE
PIO
PIO
CE
R/B
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26.5.4 Implementation Examples
The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability.
26.5.4.1 2x8-bit DDR2 on EBI
Hardware Configuration
Software Configuration
Assign EBI_CS1 to the DDR2 controller by setting the EBI_CS1A bit in the EBI Chip Select Assignment Register
(CCFG_EBICSA) in the Bus Matrix.
Initialize the DDR2 Controller depending on the DDR2 device and system bus frequency.
The DDR2 initialization sequence is described in the subsection “DDR2 Device Initialization” of the DDRSDRC section.
In this case VDDNF can be different from VDDIOM. NAND Flash device can be 3.3V or 1.8V and wired on D16–D31 data bus. NFD0_ON_D16 is to be set to 1.
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26.5.4.2 16-bit LPDDR on EBI
Hardware Configuration
Software Configuration
The following configuration has to be performed:
Assign EBI_CS1 to the DDR2 controller by setting the bit EBI_CS1A bit in the EBI Chip Select Assignment
Register (CCFG_EBICSA) in the Bus Matrix.
Initialize the DDR2 Controller depending on the LP-DDR device and system bus frequency.
The LP-DDR initialization sequence is described in the section “Low-power DDR1-SDRAM Initialization” in “DDR/SDR
SDRAM Controller (DDRSDRC)”.
In this case VDDNF can be different from VDDIOM. NAND Flash device can be 3.3V or 1.8V and wired on D16–D31 data bus. NFD0_ON_D16 is to be set to 1.
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26.5.4.3 16-bit SDRAM on EBI
Hardware Configuration
Software Configuration
The following configuration has to be performed:
Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A bit in the EBI Chip Select Assignment
Register (CCFG_EBICSA) in the Bus Matrix.
Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
The Data Bus Width is to be programmed to 16 bits.
The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in “SDRAM Controller
(SDRAMC)”.
In this case VDDNF can be different from VDDIOM. NAND Flash device can be 3.3V or 1.8V and wired on D16–D31 data bus. NFD0_ON_D16 is to be set to 1.
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26.5.4.4 2x16-bit SDRAM on EBI
Hardware Configuration
A[1..14]
D[0..31]
SDRAM
20
21
36
40
37
38
15
39
17
18
29
30
31
32
23
24
25
26
33
34
22
35
A0
A5
A6
A7
A8
A1
A2
A3
A4
A9
A10
A11
BA0
BA1
A12
N.C1
CKE
CLK
DQML
DQMH
CAS
RAS
16
19
WE
CS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
8
10
11
13
2
4
5
7
42
44
45
47
48
50
51
53
28
41
54
6
12
46
52
1
14
27
3
9
43
49
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VDDIOM
256 Mbits
SDCS
VDDIOM
CKE
CLK
DQM0
DQM1
CAS
RAS
WE
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
SDA10
A13
BA0
BA1
A14
VDDIOM
CKE
CLK
DQM2
DQM3
CAS
RAS
WE
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
SDA10
A13
BA0
BA1
A14
29
30
31
32
23
24
25
26
33
34
22
35
20
21
BA0
BA1
36
40
17
18
A12
N.C1
37
15
39
CKE
38
CLK
DQML
DQMH
CAS
RAS
A0
A5
A6
A7
A8
A1
A2
A3
A4
A9
A10
A11
16
19
WE
CS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
8
10
11
13
2
4
5
7
42
44
45
47
48
50
51
53
28
41
54
6
12
46
52
1
14
27
3
9
43
49
256 Mbits
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
VDDIOM
Software Configuration
The following configuration has to be performed:
Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A bit in the EBI Chip Select Assignment
Register (CCFG_EBICSA) in the Bus Matrix.
Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
The Data Bus Width is to be programmed to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller.
The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in “SDRAM Controller
(SDRAMC)”.
In this case VDDNF must to be equal to VDDIOM. The NAND Flash device must be 3.3V and wired on D0–D15 data bus.
NFD0_ON_D16 is to be set to 0.
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26.5.4.5 8-bit NAND Flash with NFD0_ON_D16 = 0
Hardware Configuration
D[0..7]
CLE
ALE
NANDOE
NANDWE
(ANY PIO)
(ANY PIO)
3V3
16
17
8
18
9
7
19
10
11
14
15
4
5
6
1
2
3
20
21
22
23
24
25
26
CLE
ALE
RE
WE
CE
R/B
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
VCC
VCC
VSS
VSS
2 Gb
TSOP48 PACKAGE
N.C
N.C
N.C
N.C
N.C
N.C
PRE
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
29
30
31
32
41
42
43
44
48
47
46
45
40
39
38
35
34
33
28
27
37
12
36
13
D0
D1
D2
D3
D4
D5
D6
D7
3V3
Software Configuration
The following configuration has to be performed:
Set NFD0_ON_D16 = 0 in the EBI Chip Select Assignment Register located in the bus matrix memory space
Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register
Reserve A21/A22 for ALE/CLE functions. Address and Command Latches are controlled respectively by setting to
1 the address bits A21 and A22 during accesses.
Configure a PIO line as an input to manage the Ready/Busy signal.
Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency.
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26.5.4.6 16-bit NAND Flash with NFD0_ON_D16 = 0
Hardware Configuration
D[0..15]
CLE
ALE
NANDOE
NANDWE
(ANY PIO)
(ANY PIO)
3V3
16
17
8
18
9
7
19
14
15
20
21
22
23
24
34
35
1
10
11
4
5
6
2
3
CLE
ALE
RE
WE
CE
R/B
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
PRE
N.C
VCC
VCC
VSS
VSS
VSS
2 Gb
TSOP48 PACKAGE
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O12
I/O13
I/O14
I/O15
44
46
27
29
31
33
41
43
45
47
26
28
30
32
40
42
39
38
36
37
12
48
25
13
D8
D9
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
3V3
Software Configuration
The software configuration is the same as for an 8-bit NAND Flash except for the data bus width programmed in the mode register of the Static Memory Controller.
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26.5.4.7 8-bit NAND Flash with NFD0_ON_D16 = 1
Hardware Configuration
Software Configuration
The following configuration has to be performed:
Set NFD0_ON_D16 = 1 in the EBI Chip Select Assignment Register in the Bus Matrix.
Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register
Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled respectively by setting to 1 the address bit A21 and A22 during accesses.
Configure a PIO line as an input to manage the Ready/Busy signal.
Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency.
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26.5.4.8 16-bit NAND Flash with NFD0_ON_D16 = 1
Hardware Configuration
Software Configuration
The software configuration is the same as for an 8-bit NAND Flash except for the data bus width programmed in the mode register of the Static Memory Controller.
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26.5.4.9 NOR Flash on NCS0
Hardware Configuration
D[0..15]
A[1..22]
NRST
NWE
NCS0
NRD
3V3
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A5
A6
A7
A8
A9
A1
A2
A3
A4
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A4
A5
A6
A7
A0
A1
A2
A3
1
48
17
3
2
5
4
18
8
7
6
16
15
10
9
25
24
23
22
21
20
19
12
11
14
13
26
28
RESET
WE
WP
VPP
CE
OE
VCCQ
47
VCC
37
VSS
VSS
46
27
TSOP48 PACKAGE
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
36
39
41
43
45
44
30
32
34
29
31
33
35
38
40
42
D9
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
3V3
C2
100NF
Software Configuration
The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by
Chip Select, allows boot on 16-bit non-volatile memory at slow clock.
For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on
Flash timings and system bus frequency.
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27.
Programmable Multibit ECC Controller (PMECC)
27.1 Description
The Programmable Multibit ECC Controller (PMECC) is a programmable binary BCH (Bose, Chaudhuri and
Hocquenghem) encoder/decoder. This controller can be used to generate redundancy information for both Single-Level
Cell (SLC) and Multi-level Cell (MLC) NAND Flash devices. It supports redundancy for correction of 2, 4, 8, 12 or 24 bits of error per sector of data.
27.2 Embedded Characteristics
8-bit Nand Flash Data Bus Support
Multibit Error Correcting Code.
Algorithm based on binary shortened Bose, Chaudhuri and Hocquenghem (BCH) codes.
Programmable Error Correcting Capability: 2, 4, 8, 12 and 24 bit of errors per sector.
Programmable Sector Size: 512 bytes or 1024 bytes.
Programmable Number of Sectors per page: 1, 2, 4 or 8 sectors of data per page.
Programmable Spare Area Size.
Supports Spare Area ECC Protection.
Supports 8 Kbytes page size using 1024 bytes per sector and 4 kbytes page size using 512 bytes per sector.
Configurable through APB interface
Multibit Error Detection is Interrupt Driven.
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27.3 Block Diagram
Figure 27-1. Block Diagram
Static
Memory
Controller
Control Bus
PMECC
Controller
Programmable BCH Algorithm
MLC/SLC
NAND Flash device
8-Bit
Data Bus
User Interface
APB
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27.4 Functional Description
The NAND Flash sector size is programmable and can be set to 512 bytes or 1024 bytes. The PMECC module generates redundancy at encoding time, when a NAND write page operation is performed. The redundancy is appended to the page and written in the spare area. This operation is performed by the processor. It moves the content of the
PMECCx registers into the NAND Flash memory. The number of registers depends on the selected error correction capability, refer to
Table 27-1 on page 320 . This operation is executed for each sector. At decoding time, the PMECC
module generates the remainder of the received codeword by minimal polynomials. When all polynomial remainders for a given sector are set to zero, no error occurred. When the polynomial remainders are other than zero, the codeword is corrupted and further processing is required.
The PMECC module generates an interrupt indicating that an error occurred. The processor must read the PMECCISR register. This register indicates which sector is corrupted.
To find the error location within a sector, the processor must execute the decoding steps as follows:
1.
Syndrome computation
2.
Find the error locator polynomials
3.
Find the roots of the error locator polynomial
All decoding steps involve finite field computation. It means that a library of finite field arithmetic must be available to perform addition, multiplication and inversion. The finite field arithmetic operations can be performed through the use of a memory mapped lookup table, or direct software implementation. The software implementation presented is based on lookup tables. Two tables named gf_log and gf_antilog are used. If alpha is the primitive element of the field, then a power of alpha is in the field. Assume beta = alpha ^ index, then beta belongs to the field, and gf_log(beta) = gf_log(alpha
^ index) = index. The gf_antilog tables provide exponent inverse of the element, if beta = alpha ^ index, then gf_antilog(index) = beta.
The first step consists of the syndrome computation. The PMECC module computes the remainders and software must substitute the power of the primitive element.
.
The second step is the most software intensive. It is the Berlekamp’s iterative algorithm for finding the error-location polynomial.
.
The Last step is finding the root of the error location polynomial. This step can be very software intensive. Indeed, there is no straightforward method of finding the roots, except by evaluating each element of the field in the error location polynomial. However a hardware accelerator can be used to find the roots of the polynomial. The Programmable Multibit
Error Correction Code Location (PMERRLOC) module provides this kind of hardware acceleration.
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Figure 27-2. Software/Hardware Multibit Error Correction Dataflow
NAND Flash
PROGRAM PAGE
Operation
Processor
Software
Configure PMECC : error correction capability sector size/page size
NAND write field set to true spare area desired layout
Move the NAND Page to external Memory whether using DMA or
Copy redundancy from
PMECC user interface to user defined spare area.
using DMA or Processor.
Hardware
Accelerator
PMECC computes redundancy as the data is written into external memory
NAND Flash
READ PAGE
Operation
Software
Configure PMECC : error correction capability sector size/page size
NAND write field set to false spare area desired layout
Hardware
Accelerator
Move the NAND Page from external Memory whether using DMA or
Processor
PMECC computes polynomial remainders as the data is read from external memory
PMECC modules indicate if at least one error is detected.
If a sector is corrupted use the substitute() function to determine the syndromes.
When the table of syndromes is completed, use the get_sigma() function to get the error location polynomial.
Find the error positions finding the roots of the error location polynomial.
And correct the bits.
This step can be hardware assisted using the PMERRLOC module.
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27.4.1 MLC/SLC Write Page Operation using PMECC
When an MLC write page operation is performed, the PMECC controller is configured with the NANDWR field of the
PMECCFG register set to one. When the NAND spare area contains file system information and redundancy (PMECCx), the spare area is error protected, then the SPAREEN bit of the PMECCFG register is set to one. When the NAND spare area contains only redundancy information, the SPAREEN bit is set to zero.
When the write page operation is terminated, the user writes the redundancy in the NAND spare area. This operation can be done with DMA assistance.
Table 27-1. Relevant Redundancy Registers
BCH_ERR field Sector size set to 512 bytes
0 PMECC_ECC0
1
2
3
PMECC_ECC0, PMECC_ECC1
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3,
PMECC_ECC4, PMECC_ECC5,
PMECC_ECC6
4
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3,
PMECC_ECC4, PMECC_ECC5,
PMECC_ECC6, PMECC_ECC7,
PMECC_ECC8, PMECC_ECC9
Sector size set to 1024 bytes
PMECC_ECC0
PMECC_ECC0, PMECC_ECC1
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3,
PMECC_ECC4, PMECC_ECC5,
PMECC_ECC6
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3,
PMECC_ECC4, PMECC_ECC5,
PMECC_ECC6, PMECC_ECC7,
PMECC_ECC8, PMECC_ECC9,
PMECC_ECC10
2
3
4
Table 27-2. Number of relevant ECC bytes per sector, copied from LSbyte to MSbyte
BCH_ERR field Sector size set to 512 bytes Sector size set to 1024 bytes
0
1
4 bytes
7 bytes
4 bytes
7 bytes
13 bytes
20 bytes
39 bytes
14 bytes
21 bytes
42 bytes
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27.4.1.1 SLC/MLC Write Operation with Spare Enable Bit Set
When the SPAREEN field of the PMECC_CFG register is set to one, the spare area of the page is encoded with the stream of data of the last sector of the page. This mode is entered by writing one in the DATA field of the PMECC_CTRL register. When the encoding process is over, the redundancy is written to the spare area in user mode, USER field of the
PMECC_CTRL must be set to one.
Figure 27-3. NAND Write Operation with Spare Encoding
Write NAND operation with SPAREEN set to one pagesize = n * sectorsize sparesize
Sector 0 Sector 1 Sector 2 Sector 3 Spare
512 or 1024 bytes ecc_area start_addr end_addr
ECC computation enable signal
27.4.1.2 MLC/SLC Write Operation with Spare Area Disabled
When the SPAREEN field of PMECC_CFG is set to zero the spare area is not encoded with the stream of data. This mode is entered by writing one to the DATA field of the PMECC_CTRL register.
Figure 27-4. NAND Write Operation
Write NAND operation with SPAREEN set to zero pagesize = n * sectorsize
Sector 2 Sector 3 Sector 0
512 or 1024 bytes
ECC computation enable signal
Sector 1
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27.4.2 MLC/SLC Read Page Operation using PMECC
Table 27-3. Relevant Remainders Registers
BCH_ERR field Sector size set to 512 bytes
0 PMECC_REM0
1
2
3
4
PMECC_REM0, PMECC_REM1
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM4, PMECC_REM5,
PMECC_REM6, PMECC_REM7
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM4, PMECC_REM5,
PMECC_REM6, PMECC_REM7,
PMECC_REM8, PMECC_REM9,
PMECC_REM10, PMECC_REM11
Sector size set to 1024 bytes
PMECC_REM0
PMECC_REM0, PMECC_REM1
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM4, PMECC_REM5,
PMECC_REM6, PMECC_REM7
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM4, PMECC_REM5,
PMECC_REM6, PMECC_REM7,
PMECC_REM8, PMECC_REM9,
PMECC_REM10, PMECC_REM11
27.4.2.1 MLC/SLC Read Operation with Spare Decoding
When the spare area is protected, the spare area contains valid data. As the redundancy may be included in the middle of the information stream, the user programs the start address and the end address of the ECC area. The controller will automatically skip the ECC area. This mode is entered by writing one in the DATA field of the PMECC_CTRL register.
When the page has been fully retrieved from NAND, the ECC area is read using the user mode by writing one to the
USER field of the PMECC_CTRL register.
Figure 27-5. Read Operation with Spare Decoding
Read NAND operation with SPAREEN set to One and AUTO set to Zero pagesize = n * sectorsize sparesize
Sector 0 Sector 1 Sector 2 Sector 3 Spare
512 or 1024 bytes ecc_area start_addr end_addr
Remainder computation enable signal
27.4.2.2 MLC/SLC Read Operation
If the spare area is not protected with the error correcting code, the redundancy area is retrieved directly. This mode is entered by writing one in the DATA field of the PMECC_CTRL register. When AUTO field is set to one the ECC is retrieved automatically, otherwise the ECC must be read using user mode.
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Figure 27-6. Read Operation
Read NAND operation with SPAREEN set to Zero and AUTO set to One pagesize = n * sectorsize
Sector 1 Sector 2 Sector 0
512 or 1024 bytes
Sector 3 sparesize
Spare ecc_area start_addr end_addr
Remainder computation enable signal
27.4.2.3 MLC/SLC User Read ECC Area
This mode allows a manual retrieve of the ECC.
This mode is entered writing one in the USER field of the PMECC_CTRL register.
Figure 27-7. User Read Mode
ecc_area_size
ECC ecc_area addr = 0 end_addr
Partial Syndrome computation enable signal
27.5 Software Implementation
27.5.1 Remainder Substitution Procedure
The substitute function evaluates the polynomial remainder, with different values of the field primitive elements. The finite field arithmetic addition operation is performed with the Exclusive or. The finite field arithmetic multiplication operation is performed through the gf_log, gf_antilog lookup tables.
The REM2NP1 and REMN2NP3 fields of the PMECC_REMx registers contain only odd remainders. Each bit indicates whether the coefficient of the polynomial remainder is set to zero or not.
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NB_ERROR_MAX defines the maximum value of the error correcting capability.
NB_ERROR defines the error correcting capability selected at encoding/decoding time.
NB_FIELD_ELEMENTS defines the number of elements in the field.
si[] is a table that holds the current syndrome value, an element of that table belongs to the field. This is also a shared variable for the next step of the decoding operation.
oo[] is a table that contains the degree of the remainders.
int substitute()
{ int i; int j; for (i = 1; i < 2 * NB_ERROR_MAX; i++)
{ si[i] = 0;
} for (i = 1; i < 2*NB_ERROR; i++)
{ for (j = 0; j < oo[i]; j++)
{ if (REM2NPX[i][j])
{ si[i] = gf_antilog[(i * j)%NB_FIELD_ELEMENTS] ^ si[i];
}
}
} return 0;
}
27.5.2 Find the Error Location Polynomial Sigma(x)
The sample code below gives a Berlekamp iterative procedure for finding the value of the error location polynomial.
The input of the procedure is the si[] table defined in the remainder substitution procedure.
The output of the procedure is the error location polynomial named smu (sigma mu). The polynomial coefficients belong to the field. The smu[NB_ERROR+1][] is a table that contains all these coefficients.
NB_ERROR_MAX defines the maximum value of the error correcting capability.
NB_ERROR defines the error correcting capability selected at encoding/decoding time.
NB_FIELD_ELEMENTS defines the number of elements in the field.
int get_sigma()
{ int i; int j; int k;
/* mu */ int mu[NB_ERROR_MAX+2];
/* sigma ro */ int sro[2*NB_ERROR_MAX+1];
/* discrepancy */ int dmu[NB_ERROR_MAX+2];
/* delta order */ int delta[NB_ERROR_MAX+2];
/* index of largest delta */ int ro; int largest; int diff;
/* */
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/* First Row */
/* */
/* Mu */ mu[0] = -1; /* Actually -1/2 */
/* Sigma(x) set to 1 */ for (i = 0; i < (2*NB_ERROR_MAX+1); i++) smu[0][i] = 0; smu[0][0] = 1;
/* discrepancy set to 1 */ dmu[0] = 1;
/* polynom order set to 0 */ lmu[0] = 0;
/* delta set to -1 */ delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
/* */
/* Second Row */
/* */
/* Mu */ mu[1] = 0;
/* Sigma(x) set to 1 */ for (i = 0; i < (2*NB_ERROR_MAX+1); i++) smu[1][i] = 0; smu[1][0] = 1;
/* discrepancy set to Syndrome 1 */ dmu[1] = si[1];
/* polynom order set to 0 */ lmu[1] = 0;
/* delta set to 0 */ delta[1] = (mu[1] * 2 - lmu[1]) >> 1; for (i=1; i <= NB_ERROR; i++)
{ mu[i+1] = i << 1;
/*************************************************/
/* */
/* */
/* Compute Sigma (Mu+1) */
/* And L(mu) */
/* check if discrepancy is set to 0 */ if (dmu[i] == 0)
{
/* copy polynom */ for (j=0; j<2*NB_ERROR_MAX+1; j++)
{ smu[i+1][j] = smu[i][j];
}
/* copy previous polynom order to the next */ lmu[i+1] = lmu[i];
} else
{ ro = 0; largest = -1;
/* find largest delta with dmu != 0 */ for (j=0; j<i; j++)
{ if (dmu[j])
{ if (delta[j] > largest)
{ largest = delta[j]; ro = j;
}
}
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}
/* initialize signal ro */ for (k = 0; k < 2*NB_ERROR_MAX+1; k ++)
{ sro[k] = 0;
}
/* compute difference */ diff = (mu[i] - mu[ro]);
/* compute X ^ (2(mu-ro)) */ for (k = 0; k < (2*NB_ERROR_MAX+1); k ++)
{ sro[k+diff] = smu[ro][k];
}
/* multiply by dmu * dmu[ro]^-1 */ for (k = 0; k < 2*NB_ERROR_MAX+1; k ++)
{
/* dmu[ro] is not equal to zero by definition */
/* check that operand are different from 0 */ if (sro[k] && dmu[i])
{
/* galois inverse */ sro[k] = gf_antilog[(gf_log[dmu[i]] + (NB_FIELD_ELEMENTSgf_log[dmu[ro]]) + gf_log[sro[k]]) % NB_FIELD_ELEMENTS];
}
}
/* multiply by dmu * dmu[ro]^-1 */ for (k = 0; k < 2*NB_ERROR_MAX+1; k++)
{ smu[i+1][k] = smu[i][k] ^ sro[k]; if (smu[i+1][k])
{
/* find the order of the polynom */ lmu[i+1] = k << 1;
}
}
}
/* */
/* */
/* End Compute Sigma (Mu+1) */
/* And L(mu) */
/*************************************************/
/* In either case compute delta */ delta[i+1] = (mu[i+1] * 2 - lmu[i+1]) >> 1;
/* In either case compute the discrepancy */ for (k = 0 ; k <= (lmu[i+1]>>1); k++)
{ if (k == 0) dmu[i+1] = si[2*(i-1)+3];
/* check if one operand of the multiplier is null, its index is -1 */ else if (smu[i+1][k] && si[2*(i-1)+3-k]) dmu[i+1] = gf_antilog[(gf_log[smu[i+1][k]] + gf_log[si[2*(i-1)+3-k]])%nn]
^ dmu[i+1];
}
} return 0;
}
27.5.3 Find the Error Position
The output of the get_sigma() procedure is a polynomial stored in the smu[NB_ERROR+1][] table. The error position is the roots of that polynomial. The degree of this polynomial is very important information, as it gives the number of errors.
The PMERRLOC module provides a hardware accelerator for this step.
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27.6 Programmable Multibit ECC Controller (PMECC) User Interface
Table 27-4. Register Mapping
Offset
0x00000000
0x00000004
0x00000008
0x0000000C
0x00000010
0x00000014
Register
PMECC Configuration Register
PMECC Spare Area Size Register
PMECC Start Address Register
PMECC End Address Register
PMECC Clock Control Register
PMECC Control Register
0x00000018
0x0000001C
0x00000020
0x00000024
PMECC Status Register
PMECC Interrupt Enable register
PMECC Interrupt Disable Register
PMECC Interrupt Mask Register
0x00000028
0x0000002C
PMECC Interrupt Status Register
Reserved
0x040+sec_num*(0x40)+0x00 PMECC ECC 0 Register
0x040+sec_num*(0x40)+0x04 PMECC ECC 1 Register
0x040+sec_num*(0x40)+0x08 PMECC ECC 2 Register
0x040+sec_num*(0x40)+0x0C PMECC ECC 3 Register
0x040+sec_num*(0x40)+0x10 PMECC ECC 4 Register
0x040+sec_num*(0x40)+0x14 PMECC ECC 5 Register
0x040+sec_num*(0x40)+0x18 PMECC ECC 6 Register
0x040+sec_num*(0x40)+0x1C PMECC ECC 7 Register
0x040+sec_num*(0x40)+0x20 PMECC ECC 8 Register
0x040+sec_num*(0x40)+0x24 PMECC ECC 9 Register
0x040+sec_num*(0x40)+0x28 PMECC ECC 10 Register
0x240+sec_num*(0x40)+0x00 PMECC REM 0 Register
0x240+sec_num*(0x40)+0x04 PMECC REM 1 Register
0x240+sec_num*(0x40)+0x08 PMECC REM 2 Register
0x240+sec_num*(0x40)+0x0C PMECC REM 3 Register
0x240+sec_num*(0x40)+0x10 PMECC REM 4 Register
0x240+sec_num*(0x40)+0x14 PMECC REM 5 Register
0x240+sec_num*(0x40)+0x18 PMECC REM 6 Register
0x240+sec_num*(0x40)+0x1C PMECC REM 7 Register
0x240+sec_num*(0x40)+0x20 PMECC REM 8 Register
0x240+sec_num*(0x40)+0x24 PMECC REM 9 Register
PMECC_ECC2
PMECC_ECC3
PMECC_ECC4
PMECC_ECC5
PMECC_ECC6
PMECC_ECC7
PMECC_ECC8
PMECC_ECC9
PMECC_ECC10
PMECC_REM0
PMECC_REM1
PMECC_REM2
PMECC_REM3
PMECC_REM4
PMECC_REM5
PMECC_REM6
PMECC_REM7
PMECC_REM8
PMECC_REM9
Name
PMECC_CFG
PMECC_SAREA
PMECC_SADDR
PMECC_EADDR
PMECC_CLK
PMECC_CTRL
PMECC_SR
PMECC_IER
PMECC_IDR
PMECC_IMR
PMECC_ISR
–
PMECC_ECC0
PMECC_ECC1
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Access
Read-write
Read-write
Read-write
Read-write
Read-write
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
–
Read-only
Read-only
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
–
0x00000000
0x00000000
–
0x00000000
0x00000000
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Table 27-4. Register Mapping (Continued)
Offset Register
0x240+sec_num*(0x40)+0x28 PMECC REM 10 Register
0x240+sec_num*(0x40)+0x2C PMECC REM 11 Register
0x440 - 0x5FC Reserved –
Name
PMECC_REM10
PMECC_REM11
Access
Read-only
Read-only
–
Reset
0x00000000
0x00000000
–
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27.6.1 PMECC Configuration Register
Name: PMECC_CFG
Address:
Access:
Reset:
0xFFFFE000
Read-write
0x00000000
31
–
23
–
15
30
–
22
–
14
29
–
21
–
13
7
–
6
–
5
–
28
–
20
AUTO
12
NANDWR
4
SECTORSZ
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
• BCH_ERR: Error Correct Capability
3
4
1
2
Value
0
Name
BCH_ERR2
BCH_ERR4
BCH_ERR8
BCH_ERR12
BCH_ERR24
Description
2 errors
4 errors
8 errors
12 errors
24 errors
• SECTORSZ: Sector Size
0: The ECC computation is based on a sector of 512 bytes.
1: The ECC computation is based on a sector of 1024 bytes.
• PAGESIZE: Number of Sectors in the Page
1
2
Value
0
3
Name
PAGESIZE_1SEC
PAGESIZE_2SEC
PAGESIZE_4SEC
PAGESIZE_8SEC
Description
1 sector for main area (512 or 1024 bytes)
2 sectors for main area (1024 or 2048 bytes)
4 sectors for main area (2048 or 4096 bytes)
8 errors for main area (4096 or 8192 bytes)
• NANDWR: NAND Write Access
:0: NAND read access
1: NAND write access
• SPAREEN: Spare Enable
– for NAND write access:
0: The spare area is skipped
1: The spare area is protected with the last sector of data.
– for NAND read access:
0: The spare area is skipped.
1: The spare area contains protected data or only redundancy information.
25
–
17
–
9
24
–
16
SPAREEN
8
PAGESIZE
1
BCH_ERR
0
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• AUTO: Automatic Mode Enable
This bit is only relevant in NAND Read Mode, when spare enable is activated.
0: Indicates that the spare area is not protected. In that case the ECC computation takes into account the ECC area located in the spare area. (within the start address and the end address).
1: Indicates that the spare is error protected. In this case, the ECC computation takes into account the whole spare area minus the ECC area in the ECC computation operation.
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27.6.2 PMECC Spare Area Size Register
Name: PMECC_SAREA
Address: 0xFFFFE004
Access: Read-write
Reset: 0x00000000
31
–
23
–
15
–
7
30
–
22
–
14
–
6
29
–
21
–
13
–
5
• SPARESIZE: Spare Area Size
The spare area size is equal to (SPARESIZE+1) bytes.
28
–
20
–
12
–
4
SPARESIZE
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
SPARESIZE
0
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27.6.3 PMECC Start Address Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
PMECC_SADDR
0xFFFFE008
Read-write
0x00000000
30
–
22
–
14
–
6
29
–
21
–
13
–
5
28
–
20
–
12
–
4
STARTADDR
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
• STARTADDR: ECC Area Start Address (byte oriented address)
This field indicates the first byte address of the ECC area. Location 0 matches the first byte of the spare area.
24
–
16
–
8
STARTADDR
0
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27.6.4 PMECC End Address Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
7
PMECC_EADDR
0xFFFFE00C
Read-write
0x00000000
30
–
22
–
14
6
29
–
21
–
13
5
28
–
20
–
12
27
–
19
–
11
4
ENDADDR
3
• ENDADDR: ECC Area End Address (byte oriented address)
This field indicates the last byte address of the ECC area.
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
–
8
ENDADDR
0
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27.6.5 PMECC Clock Control Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
PMECC_CLK
0xFFFFE010
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
25
–
17
–
9
–
1
CLKCTRL
24
–
16
–
8
–
0
• CLKCTRL: Clock Control Register
The PMECC Module data path Setup Time is set to CLKCTRL+1.
This field indicates the database setup times in number of clock cycles. At 133 MHz, this field must be programmed with 2, indicating that the setup time is 3 clock cycles.
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27.6.6 PMECC Control Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
PMECC_CTRL
0xFFFFE014
Write-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
DISABLE
28
–
20
–
12
–
4
ENABLE
27
–
19
–
11
–
3
–
• RST: Reset the PMECC Module
When set to one, this bit reset PMECC controller, configuration registers remain unaffected.
• DATA: Start a Data Phase
• USER: Start a User Mode Phase
• ENABLE: PMECC Module Enable
PMECC module must always be configured before being activated.
• DISABLE: PMECC Module Disable
PMECC module must always be configured after being deactivated.
26
–
18
–
10
–
2
USER
25
–
17
–
9
–
1
DATA
24
–
16
–
8
–
0
RST
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27.6.7 PMECC Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
PMECC_SR
0xFFFFE018
Read-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
ENABLE
27
–
19
–
11
–
3
–
• BUSY: The Kernel of the PMECC is Busy
• ENABLE: PMECC Module Status
0: The PMECC Module is disabled and can be configured.
1: The PMECC Module is enabled and the configuration registers cannot be written.
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
BUSY
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27.6.8 PMECC Interrupt Enable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
PMECC_IER
0xFFFFE01C
Write-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
• ERRIE: Error Interrupt Enable
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
ERRIE
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27.6.9 PMECC Interrupt Disable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
PMECC_IDR
0xFFFFE020
Write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
• ERRID: Error Interrupt Disable
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
ERRID
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27.6.10 PMECC Interrupt Mask Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
PMECC_IMR
0xFFFFE024
Read-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
• ERRIM: Error Interrupt Enable
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
ERRIM
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27.6.11 PMECC Interrupt Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
PMECC_ISR
0xFFFFE028
Read-only
0x00000000
30
–
22
–
14
–
6
29
–
21
–
13
–
5
28
–
20
–
12
–
4
ERRIS
27
–
19
–
11
–
3
• ERRIS: Error Interrupt Status Register
When set to one, bit i of the PMECCISR register indicates that sector i is corrupted.
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
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27.6.12 PMECC ECC x Register
Name:
Address:
Access:
Reset:
PMECC_ECCx [x=0..10] [sec_num=0..7]
0xFFFFE040 [0][0] .. 0xFFFFE068 [10][0]
0xFFFFE080 [0][1] .. 0xFFFFE0A8 [10][1]
0xFFFFE0C0 [0][2] .. 0xFFFFE0E8 [10][2]
0xFFFFE100 [0][3] .. 0xFFFFE128 [10][3]
0xFFFFE140 [0][4] .. 0xFFFFE168 [10][4]
0xFFFFE180 [0][5] .. 0xFFFFE1A8 [10][5]
0xFFFFE1C0 [0][6] .. 0xFFFFE1E8 [10][6]
0xFFFFE200 [0][7] .. 0xFFFFE228 [10][7]
Read-only
0x00000000
31 30 29 28
23
15
7
22
14
6
21
13
5
20
12
4
ECC
ECC
ECC
ECC
11
3
27
19
10
2
26
18
• ECC: BCH Redundancy
This register contains the remainder of the division of the codeword by the generator polynomial.
9
1
25
17
8
0
24
16
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27.6.13 PMECC Remainder x Register
Name:
Address:
PMECC_REMx [x=0..11] [sec_num=0..7]
0xFFFFE240 [0][0] .. 0xFFFFE26C [11][0]
0xFFFFE280 [0][1] .. 0xFFFFE2AC [11][1]
0xFFFFE2C0 [0][2] .. 0xFFFFE2EC [11][2]
0xFFFFE300 [0][3] .. 0xFFFFE32C [11][3]
0xFFFFE340 [0][4] .. 0xFFFFE36C [11][4]
0xFFFFE380 [0][5] .. 0xFFFFE3AC [11][5]
0xFFFFE3C0 [0][6] .. 0xFFFFE3EC [11][6]
0xFFFFE400 [0][7] .. 0xFFFFE42C [11][7]
Access: Read-only
Reset: 0x00000000
31
–
23
30
–
22
29
21
28
20
15
–
7
14
–
6
13
5
12
4
REM2NP3
27
REM2NP3
26
19 18
11
REM2NP1
10
3 2
REM2NP1
9
1
25
17
• REM2NP1: BCH Remainder 2 * N + 1
When sector size is set to 512 bytes, bit REM2NP1[13] is not used and read as zero.
If bit i of the REM2NP1 field is set to one then the coefficient of the X ^ i is set to one, otherwise the coefficient is zero.
• REM2NP3: BCH Remainder 2 * N + 3
When sector size is set to 512 bytes, bit REM2NP3[29] is not used and read as zero.
If bit i of the REM2NP3 field is set to one then the coefficient of the X ^ i is set to one, otherwise the coefficient is zero.
8
0
24
16
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28.
Programmable Multibit ECC Error Location Controller (PMERRLOC)
28.1 Description
The PMECC Error Location Controller provides hardware acceleration for determining roots of polynomials over two finite fields: GF(2^13) and GF(2^14). It integrates 24 fully programmable coefficients. These coefficients belong to GF(2^13) or
GF(2^14). The coefficient programmed in the PMERRLOC_SIGMAx register is the coefficient of degree x in the polynomial.
28.2 Embedded Characteristics
Provides Hardware Acceleration for determining roots of polynomials defined over a finite field
Programmable Finite Field GF(2^13) or GF(2^14)
Finds Roots of Error Locator Polynomial
Programmable Number of Roots
28.3 Block Diagram
Figure 28-1. Block Diagram
PMECC Error Location
Controller
Programmable Searching Circuit
User Interface
APB
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28.4 Functional Description
The PMERRLOC search operation is started as soon as a write access is detected in the ELEN register and can be disabled by writing to the ELDIS register. The ENINIT field of the ELEN register shall be initialized with the number of
Galois field elements to test. The set of the roots can be limited to a valid range.
Table 28-1. ENINIT field value for a sector size of 512 bytes
Error Correcting Capability
2
ENINIT Value
4122
12
24
4
8
4148
4200
4252
4408
Table 28-2. ENINIT field value for a sector size of 1024 bytes
Error Correcting Capability ENINIT Value
2
4
8220
8248
8
12
24
8304
8360
8528
When the PMEERRLOC engine is searching for roots the BUSY field of the ELSR remains asserted. An interrupt is asserted at the end of the computation, and the DONE bit of the ELSIR register is set. The ERR_CNT field of the ELISR indicates the number of errors. The error position can be read in the PMERRLOCx registers.
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28.5 Programmable Multibit ECC Error Location Controller (PMERRLOC) User Interface
Table 28-3. Register Mapping
Offset Register
0x000 Error Location Configuration Register
0x004
0x008
0x00C
0x010
Error Location Primitive Register
Error Location Enable Register
Error Location Disable Register
Error Location Status Register
0x014
0x018
0x01C
0x020
0x024
0x028
...
0x088
0x08C
...
0x0E4
0xE8 - 0X1FC
Error Location Interrupt Enable register
Error Location Interrupt Disable Register
Error Location Interrupt Mask Register
Error Location Interrupt Status Register
Reserved
PMECC SIGMA 0 Register
...
PMECC SIGMA 24 Register
PMECC Error Location 0 Register
...
PMECC Error Location 23 Register
Reserved
Name
PMERRLOC_ELCFG
PMERRLOC_ELPRIM
PMERRLOC_ELEN
PMERRLOC_ELDIS
PMERRLOC_ELSR
PMERRLOC_ELIER
PMERRLOC_ELIDR
PMERRLOC_ELIMR
PMERRLOC_ELISR
–
PMERRLOC_SIGMA0
...
PMERRLOC_SIGMA24
PMERRLOC_EL0
...
PMERRLOC_EL23
–
Access
Read-write
Read-only
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
Read-only
–
Read-write
...
Read-write
Read-only
...
Read-only
–
Reset
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
–
0x00000000
...
0x00000000
0x00000000
...
0x00000000
–
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28.5.1 Error Location Configuration Register
Name: PMERRLOC_ELCFG
Address: 0xFFFFE600
Access: Read-write
Reset: 0x00000000
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
12
–
4
–
28
–
20
• ERRNUM: Number of Errors
• SECTORSZ: Sector Size
0: The ECC computation is based on a 512-byte sector.
1: The ECC computation is based on a 1024-byte sector.
27
–
19
11
–
3
–
26
–
18
ERRNUM
10
–
2
–
25
–
17
1
–
9
–
24
–
16
8
–
0
SECTORSZ
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28.5.2 Error Location Primitive Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
PMERRLOC_ELPRIM
0xFFFFE604
Read-only
0x00000000
30
–
22
–
14
29
–
21
–
13
7 6 5
• PRIMITIV: Primitive Polynomial
28
–
20
–
12
4
PRIMITIV
27
–
19
–
11
3
PRIMITIV
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
–
8
0
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28.5.3 Error Location Enable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
PMERRLOC_ELEN
0xFFFFE608
Read-write
0x00000000
30
–
22
–
14
–
6
29
–
21
–
13
5
• ENINIT: Initial Number of Bits in the Codeword
28
–
20
–
12
4
ENINIT
27
–
19
–
11
3
ENINIT
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
–
8
0
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28.5.4 Error Location Disable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
PMERRLOC_ELDIS
0xFFFFE60C
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
• DIS: Disable Error Location Engine
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
DIS
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28.5.5 Error Location Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
PMERRLOC_ELSR
0xFFFFE610
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
• BUSY: Error Location Engine Busy
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
BUSY
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28.5.6 Error Location Interrupt Enable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
PMERRLOC_ELIER
0xFFFFE614
Read-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
• DONE: Computation Terminated Interrupt Enable
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
DONE
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28.5.7 Error Location Interrupt Disable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
PMERRLOC_ELIDR
0xFFFFE618
Read-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
• DONE: Computation Terminated Interrupt Disable
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
DONE
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28.5.8 Error Location Interrupt Mask Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
PMERRLOC_ELIMR
0xFFFFE61C
Read-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
• DONE: Computation Terminated Interrupt Mask
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
DONE
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28.5.9 Error Location Interrupt Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
PMERRLOC_ELISR
0xFFFFE620
Read-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
4
–
• DONE: Computation Terminated Interrupt Status
• ERR_CNT: Error Counter Value
27
–
19
–
11
3
–
26
–
18
–
10
ERR_CNT
2
–
25
–
17
–
9
1
–
24
–
16
–
8
0
DONE
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28.5.10 Error Location SIGMAx Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
PMERRLOC_SIGMAx [x=0..24]
0xFFFFE628 [0] .. 0xFFFFE688 [24]
Read-Write
0x00000000
30
–
22
–
14
–
6
29
–
21
–
13
5
28
–
20
–
12
4
SIGMAx
27
–
19
–
11
SIGMAx
3
26
–
18
–
10
2
• SIGMAx: Coefficient of Degree x in the SIGMA Polynomial.
SIGMAx belongs to the finite field GF(2^13) when the sector size is set to 512 bytes.
SIGMAx belongs to the finite field GF(2^14) when the sector size is set to 1024 bytes.
25
–
17
–
9
1
24
–
16
–
8
0
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28.5.11 PMECC Error Locationx Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
PMERRLOC_ELx [x=0..23]
0xFFFFE68C
Read-only
0x00000000
30
–
22
–
14
–
6
29
–
21
–
13
5
28
–
20
–
12
4
ERRLOCN
27
–
19
–
11
ERRLOCN
3
26
–
18
–
10
2
25
–
17
–
9
1
• ERRLOCN: Error Position within the Set {sector area, spare area}.
ERRLOCN points to 0 when the first bit of the main area is corrupted.
If the sector size is set to 512 bytes, the ERRLOCN points to 4096 when the last bit of the sector area is corrupted.
If the sector size is set to 1024 bytes, the ERRLOCN points to 8192 when the last bit of the sector area is corrupted.
If the sector size is set to 512 bytes, the ERRLOCN points to 4097 when the first bit of the spare area is corrupted.
If the sector size is set to 1024 bytes, the ERRLOCN points to 8193 when the first bit of the spare area is corrupted.
24
–
16
–
8
0
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29.
Static Memory Controller (SMC)
29.1 Description
The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for page size up to 32 bytes.
29.2 Embedded Characteristics
6
Chip Selects Available
64-Mbyte Address Space per Chip Select
8-bit, 16-bit or 32-bit Data Bus
Word, Halfword, Byte Transfers
Byte Write or Byte Select Lines
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
Programmable Data Float Time per Chip Select
Compliant with LCD Module
External Wait Request
Automatic Switch to Slow Clock Mode
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
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29.3 I/O Lines Description
Table 29-1. I/O Line Description
Name Description
NCS[7:0] Static Memory Controller Chip Select Lines
NRD
NWR0/NWE
A0/NBS0
NWR1/NBS1
Read Signal
Write 0/Write Enable Signal
Address Bit 0/Byte 0 Select Signal
Write 1/Byte 1 Select Signal
A1/NWR2/NBS2
NWR3/NBS3
A[25:2]
Address Bit 1/Write 2/Byte 2 Select Signal
Write 3/Byte 3 Select Signal
Address Bus
NWAIT External Wait Signal
Type
Output
Output
Output
Output
Output
Output
Output
Output
I/O
Input
Active Level
Low
Low
Low
Low
Low
Low
Low
Low
29.4 Multiplexed Signals
Table 29-2. Static Memory Controller (SMC) Multiplexed Signals
Multiplexed Signals Related Function
NWR0
A0
NWR1
NWE
NBS0
NBS1
Byte-write or byte-select access, see
8-bit or 16-/32-bit data bus, see
“Byte Write or Byte Select Access” on page 361
A1
NWR3
NWR2
NBS3
NBS2
Byte-write or byte-select access see
“Byte Write or Byte Select Access” on page 361
8-/16-bit or 32-bit data bus, see
.
Byte-write or byte-select access, see “Byte Write or Byte Select Access” on page 361
Byte-write or byte-select access see
“Byte Write or Byte Select Access” on page 361
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29.5 Application Example
29.5.1 Hardware Interface
Figure 29-1. SMC Connections to Static Memory Devices
D0-D31
A0/NBS0
NWR0/NWE
NWR1/NBS1
A1/NWR2/NBS2
NWR3/NBS3
NCS0
NCS1
NCS2
NCS3
NCS4
NCS5
NCS6
NCS7
D0 - D7
D0 - D7
128K x 8
SRAM
CS
A0 - A16
NRD
NWR0/NWE
OE
WE
A2 - A18
D8-D15
128K x 8
D0-D7
SRAM
CS
A0 - A16
NRD
NWR1/NBS1
OE
WE
A2 - A18
A2 - A25
D16 - D23
128K x 8
SRAM
D0 - D7
CS
A0 - A16
A2 - A18
NRD
A1/NWR2/NBS2
OE
WE
D24-D31
128K x 8
D0-D7
SRAM
CS
A0 - A16
NRD
OE
NWR3/NBS3
WE
A2 - A18
Static Memory
Controller
29.6 Product Dependencies
29.6.1 I/O Lines
The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O Lines of the
SMC are not used by the application, they can be used for other purposes by the PIO Controller.
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29.7 External Memory Mapping
The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory.
If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see
A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory, A[25:2] is used for 32-bit memory.
Figure 29-2. Memory Connections for Eight External Devices
SMC
NCS[0] - NCS[7]
NRD
NWE
A[25:0]
D[31:0]
NCS7
Memory Enable
NCS6
NCS2
NCS5
Memory Enable
Memory Enable
NCS4
NCS3
Memory Enable
Memory Enable
Memory Enable
NCS1
Memory Enable
NCS0
Memory Enable
Output Enable
Write Enable
8 or 16 or 32
A[25:0]
D[31:0] or D[15:0] or
D[7:0]
29.8 Connection to External Devices
29.8.1 Data Bus Width
A data bus width of 8, 16, or 32 bits can be selected for each chip select. This option is controlled by the field DBW in
SMC_MODE (Mode Register) for the corresponding chip select.
Figure 29-3 shows how to connect a 512K x 8-bit memory on NCS2. Figure 29-4
shows how to connect a 512K x 16-bit
memory on NCS2. Figure 29-5 shows two 16-bit memories connected as a single 32-bit memory
29.8.2 Byte Write or Byte Select Access
Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access. This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select.
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Figure 29-3. Memory Connection for an 8-bit Data Bus
D[7:0]
SMC
A[18:2]
A0
A1
NWE
NRD
NCS[2]
Figure 29-4. Memory Connection for a 16-bit Data Bus
SMC
D[15:0]
A[19:2]
A1
NBS0
NBS1
NWE
NRD
NCS[2]
Figure 29-5. Memory Connection for a 32-bit Data Bus
D[31:16]
D[15:0]
A[20:2]
SMC
NBS0
NBS1
NBS2
NBS3
NWE
NRD
NCS[2]
D[7:0]
A[18:2]
A0
A1
Write Enable
Output Enable
Memory Enable
D[15:0]
A[18:1]
A[0]
Low Byte Enable
High Byte Enable
Write Enable
Output Enable
Memory Enable
D[31:16]
D[15:0]
A[18:0]
Byte 0 Enable
Byte 1 Enable
Byte 2 Enable
Byte 3 Enable
Write Enable
Output Enable
Memory Enable
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29.8.2.1 Byte Write Access
Byte write access supports one byte write signal per byte of the data bus and a single read signal.
Note that the SMC does not allow boot in Byte Write Access mode.
For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1
(upper byte) of a 16-bit bus. One single read signal (NRD) is provided.
Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
For 32-bit devices: NWR0, NWR1, NWR2 and NWR3, are the write signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. One single read signal (NRD) is provided.
Byte Write Access is used to connect 4 x 8-bit devices as a 32-bit memory.
Byte Write option is illustrated on
29.8.2.2 Byte Select Access
In this mode, read/write operations can be enabled/disabled at a byte level. One byte-select line per byte of the data bus is provided. One NRD and one NWE signal control read and write.
For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus.
Byte Select Access is used to connect one 16-bit device.
For 32-bit devices: NBS0, NBS1, NBS2 and NBS3, are the selection signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. Byte Select Access is used to connect two 16-bit devices.
Byte Select Access).
Figure 29-6. Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option
D[7:0]
SMC
D[7:0]
D[15:8]
A[24:2]
A1
NWR0
NWR1
NRD
NCS[3]
A[23:1]
A[0]
Write Enable
Read Enable
Memory Enable
D[15:8]
A[23:1]
A[0]
Write Enable
Read Enable
Memory Enable
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29.8.2.3 Signal Multiplexing
Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus
interface, control signals at the SMC interface are multiplexed. Table 29-3
shows signal multiplexing depending on the data bus width and the byte access type.
For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused.
Figure 29-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option)
D[15:0]
SMC
D[15:0]
D[31:16]
A[25:2]
NWE
NBS0
NBS1
NBS2
NBS3
NRD
NCS[3]
A[23:0]
Write Enable
Low Byte Enable
High Byte Enable
Read Enable
Memory Enable
D[31:16]
A[23:0]
Write Enable
Low Byte Enable
High Byte Enable
Read Enable
Memory Enable
Table 29-3. SMC Multiplexed Signal Translation
Signal Name
Device Type 1x32-bit
32-bit Bus
2x16-bit
Byte Access Type (BAT)
NBS0_A0
NWE_NWR0
NBS1_NWR1
NBS2_NWR2_A1
NBS3_NWR3
Byte Select
NBS0
NWE
NBS1
NBS2
NBS3
Byte Select
NBS0
NWE
NBS1
NBS2
NBS3
4 x 8-bit
Byte Write
NWR0
NWR1
NWR2
NWR3
16-bit Bus
1x16-bit 2 x 8-bit
Byte Select
NBS0
Byte Write
NWE
NBS1
A1
NWR0
NWR1
A1
8-bit Bus
1 x 8-bit
A0
NWE
A1
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29.9 Standard Read and Write Protocols
In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..5] chip select lines.
29.9.1 Read Waveforms
The read cycle is shown on Figure 29-8
.
The read cycle starts with the address setting on the memory address bus, i.e.:
{A[25:2], A1, A0} for 8-bit devices
{A[25:2], A1} for 16-bit devices
A[25:2] for 32-bit devices.
Figure 29-8. Standard Read Cycle
MCK
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NRD
NCS
D[31:0]
NRD_SETUP
NCS_RD_SETUP
NRD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_HOLD
NCS_RD_HOLD
29.9.1.1 NRD Waveform
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1.
NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge;
2.
NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge;
3.
NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge.
29.9.1.2 NCS Waveform
Similarly, the NCS signal can be divided into a setup time, pulse length and hold time:
1.
NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge.
2.
NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge;
3.
NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.
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29.9.1.3 Read Cycle
The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to:
NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD
= NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD
All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NRD and NCS timings are coherent, user must define the total read cycle instead of the hold timing.
NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as:
NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE
NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE
29.9.1.4 Null Delay Setup and Hold
If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see
).
Figure 29-9. No Setup, No Hold On NRD and NCS Read Signals
MCK
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NRD
NCS
D[31:0]
NRD_PULSE
NCS_RD_PULSE
NRD_PULSE NRD_PULSE
NCS_RD_PULSE NCS_RD_PULSE
NRD_CYCLE NRD_CYCLE NRD_CYCLE
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29.9.1.5 Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.
29.9.2 Read Mode
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The
READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal of NRD and
NCS controls the read operation.
29.9.2.1 Read is Controlled by NRD (READ_MODE = 1):
PACC after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE must be set to
1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the programmed waveform of NCS may be.
Figure 29-10.READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD
MCK
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NRD
NCS t
PACC
D[31:0]
Data Sampling
29.9.2.2 Read is Controlled by NCS (READ_MODE = 0)
Figure 29-11 shows the typical read cycle of an LCD module. The read data is valid t
PACC after the falling edge of the
NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the
READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of
Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD may be.
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Figure 29-11.READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS
MCK
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NRD
NCS
D[31:0] t
PACC
Data Sampling
29.9.3 Write Waveforms
The write protocol is similar to the read protocol. It is depicted in
. The write cycle starts with the address setting on the memory address bus.
29.9.3.1 NWE Waveforms
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
1.
NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge;
2.
NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge;
3.
NWE_HOLD: The NWE hold time is defined as the hold time of address and data after the NWE rising edge.
The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3.
29.9.3.2 NCS Waveforms
The NCS signal waveforms in write operation are not the same that those applied in read operations, but are separately defined:
1.
NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge.
2.
NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge;
3.
NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.
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Figure 29-12.Write Cycle
MCK
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE
NCS
NWE_SETUP
NCS_WR_SETUP
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_HOLD
NCS_WR_HOLD
29.9.3.3 Write Cycle
The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is equal to:
NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD
= NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as:
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
29.9.3.4 Null Delay Setup and Hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see
Figure 29-13 ). However, for devices that perform write operations on
the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.
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Figure 29-13.Null Setup and Hold Values of NCS and NWE in Write Cycle
MCK
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NCS
D[31:0]
NWE_PULSE
NCS_WR_PULSE
NWE_PULSE NWE_PULSE
NCS_WR_PULSE NCS_WR_PULSE
NWE_CYCLE NWE_CYCLE NWE_CYCLE
29.9.3.5 Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.
29.9.4 Write Mode
The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal controls the write operation.
29.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1)
the pulse and hold steps of the NWE signal. The internal data buffers are switched to output mode after the
NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.
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Figure 29-14.WRITE_MODE = 1. The write operation is controlled by NWE
MCK
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NCS
D[31:0]
29.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0)
the pulse and hold steps of the NCS signal. The internal data buffers are switched to output mode after the
NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.
Figure 29-15.WRITE_MODE = 0. The write operation is controlled by NCS
MCK
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NCS
D[31:0]
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29.9.5 Write Protected Registers
To prevent any single software error that may corrupt SMC behavior, the registers listed below can be write-protected by setting the WPEN bit in the SMC Write Protect Mode Register (SMC_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the SMC Write Protect Status Register
(SMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset after reading the SMC Write Protect Status Register (SMC_WPSR).
List of the write-protected registers:
Section 29.16.1 ”SMC Setup Register”
Section 29.16.2 ”SMC Pulse Register”
Section 29.16.3 ”SMC Cycle Register”
Section 29.16.4 ”SMC MODE Register”
Section 29.16.5 ”SMC DELAY I/O Register”
29.9.6 Coding Timing Parameters
All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to their type.
The SMC_SETUP register groups the definition of all setup parameters:
• NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
• NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
• NRD_CYCLE, NWE_CYCLE
shows how the timing parameters are coded and their permitted range.
Table 29-4. Coding and Range of Timing Parameters
Coded Value setup [5:0] pulse [6:0] cycle [8:0]
Number of Bits
6
7
9
Effective Value
128 x setup[5] + setup[4:0]
256 x pulse[6] + pulse[5:0]
256 x cycle[8:7] + cycle[6:0]
Permitted Range
Coded Value Effective Value
0 ≤ ≤ 31
0 ≤ ≤ 63
0 ≤ ≤ 127
0 ≤ ≤ 128+31
0 ≤ ≤ 256+63
0 ≤ ≤ 256+127
0 ≤ ≤ 512+127
0 ≤ ≤ 768+127
29.9.7 Reset Values of Timing Parameters
Table 29-8, “Register Mapping,” on page 393
gives the default value of timing parameters at reset.
29.9.8 Usage Restriction
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.
For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface because of the propagation delay of theses signals through external logic and pads. If positive setup and hold values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between address, NCS and NRD signals.
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For write operations:
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines, and
For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals
(write), these setup and hold times must be converted into setup and hold times in reference to the address bus.
29.10 Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict.
29.10.1 Chip Select Wait States
The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..5], NRD lines are all set to 1.
Figure 29-16 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.
Figure 29-16.Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NRD
NWE
NCS0
NCS2
NRD_CYCLE NWE_CYCLE
D[31:0]
Read to Write
Wait State
Chip Select
Wait State
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29.10.2 Early Read Wait State
In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is valid:
If the write controlling signal has no hold time and the read controlling signal has no setup time (
).
In NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the
NCS_RD_SETUP parameter is set to 0, regardless of the read mode (
Figure 29-18 ). The write operation must end
with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly.
In NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address,
data and control signals are maintained one more cycle. See Figure 29-19 .
Figure 29-17.Early Read Wait State: Write with No Hold Followed by Read with No Setup
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE
NRD
D[31:0] no hold no setup write cycle Early Read wait state read cycle
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Figure 29-18.Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NCS
NRD
D[31:0] no hold no setup write cycle
(WRITE_MODE = 0)
Early Read wait state read cycle
(READ_MODE = 0 or READ_MODE = 1)
Figure 29-19.Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle
MCK
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1 internal write controlling signal external write controlling signal
(NWE)
NRD
D[31:0] no hold read setup = 1 write cycle
(WRITE_MODE = 1)
Early Read wait state read cycle
(READ_MODE = 0 or READ_MODE = 1)
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29.10.3 Reload User Configuration Wait State
The user may change any of the configuration parameters by writing the SMC user interface.
When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called “Reload User Configuration Wait State” is used by the SMC to load the new set of parameters to apply to next accesses.
The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before and after re-programming the user interface are made to different devices (Chip Selects), then one single Chip Select Wait State is applied.
On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload
Configuration Wait State is inserted, even if the change does not concern the current Chip Select.
29.10.3.1User Procedure
To insert a Reload Configuration Wait State, the SMC detects a write access to any SMC_MODE register of the user interface. If the user only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in the user interface, he must validate the modification by writing the SMC_MODE, even if no change was made on the mode parameters.
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if accesses are performed on this CS during the modification. Any change of the Chip Select parameters, while fetching the code from a memory connected on this CS, may lead to unpredictable behavior. The instructions used to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory connected to another CS.
29.10.3.2Slow Clock Mode Transition
A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the
current transfer (see “Slow Clock Mode” on page 387 ).
29.10.4 Read to Write Wait State
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted.
.
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29.11 Data Float Wait States
Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access:
before starting a read access to a different external memory before starting a write access to the same device or to a different external one.
The Data Float Output Time (t
DF
) for each external memory device is programmed in the TDF_CYCLES field of the
SMC_MODE register for the corresponding chip select. The value of TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long t
DF will not slow down the execution of a program from internal memory.
The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the SMC_MODE register for the corresponding chip select.
29.11.1 READ_MODE
Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts
TDF_CYCLES MCK cycles.
When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS.
illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), assuming a data float period
the TDF_CYCLES parameter equals 3.
Figure 29-20.TDF Period in NRD Controlled Read Access (TDF = 2)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NRD
NCS
D[31:0] tpacc
TDF = 2 clock cycles
NRD controlled read operation
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Figure 29-21.TDF Period in NCS Controlled Read Operation (TDF = 3)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NRD
NCS
D[31:0] tpacc
TDF = 3 clock cycles
NCS controlled read operation
29.11.2 TDF Optimization Enabled (TDF_MODE = 1)
When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0.
Chip Select 0 has been programmed with:
NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
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Figure 29-22.TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins
MCK
A [25:2]
NRD
NRD_HOLD= 4
NWE
NWE_SETUP= 3
NCS0
TDF_CYCLES = 6
D[31:0] read access on NCS0 (NRD controlled)
Read to Write
Wait State write access on NCS0 (NWE controlled)
29.11.3 TDF Optimization Disabled (TDF_MODE = 0)
When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait states will be inserted.
and
Figure 29-25 illustrate the cases:
Read access followed by a read access on another chip select,
Read access followed by a write access on another chip select,
Read access followed by a write access on the same chip select, with no TDF optimization.
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Figure 29-23.TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects
MCK
A[ 25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1 read1 controlling signal
(NRD) read2 controlling signal
(NRD)
D[31:0] read1 hold = 1
TDF_CYCLES = 6 read2 setup = 1
5 TDF WAIT STATES read1 cycle
TDF_CYCLES = 6
Chip Select Wait State
Figure 29-24. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects
MCK read 2 cycle
TDF_MODE = 0
(optimization disabled)
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1 read1 controlling signal
(NRD) write2 controlling signal
(NWE)
D[31:0] read1 hold = 1
TDF_CYCLES = 4 write2 setup = 1 read1 cycle
TDF_CYCLES = 4
Read to Write Chip Select
Wait State Wait State
2 TDF WAIT STATES write2 cycle
TDF_MODE = 0
(optimization disabled)
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Figure 29-25.TDF Mode = 0: TDF wait states between read and write accesses on the same chip select
MCK
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1 read1 controlling signal
(NRD) write2 controlling signal
(NWE)
D[31:0] read1 hold = 1
TDF_CYCLES = 5 write2 setup = 1
4 TDF WAIT STATES read1 cycle
TDF_CYCLES = 5
Read to Write
Wait State write2 cycle
TDF_MODE = 0
(optimization disabled)
29.12 External Wait
Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE field of the SMC_MODE register on the corresponding chip select must be set to either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00” (disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select.
29.12.1 Restriction
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in Page Mode (
“Asynchronous Page Mode” on page 389
), or in Slow Clock Mode (
).
The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior.
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29.12.2 Frozen Mode
When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the
SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See
. This mode must be selected when the external device uses the NWAIT signal to delay the access and to freeze the SMC.
Figure 29-26.Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
MCK
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
4 3 2 1 1
FROZEN STATE
1 1 0
NWE
NCS
D[31:0]
6 5 4 3 2 2 2 2 1 0
NWAIT internally synchronized
NWAIT signal
Write cycle
EXNW_MODE = 10 (Frozen)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
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Figure 29-27.Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
MCK
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NCS
1
4 3
0
2
FROZEN STATE
2 2 1
NRD
NWAIT
5 5 5 4
0
3 internally synchronized
NWAIT signal
2
2
Read cycle
EXNW_MODE = 10 (Frozen)
READ_MODE = 0 (NCS_controlled)
NRD_PULSE = 2, NRD_HOLD = 6
NCS_RD_PULSE =5, NCS_RD_HOLD =3
Assertion is ignored
1
1
0
0
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29.12.3 Ready Mode
In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in
. After deassertion, the access is completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in
Figure 29-28.NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11)
MCK
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
4 3 2 1 0
Wait STATE
0 0
NWE
NCS
6 5 4 3 2 1 1 1 0
D[31:0]
NWAIT internally synchronized
NWAIT signal
Write cycle
EXNW_MODE = 11 (Ready mode)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
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Figure 29-29.NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NCS
6 5 4 3 2 1
6 5 4 3 2
NRD
NWAIT
0
Wait STATE
0
1 1 0 internally synchronized
NWAIT signal
Assertion is ignored
Read cycle
EXNW_MODE = 11(Ready mode)
READ_MODE = 0 (NCS_controlled)
NRD_PULSE = 7
NCS_RD_PULSE =7
Assertion is ignored
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29.12.4 NWAIT Latency and Read/Write Timings
There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting
.
When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read and write controlling signal of at least: minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle
Figure 29-30.NWAIT Latency
MCK
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
4 3 0 0
WAIT STATE
0
NRD
2 1 minimal pulse length
NWAIT intenally synchronized
NWAIT signal
NWAIT latency 2 cycle resynchronization
Read cycle
EXNW_MODE = 10 or 11
READ_MODE = 1 (NRD_controlled)
NRD_PULSE = 5
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29.13 Slow Clock Mode
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate. When activated, the slow mode is active on all chip selects.
29.13.1 Slow Clock Mode Waveforms
indicates the value of read and write parameters in slow clock mode.
Figure 29-31. Read/write Cycles in Slow Clock Mode
MCK MCK
A [25:2] A[ 25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NRD
NWE 1 1
1
1
1
NCS
NCS
NWE_CYCLE = 3
SLOW CLOCK MODE WRITE
NRD_CYCLE = 2
SLOW CLOCK MODE READ
Table 29-5. Read and Write Timing Parameters in Slow Clock Mode
Read Parameters Duration (cycles) Write Parameters Duration (cycles)
NRD_SETUP
NRD_PULSE
NCS_RD_SETUP
NCS_RD_PULSE
NRD_CYCLE
1
1
0
2
2
NWE_SETUP
NWE_PULSE
NCS_WR_SETUP
NCS_WR_PULSE
NWE_CYCLE
1
1
0
3
3
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29.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode
When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.See
. The external device may not be fast enough to support such timings.
Figure 29-33 illustrates the recommended procedure to properly switch from one mode to the other.
Figure 29-32.Clock Rate Transition Occurs while the SMC is Performing a Write Operation
Slow Clock Mode internal signal from PMC
MCK
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NWE
1 1 1 1 1 1 2 3 2
NCS
NWE_CYCLE = 3
SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE
NWE_CYCLE = 7
NORMAL MODE WRITE
This write cycle finishes with the slow clock mode set of parameters after the clock rate transition
Slow clock mode transition is detected:
Reload Configuration Wait State
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Figure 29-33.Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock
Mode
Slow Clock Mode internal signal from PMC
MCK
A [25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NWE
1 1 1 2 3 2
NCS
SLOW CLOCK MODE WRITE IDLE STATE NORMAL MODE WRITE
Reload Configuration
Wait State
29.14 Asynchronous Page Mode
The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the page in memory, the LSB of address define the address of the data in the page as detailed in
With page mode memory devices, the first access to one page (t pa page (t sa
) takes longer than the subsequent accesses to the
) as shown in
Figure 29-34 . When in page mode, the SMC enables the user to define different read timings for
the first access within one page, and next accesses within the page.
Table 29-6. Page Address and Data Address within a Page
Page Size
Data Address in the Page
4 bytes A[25:2] A[1:0]
8 bytes
16 bytes
32 bytes
A[25:3]
A[25:4]
A[25:5]
A[2:0]
A[3:0]
A[4:0]
Notes: 1. A denotes the address bus of the memory device
2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored.
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29.14.1 Protocol and Timings in Page Mode
Figure 29-34 shows the NRD and NCS timings in page mode access.
Figure 29-34.Page Mode Read Protocol (Address MSB and LSB are defined in
MCK
A[MSB]
A[LSB]
NRD
NCS tpa tsa tsa
D[31:0]
NCS_RD_PULSE NRD_PULSE NRD_PULSE
The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesses within the page are defined using the NRD_PULSE parameter.
In page mode, the programming of the read timings is described in
Table 29-7. Programming of Read Timings in Page Mode
Parameter Value Definition
READ_MODE
NCS_RD_SETUP
NCS_RD_PULSE
NRD_SETUP
NRD_PULSE
NRD_CYCLE t pa
‘x’ t sa
‘x’
Access time of first access to the page
No impact
Access time of subsequent accesses in the page
No impact
The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page access timing (t pa
) and the NRD_PULSE for accesses to the page (t sa
), even if the programmed value for t pa
is shorter than the programmed value for t sa
.
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29.14.2 Byte Access Type in Page Mode
The Byte Access Type configuration remains active in page mode. For 16-bit or 32-bit page mode devices that require byte selection signals, configure the BAT field of the SMC_REGISTER to 0 (byte select access type).
29.14.3 Page Mode Restriction
The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal may lead to unpredictable behavior.
29.14.4 Sequential and Non-sequential Accesses
If the chip select and the MSB of addresses as defined in Table 29-6
are identical, then the current access lies in the same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (t sa
).
illustrates access to an 8-bit memory device in page mode, with 8-byte pages. Access to D1 causes a page access with a long access time (t pa
). Accesses to D3 and D7, though they are not sequential accesses, only require a short access time (t sa
).
If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip select is different from the previous access, a page break occurs. If two sequential accesses are made to the page mode memory, but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses.
Figure 29-35. Access to Non-sequential Data within the Same Page
MCK
A [25:3] Page address
A[2], A1, A0 A1 A3 A7
NRD
NCS
D[7:0]
NCS_RD_PULSE
D1
NRD_PULSE
D3
NRD_PULSE
D7
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29.15 Programmable IO Delays
The external bus interface consists of a data bus, an address bus and control signals. The simultaneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines.
In order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, SMC_DELAY1-8.
The additional programmable delays for each IO range from 0 to 4 ns (Worst Case PVT). The delay can differ between
IOs supporting this feature. Delay can be modified per programming for each IO. The minimal additional delay that can be programmed on a PAD suppporting this feature is 1/16 of the maximum programmable delay.
When programming 0x0 in fields “Delay1 to Delay 8”, no delay is added (reset value) and the propagation delay of the pad buffers is the inherent delay of the pad buffer. When programming 0xF in field “Delay1” the propagation delay of the corresponding pad is maximal.
SMC_DELAY1, SMC_DELAY2 allow to configure delay on D[15:0], SMC_DELAY1[3:0] corresponds to D[0] and
SMC_DELAY2[3:0] corresponds to D[8].
SMC_DELAY3, SMC_DELAY4 allow to configure delay on D[31:16], SMC_DELAY3[3:0] corresponds to D[16] and
SMC_DELAY4[3:0] corresponds to D[24]. In case of multiplexing through the PIO controller, refer to the alternate function of D[31:16].
SMC_DELAY5, 6, 7 and 8 allow to configure delay on A[25:0], SMC_DELAY5[3:0] corresponds to A[0]. In case of multiplexing through the PIO controller, refer to the alternate function of A[25:0].
Figure 29-36.Programmable IO Delays
SMC
D_in[0]
D_out[0]
Programmable Delay Line
D[0]
DELAY1
D_in[1]
D_out[1] D[1]
Programmable Delay Line
DELAY2
PIO
D_in[n]
D_out[n]
Programmable Delay Line
D[n]
DELAYx
PIO
DELAYy
A[m]
Programmable Delay Line
A[m]
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29.16 Static Memory Controller (SMC) User Interface
The SMC is programmed using the registers listed in Table 29-8
. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In
Table 29-8 , “CS_number” denotes the chip select number. 16 bytes (0x10)
are required per chip select.
The user must complete writing the configuration by writing any one of the SMC_MODE registers.
Table 29-8. Register Mapping
Offset
0x10 x CS_number + 0x00
0x10 x CS_number + 0x04
0x10 x CS_number + 0x08
0x10 x CS_number + 0x0C
0xC0
0xC4
0xC8
0xCC
0xD0
0xD4
0xD8
0xDC
0xE4
0xE8
0xEC-0xFC
Register Name
SMC Setup Register SMC_SETUP
SMC Pulse Register
SMC Cycle Register
SMC Mode Register
SMC_PULSE
SMC_CYCLE
SMC_MODE
SMC Delay on I/O
SMC Delay on I/O
SMC Delay on I/O
SMC Delay on I/O
SMC Delay on I/O
SMC Delay on I/O
SMC Delay on I/O
SMC Delay on I/O
SMC Write Protect Mode
Register
SMC Write Protect Status
Register
Reserved
SMC_DELAY1
SMC_DELAY2
SMC_DELAY3
SMC_DELAY4
SMC_DELAY5
SMC_DELAY6
SMC_DELAY7
SMC_DELAY8
SMC_WPMR
SMC_WPSR
-
Access
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
-
Reset
0x01010101
0x01010101
0x00030003
0x10001000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
-
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29.16.1 SMC Setup Register
Name:
Address:
Access:
SMC_SETUP[0..
5 ]
0xFFFFEA00 [0], 0xFFFFEA10 [1], 0xFFFFEA20 [2], 0xFFFFEA30 [3], 0xFFFFEA40 [4], 0xFFFFEA50 [5]
Read-write
31
–
30
–
29 28 27 26
NCS_RD_SETUP
25 24
21 20 17 16 23
–
15
–
7
–
22
–
14
–
6
–
13
5
12
4
19
NRD_SETUP
18
11 10
NCS_WR_SETUP
3
NWE_SETUP
2
9
1
8
0
• NWE_SETUP: NWE Setup Length
The NWE signal setup length is defined as:
NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles
• NCS_WR_SETUP: NCS Setup Length in WRITE Access
In write access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles
• NRD_SETUP: NRD Setup Length
The NRD signal setup length is defined in clock cycles as:
NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles
• NCS_RD_SETUP: NCS Setup Length in READ Access
In read access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles
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29.16.2 SMC Pulse Register
Name:
Address:
Access:
SMC_PULSE[0..
5 ]
0xFFFFEA04 [0], 0xFFFFEA14 [1], 0xFFFFEA24 [2], 0xFFFFEA34 [3], 0xFFFFEA44 [4], 0xFFFFEA54 [5]
Read-write
31
–
30 29 28 27
NCS_RD_PULSE
26 25 24
22 21 20 18 17 16 23
–
15
–
7
–
14
6
13
5
12
4
19
NRD_PULSE
11
NCS_WR_PULSE
3
NWE_PULSE
10
2
9
1
8
0
• NWE_PULSE: NWE Pulse Length
The NWE signal pulse length is defined as:
NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles
The NWE pulse length must be at least 1 clock cycle.
• NCS_WR_PULSE: NCS Pulse Length in WRITE Access
In write access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
• NRD_PULSE: NRD Pulse Length
In standard read access, the NRD signal pulse length is defined in clock cycles as:
NRD pulse length = (256* NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles
The NRD pulse length must be at least 1 clock cycle.
In page mode read access, the NRD_PULSE parameter defines the duration of the subsequent accesses in the page.
• NCS_RD_PULSE: NCS Pulse Length in READ Access
In standard read access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
In page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page.
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29.16.3 SMC Cycle Register
Name:
Address:
Access:
SMC_CYCLE[0..
5 ]
0xFFFFEA08 [0], 0xFFFFEA18 [1], 0xFFFFEA28 [2], 0xFFFFEA38 [3], 0xFFFFEA48 [4], 0xFFFFEA58 [5]
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
NRD_CYCLE
23 22 21 18 17 16
15
–
7
14
–
6
13
–
5
20
NRD_CYCLE
19
12
–
11
–
4
NWE_CYCLE
3
10
–
2
9
–
1
8
NWE_CYCLE
0
• NWE_CYCLE: Total Write Cycle Length
The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and hold steps of the NWE and NCS signals. It is defined as:
Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles
• NRD_CYCLE: Total Read Cycle Length
The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals. It is defined as:
Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles
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29.16.4 SMC MODE Register
Name:
Address:
Access:
SMC_MODE[0..
5 ]
0xFFFFEA0C [0], 0xFFFFEA1C [1], 0xFFFFEA2C [2], 0xFFFFEA3C [3], 0xFFFFEA4C [4], 0xFFFFEA5C [5]
Read-write
31
–
30
–
29
PS
28 27
–
26
–
25
–
24
PMEN
19 23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
DBW
20
TDF_MODE
12
5
EXNW_MODE
4
11
–
3
–
18
TDF_CYCLES
17
10
–
2
–
9
–
16
8
BAT
1
WRITE_MODE
0
READ_MODE
• READ_MODE:
1: The read operation is controlled by the NRD signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD.
0: The read operation is controlled by the NCS signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS.
• WRITE_MODE
1: The write operation is controlled by the NWE signal.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE.
0: The write operation is controlled by the NCS signal.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS.
• EXNW_MODE: NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for the read and write controlling signal.
EXNW_MODE NWAIT Mode
0 0 Disabled
0
1
1
1
0
1
Reserved
Frozen Mode
Ready Mode
• Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.
• Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until
NWAIT returns high.
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• BAT: Byte Access Type
This field is used only if DBW defines a 16- or 32-bit data bus.
• 1: Byte write access type:
– Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3.
– Read operation is controlled using NCS and NRD.
• 0: Byte select access type:
– Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3
– Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3
• DBW: Data Bus Width
DBW
0
0
1
1
0
1
0
1
Data Bus Width
8-bit bus
16-bit bus
32-bit bus
Reserved
• TDF_CYCLES: Data Float Time
This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set.
• TDF_MODE: TDF Optimization
1: TDF optimization is enabled.
– The number of TDF wait states is optimized using the setup period of the next read/write access.
0: TDF optimization is disabled.
– The number of TDF wait states is inserted before the next access begins.
• PMEN: Page Mode Enabled
1: Asynchronous burst read in page mode is applied on the corresponding chip select.
0: Standard read is applied.
• PS: Page Size
If page mode is enabled, this field indicates the size of the page in bytes.
PS Page Size
0 0 4-byte page
0
1
1
1
0
1
8-byte page
16-byte page
32-byte page
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29.16.5 SMC DELAY I/O Register
Name:
Address:
Access:
Reset:
SMC_DELAY 1-8
0xFFFFEAC0 [1] .. 0xFFFFEADC [8]
Read-write
See
31 30 29
Delay8
28
23 22 21 20
Delay6
15 14 13 12
Delay4
7 6 5 4
Delay2
• Delay x:
Gives the number of elements in the delay line.
11
3
27
19
26
18
10
2
Delay7
25
17
Delay5
9
Delay3
1
Delay1
8
0
24
16
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29.16.6 SMC Write Protect Mode Register
Name:
Address:
Access:
Reset:
SMC_WPMR
0xFFFFEAE4
Read-write
See
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
7
—
6
—
5
—
4
—
3
—
2
—
1
—
0
WPEN
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
Protects the registers listed below:
•
Section 29.16.1 ”SMC Setup Register”
•
Section 29.16.2 ”SMC Pulse Register”
•
Section 29.16.3 ”SMC Cycle Register”
•
Section 29.16.4 ”SMC MODE Register”
•
Section 29.16.5 ”SMC DELAY I/O Register”
• WPKEY: Write Protect KEY
Should be written at value 0x534D43 (“SMC” in ASCII). Writing any other value in this field aborts the write operation of the
WPEN bit. Always reads as 0.
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29.16.7 SMC Write Protect Status Register
Name:
Address:
Access:
Reset:
SMC_WPSR
0xFFFFEAE8
Read-only
See
31
—
30
—
29
—
23
15
22
14
21
13
28
—
27
—
20
WPVSRC
19
12
WPVSRC
11
4
—
3
—
26
—
18
10
25
—
17
9
24
—
16
8
7
—
6
—
5
—
2
—
1
—
0
WPVS
• WPVS: Write Protect Enable
0 = No Write Protect Violation has occurred since the last read of the SMC_WPSR register.
1 = A Write Protect Violation occurred since the last read of the SMC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted.
Note: Reading SMC_WPSR automatically clears all fields.
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30.
DDR SDR SDRAM Controller (DDRSDRC)
30.1 Description
The DDR SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises four slave AHB interfaces.
All simultaneous accesses (four independent AHB ports) are interleaved to maximize memory bandwidth and minimize transaction latency due to SDRAM protocol.
The DDRSDRC extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDR-
SDRAM device and external 16-bit DDR-SDRAM device. The page size supports ranges from 2048 to 16384 and the number of columns from 256 to 4096. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses.
The DDRSDRC supports a read or write burst length of 8 locations which frees the command and address bus to anticipate the next command, thus reducing latency imposed by the SDRAM protocol and improving the SDRAM bandwidth. Moreover it keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same bank. The DDRSDRC supports a CAS latency of 2 or 3 and optimizes the read access depending on the frequency.
The features of self refresh, power-down and deep power-down modes minimize the consumption of the SDRAM device.
The DDRSDRC user interface is compliant with ARM Advanced Peripheral Bus (APB rev2).
Note: The term “SDRAM device” regroups SDR-SDRAM, Low-power SDR-SDRAM, Low-power DDR1-SDRAM and
DDR2-SDRAM devices.
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30.2 Embedded Characteristics
AMBA Compliant Interface, interfaces Directly to the ARM Advanced High performance Bus (AHB)
Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Minimizes
Transaction Latency
AHB Transfer: Word, Half Word, Byte Access
Supports DDR2-SDRAM, Low-power DDR1-SDRAM, SDR-SDRAM and Low-power SDR-SDRAM
Numerous Configurations Supported
2K, 4K, 8K, 16K Row Address Memory Parts
SDRAM with Four and Eight Internal Banks
SDR-SDRAM with 16- or 32-bit Data Path
DDR-SDRAM with 16-bit Data Path
One Chip Select for SDRAM Device (256 Mbyte Address Space)
Programming Facilities
Multibank Ping-pong Access (up to 4 banks or 8 banks opened at the same time = Reduces Average
Latency of Transactions)
Timing Parameters Specified by Software
Automatic Refresh Operation, Refresh Rate is Programmable
Automatic Update of DS, TCR and PASR Parameters (Low-power SDRAM Devices)
Energy-saving Capabilities
Self-refresh, Power-down, Active Power-down and Deep Power-down Modes Supported
SDRAM Power-up Initialization by Software
CAS Latency of 2, 3 Supported
Reset Function Supported (DDR2-SDRAM)
ODT (On-die Termination) Not Supported
Auto Precharge Command Not Used
SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported
DDR2-SDRAM with Eight Internal Banks Supported
Linear and Interleaved Decoding Supported
SDR-SDRAM or Low-power DDR1-SDRAM with 2 Internal Banks Not Supported
Clock Frequency Change in Precharge Power-down Mode Not Supported
OCD (Off-chip Driver) Mode Not Supported
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30.3 DDRSDRC Module Diagram
Figure 30-1. DDRSDRC Module Diagram
AHB S l a ve Interf a ce 0
Inp u t
S t a ge
AHB S l a ve Interf a ce 1
Inp u t
S t a ge
AHB S l a ve Interf a ce 2
Inp u t
S t a ge
O u tp u t
S t a ge
Ar b iter
DDRS DR Controller
Power M a n a gement
Memory Controller
Finite S t a te M a chine
S DRAM S ign a l M a n a gement clk/nclk r as ,c as ,we cke
Addr, DQM
DDRS DR
Device s
DQ S
D a t a odt
A s ynchrono us Timing
Refre s h M a n a gement
AHB S l a ve Interf a ce 3
Inp u t
S t a ge
Interconnect M a trix
APB
Interf a ce APB
DDRSDRC is partitioned in two blocks (see
An Interconnect-Matrix that manages concurrent accesses on the AHB bus between four AHB masters and integrates an arbiter.
A controller that translates AHB requests (Read/Write) in the SDRAM protocol.
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30.4 Initialization Sequence
The addresses given are for example purposes only. The real address depends on implementation in the product.
30.4.1 SDR-SDRAM Initialization
The initialization sequence is generated by software. The SDR-SDRAM devices are initialized by the following sequence:
1.
Program the memory device type into the Memory Device Register (see Section 30.7.8 on page 441
).
2.
Program the features of the SDR-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.)), and into the Configuration Register (number of columns, rows, banks, cas latency) (see
and
).
3.
For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self
refresh (PASR) must be set in the Low-power Register (see Section 30.7.7 on page 439 ).
A minimum pause of 200
µ s is provided to precede any signal toggle.
4.
A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode Register, the application must
set Mode to 1 in the Mode Register (See Section 30.7.1 on page 430
). Perform a write access to any SDR-
SDRAM address to acknowledge this command. Now the clock which drives SDR-SDRAM device is enabled.
5.
An all banks precharge command is issued to the SDR-SDRAM. Program all banks precharge command into
). Perform a write access to any SDR-SDRAM address to acknowledge this command.
6.
Eight auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into Mode Register, the application must set Mode to 4 in the Mode Register (see
).Performs a write access to any SDR-SDRAM location eight times to acknowledge these commands.
7.
A Mode Register set (MRS) cycle is issued to program the parameters of the SDR-SDRAM devices, in particular
) and perform a write access to the SDR-SDRAM to acknowledge this command. The write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDR-SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000.
Note: This address is for example purposes only. The real address is dependent on implementation in the product.
8.
For low-power SDR-SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the
SDR-SDRAM parameters (TCSR, PASR, DS). The application must set Mode to 5 in the Mode Register (see
) and perform a write access to the SDR-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 MB SDRAM,
(12 rows, 9 columns, 4 banks) bank address the SDRAM write access should be done at the address 0x20800000.
9.
The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see
) and perform a write access at any location in the SDRAM to acknowledge this command.
10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register (see
delay between refresh cycles). The SDR-SDRAM device requires a refresh every 15.625 µ s or 7.81 µ s. With a 100
MHz frequency, the refresh timer count register must to be set with (15.625*100 MHz) = 1562 i.e. 0x061A or
(7.81*100 MHz) = 781 i.e. 0x030d
After initialization, the SDR-SDRAM device is fully functional.
30.4.2 Low-power DDR1-SDRAM Initialization
The initialization sequence is generated by software. The low-power DDR1-SDRAM devices are initialized by the following sequence:
1.
Program the memory device type into the Memory Device Register (see Section 30.7.8 on page 441
).
2.
Program the features of the low-power DDR1-SDRAM device into the Configuration Register: asynchronous tim-
ing (trc, tras, etc.), number of columns, rows, banks, cas latency. See Section 30.7.3 on page 432
, Section 30.7.4 on page 435 and
.
3.
Program temperature compensated self refresh (tcr), Partial array self refresh (pasr) and Drive strength (ds) into
the Low-power Register. See Section 30.7.7 on page 439
.
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4.
An NOP command will be issued to the low-power DDR1-SDRAM. Program NOP command into the Mode Register, the application must set Mode to 1 in the Mode Register (see
). Perform a write access to any DDR1-SDRAM address to acknowledge this command. Now clocks which drive DDR1-SDRAM device are enabled.
A minimum pause of 200 µ s will be provided to precede any signal toggle.
5.
An all banks precharge command is issued to the low-power DDR1-SDRAM. Program all banks precharge command into the Mode Register, the application must set Mode to 2 in the Mode Register (See
6.
Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register, the application must set Mode to 4 in the Mode Register (see
Section 30.7.1 on page 430 ). Perform a write access
to any low-power DDR1-SDRAM location twice to acknowledge these commands.
7.
An Extended Mode Register set (EMRS) cycle is issued to program the low-power DDR1-SDRAM parameters
(TCSR, PASR, DS). The application must set Mode to 5 in the Mode Register (see
and perform a write access to the SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 1 BA[0] is set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the low-power DDR1-SDRAM write access should be done at address 0x20800000.
Note: This address is for example purposes only. The real address is dependent on implementation in the product.
8.
A Mode Register set (MRS) cycle is issued to program the parameters of the low-power DDR1-SDRAM devices, in
write address must be chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB low-power
DDR1-SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000. The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see
acknowledge this command.
9.
Perform a write access to any low-power DDR1-SDRAM address.
10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register (see
delay between refresh cycles). The low-power DDR1-SDRAM device requires a refresh every 15.625 µ s or 7.81
µ s. With a 100 MHz frequency, the refresh timer count register must to be set with (15.625*100 MHz) = 1562 i.e.
0x061A or (7.81*100 MHz) = 781 i.e. 0x030d
11. After initialization, the low-power DDR1-SDRAM device is fully functional.
30.4.3 DDR2-SDRAM Initialization
The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized by the following sequence:
1.
Program the memory device type into the Memory Device Register (see Section 30.7.8 on page 441
).
2.
Program the features of DDR2-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.)), and into the Configuration Register (number of columns, rows, banks, cas latency and output drive strength) (see
,
and
3.
An NOP command is issued to the DDR2-SDRAM. Program the NOP command into the Mode Register, the appli-
DDR2-SDRAM address to acknowledge this command. Now clocks which drive DDR2-SDRAM device are enabled.
A minimum pause of 200
µ s is provided to precede any signal toggle.
4.
An NOP command is issued to the DDR2-SDRAM. Program the NOP command into the Mode Register, the appli-
DDR2-SDRAM address to acknowledge this command. Now CKE is driven high.
5.
An all banks precharge command is issued to the DDR2-SDRAM. Program all banks precharge command into the
). Perform a write access to any DDR2-SDRAM address to acknowledge this command
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6.
An Extended Mode Register set (EMRS2) cycle is issued to chose between commercial or high temperature operations. The application must set Mode to 5 in the Mode Register (see
) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that
BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address 0x20800000.
Note: This address is for example purposes only. The real address is dependent on implementation in the product.
7.
An Extended Mode Register set (EMRS3) cycle is issued to set the Extended Mode Register to “0”. The applica-
tion must set Mode to 5 in the Mode Register (see Section 30.7.1 on page 430
) and perform a write access to the
DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 1 and
BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address 0x20C00000.
8.
An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. The application must set Mode to 5 in the
Mode Register (see
Section 30.7.1 on page 430 ) and perform a write access to the DDR2-SDRAM to acknowl-
edge this command. The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address 0x20400000.
An additional 200 cycles of clock are required for locking DLL
9.
Program DLL field into the Configuration Register (see Section 30.7.3 on page 432
) to high (Enable DLL reset).
10. A Mode Register set (MRS) cycle is issued to reset DLL. The application must set Mode to 3 in the Mode Register
(see Section 30.7.1 on page 430
) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB
DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000.
11. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks precharge command into the
). Perform a write access to any DDR2-SDRAM address to acknowledge this command
12. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register,
the application must set Mode to 4 in the Mode Register (see Section 30.7.1 on page 430
). Performs a write access to any DDR2-SDRAM location twice to acknowledge these commands.
13. Program DLL field into the Configuration Register (see Section 30.7.3 on page 432
) to low (Disable DLL reset).
14. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices, in particular
CAS latency, burst length and to disable DLL reset. The application must set Mode to 3 in the Mode Register (see
write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000
15. Program OCD field into the Configuration Register (see
Section 30.7.3 on page 432 ) to high (OCD calibration
default).
16. An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. The application must set Mode to
5 in the Mode Register (see Section 30.7.1 on page 430
) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address 0x20400000.
exit).
18. An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit. The application must set Mode to 5
acknowledge this command. The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address 0x20400000.
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). Perform a write access to any DDR2-SDRAM address to acknowledge this command.
20. Perform a write access to any DDR2-SDRAM address.
21. Write the refresh rate into the count field in the Refresh Timer register (see
). (Refresh rate = delay between refresh cycles). The DDR2-SDRAM device requires a refresh every 15.625 µ s or 7.81 µ s. With a 133
MHz frequency, the refresh timer count register must to be set with (15.625*133 MHz) = 2079 i.e. 0x081f or
(7.81*133 MHz) = 1039 i.e. 0x040f.
After initialization, the DDR2-SDRAM devices are fully functional.
30.5 Functional Description
30.5.1 SDRAM Controller Write Cycle
The DDRSDRC allows burst access or single access in normal mode (mode = 000). Whatever the access type, the
DDRSDRC keeps track of the active row in each bank, thus maximizing performance.
The SDRAM device is programmed with a burst length equal to 8. This determines the length of a sequential data input by the write command that is set to 8. The latency from write command to data input is fixed to 1 in the case of DDR-
SDRAM devices. In the case of SDR-SDRAM devices, there is no latency from write command to data input.
To initiate a single access, the DDRSDRC checks if the page access is already open. If row/bank addresses match with the previous row/bank addresses, the controller generates a write command. If the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/active (t RP) commands and active/write (t RCD) command. As the burst length is fixed to 8, in the case of single access, it has to stop the burst, otherwise seven invalid values may be written. In the case of
SDR-SDRAM devices, a Burst Stop command is generated to interrupt the write operation. In the case of DDR-SDRAM devices, Burst Stop command is not supported for the burst write operation. In order to then interrupt the write operation,
Dm must be set to 1 to mask invalid data (see Figure 30-2 on page 409
and Figure 30-5 on page 410 ) and DQS must
continue to toggle.
To initiate a burst access, the DDRSDRC uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out. If the next access is a write nonsequential access, then an automatic access break is inserted, the DDRSDRC generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/write (tRCD) commands.
For a definition of timing parameters, refer to
Section 30.7.4 “DDRSDRC Timing Parameter 0 Register” on page 435 .
Write accesses to the SDRAM devices are burst oriented and the burst length is programmed to 8. It determines the maximum number of column locations that can be accessed for a given write command. When the write command is issued, 8 columns are selected. All accesses for that burst take place within these eight columns, thus the burst wraps within these 8 columns if a boundary is reached. These 8 columns are selected by addr[13:3]. addr[2:0] is used to select the starting location within the block.
In the case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the 16-byte boundary of the
SDRAM device. For example, in the case of DDR-SDRAM devices, when a transfer (INCR4) starts at address 0x0C, the next access is 0x10, but since the burst length is programmed to 8, the next access is at 0x00. Since the boundary is reached, the burst is wrapping. The DDRSDRC takes this feature of the SDRAM device into account. In the case of transfer starting at address 0x04/0x08/0x0C (DDR-SDRAM devices) or starting at address 0x10/0x14/0x18/0x1C, two write commands are issued to avoid to wrap when the boundary is reached. The last write command is subject to DM input logic level. If DM is registered high, the corresponding data input is ignored and write access is not done. This avoids additional writing being done.
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Figure 30-2. Single Write Access, Row Closed, Low-power DDR1-SDRAM Device
S DCLK
A[12:0] Row a col a
COMMAND NOP
BA[1:0]
DQ S [1:0]
0 0
PRCHG NOP ACT NOP WRITE NOP
DM[1:0]
D[15:0]
3 0
D a D b
3
Trp = 2 Trcd = 2
Figure 30-3. Single Write Access, Row Closed, DDR2-SDRAM Device
S DCLK
A[12:0] Row a
NOP PRCHG NOP ACT NOP COMMAND
BA[1:0]
DQ S [1:0]
DM[1:0]
0 0 col a
WRITE NOP
3 0 3
D[15:0]
D a D b
Trp = 2 Trcd = 2
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Figure 30-4. Single Write Access, Row Closed, SDR-SDRAM Device
SDCLK
A[12:0]
Row a
COMMAND NOP PRCHG NOP ACT
0 0
Col a
NOP
BA[1:0]
DM[1:0] 3
WRITE
0
D[31:0]
Trcd = 2
DaDb
Trp = 2
Figure 30-5. Burst Write Access, Row Closed, Low-power DDR1-SDRAM Device
SDCLK
BST
3
NOP
A[12:0]
COMMAND
BA[1:0] 0
DQS[1:0]
DM[1:0]
D [15:0]
3
NOP
Row a col a
PRCHG NOP ACT NOP WRITE NOP
0
Db Dc Dd De Df Dg Dh
3
Trp = 2 Trcd = 2
Da
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Figure 30-6. Burst Write Access, Row Closed, DDR2-SDRAM Device
SDCLK
A[12:0] Row a col a
COMMAND NOP
BA[1:0] 0
DQS[1:0]
DM[1:0]
D [15:0]
3
PRCHG NOP ACT NOP WRITE NOP
Da
0
Db Dc Dd De Df Dg Dh
3
Trp = 2 Trcd = 2
Figure 30-7. Burst Write Access, Row Closed, SDR-SDRAM Device
SDCLK
A[12:0] Row a Col a
COMMAND NOP PRCHG NOP ACT NOP WRITE
BA[1:0] 0
DM[3:0] F
D[31:0]
0
NOP
Da Db Dc Dd De Df Dg Dhs
BST
F
NOP
Trp Trcd
A write command can be followed by a read command. To avoid breaking the current write burst, Twtr/Twrd (bl/2 + 2 = 6 cycles) should be met. See
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Figure 30-8. Write Command Followed By a Read Command without Burst Write Interrupt, Low-power DDR1-SDRAM Device
SDCLK
A[12:0]
COMMAND NOP col a
WRITE NOP col a
READ BST NOP
BA[1:0] 0
DQS[1:0]
DM[1:0] 3
D[15:0]
0
Da Db Dc Dd De Df Dg Dh
Twrd = BL/2 +2 = 8/2 +2 = 6
3
Da Db
Twr = 1
In the case of a single write access, write operation should be interrupted by a read access but DM must be input 1 cycle prior to the read command to avoid writing invalid data. See
Figure 30-9. Single Write Access Followed By A Read Access Low-power DDR1-SDRAM Devices
SDCLK
A[12:0]
Row a col a
PRCHG NOP ACT NOP WRITE NOP READ BST NOP COMMAND NOP
BA[1:0] 0
DQS[1:0]
0 3 DM[1:0] 3
D[15:0]
Da Db Da Db
Data masked
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Figure 30-10.SINGLE Write Access Followed By A Read Access, DDR2 -SDRAM Device
SDCLK
A[12:0] Row a col a
COMMAND NOP PRCHG NOP ACT NOP WRITE
BA[1:0] 0
DQS[1:0]
DM[1:0] 3
NOP
0 3
READ NOP
D[15:0] Da Db Da Db
Data masked twtr
30.5.2 SDRAM Controller Read Cycle
The DDRSDRC allows burst access or single access in normal mode (mode =000). Whatever access type, the
DDRSDRC keeps track of the active row in each bank, thus maximizing performance of the DDRSDRC.
The SDRAM devices are programmed with a burst length equal to 8 which determines the length of a sequential data output by the read command that is set to 8. The latency from read command to data output is equal to 2 or 3. This value
).
To initiate a single access, the DDRSDRC checks if the page access is already open. If row/bank addresses match with the previous row/bank addresses, the controller generates a read command. If the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a read command. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/active (Trp) commands and active/read (Trcd) command. After a read command, additional wait states are generated to comply with cas latency. The DDRSDRC supports a cas latency of two, two and half, and three (2 or 3 clocks delay). As the burst length is fixed to 8, in the case of single access or burst access inferior to 8 data requests, it has to stop the burst otherwise seven or X values could be read. Burst Stop Command (BST) is used to stop output during a burst read.
To initiate a burst access, the DDRSDRC checks the transfer type signal. If the next accesses are sequential read accesses, reading to the SDRAM device is carried out. If the next access is a read non-sequential access, then an automatic page break can be inserted. If the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a read command. In the case where the page access is already open, a read command is generated.
To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/active (Trp) commands and active/read (Trcd) commands. The DDRSDRC supports a cas latency of two, two and half, and three (2 or 3 clocks delay). During this delay, the controller uses internal signals to anticipate the next access and improve the performance of the controller. Depending on the latency(2/3), the DDRSDRC anticipates 2 or 3 read accesses. In the case of burst of specified length, accesses are not anticipated, but if the burst is broken (border, busy mode, etc.), the next access is treated as an incrementing burst of unspecified length, and in function of the latency(2/3), the DDRSDRC anticipates 2 or 3 read accesses.
For a definition of timing parameters, refer to
Section 30.7.3 “DDRSDRC Configuration Register” on page 432
.
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Read accesses to the SDRAM are burst oriented and the burst length is programmed to 8. It determines the maximum number of column locations that can be accessed for a given read command. When the read command is issued, 8 columns are selected. All accesses for that burst take place within these eight columns, meaning that the burst wraps within these 8 columns if the boundary is reached. These 8 columns are selected by addr[13:3]; addr[2:0] is used to select the starting location within the block.
In the case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the 16-byte boundary of the
SDRAM device. For example, when a transfer (INCR4) starts at address 0x0C, the next access is 0x10, but since the burst length is programmed to 8, the next access is 0x00. Since the boundary is reached, the burst wraps. The
DDRSDRC takes into account this feature of the SDRAM device. In the case of DDR-SDRAM devices, transfers start at address 0x04/0x08/0x0C. In the case of SDR-SDRAM devices, transfers start at address 0x14/0x18/0x1C. Two read commands are issued to avoid wrapping when the boundary is reached. The last read command may generate additional reading (1 read cmd = 4 DDR words or 1 read cmd = 8 SDR words).
To avoid additional reading, it is possible to use the burst stop command to truncate the read burst and to decrease power consumption.
Figure 30-11.Single Read Access, Row Close, Latency = 2,Low-power DDR1-SDRAM Device
SDCLK
A[12:0]
COMMAND NOP PRCHG NOP
Row a
ACT
Col a
NOP READ BST NOP
BA[1:0]
0
DQS[1]
DQS[0]
DM[1:0] 3
D[15:0] Da Db
Trp Trcd Latency = 2
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Figure 30-12.Single Read Access, Row Close, Latency = 3, DDR2-SDRAM Device
SDCLK
A[12:0] Row a Col a
ACT NOP READ COMMAND NOP PRCHG NOP
BA[1:0]
0
DQS[1]
DQS[0]
DM[1:0]
3
D[15:0] Da Db
Trp Trcd Latency = 2
Figure 30-13.Single Read Access, Row Close, Latency = 2, SDR-SDRAM Device
SDCLK
Row a
ACT NOP col a
READ BST NOP
A[12:0]
COMMAND NOP PRCHG NOP
BA[1:0] 0
DM[3:0] 3
D[31:0]
Trp Trcd
DaDb
Latency = 2
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Figure 30-14.Burst Read Access, Latency = 2, Low-power DDR1-SDRAM Devices
SDCLK
A[12:0] Col a
COMMAND NOP READ NOP
BA[1:0] 0
DQS[1:0]
DM[1:0]
D[15:0]
3
Da Db Dc Dd De Df Dg Dh
Latency = 2
Figure 30-15.Burst Read Access, Latency = 3, DDR2-SDRAM Devices
SDCLK
A[12:0] Col a
COMMAND
BA[1:0]
DQS[1:0]
NOP
0
DM[1:0]
D[15:0]
3
READ NOP
Da Db Dc Dd De Df Dg Dh
Latency = 3
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Figure 30-16.Burst Read Access, Latency = 2, SDR-SDRAM Devices
SDCLK
A[12:0] col a
COMMAND NOP READ NOP
BA[1:0] 0
DQS[1:0]
DM[3:0]
D[31:0]
F
DaDb DcDd
Latency = 2
BST
DeDf Dg Dh
NOP
30.5.3 Refresh (Auto-refresh Command)
An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The DDRSDRC generates these auto-refresh commands periodically. A timer is loaded with the value in the register DDRSDRC_TR that indicates the number of clock cycles between refresh cycles. When the DDRSDRC initiates a refresh of an SDRAM device, internal memory accesses are not delayed. However, if the CPU tries to access the SDRAM device, the slave indicates that the device is busy. A request of refresh does not interrupt a burst transfer in progress.
30.5.4 Power Management
30.5.4.1 Self Refresh Mode
This mode is activated by setting low-power command bits [LPCB] to ‘01’ in the DDRSDRC_LPR Register
Self refresh mode is used to reduce power consumption, i.e., when no access to the SDRAM device is possible. In this case, power consumption is very low. In self refresh mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the SDRAM device become “don’t care” except CKE, which remains low. As soon as the SDRAM device is selected, the DDRSDRC provides a sequence of commands and exits self refresh mode.
The DDRSDRC re-enables self refresh mode as soon as the SDRAM device is not selected. It is possible to define when self refresh mode will be enabled by setting the register LPR (see
Section 30.7.7 “DDRSDRC Low-power Register” on page 439
), timeout command bit:
00 = Self refresh mode is enabled as soon as the SDRAM device is not selected
01 = Self refresh mode is enabled 64 clock cycles after completion of the last access
10 = Self refresh mode is enabled 128 clock cycles after completion of the last access
As soon as the SDRAM device is no longer selected, PRECHARGE ALL BANKS command is generated followed by a
SELF-REFREFSH command. If, between these two commands an SDRAM access is detected, SELF-REFREFSH command will be replaced by an AUTO-REFRESH command. According to the application, more AUTO-REFRESH commands will be performed when the self refresh mode is enabled during the application.
This controller also interfaces low-power SDRAM. These devices add a new feature: A single quarter, one half quarter or all banks of the SDRAM array can be enabled in self refresh mode. Disabled banks will be not refreshed in self refresh mode. This feature permits to reduce the self refresh current. The extended mode register controls this feature, it includes Temperature Compensated Self Refresh (TSCR), Partial Array Self Refresh (PASR) parameters and Drive
Strength (DS). These parameters are set during the initialization phase. After initialization, as soon as PASR/DS/TCSR fields are modified, the Extended Mode Register in the memory of the external device is accessed automatically and
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PASR/DS/TCSR bits are updated before entry into self refresh mode if DDRSDRC does not share an external bus with another controller or during a refresh command, and a pending read or write access, if DDRSDRC does share an external bus with another controller. This type of update is a function of the UPD_MR bit (see
Low-power Register” on page 439
).
The low-power SDR-SDRAM must remain in self refresh mode for a minimum period of TRAS periods and may remain in self refresh mode for an indefinite period. (See
)
The low-power DDR1-SDRAM must remain in self refresh mode for a minimum of TRFC periods and may remain in self refresh mode for an indefinite period.
The DDR2-SDRAM must remain in self refresh mode for a minimum of TCKE periods and may remain in self refresh mode for an indefinite period.
Figure 30-17.Self Refresh Mode Entry, Timeout = 0
SDCLK
A[12:0]
COMMAND NOP READ
CKE
BA[1:0] 0
BST NOP PRCHG NOP ARFSH NOP
DQS[0:1]
DM[1:0] 3
D[15:0] Da Db
Trp
Enter Self refresh
Mode
Figure 30-18.Self Refresh Mode Entry, Timeout = 1 or 2
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[1:0]
DM[1:0]
D[15:0]
NOP READ BST
0
3
NOP
Da Db
PRCHG NOP ARFSH NOP
64 or 128 wait states
Trp Enter Self refresh
Mode
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Figure 30-19.Self Refresh Mode Exit
S DCLK
A[12:0]
COMMAND NOP
CKE
BA[1:0] 0
DQ S [1:0]
DM[1:0]
D[15:0]
3
VALID NOP
D a D b clock m b us t b e efore exiting s s t ab le elf refre s h mode
Figure 30-20.Self Refresh and Automatic Update
S DCLK
A[12:0] P as r-Tcr-D s
NOP MR S COMMAND NOP PRCHG
CKE
BA[1:0] 0 2
NOP ARF S H
Exit S elf Refre s h mode
TXNRD/TX S RD (DDR device)
TX S R (Low-power DDR1 device)
TX S R (Low-power S DR, S DRS DRAM device)
NOP
Enter S elf Refre s h
Mode
Trp
Tmrd
Upd a te Extended Mode regi s ter
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Figure 30-21.Automatic Update During AUTO-REFRESH Command and SDRAM Access
S DCLK
A[12:0] P as r-Tcr-D s
COMMAND NOP PRCHALL NOP ARF S H NOP MR S NOP
CKE
BA[1:0] 0 2
Trp
Trfc Tmrd
ACT
0
Upd a te Extended mode regi s ter
30.5.4.2 Power-down Mode
This mode is activated by setting the low-power command bits [LPCB] to ‘10’.
Power-down mode is used when no access to the SDRAM device is possible. In this mode, power consumption is greater than in self refresh mode. This state is similar to normal mode (No low-power mode/No self refresh mode), but the CKE pin is low and the input and output buffers are deactivated as soon the SDRAM device is no longer accessible.
In contrast to self refresh mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64 ms). As no auto-refresh operations are performed in this mode, the DDRSDRC carries out the refresh operation. In order to exit low-power mode, a NOP command is required in the case of Low-power SDR-SDRAM and SDR-SDRAM devices.
In the case of Low-power DDR1-SDRAM devices, the controller generates a NOP command during a delay of at least
TXP. In addition, Low-power DDR1-SDRAM and DDR2-SDRAM must remain in power-down mode for a minimum period of TCKE periods.
The exit procedure is faster than in self refresh mode. See
. The DDRSDRC returns to powerdown mode as soon as the SDRAM device is not selected. It is possible to define when power-down mode is enabled by setting the register LPR, timeout command bit.
00 = Power-down mode is enabled as soon as the SDRAM device is not selected
01 = Power-down mode is enabled 64 clock cycles after completion of the last access
10 = Power-down mode is enabled 128 clock cycles after completion of the last access
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Figure 30-22.Power-down Entry/Exit, Timeout = 0
SDCLK
A[12:0]
COMMAND READ BST NOP
Da Db
READ
CKE
BA[1:0]
0
DQS[1:0]
DM[1:0] 3
D[15:0]
Da Db
Entry power down mode Exit power down mode
30.5.4.3 Deep Power-down Mode
The deep power-down mode is a new feature of the Low-power SDRAM. When this mode is activated, all internal voltage generators inside the device are stopped and all data is lost.
This mode is activated by setting the low-power command bits [LPCB] to ‘11’. When this mode is enabled, the
DDRSDRC leaves normal mode (mode == 000) and the controller is frozen. To exit deep power-down mode, the lowpower bits (LPCB) must be set to “00”, an initialization sequence must be generated by software. See
“Low-power DDR1-SDRAM Initialization” on page 405
.
Figure 30-23.Deep Power-down Mode Entry
SDCLK
A[12:0]
COMMAND
NOP READ BST NOP PRCHG NOP DEEPOWER NOP
CKE
BA[1:0]
DQS[1:0]
0
DM[1:0] 3
D[15:0]
Trp
Enter Deep
Power-down
Mode
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30.5.4.4 Reset Mode
The reset mode is a feature of the DDR2-SDRAM. This mode is activated by setting the low-power command bits (LPCB) to 11 and the clock frozen command bit (CLK_FR) to 1.
When this mode is enabled, the DDRSDRC leaves normal mode (mode == 000) and the controller is frozen. Before enabling this mode, the end user must assume there is not an access in progress.
To exit reset mode, the low-power command bits (LPCB) must be set to “00”, clock frozen command bit (CLK_FR) set to
0 and an initialization sequence must be generated by software. See
Section 30.4.3 “DDR2-SDRAM Initialization” on page 406
.
30.5.5 Multi-port Functionality
The SDRAM protocol imposes a check of timings prior to performing a read or a write access, thus decreasing the performance of systems. An access to SDRAM is performed if banks and rows are open (or active). To activate a row in a particular bank, it has to de-active the last open row and open the new row. Two SDRAM commands must be performed to open a bank: Precharge and Active command with respect to Trp timing. Before performing a read or write command, Trcd timing must checked.
This operation represents a significative loss. (see
).
Figure 30-24.Trp and Trcd Timings
SDCLK
A[12:0]
COMMAND NOP PRCHG NOP ACT NOP READ BST NOP
BA[1:0] 0
DQS[1:0]
DM1:0]
3
D[15:0]
Da Db
Trp Trcd Latency =2
4 cycles before performing a read command
The multi-port controller has been designed to mask these timings and thus improve the bandwidth of the system.
DDRSDRC is a multi-port controller since four masters can simultaneously reach the controller. This feature improves the bandwidth of the system because it can detect four requests on the AHB slave inputs and thus anticipate the commands that follow, PRECHARGE and ACTIVE commands in bank X during current access in bank Y. This allows Trp
already open. The best condition is met when the four masters work in different banks. In the case of four simultaneous read accesses, when the four banks and associated rows are open, the controller reads with a continuous flow and masks the cas latency for each different access. To allow a continuous flow, the read command must be set at 2 or 3 cycles (cas latency) before the end of current access. This requires that the scheme of arbitration changes since the round-robin arbitration cannot be respected. If the controller anticipates a read access, and thus before the end of current access a master with a high priority arises, then this master will not serviced.
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The arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters try to access the
SDRAM device at the same time.
The arbitration type is round-robin arbitration. This algorithm dispatches the requests from different masters to the
SDRAM device in a round-robin manner. If two or more master requests arise at the same time, the master with the lowest number is serviced first, then the others are serviced in a round-robin manner. To avoid burst breaking and to provide the maximum throughput for the SDRAM device, arbitration may only take place during the following cycles:
1.
Idle cycles: When no master is connected to the SDRAM device.
2.
Single cycles: When a slave is currently doing a single access.
3.
End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For bursts of defined length, predicted end of burst matches the size of the transfer. For bursts of undefined length, predicted end of burst is generated at the end of each four beat boundary inside the INCR transfer.
4.
Anticipated Access: When an anticipate read access is done while current access is not complete, the arbitration scheme can be changed if the anticipated access is not the next access serviced by the arbitration scheme.
Figure 30-25.Anticipate Precharge/Active Command in Bank 2 during Read Access in Bank 1
SDClK
A[12:0]
COMMAND NOP READ PRECH NOP ACT READ NOP
BA[1:0]
0
DQS[1:0]
DM1:0]
3
D[15:0]
1 2 1
Da Db Dc Dd De
Trp
Anticipate command, Precharge/Active Bank 2
Read access in Bank 1
Df Dg Dh Di Dj Dk Dl
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30.5.6 Write Protected Registers
To prevent any single software error that may corrupt DDRSDRC behavior, the registers listed below can be writeprotected by setting the WPEN bit in the DDRSDRC Write Protect Mode Register (DDRSDRC_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the DDRSDRC Write Protect Status
Register (DDRSDRC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset after reading the DDRSDRC Write Protect Status Register (DDRSDRC_WPSR).
Following is a list of the write protected registers:
“DDRSDRC Mode Register” on page 430
“DDRSDRC Refresh Timer Register” on page 431
“DDRSDRC Configuration Register” on page 432
“DDRSDRC Timing Parameter 0 Register” on page 435
“DDRSDRC Timing Parameter 1 Register” on page 437
“DDRSDRC Timing Parameter 2 Register” on page 438
“DDRSDRC Memory Device Register” on page 441
“DDRSDRC High Speed Register” on page 443
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30.6 Software Interface/SDRAM Organization, Address Mapping
The SDRAM address space is organized into banks, rows and columns. The DDRSDRC maps different memory types depending on the values set in the DDRSDRC Configuration Register. See
Section 30.7.3 “DDRSDRC Configuration
. The following figures illustrate the relation between CPU addresses and columns, rows and banks addresses for 16-bit memory data bus widths and 32-bit memory data bus widths.
The DDRSDRC supports address mapping in linear mode and interleaved mode.
Linear mode is a method for address mapping where banks alternate at each last SDRAM page of current bank.
Interleaved mode is a method for address mapping where banks alternate at each SDRAM end page of current bank.
The DDRSDRC makes the SDRAM devices access protocol transparent to the user.
illustrate the SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated.
30.6.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Four Banks
Table 30-1. Linear Mapping for SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bk[1:0] Row[10:0]
9 8 7 6 5
Column[8:0]
4
Bk[1:0]
Bk[1:0]
Bk[1:0]
Row[10:0]
Row[10:0]
Row[10:0]
Column[9:0]
Column[10:0]
Column[11:0]
3 2 1 0
M0
M0
M0
M0
Table 30-2. Linear Mapping for SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bk[1:0] Row[11:0]
9 8 7 6 5
Column[8:0]
4
Bk[1:0]
Bk[1:0]
Bk[1:0]
Row[11:0]
Row[11:0]
Row[11:0]
Column[9:0]
Column[10:0]
Column[11:0]
3 2 1 0
M0
M0
M0
M0
Table 30-3. Linear Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bk[1:0] Row[12:0]
9 8 7 6 5
Column[8:0]
4
Bk[1:0] Row[12:0] Column[9:0]
Bk[1:0]
Bk[1:0]
Row[12:0]
Row[12:0]
Column[10:0]
Column[11:0]
3 2 1 0
M0
M0
M0
M0
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Table 30-4. Linear Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bk[1:0] Row[13:0]
9 8 7
Bk[1:0]
Bk[1:0]
Row[13:0]
Row[13:0]
6 5
Column[8:0]
4
Column[9:0]
Column[10:0]
3 2 1 0
M0
M0
M0
Table 30-5. Interleaved Mapping for SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Row[10:0] Bk[1:0]
9 8 7 6 5
Column[8:0]
4
Row[10:0] Bk[1:0] Column[9:0]
Row[10:0]
Row[10:0]
Bk[1:0]
Bk[1:0]
Column[10:0]
Column[11:0]
3 2 1 0
M0
M0
M0
M0
Table 30-6. Interleaved Mapping for SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Row[11:0] Bk[1:0]
9 8 7 6 5
Column[8:0]
4
Row[11:0]
Row[11:0]
Row[11:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Column[9:0]
Column[10:0]
Column[11:0]
3 2 1 0
M0
M0
M0
M0
Table 30-7. Interleaved Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Row[12:0] Bk[1:0]
9 8 7 6 5
Column[8:0]
4
Row[12:0]
Row[12:0]
Row[12:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Column[9:0]
Column[10:0]
Column[11:0]
3 2 1 0
M0
M0
M0
M0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
426
Table 30-8. Interleaved Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Row[13:0] Bk[1:0]
9 8 7 6 5
Column[8:0]
4
Row[13:0]
Row[13:0]
Bk[1:0]
Bk[1:0]
Column[9:0]
Column[10:0]
3 2 1 0
M0
M0
M0
30.6.2 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Eight Banks
Table 30-9. Linear Mapping for SDRAM Configuration: 8K Rows, 1024 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bk[2:0] Row[12:0]
9 8 7 6 5
Column[9:0]
4 3 2 1 0
M0
Table 30-10. Linear Mapping for SDRAM Configuration: 16K Rows, 1024 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bk[2:0] Row[13:0]
9 8 7 6 5
Column[9:0]
4 3 2 1 0
M0
Table 30-11. Interleaved Mapping for SDRAM Configuration: 8K Rows, 1024 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Row[12:0] Bk[2:0]
9 8 7 6 5
Column[9:0]
4 3 2 1 0
M0
Table 30-12. Interleaved Mapping for SDRAM Configuration: 16K Rows, 1024 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Row[12:0] Bk[2:0]
9 8
30.6.3 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width
7 6 5
Column[9:0]
4 3 2 1 0
M0
Table 30-13. SDR-SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bk[1:0] Row[10:0]
9 8 7 6 5
Column[7:0]
4 3 2 1
M[1:0]
0
SAM9X35 [DATASHEET]
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Table 30-13. SDR-SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bk[1:0] Row[10:0]
Bk[1:0]
Bk[1:0]
Row[10:0]
Row[10:0]
9 8 7 6
Column[8:0]
5
Column[9:0]
Column[10:0]
4 3 2 1
M[1:0]
0
M[1:0]
M[1:0]
Table 30-14. SDR-SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bk[1:0]
Bk[1:0]
Row[11:0]
Row[11:0]
Bk[1:0]
Bk[1:0]
Row[11:0]
Row[11:0]
9 8 7 6 5
Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
4 3 2 1
M[1:0]
M[1:0]
0
M[1:0]
M[1:0]
Table 30-15. SDR-SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bk[1:0] Row[12:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Row[12:0]
Row[12:0]
Row[12:0]
9 8 7 6 5
Column[7:0]
4
Column[8:0]
Column[9:0]
Column[10:0]
Notes: 1. M[1:0] is the byte address inside a 32-bit word.
2. Bk[1] = BA1, Bk[0] = BA0
3 2 1
M[1:0]
0
M[1:0]
M[1:0]
M[1:0]
SAM9X35 [DATASHEET]
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30.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface
The User Interface is connected to the APB bus.
The DDRSDRC is programmed using the registers listed in
Table 30-16. Register Mapping
Offset Register
0x00
0x04
DDRSDRC Mode Register
DDRSDRC Refresh Timer Register
0x08
0x0C
0x10
0x14
DDRSDRC Configuration Register
DDRSDRC Timing Parameter 0 Register
DDRSDRC Timing Parameter 1 Register
DDRSDRC Timing Parameter 2 Register
0x18
0x1C
0x20
0x24
0x2C
0x54-0x58
0x60-0xE0
0xE4
0xE8
Reserved
DDRSDRC Low-power Register
DDRSDRC Memory Device Register
DDRSDRC DLL Information Register
Name
DDRSDRC_MR
DDRSDRC_RTR
DDRSDRC_CR
DDRSDRC_TPR0
DDRSDRC_TPR1
DDRSDRC_TPR2
–
DDRSDRC_LPR
DDRSDRC_MD
DDRSDRC_DLL
DDRSDRC High Speed Register
Reserved -
DDRSDRC_HS
Reserved –
DDRSDRC Write Protect Mode Register DDRSDRC_WPMR
DDRSDRC Write Protect Status Register DDRSDRC_WPSR
Access Reset
Read-write
Read-write
0x00000000
0x00000000
Read-write
Read-write
Read-write
Read-write
0x7024
0x20227225
0x3c80808
0x2062
–
Read-write
Read-write
Read-only
-
Read-write
–
Read-write
Read-only
-
–
0x10000
0x10
0x00000001
0x0
–
0x00000000
0x00000000
SAM9X35 [DATASHEET]
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30.7.1 DDRSDRC Mode Register
Name:
Address:
Access:
Reset:
DDRSDRC_MR
0xFFFFE800
Read-write
See
31
–
30
–
29
–
23
–
22
–
21
–
001
010
011
100
101
110
111
28
–
20
–
27
–
19
–
26
–
18
–
25
–
17
–
24
–
16
–
15
–
7
–
14
–
6
–
13
–
5
–
12
–
4
–
11
–
3
–
10
–
2
9
–
1
MODE
8
–
0
• MODE: DDRSDRC Command Mode
This field defines the command issued by the DDRSDRC when the SDRAM device is accessed. This register is used to initialize the SDRAM device and to activate deep power-down mode.
MODE
000
Description
Normal Mode. Any access to the DDRSDRC will be decoded normally. To activate this mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of the cycle.
To activate this mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the cycle.
To activate this mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues an “Auto-Refresh” Command when the SDRAM device is accessed regardless of the cycle.
Previously, an “All Banks Precharge” command must be issued. To activate this mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues an “Extended Load Mode Register” command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the “Extended Load Mode Register” command must be followed by a write to the
SDRAM. The write in the SDRAM must be done in the appropriate bank.
Deep power mode: Access to deep power-down mode
Reserved
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
430
30.7.2 DDRSDRC Refresh Timer Register
Name:
Address:
Access:
Reset:
DDRSDRC_RTR
0xFFFFE804
Read-write
See
31
–
23
–
30
–
22
–
29
–
21
–
28
–
20
–
27
–
19
–
26
–
18
–
25
–
17
–
24
–
16
–
15
–
14
–
13
–
12
–
11 10
COUNT
9 8
7 6 5 4 3 2 1
COUNT
0
• COUNT: DDRSDRC Refresh Timer Count
This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh sequence is initiated.
SDRAM devices require a refresh of all rows every 64 ms. The value to be loaded depends on the DDRSDRC clock frequency
(MCK: Master Clock) and the number of rows in the device.
For example, for an SDRAM with 8192 rows and a 100 MHz Master clock, the value of Refresh Timer Count bit is programmed:
(((64 x 10 -3 )/8192) x100 x10 6 )= 781 or 0x030D.
SAM9X35 [DATASHEET]
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431
30.7.3 DDRSDRC Configuration Register
Name:
Address:
Access:
Reset:
DDRSDRC_CR
0xFFFFE808
Read-write
See
31
–
30
–
29
–
23
–
22
DECOD
21
–
28
–
20
NB
15
–
7
DLL
14
6
13
OCD
5
CAS
12
4
11
–
3
10
–
2
9
DIS_DLL
1
NC
8
DIC/DS
0
NR
• NC: Number of Column Bits
The reset value is 9 column bits.
SDR-SDRAM devices with eight columns in 16-bit mode are not supported.
NC
00
01
10
11
DDR - Column bits
9
10
11
12
SDR - Column bits
8
9
10
11
27
–
19
–
26
–
18
ACTBST
25
–
17
–
24
–
16
EBISHARE
• NR: Number of Row Bits
The reset value is 12 row bits.
NR
00
01
10
11
Row bits
11
12
13
14
• CAS: CAS Latency
The reset value is 2 cycles.
CAS
000
001
010
DDR2 CAS Latency SDR CAS Latency
Reserved Reserved
Reserved
Reserved
Reserved
2
SAM9X35 [DATASHEET]
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CAS
011
100
101
110
111
DDR2 CAS Latency SDR CAS Latency
3
Reserved
Reserved
Reserved
Reserved
3
Reserved
Reserved
Reserved
Reserved
• DLL: Reset DLL
Reset value is 0.
This field defines the value of Reset DLL.
0 = Disable DLL reset.
1 = Enable DLL reset.
This value is used during the power-up sequence.
Note: Note: This field is found only in DDR2-SDRAM devices.
• DIC/DS: Output Driver Impedance Control
Reset value is 0.
This field defines the output drive strength.
0 = Normal driver strength.
1 = Weak driver strength.
This value is used during the power-up sequence. This parameter is found in the datasheet as DIC or DS.
Note: Note: This field is found only in DDR2-SDRAM devices.
• DIS_DLL: Disable DLL
Reset value is 0.
0 = Enable DLL
1 = Disable DLL
Note: Note: This field is found only in DDR2-SDRAM devices.
• OCD: Off-chip Driver
Reset value is 7.
Notes: 1. OCD is NOT supported by the controller, but these values MUST be programmed during the initialization sequence.
2. This field is found only in DDR2-SDRAM devices.
OCD
000
111
Use
OCD calibration mode exit, maintain setting
OCD calibration default
• EBISHARE: External Bus Interface is Shared
The DDR controller embedded in the EBI is used at the same time as another memory controller (SMC,..)
Reset value is 0.
0 = Only the DDR controller function is used.
1 = The DDR controller shares the EBI with another memory controller (SMC, NAND,..)
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• ACTBST: ACTIVE Bank X to Burst Stop Read Access Bank Y
Reset value is 0.
0 = After an ACTIVE command in Bank X, BURST STOP command can be issued to another bank to stop current read access.
1 = After an ACTIVE command in Bank X, BURST STOP command cannot be issued to another bank to stop current read access.
This field is unique to SDR-SDRAM, Low-power SDR-SDRAM and Low-power DDR1-SDRAM devices.
• NB: Number of Banks
The reset value is four banks.
NB
0
1
Number of banks
4
8
Note: Only DDR-SDRAM 2 devices support eight internal banks.
• DECOD: Type of Decoding
The reset value is 0: sequential decoding.
0 = Sequential Decoding.
1 = Interleaved Decoding.
SAM9X35 [DATASHEET]
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434
30.7.4 DDRSDRC Timing Parameter 0 Register
Name:
Address:
Access:
Reset:
DDRSDRC_TPR0
0xFFFFE80C
Read-write
See
31 30 29
TMRD
28
23 22 21 20
TRRD
27
REDUCE_WRRD
19
26
18
TRP
25
TWTR
17
24
16
15 14 13 12 11 10 9 8
TRC TWR
7 6 5 4 3 2 1
TRCD TRAS
0
• TRAS: Active to Precharge Delay
Reset Value is 5 cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is between 0 and 15.
• TRCD: Row to Column Delay
Reset Value is 2 cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of cycles is between 0 and 15.
• TWR: Write Recovery Delay
Reset value is 2 cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 1 and 15.
• TRC: Row Cycle Delay
Reset value is 7 cycles.
This field defines the delay between an Activate command and Refresh command in number of cycles. Number of cycles is between 0 and 15
• TRP: Row Precharge Delay
Reset Value is 2 cycles.
This field defines the delay between a Precharge Command and another command in number of cycles. Number of cycles is between 0 and 15.
• TRRD: Active bankA to Active bankB
Reset value is 2 cycles.
This field defines the delay between an Active command in BankA and an active command in bankB in number of cycles. Number of cycles is between 1 and 15.
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• TWTR: Internal Write to Read Delay
Reset value is 0.
This field is unique to Low-power DDR1-SDRAM devices and DDR2-SDRAM devices.
This field defines the internal write to read command Time in number of cycles. Number of cycles is between 1 and 7.
• REDUCE_WRRD: Reduce Write to Read Delay
Reset value is 0.
This field reduces the delay between write to read access for low-power DDR-SDRAM devices with a latency equal to 2. To use this feature, TWTR field must be equal to 0. Important to note is that some devices do not support this feature.
• TMRD: Load Mode Register Command to Active or Refresh Command
Reset Value is 2 cycles.
This field defines the delay between a Load mode register command and an active or refresh command in number of cycles.
Number of cycles is between 0 and 15.
SAM9X35 [DATASHEET]
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436
30.7.5 DDRSDRC Timing Parameter 1 Register
Name:
Address:
Access:
Reset:
DDRSDRC_TPR1
0xFFFFE810
Read-write
See
31
–
30
–
29
–
28
–
23 22 21 20
27
19
26
18
TXP
25
17
24
16
TXSRD
15 14 13 12 11 10 9 8
TXSNR
7
–
6
–
5
–
4 3 2
TRFC
1
0
• TRFC: Row Cycle Delay
Reset Value is 8 cycles.
This field defines the delay between a Refresh and an Activate command or Refresh command in number of cycles. Number of cycles is between 0 and 31
• TXSNR: Exit Self Refresh Delay to Non-read Command
Reset Value is 8 cycles.
This field defines the delay between cke set high and a non Read Command in number of cycles. Number of cycles is between 0 and 255. This field is used for SDR-SDRAM and DDR-SDRAM devices. In the case of SDR-SDRAM devices and Low-power DDR1-SDRAM, this field is equivalent to TXSR timing.
• TXSRD: ExiT Self Refresh Delay to Read Command
Reset Value is 200 cycles.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 255 cycles.This field is unique to DDR-SDRAM devices. In the case of a Low-power DDR1-SDRAM, this field must be written to 0.
• TXP: Exit Power-down Delay to First Command
Reset Value is 3 cycles.
This field defines the delay between cke set high and a Valid Command in number of cycles. Number of cycles is between 0 and
15 cycles. This field is unique to Low-power DDR1-SDRAM devices and DDR2-SDRAM devices.
SAM9X35 [DATASHEET]
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437
30.7.6 DDRSDRC Timing Parameter 2 Register
Name:
Address:
Access:
Reset:
DDRSDRC_TPR2
0xFFFFE814
Read-write
See
31
–
30
–
29
–
28
–
23
–
15
7
22
–
21
–
14
6
TXARDS
13
TRTP
5
20
–
12
4
27
–
19
11
3
26
–
18
10
2
TFAW
TRPA
25
–
17
9
1
24
–
16
8
0
TXARD
• TXARD: Exit Active Power Down Delay to Read Command in Mode “Fast Exit”.
The Reset Value is 2 cycles.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 15.
Note: This field is found only in DDR2-SDRAM devices .
• TXARDS: Exit Active Power Down Delay to Read Command in Mode “Slow Exit”.
The Reset Value is 6 cycles.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 15.
Note: This field is found only in DDR2-SDRAM devices .
• TRPA: Row Precharge All Delay
The Reset Value is 0 cycle.
This field defines the delay between a Precharge ALL banks Command and another command in number of cycles. Number of cycles is between 0 and 15.
Note: This field is found only in DDR2-SDRAM devices .
• TRTP: Read to Precharge
The Reset Value is 2 cycles.
This field defines the delay between Read Command and a Precharge command in number of cycle.
Number of cycles is between 0 and 7.
• TFAW: Four Active window
The Reset Value is 4 cycles.
DDR2 devices with 8-banks (1Gb or larger) have an additional requirement: t
FAW
ACTIVATE commands may be issued in any given t
FAW
(MIN) period.
. This requires that no more than four
Number of cycles is between 0 and 15.
Note: This field is found only in DDR-SDRAM 2 devices with eight internal banks
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
438
30.7.7 DDRSDRC Low-power Register
Name:
Address:
Access:
Reset:
DDRSDRC_LPR
0xFFFFE81C
Read-write
See
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
29
–
28
–
21
UPD_MR
20
13
TIMEOUT
12
5
PASR
4
27
–
19
–
11
–
3
26
–
18
–
10
2
CLK_FR
25
–
17
–
9
DS
1
LPCB
24
–
16
APDE
8
0
• LPCB: Low-power Command Bit
Reset value is “00”.
00 = Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device.
01 = The DDRSDRC issues a Self Refresh Command to the SDRAM device, the clock(s) is/are de-activated and the CKE signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access.
10 = The DDRSDRC issues a Power-down Command to the SDRAM device after each access, the CKE signal is set low. The
SDRAM device leaves the power-down mode when accessed and enters it after the access.
11 = The DDRSDRC issues a Deep Power-down Command to the Low-power SDRAM device.
This mode is unique to Lowpower SDRAM devices.
• CLK_FR: Clock Frozen Command Bit
Reset value is “0”.
This field sets the clock low during power-down mode or during deep power-down mode. Some SDRAM devices do not support freezing the clock during power-down mode or during deep power-down mode. Refer to the SDRAM device datasheet for details on this.
1 = Clock(s) is/are frozen.
0 = Clock(s) is/are not frozen.
• PASR: Partial Array Self Refresh
Reset value is “0”.
This field is unique to Low-power SDRAM. It is used to specify whether only one quarter, one half or all banks of the SDRAM array are enabled. Disabled banks are not refreshed in self refresh mode.
The values of this field are dependant on Low-power SDRAM devices.
After the initialization sequence, as soon as PASR field is modified, Extended Mode Register in the external device memory is accessed automatically and PASR bits are updated. In function of the UPD_MR bit, update is done before entering in self refresh mode or during a refresh command and a pending read or write access.
• DS: Drive Strength
Reset value is “0”.
This field is unique to Low-power SDRAM . It selects the driver strength of SDRAM output.
SAM9X35 [DATASHEET]
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439
00
01
10
11
After the initialization sequence, as soon as DS field is modified, Extended Mode Register is accessed automatically and DS bits are updated. In function of UPD_MR bit, update is done before entering in self refresh mode or during a refresh command and a pending read or write access.
• TIMEOUT: Low Power Mode
Reset value is “00”.
This field defines when low-power mode is enabled.
The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer.
The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer.
The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer.
Reserved
00
01
10
11
• APDE: Active Power Down Exit Time
Reset value is “1”.
This mode is unique to DDR2-SDRAM devices. This mode allows to determine the active power-down mode, which determines performance versus power saving .
0 = Fast Exit
1 = Slow Exit
After the initialization sequence, as soon as APDE field is modified Extended Mode Register, located in the memory of the external device, is accessed automatically and APDE bits are updated. In function of the UPD_MR bit, update is done before entering in self refresh mode or during a refresh command and a pending read or write access
• UPD_MR: Update Load Mode Register and Extended Mode Register
Reset value is “0”.
This bit is used to enable or disable automatic update of the Load Mode Register and Extended Mode Register. This update is function of DDRSDRC integration in a system. DDRSDRC can either share or not share an external bus with another controller.
Update is disabled.
DDRSDRC shares external bus. Automatic update is done during a refresh command and a pending read or write access in SDRAM device.
DDRSDRC does not share external bus. Automatic update is done before entering in self refresh mode.
Reserved
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
440
30.7.8 DDRSDRC Memory Device Register
Name:
Address:
Access:
Reset:
DDRSDRC_MD
0xFFFFE820
Read-write
See
31
–
30
–
29
–
23
–
22
–
21
–
28
–
20
–
27
–
19
–
26
–
18
–
25
–
17
–
15
–
7
–
14
–
6
–
13
–
5
–
12
–
4
DBW
11
–
3
–
10
–
2
9
–
1
MD
• MD: Memory Device
Indicates the type of memory used.
Reset value is for SDR-SDRAM device.
000 = SDR-SDRAM
001 = Low-power SDR-SDRAM
010 = Reserved
011 = Low-power DDR1-SDRAM
110 = DDR2-SDRAM
• DBW: Data Bus Width
Reset value is 16 bits.
0 = Data bus width is 32 bits (reserved for SDR-SDRAM device).
1 = Data bus width is 16 bits.
8
–
0
24
–
16
–
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30.7.9 DDRSDRC DLL Register
Name:
Address:
Access:
Reset:
DDRSDRC_DLL
0xFFFFE824
Read-only
31
–
30
–
29
–
23
–
22
–
21
–
28
–
20
–
27
–
19
–
26
–
18
–
25
–
17
–
24
–
16
–
15 14 13 12 11 10 9 8
MDVAL
7
–
6
–
5
–
4
–
3
–
2
MDOVF
1
MDDEC
0
MDINC
The DLL logic is internally used by the controller in order to delay DQS inputs. This is necessary to center the strobe time and the data valid window.
• MDINC: DLL Master Delay Increment
0 = The DLL is not incrementing the Master delay counter.
1 = The DLL is incrementing the Master delay counter.
• MDDEC: DLL Master Delay Decrement
0 = The DLL is not decrementing the Master delay counter.
1 = The DLL is decrementing the Master delay counter.
• MDOVF : DLL Master Delay Overflow Flag
0 = The Master delay counter has not reached its maximum value, or the Master is not locked yet.
1 = The Master delay counter has reached its maximum value, the Master delay counter increment is stopped and the DLL forces the Master lock. If this flag is set, it means the DDRSDRC clock frequency is too low compared to Master delay line number of elements.
• MDVAL : DLL Master Delay Value
Value of the Master delay counter.
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30.7.10 DDRSDRC High Speed Register
Name:
Address:
Access:
Reset:
DDRSDRC_HS
0xFFFFE82C
Read-write
See
31
–
30
–
29
–
23
–
22
–
21
–
28
–
20
–
27
–
19
–
26
–
18
–
25
–
17
–
24
–
16
–
15
–
7
–
14
–
6
–
13
–
5
–
12
–
4
–
11
–
3
–
10
–
2
DIS_ANTICIP_RE
AD
1
–
9
–
0
–
8
–
• DIS_ANTICIP_READ: Anticip Read Access
0 = anticip read access is enabled.
1 = anticip read access is disabled (default).
DIS_ANTICIP_READ allows DDR2 read access optimization with multi-port.
As this feature is based on the “bank open policy”, the software must map different buffers in different DDR2 banks to take advantage of that feature.
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30.7.11 DDRSDRC Write Protect Mode Register
Name:
Address:
Access:
Reset
DDRSDRC_WPMR
0xFFFFE8E4
Read-write
See
31 30 29 28
23 22 21
27
WPKEY
20
WPKEY
19
15 14 13 12 11
WPKEY
7
—
6
—
5
—
4
—
3
—
26
18
10
25
17
9
24
16
8
2
—
1
—
0
WPEN
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII).
Protects the registers:
•
“DDRSDRC Mode Register” on page 430
•
“DDRSDRC Refresh Timer Register” on page 431
•
“DDRSDRC Configuration Register” on page 432
•
“DDRSDRC Timing Parameter 0 Register” on page 435
•
“DDRSDRC Timing Parameter 1 Register” on page 437
•
“DDRSDRC Timing Parameter 2 Register” on page 438
•
“DDRSDRC Memory Device Register” on page 441
•
“DDRSDRC High Speed Register” on page 443
• WPKEY: Write Protect KEY
Should be written at value 0x444452 (“DDR” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
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30.7.12 DDRSDRC Write Protect Status Register
Name:
Address:
Access:
Reset:
DDRSDRC_WPSR
0xFFFFE8E8
Read-only
See
31
–
30
–
29
–
28
–
23 22 21
27
–
20
WPVSRC
19
15 14 13
7
–
6
–
5
–
12
WPVSRC
11
4
–
3
–
26
–
18
10
25
–
17
9
24
–
16
8
2
–
1
–
0
WPVS
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the DDRSDRC_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the DDRSDRC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted.
Note: Reading DDRSDRC_WPSR automatically clears all fields.
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31.
DMA Controller (DMAC)
31.1 Description
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data transfer. This is also known as a dual-access transfer.
The DMAC is programmed via the APB interface.
The DMAC embeds 8 channels.
31.2 Embedded Characteristics
2 AHB-Lite Master Interfaces
DMA Module Supports the Following Transfer Schemes: Peripheral-to-Memory, Memory-to-Peripheral, Peripheralto-Peripheral and Memory-to-Memory
Source and Destination Operate independently on BYTE (8-bit), HALF-WORD (16-bit) and WORD (32-bit)
Supports Hardware and Software Initiated Transfers
Supports Multiple Buffer Chaining Operations
Supports Incrementing/decrementing/fixed Addressing Mode Independently for Source and Destination
Supports Programmable Address Increment/decrement on User-defined Boundary Condition to Enable Picture-in-
Picture Mode
Programmable Arbitration Policy, Modified Round Robin and Fixed Priority are Available
Supports Specified Length and Unspecified Length AMBA AHB Burst Access to Maximize Data Bandwidth
AMBA APB Interface Used to Program the DMA Controller
8 DMA Channels
12 External Request Lines
Embedded FIFO
Channel Locking and Bus Locking Capability
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31.2.1 DMA Controller 0
Two Masters
Embeds 8 channels
64-byte FIFO for channel 0, 16-byte FIFO for Channel 1 to 7
Features:
Linked List support with Status Write Back operation at End of Transfer
Word, HalfWord, Byte transfer support.
Memory to memory transfer
Peripheral to memory
Memory to peripheral
The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the
peripherals below. The hardware interface numbers are provided in Table 31-1
.
Table 31-1. DMA Channel Definition
Instance name
HSMCI0
SPI0
SPI0
USART0
USART0
USART1
USART1
TWI0
TWI0
TWI2
TWI2
UART0
UART0
SSC
SSC
RX
TX
RX
TX
RX
RX
TX
RX
TX
T/R
RX/TX
TX
RX
TX
RX
TX
DMA Channel HW
Interface Number
0
3
4
1
2
9
10
11
12
7
8
5
6
13
14
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31.2.2 DMA Controller 1
Two Masters
Embeds 8 channels
16-bytes FIFO per Channel
Features:
Linked List support with Status Write Back operation at End of Transfer
Word, HalfWord, Byte transfer support.
Peripheral to memory
Memory to peripheral
The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the
peripherals below. The hardware interface numbers are provided in Table 31-2
.
Table 31-2. DMA Channel Definition
Instance name
HSMCI1
SPI1
SPI1
SMD
SMD
TWI1
TWI1
ADC
DBGU
DBGU
UART1
UART1
USART2
USART2
RX
TX
RX
TX
RX
TX
RX
RX
TX
T/R
RX/TX
TX
RX
TX
RX
DMA Channel HW
Interface Number
0
1
4
5
2
3
10
11
12
13
8
9
6
7
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31.3 Block Diagram
Figure 31-1. DMA Controller (DMAC) Block Diagram
AMBA AHB Layer 1
DMA AHB Lite Master Interface 1
DMA Global Control and Data Mux
DMA Global
Request Arbiter
DMA Write
Datapath Bundles
DMA FIFO Controller
DMA Channel n
DMA Channel 2
DMA Channel 1
DMA Channel 0
DMA Channel 0
Write data path to destination
DMA Destination
Control State Machine
Destination Pointer
Management
DMA Destination
DMA Destination
Requests Pool
Atmel APB rev2 Interface
Status
Registers
Configuration
Registers
DMA Interrupt
Controller
DMA
Atmel
APB
Interface
DMA Interrupt
DMA FIFO
Up to 64 bytes
Trigger Manager
External
Triggers
DMA
REQ/ACK
Interface
Soft
Triggers
DMA
Hardware
Handshaking
Interface
DMA Channel 0
Read data path from source
DMA Source
Control State Machine
Source Pointer
Management
DMA Read
Datapath Bundles
DMA Global Control and Data Mux
DMA Global
Request Arbiter
DMA Source
Requests Pool
DMA AHB Lite Master Interface 0
AMBA AHB Layer 0
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31.4 Functional Description
31.4.1 Basic Definitions
Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel
FIFO. The source peripheral teams up with a destination peripheral to form a channel.
Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the source peripheral).
Memory: Source or destination that is always “ready” for a DMAC transfer and does not require a handshaking interface to interact with the DMAC.
Programmable Arbitration Policy: Modified Round Robin and Fixed Priority are available by means of the ARB_CFG bit in the Global Configuration Register (DMAC_GCFG). The fixed priority is linked to the channel number. The highest
DMAC channel number has the highest priority.
Channel: Read/write datapath between a source peripheral on one configured AMBA layer and a destination peripheral on the same or different AMBA layer that occurs through the channel FIFO. If the source peripheral is not memory, then a source handshaking interface is assigned to the channel. If the destination peripheral is not memory, then a destination handshaking interface is assigned to the channel. Source and destination handshaking interfaces can be assigned dynamically by programming the channel registers.
Master interface: DMAC is a master on the AHB bus reading data from the source and writing it to the destination over the AHB bus.
Slave interface: The APB interface over which the DMAC is programmed. The slave interface in practice could be on the same layer as any of the master interfaces or on a separate layer.
Handshaking interface: A set of signal registers that conform to a protocol and handshake between the DMAC and source or destination peripheral to control the transfer of a single or chunk transfer between them. This interface is used to request, acknowledge, and control a DMAC transaction. A channel can receive a request through one of two types of handshaking interface: hardware or software.
Hardware handshaking interface: Uses hardware signals to control the transfer of a single or chunk transfer between the DMAC and the source or destination peripheral.
Software handshaking interface: Uses software registers to control the transfer of a single or chunk transfer between the DMAC and the source or destination peripheral. No special DMAC handshaking signals are needed on the I/O of the peripheral. This mode is useful for interfacing an existing peripheral to the DMAC without modifying it.
Flow controller: The device (either the DMAC or source/destination peripheral) that determines the length of and terminates a DMAC buffer transfer. If the length of a buffer is known before enabling the channel, then the DMAC should be programmed as the flow controller. If the length of a buffer is not known prior to enabling the channel, the source or destination peripheral needs to terminate a buffer transfer. In this mode, the peripheral is the flow controller.
Transfer hierarchy: Figure 31-2 on page 451
illustrates the hierarchy between DMAC transfers, buffer transfers, chunk
hierarchy for memory.
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Figure 31-2. DMAC Transfer Hierarchy for Non-Memory Peripheral
DMAC Transfer
Buffer Buffer
Chunk
Transfer
Chunk
Transfer
Buffer
Chunk
Transfer
DMA Transfer
Level
Buffer Transfer
Level
Single
Transfer
DMA Transaction
Level
AMBA
Burst
Transfer
AMBA
Burst
Transfer
AMBA
Burst
Transfer
AMBA
Single
Transfer
Figure 31-3. DMAC Transfer Hierarchy for Memory
DMAC Transfer
AMBA
Single
Transfer
AMBA Transfer
Level
Buffer Buffer Buffer
DMA Transfer
Level
Buffer Transfer
Level
AMBA
Burst
Transfer
AMBA
Burst
Transfer
AMBA
Burst
Transfer
AMBA
Single
Transfer
AMBA Transfer
Level
Buffer: A buffer of DMAC data. The amount of data (length) is determined by the flow controller. For transfers between the DMAC and memory, a buffer is broken directly into a sequence of AMBA bursts and AMBA single transfers.
For transfers between the DMAC and a non-memory peripheral, a buffer is broken into a sequence of DMAC transactions (single and chunks). These are in turn broken into a sequence of AMBA transfers.
Transaction: A basic unit of a DMAC transfer as determined by either the hardware or software handshaking interface.
A transaction is only relevant for transfers between the DMAC and a source or destination peripheral if the source or destination peripheral is a non-memory device. There are two types of transactions: single transfer and chunk transfer.
Single transfer: The length of a single transaction is always 1 and is converted to a single AMBA access.
Chunk transfer: The length of a chunk is programmed into the DMAC. The chunk is then converted into a sequence of AHB access.DMAC executes each AMBA burst transfer by performing incremental bursts that are no longer than 16 beats.
DMAC transfer: Software controls the number of buffers in a DMAC transfer. Once the DMAC transfer has completed, then hardware within the DMAC disables the channel and can generate an interrupt to signal the completion of the
DMAC transfer. You can then re-program the channel for a new DMAC transfer.
Single-buffer DMAC transfer: Consists of a single buffer.
Multi-buffer DMAC transfer: A DMAC transfer may consist of multiple DMAC buffers. Multi-buffer DMAC transfers are supported through buffer chaining (linked list pointers), auto-reloading of channel registers, and contiguous buffers. The source and destination can independently select which method to use.
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Linked lists (buffer chaining) – A descriptor pointer (DSCR) points to the location in system memory where the next linked list item (LLI) exists. The LLI is a set of registers that describe the next buffer (buffer descriptor) and a descriptor pointer register. The DMAC fetches the LLI at the beginning of every buffer when buffer chaining is enabled.
Replay – The DMAC automatically reloads the channel registers at the end of each buffers to the value when the channel was first enabled.
Contiguous buffers – Where the address of the next buffer is selected to be a continuation from the end of the previous buffer.
Picture-in-Picture Mode: DMAC contains a Picture-in-Picture mode support. When this mode is enabled, addresses are automatically incremented by a programmable value when the DMAC channel transfer count reaches a user defined boundary.
A user defined start address is defined at Picture_start_address. The incremented value is set to memory_hole_size = image_width - picture_width, and the boundary is set to picture_width.
Figure 31-4. Picture-In-Picture Mode Support
DMAC PIP tr a n s fer s
Channel locking: Software can program a channel to keep the AHB master interface by locking the arbitration for the master bus interface for the duration of a DMAC transfer, buffer, or chunk.
Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting hmastlock for the duration of a DMAC transfer, buffer, or transaction (single or chunk). Channel locking is asserted for the duration of bus locking at a minimum.
31.4.2 Memory Peripherals
shows the DMAC transfer hierarchy of the DMAC for a memory peripheral. There is no handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once the channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. By using the handshaking interface, the peripheral can signal to the DMAC that it is ready to transmit/receive data, and then the DMAC can access the peripheral without the peripheral inserting wait states onto the bus.
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31.4.3 Handshaking Interface
Handshaking interfaces are used at the transaction level to control the flow of single or chunk transfers. The operation of the handshaking interface is different and depends on whether the peripheral or the DMAC is the flow controller.
The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to transfer/accept data over the
AMBA bus. A non-memory peripheral can request a DMAC transfer through the DMAC using one of two handshaking interfaces:
Hardware handshaking
Software handshaking
Software selects between the hardware or software handshaking interface on a per-channel basis. Software handshaking is accomplished through memory-mapped registers, while hardware handshaking is accomplished using a dedicated handshaking interface.
31.4.3.1 Software Handshaking
When the slave peripheral requires the DMAC to perform a DMAC transaction, it communicates this request by sending an interrupt to the CPU or interrupt controller.
The interrupt service routine then uses the software registers to initiate and control a DMAC transaction. These software registers are used to implement the software handshaking interface.
The SRC_H2SEL/DST_H2SEL bit in the DMAC_CFGx channel configuration register must be set to zero to enable software handshaking.
When the peripheral is not the flow controller, then the last transaction register DMAC_LAST is not used, and the values in these registers are ignored.
Chunk Transactions
Writing a 1 to the DMAC_CREQ[2x] register starts a source chunk transaction request, where x is the channel number.
Writing a 1 to the DMAC_CREQ[2x+1] register starts a destination chunk transfer request, where x is the channel number.
Upon completion of the chunk transaction, the hardware clears the DMAC_CREQ[ 2x ] or DMAC_CREQ[2x+1].
Single Transactions
Writing a 1 to the DMAC_SREQ[2x] register starts a source single transaction request, where x is the channel number.
Writing a 1 to the DMAC_SREQ[2x+1] register starts a destination single transfer request, where x is the channel number.
Upon completion of the chunk transaction, the hardware clears the DMAC_SREQ[x] or DMAC_SREQ[2x+1].
T h e s o f t w a r e c a n p o l l t h e r e l e v a n t c h a n n e l b i t i n t h e D M A C _ C R E Q [ 2 x ] / D M A C _ C R E Q [ 2 x + 1 ] a n d
DMAC_SREQ[x]/DMAC_SREQ[2x+1] registers. When both are 0, then either the requested chunk or single transaction has completed.
31.4.4 DMAC Transfer Types
A DMAC transfer may consist of single or multi-buffer transfers. On successive buffers of a multi-buffer transfer, the
DMAC_SADDRx/DMAC_DADDRx registers in the DMAC are reprogrammed using either of the following methods:
Buffer chaining using linked lists
Replay mode
Contiguous address between buffers
On successive buffers of a multi-buffer transfer, the DMAC_CTRLAx and DMAC_CTRLBx registers in the DMAC are reprogrammed using either of the following methods:
Buffer chaining using linked lists
Replay mode
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When buffer chaining using linked lists is the multi-buffer method of choice, and on successive buffers, the
DMAC_DSCRx register in the DMAC is re-programmed using the following method:
Buffer chaining using linked lists
A buffer descriptor (LLI) consists of following registers, DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx,
DMAC_CTRLAx, DMAC_CTRLBx.These registers, along with the DMAC_CFGx register, are used by the DMAC to set up and describe the buffer transfer.
31.4.4.1 Multi-buffer Transfers
Buffer Chaining Using Linked Lists
In this case, the DMAC re-programs the channel registers prior to the start of each buffer by fetching the buffer descriptor for that buffer from system memory. This is known as an LLI update.
DMAC buffer chaining is supported by using a Descriptor Pointer register (DMAC_DSCRx) that stores the address in memory of the next buffer descriptor. Each buffer descriptor contains the corresponding buffer descriptor
(DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx DMAC_CTRLBx).
To set up buffer chaining, a sequence of linked lists must be programmed in memory.
The DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx registers are fetched from system memory on an LLI update. The updated content of the DMAC_CTRLAx register is written back to memory
transfers using buffer chaining.
The Linked List multi-buffer transfer is initiated by programming DMAC_DSCRx with DSCRx(0) (LLI(0) base address) different from zero. Other fields and registers are ignored and overwritten when the descriptor is retrieved from memory.
The last transfer descriptor must be written to memory with its next descriptor address set to 0.
Figure 31-5. Multi Buffer Transfer Using Linked List
System Memory
LLI(0) LLI(1)
DSCRx(0)
DSCRx(1)
= DSCRx(0) + 0x10
CTRLBx
= DSCRx(0) + 0xC
CTRLAx
= DSCRx(0) + 0x8
DADDRx
= DSCRx(0) + 0x4
SADDRx
= DSCRx(0) + 0x0
DSCRx(1)
DSCRx(2)
= DSCRx(1) + 0x10
CTRLBx
= DSCRx(1) + 0xC
CTRLBx
= DSCRx(1) + 0x8
DADDRx
= DSCRx(1) + 0x4
SADDRx
= DSCRx(1) + 0x0
DSCRx(2)
(points to 0 if
LLI(1) is the last transfer descriptor
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31.4.4.2 Programming DMAC for Multiple Buffer Transfers
Table 31-3. Multiple Buffers Transfer Management Table
Transfer Type
1) Single Buffer or Last buffer of a multiple buffer transfer
2) Multi Buffer transfer with contiguous DADDR
3) Multi Buffer transfer with contiguous SADDR
4) Multi Buffer transfer with
LLI support
5) Multi Buffer transfer with
DADDR reloaded
AUTO SRC_REP DST_REP SRC_DSCR DST_DSCR BTSIZE DSCR SADDR DADDR Other Fields
0
0
0
0
0
–
–
0
–
–
–
0
–
–
1
–
0
1
0
0
–
1
0
0
1
USR
LLI
LLI
LLI
LLI
0
USR
USR
USR
USR
USR
LLI
CONT
LLI
LLI
USR
CONT
LLI
LLI
REP
USR
LLI
LLI
LLI
LLI
6) Multi Buffer transfer with
SADDR reloaded
7) Multi Buffer transfer with BTSIZE reloaded and contiguous DADDR
8) Multi Buffer transfer with
BTSIZE reloaded and contiguous SADDR
9) Automatic mode channel is stalling
BTsize is reloaded
10) Automatic mode
BTSIZE, SADDR and
DADDR reloaded
11) Automatic mode
BTSIZE, SADDR reloaded and DADDR contiguous
0
1
1
1
1
1
1
–
0
0
1
1
–
0
–
0
1
0
1
0
1
1
1
1
0
1
0
1
1
1
LLI
REP
REP
REP
REP
REP
USR
USR
USR
USR
USR
USR
REP
LLI
CONT
CONT
REP
REP
LLI
CONT
LLI
CONT
REP
CONT
LLI
LLI
LLI
REP
REP
REP
Notes: 1. USR means that the register field is manually programmed by the user.
2. CONT means that address are contiguous.
3. REP means that the register field is updated with its previous value. If the transfer is the first one, then the user must manually program the value.
4. Channel stalled is true if the relevant BTC interrupt is not masked.
5. LLI means that the register field is updated with the content of the linked list item.
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Replay Mode of Channel Registers
During automatic replay mode, the channel registers are reloaded with their initial values at the completion of each buffer and the new values used for the new buffer. Depending on the row number in
Table 31-3 on page 455 , some or all of the
DMAC_SADDRx, DMAC_DADDRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers are reloaded from their initial value at the start of a buffer transfer.
Contiguous Address Between Buffers
In this case, the address between successive buffers is selected to be a continuation from the end of the previous buffer.
E n a b l i n g t h e s o u r c e o r d e s t i n a t i o n a d d r e s s t o b e c o n t i g u o u s b e t w e e n b u f f e r s i s a f u n c t i o n o f
DMAC_CTRLAx.SRC_DSCR, DMAC_CFGx.DST_REP, DMAC_CFGx.SRC_REP and DMAC_CTRLAx.DST_DSCR
registers.
Suspension of Transfers Between Buffers
At the end of every buffer transfer, an end of buffer interrupt is asserted if:
The channel buffer interrupt is unmasked, DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number.
Note: The Buffer Transfer Completed Interrupt is generated at the completion of the buffer transfer to the destination.
At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:
The channel end of the Chained Buffer Transfer Completed Interrupt is unmasked, DMAC_EBCIMR.CBTCx = ‘1’, when n is the channel number.
31.4.4.3 Ending Multi-buffer Transfers
All multi-buffer transfers must end as shown in Row 1 of
Table 31-3 on page 455 . At the end of every buffer transfer, the
DMAC samples the row number, and if the DMAC is in Row 1 state, then the previous buffer transferred was the last buffer and the DMAC transfer is terminated.
DMAC transfers continue until the automatic mode is disabled by writing a ‘1’ in DMAC_CTRLBx.AUTO bit. This bit should be programmed to zero in the end of buffer interrupt service routine that services the next-to-last buffer transfer.
This puts the DMAC into Row 1 state.
For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared), the user must set up the last buffer descriptor in memory so that LLI.DMAC_DSCRx is set to 0.
31.4.5 Programming a Channel
Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and DMAC_CFGx, need to be programmed to set up whether single or multi-buffer transfers take place, and which type of multi-buffer transfer is used.
The different transfer types are shown in
The “BTSIZE, SADDR and DADDR” columns indicate where the values of DMAC_SARx, DMAC_DARx, DMAC_CTLx, and DMAC_LLPx are obtained for the next buffer transfer when multi-buffer DMAC transfers are enabled.
31.4.5.1 Programming Examples
Single-buffer Transfer (Row 1)
1.
Read the Channel Handler Status Register DMAC_CHSR.ENAx Field to choose a free (disabled) channel.
2.
Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register, DMAC_EBCISR.
3.
Program the following channel registers:
1. Write the starting source address in the DMAC_SADDRx register for channel x.
2. Write the starting destination address in the DMAC_DADDRx register for channel x.
3. Write the next descriptor address in the DMA_DSCRx register for channel x with 0x0..
. Program the DMAC_CTRLBx register with both AUTO fields set to 0.
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5. Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx registers for channel x. For example, in the register, you can program the following:
i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register.
ii. Set up the transfer characteristics, such as:
Transfer width for the source in the SRC_WIDTH field.
Transfer width for the destination in the DST_WIDTH field.
Source AHB Master interface layer in the SIF field where source resides.
Destination AHB Master Interface layer in the DIF field where destination resides.
Incrementing/decrementing or fixed address for source in SRC_INC field.
Incrementing/decrementing or fixed address for destination in DST_INC field.
6. Write the channel configuration information into the DMAC_CFGx register for channel x.
i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests.
ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign a handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively.
7. If source Picture-in-Picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the
DMAC_SPIPx register for channel x.
8. If destination Picture-in-Picture mode is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the
DMAC_DPIPx register for channel x.
4.
After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the
DMAC_CHER.ENAx bit, where x is the channel number. Make sure that bit 0 of DMAC_EN.ENABLE register is enabled.
5.
Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming nonmemory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer.
6.
Once the transfer completes, the hardware sets the interrupts and disables the channel. At this time, you can either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or poll for the Channel Handler Status Register (DMAC_CHSR.ENAx) bit until it is cleared by hardware, to detect when the transfer is complete.
Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4)
1.
Read the Channel Handler Status register to choose a free (disabled) channel.
2.
Set up the chain of Linked List Items (otherwise known as buffer descriptors) in memory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers location of the buffer descriptor for each LLI in memory (see
) for channel x. For example, in the register, you can program the following:
1. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register.
2. Set up the transfer characteristics, such as:
i. Transfer width for the source in the SRC_WIDTH field.
ii. Transfer width for the destination in the DST_WIDTH field.
iii. Source AHB master interface layer in the SIF field where source resides.
iv. Destination AHB master interface layer in the DIF field where destination resides.
v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
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3.
Write the channel configuration information into the DMAC_CFGx register for channel x.
1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals.
This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests.
2. If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and
DST_PER bits, respectively.
4.
Make sure that the LLI.DMAC_CTRLBx register locations of all LLI entries in memory (except the last) are set as shown in Row 4 of
Figure 31-5 on page 454 shows a Linked List example with two list items.
5.
Make sure that the LLI.DMAC_DSCRx register locations of all LLI entries in memory (except the last) are non-zero and point to the base address of the next Linked List Item.
6.
Make sure that the LLI.DMAC_SADDRx/LLI.DMAC_DADDRx register locations of all LLI entries in memory point to the start source/destination buffer address preceding that LLI fetch.
7.
Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLI entries in memory are cleared.
8.
If source Picture-in-Picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the DMAC_SPIPx register for channel x.
9.
If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the DMAC_DPIPx register for channel x.
10. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the status register:
DMAC_EBCISR.
11. Program the DMAC_CTRLBx, DMAC_CFGx registers according to Row 4 as shown in
12. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item.
13. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. The transfer is performed.
14. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note: The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the DMAC_SADDRx,
DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx channel registers from the
DMAC_DSCRx(0).
15. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming nonmemory peripheral). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer.
16. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to system memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is, the location of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only
DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE bits have been updated by DMAC hardware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed.
Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the transfer.
17. The DMAC does not wait for the buffer interrupt to be cleared, but continues fetching the next LLI from the memory location pointed to by current DMAC_DSCRx register and automatically reprograms the DMAC_SADDRx,
DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers. The DMAC transfer continues until the DMAC determines that the DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer
transferred was the last buffer in the DMAC transfer. The DMAC transfer might look like that shown in
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Figure 31-6. Multi-buffer with Linked List Address for Source and Destination
Address of
Source Layer
Address of
Destination Layer
Buffer 2 Buffer 2
SADDR(2) DADDR(2)
Buffer 1 Buffer 1
SADDR(1) DADDR(1)
Buffer 0 Buffer 0
SADDR(0)
DADDR(0)
Source Buffers Destination Buffers
If the user needs to execute a DMAC transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum buffer size DMAC_CTRLAx.BTSIZE, then this can be achieved using the type of multi-buffer transfer as shown in
Figure 31-7. Multi-buffer with Linked Address for Source and Destination Buffers are Contiguous
Address of
Source Layer
Address of
Destination Layer
Buffer 2
DADDR(3)
Buffer 2
Buffer 2
SADDR(3)
DADDR(2)
Buffer 2
Buffer 1
SADDR(2)
DADDR(1)
Buffer 1
SADDR(1)
Buffer 0
SADDR(0)
Source Buffers
The DMAC transfer flow is shown in Figure 31-8 on page 460
.
Buffer 0
DADDR(0)
Destination Buffers
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Figure 31-8. DMAC Transfer Flow for Source and Destination Linked List Address
Channel enabled by software
LLI Fetch
Hardware reprograms
SADDRx, DADDRx, CTRLA/Bx, DSCRx
DMAC buffer transfer
Chained Buffer Transfer Completed
Interrupt generated here
Writeback of DMAC_CTRLAx register in system memory
Is DMAC in
Row 1 of
DMAC State Machine Table?
no
DMAC Chained Buffer Transfer
Completed Interrupt generated here yes
Channel disabled by hardware
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Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10)
1.
Read the Channel Handler Status register to choose an available (disabled) channel.
2.
Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register. Program the following channel registers:
1. Write the starting source address in the DMAC_SADDRx register for channel x.
2. Write the starting destination address in the DMAC_DADDRx register for channel x.
3. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 10 as shown in
. Program the DMAC_DSCRx register with ‘0’.
4. Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx register for channel x. For example, in the register, you can program the following:
i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register.
ii. Set up the transfer characteristics, such as:
Transfer width for the source in the SRC_WIDTH field.
Transfer width for the destination in the DST_WIDTH field.
Source AHB master interface layer in the SIF field where source resides.
Destination AHB master interface layer in the DIF field where destination resides.
Incrementing/decrementing or fixed address for source in SRC_INCR field.
Incrementing/decrementing or fixed address for destination in DST_INCR field.
5. If source Picture-in-Picture mode is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x.
6. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for channel x.
7. Write the channel configuration information into the DMAC_CFGx register for channel x. Ensure that the reload bits, DMAC_CFGx.SRC_REP, DMAC_CFGx.DST_REP and DMAC_CTRLBx.AUTO are enabled.
i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_h2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests.
ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively.
3.
After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the
DMAC_CHER.ENAx bit where the channel number is. Make sure that bit 0 of the DMAC_EN register is enabled.
4.
Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming nonmemory peripherals). The DMAC acknowledges on completion of each chunk/single transaction and carries out the buffer transfer.
5.
When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx, DMAC_DADDRx and
DMAC_CTRLAx registers. The hardware sets the Buffer Transfer Completed Interrupt. The DMAC then samples
pleted. The hardware sets the Chained Buffer Transfer Completed Interrupt and disables the channel. So you can either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or poll for the Channel Enable in the Channel Status Register (DMAC_CHSR.ENAx) until it is disabled, to detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed.
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6.
The DMAC transfer proceeds as follows:
1. If the Buffer Transfer Completed Interrupt is unmasked (DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number), the hardware sets the Buffer Transfer Completed Interrupt when the buffer transfer has completed.
It then stalls until the STALx bit of DMAC_CHSR register is cleared by software, writing ‘1’ to
DMAC_CHER.KEEPx bit, where x is the channel number. If the next buffer is to be the last buffer in the
DMAC transfer, then the buffer complete ISR (interrupt service routine) should clear the automatic mode bit in the DMAC_CTRLBx.AUTO bit. This puts the DMAC into Row 1 as shown in
. If the next buffer is not the last buffer in the DMAC transfer, then the reload bits should remain enabled to keep the DMAC in Row 4.
2. If the Buffer Transfer Completed Interrupt is masked (DMAC_EBCIMR.BTCx = ‘0’, where x is the channel number), the hardware does not stall until it detects a write to the Buffer Transfer Completed Interrupt
Enable register DMAC_EBCIER register, but starts the next buffer transfer immediately. In this case, the
software must clear the automatic mode bit in the DMAC_CTRLB to put the DMAC into ROW 1 of Table 31-
shown in Figure 31-9 on page 462
. The DMAC transfer flow is shown in Figure 31-10 on page 463
.
Figure 31-9. Multi-buffer DMAC Transfer with Source and Destination Address Auto-reloaded
Address of
Source Layer
Address of
Destination Layer
Block0
Block1
Block2
SADDR
Source Buffers
BlockN
Destination Buffers
DADDR
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Figure 31-10. DMAC Transfer Flow for Source and Destination Address Auto-reloaded
Channel enabled by software
Buffer Transfer
Replay mode for SADDRx,
DADDRx, CTRLAx, CTRLBx
Buffer Transfer Completed
Interrupt generated here
DMAC Chained Buffer Transfer
Completed Interrupt generated here yes Is DMAC in Row 1 of
DMAC State Machine table?
Channel disabled by hardware no no
EBCIMR[x]=1?
yes
Stall until STALLx is cleared by writing to KEEPx field
Multi-buffer Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row 6)
1.
Read the Channel Handler Status register to choose a free (disabled) channel.
2.
Set up the chain of linked list items (otherwise known as buffer descriptors) in memory. Write the control information in the LLI.DMAC_CTRLAx and DMAC_CTRLBx registers location of the buffer descriptor for each LLI in memory for channel x. For example, in the register, you can program the following:
1. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control peripheral by programming the FC of the DMAC_CTRLBx register.
2. Set up the transfer characteristics, such as:
i. Transfer width for the source in the SRC_WIDTH field.
ii. Transfer width for the destination in the DST_WIDTH field.
iii. Source AHB master interface layer in the SIF field where source resides.
iv. Destination AHB master interface layer in the DIF field where destination resides.
v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
3.
Write the starting source address in the DMAC_SADDRx register for channel x.
Note: The values in the LLI.DMAC_SADDRx register locations of each of the Linked List Items (LLIs) set up in memory, although fetched during an LLI fetch, are not used.
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4.
Write the channel configuration information into the DMAC_CFGx register for channel x.
1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals.
This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface source/destination requests.
2. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and
DST_PER bits, respectively.
5.
Make sure that the LLI.DMAC_CTRLBx register locations of all LLIs in memory (except the last one) are set as
shown in Row 6 of Table 31-3 on page 455
while the LLI.DMAC_CTRLBx register of the last Linked List item must
be set as described in Row 1 of Table 31-3
. Figure 31-5 on page 454 shows a Linked List example with two list
items.
6.
Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except the last one) are non-zero and point to the next Linked List Item.
7.
Make sure that the LLI.DMAC_DADDRx register locations of all LLIs in memory point to the start destination buffer address proceeding that LLI fetch.
8.
Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTRLA register locations of all LLIs in memory is cleared.
9.
If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x.
10. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP is enabled), program the DMAC_DPIPx register for channel x.
11. Clear any pending interrupts on the channel from the previous DMAC transfer by reading to the DMAC_EBCISR register.
12. Program the DMAC_CTLx and DMAC_CFGx registers according to Row 6 as shown in
13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item.
14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. The transfer is performed. Make sure that bit 0 of the DMAC_EN register is enabled.
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note: The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI. DMAC_LLPx LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The LLI.DMAC_SADDRx register, although fetched, is not used.
16. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming nonmemory peripherals). DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer.
17. The DMAC_CTRLAx register is written out to the system memory. The DMAC_CTRLAx register is written out to the same location on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is the location of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only
DMAC_CTRLAx register is written out, because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAx.DONE fields have been updated by hardware within the DMAC. The LLI.DMAC_CTRLAx.DONE bit is asserted to indicate buffer completion. Therefore, the software can poll the LLI.DMAC_CTRLAx.DONE field of the DMAC_CTRLAx register in the LLi to ascertain when a buffer transfer has completed.
Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the polled LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLA.DONE bit was cleared at the start of the transfer.
18. The DMAC reloads the DMAC_SADDRx register from the initial value. The hardware sets the Buffer Transfer
Completed Interrupt. The DMAC samples the row number as shown in
Table 31-3 on page 455 . If the DMAC is in
Row 1, then the DMAC transfer has completed. The hardware sets the Chained Buffer Transfer Completed Interrupt and disables the channel. You can either respond to the Buffer Transfer Completed Interrupt or Chained
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Buffer Transfer Completed Interrupt, or poll for the Channel Enable. (DMAC_CHSR.ENAx) bit until it is cleared by
, the following step is performed.
19. The DMAC fetches the next LLI from the memory location pointed to by the current DMAC_DSCRx register, and automatically reprograms the DMAC_DADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. Note that the DMAC_SADDRx is not re-programmed as the reloaded value is used for the next DMAC buffer transfer. If the next buffer is the last buffer of the DMAC transfer, then the DMAC_CTRLBx and
DMAC_DSCRx registers just fetched from the LLI should match Row 1 of
Table 31-3 on page 455 . The DMAC
transfer might look like that shown in
Figure 31-11. Multi-buffer DMAC Transfer with Source Address Auto-reloaded and Linked List Destination Address
Address of
Source Layer
Address of
Destination Layer
SADDR
Buffer0
DADDR(0)
Buffer1
DADDR(1)
Buffer2
DADDR(2)
BufferN
DADDR(N)
Source Buffers
The DMAC Transfer flow is shown in Figure 31-12 on page 466 .
Destination Buffers
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Figure 31-12. DMAC Transfer Flow for Replay Mode at Source and Linked List Destination Address
Channel enabled by software
LLI Fetch
Hardware reprograms
DADDRx, CTRLAx, CTRLBx, DSCRx
DMAC buffer transfer
Writeback of control status information in LLI
Reload SADDRx
Buffer Transfer Completed
Interrupt generated here yes
DMAC Chained Buffer Transfer
Completed Interrupt generated here
Channel disabled by hardware
Is DMAC in
Row 1 of
DMAC State Machine Table?
no
Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 11)
1.
Read the Channel Handler Status register to choose a free (disabled) channel.
2.
Clear any pending interrupts on the channel from the previous DMAC transfer by reading to the Interrupt Status
Register.
3.
Program the following channel registers:
1. Write the starting source address in the DMAC_SADDRx register for channel x.
2. Write the starting destination address in the DMAC_DADDRx register for channel x.
3. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 11 as shown in
. Program the DMAC_DSCRx register with ‘0’. DMAC_CTRLBx.AUTO field is set to ‘1’ to enable automatic mode support.
4. Write the control information for the DMAC transfer in the DMAC_CTRLBx and DMAC_CTRLAx register for channel x. For example, in this register, you can program the following:
i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register.
ii. Set up the transfer characteristics, such as:
Transfer width for the source in the SRC_WIDTH field.
Transfer width for the destination in the DST_WIDTH field.
Source AHB master interface layer in the SIF field where source resides.
Destination AHB master interface master layer in the DIF field where destination resides.
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Incrementing/decrementing or fixed address for source in SRC_INCR field.
Incrementing/decrementing or fixed address for destination in DST_INCR field.
5. If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x.
6. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for channel x.
7. Write the channel configuration information into the DMAC_CFGx register for channel x.
i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests.
ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively.
4.
After the DMAC channel has been programmed, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. Make sure that bit 0 of the DMAC_EN.ENABLE register is enabled.
5.
Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming nonmemory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer.
6.
When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx register. The DMAC_DADDRx register remains unchanged. The hardware sets the Buffer Transfer Completed Interrupt. The DMAC then samples
pleted. The hardware sets the Chained Buffer Transfer Completed Interrupt and disables the channel. So you can either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or poll for the enable (ENAx) field in the Channel Status Register (DMAC_CHSR.ENAx bit) until it is cleared by hardware, to detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed.
7.
The DMAC transfer proceeds as follows:
1. If the Buffer Transfer Completed Interrupt is unmasked (DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number), the hardware sets the Buffer Transfer Completed Interrupt when the buffer transfer has completed.
It then stalls until STALx bit of DMAC_CHSR is cleared by writing in the KEEPx field of DMAC_CHER register, where x is the channel number. If the next buffer is to be the last buffer in the DMAC transfer, then the buffer complete ISR (interrupt service routine) should clear the automatic mode bit, DMAC_CTRLBx.AUTO.
in the DMAC transfer, then the automatic transfer mode bit should remain enabled to keep the DMAC in
Row 11 as shown in Table 31-3 on page 455
.
2. If the Buffer Transfer Completed Interrupt is masked (DMAC_EBCIMR.BTCx = ‘0’, where x is the channel number), the hardware does not stall until it detects a write to the Buffer Transfer Completed Interrupt
Enable register, but starts the next buffer transfer immediately. In this case, the software must clear the automatic mode bit, DMAC_CTRLBx.AUTO, to put the device into ROW 1 of
the last buffer of the DMAC transfer has completed.
The transfer is similar to that shown in
The DMAC Transfer flow is shown in Figure 31-14 on page 469 .
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Figure 31-13. Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address
Address of
Source Layer
Address of
Destination Layer
Buffer2
DADDR(2)
Buffer1
SADDR
Buffer0
DADDR(1)
DADDR(0)
Source Buffers Destination Buffers
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Figure 31-14. DMAC Transfer Replay Mode is Enabled for the Source and Contiguous Destination Address
Channel enabled by software
Buffer Transfer
Replay mode for SADDRx,
Contiguous mode for DADDRx
CTRLAx, CTRLBx
Buffer Transfer Completed
Interrupt generated here
Buffer Transfer Completed
Interrupt generated here yes Is DMAC in Row 1 of
DMAC State Machine Table?
Channel disabled by hardware no
DMA_EBCIMR[x]=1?
no yes
Stall until STALLx field is cleared by software writing
KEEPx field
Multi-buffer DMAC Transfer with Linked List for Source and Contiguous Destination Address (Row 2)
1.
Read the Channel Handler Status register to choose a free (disabled) channel.
2.
Set up the linked list in memory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx register location of the buffer descriptor for each LLI in memory for channel x. For example, in the register, you can program the following:
1. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register.
2. Set up the transfer characteristics, such as:
i. Transfer width for the source in the SRC_WIDTH field.
ii. Transfer width for the destination in the DST_WIDTH field.
iii. Source AHB master interface layer in the SIF field where source resides.
iv. Destination AHB master interface layer in the DIF field where destination resides.
v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
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3.
Write the starting destination address in the DMAC_DADDRx register for channel x.
Note: The values in the LLI.DMAC_DADDRx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used.
4.
Write the channel configuration information into the DMAC_CFGx register for channel x.
1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals.
This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests.
2. If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination peripherals. This requires programming the SRC_PER and
DST_PER bits, respectively.
5.
Make sure that all LLI.DMAC_CTRLBx register locations of the LLI (except the last) are set as shown in Row 2 of
shows a Linked List example with two list items.
6.
Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except the last) are non-zero and point to the next Linked List Item.
7.
Make sure that the LLI.DMAC_SADDRx register locations of all LLIs in memory point to the start source buffer address proceeding that LLI fetch.
8.
Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLIs in memory is cleared.
9.
If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x.
10. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP is enabled), program the DMAC_DPIPx register for channel x.
11. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register.
12. Program the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx registers according to Row 2 as shown in
13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item.
14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit. The transfer is performed. Make sure that bit 0 of the DMAC_EN register is enabled.
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note: The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI.DMAC_DSCRx and LLI.DMAC_CTRLA/Bx registers are fetched. The LLI.DMAC_DADDRx register location of the LLI, although fetched, is not used. The
DMAC_DADDRx register in the DMAC remains unchanged.
16. Source and destination requests single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer.
17. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to the system memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is, the location of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only
DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE fields have been updated by DMAC hardware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed.
Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the transfer.
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18. The DMAC does not wait for the buffer interrupt to be cleared, but continues and fetches the next LLI from the memory location pointed to by the current DMAC_DSCRx register, then automatically reprograms the
DMAC_SADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx register is left unchanged. The DMAC transfer continues until the DMAC samples the DMAC_CTRLAx,
DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match that described in Row 1 of
DMAC transfer.
The DMAC transfer might look like that shown in
Figure 31-15 on page 471 . Note that the destination address is
decrementing.
Figure 31-15. DMAC Transfer with Linked List Source Address and Contiguous Destination Address
Address of
Source Layer
Address of
Destination Layer
Buffer 2
SADDR(2)
Buffer 2
DADDR(2)
Buffer 1
Buffer 1
SADDR(1) DADDR(1)
Buffer 0
Buffer 0
SADDR(0)
Source Buffers
The DMAC transfer flow is shown in Figure 31-16 on page 472
.
Destination Buffers
DADDR(0)
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Figure 31-16. DMAC Transfer Flow for Linked List Source Address and Contiguous Destination Address
Channel enabled by software
LLI Fetch
Hardware reprograms
SADDRx, CTRLAx,CTRLBx, DSCRx
DMAC buffer transfer
Writeback of control information of LLI
Buffer Transfer Completed
Interrupt generated here
Is DMAC in
Row 1 ?
DMAC Chained Buffer Transfer
Completed Interrupt generated here yes
Channel disabled by hardware no
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31.4.6 Disabling a Channel Prior to Transfer Completion
Under normal operation, the software enables a channel by writing a ‘1’ to the Channel Handler Enable Register,
DMAC_CHER.ENAx, and the hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENAx
register bit.
The recommended way for software to disable a channel without losing data is to use the SUSPx bit in conjunction with the EMPTx bit in the Channel Handler Status Register.
1.
If the software wishes to disable a channel n prior to the DMAC transfer completion, then it can set the
DMAC_CHER.SUSPx bit to tell the DMAC to halt all transfers from the source peripheral. Therefore, the channel
FIFO receives no new data.
2.
The software can now poll the DMAC_CHSR.EMPTx bit until it indicates that the channel n FIFO is empty, where n is the channel number.
3.
The DMAC_CHER.ENAx bit can then be cleared by software once the channel n FIFO is empty, where n is the channel number.
When DMAC_CTRLAx.SRC_WIDTH is less than DMAC_CTRLAx.DST_WIDTH and the DMAC_CHSRx.SUSPx bit is high, the DMAC_CHSRx.EMPTx is asserted once the contents of the FIFO does not permit a single word of
DMAC_CTRLAx.DST_WIDTH to be formed. However, there may still be data in the channel FIFO but not enough to form a single transfer of DMAC_CTLx.DST_WIDTH width. In this configuration, once the channel is disabled, the remaining data in the channel FIFO are not transferred to the destination peripheral. It is permitted to remove the channel from the suspension state by writing a ‘1’ to the DMAC_CHER.RESx field register. The DMAC transfer completes in the normal manner. n defines the channel number.
Note: If a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an acknowledgement.
31.4.6.1 Abnormal Transfer Termination
A DMAC transfer may be terminated abruptly by software by clearing the channel enable bit, DMAC_CHDR.ENAx, where x is the channel number. This does not mean that the channel is disabled immediately after the
DMAC_CHSR.ENAx bit is cleared over the APB interface. Consider this as a request to disable the channel. The
DMAC_CHSR.ENAx must be polled and then it must be confirmed that the channel is disabled by reading back 0.
The software may terminate all channels abruptly by clearing the global enable bit in the DMAC Configuration Register
(DMAC_EN.ENABLE bit). Again, this does not mean that all channels are disabled immediately after the
DMAC_EN.ENABLE is cleared over the APB slave interface. Consider this as a request to disable all channels. The
DMAC_CHSR.ENABLE must be polled and then it must be confirmed that all channels are disabled by reading back ‘0’.
Note: If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to the destination peripheral and is not present when the channel is re-enabled. For read sensitive source peripherals, such as a source FIFO, this data is therefore lost. When the source is not a read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to empty may be acceptable as the data is available from the source peripheral upon request and is not lost.
Note: If a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an acknowledgement.
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31.5 DMAC Software Requirements
There must not be any write operation to Channel registers in an active channel after the channel enable is made
HIGH. If any channel parameters must be reprogrammed, this can only be done after disabling the DMAC channel.
When the destination peripheral has been defined as the flow controller, source single transfer requests are not serviced until the destination peripheral has asserted its Last Transfer Flag.
When the source peripheral has been defined as the flow controller, destination single transfer requests are not serviced until the source peripheral has asserted its Last Transfer Flag.
When the destination peripheral has been defined as the flow controller, if the destination width is smaller than the source width, then a data loss may occur, and the loss is equal to the Source Single Transfer size in bytes- destination Single Transfer size in bytes.
When a Memory to Peripheral transfer occurs, if the destination peripheral has been defined as the flow controller, then a prefetch operation is performed. It means that data is extracted from the memory before any request from the peripheral is generated.
You must program the DMAC_SADDRx and DMAC_DADDRx channel registers with a byte, half-word and word aligned address depending on the source width and destination width.
After the software disables a channel by writing into the channel disable register, it must re-enable the channel only after it has polled a 0 in the corresponding channel enable status register. This is because the current AHB
Burst must terminate properly.
If you program the BTSIZE field in the DMAC_CTRLA as zero, and the DMAC has been defined as the flow controller, then the channel is automatically disabled.
When hardware handshaking interface protocol is fully implemented, a peripheral is expected to deassert any sreq or breq signals on receiving the ack signal irrespective of the request the ack was asserted in response to.
Multiple Transfers involving the same peripheral must not be programmed and enabled on different channels, unless this peripheral integrates several hardware handshaking interfaces.
When a Peripheral has been defined as the flow controller, the targeted DMAC Channel must be enabled before the Peripheral. If you do not ensure this and the First DMAC request is also the last transfer, the DMAC Channel might miss a Last Transfer Flag.
When the AUTO Field is set to TRUE, then the BTSIZE Field is automatically reloaded from its previous value.
BTSIZE must be initialized to a non zero value if the first transfer is initiated with the AUTO field set to TRUE, even if LLI mode is enabled, because the LLI fetch operation will not update this field.
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31.6 Write Protection Registers
To prevent any single software error that may corrupt the DMAC behavior, the DMAC address space can be write-
protected by setting the WPEN bit in the “DMAC Write Protect Mode Register” (DMAC_WPMR).
If a write access to anywhere in the DMAC address space is detected, then the WPVS flag in the DMAC Write Protect
Status Register (MCI_WPSR) is set, and the WPVSRC field indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the DMAC Write Protect Mode Register (DMAC_WPMR) with the appropriate access key, WPKEY.
The protected registers are:
“DMAC Global Configuration Register” on page 477
“DMAC Enable Register” on page 478
“DMAC Channel x [x = 0..7] Source Address Register” on page 489
“DMAC Channel x [x = 0..7] Destination Address Register” on page 490
“DMAC Channel x [x = 0..7] Descriptor Address Register” on page 491
“DMAC Channel x [x = 0..7] Control A Register” on page 492
“DMAC Channel x [x = 0..7] Control B Register” on page 494
“DMAC Channel x [x = 0..7] Configuration Register” on page 496
“DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register” on page 498
“DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register” on page 499
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31.7 DMA Controller (DMAC) User Interface
Table 31-4. Register Mapping
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
Register
DMAC Global Configuration Register
DMAC Enable Register
DMAC Software Single Request Register
DMAC Software Chunk Transfer Request Register
DMAC Software Last Transfer Flag Register
Reserved
DMAC Error, Chained Buffer Transfer Completed Interrupt and
Buffer Transfer Completed Interrupt Enable register.
DMAC Error, Chained Buffer Transfer Completed Interrupt and
Buffer Transfer Completed Interrupt Disable register.
Name
DMAC_GCFG
DMAC_EN
DMAC_SREQ
DMAC_CREQ
DMAC_LAST
DMAC_EBCIER
DMAC_EBCIDR
Access Reset
Read-write 0x10
Read-write 0x0
Read-write 0x0
Read-write 0x0
Read-write
Write-only
Write-only
0x0
–
–
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C+ch_num*(0x28)+(0x0)
0x03C+ch_num*(0x28)+(0x4)
0x03C+ch_num*(0x28)+(0x8)
DMAC Error, Chained Buffer Transfer Completed Interrupt and
Buffer transfer completed Mask Register.
DMAC Error, Chained Buffer Transfer Completed Interrupt and
Buffer transfer completed Status Register.
DMAC Channel Handler Enable Register
DMAC Channel Handler Disable Register
DMAC Channel Handler Status Register
Reserved
Reserved
DMAC Channel Source Address Register
DMAC Channel Destination Address Register
DMAC Channel Descriptor Address Register
0x03C+ch_num*(0x28)+(0xC) DMAC Channel Control A Register
0x03C+ch_num*(0x28)+(0x10) DMAC Channel Control B Register
0x03C+ch_num*(0x28)+(0x14) DMAC Channel Configuration Register
0x03C+ch_num*(0x28)+(0x18)
DMAC Channel Source Picture-in-Picture Configuration
Register
DMAC_EBCIMR
DMAC_EBCISR
DMAC_CHER
DMAC_CHDR
DMAC_CHSR
–
–
DMAC_SADDR
DMAC_DADDR
DMAC_DSCR
DMAC_CTRLA
DMAC_CTRLB
DMAC_CFG
DMAC_SPIP
0x03C+ch_num*(0x28)+(0x1C)
DMAC Channel Destination Picture-in-Picture Configuration
Register
0x03C+ch_num*(0x28)+(0x20) Reserved
0x03C+ch_num*(0x28)+(0x24)
0x1E4
0x1E8
0x01EC- 0x1FC
DMAC_DPIP
Reserved
–
–
DMAC Write Protect Mode Register DMAC_WPMR
DMAC Write Protect Status Register DMAC_WPSR
Reserved –
Read-only
Read-only
Write-only
Write-only
Read-only
–
–
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
–
–
Read-only
–
0x0
0x0
–
–
0x00FF0000
–
–
0x0
0x0
0x0
0x0
0x0
0x01000000
0x0
0x0
–
–
0x0
–
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31.7.1 DMAC Global Configuration Register
Name: DMAC_GCFG
Address: 0xFFFFEC00 (0), 0xFFFFEE00 (1)
Access: Read-write
Reset: 0x00000010
31
–
30
–
29
–
23
–
22
–
21
–
28
–
20
–
27
–
19
–
26
–
18
–
15
–
7
–
14
–
6
–
13
–
5
–
12
–
4
ARB_CFG
11
–
3
–
10
–
2
–
Note: Bit fields 0, 1, 2, 3, have a default value of 0. This should not be changed.
This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register”
.
• ARB_CFG: Arbiter Configuration
0 (FIXED): Fixed priority arbiter.
1 (ROUND_ROBIN): Modified round robin arbiter.
25
–
17
–
1
–
9
–
24
–
16
–
0
–
8
–
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31.7.2 DMAC Enable Register
Name:
Address:
Access:
DMAC_EN
0xFFFFEC04 (0), 0xFFFFEE04 (1)
Read-write
Reset: 0x00000000
31
–
30
–
29
–
23
–
22
–
21
–
28
–
20
–
27
–
19
–
26
–
18
–
15
–
7
–
14
–
6
–
13
–
5
–
12
–
4
–
11
–
3
–
10
–
2
–
This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register”
.
• ENABLE: General Enable of DMA
0: DMA Controller is disabled.
1: DMA Controller is enabled.
25
–
17
–
1
–
9
–
24
–
16
–
8
–
0
ENABLE
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31.7.3 DMAC Software Single Request Register
Name:
Address:
Access:
Reset:
31
–
DMAC_SREQ
0xFFFFEC08 (0), 0xFFFFEE08 (1)
Read-write
0x00000000
30
–
29
–
28
–
23
–
22
–
21
–
20
–
15
DSREQ7
7
DSREQ3
14
SSREQ7
6
SSREQ3
13
DSREQ6
5
DSREQ2
12
SSREQ6
4
SSREQ2
• DSREQx: Destination Request
Request a destination single transfer on channel i.
• SSREQx: Source Request
Request a source single transfer on channel i.
27
–
19
–
11
DSREQ5
3
DSREQ1
26
–
18
–
10
SSREQ5
2
SSREQ1
25
–
17
–
9
DSREQ4
1
DSREQ0
24
–
16
–
8
SSREQ4
0
SSREQ0
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31.7.4 DMAC Software Chunk Transfer Request Register
Name:
Address:
Access:
Reset:
31
–
DMAC_CREQ
0xFFFFEC0C (0), 0xFFFFEE0C (1)
Read-write
0x00000000
30
–
29
–
28
–
23
–
22
–
21
–
20
–
15
DCREQ7
7
DCREQ3
14
SCREQ7
6
SCREQ3
13
DCREQ6
5
DCREQ2
12
SCREQ6
4
SCREQ2
27
–
19
–
11
DCREQ5
3
DCREQ1
• DCREQx: Destination Chunk Request
Request a destination chunk transfer on channel i.
• SCREQx: Source Chunk Request
Request a source chunk transfer on channel i.
26
–
18
–
10
SCREQ5
2
SCREQ1
25
–
17
–
9
DCREQ4
1
DCREQ0
24
–
16
–
8
SCREQ4
0
SCREQ0
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31.7.5 DMAC Software Last Transfer Flag Register
Name:
Address:
Access:
Reset:
31
–
DMAC_LAST
0xFFFFEC10 (0), 0xFFFFEE10 (1)
Read-write
0x00000000
30
–
29
–
28
–
23
–
15
DLAST7
7
DLAST3
22
–
14
SLAST7
6
SLAST3
21
–
13
DLAST6
5
DLAST2
20
–
12
SLAST6
4
SLAST2
27
–
19
–
11
DLAST5
3
DLAST1
26
–
18
–
10
SLAST5
2
SLAST1
25
–
17
–
9
DLAST4
1
DLAST0
24
–
16
–
8
SLAST4
0
SLAST0
• DLASTx: Destination Last
Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer.
• SLASTx: Source Last
Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer.
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31.7.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register
Name: DMAC_EBCIER
Address: 0xFFFFEC18 (0), 0xFFFFEE18 (1)
Access: Write-only
Reset: 0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
23
ERR7
15
CBTC7
7
BTC7
22
ERR6
14
CBTC6
6
BTC6
21
ERR5
13
CBTC5
5
BTC5
20
ERR4
12
CBTC4
4
BTC4
19
ERR3
11
CBTC3
3
BTC3
18
ERR2
10
CBTC2
2
BTC2
17
ERR1
9
CBTC1
1
BTC1
24
–
16
ERR0
8
CBTC0
0
BTC0
• BTCx: Buffer Transfer Completed [7:0]
Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the BTC field to enable the interrupt for channel i.
• CBTCx: Chained Buffer Transfer Completed [7:0]
Chained Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the CBTC field to enable the interrupt for channel i.
• ERRx: Access Error [7:0]
Access Error Interrupt Enable Register. Set the relevant bit in the ERR field to enable the interrupt for channel i.
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31.7.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register
Name: DMAC_EBCIDR
Address:
Access:
0xFFFFEC1C (0), 0xFFFFEE1C (1)
Write-only
Reset: 0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
23
ERR7
15
CBTC7
7
BTC7
22
ERR6
14
CBTC6
6
BTC6
21
ERR5
13
CBTC5
5
BTC5
20
ERR4
12
CBTC4
4
BTC4
19
ERR3
11
CBTC3
3
BTC3
18
ERR2
10
CBTC2
2
BTC2
17
ERR1
9
CBTC1
1
BTC1
24
–
16
ERR0
8
CBTC0
0
BTC0
• BTCx: Buffer Transfer Completed [7:0]
Buffer transfer completed Disable Interrupt Register. When set, a bit of the BTC field disables the interrupt from the relevant
DMAC channel.
• CBTCx: Chained Buffer Transfer Completed [7:0]
Chained Buffer transfer completed Disable Register. When set, a bit of the CBTC field disables the interrupt from the relevant
DMAC channel.
• ERRx: Access Error [7:0]
Access Error Interrupt Disable Register. When set, a bit of the ERR field disables the interrupt from the relevant DMAC channel.
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31.7.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register
Name: DMAC_EBCIMR
Address: 0xFFFFEC20 (0), 0xFFFFEE20 (1)
Access: Read-only
Reset: 0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
23
ERR7
22
ERR6
21
ERR5
20
ERR4
19
ERR3
18
ERR2
17
ERR1
15
CBTC7
7
BTC7
14
CBTC6
6
BTC6
13
CBTC5
5
BTC5
12
CBTC4
4
BTC4
11
CBTC3
3
BTC3
10
CBTC2
2
BTC2
9
CBTC1
1
BTC1
• BTCx: Buffer Transfer Completed [7:0]
0: Buffer Transfer Completed Interrupt is disabled for channel i.
1: Buffer Transfer Completed Interrupt is enabled for channel i.
• CBTCx: Chained Buffer Transfer Completed [7:0]
0: Chained Buffer Transfer interrupt is disabled for channel i.
1: Chained Buffer Transfer interrupt is enabled for channel i.
• ERRx: Access Error [7:0]
0: Transfer Error Interrupt is disabled for channel i.
1: Transfer Error Interrupt is enabled for channel i.
24
–
16
ERR0
8
CBTC0
0
BTC0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
484
31.7.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register
Name:
Address:
Access:
Reset:
31
–
DMAC_EBCISR
0xFFFFEC24 (0), 0xFFFFEE24 (1)
Read-only
0x00000000
30
–
29
–
28
–
27
–
26
–
23
ERR7
22
ERR6
21
ERR5
20
ERR4
19
ERR3
18
ERR2
15
CBTC7
7
BTC7
14
CBTC6
6
BTC6
13
CBTC5
5
BTC5
12
CBTC4
4
BTC4
11
CBTC3
3
BTC3
10
CBTC2
2
BTC2
• BTCx: Buffer Transfer Completed [7:0]
When BTC[ i ] is set, Channel i buffer transfer has terminated.
• CBTCx: Chained Buffer Transfer Completed [7:0]
When CBTC[ i ] is set, Channel i Chained buffer has terminated. LLI Fetch operation is disabled.
• ERRx: Access Error [7:0]
When ERR[ i ] is set, Channel i has detected an AHB Read or Write Error Access.
25
–
17
ERR1
9
CBTC1
1
BTC1
24
–
16
ERR0
8
CBTC0
0
BTC0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
485
31.7.10 DMAC Channel Handler Enable Register
Name: DMAC_CHER
Address:
Access:
Reset:
0xFFFFEC28 (0), 0xFFFFEE28 (1)
Write-only
0x00000000
31
KEEP7
30
KEEP6
29
KEEP5
28
KEEP4
23
–
15
SUSP7
7
ENA7
22
–
14
SUSP6
6
ENA6
21
–
13
SUSP5
5
ENA5
20
–
12
SUSP4
4
ENA4
27
KEEP3
19
–
11
SUSP3
3
ENA3
• ENAx: Enable [7:0]
When set, a bit of the ENA field enables the relevant channel.
• SUSPx: Suspend [7:0]
When set, a bit of the SUSP field freezes the relevant channel and its current context.
• KEEPx: Keep on [7:0]
When set, a bit of the KEEP field resumes the current channel from an automatic stall state.
26
KEEP2
18
–
10
SUSP2
2
ENA2
25
KEEP1
17
–
9
SUSP1
1
ENA1
24
KEEP0
16
–
8
SUSP0
0
ENA0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
486
31.7.11 DMAC Channel Handler Disable Register
Name: DMAC_CHDR
Address: 0xFFFFEC2C (0), 0xFFFFEE2C (1)
Access: Write-only
Reset: 0x00000000
31
–
30
–
29
–
28
–
23
–
15
RES7
7
DIS7
22
–
14
RES6
6
DIS6
21
–
13
RES5
5
DIS5
20
–
12
RES4
4
DIS4
27
–
19
–
11
RES3
3
DIS3
26
–
18
–
10
RES2
2
DIS2
25
–
17
–
9
RES1
1
DIS1
24
–
16
–
8
RES0
0
DIS0
• DISx: Disable [7:0]
Write one to this field to disable the relevant DMAC Channel. The content of the FIFO is lost and the current AHB access is terminated. Software must poll DIS[7:0] field in the DMAC_CHSR register to be sure that the channel is disabled.
• RESx: Resume [7:0]
Write one to this field to resume the channel transfer restoring its context.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
487
31.7.12 DMAC Channel Handler Status Register
Name:
Address:
Access:
Reset:
31
STAL7
DMAC_CHSR
0xFFFFEC30 (0), 0xFFFFEE30 (1)
Read-only
0x00FF0000
30
STAL6
29
STAL5
28
STAL4
23
EMPT7
15
SUSP7
7
ENA7
22
EMPT6
14
SUSP6
6
ENA6
21
EMPT5
13
SUSP5
5
ENA5
20
EMPT4
12
SUSP4
4
ENA4
27
STAL3
19
EMPT3
11
SUSP3
3
ENA3
• ENAx: Enable [7:0]
A one in any position of this field indicates that the relevant channel is enabled.
• SUSPx: Suspend [7:0]
A one in any position of this field indicates that the channel transfer is suspended.
• EMPTx: Empty [7:0]
A one in any position of this field indicates that the relevant channel is empty.
• STALx: Stalled [7:0]
A one in any position of this field indicates that the relevant channel is stalling.
26
STAL2
18
EMPT2
10
SUSP2
2
ENA2
25
STAL1
17
EMPT1
9
SUSP1
1
ENA1
24
STAL0
16
EMPT0
8
SUSP0
0
ENA0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
488
31.7.13 DMAC Channel x [x = 0..7] Source Address Register
Name:
Address:
DMAC_SADDRx [x = 0..7]
0xFFFFEC3C (0)[0], 0xFFFFEC64 (0)[1], 0xFFFFEC8C (0)[2], 0xFFFFECB4 (0)[3], 0xFFFFECDC (0)[4],
0xFFFFED04 (0)[5], 0xFFFFED2C (0)[6], 0xFFFFED54 (0)[7], 0xFFFFEE3C (1)[0], 0xFFFFEE64 (1)[1],
0xFFFFEE8C (1)[2], 0xFFFFEEB4 (1)[3], 0xFFFFEEDC (1)[4], 0xFFFFEF04 (1)[5], 0xFFFFEF2C (1)[6],
0xFFFFEF54 (1)[7]
Access: Read-write
Reset: 0x00000000
31 30 29 28 27 26 25 24
SADDR
23 22 21 18 17 16
15
7
14
6
13
5
20
SADDR
19
12
SADDR
11
4 3
SADDR
10
2
9
1
8
0
This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register”
.
• SADDR: Channel x Source Address
This register must be aligned with the source transfer width.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
489
31.7.14 DMAC Channel x [x = 0..7] Destination Address Register
Name:
Address:
DMAC_DADDRx [x = 0..7]
0xFFFFEC40 (0)[0], 0xFFFFEC68 (0)[1], 0xFFFFEC90 (0)[2], 0xFFFFECB8 (0)[3], 0xFFFFECE0 (0)[4],
0xFFFFED08 (0)[5], 0xFFFFED30 (0)[6], 0xFFFFED58 (0)[7], 0xFFFFEE40 (1)[0], 0xFFFFEE68 (1)[1],
0xFFFFEE90 (1)[2], 0xFFFFEEB8 (1)[3], 0xFFFFEEE0 (1)[4], 0xFFFFEF08 (1)[5], 0xFFFFEF30 (1)[6],
0xFFFFEF58 (1)[7]
Access: Read-write
Reset: 0x00000000
31 30 29 28 27 26 25 24
DADDR
23 22 21 18 17 16
15
7
14
6
13
5
20
DADDR
19
12
DADDR
11
4 3
DADDR
10
2
9
1
8
0
This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register”
.
• DADDR: Channel x Destination Address
This register must be aligned with the destination transfer width.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
490
31.7.15 DMAC Channel x [x = 0..7] Descriptor Address Register
Name:
Address:
DMAC_DSCRx [x = 0..7]
0xFFFFEC44 (0)[0], 0xFFFFEC6C (0)[1], 0xFFFFEC94 (0)[2], 0xFFFFECBC (0)[3], 0xFFFFECE4 (0)[4],
0xFFFFED0C (0)[5], 0xFFFFED34 (0)[6], 0xFFFFED5C (0)[7], 0xFFFFEE44 (1)[0], 0xFFFFEE6C (1)[1],
0xFFFFEE94 (1)[2], 0xFFFFEEBC (1)[3], 0xFFFFEEE4 (1)[4], 0xFFFFEF0C (1)[5], 0xFFFFEF34 (1)[6],
0xFFFFEF5C (1)[7]
Access: Read-write
Reset: 0x00000000
31 30 29 28 27 26 25 24
DSCR
23 22 21 20 19 18 17 16
DSCR
15 14 13 12 11 10 9 8
DSCR
7 6 5 4 3 2
DSCR
This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register”
.
• DSCR_IF: Descriptor Interface Selection
1
DSCR_IF
0
Value
00
01
Name
AHB_IF0
AHB_IF1
Description
The buffer transfer descriptor is fetched via AHB-Lite Interface 0
The buffer transfer descriptor is fetched via AHB-Lite Interface 1
• DSCR: Buffer Transfer Descriptor Address
This address is word aligned.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
491
31.7.16 DMAC Channel x [x = 0..7] Control A Register
Name:
Address:
DMAC_CTRLAx [x = 0..7]
0xFFFFEC48 (0)[0], 0xFFFFEC70 (0)[1], 0xFFFFEC98 (0)[2], 0xFFFFECC0 (0)[3], 0xFFFFECE8 (0)[4],
0xFFFFED10 (0)[5], 0xFFFFED38 (0)[6], 0xFFFFED60 (0)[7], 0xFFFFEE48 (1)[0], 0xFFFFEE70 (1)[1],
0xFFFFEE98 (1)[2], 0xFFFFEEC0 (1)[3], 0xFFFFEEE8 (1)[4], 0xFFFFEF10 (1)[5], 0xFFFFEF38 (1)[6],
0xFFFFEF60 (1)[7]
Access: Read-write
Reset: 0x00000000
31
DONE
30
–
29
DST_WIDTH
28 27
–
26
–
25
SRC_WIDTH
24
22 18 16 23
–
15
7
14
6
21
DCSIZE
13
5
20 19
–
12
BTSIZE
11
4 3
BTSIZE
10
2
17
SCSIZE
9
1
8
0
• BTSIZE: Buffer Transfer Size
The transfer size relates to the number of transfers to be performed, that is, for writes it refers to the number of source width transfers to perform when DMAC is flow controller. For Reads, BTSIZE refers to the number of transfers completed on the Source
Interface. When this field is set to 0, the DMAC module is automatically disabled when the relevant channel is enabled.
• SCSIZE: Source Chunk Transfer Size
Value
000
001
010
011
Value
000
001
010
011
Name
CHK_1
CHK_4
CHK_8
CHK_16
• DCSIZE: Destination Chunk Transfer Size
Name
CHK_1
CHK_4
CHK_8
CHK_16
Description
1 data transferred
4 data transferred
8 data transferred
16 data transferred
Description
1 data transferred
4 data transferred
8 data transferred
16 data transferred
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
492
• SRC_WIDTH: Transfer Width for the Source
Value
00
01
1X
Name
BYTE
HALF_WORD
WORD
• DST_WIDTH: Transfer Width for the Destination
Description the transfer size is set to 8-bit width the transfer size is set to 16-bit width the transfer size is set to 32-bit width
Value
00
01
1X
Name
BYTE
HALF_WORD
WORD
Description the transfer size is set to 8-bit width the transfer size is set to 16-bit width the transfer size is set to 32-bit width
• DONE: Current Descriptor Stop Command and Transfer Completed Memory Indicator
0: The transfer is performed.
1: If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the content of this register.
The DONE field is written back to memory at the end of the current descriptor transfer.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
493
31.7.17 DMAC Channel x [x = 0..7] Control B Register
Name:
Address:
DMAC_CTRLBx [x = 0..7]
0xFFFFEC4C (0)[0], 0xFFFFEC74 (0)[1], 0xFFFFEC9C (0)[2], 0xFFFFECC4 (0)[3], 0xFFFFECEC (0)[4],
0xFFFFED14 (0)[5], 0xFFFFED3C (0)[6], 0xFFFFED64 (0)[7], 0xFFFFEE4C (1)[0], 0xFFFFEE74 (1)[1],
0xFFFFEE9C (1)[2], 0xFFFFEEC4 (1)[3], 0xFFFFEEEC (1)[4], 0xFFFFEF14 (1)[5], 0xFFFFEF3C (1)[6],
0xFFFFEF64 (1)[7]
Access: Read-write
Reset: 0x00000000
31
AUTO
30
IEN
29
DST_INCR
28 27
–
26
–
25
SRC_INCR
24
23 21
15
–
7
–
22
FC
14
–
6
–
13
5
20
DST_DSCR
DIF
12
DST_PIP
4
19
–
11
–
3
–
18
–
10
–
2
–
17
–
9
–
1
16
SRC_DSCR
SIF
8
SRC_PIP
0
This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register”
.
• SIF: Source Interface Selection Field
Value
00
01
Name
AHB_IF0
AHB_IF1
Description
The source transfer is done via AHB-Lite Interface 0
The source transfer is done via AHB-Lite Interface 1
• DIF: Destination Interface Selection Field
Value
00
01
Name
AHB_IF0
AHB_IF1
Description
The destination transfer is done via AHB-Lite Interface 0
The destination transfer is done via AHB-Lite Interface 1
• SRC_PIP: Source Picture-in-Picture Mode
0 (DISABLE): Picture-in-Picture mode is disabled. The source data area is contiguous.
1 (ENABLE): Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount.
• DST_PIP: Destination Picture-in-Picture Mode
0 (DISABLE): Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1 (ENABLE): Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount.
• SRC_DSCR: Source Address Descriptor
0 (FETCH_FROM_MEM): Source address is updated when the descriptor is fetched from the memory.
1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the source.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
494
• DST_DSCR: Destination Address Descriptor
0 (FETCH_FROM_MEM): Destination address is updated when the descriptor is fetched from the memory.
1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the destination.
• FC: Flow Control
This field defines which device controls the size of the buffer transfer, also referred to as the Flow Controller.
Value
000
001
010
011
Name
MEM2MEM_DMA_FC
MEM2PER_DMA_FC
PER2MEM_DMA_FC
PER2PER_DMA_FC
Description
Memory-to-Memory Transfer DMAC is flow controller
Memory-to-Peripheral Transfer DMAC is flow controller
Peripheral-to-Memory Transfer DMAC is flow controller
Peripheral-to-Peripheral Transfer DMAC is flow controller
• SRC_INCR: Incrementing, Decrementing or Fixed Address for the Source
Value
00
01
10
Name
INCREMENTING
DECREMENTING
FIXED
Description
The source address is incremented
The source address is decremented
The source address remains unchanged
• DST_INCR: Incrementing, Decrementing or Fixed Address for the Destination
Value
00
01
10
Name
INCREMENTING
DECREMENTING
FIXED
Description
The destination address is incremented
The destination address is decremented
The destination address remains unchanged
• IEN: Interrupt Enable Not
0: When the buffer transfer is completed, the BTCx flag is set in the EBCISR status register. This bit is active low.
1: When the buffer transfer is completed, the BTCx flag is not set.
If this bit is cleared, when the buffer transfer is completed, the BTCx flag is set in the EBCISR status register.
• AUTO: Automatic Multiple Buffer Transfer
0 (DISABLE): Automatic multiple buffer transfer is disabled.
1 (ENABLE): Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
495
31.7.18 DMAC Channel x [x = 0..7] Configuration Register
Name:
Address:
Access:
Reset:
DMAC_CFGx [x = 0..7]
0xFFFFEC50 (0)[0], 0xFFFFEC78 (0)[1], 0xFFFFECA0 (0)[2], 0xFFFFECC8 (0)[3], 0xFFFFECF0 (0)[4],
0xFFFFED18 (0)[5], 0xFFFFED40 (0)[6], 0xFFFFED68 (0)[7], 0xFFFFEE50 (1)[0], 0xFFFFEE78 (1)[1],
0xFFFFEEA0 (1)[2], 0xFFFFEEC8 (1)[3], 0xFFFFEEF0 (1)[4], 0xFFFFEF18 (1)[5], 0xFFFFEF40 (1)[6],
0xFFFFEF68 (1)[7]
Read-write
0x0100000000
31
–
30
–
29
FIFOCFG
28 27
–
26 25
AHB_PROT
24
23
–
15
–
7
22
LOCK_IF_L
14
–
21
LOCK_B
13
DST_H2SEL
6
DST_PER
5
20
LOCK_IF
12
DST_REP
4
19
–
11
–
3
18
–
10
–
17
–
9
SRC_H2SEL
2
SRC_PER
1
16
SOD
8
SRC_REP
0
• SRC_PER: Source with Peripheral identifier
Channel x Source Request is associated with peripheral identifier coded SRC_PER handshaking interface.
• DST_PER: Destination with Peripheral identifier
Channel x Destination Request is associated with peripheral identifier coded DST_PER handshaking interface.
• SRC_REP: Source Reloaded from Previous
0 (CONTIGUOUS_ADDR): When automatic mode is activated, source address is contiguous between two buffers.
1 (RELOAD_ADDR): When automatic mode is activated, the source address and the control register are reloaded from previous transfer.
• SRC_H2SEL: Software or Hardware Selection for the Source
0 (SW): Software handshaking interface is used to trigger a transfer request.
1 (HW): Hardware handshaking interface is used to trigger a transfer request.
• DST_REP: Destination Reloaded from Previous
0 (CONTIGUOUS_ADDR): When automatic mode is activated, destination address is contiguous between two buffers.
1 (RELOAD_ADDR): When automatic mode is activated, the destination and the control register are reloaded from the previous transfer.
• DST_H2SEL: Software or Hardware Selection for the Destination
0 (SW): Software handshaking interface is used to trigger a transfer request.
1 (HW): Hardware handshaking interface is used to trigger a transfer request.
• SOD: Stop On Done
0 (DISABLE): STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
1 (ENABLE): STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
496
• LOCK_IF: Interface Lock
0 (DISABLE): Interface Lock capability is disabled
1 (ENABLE): Interface Lock capability is enabled
• LOCK_B: Bus Lock
0 (DISABLE): AHB Bus Locking capability is disabled.
1(ENABLE): AHB Bus Locking capability is enabled.
• LOCK_IF_L: Master Interface Arbiter Lock
0 (CHUNK): The Master Interface Arbiter is locked by the channel x for a chunk transfer.
1 (BUFFER): The Master Interface Arbiter is locked by the channel x for a buffer transfer.
• AHB_PROT: AHB Protection
AHB_PROT field provides additional information about a bus access and is primarily used to implement some level of protection.
HPROT[3]
AHB_PROT[2]
HPROT[2]
AHB_PROT[1]
HPROT[1]
AHB_PROT[0]
1
HPROT[0] Description
Data access
0: User Access
1: Privileged Access
0: Not Bufferable
1: Bufferable
0: Not cacheable
1: Cacheable
• FIFOCFG: FIFO Configuration
Value
00
01
10
Name
ALAP_CFG
HALF_CFG
ASAP_CFG
Description
The largest defined length AHB burst is performed on the destination AHB interface.
When half FIFO size is available/filled, a source/destination request is serviced.
When there is enough space/data available to perform a single AHB access, then the request is serviced.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
497
31.7.19 DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register
Name:
Address:
Access:
Reset:
DMAC_SPIPx [x = 0..7]
0xFFFFEC54 (0)[0], 0xFFFFEC7C (0)[1], 0xFFFFECA4 (0)[2], 0xFFFFECCC (0)[3], 0xFFFFECF4 (0)[4],
0xFFFFED1C (0)[5], 0xFFFFED44 (0)[6], 0xFFFFED6C (0)[7], 0xFFFFEE54 (1)[0], 0xFFFFEE7C (1)[1],
0xFFFFEEA4 (1)[2], 0xFFFFEECC (1)[3], 0xFFFFEEF4 (1)[4], 0xFFFFEF1C (1)[5], 0xFFFFEF44 (1)[6],
0xFFFFEF6C (1)[7]
Read-write
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25 24
SPIP_BOUNDARY
23 22 21 18 17 16
15
7
14
6
13
5
20 19
SPIP_BOUNDARY
12
SPIP_HOLE
11
4
SPIP_HOLE
3
10
2
9
1
8
0
• SPIP_HOLE: Source Picture-in-Picture Hole
This field indicates the value to add to the address when the programmable boundary has been reached.
• SPIP_BOUNDARY: Source Picture-in-Picture Boundary
This field indicates the number of source transfers to perform before the automatic address increment operation.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
498
31.7.20 DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register
Name:
Address:
Access:
Reset:
DMAC_DPIPx [x = 0..7]
0xFFFFEC58 (0)[0], 0xFFFFEC80 (0)[1], 0xFFFFECA8 (0)[2], 0xFFFFECD0 (0)[3], 0xFFFFECF8 (0)[4],
0xFFFFED20 (0)[5], 0xFFFFED48 (0)[6], 0xFFFFED70 (0)[7], 0xFFFFEE58 (1)[0], 0xFFFFEE80 (1)[1],
0xFFFFEEA8 (1)[2], 0xFFFFEED0 (1)[3], 0xFFFFEEF8 (1)[4], 0xFFFFEF20 (1)[5], 0xFFFFEF48 (1)[6],
0xFFFFEF70 (1)[7]
Read-write
0x00000000
31
–
30
–
29
–
28
–
27
–
26
–
25 24
DPIP_BOUNDARY
23 22 21 18 17 16
15
7
14
6
13
5
20 19
DPIP_BOUNDARY
12
DPIP_HOLE
11
4
DPIP_HOLE
3
10
2
9
1
8
0
• DPIP_HOLE: Destination Picture-in-Picture Hole
This field indicates the value to add to the address when the programmable boundary has been reached.
• DPIP_BOUNDARY: Destination Picture-in-Picture Boundary
This field indicates the number of source transfers to perform before the automatic address increment operation.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
499
31.7.21 DMAC Write Protect Mode Register
Name:
Address:
Access:
Reset:
DMAC_WPMR
0xFFFFEDE4 (0), 0xFFFFEFE4 (1)
Read-write
See
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
7
—
6
—
5
—
4
—
3
—
2
—
1
—
0
WPEN
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x444D41 (“DMA” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x444D41 (“DMA” in ASCII).
Protects the registers:
•
“DMAC Global Configuration Register” on page 477
•
“DMAC Enable Register” on page 478
•
“DMAC Channel x [x = 0..7] Source Address Register” on page 489
•
“DMAC Channel x [x = 0..7] Destination Address Register” on page 490
•
“DMAC Channel x [x = 0..7] Descriptor Address Register” on page 491
•
“DMAC Channel x [x = 0..7] Control A Register” on page 492
•
“DMAC Channel x [x = 0..7] Control B Register” on page 494
•
“DMAC Channel x [x = 0..7] Configuration Register” on page 496
•
“DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register” on page 498
•
“DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register” on page 499
• WPKEY: Write Protect KEY
Should be written at value 0x444D41 (“DMA” in ASCII). Writing any other value in this field aborts the write operation of the
WPEN bit. Always reads as 0.
SAM9X35 [DATASHEET]
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31.7.22 DMAC Write Protect Status Register
Name:
Address:
Access:
Reset:
DMAC_WPSR
0xFFFFEDE8 (0), 0xFFFFEFE8 (1)
Read-only
See
31
—
30
—
29
—
23
15
22
14
21
13
28
—
27
—
20
WPVSRC
19
12
WPVSRC
11
4
—
3
—
26
—
18
10
25
—
17
9
24
—
16
8
7
—
6
—
5
—
2
—
1
—
0
WPVS
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the DMAC_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the DMAC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted.
Note: Reading DMAC_WPSR automatically clears all fields.
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32.
USB High Speed Device Port (UDPHS)
32.1 Description
The USB High Speed Device Port (UDPHS) is compliant with the Universal Serial Bus (USB), rev 2.0 High Speed device specification.
Each endpoint can be configured in one of several USB transfer types. It can be associated with one, two or three banks of a Dual-port RAM used to store the current data payload. If two or three banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral. This feature is mandatory for isochronous endpoints.
32.2 Embedded Characteristics
1 Device High Speed
1 UTMI transceiver shared between Host and Device
USB v2.0 High Speed Compliant, 480 Mbits Per Second
7 Endpoints up to 1024 bytes
Embedded Dual-port RAM for Endpoints
Suspend/Resume Logic (Command of UTMI)
Up to Three Memory Banks for Endpoints (Not for Control Endpoint)
4 Kbytes of DPRAM
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32.3 Block Diagram
Figure 32-1. Block Diagram
APB bus
APB
Interf a ce
AHB1
DMA
AHB0 ctrl s t a t us
Rd/Wr/Re a dy
U S B2.0
CORE
AHB bus
AHB bus
AHB
S witch
Loc a l
AHB
S l a ve interf a ce
EPT
Alloc
3 2 b it s
DPRAM
16/ 8 b it s
S y s tem Clock
Dom a in
U S B Clock
Dom a in
PMC
UTMI
DH S DP
DH S DM
DF S DP
DF S DM
DP
DM
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32.4 Typical Connection
Figure 32-2. Board Schematic
22k Ω
(1)
15k
Ω (1)
"B" Recept a cle
1 = VBU S
2 = D-
3 = D+
4 = GND
1 2
C
RPB
3 4
S hell = S hield
C
RPB
:1 µ F to 10 µ F
3 9 ± 1%
Ω
3 9 ± 1%
Ω
6K 8 ± 1%
Ω
10 pF
PIO (VBU S DETECT)
DH S DM
DF S DM
DH S DP
DF S DP
VBG
GNDUTMI
Note: The values shown on the 22 k Ω and 15 k Ω resistors are only valid with 3V3 supplied PIOs.
Both 39 Ω resistors need to be placed as close to the device pins as possible.
32.5 Product Dependencies
32.5.1 Power Management
The UDPHS is not continuously clocked.
For using the UDPHS, the programmer must first enable the UDPHS Clock in the Power Management Controller
(PMC_PCER register). Then enable the PLL (PMC_UCKR register).
However, if the application does not require UDPHS operations, the UDPHS clock can be stopped when not needed and restarted later.
32.5.2 Interrupt
The UDPHS interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the UDPHS
Table 32-1. Peripheral IDs
Instance ID
UDPHS 23 interrupt requires the Interrupt Controller to be programmed first.
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32.6 Functional Description
32.6.1 UTMI Transceivers Sharing
The High Speed USB Host Port A is shared with the High Speed USB Device port and connected to the second UTMI transceiver. The selection between Host Port A and USB Device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL control register.
Figure 32-3. USB Selection
Other
Transceivers
HS
Transceiver
EN_UDPHS
Others Ports
HS USB Host
HS EHCI
FS OHCI
PA
DMA
0 1
HS
USB
Device
DMA
32.6.2 USB V2.0 High Speed Device Port Introduction
The USB V2.0 High Speed Device Port provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB Device through a set of communication flows.
32.6.3 USB V2.0 High Speed Transfer Types
A communication flow is carried over one of four transfer types defined by the USB device.
A device provides several logical communication pipes with the host. To each logical pipe is associated an endpoint.
Transfer through a pipe belongs to one of the four transfer types:
Control Transfers: Used to configure a device at attach time and can be used for other device-specific purposes, including control of other pipes on the device.
Bulk Data Transfers: Generated or consumed in relatively large burst quantities and have wide dynamic latitude in transmission constraints.
Interrupt Data Transfers: Used for timely but reliable delivery of data, for example, characters or coordinates with human-perceptible echo or feedback response characteristics.
Isochronous Data Transfers: Occupy a prenegotiated amount of USB bandwidth with a prenegotiated delivery latency. (Also called streaming real time transfers.)
As indicated below, transfers are sequential events carried out on the USB bus.
Endpoints must be configured according to the transfer type they handle.
Table 32-2. USB Communication Flow
Transfer
Control
Direction
Bidirectional
Isochronous
Interrupt
Bulk
Unidirectional
Unidirectional
Unidirectional
Bandwidth
Not guaranteed
Guaranteed
Not guaranteed
Not guaranteed
Endpoint Size
8, 16, 32, 64
8-1024
8-1024
8-512
Error Detection
Yes
Yes
Yes
Yes
Retrying
Automatic
No
Yes
Yes
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32.6.4 USB Transfer Event Definitions
A transfer is composed of one or several transactions;
Table 32-3. USB Transfer Events
CONTROL
(bidirectional)
Control Transfers
IN
(device toward host)
OUT
(host toward device)
Bulk IN Transfer
Interrupt IN Transfer
Isochronous IN Transfer
Bulk OUT Transfer
Interrupt OUT Transfer
Isochronous OUT Transfer
• Setup transaction → Data IN transactions ∅ Status OUT transaction
•
Setup transaction → Data OUT transactions ∅ Status IN transaction
• Setup transaction → Status IN transaction
•
Data IN transaction → Data IN transaction
•
Data IN transaction → Data IN transaction
•
Data IN transaction → Data IN transaction
•
Data OUT transaction → Data OUT transaction
•
Data OUT transaction → Data OUT transaction
•
Data OUT transaction → Data OUT transaction
Notes: 1. Control transfer must use endpoints with one bank and can be aborted using a stall handshake.
2. Isochronous transfers must use endpoints configured with two or three banks.
An endpoint handles all transactions related to the type of transfer for which it has been configured.
4
5
6
1
2
3
Table 32-4. UDPHS Endpoint Description
Endpoint #
0
Mnemonic
EPT_0
Nb Bank
1
EPT_1
EPT_2
EPT_3
2
2
3
EPT_4
EPT_5
EPT_6
3
3
3
DMA
N
Y
Y
Y
Y
Y
Y
High Band
Width
N
Y
Y
N
N
Y
Y
Max. Endpoint Size
64
1024
1024
1024
1024
1024
1024
Endpoint Type
Control
/Interrupt
/Interrupt
/Interrupt
/Interrupt
/Interrupt
/Interrupt
Note: 1. In Isochronous Mode (Iso), it is preferable that High Band Width capability is available.
The size of internal DPRAM is 4 KB.
Suspend and resume are automatically detected by the UDPHS device, which notifies the processor by raising an interrupt.
32.6.5 USB V2.0 High Speed BUS Transactions
Each transfer results in one or more transactions over the USB bus.
There are five kinds of transactions flowing across the bus in packets:
1.
Setup Transaction
2.
Data IN Transaction
3.
Data OUT Transaction
4.
Status IN Transaction
5.
Status OUT Transaction
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Figure 32-4. Control Read and Write Sequences
Setup Stage Data Stage
Control Write
Setup TX
Setup Stage
Data OUT TX Data OUT TX
Data Stage
Status Stage
Status IN TX
Status Stage
Control Read
Setup TX
Setup Stage
Data IN TX
Status Stage
Data IN TX
Status OUT TX
No Data
Control
Setup TX Status IN TX
A status IN or OUT transaction is identical to a data IN or OUT transaction.
32.6.6 Endpoint Configuration
The endpoint 0 is always a control endpoint, it must be programmed and active in order to be enabled when the End Of
Reset interrupt occurs.
To configure the endpoints:
Fill the configuration register (UDPHS_EPTCFG) with the endpoint size, direction (IN or OUT), type (CTRL, Bulk,
IT, ISO) and the number of banks.
Fill the number of transactions (NB_TRANS) for isochronous endpoints.
Note: For control endpoints the direction has no effect.
Verify that the EPT_MAPD flag is set. This flag is set if the endpoint size and the number of banks are correct compared to the FIFO maximum capacity and the maximum number of allowed banks.
Configure control flags of the endpoint and enable it in UDPHS_EPTCTLENBx according to
Control Disable Register (Isochronous Endpoint)” on page 546 .
Control endpoints can generate interrupts and use only 1 bank.
All endpoints (except endpoint 0) can be configured either as Bulk, Interrupt or Isochronous. See
.
The maximum packet size they can accept corresponds to the maximum endpoint size.
Note: The endpoint size of 1024 is reserved for isochronous endpoints.
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The size of the DPRAM is 4 KB. The DPR is shared by all active endpoints. The memory size required by the active endpoints must not exceed the size of the DPRAM.
SIZE_DPRAM = SIZE _EPT0
+ NB_BANK_EPT1 x SIZE_EPT1
+ NB_BANK_EPT2 x SIZE_EPT2
+ NB_BANK_EPT3 x SIZE_EPT3
+ NB_BANK_EPT4 x SIZE_EPT4
+ NB_BANK_EPT5 x SIZE_EPT5
+ NB_BANK_EPT6 x SIZE_EPT6
+... (refer to 32.7.8 UDPHS Endpoint Configuration Register )
If a user tries to configure endpoints with a size the sum of which is greater than the DPRAM, then the EPT_MAPD is not set.
The application has access to the physical block of DPR reserved for the endpoint through a 64 KB logical address space.
The physical block of DPR allocated for the endpoint is remapped all along the 64 KB logical address space. The application can write a 64 KB buffer linearly.
Figure 32-5. Logical Address Space for DPR Access
DPR
8 to 64 B
Logical address
1 bank
64 KB
EP0
8 to 64 B
64 KB
EP1
8 to1024 B
8 to1024 B
8 to1024 B
...
8 to1024 B x banks y banks
64 KB
EP2
64 KB
EP3
...
8 to1024 B z banks
Configuration examples of UDPHS_EPTCTLx (
UDPHS Endpoint Control Disable Register (Isochronous Endpoint) ) for
Bulk IN endpoint type follow below.
With DMA
AUTO_VALID: Automatically validate the packet and switch to the next bank.
EPT_ENABL: Enable endpoint.
Without DMA:
TXRDY: An interrupt is generated after each transmission.
EPT_ENABL: Enable endpoint.
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Configuration examples of Bulk OUT endpoint type follow below.
With DMA
AUTO_VALID: Automatically validate the packet and switch to the next bank.
EPT_ENABL: Enable endpoint.
Without DMA
RXRDY_TXKL: An interrupt is sent after a new packet has been stored in the endpoint FIFO.
EPT_ENABL: Enable endpoint.
32.6.7 DPRAM Management
Endpoints can only be allocated in ascending order, from the endpoint 0 to the last endpoint to be allocated. The user shall therefore configure them in the same order.
The allocation of an endpoint x starts when the Number of Banks field in the UDPHS Endpoint Configuration Register
(UDPHS_EPTCFGx.BK_NUMBER) is different from zero. Then, the hardware allocates a memory area in the DPRAM and inserts it between the x-1 and x+1 endpoints. The x+1 endpoint memory window slides up and its data is lost. Note that the following endpoint memory windows (from x+2) do not slide.
Disabling an endpoint, by writing a one to the Endpoint Disable bit in the UDPHS Endpoint Control Disable Register
(UDPHS_EPTCTLDISx.EPT_DISABL), does not reset its configuration:
The Endpoint Banks (UDPHS_EPTCFGx.BK_NUMBER),
The Endpoint Size (UDPHS_EPTCFGx.EPT_SIZE),
The Endpoint Direction (UDPHS_EPTCFGx.EPT_DIR), and
The Endpoint Type (UDPHS_EPTCFGx.EPT_TYPE).
To free its memory, the user shall write a zero to the UDPHS_EPTCFGx.BK_NUMBER field. The x+1 endpoint memory window then slides down and its data is lost. Note that the following endpoint memory windows (from x+2) do not slide.
Figure 32-6. Allocation and Reorganization of the DPRAM
Free Memory
EPT5
EPT4
EPT3
EPT2
Free Memory
EPT5
EPT4
EPT3
(always allocated)
EPT2
Free Memory
EPT5
EPT4 Lost Memory
EPT4
EPT2
Free Memory
EPT5
EPT4
EPT3 (larger size)
EPT2
Conflict
EPT1 EPT1 EPT1 EPT1
EPT0 EPT0 EPT0
Device:
UDPH S _EPTCTLENBx.EPT_ENABL = 1
UDPH S _EPTCFGx.BK_NUMBER
<>
0
Device: Device:
UDPH S _EPTCTLDI S3 .EPT_DI
S ABL = 1 UDPH S _EPTCFG 3 .BK_NUMBER
=
0
EPT0
Device:
UDPH S _EPTCTLENB 3 .EPT_ENABL = 1
UDPH S _EPTCFG 3 .BK_NUMBER
<>
0
Endpoints 0..5
Activated
Endpoint 3
Disabled
Endpoint 3
Memory Freed
Endpoint 3
Activated
1.
The endpoints 0 to 5 are enabled, configured and allocated in ascending order.
Each endpoint then owns a memory area in the DPRAM.
2.
The endpoint 3 is disabled, but its memory is kept allocated by the controller.
3.
In order to free its memory, its UDPHS_EPTCFGx.BK_NUMBER field is written to zero. The endpoint 4 memory window slides down, but the endpoint 5 does not move.
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4.
If the user chooses to reconfigure the endpoint 3 with a larger size, the controller allocates a memory area after the endpoint 2 memory area and automatically slides up the endpoint 4 memory window. The endpoint 5 does not move and a memory conflict appears as the memory windows of the endpoints 4 and 5 overlap. The data of these endpoints is potentially lost.
Notes: 1. There is no way the data of the endpoint 0 can be lost (except if it is de-allocated) as the memory allocation and de-allocation may affect only higher endpoints.
2. Deactivating then reactivating the same endpoint with the same configuration only modifies temporarily the controller DPRAM pointer and size for this endpoint. Nothing changes in the DPRAM, higher endpoints seem not to have been moved and their data is preserved as far as nothing has been written or received into them while changing the allocation state of the first endpoint.
3. When the user writes a value different from zero to the UDPHS_EPTCFGx.BK_NUMBER field, the Endpoint
Mapped bit (UDPHS_EPTCFGx.EPT_MAPD) is set only if the configured size and number of banks are correct as compared to the endpoint maximal allowed values and to the maximal FIFO size (i.e. the DPRAM size). The UDPHS_EPTCFGx.EPT_MAPD value does not consider memory allocation conflicts.
32.6.8 Transfer With DMA
USB packets of any length may be transferred when required by the UDPHS Device. These transfers always feature sequential addressing.
Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance boost with paged memories. These clock-cycle consuming memory row (or bank) changes will then likely not occur, or occur only once instead of dozens times, during a single big USB packet DMA transfer in case another AHB master addresses the memory. This means up to 128-word single-cycle unbroken AHB bursts for Bulk endpoints and 256-word single-cycle unbroken bursts for isochronous endpoints. This maximum burst length is then controlled by the lowest programmed
USB endpoint size (EPT_SIZE field in the UDPHS_EPTCFGx register) and DMA Size (BUFF_LENGTH field in the
UDPHS_DMACONTROLx register).
The USB 2.0 device average throughput may be up to nearly 60 MBytes. Its internal slave average access latency decreases as burst length increases due to the 0 wait-state side effect of unchanged endpoints. If at least 0 wait-state word burst capability is also provided by the external DMA AHB bus slaves, each of both DMA AHB busses need less than 50% bandwidth allocation for full USB 2.0 bandwidth usage at 30 MHz, and less than 25% at 60 MHz.
Note: In case of debug, be careful to address the DMA to an SRAM address even if a remap is done.
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Figure 32-7. Example of DMA Chained List
Transfer Descriptor
UDPHS Registers
(Current Transfer Descriptor) Next Descriptor Address
UDPHS Next Descriptor
DMA Channel Address
DMA Channel Control
DMA Channel Address
DMA Channel Control
Transfer Descriptor
Next Descriptor Address
DMA Channel Address
DMA Channel Control
Transfer Descriptor
Next Descriptor Address
DMA Channel Address
DMA Channel Control
Memory Area
Data Buff 1
Null
Data Buff 2
Data Buff 3
32.6.9 Transfer Without DMA
Important. If the DMA is not to be used, it is necessary that it be disabled because otherwise it can be enabled by previous versions of software without warning . If this should occur, the DMA can process data before an interrupt without knowledge of the user.
The recommended means to disable DMA is as follows:
// Reset IP UDPHS
AT91C_BASE_UDPHS->UDPHS_CTRL &= ~AT91C_UDPHS_EN_UDPHS;
AT91C_BASE_UDPHS->UDPHS_CTRL |= AT91C_UDPHS_EN_UDPHS;
// With OR without DMA !!!
for( i=1; i<=((AT91C_BASE_UDPHS->UDPHS_IPFEATURES &
AT91C_UDPHS_DMA_CHANNEL_NBR)>>4); i++ ) {
// RESET endpoint canal DMA:
// DMA stop channel command
AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command
// Disable endpoint
AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLDIS |= 0XFFFFFFFF;
// Reset endpoint config
AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLCFG = 0;
// Reset DMA channel (Buff count and Control field)
AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0x02; // NON
STOP command
// Reset DMA channel 0 (STOP)
AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command
// Clear DMA channel status (read the register for clear it)
AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS =
AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS;
}
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32.6.10 Handling Transactions with USB V2.0 Device Peripheral
32.6.10.1 Setup Transaction
The setup packet is valid in the DPR while RX_SETUP is set. Once RX_SETUP is cleared by the application, the
UDPHS accepts the next packets sent over the device endpoint.
When a valid setup packet is accepted by the UDPHS:
The UDPHS device automatically acknowledges the setup packet (sends an ACK response)
Payload data is written in the endpoint
Sets the RX_SETUP interrupt
The BYTE_COUNT field in the UDPHS_EPTSTAx register is updated
An endpoint interrupt is generated while RX_SETUP in the UDPHS_EPTSTAx register is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint.
Thus, firmware must detect RX_SETUP polling UDPHS_EPTSTAx or catching an interrupt, read the setup packet in the
FIFO, then clear the RX_SETUP bit in the UDPHS_EPTCLRSTA register to acknowledge the setup stage.
If STALL_SNT was set to 1, then this bit is automatically reset when a setup token is detected by the device. Then, the device still accepts the setup stage. (See
Section 32.6.10.15 “STALL” on page 521 ).
32.6.10.2 NYET
NYET is a High Speed only handshake. It is returned by a High Speed endpoint as part of the PING protocol.
High Speed devices must support an improved NAK mechanism for Bulk OUT and control endpoints (except setup stage). This mechanism allows the device to tell the host whether it has sufficient endpoint space for the next OUT transfer (see USB 2.0 spec 8.5.1 NAK Limiting via Ping Flow Control).
The NYET/ACK response to a High Speed Bulk OUT transfer and the PING response are automatically handled by hardware in the UDPHS_EPTCTLx register (except when the user wants to force a NAK response by using the
NYET_DIS bit).
If the endpoint responds instead to the OUT/DATA transaction with an NYET handshake, this means that the endpoint accepted the data but does not have room for another data payload. The host controller must return to using a PING token until the endpoint indicates it has space available.
Figure 32-8. NYET Example with Two Endpoint Banks data 0 ACK data 1 NYET PING ACK data 0 NYET PING NACK PING ACK t = 0 t = 125 µs t = 250 µs t = 375 µs t = 500 µs t = 625 µs E: empty
E': begin to empty
F: full
Bank 1
Bank 0
E
F
Bank 1 F
Bank 0 E'
Bank 1
Bank 0
F
E
Bank 1
Bank 0
F
E
Bank 1
Bank 0
F
F
Bank 1
Bank 0
E'
F
Bank 1
Bank 0
E
F
32.6.10.3 Data IN
32.6.10.4 Bulk IN or Interrupt IN
Data IN packets are sent by the device during the data or the status stage of a control transfer or during an
(interrupt/bulk/isochronous) IN transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel.
There are three ways for an application to transfer a buffer in several packets over the USB:
Packet by packet (see 32.6.10.5
64 KB (see
below)
DMA (see
below)
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32.6.10.5 Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)
The application can write one or several banks.
A simple algorithm can be used by the application to send packets regardless of the number of banks associated to the endpoint.
Algorithm Description for Each Packet:
The application waits for TXRDY flag to be cleared in the UDPHS_EPTSTAx register before it can perform a write access to the DPR.
The application writes one USB packet of data in the DPR through the 64 KB endpoint logical memory window.
The application sets TXRDY flag in the UDPHS_EPTSETSTAx register.
The application is notified that it is possible to write a new packet to the DPR by the TXRDY interrupt. This interrupt can be enabled or masked by setting the TXRDY bit in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register.
Algorithm Description to Fill Several Packets:
Using the previous algorithm, the application is interrupted for each packet. It is possible to reduce the application overhead by writing linearly several banks at the same time. The AUTO_VALID bit in the UDPHS_EPTCTLx must be set by writing the AUTO_VALID bit in the UDPHS_EPTCTLENBx register.
The auto-valid-bank mechanism allows the transfer of data (IN and OUT) without the intervention of the CPU. This means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware.
The application checks the BUSY_BANK_STA field in the UDPHS_EPTSTAx register. The application must wait that at least one bank is free.
The application writes a number of bytes inferior to the number of free DPR banks for the endpoint. Each time the application writes the last byte of a bank, the TXRDY signal is automatically set by the UDPHS.
If the last packet is incomplete (i.e., the last byte of the bank has not been written) the application must set the
TXRDY bit in the UDPHS_EPTSETSTAx register.
The application is notified that all banks are free, so that it is possible to write another burst of packets by the
BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the BUSY_BANK flag in the
UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers.
This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism does not operate.
A Zero Length Packet can be sent by setting just the TXRDY flag in the UDPHS_EPTSETSTAx register.
32.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)
The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buffer from the memory to the DPR or from the DPR to the processor memory under the UDPHS control. The DMA can be used for all transfer types except control transfer.
Example DMA configuration:
1.
Program UDPHS_DMAADDRESS x with the address of the buffer that should be transferred.
2.
Enable the interrupt of the DMA in UDPHS_IEN
3.
Program UDPHS_ DMACONTROLx:
Size of buffer to send: size of the buffer to be sent to the host.
END_B_EN: The endpoint can validate the packet (according to the values programmed in the
AUTO_VALID and SHRT_PCKT fields of UDPHS_EPTCTLx.) (See “UDPHS Endpoint Control Disable
Register (Isochronous Endpoint)” on page 546 and
Figure 32-13. Autovalid with DMA )
END_BUFFIT: generate an interrupt when the BUFF_COUNT in UDPHS_DMASTATUSx reaches 0.
CHANN_ENB: Run and stop at end of buffer
The auto-valid-bank mechanism allows the transfer of data (IN & OUT) without the intervention of the CPU. This means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware.
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A transfer descriptor can be used. Instead of programming the register directly, a descriptor should be programmed and the address of this descriptor is then given to UDPHS_DMANXTDSC to be processed after setting the LDNXT_DSC field
(Load Next Descriptor Now) in UDPHS_DMACONTROLx register.
The structure that defines this transfer descriptor must be aligned.
Each buffer to be transferred must be described by a DMA Transfer descriptor (see
fetch a new transfer descriptor from the memory address pointed by the UDPHS_DMANXTDSCx register. Once the transfer is complete, the transfer status is updated in the UDPHS_DMASTATUSx register.
To chain a new transfer descriptor with the current DMA transfer, the DMA channel must be stopped.
To do so,
INTDIS_DMA and TXRDY may be set in the UDPHS_EPTCTLENBx register.
It is also possible for the application to wait for the completion of all transfers. In this case the LDNXT_DSC field in the last transfer descriptor
UDPHS_DMACONTROLx register must be set to 0 and CHANN_ENB set to 1.
Then the application can chain a new transfer descriptor.
The INTDIS_DMA can be used to stop the current DMA transfer if an enabled interrupt is triggered. This can be used to stop DMA transfers in case of errors.
The application can be notified at the end of any buffer transfer (ENB_BUFFIT bit in the UDPHS_DMACONTROLx register).
Figure 32-9. Data IN Transfer for Endpoint with One Bank
Prevous Data IN TX Microcontroller Loads Data in FIFO Data is Sent on USB Bus
USB Bus
Packets
Token IN Data IN 1 ACK Token IN NAK Token IN Data IN 2 ACK
TXRDY
Flag
(UDPHS_EPTSTAx) Set by firmware
TX_COMPLT Flag
(UDPHS_EPTSTAx)
FIFO
Content
Cleared by hardware Set by the firmware Cleared by hardware
Data IN 1
Set by hardware
Interrupt Pending
DPR access by firmware
Load in progress
Interrupt Pending
Cleared by firmware
Payload in FIFO
DPR access by hardware
Data IN 2
Cleared by firmware
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Figure 32-10.Data IN Transfer for Endpoint with Two Banks
Microcontroller
Load Data IN Bank 0
Microcontroller Load Data IN Bank 1
UDPHS Device Send Bank 0
USB Bus
Packets
Token IN Data IN
Set by Firmware,
Data Payload Written in FIFO Bank 0
Cleared by Hardware switch to next bank
Virtual TXRDY bank 0
(UDPHS_EPTSTAx)
Virtual TXRDY bank 1
(UDPHS_EPTSTAx)
ACK
Microcontroller Load Data IN Bank 0
UDPHS Device Send Bank 1
Token IN
Cleared by Hardware
Data Payload Fully Transmitted
Data IN
TX_COMPLT
Flag
(UDPHS_EPTSTAx)
Set by Hardware
ACK
Interrupt Pending
Set by Firmware,
Data Payload Written in FIFO Bank 1
Set by Hardware
Interrupt Cleared by Firmware
FIFO
(DPR)
Bank 0
Written by
Microcontroller
Read by USB Device
Written by
Microcontroller
FIFO
(DPR)
Bank1
Written by
Microcontroller
Read by UDPHS Device
Figure 32-11.Data IN Followed By Status OUT Transfer at the End of a Control Transfer
Device Sends the Last
Data Payload to Host
Device Sends a
Status OUT to Host
USB Bus
Packets
Token IN Data IN ACK Token OUT Data OUT (ZLP) ACK Token OUT
RXRDY
(UDPHS_EPTSTAx)
Data OUT (ZLP) ACK
Interrupt
Pending
Set by Hardware
Cleared by Firmware
TX_COMPLT
(UDPHS_EPTSTAx)
Note:
Set by Hardware Cleared by Firmware
A NAK handshake is always generated at the first status stage token.
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Figure 32-12.Data OUT Followed by Status IN Transfer
Host Sends the Last
Data Payload to the Device
Device Sends a Status IN to the Host
USB Bus
Packets
Token OUT Data OUT ACK Token IN
Interrupt Pending
Data IN ACK
RXRDY
(UDPHS_EPTSTAx)
Cleared by Firmware
Set by Hardware
TXRDY
(UDPHS_EPTSTAx)
Set by Firmware Clear by Hardware
Note: Before proceeding to the status stage, the software should determine that there is no risk of extra data from the host
(data stage). If not certain (non-predictable data stage length), then the software should wait for a NAK-IN interrupt before proceeding to the status stage. This precaution should be taken to avoid collision in the FIFO.
Figure 32-13.Autovalid with DMA
Bank (system) Bank 0 Bank 1 Bank 0 Bank 1
Write write bank 0 write bank 1 bank 0 is full bank 1 is full write bank 0 bank 0 is full
Bank 1 Bank 0
Bank (usb) Bank 0
IN data 0
Bank 1
IN data 1 IN data 0
Bank 0
Bank 1
Virtual TXRDY Bank 0
Note:
Virtual TXRDY Bank 1
TXRDY
(Virtual 0 & Virtual 1)
In the illustration above Autovalid validates a bank as full, although this might not be the case, in order to continue processing data and to send to DMA.
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32.6.10.7 Isochronous IN
Isochronous-IN is used to transmit a stream of data whose timing is implied by the delivery rate. Isochronous transfer provides periodic, continuous communication between host and device.
It guarantees bandwidth and low latencies appropriate for telephony, audio, video, etc.
If the endpoint is not available (TXRDY_TRER = 0), then the device does not answer to the host. An ERR_FL_ISO interrupt is generated in the UDPHS_EPTSTAx register and once enabled, then sent to the CPU.
The STALL_SNT command bit is not used for an ISO-IN endpoint.
32.6.10.8 High Bandwidth Isochronous Endpoint Handling: IN Example
For high bandwidth isochronous endpoints, the DMA can be programmed with the number of transactions
(BUFF_LENGTH field in UDPHS_DMACONTROLx) and the system should provide the required number of packets per microframe, otherwise, the host will notice a sequencing problem.
A response should be made to the first token IN recognized inside a microframe under the following conditions:
If at least one bank has been validated, the correct DATAx corresponding to the programmed Number Of
Transactions per Microframe (NB_TRANS) should be answered. In case of a subsequent missed or corrupted token IN inside the microframe, the USB 2.0 Core available data bank(s) that should normally have been transmitted during that microframe shall be flushed at its end. If this flush occurs, an error condition is flagged
(ERR_FLUSH is set in UDPHS_EPTSTAx).
If no bank is validated yet, the default DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in
UDPHS_EPTSTAx). Then, no data bank is flushed at microframe end.
If no data bank has been validated at the time when a response should be made for the second transaction of
NB_TRANS = 3 transactions microframe, a DATA1 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). If and only if remaining untransmitted banks for that microframe are available at its end, they are flushed and an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx).
If no data bank has been validated at the time when a response should be made for the last programmed transaction of a microframe, a DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in
UDPHS_EPTSTAx). If and only if the remaining untransmitted data bank for that microframe is available at its end, it is flushed and an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx).
If at the end of a microframe no valid token IN has been recognized, no data bank is flushed and no error condition is reported.
At the end of a microframe in which at least one data bank has been transmitted, if less than NB_TRANS banks have been validated for that microframe, an error condition is flagged (ERR_TRANS is set in UDPHS_EPTSTAx).
Cases of Error (in UDPHS_EPTSTAx)
ERR_FL_ISO: There was no data to transmit inside a microframe, so a ZLP is answered by default.
ERR_FLUSH: At least one packet has been sent inside the microframe, but the number of token IN received is lesser than the number of transactions actually validated (TXRDY_TRER) and likewise with the NB_TRANS programmed.
ERR_TRANS: At least one packet has been sent inside the microframe, but the number of token IN received is lesser than the number of programmed NB_TRANS transactions and the packets not requested were not validated.
ERR_FL_ISO + ERR_FLUSH: At least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token IN.
ERR_FL_ISO + ERR_TRANS: At least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token IN and the data can be discarded at the microframe end.
ERR_FLUSH + ERR_TRANS: The first token IN has been answered and it was the only one received, a second bank has been validated but not the third, whereas NB_TRANS was waiting for three transactions.
ERR_FL_ISO + ERR_FLUSH + ERR_TRANS: The first token IN has been treated, the data for the second Token
IN was not available in time, but the second bank has been validated before the end of the microframe. The third bank has not been validated, but three transactions have been set in NB_TRANS.
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32.6.10.9 Data OUT
32.6.10.10 Bulk OUT or Interrupt OUT
Like data IN, data OUT packets are sent by the host during the data or the status stage of control transfer or during an interrupt/bulk/isochronous OUT transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel.
32.6.10.11 Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device)
Algorithm Description for Each Packet:
The application enables an interrupt on RXRDY_TXKL.
When an interrupt on RXRDY_TXKL is received, the application knows that UDPHS_EPTSTAx register
BYTE_COUNT bytes have been received.
The application reads the BYTE_COUNT bytes from the endpoint.
The application clears RXRDY_TXKL.
Note: If the application does not know the size of the transfer, it may not be a good option to use AUTO_VALID.
Because if a zero-length-packet is received, the RXRDY_TXKL is automatically cleared by the AUTO_VALID hardware and if the endpoint interrupt is triggered, the software will not find its originating flag when reading the
UDPHS_EPTSTAx register.
Algorithm to Fill Several Packets:
The application enables the interrupts of BUSY_BANK and AUTO_VALID.
When a BUSY_BANK interrupt is received, the application knows that all banks available for the endpoint have been filled. Thus, the application can read all banks available.
If the application doesn’t know the size of the receive buffer, instead of using the BUSY_BANK interrupt, the application must use RXRDY_TXKL.
32.6.10.12 Bulk OUT or Interrupt OUT: Sending a Buffer Using DMA (Host To Device)
To use the DMA setting, the AUTO_VALID field is mandatory.
See 32.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)
for more information.
DMA Configuration Example:
1.
First program UDPHS_DMAADDRESSx with the address of the buffer that should be transferred.
2.
Enable the interrupt of the DMA in UDPHS_IEN
3.
Program the DMA Channelx Control Register:
Size of buffer to be sent.
END_B_EN: Can be used for OUT packet truncation (discarding of unbuffered packet data) at the end of
DMA buffer.
END_BUFFIT: Generate an interrupt when BUFF_COUNT in the UDPHS_DMASTATUSx register reaches
0.
END_TR_EN: End of transfer enable, the UDPHS device can put an end to the current DMA transfer, in case of a short packet.
END_TR_IT: End of transfer interrupt enable, an interrupt is sent after the last USB packet has been transferred by the DMA, if the USB transfer ended with a short packet. (Beneficial when the receive size is unknown.)
CHANN_ENB: Run and stop at end of buffer.
For OUT transfer, the bank will be automatically cleared by hardware when the application has read all the bytes in the bank (the bank is empty).
Notes: 1. When a zero-length-packet is received, RXRDY_TXKL bit in UDPHS_EPTSTAx is cleared automatically by
AUTO_VALID, and the application knows of the end of buffer by the presence of the END_TR_IT.
2. If the host sends a zero-length packet, and the endpoint is free, then the device sends an ACK. No data is written in the endpoint, the RXRDY_TXKL interrupt is generated, and the BYTE_COUNT field in
UDPHS_EPTSTAx is null.
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Figure 32-14.Data OUT Transfer for Endpoint with One Bank
Host Sends Data Payload
Microcontroller Transfers Data
Host Sends the Next Data Payload Host Resends the Next Data Payload
USB Bus
Packets
Token OUT Data OUT 1 ACK Token OUT Data OUT 2 NAK Token OUT Data OUT 2 ACK
RXRDY
(UDPHS_EPTSTAx)
Interrupt Pending
Set by Hardware
FIFO (DPR)
Content
Data OUT 1 Data OUT 1
Written by UDPHS Device Microcontroller Read
Cleared by Firmware,
Data Payload Written in FIFO
Data OUT 2
Written by UDPHS Device
Figure 32-15.Data OUT Transfer for an Endpoint with Two Banks
Host sends first data payload
Microcontroller reads Data 1 in bank 0,
Host sends second data payload
USB Bus
Packets
Token OUT Data OUT 1 ACK Token OUT
Microcontroller reads Data 2 in bank 1,
Host sends third data payload
Data OUT 2 ACK Token OUT Data OUT 3
Virtual RXRDY
Bank 0
Set by Hardware,
Data payload written in FIFO endpoint bank 0
Interrupt pending
Set by Hardware
Data Payload written in FIFO endpoint bank 1
Cleared by Firmware
Virtual RXRDY
Bank 1
RXRDY = (virtual bank 0 | virtual bank 1)
(UDPHS_EPTSTAx)
FIFO (DPR)
Bank 0 Data OUT 1
Write by UDPHS Device
Data OUT 1
Read by Microcontroller
FIFO (DPR)
Bank 1 Data OUT 2
Write by Hardware
Interrupt pending
Data OUT 3
Data OUT 2
Read by Microcontroller
Cleared by Firmware
Write in progress
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32.6.10.13 High Bandwidth Isochronous Endpoint OUT
Figure 32-16.Bank Management, Example of Three Transactions per Microframe
USB bus
Transactions
MDATA0 MDATA1 DATA2 MDATA0 MDATA1 DATA2 t = 0 t = 52.5 µs
(40 % of 125 µs) t = 125 µs
RXRDY
USB line
RXRDY
Microcontroller FIFO
(DPR) Access
Read Bank 1 Read Bank 2 Read Bank 3 Read Bank 1
USB 2.0 supports individual High Speed isochronous endpoints that require data rates up to 192 Mb/s (24 MB/s): 3x1024 data bytes per microframe.
To support such a rate, two or three banks may be used to buffer the three consecutive data packets. The microcontroller
(or the DMA) should be able to empty the banks very rapidly (at least 24 MB/s on average).
NB_TRANS field in UDPHS_EPTCFGx register = Number Of Transactions per Microframe.
If NB_TRANS > 1 then it is High Bandwidth.
Example:
If NB_TRANS = 3, the sequence should be either
MData0
MData0/Data1
MData0/Data1/Data2
If NB_TRANS = 2, the sequence should be either
MData0
MData0/Data1
If NB_TRANS = 1, the sequence should be
Data0
32.6.10.14 Isochronous Endpoint Handling: OUT Example
The user can ascertain the bank status (free or busy), and the toggle sequencing of the data packet for each bank with the UDPHS_EPTSTAx register in the three bit fields as follows:
TOGGLESQ_STA: PID of the data stored in the current bank
CURBK: Number of the bank currently being accessed by the microcontroller.
BUSY_BANK_STA: Number of busy bank
This is particularly useful in case of a missing data packet.
If the inter-packet delay between the OUT token and the Data is greater than the USB standard, then the ISO-OUT transaction is ignored. (Payload data is not written, no interrupt is generated to the CPU.)
If there is a data CRC (Cyclic Redundancy Check) error, the payload is, none the less, written in the endpoint. The
ERR_CRC_NTR flag is set in UDPHS_EPTSTAx register.
If the endpoint is already full, the packet is not written in the DPRAM. The ERR_FL_ISO flag is set in UDPHS_EPTSTAx.
If the payload data is greater than the maximum size of the endpoint, then the ERR_OVFLW flag is set. It is the task of the CPU to manage this error. The data packet is written in the endpoint (except the extra data).
If the host sends a Zero Length Packet, and the endpoint is free, no data is written in the endpoint, the RXRDY_TXKL flag is set, and the BYTE_COUNT field in UDPHS_EPTSTAx register is null.
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The FRCESTALL command bit is unused for an isochonous endpoint.
Otherwise, payload data is written in the endpoint, the RXRDY_TXKL interrupt is generated and the BYTE_COUNT in
UDPHS_EPTSTAx register is updated.
32.6.10.15 STALL
STALL is returned by a function in response to an IN token or after the data phase of an OUT or in response to a PING transaction. STALL indicates that a function is unable to transmit or receive data, or that a control pipe request is not supported.
OUT
To stall an endpoint, set the FRCESTALL bit in UDPHS_EPTSETSTAx register and after the STALL_SNT flag has been set, set the TOGGLE_SEG bit in the UDPHS_EPTCLRSTAx register.
IN
Set the FRCESTALL bit in UDPHS_EPTSETSTAx register.
Figure 32-17.Stall Handshake Data OUT Transfer
USB Bus
Packets
Token OUT Data OUT Stall PID
FRCESTALL
Set by Firmware Cleared by Firmware
Interrupt Pending
STALL_SNT
Figure 32-18.Stall Handshake Data IN Transfer
USB Bus
Packets
Token IN
Set by Hardware
Stall PID
Cleared by Firmware
FRCESTALL
Set by Firmware
Cleared by Firmware
Interrupt Pending
STALL_SNT
Set by Hardware Cleared by Firmware
32.6.11 Speed Identification
The high speed reset is managed by the hardware.
At the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset.
At the end of the reset process (full or high), the ENDRESET interrupt is generated.
Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of the device.
32.6.12 USB V2.0 High Speed Global Interrupt
Interrupts are defined in
Section 32.7.3 ”UDPHS Interrupt Enable Register” (UDPHS_IEN) and in
”UDPHS Interrupt Status Register” (UDPHS_INTSTA).
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32.6.13 Endpoint Interrupts
Interrupts are enabled in UDPHS_IEN (see Section 32.7.3 ”UDPHS Interrupt Enable Register”
) and individually masked in UDPHS_EPTCTLENBx (see
Section 32.7.9 ”UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt
Table 32-5. Endpoint Interrupt Source Masks
SHRT_PCKT
BUSY_BANK
NAK_OUT
NAK_IN/ERR_FLUSH
STALL_SNT/ERR_CRC_NTR
RX_SETUP/ERR_FL_ISO
TXRDY_TRER
TX_COMPLT
RXRDY_TXKL
ERR_OVFLW
MDATA_RX
DATAX_RX
Short Packet Interrupt
Busy Bank Interrupt
NAKOUT Interrupt
NAKIN/Error Flush Interrupt
Stall Sent/CRC error/Number of Transaction
Error Interrupt
Received SETUP/Error Flow Interrupt
TX Packet Read/Transaction Error Interrupt
Transmitted IN Data Complete Interrupt
Received OUT Data Interrupt
Overflow Error Interrupt
MDATA Interrupt
DATAx Interrupt
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Figure 32-19.UDPHS Interrupt Control Interface
(UDPHS_IEN)
USB Global
IT Sources
DET_SUSPD
MICRO_SOF
INT_SOF
ENDRESET
WAKE_UP
ENDOFRSM
UPSTR_RES
EPT0 IT
Sources
Global IT mask
Global IT sources
(UDPHS_EPTCTLENBx)
SHRT_PCKT
BUSY_BANK
NAK_OUT
NAK_IN/ERR_FLUSH
STALL_SNT/ER_CRC_NTR
RX_SETUP/ERR_FL_ISO
TXRDY_TRER
EP mask
EP sources
TX_COMPLT
RXRDY_TXKL
ERR_OVFLW
MDATA_RX
DATAX_RX
EP mask
EP sources
(UDPHS_IEN)
EPT_0
(UDPHS_IEN)
EPT_x
EPT1-6 IT
Sources husb2dev interrupt
(UDPHS_EPTCTLx)
INTDIS_DMA disable DMA channelx request
DMA CH x
(UDPHS_DMACONTROLx)
EN_BUFFIT mask mask
END_TR_IT mask
DESC_LD_IT
(UDPHS_IEN)
DMA_x
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32.6.14 Power Modes
32.6.14.1 Controlling Device States
A USB device has several possible states. Refer to Chapter 9 (USB Device Framework) of the Universal Serial Bus
Specification, Rev 2.0.
Figure 32-20.UDPHS Device State Diagram
Attached
Hub Reset or
Deconfigured
Hub
Configured
Bus Inactive
Powered
Bus Activity
Power
Interruption
Reset
Reset
Bus Inactive
Default
Bus Activity
Address
Assigned
Bus Inactive
Address
Device
Deconfigured
Bus Activity
Device
Configured
Bus Inactive
Configured
Bus Activity
Suspended
Suspended
Suspended
Suspended
Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0).
After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the
USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 µA on the USB bus.
While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake-up request to the host, e.g., waking up a PC by moving a USB mouse.
The wake-up feature is not mandatory for all devices and must be negotiated with the host.
32.6.14.2 Not Powered State
Self powered devices can detect 5V VBUS using a PIO. When the device is not connected to a host, device power consumption can be reduced by the DETACH bit in UDPHS_CTRL. Disabling the transceiver is automatically done.
HSDM, HSDP, FSDP and FSDP lines are tied to GND pull-downs integrated in the hub downstream ports.
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32.6.14.3 Entering Attached State
When no device is connected, the USB FSDP and FSDM signals are tied to GND by 15 K Ω pull-downs integrated in the hub downstream ports. When a device is attached to an hub downstream port, the device connects a 1.5 K Ω pull-up on
FSDP. The USB bus line goes into IDLE state, FSDP is pulled-up by the device 1.5 K Ω resistor to 3.3V and FSDM is pulled-down by the 15 K Ω resistor to GND of the host.
After pull-up connection, the device enters the powered state. The transceiver remains disabled until bus activity is detected.
In case of low power consumption need, the device can be stopped. When the device detects the VBUS, the software must enable the USB transceiver by enabling the EN_UDPHS bit in UDPHS_CTRL register.
The software can detach the pull-up by setting DETACH bit in UDPHS_CTRL register.
32.6.14.4 From Powered State to Default State (Reset)
After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmasked flag ENDRESET is set in the UDPHS_IEN register and an interrupt is triggered.
Once the ENDRESET interrupt has been triggered, the device enters Default State. In this state, the UDPHS software must:
Enable the default endpoint, setting the EPT_ENABL flag in the UDPHS_EPTCTLENB[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 in EPT_0 of the UDPHS_IEN register. The enumeration then begins by a control transfer.
Configure the Interrupt Mask Register which has been reset by the USB reset detection
Enable the transceiver.
In this state, the EN_UDPHS bit in UDPHS_CTRL register must be enabled.
32.6.14.5 From Default State to Address State (Address Assigned)
After a Set Address standard device request, the USB host peripheral enters the address state.
Warning : before the device enters address state, it must achieve the Status IN transaction of the control transfer, i.e., the
UDPHS device sets its new address once the TX_COMPLT flag in the UDPHS_EPTCTL[0] register has been received and cleared.
To move to address state, the driver software sets the DEV_ADDR field and the FADDR_EN flag in the UDPHS_CTRL register.
32.6.14.6 From Address State to Configured State (Device Configured)
Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the BK_NUMBER, EPT_TYPE, EPT_DIR and
EPT_SIZE fields in the UDPHS_EPTCFGx registers and enabling them by setting the EPT_ENABL flag in the
UDPHS_EPTCTLENBx registers, and, optionally, enabling corresponding interrupts in the UDPHS_IEN register.
32.6.14.7 Entering Suspend State (Bus Activity)
When a Suspend (no bus activity on the USB bus) is detected, the DET_SUSPD signal in the UDPHS_STA register is set. This triggers an interrupt if the corresponding bit is set in the UDPHS_IEN register. This flag is cleared by writing to the UDPHS_CLRINT register. Then the device enters Suspend Mode.
In this state bus powered devices must drain less than 500 µA from the 5V VBUS. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board.
The UDPHS device peripheral clocks can be switched off. Resume event is asynchronously detected.
32.6.14.8 Receiving a Host Resume
In Suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks disabled
(however the pull-up should not be removed).
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Once the resume is detected on the bus, the signal WAKE_UP in the UDPHS_INTSTA is set. It may generate an interrupt if the corresponding bit in the UDPHS_IEN register is set. This interrupt may be used to wake-up the core, enable PLL and main oscillators and configure clocks.
32.6.14.9 Sending an External Resume
In Suspend State it is possible to wake-up the host by sending an external resume.
The device waits at least 5 ms after being entered in Suspend State before sending an external resume.
The device must force a K state from 1 to 15 ms to resume the host.
32.6.15 Test Mode
A device must support the TEST_MODE feature when in the Default, Address or Configured High Speed device states.
TEST_MODE can be:
Test_J
Test_K
Test_Packet
Test_SEO_NAK
(See Section 32.7.7 “UDPHS Test Register” on page 536 for definitions of each test mode.)
const char test_packet_buffer[] = {
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // JKJKJKJK * 9
0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, // JJKKJJKK * 8
0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, // JJKKJJKK * 8
0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, //
JJJJJJJKKKKKKK * 8
0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD, // JJJJJJJK * 8
0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E // {JKKKKKKK *
10}, JK
};
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32.7 USB High Speed Device Port (UDPHS) User Interface
Table 32-6. Register Mapping
Offset
0x00
0x04
0x08 - 0x0C
0x10
0x14
0x18
0x1C
0x20 - 0xCC
0xE0
0xE4 - 0xE8
0x100 + endpoint * 0x20 + 0x00
0x100 + endpoint * 0x20 + 0x04
0x100 + endpoint * 0x20 + 0x08
0x300 + channel * 0x10 + 0x00
0x300 + channel * 0x10 + 0x04
0x300 + channel * 0x10 + 0x08
0x300 + channel * 0x10 + 0x0C
0x310 - 0x370
UDPHS Control Register
UDPHS Frame Number Register
Reserved
UDPHS Interrupt Enable Register
UDPHS Interrupt Status Register
UDPHS Clear Interrupt Register
UDPHS Endpoints Reset Register
Reserved
UDPHS Test Register
Reserved
UDPHS Endpoint Configuration Register
UDPHS Endpoint Control Enable Register
UDPHS Endpoint Control Disable Register
0x100 + endpoint * 0x20 + 0x0C UDPHS Endpoint Control Register
0x100 + endpoint * 0x20 + 0x10
0x100 + endpoint * 0x20 + 0x14
Reserved (for endpoint)
UDPHS Endpoint Set Status Register
0x100 + endpoint * 0x20 + 0x18 UDPHS Endpoint Clear Status Register
0x100 + endpoint * 0x20 + 0x1C UDPHS Endpoint Status Register
0x120 - 0x1DC UDPHS Endpoint1 to
Registers
UDPHS_CTRL
UDPHS_FNUM
–
UDPHS_IEN
UDPHS_INTSTA
UDPHS_CLRINT
UDPHS_EPTRST
–
UDPHS_TST
–
UDPHS_EPTCFG
UDPHS_EPTCTLENB
UDPHS_EPTCTLDIS
UDPHS_EPTCTL
–
UDPHS_EPTSETSTA
UDPHS_EPTCLRSTA
UDPHS_EPTSTA
UDPHS DMA Next Descriptor Address Register UDPHS_DMANXTDSC
UDPHS DMA Channel Address Register UDPHS_DMAADDRESS
UDPHS DMA Channel Control Register
UDPHS DMA Channel Status Register
DMA Channel1 to 5
UDPHS_DMACONTROL
UDPHS_DMASTATUS
Read-write
Read-only
–
Read-write
Read-only
Write-only
Write-only
–
Read-write
–
Read-write
Write-only
Write-only
Read-only
–
Write-only
Write-only
Read-only
Read-write
Read-write
Read-write
Read-write
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Notes: 1. The reset value for UDPHS_EPTCTL0 is 0x0000_0001.
2. The addresses for the UDPHS Endpoint registers shown here are for UDPHS Endpoint0. The structure of this group of registers is repeated successively for each endpoint according to the consecution of endpoint registers located between 0x120 and 0x1DC.
3. The DMA channel index refers to the corresponding EP number. When no DMA channel is assigned to one EP, the associated registers are reserved. This is the case for EP0, so DMA Channel 0 registers are reserved.
Reset
0x0000_0200
0x0000_0000
–
0x0000_0010
0x0000_0000
–
–
–
0x0000_0000
–
0x0000_0000
–
–
–
–
–
0x0000_0040
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32.7.1 UDPHS Control Register
Name: UDPHS_CTRL
Address:
Access:
0xF803C000
Read-write
31
–
30
–
29
–
23
–
15
–
7
FADDR_EN
22
–
14
–
6
21
–
13
–
5
28
–
20
–
12
–
4
27
–
19
–
11
PULLD_DIS
3
DEV_ADDR
26
–
18
–
10
REWAKEUP
2
25
–
17
–
9
DETACH
1
24
–
16
–
8
EN_UDPHS
0
• DEV_ADDR: UDPHS Address
This field contains the default address (0) after power-up or UDPHS bus reset (read), or it is written with the value set by a
SET_ADDRESS request received by the device firmware (write).
• FADDR_EN: Function Address Enable
0 = Device is not in address state (read), or only the default function address is used (write).
1 = Device is in address state (read), or this bit is set by the device firmware after a successful status phase of a SET_ADDRESS transaction (write). When set, the only address accepted by the UDPHS controller is the one stored in the UDPHS Address field.
It will not be cleared afterwards by the device firmware. It is cleared by hardware on hardware reset, or when UDPHS bus reset is received.
• EN_UDPHS: UDPHS Enable
0 = UDPHS is disabled (read), or this bit disables and resets the UDPHS controller (write). Switch the host to UTMI. .
1 = UDPHS is enabled (read), or this bit enables the UDPHS controller (write). Switch the host to UTMI.
• DETACH: Detach Command
0 = UDPHS is attached (read), or this bit pulls up the DP line (attach command) (write).
1 = UDPHS is detached, UTMI transceiver is suspended (read), or this bit simulates a detach on the UDPHS line and forces the
UTMI transceiver into suspend state (Suspend M = 0) (write).
See PULLD_DIS description below.
• REWAKEUP : Send Remote Wake Up
0 = Remote Wake Up is disabled (read), or this bit has no effect (write).
1 = Remote Wake Up is enabled (read), or this bit forces an external interrupt on the UDPHS controller for Remote Wake UP purposes.
An Upstream Resume is sent only after the UDPHS bus has been in SUSPEND state for at least 5 ms.
This bit is automatically cleared by hardware at the end of the Upstream Resume.
• PULLD_DIS: Pull-Down Disable
When set, there is no pull-down on DP & DM. (DM Pull-Down = DP Pull-Down = 0).
Note: If the DETACH bit is also set, device DP & DM are left in high impedance state.
SAM9X35 [DATASHEET]
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(See DETACH description above.)
1
1
DETACH
0
0
PULLD_DIS DP
0
1
0
1
Pull up
Pull up
Pull down
High impedance state
DM
Pull down
High impedance state
Pull down
High impedance state
Condition
Not recommended
VBUS present
No VBUS
VBUS present & software disconnect
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32.7.2 UDPHS Frame Number Register
Name:
Address:
Access:
UDPHS_FNUM
0xF803C004
Read-only
31
FNUM_ERR
30
–
29
–
23
–
15
–
7
22
–
14
–
6
21
–
13
5
FRAME_NUMBER
28
–
20
–
12
4
27
–
19
–
11 10
FRAME_NUMBER
3 2
26
–
18
–
25
–
17
–
9
1
MICRO_FRAME_NUM
24
–
16
–
8
0
• MICRO_FRAME_NUM: Microframe Number
Number of the received microframe (0 to 7) in one frame.This field is reset at the beginning of each new frame (1 ms).
One microframe is received each 125 microseconds (1 ms/8).
• FRAME_NUMBER: Frame Number as defined in the Packet Field Formats
This field is provided in the last received SOF packet (see INT_SOF in the
UDPHS Interrupt Status Register
).
• FNUM_ERR: Frame Number CRC Error
This bit is set by hardware when a corrupted Frame Number in Start of Frame packet (or Micro SOF) is received.
This bit and the INT_SOF (or MICRO_SOF) interrupt are updated at the same time.
SAM9X35 [DATASHEET]
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32.7.3 UDPHS Interrupt Enable Register
Name:
Address:
Access:
UDPHS_IEN
0xF803C010
Read-write
31
–
30
DMA_6
29
DMA_5
23
–
15
–
22
–
14
EPT_6
7 6
UPSTR_RES ENDOFRSM
21
–
13
EPT_5
5
WAKE_UP
28
DMA_4
20
–
12
EPT_4
4
ENDRESET
• DET_SUSPD: Suspend Interrupt Enable
0 = Disable Suspend Interrupt.
1 = Enable Suspend Interrupt.
• MICRO_SOF: Micro-SOF Interrupt Enable
0 = Disable Micro-SOF Interrupt.
1 = Enable Micro-SOF Interrupt.
• INT_SOF: SOF Interrupt Enable
0 = Disable SOF Interrupt.
1 = Enable SOF Interrupt.
• ENDRESET: End Of Reset Interrupt Enable
0 = Disable End Of Reset Interrupt.
1 = Enable End Of Reset Interrupt. Automatically enabled after USB reset.
• WAKE_UP: Wake Up CPU Interrupt Enable
0 = Disable Wake Up CPU Interrupt.
1 = Enable Wake Up CPU Interrupt.
• ENDOFRSM: End Of Resume Interrupt Enable
0 = Disable Resume Interrupt.
1 = Enable Resume Interrupt.
• UPSTR_RES: Upstream Resume Interrupt Enable
0 = Disable Upstream Resume Interrupt.
1 = Enable Upstream Resume Interrupt.
• EPT_x: Endpoint x Interrupt Enable
0 = Disable the interrupts for this endpoint.
1 = Enable the interrupts for this endpoint.
• DMA_x: DMA Channel x Interrupt Enable
0 = Disable the interrupts for this channel.
1 = Enable the interrupts for this channel.
27
DMA_3
19
–
11
EPT_3
3
INT_SOF
26
DMA_2
18
–
10
EPT_2
25
DMA_1
17
–
9
EPT_1
2 1
MICRO_SOF DET_SUSPD
24
–
16
–
8
EPT_0
0
–
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32.7.4 UDPHS Interrupt Status Register
Name:
Address:
Access:
UDPHS_INTSTA
0xF803C014
Read-only
31
–
30
DMA_6
29
DMA_5
23
–
15
–
22
–
14
EPT_6
7 6
UPSTR_RES ENDOFRSM
21
–
13
EPT_5
5
WAKE_UP
28
DMA_4
20
–
12
EPT_4
4
ENDRESET
27
DMA_3
19
–
11
EPT_3
3
INT_SOF
26
DMA_2
18
–
10
EPT_2
25
DMA_1
17
–
9
EPT_1
2 1
MICRO_SOF DET_SUSPD
24
–
16
–
8
EPT_0
0
SPEED
• SPEED: Speed Status
0 = Reset by hardware when the hardware is in Full Speed mode.
1 = Set by hardware when the hardware is in High Speed mode
• DET_SUSPD: Suspend Interrupt
0 = Cleared by setting the DET_SUSPD bit in UDPHS_CLRINT register
1 = Set by hardware when a UDPHS Suspend (Idle bus for three frame periods, a J state for 3 ms) is detected. This triggers a
UDPHS interrupt when the DET_SUSPD bit is set in UDPHS_IEN register.
• MICRO_SOF: Micro Start Of Frame Interrupt
0 = Cleared by setting the MICRO_SOF bit in UDPHS_CLRINT register.
1 = Set by hardware when an UDPHS micro start of frame PID (SOF) has been detected (every 125 us) or synthesized by the macro. This triggers a UDPHS interrupt when the MICRO_SOF bit is set in UDPHS_IEN. In case of detected SOF, the
MICRO_FRAME_NUM field in UDPHS_FNUM register is incremented and the FRAME_NUMBER field doesn’t change.
Note: The Micro Start Of Frame Interrupt (MICRO_SOF), and the Start Of Frame Interrupt (INT_SOF) are not generated at the same time.
• INT_SOF: Start Of Frame Interrupt
0 = Cleared by setting the INT_SOF bit in UDPHS_CLRINT.
1 = Set by hardware when an UDPHS Start Of Frame PID (SOF) has been detected (every 1 ms) or synthesized by the macro.
This triggers a UDPHS interrupt when the INT_SOF bit is set in UDPHS_IEN register. In case of detected SOF, in High Speed mode, the MICRO_FRAME_NUMBER field is cleared in UDPHS_FNUM register and the FRAME_NUMBER field is updated.
• ENDRESET: End Of Reset Interrupt
0 = Cleared by setting the ENDRESET bit in UDPHS_CLRINT.
1 = Set by hardware when an End Of Reset has been detected by the UDPHS controller. This triggers a UDPHS interrupt when the ENDRESET bit is set in UDPHS_IEN.
• WAKE_UP: Wake Up CPU Interrupt
0 = Cleared by setting the WAKE_UP bit in UDPHS_CLRINT.
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1 = Set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered non-idle signal from the
UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when the WAKE_UP bit is set in UDPHS_IEN register. When receiving this interrupt, the user has to enable the device controller clock prior to operation.
Note: this interrupt is generated even if the device controller clock is disabled.
• ENDOFRSM: End Of Resume Interrupt
0 = Cleared by setting the ENDOFRSM bit in UDPHS_CLRINT.
1 = Set by hardware when the UDPHS controller detects a good end of resume signal initiated by the host. This triggers a UDPHS interrupt when the ENDOFRSM bit is set in UDPHS_IEN.
• UPSTR_RES: Upstream Resume Interrupt
0 = Cleared by setting the UPSTR_RES bit in UDPHS_CLRINT.
1 = Set by hardware when the UDPHS controller is sending a resume signal called “upstream resume”. This triggers a UDPHS interrupt when the UPSTR_RES bit is set in UDPHS_IEN.
• EPT_x: Endpoint x Interrupt
0 = Reset when the UDPHS_EPTSTAx interrupt source is cleared.
1 = Set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the
EPT_x bit in UDPHS_IEN.
• DMA_x: DMA Channel x Interrupt
0 = Reset when the UDPHS_DMASTATUSx interrupt source is cleared.
1 = Set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN.
SAM9X35 [DATASHEET]
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32.7.5 UDPHS Clear Interrupt Register
Name:
Address:
Access:
UDPHS_CLRINT
0xF803C018
Write only
31
–
30
–
29
–
23
–
15
–
22
–
14
–
7 6
UPSTR_RES ENDOFRSM
21
–
13
–
5
WAKE_UP
• DET_SUSPD: Suspend Interrupt Clear
0 = No effect.
1 = Clear the DET_SUSPD bit in UDPHS_INTSTA.
• MICRO_SOF: Micro Start Of Frame Interrupt Clear
0 = No effect.
1 = Clear the MICRO_SOF bit in UDPHS_INTSTA.
• INT_SOF: Start Of Frame Interrupt Clear
0 = No effect.
1 = Clear the INT_SOF bit in UDPHS_INTSTA.
• ENDRESET: End Of Reset Interrupt Clear
0 = No effect.
1 = Clear the ENDRESET bit in UDPHS_INTSTA.
• WAKE_UP: Wake Up CPU Interrupt Clear
0 = No effect.
1 = Clear the WAKE_UP bit in UDPHS_INTSTA.
• ENDOFRSM: End Of Resume Interrupt Clear
0 = No effect.
1 = Clear the ENDOFRSM bit in UDPHS_INTSTA.
• UPSTR_RES: Upstream Resume Interrupt Clear
0 = No effect.
1 = Clear the UPSTR_RES bit in UDPHS_INTSTA.
28
–
20
–
12
–
4
ENDRESET
27
–
19
–
11
–
3
INT_SOF
26
–
18
–
10
–
25
–
17
–
9
–
2 1
MICRO_SOF DET_SUSPD
24
–
16
–
8
–
0
–
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32.7.6 UDPHS Endpoints Reset Register
Name: UDPHS_EPTRST
Address:
Access:
0xF803C01C
Write only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
EPT_6
21
–
13
–
5
EPT_5
28
–
20
–
12
–
4
EPT_4
27
–
19
–
11
–
3
EPT_3
26
–
18
–
10
–
2
EPT_2
25
–
17
–
9
–
1
EPT_1
• EPT_x: Endpoint x Reset
0 = No effect.
1 = Reset the Endpointx state.
Setting this bit clears the Endpoint status UDPHS_EPTSTAx register, except for the TOGGLESQ_STA field.
24
–
16
–
8
–
0
EPT_0
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32.7.7 UDPHS Test Register
Name: UDPHS_TST
Address:
Access:
0xF803C0E0
Read-write
31
–
30
–
23
–
15
–
7
–
22
–
14
–
6
–
29
–
21
–
13
–
5
OPMODE2
28
–
20
–
12
–
4
TST_PKT
27
–
19
–
11
–
3
TST_K
26
–
18
–
10
–
2
TST_J
25
–
17
–
9
–
1
SPEED_CFG
0
24
–
16
–
8
–
• SPEED_CFG: Speed Configuration
Speed Configuration:
Value
0
1
2
3
Name
NORMAL
HIGH_SPEED
FULL_SPEED
Description
Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode
Reserved
Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose.
Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake.
• TST_J: Test J Mode
0 = No effect.
1 = Set to send the J state on the UDPHS line. This enables the testing of the high output drive level on the D+ line.
• TST_K: Test K Mode
0 = No effect.
1 = Set to send the K state on the UDPHS line. This enables the testing of the high output drive level on the D- line.
• TST_PKT: Test Packet Mode
0 = No effect.
1 = Set to repetitively transmit the packet stored in the current bank. This enables the testing of rise and fall times, eye patterns, jitter, and any other dynamic waveform specifications.
• OPMODE2: OpMode2
0 = No effect.
1 = Set to force the OpMode signal (UTMI interface) to “10”, to disable the bit-stuffing and the NRZI encoding.
Note: For the Test mode, Test_SE0_NAK (see Universal Serial Bus Specification, Revision 2.0: 7.1.20, Test Mode Support).
Force the device in High Speed mode, and configure a bulk-type endpoint. Do not fill this endpoint for sending NAK to the host.
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Upon command, a port’s transceiver must enter the High Speed receive mode and remain in that mode until the exit action is taken. This enables the testing of output impedance, low level output voltage and loading characteristics. In addition, while in this mode, upstream facing ports (and only upstream facing ports) must respond to any IN token packet with a NAK handshake (only if the packet CRC is determined to be correct) within the normal allowed device response time. This enables testing of the device squelch level circuitry and, additionally, provides a general purpose stimulus/response test for basic functional testing.
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32.7.8 UDPHS Endpoint Configuration Register
Name: UDPHS_EPTCFGx
Address: 0xF803C100 [0], 0xF803C120 [1], 0xF803C140 [2], 0xF803C160 [3], 0xF803C180 [4], 0xF803C1A0 [5],
0xF803C1C0 [6]
Access: Read-write
31
EPT_MAPD
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
15
–
7
BK_NUMBER
6
22
–
14
–
21
–
13
–
5
EPT_TYPE
4
20
–
12
–
19
–
11
–
3
EPT_DIR
18
–
10
–
2
17
–
1
EPT_SIZE
16
–
9
NB_TRANS
8
0
• EPT_SIZE: Endpoint Size
Endpoint Size
5
6
3
4
Value
0
1
2
64
128
256
512
Name
8
16
32
Description
8 bytes
16 bytes
32 bytes
64 bytes
128 bytes
256 bytes
512 bytes
7 1024 1024 bytes
Note: 1. 1024 bytes is only for isochronous endpoint.
• EPT_DIR: Endpoint Direction
0 = Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.
1 = Set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints.
For Control endpoints this bit has no effect and should be left at zero.
• EPT_TYPE: Endpoint Type
Set this field according to the endpoint type (see
Section 32.6.6 ”Endpoint Configuration”
).
(Endpoint 0 should always be configured as control)
SAM9X35 [DATASHEET]
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Endpoint Type
Value
0
1
2
3
Name
CTRL8
ISO
BULK
INT
Description
Control endpoint
Isochronous endpoint
Bulk endpoint
Interrupt endpoint
• BK_NUMBER: Number of Banks
Number of Banks
Value
0
1
2
3
2
3
Name
0
1
Description
Zero bank, the endpoint is not mapped in memory
One bank (bank 0)
Double bank (Ping-Pong: bank0/bank1)
Triple bank (bank0/bank1/bank2)
• NB_TRANS: Number Of Transaction per Microframe
The Number of transactions per microframe is set by software.
Note: Meaningful for high bandwidth isochronous endpoint only.
• EPT_MAPD: Endpoint Mapped
0 = The user should reprogram the register with correct values.
1 = Set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding:
– The fifo max capacity (FIFO_MAX_SIZE in UDPHS_IPFEATURES register)
– The number of endpoints/banks already allocated
– The number of allowed banks for this endpoint
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32.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)
Name: UDPHS_EPTCTLENBx
Access: Write-only
31
SHRT_PCKT
23
–
15
NAK_OUT
30
–
22
–
14
NAK_IN
29
–
21
–
13
STALL_SNT
28
–
20
–
12
RX_SETUP
27
–
19
–
11
TXRDY
26
–
25
–
24
–
18
BUSY_BANK
17
–
16
–
10 9 8
TX_COMPLT RXRDY_TXKL ERR_OVFLW
7
–
6
–
5
–
4
NYET_DIS
3
INTDIS_DMA
2
–
1 0
AUTO_VALID EPT_ENABL
• EPT_ENABL: Endpoint Enable
0 = No effect.
1 = Enable endpoint according to the device configuration.
• AUTO_VALID: Packet Auto-Valid Enable
0 = No effect.
1 = Enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers.
• INTDIS_DMA: Interrupts Disable DMA
0 = No effect.
1 = If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.
• NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
0 = No effect.
1 = Forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.
• ERR_OVFLW: Overflow Error Interrupt Enable
0 = No effect.
1 = Enable Overflow Error Interrupt.
• RXRDY_TXKL: Received OUT Data Interrupt Enable
0 = No effect.
1 = Enable Received OUT Data Interrupt.
• TX_COMPLT: Transmitted IN Data Complete Interrupt Enable
0 = No effect.
1 = Enable Transmitted IN Data Complete Interrupt.
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• TXRDY: TX Packet Ready Interrupt Enable
0 = No effect.
1 = Enable TX Packet Ready/Transaction Error Interrupt.
• RX_SETUP: Received SETUP
0 = No effect.
1 = Enable RX_SETUP Interrupt.
• STALL_SNT: Stall Sent Interrupt Enable
0 = No effect.
1 = Enable Stall Sent Interrupt.
• NAK_IN: NAKIN Interrupt Enable
0 = No effect.
1 = Enable NAKIN Interrupt.
• NAK_OUT: NAKOUT Interrupt Enable
0 = No effect.
1 = Enable NAKOUT Interrupt.
• BUSY_BANK: Busy Bank Interrupt Enable
0 = No effect.
1 = Enable Busy Bank Interrupt.
• SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable
For OUT endpoints:
0 = No effect.
1 = Enable Short Packet Interrupt.
For IN endpoints:
Guarantees short packet at end of DMA Transfer if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTOVALID bits are also set.
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32.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints)
Name: UDPHS_EPTCTLENBx (ISOENDPT)
Address: 0xF803C104 [0], 0xF803C124 [1], 0xF803C144 [2], 0xF803C164 [3], 0xF803C184 [4], 0xF803C1A4 [5],
0xF803C1C4 [6]
Access: Write-only
31
SHRT_PCKT
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
15
–
22
–
21
–
20
–
19
–
18
BUSY_BANK
17
–
16
–
14
ERR_FLUSH
13
ERR_CRC_NT
R
12 11 10 9 8
ERR_FL_ISO TXRDY_TRER TX_COMPLT RXRDY_TXKL ERR_OVFLW
7
MDATA_RX
6
DATAX_RX
5
–
4
–
3
INTDIS_DMA
2
–
1 0
AUTO_VALID EPT_ENABL
This register view is relevant only if EPT_TYPE=0x1 in
“UDPHS Endpoint Configuration Register” on page 538
• EPT_ENABL: Endpoint Enable
0 = No effect.
1 = Enable endpoint according to the device configuration.
• AUTO_VALID: Packet Auto-Valid Enable
0 = No effect.
1 = Enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers.
• INTDIS_DMA: Interrupts Disable DMA
0 = No effect.
1 = If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.
• DATAX_RX: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
0 = No effect.
1 = Enable DATAx Interrupt.
• MDATA_RX: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
0 = No effect.
1 = Enable MDATA Interrupt.
• ERR_OVFLW: Overflow Error Interrupt Enable
0 = No effect.
1 = Enable Overflow Error Interrupt.
• RXRDY_TXKL: Received OUT Data Interrupt Enable
0 = No effect.
1 = Enable Received OUT Data Interrupt.
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• TX_COMPLT: Transmitted IN Data Complete Interrupt Enable
0 = No effect.
1 = Enable Transmitted IN Data Complete Interrupt.
• TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Enable
0 = No effect.
1 = Enable TX Packet Ready/Transaction Error Interrupt.
• ERR_FL_ISO: Error Flow Interrupt Enable
0 = No effect.
1 = Enable Error Flow ISO Interrupt.
• ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Enable
0 = No effect.
1 = Enable Error CRC ISO/Error Number of Transaction Interrupt.
• ERR_FLUSH: Bank Flush Error Interrupt Enable
0 = No effect.
1 = Enable Bank Flush Error Interrupt.
• BUSY_BANK: Busy Bank Interrupt Enable
0 = No effect.
1 = Enable Busy Bank Interrupt.
• SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable
For OUT endpoints:
0 = No effect.
1 = Enable Short Packet Interrupt.
For IN endpoints:
Guarantees short packet at end of DMA Transfer if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTOVALID bits are also set.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
543
32.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints)
Name: UDPHS_EPTCTLDISx
Address: 0xF803C108 [0], 0xF803C128 [1], 0xF803C148 [2], 0xF803C168 [3], 0xF803C188 [4], 0xF803C1A8 [5],
0xF803C1C8 [6]
Access: Write-only
31
SHRT_PCKT
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
15
NAK_OUT
22
–
14
NAK_IN
21
–
13
STALL_SNT
20
–
12
RX_SETUP
19
–
11
TXRDY
18
BUSY_BANK
17
–
16
–
10 9 8
TX_COMPLT RXRDY_TXKL ERR_OVFLW
7
–
6
–
5
–
4
NYET_DIS
3
INTDIS_DMA
2
–
1 0
AUTO_VALID EPT_DISABL
• EPT_DISABL: Endpoint Disable
0 = No effect.
1 = Disable endpoint.
• AUTO_VALID: Packet Auto-Valid Disable
0 = No effect.
1 = Disable this bit to not automatically validate the current packet.
• INTDIS_DMA: Interrupts Disable DMA
0 = No effect.
1 = Disable the “Interrupts Disable DMA”.
• NYET_DIS: NYET Enable (Only for High Speed Bulk OUT endpoints)
0 = No effect.
1 = Let the hardware handle the handshake response for the High Speed Bulk OUT transfer.
• ERR_OVFLW: Overflow Error Interrupt Disable
0 = No effect.
1 = Disable Overflow Error Interrupt.
• RXRDY_TXKL: Received OUT Data Interrupt Disable
0 = No effect.
1 = Disable Received OUT Data Interrupt.
• TX_COMPLT: Transmitted IN Data Complete Interrupt Disable
0 = No effect.
1 = Disable Transmitted IN Data Complete Interrupt.
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• TXRDY: TX Packet Ready Interrupt Disable
0 = No effect.
1 = Disable TX Packet Ready/Transaction Error Interrupt.
• RX_SETUP: Received SETUP Interrupt Disable
0 = No effect.
1 = Disable RX_SETUP Interrupt.
• STALL_SNT: Stall Sent Interrupt Disable
0 = No effect.
1 = Disable Stall Sent Interrupt.
• NAK_IN: NAKIN Interrupt Disable
0 = No effect.
1 = Disable NAKIN Interrupt.
• NAK_OUT: NAKOUT Interrupt Disable
0 = No effect.
1 = Disable NAKOUT Interrupt.
• BUSY_BANK: Busy Bank Interrupt Disable
0 = No effect.
1 = Disable Busy Bank Interrupt.
• SHRT_PCKT: Short Packet Interrupt Disable
For OUT endpoints:
0 = No effect.
1 = Disable Short Packet Interrupt.
For IN endpoints:
Never automatically add a zero length packet at end of DMA transfer.
SAM9X35 [DATASHEET]
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32.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint)
Name: UDPHS_EPTCTLDISx (ISOENDPT)
Address: 0xF803C108 [0], 0xF803C128 [1], 0xF803C148 [2], 0xF803C168 [3], 0xF803C188 [4], 0xF803C1A8 [5],
0xF803C1C8 [6]
Access: Write-only
31
SHRT_PCKT
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
15
–
22
–
21
–
20
–
19
–
18
BUSY_BANK
17
–
16
–
14
ERR_FLUSH
13
ERR_CRC_NT
R
12 11 10 9 8
ERR_FL_ISO TXRDY_TRER TX_COMPLT RXRDY_TXKL ERR_OVFLW
7
MDATA_RX
6
DATAX_RX
5
–
4
–
3
INTDIS_DMA
2
–
1 0
AUTO_VALID EPT_DISABL
This register view is relevant only if EPT_TYPE=0x1 in
“UDPHS Endpoint Configuration Register” on page 538
• EPT_DISABL: Endpoint Disable
0 = No effect.
1 = Disable endpoint.
• AUTO_VALID: Packet Auto-Valid Disable
0 = No effect.
1 = Disable this bit to not automatically validate the current packet.
• INTDIS_DMA: Interrupts Disable DMA
0 = No effect.
1 = Disable the “Interrupts Disable DMA”.
• DATAX_RX: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
0 = No effect.
1 = Disable DATAx Interrupt.
• MDATA_RX: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
0 = No effect.
1 = Disable MDATA Interrupt.
• ERR_OVFLW: Overflow Error Interrupt Disable
0 = No effect.
1 = Disable Overflow Error Interrupt.
• RXRDY_TXKL: Received OUT Data Interrupt Disable
0 = No effect.
1 = Disable Received OUT Data Interrupt.
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• TX_COMPLT: Transmitted IN Data Complete Interrupt Disable
0 = No effect.
1 = Disable Transmitted IN Data Complete Interrupt.
• TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Disable
0 = No effect.
1 = Disable TX Packet Ready/Transaction Error Interrupt.
• ERR_FL_ISO: Error Flow Interrupt Disable
0 = No effect.
1 = Disable Error Flow ISO Interrupt.
• ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Disable
0 = No effect.
1 = Disable Error CRC ISO/Error Number of Transaction Interrupt.
• ERR_FLUSH: bank flush error Interrupt Disable
0 = No effect.
1 = Disable Bank Flush Error Interrupt.
• BUSY_BANK: Busy Bank Interrupt Disable
0 = No effect.
1 = Disable Busy Bank Interrupt.
• SHRT_PCKT: Short Packet Interrupt Disable
For OUT endpoints:
0 = No effect.
1 = Disable Short Packet Interrupt.
For IN endpoints:
Never automatically add a zero length packet at end of DMA transfer.
SAM9X35 [DATASHEET]
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32.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints)
Name: UDPHS_EPTCTLx
Access: Read-only
31
SHRT_PCKT
23
–
15
NAK_OUT
30
–
22
–
14
NAK_IN
29
–
21
–
13
STALL_SNT
28
–
20
–
12
RX_SETUP
27
–
19
–
11
TXRDY
26
–
25
–
24
–
18
BUSY_BANK
17
–
16
–
10 9 8
TX_COMPLT RXRDY_TXKL ERR_OVFLW
7
–
6
–
5
–
4
NYET_DIS
3
INTDIS_DMA
2
–
1 0
AUTO_VALID EPT_ENABL
• EPT_ENABL: Endpoint Enable
0 = If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration.
1 = If set, the endpoint is enabled according to the device configuration.
• AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints.
For IN Transfer:
If this bit is set, then the UDPHS_EPTSTAx register TXRDY bit is set automatically when the current bank is full and at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set.
The user may still set the UDPHS_EPTSTAx register TXRDY bit if the current bank is not full, unless the user wants to send a Zero Length Packet by software.
For OUT Transfer:
If this bit is set, then the UDPHS_EPTSTAx register RXRDY_TXKL bit is automatically reset for the current bank when the last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is reached.
The user may still clear the UDPHS_EPTSTAx register RXRDY_TXKL bit, for example, after completing a DMA buffer by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of the remaining data bank(s).
• INTDIS_DMA: Interrupt Disables DMA
If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the UDPHS_IEN register EPT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source or clear this bit if transfer completion is needed.
If the exception raised is associated with the new system bank packet, then the previous DMA packet transfer is normally completed, but the new DMA packet transfer is not started (not requested).
If the exception raised is not associated to a new system bank packet (NAK_IN, NAK_OUT...), then the request cancellation may happen at any time and may immediately stop the current DMA transfer.
This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a DMA buffer by software after reception of a short packet.
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• NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
0 = If cleared, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer.
1 = If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.
Note: According to the Universal Serial Bus Specification, Rev 2.0
(8.5.1.1 NAK Responses to OUT/DATA During PING
Protocol), a NAK response to an HS Bulk OUT transfer is expected to be an unusual occurrence.
• ERR_OVFLW: Overflow Error Interrupt Enabled
0 = Overflow Error Interrupt is masked.
1 = Overflow Error Interrupt is enabled.
• RXRDY_TXKL: Received OUT Data Interrupt Enabled
0 = Received OUT Data Interrupt is masked.
1 = Received OUT Data Interrupt is enabled.
• TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled
0 = Transmitted IN Data Complete Interrupt is masked.
1 = Transmitted IN Data Complete Interrupt is enabled.
• TXRDY: TX Packet Ready Interrupt Enabled
0 = TX Packet Ready Interrupt is masked.
1 = TX Packet Ready Interrupt is enabled.
Caution: Interrupt source is active as long as the corresponding UDPHS_EPTSTAx register TXRDY flag remains low. If there are no more banks available for transmitting after the software has set UDPHS_EPTSTAx/TXRDY for the last transmit packet, then the interrupt source remains inactive until the first bank becomes free again to transmit at
UDPHS_EPTSTAx/TXRDY hardware clear.
• RX_SETUP: Received SETUP Interrupt Enabled
0 = Received SETUP is masked.
1 = Received SETUP is enabled.
• STALL_SNT: Stall Sent Interrupt Enabled
0 = Stall Sent Interrupt is masked.
1 = Stall Sent Interrupt is enabled.
• NAK_IN: NAKIN Interrupt Enabled
0 = NAKIN Interrupt is masked.
1 = NAKIN Interrupt is enabled.
• NAK_OUT: NAKOUT Interrupt Enabled
0 = NAKOUT Interrupt is masked.
1 = NAKOUT Interrupt is enabled.
• BUSY_BANK: Busy Bank Interrupt Enabled
0 = BUSY_BANK Interrupt is masked.
1 = BUSY_BANK Interrupt is enabled.
For OUT endpoints : an interrupt is sent when all banks are busy.
For IN endpoints: an interrupt is sent when all banks are free.
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• SHRT_PCKT: Short Packet Interrupt Enabled
For OUT endpoints : send an Interrupt when a Short Packet has been received.
0 = Short Packet Interrupt is masked.
1 = Short Packet Interrupt is enabled.
For IN endpoints : a Short Packet transmission is guaranteed upon end of the DMA Transfer, thus signaling a BULK or
INTERRUPT end of transfer, but only if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTO_VALID bits are also set.
SAM9X35 [DATASHEET]
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550
32.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint)
Name:
Address:
Access:
UDPHS_EPTCTLx [x=0..6] (ISOENDPT)
0xF803C10C [0], 0xF803C12C [1], 0xF803C14C [2], 0xF803C16C [3], 0xF803C18C [4], 0xF803C1AC [5],
0xF803C1CC [6]
Read-only
31
SHRT_PCKT
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
15
–
22
–
21
–
20
–
19
–
18
BUSY_BANK
17
–
16
–
14
ERR_FLUSH
13
ERR_CRC_NT
R
12 11 10 9 8
ERR_FL_ISO TXRDY_TRER TX_COMPLT RXRDY_TXKL ERR_OVFLW
7
MDATA_RX
6
DATAX_RX
5
–
4
–
3
INTDIS_DMA
2
–
1 0
AUTO_VALID EPT_ENABL
This register view is relevant only if EPT_TYPE=0x1 in
“UDPHS Endpoint Configuration Register” on page 538
• EPT_ENABL: Endpoint Enable
0 = If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration.
1 = If set, the endpoint is enabled according to the device configuration.
• AUTO_VALID: Packet Auto-Valid Enabled
Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints.
For IN Transfer:
If this bit is set, then the UDPHS_EPTSTAx register TXRDY_TRER bit is set automatically when the current bank is full and at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set.
The user may still set the UDPHS_EPTSTAx register TXRDY_TRER bit if the current bank is not full, unless the user wants to send a Zero Length Packet by software.
For OUT Transfer:
If this bit is set, then the UDPHS_EPTSTAx register RXRDY_TXKL bit is automatically reset for the current bank when the last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is reached.
The user may still clear the UDPHS_EPTSTAx register RXRDY_TXKL bit, for example, after completing a DMA buffer by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of the remaining data bank(s).
• INTDIS_DMA: Interrupt Disables DMA
If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the UDPHS_IEN register EPT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source or clear this bit if transfer completion is needed.
If the exception raised is associated with the new system bank packet, then the previous DMA packet transfer is normally completed, but the new DMA packet transfer is not started (not requested).
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If the exception raised is not associated to a new system bank packet (ex:ERR_FL_ISO), then the request cancellation may happen at any time and may immediately stop the current DMA transfer.
This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a DMA buffer by software after reception of a short packet, or to perform buffer truncation on ERR_FL_ISO interrupt for adaptive rate.
• DATAX_RX: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
0 = No effect.
1 = Send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received.
• MDATA_RX: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
0 = No effect.
1 = Send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data payload has been received.
• ERR_OVFLW: Overflow Error Interrupt Enabled
0 = Overflow Error Interrupt is masked.
1 = Overflow Error Interrupt is enabled.
• RXRDY_TXKL: Received OUT Data Interrupt Enabled
0 = Received OUT Data Interrupt is masked.
1 = Received OUT Data Interrupt is enabled.
• TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled
0 = Transmitted IN Data Complete Interrupt is masked.
1 = Transmitted IN Data Complete Interrupt is enabled.
• TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Enabled
0 = TX Packet Ready/Transaction Error Interrupt is masked.
1 = TX Packet Ready/Transaction Error Interrupt is enabled.
Caution: Interrupt source is active as long as the corresponding UDPHS_EPTSTAx register TXRDY_TRER flag r e m a i n s l o w . I f t h e r e a r e n o m o r e b a n k s a v a i l a b l e f o r t r a n s m i t t i n g a f t e r t h e s o f t w a r e h a s s e t
UDPHS_EPTSTAx/TXRDY_TRER for the last transmit packet, then the interrupt source remains inactive until the first bank becomes free again to transmit at UDPHS_EPTSTAx/TXRDY_TRER hardware clear.
• ERR_FL_ISO: Error Flow Interrupt Enabled
0 = Error Flow Interrupt is masked.
1 = Error Flow Interrupt is enabled.
• ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Enabled
0 = ISO CRC error/number of Transaction Error Interrupt is masked.
1 = ISO CRC error/number of Transaction Error Interrupt is enabled.
• ERR_FLUSH: Bank Flush Error Interrupt Enabled
0 = Bank Flush Error Interrupt is masked.
1 = Bank Flush Error Interrupt is enabled.
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• BUSY_BANK: Busy Bank Interrupt Enabled
0 = BUSY_BANK Interrupt is masked.
1 = BUSY_BANK Interrupt is enabled.
For OUT endpoints : An interrupt is sent when all banks are busy.
For IN endpoints: An interrupt is sent when all banks are free.
• SHRT_PCKT: Short Packet Interrupt Enabled
For OUT endpoints : send an Interrupt when a Short Packet has been received.
0 = Short Packet Interrupt is masked.
1 = Short Packet Interrupt is enabled.
For IN endpoints : a Short Packet transmission is guaranteed upon end of the DMA Transfer, thus signaling an end of isochronous (micro-)frame data, but only if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTO_VALID bits are also set.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
553
32.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints)
Name: UDPHS_EPTSETSTAx
Access: Write-only
31
–
30
–
29
–
28
–
27
–
26
–
23
–
15
–
22
–
14
–
21
–
13
–
20
–
12
–
19
–
11
TXRDY
18
–
10
–
25
–
17
–
9
RXRDY_TXKL
24
–
16
–
8
–
7
–
6
–
5
FRCESTALL
4
–
3
–
2
–
1
–
0
–
• FRCESTALL: Stall Handshake Request Set
0 = No effect.
1 = Set this bit to request a STALL answer to the host for the next handshake
Refer to chapters 8.4.5 (Handshake Packets) and 9.4.5 (Get Status) of the Universal Serial Bus Specification, Rev 2.0
for more information on the STALL handshake.
• RXRDY_TXKL: KILL Bank Set (for IN Endpoint)
0 = No effect.
1 = Kill the last written bank.
• TXRDY: TX Packet Ready Set
0 = No effect.
1 = Set this bit after a packet has been written into the endpoint FIFO for IN data transfers
– This flag is used to generate a Data IN transaction (device to host).
– Device firmware checks that it can write a data payload in the FIFO, checking that TXRDY is cleared.
– Transfer to the FIFO is done by writing in the “Buffer Address” register.
– Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device setting
TXRDY to one.
– UDPHS bus transactions can start.
– TXCOMP is set once the data payload has been received by the host.
– Data should be written into the endpoint FIFO only after this bit has been cleared.
– Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
554
32.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint)
Name:
Address:
Access:
UDPHS_EPTSETSTAx [x=0..6] (ISOENDPT)
0xF803C114 [0], 0xF803C134 [1], 0xF803C154 [2], 0xF803C174 [3], 0xF803C194 [4], 0xF803C1B4 [5],
0xF803C1D4 [6]
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
15
–
22
–
14
–
21
–
13
–
20
–
12
–
19
–
11
TXRDY_TRER
18
–
10
–
17
–
9
RXRDY_TXKL
7
–
6
–
5
–
4
–
3
–
2
–
1
–
This register view is relevant only if EPT_TYPE=0x1 in
“UDPHS Endpoint Configuration Register” on page 538
For additional Information, see “UDPHS Endpoint Status Register (Isochronous Endpoint)” on page 561
.
0
–
• RXRDY_TXKL: KILL Bank Set (for IN Endpoint)
0 = No effect.
1 = Kill the last written bank.
• TXRDY_TRER: TX Packet Ready Set
0 = No effect.
1 = Set this bit after a packet has been written into the endpoint FIFO for IN data transfers
– This flag is used to generate a Data IN transaction (device to host).
– Device firmware checks that it can write a data payload in the FIFO, checking that TXRDY_TRER is cleared.
– Transfer to the FIFO is done by writing in the “Buffer Address” register.
– Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device setting
TXRDY_TRER to one.
– UDPHS bus transactions can start.
– TXCOMP is set once the data payload has been sent.
– Data should be written into the endpoint FIFO only after this bit has been cleared.
– Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet.
16
–
8
–
SAM9X35 [DATASHEET]
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555
32.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints)
Name: UDPHS_EPTCLRSTAx
Access: Write-only
31
–
23
–
15
NAK_OUT
30
–
22
–
14
NAK_IN
29
–
21
–
13
STALL_SNT
28
–
20
–
12
RX_SETUP
27
–
19
–
11
–
26
–
25
–
18
–
17
–
10 9
TX_COMPLT RXRDY_TXKL
7
–
6
TOGGLESQ
5
FRCESTALL
4
–
3
–
2
–
1
–
0
–
.
• FRCESTALL: Stall Handshake Request Clear
0 = No effect.
1 = Clear the STALL request. The next packets from host will not be STALLed.
• TOGGLESQ: Data Toggle Clear
0 = No effect.
1 = Clear the PID data of the current bank
For OUT endpoints, the next received packet should be a DATA0.
For IN endpoints, the next packet will be sent with a DATA0 PID.
• RXRDY_TXKL: Received OUT Data Clear
0 = No effect.
1 = Clear the RXRDY_TXKL flag of UDPHS_EPTSTAx.
• TX_COMPLT: Transmitted IN Data Complete Clear
0 = No effect.
1 = Clear the TX_COMPLT flag of UDPHS_EPTSTAx.
• RX_SETUP: Received SETUP Clear
0 = No effect.
1 = Clear the RX_SETUP flags of UDPHS_EPTSTAx.
• STALL_SNT: Stall Sent Clear
0 = No effect.
1 = Clear the STALL_SNT flags of UDPHS_EPTSTAx.
• NAK_IN: NAKIN Clear
0 = No effect.
1 = Clear the NAK_IN flags of UDPHS_EPTSTAx.
• NAK_OUT: NAKOUT Clear
0 = No effect.
1 = Clear the NAK_OUT flag of UDPHS_EPTSTAx.
24
–
16
–
8
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
556
32.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint)
Name: UDPHS_EPTCLRSTAx (ISOENDPT)
Address: 0xF803C118 [0], 0xF803C138 [1], 0xF803C158 [2], 0xF803C178 [3], 0xF803C198 [4], 0xF803C1B8 [5],
0xF803C1D8 [6]
Access: Write-only
31
–
23
–
15
–
30
–
22
–
29
–
21
–
28
–
20
–
14
ERR_FLUSH
13
ERR_CRC_NT
R
12
ERR_FL_ISO
27
–
19
–
11
–
26
–
18
–
25
–
17
–
10 9
TX_COMPLT RXRDY_TXKL
7
–
6
TOGGLESQ
5
–
4
–
3
–
2
–
1
–
This register view is relevant only if EPT_TYPE=0x1 in
“UDPHS Endpoint Configuration Register” on page 538
For additional Information, see “UDPHS Endpoint Status Register (Isochronous Endpoint)” on page 561
.
• TOGGLESQ: Data Toggle Clear
0 = No effect.
1 = Clear the PID data of the current bank
For OUT endpoints, the next received packet should be a DATA0.
For IN endpoints, the next packet will be sent with a DATA0 PID.
• RXRDY_TXKL: Received OUT Data Clear
0 = No effect.
1 = Clear the RXRDY_TXKL flag of UDPHS_EPTSTAx.
• TX_COMPLT: Transmitted IN Data Complete Clear
0 = No effect.
1 = Clear the TX_COMPLT flag of UDPHS_EPTSTAx.
• ERR_FL_ISO: Error Flow Clear
0 = No effect.
1 = Clear the ERR_FL_ISO flags of UDPHS_EPTSTAx.
• ERR_CRC_NTR: Number of Transaction Error Clear
0 = No effect.
1 = Clear the ERR_CRC_NTR flags of UDPHS_EPTSTAx.
• ERR_FLUSH: Bank Flush Error Clear
0 = No effect.
1 = Clear the ERR_FLUSH flags of UDPHS_EPTSTAx.
24
–
16
–
8
–
0
–
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32.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)
Name: UDPHS_EPTSTAx
Access: Read-only
31
SHRT_PCKT
30 29 28 27
BYTE_COUNT
26
23 20
15
NAK_OUT
22
BYTE_COUNT
21
14
NAK_IN
13
STALL_SNT
12
RX_SETUP
25 24
19 18
BUSY_BANK_STA
11
TXRDY
10
17 16
CURBK_CTLDIR
9 8
TX_COMPLT RXRDY_TXKL ERR_OVFLW
7 6
TOGGLESQ_STA
5
FRCESTALL
4
–
3
–
2
–
1
–
0
–
• FRCESTALL: Stall Handshake Request
0 = No effect.
1 = If set a STALL answer will be done to the host for the next handshake.
This bit is reset by hardware upon received SETUP.
• TOGGLESQ_STA: Toggle Sequencing
Toggle Sequencing:
– IN Endpoint: It indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to the current bank.
– CONTROL and OUT endpoint:
These bits are set by hardware to indicate the PID data of the current bank:
Value
0
1
2
3
Name
DATA0
DATA1
DATA2
MDATA
Description
DATA0
DATA1
Reserved for High Bandwidth Isochronous Endpoint
Reserved for High Bandwidth Isochronous Endpoint
Notes: 1. In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1).
2. These bits are updated for OUT transfer:
- A new data has been written into the current bank.
- The user has just cleared the Received OUT Data bit to switch to the next bank.
3. This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx
(disable endpoint).
• ERR_OVFLW: Overflow Error
This bit is set by hardware when a new too-long packet is received.
Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow
Error bit is set.
This bit is updated at the same time as the BYTE_COUNT field.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
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• RXRDY_TXKL: Received OUT Data/KILL Bank
– Received OUT Data (for OUT endpoint or Control endpoint):
This bit is set by hardware after a new packet has been stored in the endpoint FIFO.
This bit is cleared by the device firmware after reading the OUT data from the endpoint.
For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile.
Hardware assertion of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register RXRDY_TXKL bit.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
– KILL Bank (for IN endpoint):
– The bank is really cleared or the bank is sent, BUSY_BANK_STA is decremented.
– The bank is not cleared but sent on the IN transfer, TX_COMPLT
Note:
– The bank is not cleared because it was empty. The user should wait that this bit is cleared before trying to clear another packet.
“Kill a packet” may be refused if at the same time, an IN token is coming and the current packet is sent on the UDPHS line. In this case, the TX_COMPLT bit is set. Take notice however, that if at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. In fact, in that case, the current bank is sent (IN transfer) and the last bank is killed.
• TX_COMPLT: Transmitted IN Data Complete
This bit is set by hardware after an IN packet has been accepted (ACK’ed) by the host.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).
• TXRDY: TX Packet Ready
This bit is cleared by hardware after the host has acknowledged the packet.
For Multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit.
Hardware clear of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register TXRDY bit.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).
• RX_SETUP: Received SETUP
– (for Control endpoint only)
This bit is set by hardware when a valid SETUP packet has been received from the host.
It is cleared by the device firmware after reading the SETUP data from the endpoint FIFO.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).
• STALL_SNT: Stall Sent
– (for Control, Bulk and Interrupt endpoints)
This bit is set by hardware after a STALL handshake has been sent as requested by the UDPHS_EPTSTAx register FRCESTALL bit.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
• NAK_IN: NAK IN
This bit is set by hardware when a NAK handshake has been sent in response to an IN request from the Host.
This bit is cleared by software.
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• NAK_OUT: NAK OUT
This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the Host.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).
• CURBK_CTLDIR: Current Bank/Control Direction
– Current Bank (not relevant for Control endpoint):
These bits are set by hardware to indicate the number of the current bank.
Value
0
1
2
Name
BANK0
BANK1
BANK2
Description
Bank 0 (or single bank)
Bank 1
Bank 2
Note: The current bank is updated each time the user:
- Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank.
- Clears the received OUT data bit to access the next bank.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
– Control Direction (for Control endpoint only):
0 = A Control Write is requested by the Host.
1 = A Control Read is requested by the Host.
Notes: 1. This bit corresponds with the 7th bit of the bmRequestType (Byte 0 of the Setup Data).
2. This bit is updated after receiving new setup data.
• BUSY_BANK_STA: Busy Bank Number
These bits are set by hardware to indicate the number of busy banks.
IN endpoint : It indicates the number of busy banks filled by the user, ready for IN transfer.
OUT endpoint : It indicates the number of busy banks filled by OUT transaction from the Host.
Value
0
1
2
Name
1BUSYBANK
Description
1 busy bank
2BUSYBANKS 2 busy banks
3BUSYBANKS 3 busy banks
• BYTE_COUNT: UDPHS Byte Count
Byte count of a received data packet.
This field is incremented after each write into the endpoint (to prepare an IN transfer).
This field is decremented after each reading into the endpoint (OUT transfer).
This field is also updated at RXRDY_TXKL flag clear with the next bank.
This field is also updated at TXRDY flag set with the next bank.
This field is reset by EPT_x of UDPHS_EPTRST register.
• SHRT_PCKT: Short Packet
An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size.
This bit is updated at the same time as the BYTE_COUNT field.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
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32.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint)
Name: UDPHS_EPTSTAx (ISOENDPT)
Address: 0xF803C11C [0], 0xF803C13C [1], 0xF803C15C [2], 0xF803C17C [3], 0xF803C19C [4], 0xF803C1BC [5],
0xF803C1DC [6]
Access: Read-only
31
SHRT_PCKT
30 29 28 27
BYTE_COUNT
26 25 24
23
15
–
22
BYTE_COUNT
21
7 6
TOGGLESQ_STA
5
–
20
4
–
19 18
BUSY_BANK_STA
3
–
2
–
17
1
–
CURBK
This register view is relevant only if EPT_TYPE=0x1 in
“UDPHS Endpoint Configuration Register” on page 538
16
14
ERR_FLUSH
13
ERR_CRC_NT
R
12 11 10 9 8
ERR_FL_ISO TXRDY_TRER TX_COMPLT RXRDY_TXKL ERR_OVFLW
0
–
• TOGGLESQ_STA: Toggle Sequencing
Toggle Sequencing:
– IN Endpoint: It indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to the current bank.
– OUT endpoint:
These bits are set by hardware to indicate the PID data of the current bank:
Value
0
1
2
3
Name
DATA0
DATA1
DATA2
MDATA
Description
DATA0
DATA1
Data2 (only for High Bandwidth Isochronous Endpoint)
MData (only for High Bandwidth Isochronous Endpoint)
Notes: 1. In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1).
2. These bits are updated for OUT transfer:
- A new data has been written into the current bank.
- The user has just cleared the Received OUT Data bit to switch to the next bank.
3. For High Bandwidth Isochronous Out endpoint, it is recommended to check the UDPHS_EPTSTAx/TXRDY_TRER bit to know if the toggle sequencing is correct or not.
4. This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx
(disable endpoint).
• ERR_OVFLW: Overflow Error
This bit is set by hardware when a new too-long packet is received.
Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow
Error bit is set.
This bit is updated at the same time as the BYTE_COUNT field.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
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• RXRDY_TXKL: Received OUT Data/KILL Bank
– Received OUT Data (for OUT endpoint or Control endpoint):
This bit is set by hardware after a new packet has been stored in the endpoint FIFO.
This bit is cleared by the device firmware after reading the OUT data from the endpoint.
For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile.
Hardware assertion of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register RXRDY_TXKL bit.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
– KILL Bank (for IN endpoint):
– The bank is really cleared or the bank is sent, BUSY_BANK_STA is decremented.
– The bank is not cleared but sent on the IN transfer, TX_COMPLT
Note:
– The bank is not cleared because it was empty. The user should wait that this bit is cleared before trying to clear another packet.
“Kill a packet” may be refused if at the same time, an IN token is coming and the current packet is sent on the UDPHS line. In this case, the TX_COMPLT bit is set. Take notice however, that if at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. In fact, in that case, the current bank is sent (IN transfer) and the last bank is killed.
• TX_COMPLT: Transmitted IN Data Complete
This bit is set by hardware after an IN packet has been sent.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).
• TXRDY_TRER: TX Packet Ready/Transaction Error
– TX Packet Ready :
This bit is cleared by hardware, as soon as the packet has been sent.
For Multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit.
Hardware clear of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register TXRDY_TRER bit.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).
– Transaction Error (for high bandwidth isochronous OUT endpoints) (Read-Only):
This bit is set by hardware when a transaction error occurs inside one microframe.
If one toggle sequencing problem occurs among the n-transactions (n = 1, 2 or 3) inside a microframe, then this bit is still set as
bank is relative to a new “good” n-transactions, then this bit is reset.
Notes: 1. A transaction error occurs when the toggle sequencing does not respect the Universal Serial Bus Specification, Rev
2.0
(5.9.2 High Bandwidth Isochronous endpoints) (Bad PID, missing data....)
2. When a transaction error occurs, the user may empty all the “bad” transactions by clearing the Received OUT Data flag (RXRDY_TXKL).
If this bit is reset, then the user should consider that a new n-transaction is coming.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).
• ERR_FL_ISO: Error Flow
This bit is set by hardware when a transaction error occurs.
– Isochronous IN transaction is missed, the micro has no time to fill the endpoint (underflow).
– Isochronous OUT data is dropped because the bank is busy (overflow).
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
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• ERR_CRC_NTR: CRC ISO Error/Number of Transaction Error
– CRC ISO Error (for Isochronous OUT endpoints) (Read-only):
This bit is set by hardware if the last received data is corrupted (CRC error on data).
This bit is updated by hardware when new data is received (Received OUT Data bit).
– Number of Transaction Error (for High Bandwidth Isochronous IN endpoints):
This bit is set at the end of a microframe in which at least one data bank has been transmitted, if less than the number of transactions per micro-frame banks (UDPHS_EPTCFGx register NB_TRANS) have been validated for transmission inside this microframe.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
• ERR_FLUSH: Bank Flush Error
– (for High Bandwidth Isochronous IN endpoints)
This bit is set when flushing unsent banks at the end of a microframe.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).
• CURBK: Current Bank
– Current Bank :
These bits are set by hardware to indicate the number of the current bank.
Value
0
1
2
Name
BANK0
BANK1
BANK2
Description
Bank 0 (or single bank)
Bank 1
Bank 2
Note: The current bank is updated each time the user:
- Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank.
- Clears the received OUT data bit to access the next bank.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
• BUSY_BANK_STA: Busy Bank Number
These bits are set by hardware to indicate the number of busy banks.
IN endpoint : It indicates the number of busy banks filled by the user, ready for IN transfer.
OUT endpoint : It indicates the number of busy banks filled by OUT transaction from the Host.
Value
0
1
2
Name Description
1BUSYBANK 1 busy bank
2BUSYBANKS 2 busy banks
3BUSYBANKS 3 busy banks
• BYTE_COUNT: UDPHS Byte Count
Byte count of a received data packet.
This field is incremented after each write into the endpoint (to prepare an IN transfer).
This field is decremented after each reading into the endpoint (OUT transfer).
This field is also updated at RXRDY_TXKL flag clear with the next bank.
This field is also updated at TXRDY_TRER flag set with the next bank.
This field is reset by EPT_x of UDPHS_EPTRST register.
• SHRT_PCKT: Short Packet
An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size.
This bit is updated at the same time as the BYTE_COUNT field.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
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32.7.21 UDPHS DMA Channel Transfer Descriptor
The DMA channel transfer descriptor is loaded from the memory.
Be careful with the alignment of this buffer.
The structure of the DMA channel transfer descriptor is defined by three parameters as described below:
Offset 0:
The address must be aligned: 0xXXXX0
Next Descriptor Address Register: UDPHS_DMANXTDSCx
Offset 4:
The address must be aligned: 0xXXXX4
DMA Channelx Address Register: UDPHS_DMAADDRESSx
Offset 8:
The address must be aligned: 0xXXXX8
DMA Channelx Control Register: UDPHS_DMACONTROLx
To use the DMA channel transfer descriptor, fill the structures with the correct value (as described in the following pages).
Then write directly in UDPHS_DMANXTDSCx the address of the descriptor to be used first.
Then write 1 in the LDNXT_DSC bit of UDPHS_DMACONTROLx (load next channel transfer descriptor). The descriptor is automatically loaded upon Endpointx request for packet transfer.
32.7.22 UDPHS DMA Next Descriptor Address Register
Name:
Address:
Access:
31
UDPHS_DMANXTDSCx [x = 0..5]
0xF803C300 [0], 0xF803C310 [1], 0xF803C320 [2], 0xF803C330 [3], 0xF803C340 [4], 0xF803C350 [5]
Read-write
30 29 28 27
NXT_DSC_ADD
26 25 24
23 22 21 18 17 16
15
7
14
6
13
5
20 19
NXT_DSC_ADD
12 11
NXT_DSC_ADD
4
NXT_DSC_ADD
3
10
2
9
1
8
0
Note: Channel 0 is not used.
• NXT_DSC_ADD: Next Descriptor Address
This field points to the next channel descriptor to be processed. This channel descriptor must be aligned, so bits 0 to 3 of the address must be equal to zero.
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32.7.23 UDPHS DMA Channel Address Register
Name:
Address:
Access:
UDPHS_DMAADDRESSx [x = 0..5]
0xF803C304 [0], 0xF803C314 [1], 0xF803C324 [2], 0xF803C334 [3], 0xF803C344 [4], 0xF803C354 [5]
Read-write
31 30 29 28
BUFF_ADD
27 26 25 24
23 22 21 18 17 16
15
7
14
6
13
5
20
BUFF_ADD
19
12
BUFF_ADD
11
4
BUFF_ADD
3
10
2
9
1
8
0
Note: Channel 0 is not used.
• BUFF_ADD: Buffer Address
This field determines the AHB bus starting address of a DMA channel transfer.
Channel start and end addresses may be aligned on any byte boundary.
The firmware may write this field only when the UDPHS_DMASTATUS register CHANN_ENB bit is clear.
This field is updated at the end of the address phase of the current access to the AHB bus. It is incrementing of the access byte width. The access width is 4 bytes (or less) at packet start or end, if the start or end address is not aligned on a word boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written by software or loaded from the descriptor, whereas the channel end address is either determined by the end of buffer or the UDPHS device, USB end of transfer if the UDPHS_DMACONTROLx register END_TR_EN bit is set.
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32.7.24 UDPHS DMA Channel Control Register
Name:
Address:
Access:
UDPHS_DMACONTROLx [x = 0..5]
0xF803C308 [0], 0xF803C318 [1], 0xF803C328 [2], 0xF803C338 [3], 0xF803C348 [4], 0xF803C358 [5]
Read-write
31 30 29 28 27
BUFF_LENGTH
26 25 24
18 17 16 23
15
–
22
14
–
21
13
–
20 19
BUFF_LENGTH
12
–
7 6 5 4
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT
11
–
3
END_B_EN
10
–
9
–
8
–
2 1 0
END_TR_EN LDNXT_DSC CHANN_ENB
Note: Channel 0 is not used.
• CHANN_ENB: (Channel Enable Command)
0 = DMA channel is disabled at and no transfer will occur upon request. This bit is also cleared by hardware when the channel source bus is disabled at end of buffer.
If the UDPHS_DMACONTROL register LDNXT_DSC bit has been cleared by descriptor loading, the firmware will have to set the corresponding CHANN_ENB bit to start the described transfer, if needed.
If the UDPHS_DMACONTROL register LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both UDPHS_DMASTATUS register CHANN_ENB and CHANN_ACT flags read as 0.
If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty, then the
UDPHS_DMASTATUS register CHANN_ENB bit is cleared.
If the LDNXT_DSC bit is set at or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer occurs) and the next descriptor is immediately loaded.
1 = UDPHS_DMASTATUS register CHANN_ENB bit will be set, thus enabling DMA channel data transfer. Then any pending request will start the transfer. This may be used to start or resume any requested transfer.
• LDNXT_DSC: Load Next Channel Transfer Descriptor Enable (Command)
0 = No channel register is loaded after the end of the channel transfer.
1 = The channel controller loads the next descriptor after the end of the current transfer, i.e. when the
UDPHS_DMASTATUS/CHANN_ENB bit is reset.
If the UDPHS_DMA CONTROL/CHANN_ENB bit is cleared, the next descriptor is immediately loaded upon transfer request.
DMA Channel Control Command Summary
LDNXT_DSC
0
0
1
1
CHANN_ENB
0
1
0
1
Description
Stop now
Run and stop at end of buffer
Load next descriptor now
Run and link at end of buffer
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• END_TR_EN: End of Transfer Enable (Control)
Used for OUT transfers only.
0 = USB end of transfer is ignored.
1 = UDPHS device can put an end to the current buffer transfer.
When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX) will close the current buffer and the UDPHS_DMASTATUSx register END_TR_ST flag will be raised.
This is intended for UDPHS non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS microframe data buffer closure.
• END_B_EN: End of Buffer Enable (Control)
0 = DMA Buffer End has no impact on USB packet transfer.
1 = Endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and
SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0.
This is mainly for short packet IN validation initiated by the DMA reaching end of buffer, but could be used for OUT packet truncation (discarding of unwanted packet data) at the end of DMA buffer.
• END_TR_IT: End of Transfer Interrupt Enable
0 = UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising.
1 = An interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer.
Use when the receive size is unknown.
• END_BUFFIT: End of Buffer Interrupt Enable
0 = UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt.
1 = An interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero.
• DESC_LD_IT: Descriptor Loaded Interrupt Enable
0 = UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt.
1 = An interrupt is generated when a descriptor has been loaded from the bus.
• BURST_LCK: Burst Lock Enable
0 = The DMA never locks bus access.
1 = USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by
AHB burst duration.
• BUFF_LENGTH: Buffer Byte Length (Write-only)
This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size (64 Kbytes) is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0, but the transfer end may occur earlier under UDPHS device control.
When this field is written, The UDPHS_DMASTATUSx register BUFF_COUNT field is updated with the write value.
Notes: 1. Bits [31:2] are only writable when issuing a channel Control Command other than “Stop Now”.
2. For reliability it is highly recommended to wait for both UDPHS_DMASTATUSx register CHAN_ACT and CHAN_ENB flags are at 0, thus ensuring the channel has been stopped before issuing a command other than “Stop Now”.
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32.7.25 UDPHS DMA Channel Status Register
Name:
Address:
Access:
UDPHS_DMASTATUSx [x = 0..5]
0xF803C30C [0], 0xF803C31C [1], 0xF803C32C [2], 0xF803C33C [3], 0xF803C34C [4], 0xF803C35C [5]
Read-write
31 30 29 28
BUFF_COUNT
27 26 25 24
23 18 17 16
15
–
7
–
22
14
–
21
13
–
20
BUFF_COUNT
19
12
–
6 5 4
DESC_LDST END_BF_ST END_TR_ST
11
–
3
–
10
–
2
–
9
–
8
–
1 0
CHANN_ACT CHANN_ENB
Note: Channel 0 is not used.
• CHANN_ENB: Channel Enable Status
0 = If cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set.
When any transfer is ended either due to an elapsed byte count or a UDPHS device initiated transfer end, this bit is automatically reset.
1 = If set, the DMA channel is currently enabled and transfers data upon request.
This bit is normally set or cleared by writing into the UDPHS_DMACONTROLx register CHANN_ENB bit field either by software or descriptor loading.
If a channel request is currently serviced when the UDPHS_DMACONTROLx register CHANN_ENB bit is cleared, the DMA FIFO buffer is drained until it is empty, then this status bit is cleared.
• CHANN_ACT: Channel Active Status
0 = The DMA channel is no longer trying to source the packet data.
When a packet transfer is ended this bit is automatically reset.
1 = The DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.
When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel descriptor load (if any) and potentially until UDPHS packet transfer completion, if allowed by the new descriptor.
• END_TR_ST: End of Channel Transfer Status
0 = Cleared automatically when read by software.
1 = Set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer.
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
• END_BF_ST: End of Channel Buffer Status
0 = Cleared automatically when read by software.
1 = Set by hardware when the BUFF_COUNT downcount reach zero.
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
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• DESC_LDST: Descriptor Loaded Status
0 = Cleared automatically when read by software.
1 = Set by hardware when a descriptor has been loaded from the system bus.
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
• BUFF_COUNT: Buffer Byte Count
This field determines the current number of bytes still to be transferred for this buffer.
This field is decremented from the AHB source bus access byte width at the end of this bus address phase.
The access byte width is 4 by default, or less, at DMA start or end, if the start or end address is not aligned on a word boundary.
At the end of buffer, the DMA accesses the UDPHS device only for the number of bytes needed to complete it.
This field value is reliable (stable) only if the channel has been stopped or frozen (UDPHS_EPTCTLx register NT_DIS_DMA bit is used to disable the channel request) and the channel is no longer active CHANN_ACT flag is 0.
Note: For OUT endpoints, if the receive buffer byte length (BUFF_LENGTH) has been defaulted to zero because the USB transfer length is unknown, the actual buffer byte length received will be 0x10000-BUFF_COUNT.
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33.
USB Host High Speed Port (UHPHS)
33.1 Description
The USB Host High Speed Port (UHPHS) interfaces the USB with the host application. It handles Open HCI protocol
(Open Host Controller Interface) as well as Enhanced HCI protocol (Enhanced Host Controller Interface).
33.2 Embedded Characteristics
Compliant with Enhanced HCI Rev 1.0 Specification
Compliant with USB V2.0 High-speed
Supports High-speed 480 Mbps
Compliant with OpenHCI Rev 1.0 Specification
Compliant with USB V2.0 Full-speed and Low-speed Specification
Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices
Root Hub Integrated with 2 Downstream USB HS Ports and 1 FS Port
Embedded USB Transceivers
Supports Power Management
2 Hosts (A and B) High Speed (EHCI), Port A shared with UDPHS
1 Host (C) Full Speed only (OHCI)
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33.3 Block Diagram
Figure 33-1. Block Diagram
AHB
S l a ve
HCI
S l a ve Block
OHCI
Regi s ter s
Control
Li s t Proce ss or
Block
ED & TD
Reg s i s ter s
AHB
M as ter
HCI
M as ter Block
D a t a
FIFO 64 x 8
Root H ub a nd
Ho s t S IE
Root
H ub Regi s ter s
PORT S /M 0
PORT S /M 1
PORT S /M 2
Em b edded U S B v2.0 Tr a n s ceiver
U
U
S
S
B High-
Tr a n s s peed ceiver
B High-
Tr a n s s peed ceiver
U S B F S Tr a n s ceiver
HF S DPA
HF S DMA
HH S DPA
HH S DMA
HF S DPB
HF S DMB
HH S DPB
HH S DMB
HF S DPC
HF S DMC
AHB
AHB
S OF
Gener a tor
S l a ve
HCI
S l a ve Block
EHCI
Regi s ter s
Control
M as ter
HCI
M as ter Block
D a t a
Li s t
Proce ss or
P a cket
B u ffer
FIFO
Access to the USB host operational registers is achieved through the AHB bus slave interface. The Open HCI host controller and Enhanced HCI host controller initialize master DMA transfers through the AHB bus master interface as follows:
Fetches endpoint descriptors and transfer descriptors
Access to endpoint data from system memory
Access to the HC communication area
Write status and retire transfer descriptor
Memory access errors (abort, misalignment) lead to an “Unrecoverable Error” indicated by the corresponding flag in the host controller operational registers.
The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of downstream ports can be determined by the software driver reading the root hub’s operational registers. Device connection is automatically detected by the USB host port logic.
USB physical transceivers are integrated in the product and driven by the root hub’s ports.
Over current protection on ports can be activated by the USB host controller. Atmel’s standard product does not dedicate pads to external over current protection.
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33.4 Typical Connection
Figure 33-2. Board Schematic to Interface UHP High-speed Host Controller
+5V
"A" Receptacle
1 = VBUS
2 = D-
3 = D+
4 = GND
3 4
39 ± 1%
W
Shell = Shield
1 2
39 ± 1%
W
6K8 ± 1%
W
10 pF
PIO (VBUS ENABLE)
HHSDM
HFSDM
HHSDP
HFSDP
VBG
GNDUTMI
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33.5 Product Dependencies
33.5.1 I/O Lines
HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The embedded USB High Speed physical transceivers are controlled by the USB host controller.
One transceiver is shared with the USB High Speed Device (port A). The selection between Host Port A and USB Device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL control register.
In the case the port A is driven by the USB High Speed Device, the output signals are DFSDP, DFSDM, DHSDP and
DHSDM. The transceiver is automatically selected for Device operation once the USB High Speed Device is enabled.
In the case the port A is driven by the USB High Speed Host, the output signals are HFSDPA, HFSDMA, HHSDPA and
HHSDMA.
33.5.2 Power Management
The system embeds 2 transceivers.
The USB Host High Speed requires a 480 MHz clock for the embedded High-speed transceivers. This clock is provided by the UTMI PLL, it is UPLLCK.
In case power consumption is saved by stopping the UTMI PLL, high-speed operations are not possible. Nevertheless,
OHCI Full-speed operations remain possible by selecting PLLACK as the input clock of OHCI.
The High-speed transceiver returns a 30 MHz clock to the USB Host controller.
The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI full-speed operations. These clocks must be generated by a PLL with a correct accuracy of ± 0.25% thanks to USBDIV field.
Thus the USB Host peripheral receives three clocks from the Power Management Controller (PMC): the Peripheral Clock
(MCK domain), the UHP48M and the UHP12M (built-in UHP48M divided by four) used by the OHCI to interface with the bus USB signals (Recovered 12 MHz domain) in Full-speed operations.
For High-speed operations, the user has to perform the following:
Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER register.
Write CKGR_PLLCOUNT field in PMC_UCKR register.
Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB register.
Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register. USBDIV must be 9
(division by 10) if UPLLCK is selected.
Enable OHCI clocks, UHP bit in PMC_SCER register.
For OHCI Full-speed operations only, the user has to perform the following:
Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER register.
Select PLLACK as Input clock of OHCI part, USBS bit in PMC_USB register.
Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register. USBDIV value is to calculated regarding the PLLACK value and USB Full-speed accuracy.
Enable the OHCI clocks, UHP bit in PMC_SCER register.
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Figure 33-3. UHP Clock Trees
AHB
MCK
UPLL (4 8 0 MHz)
EHCI
M as ter
Interf a ce
EHCI
U s er
Interf a ce
OHCI
M as ter
Interf a ce
OHCI
U s er
Interf a ce
U S B 2.0 EHCI
Ho s t Controller
U S
Ho s
B 1.1 OHCI t Controller
Port
Ro u ter
Root H ub a nd
Ho s t S IE
3 0 MHz
UTMI tr a n s ceiver
3 0 MHz
UTMI tr a n s ceiver
F S tr a n s ceiver
OHCI clock s
33.5.3 Interrupt
The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling USB host interrupts requires programming the AIC before configuring the UHP HS.
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33.6 Functional Description
33.6.1 UTMI transceivers Sharing
The High Speed USB Host Port A is shared with the High Speed USB Device port and connected to the second UTMI transceiver. The selection between Host Port A and USB Device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL control register.
Figure 33-4. USB Selection
Other
Transceivers
HS
Transceiver
EN_UDPHS
1
Other Ports
HS USB Host
HS EHCI
FS OHCI
PA
DMA
0
HS
USB
Device
DMA
33.6.2 EHCI
The USB Host Port controller is fully compliant with the Enhanced HCI specification. The USB Host Port User Interface
( r e g i s t e r s d e s c r i p t i o n ) c a n b e f o u n d i n t h e E n h a n c e d H C I R e v 1 . 0 S p e c i f i c a t i o n a v a i l a b l e o n http://www.intel.com/technology/usb/ehcispec.htm
. The standard EHCI USB stack driver can be easily ported to Atmel’s architecture in the same way all existing class drivers run, without hardware specialization.
33.6.3 OHCI
The USB Host Port integrates a root hub and transceivers on downstream ports. It provides several Full-speed halfduplex serial communication ports at a baud rate of 12 Mbit/s. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.) and the USB hub can be connected to the USB host in the USB “tiered star” topology.
The USB Host Port controller is fully compliant with the Open HCI specification. The USB Host Port User Interface
( r e g i s t e r s d e s c r i p t i o n ) c a n b e f o u n d i n t h e O p e n H C I R e v 1 . 0 S p e c i f i c a t i o n a v a i l a b l e o n http://h18000.www1.hp.com/productinfo/development/openhci.html
. The standard OHCI USB stack driver can be easily ported to Atmel’s architecture, in the same way all existing class drivers run without hardware specialization.
This means that all standard class devices are automatically detected and available to the user’s application. As an example, integrating an HID (Human Interface Device) class driver provides a plug & play feature for all USB keyboards and mouses.
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34.
High Speed MultiMedia Card Interface (HSMCI)
34.1 Description
The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD
Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
The HSMCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead.
The HSMCI supports stream, block and multi block data read and write, and is compatible with the DMA Controller
(DMAC), minimizing processor intervention for large buffer transfers.
The HSMCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 1 slot(s). Each slot may be used to interface with a High Speed MultiMedia Card bus (up to 30 Cards) or with an SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection.
The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the High Speed MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use).
The SD Memory Card interface also supports High Speed MultiMedia Card operations. The main differences between
SD and High Speed MultiMedia Cards are the initialization process and the bus topology.
HSMCI fully supports CE-ATA Revision 1.1, built on the MMC System Specification v4.0. The module includes dedicated hardware to issue the command completion signal and capture the host command completion signal disable.
34.2 Embedded Characteristics
Compatible with MultiMedia Card Specification Version 4.3
Compatible with SD Memory Card Specification Version 2.0
Compatible with SDIO Specification Version 2.0
Compatible with CE-ATA Specification 1.1
Cards Clock Rate Up to Master Clock Divided by 2
Boot Operation Mode Support
High Speed Mode Support
Embedded Power Management to Slow Down Clock Rate When Not Used
Supports 1 Multiplexed Slot(s)
Each Slot for either a High Speed MultiMedia Card Bus (Up to 30 Cards) or an SD Memory Card
Support for Stream, Block and Multi-block Data Read and Write
Supports Connection to DMA Controller (DMAC)
Minimizes Processor Intervention for Large Buffer Transfers
Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental Access
Support for CE-ATA Completion Signal Disable Command
Protection Against Unexpected Modification On-the-Fly of the Configuration Registers
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34.3 Block Diagram
Figure 34-1. Block Diagram
APB Bridge
APB
DMAC
PMC
MCK
HSMCI Interface
PIO
Interrupt Control
HSMCI Interrupt
34.4 Application Block Diagram
Figure 34-2. Application Block Diagram
Application Layer ex: File System, Audio, Security, etc.
MCCK
(1)
MCCDA
(1)
MCDA0
(1)
MCDA1
(1)
MCDA2
(1)
MCDA3
(1)
Physical Layer
HSMCI Interface
1 2 3 4 5 6 7
9 1011 1213 8
MMC
9
1 2 3 4 5 6 7 8
SDCard
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34.5 Pin Name List
Table 34-1. I/O Lines Description for 4-bit Configuration
Pin Description
MCCDA
MCCK
Command/response
Clock
Comments
I/O/PP/OD CMD of an MMC or SDCard/SDIO
I/O CLK of an MMC or SD Card/SDIO
MCDA0 - MCDA3 Data 0..3 of Slot A I/O/PP DAT[0..3] of an MMC
DAT[0..3] of an SD Card/SDIO
Notes: 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA, MCDAy to HSMCIx_DAy.
2. I: Input, O: Output, PP: Push/Pull, OD: Open Drain.
34.6 Product Dependencies
34.6.1 I/O Lines
The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to HSMCI pins.
Table 34-2. I/O Lines
Instance
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
Signal
MCI0_CDA
MCI0_CK
MCI0_DA0
MCI0_DA1
MCI0_DA2
MCI0_DA3
MCI1_CDA
MCI1_CK
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
I/O Line
PA16
PA17
PA15
PA18
PA19
PA20
PA12
PA13
PA11
PA2
PA3
PA4
B
B
B
B
B
B
Peripheral
A
A
A
A
A
A
34.6.2 Power Management
The HSMCI is clocked through the Power Management Controller (PMC), so the programmer must first configure the
PMC to enable the HSMCI clock.
34.6.3 Interrupt
The HSMCI interface has an interrupt line connected to the interrupt controller.
Handling the HSMCI interrupt requires programming the interrupt controller before configuring the HSMCI.
Table 34-3. Peripheral IDs
Instance
HSMCI0
HSMCI1
ID
12
26
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34.7 Bus Topology
Figure 34-3. High Speed MultiMedia Memory Card Bus Topology
1 2 3 4 5 6 7
9 1011 1213 8
MMC
The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines.
Table 34-4. Bus Topology
Pin
Number
Name
7
8
5
6
3
4
1
2
9
10
11
12
DAT[3]
CMD
VSS1
VDD
CLK
VSS2
DAT[0]
DAT[1]
DAT[2]
DAT[4]
DAT[5]
DAT[6]
Type
S
S
I/O/PP
I/O/PP/OD
I/O
S
I/O/PP
I/O/PP
I/O/PP
I/O/PP
I/O/PP
I/O/PP
Data 0
Data 1
Data 2
Data 4
Data 5
Data 6
Description
(Slot z)
Data MCDz3
Command/response MCCDz
Supply voltage ground
Supply voltage
Clock
Supply voltage ground
VSS
VDD
MCCK
VSS
MCDz0
MCDz1
MCDz2
MCDz4
MCDz5
MCDz6
13 DAT[7] I/O/PP Data 7 MCDz7
Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain.
2. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA, MCDAy to HSMCIx_DAy.
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Figure 34-4. MMC Bus Connections (One Slot)
HSMCI
MCDA0
MCCDA
MCCK
1 2 3 4 5 6 7
9 1011 1213 8
MMC1
1 2 3 4 5 6 7
9 1011 1213 8
MMC2
1 2 3 4 5 6 7
9 1011 1213 8
MMC3
Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA MCDAy to HSMCIx_DAy.
Figure 34-5. SD Memory Card Bus Topology
9
1 2 3 4 5 6 7 8
SD CARD
The SD Memory Card bus includes the signals listed in
7
8
5
6
3
4
1
2
Table 34-5. SD Memory Card Bus Signals
Pin
Number
Name
CD/DAT[3]
CMD
VSS1
VDD
CLK
VSS2
DAT[0]
DAT[1]
S
S
I/O/PP
PP
I/O
S
I/O/PP
I/O/PP
Description
Card detect/ Data line Bit 3
Command/response
Supply voltage ground
Supply voltage
Clock
Supply voltage ground
Data line Bit 0
Data line Bit 1 or Interrupt
(Slot z)
MCDz3
MCCDz
VSS
VDD
MCCK
VSS
MCDz0
MCDz1
9 DAT[2] I/O/PP Data line Bit 2 MCDz2
Notes: 1. I: input, O: output, PP: Push Pull, OD: Open Drain.
2. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA, MCDAy to HSMCIx_DAy.
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Figure 34-6. SD Card Bus Connections with One Slot
MCDA0 - MCDA3
MCCK
MCCDA
SD CARD
Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA MCDAy to HSMCIx_DAy.
When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the
HSMCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of High Speed MultiMedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs.
34.8 High Speed MultiMedia Card Operations
After a power-on reset, the cards are initialized by a special message-based High Speed MultiMedia Card bus protocol.
Each message is represented by one of the following tokens:
Command: A command is a token that starts an operation. A command is sent from the host either to a single card
(addressed command) or to all connected cards (broadcast command). A command is transferred serially on the
CMD line.
Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line.
Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line.
Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards.
The structure of commands, responses and data blocks is described in the High Speed MultiMedia Card System
Specification. See also
.
High Speed MultiMedia Card bus data transfers are composed of these tokens.
There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock HSMCI Clock.
Two types of data transfer commands are defined:
Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum.
Block-oriented commands: These commands send a data block succeeded by CRC bits.
Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block
transmission has a pre-defined block count ( See “Data Transfer Operation” on page 584.
The HSMCI provides a set of registers to perform the entire range of High Speed MultiMedia Card operations.
34.8.1 Command - Response Operation
After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the HSMCI_CR Control Register.
The PWSEN bit saves power by dividing the HSMCI clock by 2 PWSDIV + 1 when the bus is inactive.
The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow stopping the HSMCI Clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth.
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All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMedia Card System Specification.
The two bus modes (open drain and push/pull) needed to process all the operations are defined in the HSMCI Command
Register. The HSMCI_CMDR allows a command to be carried out.
For example, to perform an ALL_SEND_CID command:
Host Command N
ID
Cycles CID
CMD S T Content CRC E Z ****** Z S T Content Z Z Z
.
Table 34-6. ALL_SEND_CID Command Description
CMD Index Type Argument Resp Abbreviation
CMD2 bcr
[31:0] stuff bits R2 ALL_SEND_CID
Command
Description
Asks all cards to send their CID numbers on the CMD line
Note: 1. bcr means broadcast command with response.
Table 34-7. Fields and Values for HSMCI_CMDR Command Register
Field Value
CMDNB (command number)
RSPTYP (response type)
2 (CMD2)
2 (R2: 136 bits response)
SPCMD (special command)
OPCMD (open drain command)
0 (not a special command)
1
MAXLAT (max latency for command to response) 0 (NID cycles ==> 5 cycles)
TRCMD (transfer command) 0 (No transfer)
TRDIR (transfer direction)
TRTYP (transfer type)
IOSPCMD (SDIO special command)
X (available only in transfer command)
X (available only in transfer command)
0 (not a special command)
The HSMCI_ARGR contains the argument field of the command.
To send a command, the user must perform the following steps:
Fill the argument register (HSMCI_ARGR) with the command argument.
Set the command register (HSMCI_CMDR) (see Table 34-7
).
The command is sent immediately after writing the command register.
While the card maintains a busy indication (at the end of a STOP_TRANSMISSION command CMD12, for example), a new command shall not be sent. The NOTBUSY flag in the status register (HSMCI_SR) is asserted when the card releases the busy indication.
If the command requires a response, it can be read in the HSMCI Response Register (HSMCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The HSMCI embeds an error detection to prevent any corrupted data during the transfer.
The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the Interrupt Enable Register (HSMCI_IER) allows using an interrupt method.
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Figure 34-7. Command/Response Functional Flow Diagram
S et the comm a nd a rg u ment
H S MCI_ARGR = Arg u ment (1)
S et the comm a nd
H S MCI_CMDR = Comm a nd
Re a d H S MCI_ S R
W a it for comm a nd re a dy s t a t us fl a g
Check error b it s in the s t a t us regi s ter (1)
CMDRDY
1
S t a t us error fl a g s ?
0
Ye s
RETURN ERROR
(1)
Re a d re s pon s e if re qu ired
Doe s the comm a nd involve a bus y indic a tion?
No
RETURN OK
Re a d H S MCI_ S R
0
NOTBU S Y
1
RETURN OK
Note: 1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the High Speed
MultiMedia Card specification).
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34.8.2 Data Transfer Operation
The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register
(HSMCI_CMDR).
These operations can be done using the features of the DMA Controller.
In all cases, the block length (BLKLEN field) must be defined either in the Mode Register HSMCI_MR, or in the Block
Register HSMCI_BLKR. This field determines the size of the data block.
Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time):
Open-ended/Infinite Multiple block read (or write):
The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received.
Multiple block read (or write) with pre-defined block count (since version 3.1 and higher):
The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the
HSMCI Block Register (HSMCI_BLKR). Otherwise the card will start an open-ended multiple block read. The
BCNT field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer.
34.8.3 Read Operation
The following flowchart (
Figure 34-8 ) shows how to read a single block with or without use of DMAC facilities. In this
example, a polling method is used to wait for the end of read. Similarly, the user can configure the Interrupt Enable
Register (HSMCI_IER) to trigger an interrupt at the end of read.
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Figure 34-8. Read Functional Flow Diagram
Send SELECT/DESELECT_CARD command
(1)
to select the card
Send SET_BLOCKLEN command
(1)
No
Reset the DMAEN bit
HSMCI_DMA &= ~DMAEN
Set the block length (in bytes)
HSMCI_MR l= (BlockLength<<16) (2)
Set the block count (if neccessary)
HSMCI_BLKR l= (BlockCount<<0)
Send READ_SINGLE_BLOCK command
(1)
Read with DMAC
Yes
Set the DMAEN bit
HSMCI_DMA |= DMAEN
Set the block length (in bytes)
HSMCI_BLKR |= (BlockLength << 16)
(2)
Configure the DMA channel X
DMAC_SADDRx = Data Address
DMAC_BTSIZE = BlockLength/4
DMACHEN[X] = TRUE
Number of words to read = BlockLength/4
Send READ_SINGLE_BLOCK command
(1)
Yes
Number of words to read = 0 ?
No
Read status register HSMCI_SR
Read status register HSMCI_SR
Poll the bit
XFRDONE = 0?
Poll the bit
RXRDY = 0?
No
Read data = HSMCI_RDR
Number of words to read =
Number of words to read -1
Yes
RETURN
Notes: 1. It is assumed that this command has been correctly sent (see Figure 34-7
).
2. This field is also accessible in the HSMCI Block Register (HSMCI_BLKR).
No
RETURN
Yes
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34.8.4 Write Operation
In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing non-multiple block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used.
If set, the bit DMAEN in the HSMCI_DMA register enables DMA transfer.
The following flowchart ( Figure 34-9
) shows how to write a single block with or without use of DMA facilities. Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register
(HSMCI_IMR).
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Figure 34-9. Write Functional Flow Diagram
Send SELECT/DESELECT_CARD command
(1)
to select the card
Send SET_BLOCKLEN command
(1)
No Yes
Write using DMAC
Reset theDMAEN bit
HSMCI_DMA &= ~DMAEN
Set the block length (in bytes)
HSMCI_MR |= (BlockLength) <<16)
(2)
Set the block count (if necessary)
HSMCI_BLKR |= (BlockCount << 0)
Send WRITE_SINGLE_BLOCK command
(1)
Set the DMAEN bit
HSMCI_DMA |= DMAEN
Set the block length (in bytes)
HSMCI_BLKR |= (BlockLength << 16)
(2)
Send WRITE_SINGLE_BLOCK command
(1)
Number of words to write = BlockLength/4
Configure the DMA channel X
DMAC_DADDRx = Data Address to write
DMAC_BTSIZE = BlockLength/4
DMAC_CHEN[X] = TRUE
Yes
Number of words to write = 0 ?
No
Read status register HSMCI_SR
Read status register HSMCI_SR
Poll the bit
TXRDY = 0?
No
HSMCI_TDR = Data to write
Number of words to write =
Number of words to write -1
Yes
Poll the bit
XFRDONE = 0?
No
RETURN
Yes
RETURN
Note:
1. It is assumed that this command has been correctly sent (see Figure 34-7
).
2. This field is also accessible in the HSMCI Block Register (HSMCI_BLKR).
The following flowchart (
) shows how to manage read multiple block and write multiple block transfers with the DMA Controller. Polling or interrupt method can be used to wait for the end of write according to the contents of the
Interrupt Mask Register (HSMCI_IMR).
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Figure 34-10. Read Multiple Block and Write Multiple Block
Send SELECT/DESELECT_CARD command
(1)
to select the card
Send SET_BLOCKLEN command
(1)
Set the block length
HSMCI_MR |= (BlockLength << 16)
Set the DMAEN bit
HSMCI_DMA |= DMAEN
Send WRITE_MULTIPLE_BLOCK or
READ_MULTIPLE_BLOCK command
(1)
Configure the HDMA channel X
DMAC_SADDRx and DMAC_DADDRx
DMAC_BTSIZE = BlockLength/4
DMAC_CHEN[X] = TRUE
Read status register DMAC_EBCISR and Poll Bit CBTC[X]
New Buffer ?
(2)
No
Read status register HSMCI_SR and Poll Bit FIFOEMPTY
Send STOP_TRANSMISSION command
(1)
Yes
Poll the bit
XFRDONE = 1
No
Yes
RETURN
Notes: 1. It is assumed that this command has been correctly sent (see
2. Handle errors reported in HSMCI_SR.
34.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller
1.
Wait until the current command execution has successfully terminated.
3. Check that CMDRDY and NOTBUSY fields are asserted in HSMCI_SR
2.
Program the block length in the card. This value defines the value block_length.
3.
Program the block length in the HSMCI Configuration Register with block_length value.
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4.
Program the HSMCI_DMA register with the following fields:
OFFSET field with dma_offset.
CHKSIZE is user defined and set according to DMAC_DCSIZE.
DMAEN is set to true to enable DMA hardware handshaking in the HSMCI. This bit was previously set to false.
5.
Issue a WRITE_SINGLE_BLOCK command writing HSMCI_ARG then HSMCI_CMDR.
6.
Program the DMA Controller.
1. Read the channel register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the
DMAC_EBCISR register.
3. Program the channel registers.
4. The DMAC_SADDRx register for Channel x must be set to the location of the source data. When the first data location is not word aligned, the two LSB bits define the temporary value called dma_offset.
The two
LSB bits of DMAC_SADDRx must be set to 0.
5. The DMAC_DADDRx register for Channel x must be set with the starting address of the HSMCI_FIFO address.
6. Program the DMAC_CTRLAx register of Channel x with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–DCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with CEILING((block_length + dma_offset) / 4), where the ceiling function is the function that returns the smallest integer not less than x.
7. Program the DMAC_CTRLBx register for Channel x with the following field’s values:
–DST_INCR is set to INCR, the block_length value must not be larger than the HSMCI_FIFO aperture.
–SRC_INCR is set to INCR.
–FC field is programmed with memory to peripheral flow control mode.
–both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA controller is able to prefetch data and write HSMCI simultaneously.
8. Program the DMAC_CFGx register for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMAC channel FIFO.
–DST_H2SEL is set to true to enable hardware handshaking on the destination.
–DST_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
9. Enable Channel x, writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.
7.
Wait for XFRDONE in the HSMCI_SR register.
34.8.6 READ_SINGLE_BLOCK Operation using DMA Controller
34.8.6.1 Block Length is Multiple of 4
1.
Wait until the current command execution has successfully completed.
1. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.
2.
Program the block length in the card. This value defines the value block_length.
3.
Program the block length in the HSMCI Configuration Register with block_length value.
4.
Set RDPROOF bit in HSMCI_MR to avoid overflow.
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5.
Program HSMCI_DMA register with the following fields:
ROPT field is set to 0.
OFFSET field is set to 0.
CHKSIZE is user defined.
DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit was previously set to false.
6.
Issue a READ_SINGLE_BLOCK command.
7.
Program the DMA controller.
1. Read the channel register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR register.
3. Program the channel registers.
4. The DMAC_SADDRx register for Channel x must be set with the starting address of the HSMCI_FIFO address.
5. The DMAC_DADDRx register for Channel x must be word aligned.
6. Program the DMAC_CTRLAx register of Channel x with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4.
7. Program the DMAC_CTRLBx register for Channel x with the following field’s values:
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA controller is able to prefetch data and write HSMCI simultaneously.
8. Program the DMAC_CFGx register for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
–Enable Channel x, writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.
8.
Wait for XFRDONE in the HSMCI_SR register.
34.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0)
In the previous DMA transfer flow (block length multiple of 4), the DMA controller is configured to use only WORD AHB access. When the block length is no longer a multiple of 4 this is no longer true. The DMA controller is programmed to copy exactly the block length number of bytes using 2 transfer descriptors.
1.
Use the previous step until READ_SINGLE_BLOCK then
2.
Program the DMA controller to use a two descriptors linked list.
1. Read the channel register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR register.
3. Program the channel registers in the Memory for the first descriptor. This descriptor will be word oriented.
This descriptor is referred to as LLI_W, standing for LLI word oriented transfer.
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4. The LLI_W.DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address.
5. The LLI_W.DMAC_DADDRx field in the memory must be word aligned.
6. Program LLI_W.DMAC_CTRLAx with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4. If BTSIZE is zero, this descriptor is skipped later.
7. Program LLI_W.DMAC_CTRLBx with the following field’s values:
–DST_INCR is set to INCR
–SRC_INCR is set to INCR
–FC field is programmed with peripheral to memory flow control mode.
–SRC_DSCR is set to zero. (descriptor fetch is enabled for the SRC)
–DST_DSCR is set to one. (descriptor fetch is disabled for the DST)
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA controller is able to prefetch data and write HSMCI simultaneously.
8. Program the LLI_W.DMAC_CFGx register for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero meaning that address are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
9. Program LLI_W.DMAC_DSCRx with the address of LLI_B descriptor. And set DSCRx_IF to the AHB Layer
ID. This operation actually links the Word oriented descriptor on the second byte oriented descriptor. When block_length[1:0] is equal to 0 (multiple of 4) LLI_W.DMAC_DSCRx points to 0, only LLI_W is relevant.
10. Program the channel registers in the Memory for the second descriptor. This descriptor will be byte oriented.
This descriptor is referred to as LLI_B, standing for LLI Byte oriented.
11. The LLI_B.DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address.
12. The LLI_B.DMAC_DADDRx is not relevant if previous word aligned descriptor was enabled. If 1, 2 or 3 bytes are transferred that address is user defined and not word aligned.
13. Program LLI_B.DMAC_CTRLAx with the following field’s values:
–DST_WIDTH is set to BYTE.
–SRC_WIDTH is set to BYTE.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer).
14. Program LLI_B.DMAC_CTRLBx with the following field’s values:
–DST_INCR is set to INCR
–SRC_INCR is set to INCR
–FC field is programmed with peripheral to memory flow control mode.
–Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor location points to 0.
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA Controller is able to prefetch data and write HSMCI simultaneously.
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15. Program LLI_B.DMAC_CFGx memory location for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
16. Program LLI_B.DMAC_DSCR with 0.
17. Program the DMAC_CTRLBx register for Channel x with 0. its content is updated with the LLI fetch operation.
18. Program DMAC_DSCRx with the address of LLI_W if block_length greater than 4 else with address of
LLI_B.
19. Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.
3.
Wait for XFRDONE in the HSMCI_SR register.
34.8.6.3 Block Length is Not Multiple of 4, with Padding Value (ROPT field in HSMCI_DMA register set to 1)
When the ROPT field is set to one, The DMA Controller performs only WORD access on the bus to transfer a nonmultiple of 4 block length. Unlike previous flow, in which the transfer size is rounded to the nearest multiple of 4.
1.
Program the HSMCI Interface, see previous flow.
ROPT field is set to 1.
2.
Program the DMA Controller
1. Read the channel register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR register.
3. Program the channel registers.
4. The DMAC_SADDRx register for Channel x must be set with the starting address of the HSMCI_FIFO address.
5. The DMAC_DADDRx register for Channel x must be word aligned.
6. Program the DMAC_CTRLAx register of Channel x with the following field’s values:
–DST_WIDTH is set to WORD
–SRC_WIDTH is set to WORD
–SCSIZE must be set according to the value of HSMCI_DMA.CHKSIZE Field.
–BTSIZE is programmed with CEILING(block_length/4).
7. Program the DMAC_CTRLBx register for Channel x with the following field’s values:
–DST_INCR is set to INCR
–SRC_INCR is set to INCR
–FC field is programmed with peripheral to memory flow control mode.
–both DST_DSCR and SRC_DSCR are set to 1. (descriptor fetch is disabled)
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is able to prefetch data and write HSMCI simultaneously.
8. Program the DMAC_CFGx register for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
–Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.
3.
Wait for XFRDONE in the HSMCI_SR register.
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34.8.7 WRITE_MULTIPLE_BLOCK
34.8.7.1 One Block per Descriptor
1.
Wait until the current command execution has successfully terminated.
1. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.
2.
Program the block length in the card. This value defines the value block_length.
3.
Program the block length in the HSMCI Configuration Register with block_length value.
4.
Program the HSMCI_DMA register with the following fields:
OFFSET field with dma_offset.
CHKSIZE is user defined.
DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit was previously set to false.
5.
Issue a WRITE_MULTIPLE_BLOCK command.
6.
Program the DMA Controller to use a list of descriptors. Each descriptor transfers one block of data. Block n of data is transferred with descriptor LLI(n).
1. Read the channel register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the
DMAC_EBCISR register.
3. Program a List of descriptors.
4. The LLI(n).DMAC_SADDRx memory location for Channel x must be set to the location of the source data.
When the first data location is not word aligned, the two LSB bits define the temporary value called dma_offset.
The two LSB bits of LLI(n).DMAC_SADDRx must be set to 0.
5. The LLI(n).DMAC_DADDRx register for Channel x must be set with the starting address of the
HSMCI_FIFO address.
6. Program the LLI(n).DMAC_CTRLAx register of Channel x with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–DCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with CEILING((block_length + dma_offset)/4).
7. Program the LLI(n).DMAC_CTRLBx register for Channel x with the following field’s values:
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–DST_DSCR is set to 0 (fetch operation is enabled for the destination).
–SRC_DSCR is set to 1 (source address is contiguous).
–FC field is programmed with memory to peripheral flow control mode.
–Both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA Controller is able to prefetch data and write HSMCI simultaneously.
8. Program the LLI(n).DMAC_CFGx register for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_REP is set to 0. (contiguous memory access at block boundary)
–DST_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
9. If LLI(n) is the last descriptor, then LLI(n).DSCR points to 0 else LLI(n) points to the start address of
LLI(n+1).
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10. Program DMAC_CTRLBx for the Channel Register x with 0. Its content is updated with the LLI fetch operation.
11. Program DMAC_DSCRx for the Channel Register x with the address of the first descriptor LLI(0).
12. Enable Channel x writing one to DMAC_CHER[x]. The DMA is ready and waiting for request.
7.
Poll CBTC[x] bit in the DMAC_EBCISR Register.
8.
If a new list of buffers shall be transferred, repeat step 6. Check and handle HSMCI errors.
9.
Poll FIFOEMPTY field in the HSMCI_SR.
10. Send The STOP_TRANSMISSION command writing HSMCI_ARG then HSMCI_CMDR.
11. Wait for XFRDONE in the HSMCI_SR register.
34.8.8 READ_MULTIPLE_BLOCK
34.8.8.1 Block Length is a Multiple of 4
1.
Wait until the current command execution has successfully terminated.
1. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.
2.
Program the block length in the card. This value defines the value block_length.
3.
Program the block length in the HSMCI Configuration Register with block_length value.
4.
Set RDPROOF bit in HSMCI_MR to avoid overflow.
5.
Program the HSMCI_DMA register with the following fields:
ROPT field is set to 0.
OFFSET field is set to 0.
CHKSIZE is user defined.
DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit was previously set to false.
6.
Issue a READ_MULTIPLE_BLOCK command.
7.
Program the DMA Controller to use a list of descriptors:
1. Read the channel register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR register.
3. Program the channel registers in the Memory with the first descriptor. This descriptor will be word oriented.
This descriptor is referred to as LLI_W(n), standing for LLI word oriented transfer for block n .
4. The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address.
5. The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned.
6. Program LLI_W(n).DMAC_CTRLAx with the following field’s values:
–DST_WIDTH is set to WORD
–SRC_WIDTH is set to WORD
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4.
7. Program LLI_W(n).DMAC_CTRLBx with the following field’s values:
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC).
–DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is able to prefetch data and write HSMCI simultaneously.
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8. Program the LLI_W(n).DMAC_CFGx register for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero. Addresses are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
9. Program LLI_W(n).DMAC_DSCRx with the address of LLI_W(n+1) descriptor. And set the DSCRx_IF to the
AHB Layer ID. This operation actually links descriptors together. If LLI_W(n) is the last descriptor then
LLI_W(n).DMAC_DSCRx points to 0.
10. Program the DMAC_CTRLBx register for Channel x with 0. its content is updated with the LLI Fetch operation.
11. Program DMAC_DSCRx register for Channel x with the address of LLI_W(0).
12. Enable Channel x writing one to DMAC_CHER[x]. The DMA is ready and waiting for request.
8.
Poll CBTC[x] bit in the DMAC_EBCISR Register.
9.
If a new list of buffer shall be transferred repeat step 6. Check and handle HSMCI errors.
10. Poll FIFOEMPTY field in the HSMCI_SR.
11. Send The STOP_TRANSMISSION command writing the HSMCI_ARG then the HSMCI_CMDR.
12. Wait for XFRDONE in the HSMCI_SR register.
34.8.8.2 Block Length is Not Multiple of 4. (ROPT field in HSMCI_DMA register set to 0)
Two DMA Transfer descriptors are used to perform the HSMCI block transfer.
1.
Use the previous step to configure the HSMCI to perform a READ_MULTIPLE_BLOCK command.
2.
Issue a READ_MULTIPLE_BLOCK command.
3.
Program the DMA Controller to use a list of descriptors.
1. Read the channel register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the
DMAC_EBCISR register.
3. For every block of data repeat the following procedure:
4. Program the channel registers in the Memory for the first descriptor. This descriptor will be word oriented.
This descriptor is referred to as LLI_W(n) standing for LLI word oriented transfer for block n .
5. The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address.
6. The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned.
7. Program LLI_W(n).DMAC_CTRLAx with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4. If BTSIZE is zero, this descriptor is skipped later.
8. Program LLI_W(n).DMAC_CTRLBx with the following field’s values:
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC).
–DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is able to prefetch data and write HSMCI simultaneously.
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9. Program the LLI_W(n).DMAC_CFGx register for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero. Address are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
10. Program LLI_W(n).DMAC_DSCRx with the address of LLI_B(n) descriptor. And set the DSCRx_IF to the
AHB Layer ID. This operation actually links the Word oriented descriptor on the second byte oriented descriptor. When block_length[1:0] is equal to 0 (multiple of 4) LLI_W(n).DMAC_DSCRx points to 0, only
LLI_W(n) is relevant.
11. Program the channel registers in the Memory for the second descriptor. This descriptor will be byte oriented.
This descriptor is referred to as LLI_B(n), standing for LLI Byte oriented.
12. The LLI_B(n).DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address.
13. The LLI_B(n).DMAC_DADDRx is not relevant if previous word aligned descriptor was enabled. If 1, 2 or 3 bytes are transferred, that address is user defined and not word aligned.
14. Program LLI_B(n).DMAC_CTRLAx with the following field’s values:
–DST_WIDTH is set to BYTE.
–SRC_WIDTH is set to BYTE.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer).
15. Program LLI_B(n).DMAC_CTRLBx with the following field’s values:
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor location points to 0.
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is able to prefetch data and write HSMCI simultaneously.
16. Program LLI_B(n).DMAC_CFGx memory location for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMAC channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller
17. Program LLI_B(n).DMAC_DSCR with address of descriptor LLI_W(n+1). If LLI_B(n) is the last descriptor, then program LLI_B(n).DMAC_DSCR with 0.
18. Program the DMAC_CTRLBx register for Channel x with 0, its content is updated with the LLI Fetch operation.
19. Program DMAC_DSCRx with the address of LLI_W(0) if block_length is greater than 4 else with address of
LLI_B(0).
20. Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.
4.
Enable DMADONE interrupt in the HSMCI_IER register.
5.
Poll CBTC[x] bit in the DMAC_EBCISR Register.
6.
If a new list of buffers shall be transferred, repeat step 7. Check and handle HSMCI errors.
7.
Poll FIFOEMPTY field in the HSMCI_SR.
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8.
Send The STOP_TRANSMISSION command writing HSMCI_ARG then HSMCI_CMDR.
9.
Wait for XFRDONE in the HSMCI_SR register.
34.8.8.3 Block Length is Not a Multiple of 4. (ROPT field in HSMCI_DMA register set to 1)
One DMA Transfer descriptor is used to perform the HSMCI block transfer, the DMA writes a rounded up value to the nearest multiple of 4.
1.
Use the previous step to configure the HSMCI to perform a READ_MULTIPLE_BLOCK.
2.
Set the ROPT field to 1 in the HSMCI_DMA register.
3.
Issue a READ_MULTIPLE_BLOCK command.
4.
Program the DMA controller to use a list of descriptors:
1. Read the channel register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the
DMAC_EBCISR register.
3. Program the channel registers in the Memory with the first descriptor. This descriptor will be word oriented.
This descriptor is referred to as LLI_W(n), standing for LLI word oriented transfer for block n .
4. The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address.
5. The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned.
6. Program LLI_W(n).DMAC_CTRLAx with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with Ceiling(block_length/4).
7. Program LLI_W(n).DMAC_CTRLBx with the following field’s values:
–DST_INCR is set to INCR
–SRC_INCR is set to INCR
–FC field is programmed with peripheral to memory flow control mode.
–SRC_DSCR is set to 0. (descriptor fetch is enabled for the SRC)
–DST_DSCR is set to TRUE. (descriptor fetch is disabled for the DST)
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is able to prefetch data and write HSMCI simultaneously.
8. Program the LLI_W(n).DMAC_CFGx register for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero. Address are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
9. Program LLI_W(n).DMAC_DSCRx with the address of LLI_W(n+1) descriptor. And set the DSCRx_IF to the
AHB Layer ID. This operation actually links descriptors together. If LLI_W(n) is the last descriptor then
LLI_W(n).DMAC_DSCRx points to 0.
10. Program the DMAC_CTRLBx register for Channel x with 0. its content is updated with the LLI Fetch operation.
11. Program the DMAC_DSCRx register for Channel x with the address of LLI_W(0).
12. Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.
5.
Poll CBTC[x] bit in the DMAC_EBCISR register.
6.
If a new list of buffers shall be transferred repeat step 7. Check and handle HSMCI errors.
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7.
Poll FIFOEMPTY field in the HSMCI_SR.
8.
Send The STOP_TRANSMISSION command writing the HSMCI_ARG then the HSMCI_CMDR.
9.
Wait for XFRDONE in the HSMCI_SR register.
34.9 SD/SDIO Card Operation
The High Speed MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO
(SD Input Output) Card commands.
SD/SDIO cards are based on the MultiMedia Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features. The physical form factor, pin assignment and data transfer protocol are forward-compatible with the High Speed MultiMedia Card with some additions. SD slots can actually be used for more than flash memory cards. Devices that support SDIO can use small devices designed for the SD form factor, such as GPS receivers, Wi-Fi or Bluetooth adapters, modems, barcode readers,
IrDA adapters, FM radio tuners, RFID readers, digital cameras and more.
SD/SDIO is covered by numerous patents and trademarks, and licensing is only available through the Secure Digital
Card Association.
The SD/SDIO Card communication is based on a 9-pin interface (Clock, Command, 4 x Data and 3 x Power lines). The communication protocol is defined as a part of this specification. The main difference between the SD/SDIO Card and the
High Speed MultiMedia Card is the initialization process.
The SD/SDIO Card Register (HSMCI_SDCR) allows selection of the Card Slot and the data bus width.
The SD/SDIO Card bus allows dynamic configuration of the number of data lines. After power up, by default, the
SD/SDIO Card uses only DAT0 for data transfer. After initialization, the host can change the bus width (number of active data lines).
34.9.1 SDIO Data Transfer Type
SDIO cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format (1 to 511 blocks), while the SD memory cards are fixed in the block transfer mode. The TRTYP field in the HSMCI Command Register
(HSMCI_CMDR) allows to choose between SDIO Byte or SDIO Block transfer.
The number of bytes/blocks to transfer is set through the BCNT field in the HSMCI Block Register (HSMCI_BLKR). In
SDIO Block mode, the field BLKLEN must be set to the data block size while this field is not used in SDIO Byte mode.
An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share access to the SD bus. In order to allow the sharing of access to the host among multiple devices, SDIO and combo cards can implement the optional concept of suspend/resume (Refer to the SDIO Specification for more details). To send a suspend or a resume command, the host must set the SDIO Special Command field (IOSPCMD) in the HSMCI Command Register.
34.9.2 SDIO Interrupts
Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO Specification for more details). In order to allow the SDIO card to interrupt the host, an interrupt function is added to a pin on the DAT[1] line to signal the card’s interrupt to the host. An SDIO interrupt on each slot can be enabled through the HSMCI Interrupt Enable
Register. The SDIO interrupt is sampled regardless of the currently selected slot.
34.10 CE-ATA Operation
CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is mapped onto MMC register space.
CE-ATA utilizes five MMC commands:
GO_IDLE_STATE (CMD0): used for hard reset.
STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be aborted.
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FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, 8 bit access only.
RW_MULTIPLE_REGISTERS (CMD60): used to issue an ATA command or to access the control/status registers.
RW_MULTIPLE_BLOCK (CMD61): used to transfer data for an ATA command.
CE-ATA utilizes the same MMC command sequences for initialization as traditional MMC devices.
34.10.1 Executing an ATA Polling Command
1.
Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8kB of DATA.
2.
Read the ATA status register until DRQ is set.
3.
Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
4.
Read the ATA status register until DRQ && BSY are set to 0.
34.10.2 Executing an ATA Interrupt Command
1.
Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8kB of DATA with nIEN field set to zero to enable the command completion signal in the device.
2.
Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
3.
Wait for Completion Signal Received Interrupt.
34.10.3 Aborting an ATA Command
If the host needs to abort an ATA command prior to the completion signal it must send a special command to avoid potential collision on the command line. The SPCMD field of the HSMCI_CMDR must be set to 3 to issue the CE-ATA completion Signal Disable Command.
34.10.4 CE-ATA Error Recovery
Several methods of ATA command failure may occur, including:
No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60).
CRC is invalid for an MMC command or response.
CRC16 is invalid for an MMC data packet.
ATA Status register reflects an error by setting the ERR bit to one.
The command completion signal does not arrive within a host specified time out period.
Error conditions are expected to happen infrequently. Thus, a robust error recovery mechanism may be used for each error event.
The recommended error recovery procedure after a timeout is:
Issue the command completion signal disable if nIEN was cleared to zero and the RW_MULTIPLE_BLOCK
(CMD61) response has been received.
Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response.
Issue a software reset to the CE-ATA device using FAST_IO (CMD39).
If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA commands. However, if the error recovery procedure does not work as expected or there is another timeout, the next step is to issue
GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE (CMD0) is a hard reset to the device and completely resets all device states.
Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed again. If the CE-ATA device completes all MMC commands correctly but fails the ATA command with the ERR bit set in the ATA Status register, no error recovery action is required. The ATA command itself failed implying that the device could not complete the action requested, however, there was no communication or protocol failure. After the device signals an error by setting the ERR bit to one in the ATA Status register, the host may attempt to retry the command.
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34.11 HSMCI Boot Operation Mode
In boot operation mode, the processor can read boot data from the slave (MMC device) by keeping the CMD line low after power-on before issuing CMD1. The data can be read from either the boot area or user area, depending on register setting.
34.11.1 Boot Procedure, Processor Mode
1.
Configure the HSMCI data bus width programming SDCBUS Field in the HSMCI_SDCR register. The
BOOT_BUS_WIDTH field located in the device Extended CSD register must be set accordingly.
2.
Set the byte count to 512 bytes and the block count to the desired number of blocks, writing BLKLEN and BCNT fields of the HSMCI_BLKR Register.
3.
Issue the Boot Operation Request command by writing to the HSMCI_CMDR register with SPCMD field set to
BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”.
4.
The BOOT_ACK field located in the HSMCI_CMDR register must be set to one, if the BOOT_ACK field of the
MMC device located in the Extended CSD register is set to one.
5.
Host processor can copy boot data sequentially as soon as the RXRDY flag is asserted.
6.
When Data transfer is completed, host processor shall terminate the boot stream by writing the HSMCI_CMDR register with SPCMD field set to BOOTEND.
34.11.2 Boot Procedure DMA Mode
1.
Configure the HSMCI data bus width by programming SDCBUS Field in the HSMCI_SDCR register. The
BOOT_BUS_WIDTH field in the device Extended CSD register must be set accordingly.
2.
Set the byte count to 512 bytes and the block count to the desired number of blocks by writing BLKLEN and BCNT fields of the HSMCI_BLKR register.
3.
Enable DMA transfer in the HSMCI_DMA register.
4.
Configure DMA controller, program the total amount of data to be transferred and enable the relevant channel.
5.
Issue the Boot Operation Request command by writing to the HSMCI_CMDR register with SPCND set to
BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”.
6.
DMA controller copies the boot partition to the memory.
7.
When DMA transfer is completed, host processor shall terminate the boot stream by writing the HSMCI_CMDR register with SPCMD field set to BOOTEND.
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34.12 HSMCI Transfer Done Timings
34.12.1 Definition
The XFRDONE flag in the HSMCI_SR indicates exactly when the read or write sequence is finished.
34.12.2 Read Access
During a read access, the XFRDONE flag behaves as shown in
.
Figure 34-11. XFRDONE During a Read Access
CMD line
H S MCI re a d CMD C a rd re s pon s e
The CMDRDY fl a g i s rele as ed 8 t b it a fter the end of the c a rd re s pon s e.
CMDRDY fl a g
D a t a
Not bus y fl a g
XFRDONE fl a g
1 s t Block L as t Block
34.12.3 Write Access
During a write access, the XFRDONE flag behaves as shown in Figure 34-12 .
Figure 34-12. XFRDONE During a Write Access
CMD line
H S MCI write CMD C a rd re s pon s e
CMDRDY fl a g
The CMDRDY fl a g i s rele as ed 8 t b it a fter the end of the c a rd re s pon s e.
D0
D a t a bus - D0
Not bus y fl a g
XFRDONE fl a g
1 s t Block
1 s t Block
L as t Block
D0 i s tied b y the c a rd
D0 i s rele as ed
L as t Block
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34.13 Write Protection Registers
To prevent any single software error that may corrupt HSMCI behavior, the entire HSMCI address space from address
(HSMCI_WPMR).
If a write access to anywhere in the HSMCI address space from address offset 0x000 to 0x00FC is detected, then the
WPVS flag in the HSMCI Write Protect Status Register (HSMCI_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the HSMCI Write Protect Mode Register (HSMCI_WPMR) with the appropriate access key, WPKEY.
The protected registers are:
“HSMCI Mode Register” on page 605
“HSMCI Data Timeout Register” on page 606
“HSMCI SDCard/SDIO Register” on page 607
“HSMCI Completion Signal Timeout Register” on page 612
“HSMCI DMA Configuration Register” on page 625
“HSMCI Configuration Register” on page 626
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34.14 High Speed MultiMedia Card Interface (HSMCI) User Interface
Table 34-8. Register Mapping
Offset
0x00 Control Register
0x04
0x08
0x0C
0x10
0x14
Mode Register
Data Timeout Register
SD/SDIO Card Register
Argument Register
Command Register
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38 - 0x3C
0x40
0x44
0x48
0x4C
0x50
0x54
0x58-0xE0
0xE4
0xE8
0xEC - 0xFC
0x100-0x1FC
0x200
...
0x5FC
Block Register
Completion Signal Timeout Register
Receive Data Register
Transmit Data Register
Reserved
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
DMA Configuration Register
Configuration Register
Reserved
Write Protection Mode Register
Write Protection Status Register
Reserved
Reserved
FIFO Memory Aperture0
...
FIFO Memory Aperture255
HSMCI_CR
HSMCI_MR
HSMCI_DTOR
HSMCI_SDCR
HSMCI_ARGR
HSMCI_CMDR
HSMCI_BLKR
HSMCI_CSTOR
HSMCI_RSPR
HSMCI_RSPR
HSMCI_RSPR
HSMCI_RSPR
HSMCI_RDR
HSMCI_TDR
–
HSMCI_SR
HSMCI_IER
HSMCI_IDR
HSMCI_IMR
HSMCI_DMA
HSMCI_CFG
–
HSMCI_WPMR
HSMCI_WPSR
–
–
HSMCI_FIFO0
...
HSMCI_FIFO255
Write
Read-write
Read-write
Read-write
Read-write
Write
Read-write
Read-write
Read
Read
Read
Read
Read
Write
–
Read
Write
Write
Read
Read-write
Read-write
–
Read-write
Read-only
–
–
Read-write
...
Read-write
0x0
–
–
0xC0E5
–
–
0x0
0x00
0x0
0x0
0x0
0x0
0x0
0x0
0x00
–
–
–
–
–
0x0
...
0x0
–
0x0
0x0
0x0
0x0
–
Notes: 1. The Response Register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to
0x2C). N depends on the size of the response.
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34.14.1 HSMCI Control Register
Name: HSMCI_CR
Address: 0xF0008000 (0), 0xF000C000 (1)
Access: Write-only
31
–
30
–
29
–
23
–
15
–
7
SWRST
22
–
14
–
6
–
21
–
13
–
5
–
12
–
4
–
28
–
20
–
27
–
19
–
11
–
3
PWSDIS
26
–
18
–
10
–
2
PWSEN
25
–
17
–
9
–
1
MCIDIS
• MCIEN: Multi-Media Interface Enable
0 = No effect.
1 = Enables the Multi-Media Interface if MCDIS is 0.
• MCIDIS: Multi-Media Interface Disable
0 = No effect.
1 = Disables the Multi-Media Interface.
• PWSEN: Power Save Mode Enable
0 = No effect.
1 = Enables the Power Saving Mode if PWSDIS is 0.
Warning: Before enabling this mode, the user must set a value different from 0 in the PWSDIV field (Mode Register,
HSMCI_MR).
• PWSDIS: Power Save Mode Disable
0 = No effect.
1 = Disables the Power Saving Mode.
• SWRST: Software Reset
0 = No effect.
1 = Resets the HSMCI. A software triggered hardware reset of the HSMCI interface is performed.
24
–
16
–
8
–
0
MCIEN
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34.14.2 HSMCI Mode Register
Name: HSMCI_MR
Address: 0xF0008004 (0), 0xF000C004 (1)
Access: Read-write
31
–
30
–
29
–
23
–
15
–
7
22
–
14
PADV
6
21
–
13
FBYTE
5
28
–
20
–
27
–
19
–
12
WRPROOF
4
CLKDIV
11
RDPROOF
3
26
–
18
–
10
2
25
–
17
–
9
PWSDIV
1
24
–
16
CLKODD
8
0
• CLKDIV: Clock Divider
High Speed MultiMedia Card Interface clock (MCCK or HSMCI_CK) is Master Clock (MCK) divider by ({CLKDIV,CLKODD}+2).
• PWSDIV: Power Saving Divider
High Speed MultiMedia Card Interface clock is divided by 2 (PWSDIV) + 1 when entering Power Saving Mode.
Warning: This value must be different from 0 before enabling the Power Save Mode in the HSMCI_CR (HSMCI_PWSEN bit).
• RDPROOF: Read Proof Enable
Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full. This will guarantee data integrity, not bandwidth.
0 = Disables Read Proof.
1 = Enables Read Proof.
• WRPROOF: Write Proof Enable
Enabling Write Proof allows to stop the HSMCI Clock during write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth.
0 = Disables Write Proof.
1 = Enables Write Proof.
• FBYTE: Force Byte Transfer
Enabling Force Byte Transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported.
Warning: BLKLEN value depends on FBYTE.
0 = Disables Force Byte Transfer.
1 = Enables Force Byte Transfer.
• PADV: Padding Value
0 = 0x00 value is used when padding data in write transfer.
1 = 0xFF value is used when padding data in write transfer.
PADV may be only in manual transfer.
• CLKODD: Clock divider is odd
This field is the least significant bit of the clock divider and indicates the clock divider parity.
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34.14.3 HSMCI Data Timeout Register
Name: HSMCI_DTOR
Address: 0xF0008008 (0), 0xF000C008 (1)
Access: Read-write
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
21
–
13
–
5
DTOMUL
12
–
4
28
–
20
–
11
–
3
27
–
19
–
10
–
2
26
–
18
–
DTOCYC
9
–
1
25
–
17
–
8
–
0
24
–
16
–
• DTOCYC: Data Timeout Cycle Number
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers. It equals (DTOCYC x Multiplier).
• DTOMUL: Data Timeout Multiplier
Multiplier is defined by DTOMUL as shown in the following table:
5
6
3
4
7
Value
0
1
2
Name
1
16
128
256
1024
4096
65536
1048576
Description
DTOCYC
DTOCYC x 16
DTOCYC x 128
DTOCYC x 256
DTOCYC x 1024
DTOCYC x 4096
DTOCYC x 65536
DTOCYC x 1048576
If the data time-out set by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error flag (DTOE) in the HSMCI Status
Register (HSMCI_SR) rises.
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34.14.4 HSMCI SDCard/SDIO Register
Name: HSMCI_SDCR
Address: 0xF000800C (0), 0xF000C00C (1)
Access: Read-write
31
–
30
–
29
–
23
–
15
–
7
SDCBUS
22
–
14
–
6
21
–
13
–
5
–
12
–
4
–
28
–
20
–
11
–
3
–
27
–
19
–
10
–
2
–
26
–
18
–
9
–
1
25
–
17
–
SDCSEL
8
–
0
24
–
16
–
• SDCSEL: SDCard/SDIO Slot
Value
0
1
2
3
Name
SLOTA
SLOTB
SLOTC
SLOTD
–
–
Description
Slot A is selected .
–
• SDCBUS: SDCard/SDIO Bus Width
Value
0
1
2
3
Name
1
–
4
8
Description
1 bit
Reserved
4 bit
8 bit
SAM9X35 [DATASHEET]
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607
34.14.5 HSMCI Argument Register
Name: HSMCI_ARGR
Address: 0xF0008010 (0), 0xF000C010 (1)
Access: Read-write
31 30 29
22 23
15
7
14
6
21
13
5
28
ARG
20
ARG
12
ARG
4
ARG
27
19
11
3
• ARG: Command Argument
10
2
26
18
9
1
25
17
8
0
24
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
608
34.14.6 HSMCI Command Register
Name: HSMCI_CMDR
Address: 0xF0008014 (0), 0xF000C014 (1)
Access: Write-only
31
–
30
–
29
–
21 23
–
15
–
7
22
–
14
–
6
13
–
5
RSPTYP
28
–
20
TRTYP
12
MAXLAT
4
27
BOOT_ACK
19
11
OPDCMD
3
CMDNB
26
ATACS
18
TRDIR
10
2
25
IOSPCMD
24
17 16
TRCMD
9
SPCMD
1
8
0
This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writable by an interrupt response (field SPCMD). This means that the current command execution cannot be interrupted or modified.
• CMDNB: Command Number
This is the command index.
• RSPTYP: Response Type
Value
0
1
2
3
Name
NORESP
48_BIT
136_BIT
R1B
Description
No response.
48-bit response.
136-bit response.
R1b response type
• SPCMD: Special Command
Value
0
Name
STD
1 INIT
2
3
4
5
6
7
SYNC
CE_ATA
IT_CMD
IT_RESP
BOR
EBO
Description
Not a special CMD.
Initialization CMD:
74 clock cycles for initialization sequence.
Synchronized CMD:
Wait for the end of the current data block transfer before sending the pending command.
CE-ATA Completion Signal disable Command.
The host cancels the ability for the device to return a command completion signal on the command line.
Interrupt command:
Corresponds to the Interrupt Mode (CMD40).
Interrupt response:
Corresponds to the Interrupt Mode (CMD40).
Boot Operation Request.
Start a boot operation mode, the host processor can read boot data from the MMC device directly.
End Boot Operation.
This command allows the host processor to terminate the boot operation mode.
SAM9X35 [DATASHEET]
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• OPDCMD: Open Drain Command
0 (PUSHPULL) = Push pull command.
1 (OPENDRAIN) = Open drain command.
• MAXLAT: Max Latency for Command to Response
0 (5) = 5-cycle max latency.
1 (64) = 64-cycle max latency.
• TRCMD: Transfer Command
Value
0
1
2
3
Name
NO_DATA
START_DATA
STOP_DATA
–
Description
No data transfer
Start data transfer
Stop data transfer
Reserved
• TRDIR: Transfer Direction
0 (WRITE) = Write.
1 (READ) = Read.
• TRTYP: Transfer Type
Value
0
1
2
4
5
Name
SINGLE
MULTIPLE
STREAM
BYTE
BLOCK
Description
MMC/SD Card Single Block
MMC/SD Card Multiple Block
MMC Stream
SDIO Byte
SDIO Block
• IOSPCMD: SDIO Special Command
Value
0
1
2
Name
STD
SUSPEND
RESUME
Description
Not an SDIO Special Command
SDIO Suspend Command
SDIO Resume Command
• ATACS: ATA with Command Completion Signal
0 (NORMAL) = Normal operation mode.
1 (COMPLETION) = This bit indicates that a completion signal is expected within a programmed amount of time
(HSMCI_CSTOR).
• BOOT_ACK: Boot Operation Acknowledge.
The master can choose to receive the boot acknowledge from the slave when a Boot Request command is issued. When set to one this field indicates that a Boot acknowledge is expected within a programmable amount of time defined with DTOMUL and
DTOCYC fields located in the HSMCI_DTOR register. If the acknowledge pattern is not received then an acknowledge timeout error is raised. If the acknowledge pattern is corrupted then an acknowledge pattern error is set.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
610
34.14.7 HSMCI Block Register
Name: HSMCI_BLKR
Address: 0xF0008018 (0), 0xF000C018 (1)
Access: Read-write
31 30 29
23
15
7
22
14
6
21
13
5
28
BLKLEN
27
20 19
BLKLEN
12 11
BCNT
4 3
BCNT
26
18
10
2
25
17
9
1
24
16
8
0
• BCNT: MMC/SDIO Block Count - SDIO Byte Count
This field determines the number of data byte(s) or block(s) to transfer.
The transfer data type and the authorized values for BCNT field are determined by the TRTYP field in the HSMCI Command Register (HSMCI_CMDR).
When TRTYP=1 (MMC/SDCARD Multiple Block), BCNT can be programmed from 1 to 65535, 0 corresponds to an infinite block transfer.
When TRTYP=4 (SDIO Byte), BCNT can be programmed from 1 to 511, 0 corresponds to 512-byte transfer. Values in range 512 to 65536 are forbidden.
When TRTYP=5 (SDIO Block), BCNT can be programmed from 1 to 511, 0 corresponds to an infinite block transfer. Values in range 512 to 65536 are forbidden.
Warning: In SDIO Byte and Block modes (TRTYP=4 or 5), writing the 7 last bits of BCNT field with a value which differs from 0 is forbidden and may lead to unpredictable results.
• BLKLEN: Data Block Length
This field determines the size of the data block.
This field is also accessible in the HSMCI Mode Register (HSMCI_MR).
Bits 16 and 17 must be set to 0 if FBYTE is disabled.
Note: In SDIO Byte mode, BLKLEN field is not used.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
611
34.14.8 HSMCI Completion Signal Timeout Register
Name: HSMCI_CSTOR
Address: 0xF000801C (0), 0xF000C01C (1)
Access: Read-write
31
–
30
–
29
–
28
–
23
–
15
–
7
–
22
–
14
–
6
21
–
13
–
5
CSTOMUL
20
–
12
–
4
11
–
3
27
–
19
–
10
–
2
26
–
18
–
CSTOCYC
9
–
1
25
–
17
–
8
–
0
24
–
16
–
• CSTOCYC: Completion Signal Timeout Cycle Number
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers. Its value is calculated by (CSTOCYC x Multiplier).
• CSTOMUL: Completion Signal Timeout Multiplier
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers. Its value is calculated by (CSTOCYC x Multiplier).
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between the end of the data transfer and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If a non-DATA
ATA command is issued, the HSMCI starts waiting immediately after the end of the response until the completion signal.
Multiplier is defined by CSTOMUL as shown in the following table:
5
6
3
4
7
Value
0
1
2
Name
1
16
128
256
1024
4096
65536
1048576
Description
CSTOCYC x 1
CSTOCYC x 16
CSTOCYC x 128
CSTOCYC x 256
CSTOCYC x 1024
CSTOCYC x 4096
CSTOCYC x 65536
CSTOCYC x 1048576
If the data time-out set by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error flag (CSTOE) in the HSMCI Status Register (HSMCI_SR) rises.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
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34.14.9 HSMCI Response Register
Name: HSMCI_RSPR
Address: 0xF0008020 (0), 0xF000C020 (1)
Access: Read-only
31 30 29 28 27 26 25 24
RSP
23 22 21 20 19 18 17 16
RSP
15 14 13 12 11 10 9 8
RSP
7 6 5 4 3 2 1 0
RSP
• RSP: Response
Note: 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to
0x2C).
N depends on the size of the response.
SAM9X35 [DATASHEET]
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613
34.14.10 HSMCI Receive Data Register
Name: HSMCI_RDR
Address: 0xF0008030 (0), 0xF000C030 (1)
Access: Read-only
31 30 29
23
15
7
22
14
6
21
13
5
28
DATA
27
20 19
DATA
12 11
DATA
4 3
DATA
• DATA: Data to Read
10
2
26
18
9
1
25
17
8
0
24
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
614
34.14.11 HSMCI Transmit Data Register
Name: HSMCI_TDR
Address: 0xF0008034 (0), 0xF000C034 (1)
Access: Write-only
31 30 29
23
15
7
22
14
6
21
13
5
28
DATA
27
20 19
DATA
12 11
DATA
4 3
DATA
• DATA: Data to Write
10
2
26
18
9
1
25
17
8
0
24
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
615
34.14.12 HSMCI Status Register
Name: HSMCI_SR
Address: 0xF0008040 (0), 0xF000C040 (1)
Access: Read-only
31
UNRE
30
OVRE
29
ACKRCVE
23
CSTOE
15
–
7
–
22
DTOE
14
–
6
–
21
DCRCE
13
CSRCV
5
NOTBUSY
28
ACKRCV
20
RTOE
12
SDIOWAIT
4
DTIP
27
XFRDONE
19
RENDE
11
–
3
BLKE
26
FIFOEMPTY
18
RCRCE
10
–
2
TXRDY
25
DMADONE
17
RDIRE
9
–
1
RXRDY
24
BLKOVRE
16
RINDE
8
SDIOIRQA
0
CMDRDY
• CMDRDY: Command Ready
0 = A command is in progress.
1 = The last command has been sent. Cleared when writing in the HSMCI_CMDR.
• RXRDY: Receiver Ready
0 = Data has not yet been received since the last read of HSMCI_RDR.
1 = Data has been received since the last read of HSMCI_RDR.
• TXRDY: Transmit Ready
0= The last data written in HSMCI_TDR has not yet been transferred in the Shift Register.
1= The last data written in HSMCI_TDR has been transferred in the Shift Register.
• BLKE: Data Block Ended
This flag must be used only for Write Operations.
0 = A data block transfer is not yet finished. Cleared when reading the HSMCI_SR.
1 = A data block transfer has ended, including the CRC16 Status transmission.
the flag is set for each transmitted CRC Status.
Refer to the MMC or SD Specification for more details concerning the CRC Status.
• DTIP: Data Transfer in Progress
0 = No data transfer in progress.
1 = The current data transfer is still in progress, including CRC16 calculation. Cleared at the end of the CRC16 calculation.
• NOTBUSY: HSMCI Not Busy
A block write operation uses a simple busy signalling of the write operation duration on the data (DAT0) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line
(DAT0) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free.
Refer to the MMC or SD Specification for more details concerning the busy behavior.
For all the read operations, the NOTBUSY flag is cleared at the end of the host command.
For the Infinite Read Multiple Blocks, the NOTBUSY flag is set at the end of the STOP_TRANSMISSION host command
(CMD12).
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
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For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block.
For the Multiple Block Reads with pre-defined block count, the NOTBUSY flag is set at the end of the last received data block.
The NOTBUSY flag allows to deal with these different states.
0 = The HSMCI is not ready for new data transfer. Cleared at the end of the card response.
1 = The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data receive buffer of the card.
• SDIOIRQA: SDIO Interrupt for Slot A
0 = No interrupt detected on SDIO Slot A.
1 = An SDIO Interrupt on Slot A occurred. Cleared when reading the HSMCI_SR.
• SDIOWAIT: SDIO Read Wait Operation Status
0 = Normal Bus operation.
1 = The data bus has entered IO wait state.
• CSRCV: CE-ATA Completion Signal Received
0 = No completion signal received since last status read operation.
1 = The device has issued a command completion signal on the command line. Cleared by reading in the HSMCI_SR register.
• RINDE: Response Index Error
0 = No error.
1 = A mismatch is detected between the command index sent and the response index received. Cleared when writing in the
HSMCI_CMDR.
• RDIRE: Response Direction Error
0 = No error.
1 = The direction bit from card to host in the response has not been detected.
• RCRCE: Response CRC Error
0 = No error.
1 = A CRC7 error has been detected in the response. Cleared when writing in the HSMCI_CMDR.
• RENDE: Response End Bit Error
0 = No error.
1 = The end bit of the response has not been detected. Cleared when writing in the HSMCI_CMDR.
• RTOE: Response Time-out Error
0 = No error.
1 = The response time-out set by MAXLAT in the HSMCI_CMDR has been exceeded. Cleared when writing in the
HSMCI_CMDR.
• DCRCE: Data CRC Error
0 = No error.
1 = A CRC16 error has been detected in the last data block. Cleared by reading in the HSMCI_SR register.
• DTOE: Data Time-out Error
0 = No error.
1 = The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded. Cleared by reading in the
HSMCI_SR register.
SAM9X35 [DATASHEET]
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• CSTOE: Completion Signal Time-out Error
0 = No error.
1 = The completion signal time-out set by CSTOCYC and CSTOMUL in HSMCI_CSTOR has been exceeded. Cleared by reading in the HSMCI_SR register. Cleared by reading in the HSMCI_SR register.
• BLKOVRE: DMA Block Overrun Error
0 = No error.
1 = A new block of data is received and the DMA controller has not started to move the current pending block, a block overrun is raised. Cleared by reading in the HSMCI_SR register.
• DMADONE: DMA Transfer done
0 = DMA buffer transfer has not completed since the last read of the HSMCI_SR register.
1 = DMA buffer transfer has completed.
• FIFOEMPTY: FIFO empty flag
0 = FIFO contains at least one byte.
1 = FIFO is empty.
• XFRDONE: Transfer Done flag
0 = A transfer is in progress.
1 = Command Register is ready to operate and the data bus is in the idle state.
• ACKRCV: Boot Operation Acknowledge Received
0 = No Boot acknowledge received since the last read of the status register.
1 = A Boot acknowledge signal has been received. Cleared by reading the HSMCI_SR register.
• ACKRCVE: Boot Operation Acknowledge Error
0 = No error
1 = Corrupted Boot Acknowledge signal received.
• OVRE: Overrun
0 = No error.
1 = At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command.
When FERRCTRL in HSMCI_CFG is set to 1, OVRE becomes reset after read.
• UNRE: Underrun
0 = No error.
1 = At least one 8-bit data has been sent without valid information (not written). Cleared when sending a new data transfer command or when setting FERRCTRL in HSMCI_CFG to 1 .
When FERRCTRL in HSMCI_CFG is set to 1, UNRE becomes reset after read.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
618
34.14.13 HSMCI Interrupt Enable Register
Name: HSMCI_IER
Address: 0xF0008044 (0), 0xF000C044 (1)
Access: Write-only
31
UNRE
30
OVRE
29
ACKRCVE
23
CSTOE
15
–
7
–
22
DTOE
14
–
6
–
21
DCRCE
13
CSRCV
5
NOTBUSY
28
ACKRCV
20
RTOE
12
SDIOWAIT
4
DTIP
• CMDRDY: Command Ready Interrupt Enable
• RXRDY: Receiver Ready Interrupt Enable
• TXRDY: Transmit Ready Interrupt Enable
• BLKE: Data Block Ended Interrupt Enable
• DTIP: Data Transfer in Progress Interrupt Enable
• NOTBUSY: Data Not Busy Interrupt Enable
• SDIOIRQA: SDIO Interrupt for Slot A Interrupt Enable
• SDIOWAIT: SDIO Read Wait Operation Status Interrupt Enable
• CSRCV: Completion Signal Received Interrupt Enable
• RINDE: Response Index Error Interrupt Enable
• RDIRE: Response Direction Error Interrupt Enable
• RCRCE: Response CRC Error Interrupt Enable
• RENDE: Response End Bit Error Interrupt Enable
• RTOE: Response Time-out Error Interrupt Enable
• DCRCE: Data CRC Error Interrupt Enable
• DTOE: Data Time-out Error Interrupt Enable
• CSTOE: Completion Signal Timeout Error Interrupt Enable
• BLKOVRE: DMA Block Overrun Error Interrupt Enable
• DMADONE: DMA Transfer completed Interrupt Enable
27
XFRDONE
19
RENDE
11
–
3
BLKE
26
FIFOEMPTY
18
RCRCE
10
–
2
TXRDY
25
DMADONE
17
RDIRE
9
–
1
RXRDY
24
BLKOVRE
16
RINDE
8
SDIOIRQA
0
CMDRDY
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
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• FIFOEMPTY: FIFO empty Interrupt enable
• XFRDONE: Transfer Done Interrupt enable
• ACKRCV: Boot Acknowledge Interrupt Enable
• ACKRCVE: Boot Acknowledge Error Interrupt Enable
• OVRE: Overrun Interrupt Enable
• UNRE: Underrun Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
620
34.14.14 HSMCI Interrupt Disable Register
Name: HSMCI_IDR
Address: 0xF0008048 (0), 0xF000C048 (1)
Access: Write-only
31
UNRE
30
OVRE
29
ACKRCVE
23
CSTOE
15
–
7
–
22
DTOE
14
–
6
–
21
DCRCE
13
CSRCV
5
NOTBUSY
28
ACKRCV
20
RTOE
12
SDIOWAIT
4
DTIP
• CMDRDY: Command Ready Interrupt Disable
• RXRDY: Receiver Ready Interrupt Disable
• TXRDY: Transmit Ready Interrupt Disable
• BLKE: Data Block Ended Interrupt Disable
• DTIP: Data Transfer in Progress Interrupt Disable
• NOTBUSY: Data Not Busy Interrupt Disable
• SDIOIRQA: SDIO Interrupt for Slot A Interrupt Disable
• SDIOWAIT: SDIO Read Wait Operation Status Interrupt Disable
• CSRCV: Completion Signal received interrupt Disable
• RINDE: Response Index Error Interrupt Disable
• RDIRE: Response Direction Error Interrupt Disable
• RCRCE: Response CRC Error Interrupt Disable
• RENDE: Response End Bit Error Interrupt Disable
• RTOE: Response Time-out Error Interrupt Disable
• DCRCE: Data CRC Error Interrupt Disable
• DTOE: Data Time-out Error Interrupt Disable
• CSTOE: Completion Signal Time out Error Interrupt Disable
• BLKOVRE: DMA Block Overrun Error Interrupt Disable
• DMADONE: DMA Transfer completed Interrupt Disable
27
XFRDONE
19
RENDE
11
–
3
BLKE
26
FIFOEMPTY
18
RCRCE
10
–
2
TXRDY
25
DMADONE
17
RDIRE
9
–
1
RXRDY
24
BLKOVRE
16
RINDE
8
SDIOIRQA
0
CMDRDY
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
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• FIFOEMPTY: FIFO empty Interrupt Disable
• XFRDONE: Transfer Done Interrupt Disable
• ACKRCV: Boot Acknowledge Interrupt Disable
• ACKRCVE: Boot Acknowledge Error Interrupt Disable
• OVRE: Overrun Interrupt Disable
• UNRE: Underrun Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
622
34.14.15 HSMCI Interrupt Mask Register
Name: HSMCI_IMR
Address: 0xF000804C (0), 0xF000C04C (1)
Access: Read-only
31
UNRE
30
OVRE
29
ACKRCVE
23
CSTOE
15
–
7
–
22
DTOE
14
–
6
–
21
DCRCE
13
CSRCV
5
NOTBUSY
28
ACKRCV
20
RTOE
12
SDIOWAIT
4
DTIP
• CMDRDY: Command Ready Interrupt Mask
• RXRDY: Receiver Ready Interrupt Mask
• TXRDY: Transmit Ready Interrupt Mask
• BLKE: Data Block Ended Interrupt Mask
• DTIP: Data Transfer in Progress Interrupt Mask
• NOTBUSY: Data Not Busy Interrupt Mask
• SDIOIRQA: SDIO Interrupt for Slot A Interrupt Mask
• SDIOWAIT: SDIO Read Wait Operation Status Interrupt Mask
• CSRCV: Completion Signal Received Interrupt Mask
• RINDE: Response Index Error Interrupt Mask
• RDIRE: Response Direction Error Interrupt Mask
• RCRCE: Response CRC Error Interrupt Mask
• RENDE: Response End Bit Error Interrupt Mask
• RTOE: Response Time-out Error Interrupt Mask
• DCRCE: Data CRC Error Interrupt Mask
• DTOE: Data Time-out Error Interrupt Mask
• CSTOE: Completion Signal Time-out Error Interrupt Mask
• BLKOVRE: DMA Block Overrun Error Interrupt Mask
• DMADONE: DMA Transfer Completed Interrupt Mask
27
XFRDONE
19
RENDE
11
–
3
BLKE
26
FIFOEMPTY
18
RCRCE
10
–
2
TXRDY
25
DMADONE
17
RDIRE
9
–
1
RXRDY
24
BLKOVRE
16
RINDE
8
SDIOIRQA
0
CMDRDY
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
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• FIFOEMPTY: FIFO Empty Interrupt Mask
• XFRDONE: Transfer Done Interrupt Mask
• ACKRCV: Boot Operation Acknowledge Received Interrupt Mask
• ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask
• OVRE: Overrun Interrupt Mask
• UNRE: Underrun Interrupt Mask
0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
624
34.14.16 HSMCI DMA Configuration Register
Name: HSMCI_DMA
Address: 0xF0008050 (0), 0xF000C050 (1)
Access: Read-write
31 30 29
–
23
–
15
–
7
–
22
–
14
–
6
21
–
13
–
5
CHKSIZE
28
–
20
–
12
ROPT
4
11
–
3
–
27
–
19
–
10
–
2
–
26
–
18
–
9
–
1
25
–
17
–
24
–
16
–
OFFSET
8
DMAEN
0
• OFFSET: DMA Write Buffer Offset
This field indicates the number of discarded bytes when the DMA writes the first word of the transfer.
• CHKSIZE: DMA Channel Read and Write Chunk Size
The CHKSIZE field indicates the number of data available when the DMA chunk transfer request is asserted.
Value
0
1
2
3
–
Name
1
4
8
16
–
Description
1 data available
4 data available
8 data available
16 data available
Reserved
• DMAEN: DMA Hardware Handshaking Enable
0 = DMA interface is disabled.
1 = DMA Interface is enabled.
Note: To avoid unpredictable behavior, DMA hardware handshaking must be disabled when CPU transfers are performed.
• ROPT: Read Optimization with padding
0: BLKLEN bytes are moved from the Memory Card to the system memory, two DMA descriptors are used when the transfer size is not a multiple of 4.
1: Ceiling(BLKLEN/4) * 4 bytes are moved from the Memory Card to the system memory, only one DMA descriptor is used.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
625
34.14.17 HSMCI Configuration Register
Name: HSMCI_CFG
Address: 0xF0008054 (0), 0xF000C054 (1)
Access: Read-write
31 30 29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
LSYNC
4
FERRCTRL
11
–
3
–
27
–
19
–
10
–
2
–
26
–
18
–
1
–
9
–
25
–
17
–
24
–
16
–
8
HSMODE
0
FIFOMODE
• FIFOMODE: HSMCI Internal FIFO control mode
0 = A write transfer starts when a sufficient amount of data is written into the FIFO.
When the block length is greater than or equal to 3/4 of the HSMCI internal FIFO size, then the write transfer starts as soon as half the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write transfer starts as soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data is written in the internal FIFO.
1 = A write transfer starts as soon as one data is written into the FIFO.
• FERRCTRL: Flow Error flag reset control mode
0= When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag.
1= When an underflow/overflow condition flag is set, a read status resets the flag.
• HSMODE: High Speed Mode
0= Default bus timing mode.
1= If set to one, the host controller outputs command line and data lines on the rising edge of the card clock. The Host driver shall check the high speed support in the card registers.
• LSYNC: Synchronize on the last block
0= The pending command is sent at the end of the current data block.
1= The pending command is sent at the end of the block transfer when the transfer length is not infinite. (block count shall be different from zero)
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34.14.18 HSMCI Write Protect Mode Register
Name: HSMCI_WPMR
Address: 0xF00080E4 (0), 0xF000C0E4 (1)
Access: Read-write
31 30 29 28 27
WP_KEY (0x4D => “M”)
23 22 21
15
7
14
6
13
5
20 19
WP_KEY (0x43 => C”)
12 11
WP_KEY (0x49 => “I”)
4 3
10
2
26
18
• WP_EN: Write Protection Enable
0 = Disables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII).
1 = Enables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII).
• WP_KEY: Write Protection Key password
Should be written at value 0x4D4349 (ASCII code for “MCI”). Writing any other value in this field has no effect.
Protects the registers:
•
“HSMCI Mode Register” on page 605
•
“HSMCI Data Timeout Register” on page 606
•
“HSMCI SDCard/SDIO Register” on page 607
•
“HSMCI Completion Signal Timeout Register” on page 612
•
“HSMCI DMA Configuration Register” on page 625
•
“HSMCI Configuration Register” on page 626
9
1
25
17
24
16
8
0
WP_EN
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34.14.19 HSMCI Write Protect Status Register
Name: HSMCI_WPSR
Address: 0xF00080E8 (0), 0xF000C0E8 (1)
Access: Read-only
31
–
30
–
29
–
23 22 21
15
7
–
14
6
–
13
5
–
28
–
27
–
20
WP_VSRC
19
12
WP_VSRC
11
4
–
3
26
–
18
10
25
–
17
9
2
WP_VS
1
24
–
16
8
0
• WP_VS: Write Protection Violation Status
Value
0
1
2
3
Name
NONE
WRITE
RESET
BOTH
Description
No Write Protection Violation occurred since the last read of this register (WP_SR)
Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.)
Software reset had been performed while Write Protection was enabled (since the last read).
Both Write Protection violation and software reset with Write
Protection enabled have occurred since the last read.
• WP_VSRC: Write Protection Violation SouRCe
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted.
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34.14.20 HSMCI FIFOx Memory Aperture
Name: HSMCI_FIFOx[x=0..255]
Address: 0xF0008200 (0), 0xF000C200 (1)
Access: Read-write
31 30 29
23
15
7
22
14
6
21
13
5
28
DATA
27
20 19
DATA
12 11
DATA
4 3
DATA
• DATA: Data to Read or Data to Write
10
2
26
18
9
1
25
17
8
0
24
16
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35.
Serial Peripheral Interface (SPI)
35.1 Description
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s).
Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer.
Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted.
Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
35.2 Embedded Characteristics
Supports Communication with Serial External Devices
Master Mode can drive SPCK up to peripheral clock (bounded by maximum bus clock divided by 2)
Slave Mode operates on SPCK, asynchronously to Core and Bus ClockFour Chip Selects with External
Decoder Support Allow Communication with Up to 15 Peripherals
Four Chip Selects with External Decoder Support Allow Communication with Up to 15 Peripherals
Serial Memories, such as DataFlash and 3-wire EEPROMs
Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
External Coprocessors
Master or Slave Serial Peripheral Bus Interface
8-bit to 16-bit Programmable Data Length Per Chip Select
Programmable Phase and Polarity Per Chip Select
Programmable Transfer Delay Between Consecutive Transfers and Delay before SPI Clock per Chip Select
Programmable Delay Between Chip Selects
Selectable Mode Fault Detection
Connection to DMA Channel Capabilities Optimizes Data Transfers
One channel for the Receiver, One Channel for the Transmitter
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35.3 Block Diagram
Figure 35-1. Block Diagram
AHB M a trix DMA Ch.
Peripher a l Bridge
APB
PMC
MCK
SPI Interface
Interrupt Control
PIO
SPI Interrupt
35.4 Application Block Diagram
Figure 35-2. Application Block Diagram: Single Master/Multiple Slave Implementation
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
NPCS3
NC
SPCK
MISO
MOSI
NSS
SPCK
MISO
MOSI
NSS
SPCK
MISO
MOSI
NSS
Slave 0
Slave 1
Slave 2
SPCK
MISO
MOSI
NPCS0/NSS
NPCS1
NPCS2
NPCS3
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35.5 Signal Description
Table 35-1. Signal Description
Pin Name Pin Description
MISO
MOSI
SPCK
NPCS1-NPCS3
NPCS0/NSS
Master In Slave Out
Master Out Slave In
Serial Clock
Peripheral Chip Selects
Peripheral Chip Select/Slave Select
Master
Input
Output
Output
Output
Output
Type
Slave
Output
Input
Input
Unused
Input
35.6 Product Dependencies
35.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions.
Table 35-2. I/O Lines
Instance
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI1
SPI1
SPI1
SPI1
SPI1
SPI1
SPI1
Signal
SPI0_MISO
SPI0_MOSI
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
SPI0_SPCK
SPI1_MISO
SPI1_MOSI
SPI1_NPCS0
SPI1_NPCS1
SPI1_NPCS2
SPI1_NPCS3
SPI1_SPCK
PA21
PA22
PA8
PA0
PA31
PA30
PA23
I/O Line
PA11
PA12
PA14
PA7
PA1
PB3
PA13
B
B
B
B
B
B
B
Peripheral
A
A
A
B
A
B
B
35.6.2 Power Management
The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the SPI clock.
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35.6.3 Interrupt
The SPI interface has an interrupt line connected to the Interrupt Controller. Handling the SPI interrupt requires programming the interrupt controller before configuring the SPI.
Table 35-3. Peripheral IDs
Instance
SPI0
SPI1
ID
13
14
35.6.4 Direct Memory Access Controller (DMAC)
The SPI interface can be used in conjunction with the DMAC in order to reduce processor overhead. For a full description of the DMAC, refer to the corresponding section in the full datasheet.
35.7 Functional Description
35.7.1 Modes of Operation
The SPI operates in Master Mode or in Slave Mode.
Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter.
If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the
MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The
NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes.
The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode.
35.7.2 Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave.
shows the four modes and corresponding parameter settings.
Table 35-4. SPI Bus Protocol Mode
SPI Mode
0
CPOL
0
1
2
3
0
1
1
NCPHA
1
0
1
0
Shift SPCK Edge
Falling
Rising
Rising
Falling
Capture SPCK Edge
Rising
Falling
Falling
Rising
SPCK Inactive Level
Low
Low
High
High
show examples of data transfers.
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Figure 35-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
1 2 3 4 SPCK cycle (for reference)
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
MSB 6
MSB 6
5
5
4
4
5
3
3
2
7
1 LSB
2 1
NSS
(to slave)
* Not defined, but normally MSB of previous character received.
Figure 35-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
1 2 3 4
SPCK cycle (for reference)
SPCK
(CPOL = 0)
5 6 7
8
LSB
8
*
SPCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
NSS
(to slave)
MSB 6
*
MSB 6
5
5
4
4
3
3
* Not defined but normally LSB of previous character transmitted.
2
2 1
1 LSB
LSB
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35.7.3 Master Mode Operations
When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK).
The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift
Register. The holding registers maintain the data flow at a constant rate.
After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift
Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Receiving data cannot occur without transmitting data. If receiving mode is not needed, for example when communicating with a slave receiver only (such as an LCD), the receive status flags in the status register can be discarded.
Before writing the TDR, the PCS field in the SPI_MR register must be set in order to select a slave.
After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift
Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception.
Before writing the TDR, the PCS field must be set in order to select a slave.
If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts.
The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data Register
Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit DMAchannel.
The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is greater than
0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time.
The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register
Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared.
If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit.
, shows a block diagram of the SPI when operating in Master Mode.
Figure 35-6 on page 637 shows a flow
chart describing how transfers are handled.
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35.7.3.1 Master Mode Block Diagram
Figure 35-5. Master Mode Block Diagram
SPI_CSR0..3
SCBR
MCK
Baud Rate Generator
MISO
SPI
Clock
SPI_CSR0..3
BITS
NCPHA
CPOL
LSB
SPI_RDR
Shift Register
RD
MSB
RDRF
OVRES
SPI_MR
PCS
PS
0
SPI_CSR0..3
SPI_TDR
TD
CSAAT
TDRE
SPI_RDR
PCS
PCSDEC
Current
Peripheral
SPI_TDR
PCS
1
SPCK
MOSI
NPCS3
NPCS2
NPCS1
NPCS0
MSTR
MODF
NPCS0
MODFDIS
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35.7.3.2 Master Mode Flow Diagram
Figure 35-6. Master Mode Flow Diagram
SPI Enable
- NPCS defines the current Chip Select
- CSAAT, DLYBS, DLYBCT refer to the fields of the
Chip Select Register corresponding to the Current Chip Select
- When NPCS is 0xF, CSAAT is 0.
1
TDRE ?
0
1
CSAAT ?
0
PS ?
1
Variable peripheral
NPCS = SPI_TDR(PCS)
0
Fixed
peripheral
NPCS = SPI_MR(PCS)
PS ?
1
Variable peripheral
0
Fixed
peripheral yes
SPI_TDR(PCS)
= NPCS ?
no
NPCS = 0xF
SPI_MR(PCS)
= NPCS ?
no
NPCS = 0xF
Delay DLYBCS
NPCS = SPI_TDR(PCS)
Delay DLYBCS
NPCS = SPI_MR(PCS),
SPI_TDR(PCS)
Delay DLYBS
Serializer = SPI_TDR(TD)
TDRE = 1
Data Transfer
SPI_RDR(RD) = Serializer
RDRF = 1
Delay DLYBCT
1
TDRE ?
1
CSAAT ?
0
NPCS = 0xF
Delay DLYBCS
0
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shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register
Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved.
Figure 35-7. Status Register Flags Behavior
1 2
SPCK
3 4 5 7 8
NPCS0
MOSI
(from master)
TDRE
MSB 6 5 4 3 2 1 LSB
RDR read
Write in
SPI_TDR
RDRF
MISO
(from slave)
TXEMPTY
MSB 6 5 4 3 2 1 LSB shift register empty
35.7.3.3 Clock Generation
The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255.
This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by
255.
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip
Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming.
35.7.3.4 Transfer Delays
programmed to modify the transfer waveforms:
The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the
Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one.
The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted.
The delay between consecutive transfers, independently programmable for each chip select by writing the
DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
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Figure 35-8. Programmable Delays
Chip Select 1
Chip Select 2
SPCK
DLYBCS DLYBS DLYBCT DLYBCT
35.7.3.5 Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer.
Fixed Peripheral Select: SPI exchanges data with only one peripheral
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect.
Variable Peripheral Select: Data can be exchanged with more than one peripheral without having to reprogram the
NPCS field in the SPI_MR register.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The value to write in the SPI_TDR register as the following format.
[xxxxxxx(7-bit) + LASTXFER(1-bit)
(1) + xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals to the chip select
to assert as defined in Section 35.8.4
(SPI Transmit Data Register) and LASTXFER bit at 0 or 1 depending on CSAAT bit.
Note: 1. Optional.
CSAAT, LASTXFER bits are discussed in
Section 35.7.3.9 ”Peripheral Deselection with DMAC” .
If LASTXFER is used, the command must be issued before writing the last character. Instead of LASTXFER, the user can use the SPIDIS command. After the end of the DMA transfer, wait for the TXEMPTY flag, then write SPIDIS into the
SPI_CR register (this will not change the configuration register values); the NPCS will be deactivated after the last character transfer. Then, another DMA transfer can be started if the SPIEN was previously written in the SPI_CR register.
35.7.3.6 SPI Direct Access Memory Controller (DMAC)
In both fixed and variable mode the Direct Memory Access Controller (DMAC) can be used to reduce processor overhead.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the DMAC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode
Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the DMAC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and
LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor.
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35.7.3.7 Peripheral Chip Select Decoding
The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to
NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writing the PCSDEC bit at 1 in the Mode
Register (SPI_MR).
When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one
NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field on NPCS lines of either the
Mode Register or the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
below shows such an implementation.
If the CSAAT bit is used, with or without the DMAC, the Mode Fault detection for NPCS0 line must be disabled. This is not needed for all other chip select lines since Mode Fault Detection is only on NPCS0.
Figure 35-9. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation
SPCK
MISO
MOSI
SPI Master
SPCK MISO MOSI
Slave 0
NSS
SPCK MISO MOSI
Slave 1
NSS
SPCK MISO MOSI
Slave 14
NSS
NPCS0
NPCS1
NPCS2
NPCS3
1-of-n Decoder/Demultiplexer
35.7.3.8 Peripheral Deselection without DMA
During a transfer of more than one data on a Chip Select without the DMA, the SPI_TDR is loaded by the processor, the flag TDRE rises as soon as the content of the SPI_TDR is transferred into the internal shift register. When this flag is detected high, the SPI_TDR can be reloaded. If this reload by the processor occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted between the two transfers. But depending on the application software handling the SPI status register flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor may not reload the SPI_TDR in time to keep the chip select active (low). A null Delay Between Consecutive Transfer (DLYBCT) value in the SPI_CSR register, will give even less time for the processor to reload the SPI_TDR. With some SPI slave peripherals, requiring the chip select line to remain active (low) during a full set of transfers might lead to communication errors.
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To facilitate interfacing with such devices, the Chip Select Register [CSR0...CSR3] can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another chip select is required. Even if the SPI_TDR is not reloaded the chip select will remain active. To have the chip select line to raise at the end of the transfer the Last transfer Bit (LASTXFER) in the SPI_MR register must be set at 1 before writing the last data to transmit into the SPI_TDR.
35.7.3.9 Peripheral Deselection with DMAC
When the Direct Memory Access Controller is used, the chip select line will remain low during the whole transfer since the TDRE flag is managed by the DMAC itself. The reloading of the SPI_TDR by the DMAC is done as soon as TDRE flag is set to one. In this case the use of CSAAT bit might not be needed. However, it may happen that when other DMAC channels connected to other peripherals are in use as well, the SPI DMAC might be delayed by another (DMAC with a higher priority on the bus). Having DMAC buffers in slower memories like flash memory or SDRAM compared to fast internal SRAM, may lengthen the reload time of the SPI_TDR by the DMAC as well. This means that the SPI_TDR might not be reloaded in time to keep the chip select line low. In this case the chip select line may toggle between data transfer and according to some SPI Slave devices, the communication might get lost. The use of the CSAAT bit might be needed.
Figure 35-10 shows different peripheral deselection cases and the effect of the CSAAT bit.
Figure 35-10. Peripheral Deselection
CSAAT = 0 CSAAT = 1
TDRE
NPCS[0..3] A
DLYBCT
A
DLYBCT
DLYBCS
PCS = A
A A
DLYBCS
PCS = A
A
Write SPI_TDR
TDRE
NPCS[0..3] A
DLYBCT
DLYBCS
PCS=A
A
Write SPI_TDR
TDRE
NPCS[0..3] A
DLYBCT
DLYBCS
PCS = B
Write SPI_TDR
B
A
DLYBCT
A
DLYBCS
PCS = A
A
A
DLYBCT
PCS = B
DLYBCS
B
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35.7.3.10 Mode Fault Detection
A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. In this case, multi-master configuration, NPCS0, MOSI, MISO and SPCK pins must be configured in open drain (through the PIO controller). When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR
(Control Register) at 1.
By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the
MODFDIS bit in the SPI Mode Register (SPI_MR).
35.7.4 SPI Slave Mode
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0
(SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
.)
When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in
SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the
OVRES bit.
When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the
Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0.
When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin.
When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises.
This enables frequent updates of critical variables with single transfers.
Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the
Shift Register is not modified and the last received character is retransmitted.
Figure 35-11 shows a block diagram of the SPI when operating in Slave Mode.
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Figure 35-11. Slave Mode Functional Bloc Diagram
SPCK
NSS
SPIEN
SPIENS
SPIDIS
SPI_CSR0
BITS
NCPHA
CPOL
LSB
MOSI
SPI
Clock
SPI_RDR
RD
Shift Register
MSB
RDRF
OVRES
MISO
SPI_TDR
TD TDRE
35.7.5 Write Protected Registers
To prevent any single software error that may corrupt SPI behavior, the registers listed below can be write-protected by setting the WPEN bit in the SPI Write Protection Mode Register (SPI_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the SPI Write Protection Status Register
(SPI_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset after reading the SPI Write Protection Status Register (SPI_WPSR).
List of the write-protected registers:
Section 35.8.2 ”SPI Mode Register”
Section 35.8.9 ”SPI Chip Select Register”
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35.8 Serial Peripheral Interface (SPI) User Interface
Table 35-5. Register Mapping
Offset
0x00 Control Register
0x04
0x08
0x0C
0x10
Mode Register
Receive Data Register
Transmit Data Register
Status Register
0x14
0x18
0x1C
0x20 - 0x2C
0x30
0x34
0x38
0x3C
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Reserved
Chip Select Register 0
Chip Select Register 1
Chip Select Register 2
Chip Select Register 3
0x4C - 0xE0
0xE4
Reserved
Write Protection Control Register
0xE8 Write Protection Status Register
0x00E8 - 0x00F8 Reserved
0x00FC Reserved
SPI_CR
SPI_MR
SPI_RDR
SPI_TDR
SPI_SR
SPI_IER
SPI_IDR
SPI_IMR
SPI_CSR0
SPI_CSR1
SPI_CSR2
SPI_CSR3
–
SPI_WPMR
SPI_WPSR
–
–
Write-only
Read-write
Read-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-write
Read-write
Read-write
Read-write
–
Read-write
Read-only
–
–
Reset
---
0x0
0x0
---
0x000000F0
---
---
0x0
–
0x0
0x0
–
–
0x0
0x0
0x0
0x0
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35.8.1 SPI Control Register
Name: SPI_CR
Address:
Access:
0xF0000000 (0), 0xF0004000 (1)
Write-only
31
–
30
–
29
–
23
–
15
–
7
SWRST
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
• SPIEN: SPI Enable
0 = No effect.
1 = Enables the SPI to transfer and receive data.
• SPIDIS: SPI Disable
0 = No effect.
1 = Disables the SPI.
As soon as SPIDIS is set, SPI finishes its transfer.
All pins are set in input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the SPI is disabled.
If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.
25
–
17
–
9
–
1
SPIDIS
24
LASTXFER
16
–
8
–
0
SPIEN
• SWRST: SPI Software Reset
0 = No effect.
1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.
The SPI is in slave mode after software reset.
• LASTXFER: Last Transfer
0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.
Refer to
Section 35.7.3.5 ”Peripheral Selection”
for more details.
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35.8.2 SPI Mode Register
Name: SPI_MR
Address:
Access:
0xF0000004 (0), 0xF0004004 (1)
Read-write
31 30 29
23
–
15
–
7
LLB
22
–
14
–
6
–
21
–
13
–
5
WDRBT
28
DLYBCS
20
–
12
–
4
MODFDIS
27
19
11
–
3
–
26
18
10
–
2
PCSDEC
PCS
This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”
.
25
17
9
–
1
PS
24
16
8
–
0
MSTR
• MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
• PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
• MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
• WDRBT: Wait Data Read Before Transfer
0 = No Effect. In master mode, a transfer can be initiated whatever the state of the Receive Data Register is.
1 = In Master Mode, a transfer can start only if the Receive Data Register is empty, i.e. does not contain any unread data. This mode prevents overrun error in reception.
• LLB: Local Loopback Enable
0 = Local loopback path disabled.
1 = Local loopback path enabled.
LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.)
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• PCS: Peripheral Chip Select
This field is only used if Fixed Peripheral Select is active (PS = 0).
If PCSDEC = 0:
PCS = xxx0
PCS = xx01
PCS = x011
NPCS[3:0] = 1110
NPCS[3:0] = 1101
NPCS[3:0] = 1011
PCS = 0111
PCS = 1111
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS.
NPCS[3:0] = 0111 forbidden (no peripheral is selected)
• DLYBCS: Delay Between Chip Selects
This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is less than or equal to six, six MCK periods will be inserted by default.
Otherwise, the following equation determines the delay:
Delay Between Chip Selects =
MCK
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35.8.3 SPI Receive Data Register
Name: SPI_RDR
Address:
Access:
0xF0000008 (0), 0xF0004008 (1)
Read-only
31
–
30
–
29
–
23
–
15
22
–
14
21
–
13
28
–
20
–
12
27
–
19
11
26
–
18
10
PCS
RD
7 6 5 4 3 2
RD
• RD: Receive Data
Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
25
–
17
9
1
24
–
16
8
0
• PCS: Peripheral Chip Select
In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero.
Note: When using variable peripheral select mode (PS = 1 in SPI_MR) it is mandatory to also set the WDRBT field to 1 if the
SPI_RDR PCS field is to be processed.
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35.8.4 SPI Transmit Data Register
Name: SPI_TDR
Address:
Access:
0xF000000C (0), 0xF000400C (1)
Write-only
31
–
30
–
29
–
23
–
15
22
–
14
21
–
13
28
–
20
–
12
27
–
19
11
26
–
18
10
PCS
25
–
17
9
24
LASTXFER
16
8
TD
7 6 5 4 3 2 1 0
TD
• TD: Transmit Data
Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
• PCS: Peripheral Chip Select
This field is only used if Variable Peripheral Select is active (PS = 1).
If PCSDEC = 0:
PCS = xxx0
PCS = xx01
PCS = x011
PCS = 0111
PCS = 1111
(x = don’t care)
NPCS[3:0] = 1110
NPCS[3:0] = 1101
NPCS[3:0] = 1011
NPCS[3:0] = 0111 forbidden (no peripheral is selected)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS
• LASTXFER: Last Transfer
0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.
This field is only used if Variable Peripheral Select is active (PS = 1).
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35.8.5 SPI Status Register
Name: SPI_SR
Address:
Access:
0xF0000010 (0), 0xF0004010 (1)
Read-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
OVRES
26
–
18
–
10
–
2
MODF
25
–
17
–
9
TXEMPTY
1
TDRE
24
–
16
SPIENS
8
NSSR
0
RDRF
• RDRF: Receive Data Register Full
0 = No data has been received since the last read of SPI_RDR
1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of
SPI_RDR.
• TDRE: Transmit Data Register Empty
0 = Data has been written to SPI_TDR and not yet transferred to the serializer.
1 = The last data written in the Transmit Data Register has been transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• MODF: Mode Fault Error
0 = No Mode Fault has been detected since the last read of SPI_SR.
1 = A Mode Fault occurred since the last read of the SPI_SR.
• OVRES: Overrun Error Status
0 = No overrun has been detected since the last read of SPI_SR.
1 = An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
• NSSR: NSS Rising
0 = No rising edge detected on NSS pin since last read.
1 = A rising edge occurred on NSS pin since last read.
• TXEMPTY: Transmission Registers Empty
0 = As soon as data is written in SPI_TDR.
1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.
• SPIENS: SPI Enable Status
0 = SPI is disabled.
1 = SPI is enabled.
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35.8.6 SPI Interrupt Enable Register
Name: SPI_IER
Address:
Access:
0xF0000014 (0), 0xF0004014 (1)
Write-only
31
–
30
–
29
–
23
–
15
–
7
TXBUFE
22
–
14
–
6
–
21
–
13
–
5
–
0 = No effect.
1 = Enables the corresponding interrupt.
28
–
20
–
12
–
4
–
• RDRF: Receive Data Register Full Interrupt Enable
• TDRE: SPI Transmit Data Register Empty Interrupt Enable
• MODF: Mode Fault Error Interrupt Enable
• OVRES: Overrun Error Interrupt Enable
• NSSR: NSS Rising Interrupt Enable
• TXEMPTY: Transmission Registers Empty Enable
27
–
19
–
11
–
3
OVRES
26
–
18
–
10
–
2
MODF
25
–
17
–
9
TXEMPTY
1
TDRE
24
–
16
–
8
NSSR
0
RDRF
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35.8.7 SPI Interrupt Disable Register
Name: SPI_IDR
Address:
Access:
0xF0000018 (0), 0xF0004018 (1)
Write-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
0 = No effect.
1 = Disables the corresponding interrupt.
28
–
20
–
12
–
4
–
• RDRF: Receive Data Register Full Interrupt Disable
• TDRE: SPI Transmit Data Register Empty Interrupt Disable
• MODF: Mode Fault Error Interrupt Disable
• OVRES: Overrun Error Interrupt Disable
• NSSR: NSS Rising Interrupt Disable
• TXEMPTY: Transmission Registers Empty Disable
27
–
19
–
11
–
3
OVRES
26
–
18
–
10
–
2
MODF
25
–
17
–
9
TXEMPTY
1
TDRE
24
–
16
–
8
NSSR
0
RDRF
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35.8.8 SPI Interrupt Mask Register
Name: SPI_IMR
Address:
Access:
0xF000001C (0), 0xF000401C (1)
Read-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.
28
–
20
–
12
–
4
–
• RDRF: Receive Data Register Full Interrupt Mask
• TDRE: SPI Transmit Data Register Empty Interrupt Mask
• MODF: Mode Fault Error Interrupt Mask
• OVRES: Overrun Error Interrupt Mask
• NSSR: NSS Rising Interrupt Mask
• TXEMPTY: Transmission Registers Empty Mask
27
–
19
–
11
–
3
OVRES
26
–
18
–
10
–
2
MODF
25
–
17
–
9
TXEMPTY
1
TDRE
24
–
16
–
8
NSSR
0
RDRF
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35.8.9 SPI Chip Select Register
Name: SPI_CSRx[x=0..3]
Address:
Access:
0xF0000030 (0), 0xF0004030 (1)
Read/Write
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
7 6
BITS
5 4 3
CSAAT
2
–
1
NCPHA
0
CPOL
This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”
.
Note: SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the translated value unless the register is written.
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.
• CSAAT: Chip Select Active After Transfer
0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select.
• BITS: Bits Per Transfer
(See the
(Note:) below the register table, Section 35.8.9 “SPI Chip Select Register” on page 654
.)
The BITS field determines the number of data bits transferred. Reserved values should not be used.
Value
0
1
4
5
2
3
6
7
Name
8_BIT
9_BIT
10_BIT
11_BIT
12_BIT
13_BIT
14_BIT
15_BIT
Description
8 bits for transfer
9 bits for transfer
10 bits for transfer
11 bits for transfer
12 bits for transfer
13 bits for transfer
14 bits for transfer
15 bits for transfer
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Value
8
9
10
11
12
13
14
15
–
–
–
–
–
Name
16_BIT
–
–
Description
16 bits for transfer
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:
SPCK Baudrate =
MCK
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
Note: If one of the SCBR fields inSPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as well, if they are required to process transfers. If they are not used to transfer data, they can be set at any value.
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
Delay Before SPCK =
MCK
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers.
Otherwise, the following equation determines the delay:
Delay Between Consecutive Transfers =
32
× DLYBCT
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35.8.10 SPI Write Protection Mode Register
Name:
Address:
Access:
SPI_WPMR
0xF00000E4 (0), 0xF00040E4 (1)
Read-write
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
WPEN
• WPEN: Write Protection Enable
0: The Write Protection is Disabled
1: The Write Protection is Enabled
• WPKEY: Write Protection Key Password
If a value is written in WPEN, the value is taken into account only if WPKEY is written with “SPI” (SPI written in ASCII Code, ie
0x535049 in hexadecimal).
List of the write-protected registers:
Section 35.8.2 ”SPI Mode Register”
Section 35.8.9 ”SPI Chip Select Register”
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35.8.11 SPI Write Protection Status Register
Name:
Address:
Access:
SPI_WPSR
0xF00000E8 (0), 0xF00040E8 (1)
Read-only
31
–
23
–
15
7
–
30
–
22
–
14
6
–
29
–
21
–
13
5
–
28
–
20
–
12
WPVSRC
27
–
19
–
11
4
–
3
–
26
–
18
–
10
2
–
25
–
17
–
9
1
–
24
–
16
–
8
0
WPVS
• WPVS: Write Protection Violation Status
0 = No Write Protect Violation has occurred since the last read of the SPI_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the SPI_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
This Field indicates the APB Offset of the register concerned by the violation (SPI_MR or SPI_CSRx)
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36.
Timer Counter (TC)
36.1 Description
The Timer Counter (TC) includes six identical 32-bit Timer Counter channels.
Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.
Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts.
The Timer Counter block has two global registers which act upon all TC channels.
The Block Control Register allows the channels to be started simultaneously with the same instruction.
The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained.
gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2.
Table 36-1. Timer Counter Clock Assignment
Name
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
Definition
MCK/2
MCK/8
MCK/32
MCK/128
SLCK
Note: 1. When Slow Clock is selected for Master Clock (CSS = 0 in PMC Master Clock Register), TIMER_CLOCK5 input is equivalent to Master Clock.
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36.2 Embedded Characteristics
Provides six 32-bit Timer Counter channels
Wide range of functions including:
Frequency measurement
Event counting
Interval measurement
Pulse generation
Delay timing
Pulse Width Modulation
Up/down capabilities
Each channel is user-configurable and contains:
Three external clock inputs
Five Internal clock inputs
Two multi-purpose input/output signals acting as trigger event
Internal interrupt signal
Two global registers that act on all TC channels
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36.3 Block Diagram
Figure 36-1. Timer Counter Block Diagram
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
TCLK0
TCLK1
TCLK2
TIOA1
TIOA2
TCLK0
TCLK1
TIOA0
TIOA2
TCLK2
TCLK0
TCLK1
TCLK2
TIOA0
TIOA1
XC0
XC1
XC2
TC0XC0S
Timer/Counter
Channel 0
TIOA
TIOB
TIOA0
TIOB0
SYNC
INT0
XC0
XC1
XC2
TC1XC1S
Timer/Counter
Channel 1
TIOA
TIOB
SYNC
INT1
TIOA1
TIOB1
XC0
XC1
XC2
TC2XC2S
Timer/Counter
Channel 2
TIOA
TIOB
TIOA2
TIOB2
SYNC
INT2
Timer Counter
Interrupt
Controller
Parallel I/O
Controller
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Table 36-2. Signal Name Description
Channel Signal
XC0, XC1, XC2
TIOA
TIOB
INT
SYNC
Description
External Clock Inputs
Capture Mode: Timer Counter Input
Waveform Mode: Timer Counter Output
Capture Mode: Timer Counter Input
Waveform Mode: Timer Counter Input/Output
Interrupt Signal Output (internal signal)
Synchronization Input Signal (from configuration register)
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36.4 Pin Name List
Table 36-3. TC pin list
Pin Name
TCLK0-TCLK2
TIOA0-TIOA2
TIOB0-TIOB2
Description
External Clock Input
I/O Line A
I/O Line B
Type
Input
I/O
I/O
36.5 Product Dependencies
36.5.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions.
Table 36-4. I/O Lines
Instance
TC0
TC0
TC0
TC0
TC0
TC0
TC1
TC1
TC1
TC1
TC0
TC0
TC0
TC1
TC1
TC1
TC1
TC1
TIOB0
TIOB1
TIOB2
TCLK3
TCLK4
TCLK5
TIOA3
TIOA4
Signal
TCLK0
TCLK1
TCLK2
TIOA0
TIOA1
TIOA2
TIOA5
TIOB3
TIOB4
TIOB5
PA27
PA28
PA29
PC4
PC7
PC14
PC2
PC5
I/O Line
PA24
PA25
PA26
PA21
PA22
PA23
PC12
PC3
PC6
PC13
C
C
C
C
A
C
A
A
Peripheral
A
A
A
A
A
A
C
C
C
C
36.5.2 Power Management
The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock.
36.5.3 Interrupt
The TC has an interrupt line connected to the Interrupt Controller (IC). Handling the TC interrupt requires programming the IC before configuring the TC.
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36.6 Functional Description
36.6.1 TC Description
The six channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in
36.6.2 32-bit Counter
Each channel is organized around a 32-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the
COVFS bit in TC_SR (Status Register) is set.
The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock.
36.6.3 Clock Selection
At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or
TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR
(Block Mode). See Figure 36-2 ”Clock Chaining Selection”
.
Each channel can independently select an internal or external clock source for its counter:
Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5
External clock signals: XC0, XC1 or XC2
This selection is made by the TCCLKS bits in the TC Channel Mode Register.
The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock.
The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode
Register defines this signal (none, XC0, XC1, XC2). See Figure 36-3 ”Clock Selection”
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock
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Figure 36-2. Clock Chaining Selection
TCLK0
TIOA1
TIOA2
TC0XC0 S
TCLK1
TIOA0
TIOA2
TC1XC1 S
TCLK2
TIOA0
TIOA1
TC2XC2 S
Timer/Co u nter
Ch a nnel 0
TIOA0 XC0
XC1 = TCLK1
XC2 = TCLK2 TIOB0
S YNC
Timer/Co u nter
Ch a nnel 1
XC0 = TCLK0 TIOA1
XC1
XC2 = TCLK2 TIOB1
S YNC
Timer/Co u nter
Ch a nnel 2
TIOA2 XC0 = TCLK0
XC1 = TCLK1
XC2 TIOB2
S YNC
Figure 36-3. Clock Selection
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
TCCLKS
BURST
1
Synchronous
Edge Detection
CLKI
MCK
Selected
Clock
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36.6.4 Clock Control
The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See
The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control
Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform
Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register.
The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled.
Figure 36-4. Clock Control
Selected
Clock
Trigger
CLKSTA CLKEN CLKDIS
Q S
R
Q S
R
Stop
Event
Disable
Event
Counter
Clock
36.6.5 TC Operating Modes
Each channel can independently operate in two different modes:
Capture Mode provides measurement on signals.
Waveform Mode provides wave generation.
The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register.
In Capture Mode, TIOA and TIOB are configured as inputs.
In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger.
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36.6.6 Trigger
A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode.
Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock.
The following triggers are common to both modes:
Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR.
SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.
Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR.
The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR.
If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected.
36.6.7 Capture Operating Mode
This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register).
Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs.
Figure 36-5 shows the configuration of the TC channel when programmed in Capture Mode.
36.6.8 Capture Registers A and B
Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA.
The LDRA parameter in TC_CMR defines the TIOA selected edge for the loading of register A, and the LDRB parameter defines the TIOA selected edge for the loading of Register B.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status
Register). In this case, the old value is overwritten.
36.6.9 Trigger Conditions
In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined.
The ABETRG bit in the TC_CMR register selects TIOA or TIOB input signal as an external trigger . The ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled.
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Figure 36-5. Capture Mode
CPCS
LOVRS
COVFS
LDRBS
LDRAS
ETRGS
TC1_SR TC1_IMR
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36.6.10 Waveform Operating Mode
Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register).
In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses.
In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event
(EEVT parameter in TC_CMR).
Figure 36-6 shows the configuration of the TC channel when programmed in Waveform Operating Mode.
36.6.11 Waveform Selection
Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies.
With any selection, RA, RB and RC can all be used as compare registers.
RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs.
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Figure 36-6. Waveform Mode
Output Controller Output Controller
CPCS
CPBS
CPAS
COVFS
ETRGS
TC1_SR TC1_IMR
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36.6.11.1 WAVSEL = 00
When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value
of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 36-7
.
An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See
.
RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR).
Figure 36-7. WAVSEL= 00 without trigger
Counter Value
0xFFFF
Counter cleared by compare match with 0xFFFF
R
C
R
B
R
A
Time
Waveform Examples
TIOB
TIOA
Figure 36-8. WAVSEL= 00 with trigger
Counter Value
0xFFFF
R
C
R
B
R
A
Counter cleared by compare match with 0xFFFF
Counter cleared by trigger
Time
Waveform Examples
TIOB
TIOA
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36.6.11.2 WAVSEL = 10
When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC
Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See
It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See
.
In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock
(CPCDIS = 1 in TC_CMR).
Figure 36-9. WAVSEL = 10 Without Trigger
Counter Value
0xFFFF
Counter cleared by compare match with RC
R
C
R
B
R
A
Time
Waveform Examples
TIOB
TIOA
Figure 36-10.WAVSEL = 10 With Trigger
Counter Value
0xFFFF
Counter cleared by compare match with RC
R
C
Counter cleared by trigger
R
B
R
A
Time
Waveform Examples
TIOB
TIOA
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36.6.11.3 WAVSEL = 01
When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of
TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 36-11
.
A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments.
RC Compare cannot be programmed to generate a trigger in this configuration.
At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1).
Figure 36-11.WAVSEL = 01 Without Trigger
Counter Value Counter decremented by compare match with 0xFFFF
0xFFFF
R
C
R
B
R
A
Time
Waveform Examples
TIOB
TIOA
Figure 36-12.WAVSEL = 01 With Trigger
Counter Value
0xFFFF
Counter decremented by compare match with 0xFFFF
Counter decremented by trigger
R
C
R
B
Counter incremented by trigger
R
A
Time
Waveform Examples
TIOB
TIOA
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36.6.11.4 WAVSEL = 11
When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is
decremented to 0, then re-incremented to RC and so on. See Figure 36-13 .
A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments.
RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1).
Figure 36-13.WAVSEL = 11 Without Trigger
Counter Value
0xFFFF
Counter decremented by compare match with RC
R
C
R
B
R
A
Time
Waveform Examples
TIOB
TIOA
Figure 36-14.WAVSEL = 11 With Trigger
Counter Value
0xFFFF
Counter decremented by compare match with RC
R
C
R
B
Counter decremented by trigger
Counter incremented by trigger
R
A
Waveform Examples
TIOB
Time
TIOA
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36.6.12 External Event/Trigger Conditions
An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger.
The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register
B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA.
When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR.
As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL.
36.6.13 Output Controller
The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if
TIOB is defined as output (not as an external event).
The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls
TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR.
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36.7 Timer Counter (TC) User Interface
Table 36-5. Register Mapping
Offset
0x00 + channel * 0x40 + 0x00
0x00 + channel * 0x40 + 0x04
0x00 + channel * 0x40 + 0x08
0x00 + channel * 0x40 + 0x0C
0x00 + channel * 0x40 + 0x10
0x00 + channel * 0x40 + 0x14
0x00 + channel * 0x40 + 0x18
0x00 + channel * 0x40 + 0x1C
0x00 + channel * 0x40 + 0x20
0x00 + channel * 0x40 + 0x24
0x00 + channel * 0x40 + 0x28
0x00 + channel * 0x40 + 0x2C
0xC0
0xC4
0xC8 - 0xD4
0xD8
0xE4
0xE8 - 0xFC Reserved
Notes: 1. Channel index ranges from 0 to 2.
2. Read-only if WAVE = 0
Register
Channel Control Register
Channel Mode Register
Reserved
Reserved
Counter Value
Register A
Register B
Register C
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Block Control Register
Block Mode Register
Reserved
Reserved
Reserved
Name
TC_CCR
TC_CMR
Access
Write-only
Read-write
TC_CV
TC_RA
TC_RB
TC_RC
TC_SR
TC_IER
TC_IDR
TC_IMR
TC_BCR
TC_BMR
Read-only
Read-write
Read-only
Write-only
Write-only
Read-only
Write-only
Read-write
Reset
–
0
–
–
0
0
0
0
0
0
–
0
– – –
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36.7.1 TC Channel Control Register
Name:
Address:
Access:
TC_CCRx [x=0..2]
0xF8008000 (0)[0], 0xF8008040 (0)[1], 0xF8008080 (0)[2], 0xF800C000 (1)[0], 0xF800C040 (1)[1],
0xF800C080 (1)[2]
Write-only
15
–
7
–
31
–
23
–
14
–
6
–
30
–
22
–
13
–
5
–
29
–
21
–
12
–
4
–
28
–
20
–
11
–
3
–
27
–
19
–
26
–
18
–
10
–
2
SWTRG
25
–
17
–
9
–
1
CLKDIS
24
–
16
–
8
–
0
CLKEN
• CLKEN: Counter Clock Enable Command
0 = No effect.
1 = Enables the clock if CLKDIS is not 1.
• CLKDIS: Counter Clock Disable Command
0 = No effect.
1 = Disables the clock.
• SWTRG: Software Trigger Command
0 = No effect.
1 = A software trigger is performed: the counter is reset and the clock is started.
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36.7.2 TC Channel Mode Register: Capture Mode
Name:
Address:
Access:
TC_CMRx [x=0..2] (WAVE = 0)
0xF8008004 (0)[0], 0xF8008044 (0)[1], 0xF8008084 (0)[2], 0xF800C004 (1)[0], 0xF800C044 (1)[1],
0xF800C084 (1)[2]
Read-write
31
–
23
–
15
WAVE
7
LDBDIS
30
–
22
–
14
CPCTRG
6
LDBSTOP
13
–
5
29
–
21
–
BURST
12
–
4
28
–
20
–
27
–
19
11
–
3
CLKI
LDRB
26
–
18
10
ABETRG
2
25
–
17
LDRA
9
ETRGEDG
1
TCCLKS
24
–
16
8
0
• TCCLKS: Clock Selection
Value
0
1
4
5
2
3
6
7
Name
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
Description
Clock selected: TCLK1
Clock selected: TCLK2
Clock selected: TCLK3
Clock selected: TCLK4
Clock selected: TCLK5
Clock selected: XC0
Clock selected: XC1
Clock selected: XC2
• CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
Value
0
1
2
3
Name
NONE
XC0
XC1
XC2
Description
The clock is not gated by an external signal.
XC0 is ANDed with the selected clock.
XC1 is ANDed with the selected clock.
XC2 is ANDed with the selected clock.
• LDBSTOP: Counter Clock Stopped with RB Loading
0 = Counter clock is not stopped when RB loading occurs.
1 = Counter clock is stopped when RB loading occurs.
• LDBDIS: Counter Clock Disable with RB Loading
0 = Counter clock is not disabled when RB loading occurs.
1 = Counter clock is disabled when RB loading occurs.
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• ETRGEDG: External Trigger Edge Selection
Value
0
1
2
3
Name
NONE
RISING
FALLING
EDGE
Description
The clock is not gated by an external signal.
Rising edge
Falling edge
Each edge
• ABETRG: TIOA or TIOB External Trigger Selection
0 = TIOB is used as an external trigger.
1 = TIOA is used as an external trigger.
• CPCTRG: RC Compare Trigger Enable
0 = RC Compare has no effect on the counter and its clock.
1 = RC Compare resets the counter and starts the counter clock.
• WAVE: Waveform Mode
0 = Capture Mode is enabled.
1 = Capture Mode is disabled (Waveform Mode is enabled).
• LDRA: RA Loading Edge Selection
Value
0
1
2
3
Name
NONE
RISING
FALLING
EDGE
• LDRB: RB Loading Edge Selection
Description
None
Rising edge of TIOA
Falling edge of TIOA
Each edge of TIOA
Value
0
1
2
3
Name
NONE
RISING
FALLING
EDGE
Description
None
Rising edge of TIOA
Falling edge of TIOA
Each edge of TIOA
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36.7.3 TC Channel Mode Register: Waveform Mode
Name:
Access:
TC_CMRx [x=0..2] (WAVE = 1)
Read-write
29 31 30
BSWTRG
23 22
15
WAVE
7
CPCDIS
ASWTRG
14
6
CPCSTOP
WAVSEL
21
13
5
28
BEEVT
20
AEEVT
BURST
12
ENETRG
4
• TCCLKS: Clock Selection
5
6
3
4
7
Value
0
1
2
Name
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
Description
Clock selected: TCLK1
Clock selected: TCLK2
Clock selected: TCLK3
Clock selected: TCLK4
Clock selected: TCLK5
Clock selected: XC0
Clock selected: XC1
Clock selected: XC2
• CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
27
19
11
3
CLKI
Value
0
1
2
3
Name
NONE
XC0
XC1
XC2
Description
The clock is not gated by an external signal.
XC0 is ANDed with the selected clock.
XC1 is ANDed with the selected clock.
XC2 is ANDed with the selected clock.
• CPCSTOP: Counter Clock Stopped with RC Compare
0 = Counter clock is not stopped when counter reaches RC.
1 = Counter clock is stopped when counter reaches RC.
• CPCDIS: Counter Clock Disable with RC Compare
0 = Counter clock is not disabled when counter reaches RC.
1 = Counter clock is disabled when counter reaches RC.
BCPC
ACPC
EEVT
26
18
10
2
25 24
BCPB
17
ACPA
9
1
TCCLKS
EEVTEDG
16
8
0
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• EEVTEDG: External Event Edge Selection
Value
0
1
2
3
Name
NONE
RISING
FALLING
EDGE
• EEVT: External Event Selection
Signal selected as external event.
Description
None
Rising edge
Falling edge
Each edge
Value
0
1
2
3
Name
TIOB
XC0
XC1
XC2
Description
XC0
XC1
XC2
TIOB Direction
Input
Output
Output
Output
Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
• ENETRG: External Event Trigger Enable
0 = the external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output.
1 = the external event resets the counter and starts the counter clock.
• WAVSEL: Waveform Selection
Value
0
1
2
3
Name
UP
UPDOWN
UP_RC
UPDOWN_RC
Description
UP mode without automatic trigger on RC Compare
UPDOWN mode without automatic trigger on RC Compare
UP mode with automatic trigger on RC Compare
UPDOWN mode with automatic trigger on RC Compare
• WAVE: Waveform Mode
0 = Waveform Mode is disabled (Capture Mode is enabled).
1 = Waveform Mode is enabled.
• ACPA: RA Compare Effect on TIOA
Value
0
1
2
3
Name
NONE
SET
CLEAR
TOGGLE
Description
None
Set
Clear
Toggle
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• ACPC: RC Compare Effect on TIOA
Value
0
1
2
3
Name
NONE
SET
CLEAR
TOGGLE
Description
None
Set
Clear
Toggle
• AEEVT: External Event Effect on TIOA
Value
0
1
2
3
Name
NONE
SET
CLEAR
TOGGLE
Description
None
Set
Clear
Toggle
• ASWTRG: Software Trigger Effect on TIOA
Value
0
1
2
3
Name
NONE
SET
CLEAR
TOGGLE
• BCPB: RB Compare Effect on TIOB
Description
None
Set
Clear
Toggle
Value
0
1
2
3
Name
NONE
SET
CLEAR
TOGGLE
• BCPC: RC Compare Effect on TIOB
Description
None
Set
Clear
Toggle
Value
0
1
2
3
Name
NONE
SET
CLEAR
TOGGLE
Description
None
Set
Clear
Toggle
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• BEEVT: External Event Effect on TIOB
Value
0
1
2
3
Name
NONE
SET
CLEAR
TOGGLE
Description
None
Set
Clear
Toggle
• BSWTRG: Software Trigger Effect on TIOB
Value
0
1
2
3
Name
NONE
SET
CLEAR
TOGGLE
Description
None
Set
Clear
Toggle
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36.7.4 TC Counter Value Register
Name:
Address:
Access:
TC_CVx [x=0..2]
0xF8008010 (0)[0], 0xF8008050 (0)[1], 0xF8008090 (0)[2], 0xF800C010 (1)[0], 0xF800C050 (1)[1],
0xF800C090 (1)[2]
Read-only
31 30 29 28 27 26 25
CV
23 22 21 20 19 18 17
CV
15 14 13 12 11 10 9
CV
7 6 5 4 3 2 1
CV
• CV: Counter Value
CV contains the counter value in real time.
24
16
8
0
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36.7.5 TC Register A
Name:
Address:
Access:
TC_RAx [x=0..2]
0xF8008014 (0)[0], 0xF8008054 (0)[1], 0xF8008094 (0)[2], 0xF800C014 (1)[0], 0xF800C054 (1)[1],
0xF800C094 (1)[2]
Read-only if WAVE = 0, Read-write if WAVE = 1
31 30 29 28 27 26 25
RA
23 22 21 20 19 18 17
RA
15 14 13 12 11 10 9
RA
7 6 5 4 3 2 1
RA
• RA: Register A
RA contains the Register A value in real time.
24
16
8
0
36.7.6 TC Register B
Name:
Address:
Access:
TC_RBx [x=0..2]
0xF8008018 (0)[0], 0xF8008058 (0)[1], 0xF8008098 (0)[2], 0xF800C018 (1)[0], 0xF800C058 (1)[1],
0xF800C098 (1)[2]
Read-only if WAVE = 0, Read-write if WAVE = 1
31 30 29 28 27 26 25
RB
23 22 21 20 19 18 17
RB
15 14 13 12 11 10 9
RB
7 6 5 4 3 2 1
RB
• RB: Register B
RB contains the Register B value in real time.
24
16
8
0
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36.7.7 TC Register C
Name:
Address:
Access:
TC_RCx [x=0..2]
0xF800801C (0)[0], 0xF800805C (0)[1], 0xF800809C (0)[2], 0xF800C01C (1)[0], 0xF800C05C (1)[1],
0xF800C09C (1)[2]
Read-write
31 30 29 28 27 26 25
RC
23 22 21 20 19 18 17
RC
15 14 13 12 11 10 9
RC
7 6 5 4 3 2 1
RC
24
16
8
0
• RC: Register C
RC contains the Register C value in real time.
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36.7.8 TC Status Register
Name:
Address:
Access:
TC_SRx [x=0..2]
0xF8008020 (0)[0], 0xF8008060 (0)[1], 0xF80080A0 (0)[2], 0xF800C020 (1)[0], 0xF800C060 (1)[1],
0xF800C0A0 (1)[2]
Read-only
31
–
23
–
15
–
7
ETRGS
30
–
22
–
14
–
6
LDRBS
29
–
21
–
13
–
5
LDRAS
28
–
20
–
12
–
4
CPCS
27
–
19
–
11
–
3
CPBS
26
–
18
MTIOB
10
–
2
CPAS
25
–
17
MTIOA
9
–
1
LOVRS
24
–
16
CLKSTA
8
–
0
COVFS
• COVFS: Counter Overflow Status
0 = No counter overflow has occurred since the last read of the Status Register.
1 = A counter overflow has occurred since the last read of the Status Register.
• LOVRS: Load Overrun Status
0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0.
• CPAS: RA Compare Status
0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.
• CPBS: RB Compare Status
0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.
• CPCS: RC Compare Status
0 = RC Compare has not occurred since the last read of the Status Register.
1 = RC Compare has occurred since the last read of the Status Register.
• LDRAS: RA Loading Status
0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
• LDRBS: RB Loading Status
0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.
• ETRGS: External Trigger Status
0 = External trigger has not occurred since the last read of the Status Register.
1 = External trigger has occurred since the last read of the Status Register.
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• CLKSTA: Clock Enabling Status
0 = Clock is disabled.
1 = Clock is enabled.
• MTIOA: TIOA Mirror
0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.
1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.
• MTIOB: TIOB Mirror
0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.
1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.
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36.7.9 TC Interrupt Enable Register
Name:
Address:
Access:
TC_IERx [x=0..2]
0xF8008024 (0)[0], 0xF8008064 (0)[1], 0xF80080A4 (0)[2], 0xF800C024 (1)[0], 0xF800C064 (1)[1],
0xF800C0A4 (1)[2]
Write-only
31
–
23
–
15
–
7
ETRGS
30
–
22
–
14
–
6
LDRBS
29
–
21
–
13
–
5
LDRAS
28
–
20
–
12
–
4
CPCS
27
–
19
–
11
–
3
CPBS
10
–
2
CPAS
26
–
18
–
25
–
17
–
9
–
1
LOVRS
24
–
16
–
8
–
0
COVFS
• COVFS: Counter Overflow
0 = No effect.
1 = Enables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0 = No effect.
1 = Enables the Load Overrun Interrupt.
• CPAS: RA Compare
0 = No effect.
1 = Enables the RA Compare Interrupt.
• CPBS: RB Compare
0 = No effect.
1 = Enables the RB Compare Interrupt.
• CPCS: RC Compare
0 = No effect.
1 = Enables the RC Compare Interrupt.
• LDRAS: RA Loading
0 = No effect.
1 = Enables the RA Load Interrupt.
• LDRBS: RB Loading
0 = No effect.
1 = Enables the RB Load Interrupt.
• ETRGS: External Trigger
0 = No effect.
1 = Enables the External Trigger Interrupt.
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36.7.10 TC Interrupt Disable Register
Name:
Address:
Access:
TC_IDRx [x=0..2]
0xF8008028 (0)[0], 0xF8008068 (0)[1], 0xF80080A8 (0)[2], 0xF800C028 (1)[0], 0xF800C068 (1)[1],
0xF800C0A8 (1)[2]
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
23
–
15
–
22
–
14
–
21
–
13
–
7
ETRGS
6
LDRBS
5
LDRAS
• COVFS: Counter Overflow
0 = No effect.
1 = Disables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0 = No effect.
1 = Disables the Load Overrun Interrupt (if WAVE = 0).
• CPAS: RA Compare
0 = No effect.
1 = Disables the RA Compare Interrupt (if WAVE = 1).
• CPBS: RB Compare
0 = No effect.
1 = Disables the RB Compare Interrupt (if WAVE = 1).
• CPCS: RC Compare
0 = No effect.
1 = Disables the RC Compare Interrupt.
• LDRAS: RA Loading
0 = No effect.
1 = Disables the RA Load Interrupt (if WAVE = 0).
• LDRBS: RB Loading
0 = No effect.
1 = Disables the RB Load Interrupt (if WAVE = 0).
• ETRGS: External Trigger
0 = No effect.
1 = Disables the External Trigger Interrupt.
4
CPCS
20
–
12
–
19
–
11
–
3
CPBS
18
–
10
–
2
CPAS
17
–
9
–
1
LOVRS
24
–
16
–
8
–
0
COVFS
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36.7.11 TC Interrupt Mask Register
Name:
Address:
Access:
TC_IMRx [x=0..2]
0xF800802C (0)[0], 0xF800806C (0)[1], 0xF80080AC (0)[2], 0xF800C02C (1)[0], 0xF800C06C (1)[1],
0xF800C0AC (1)[2]
Read-only
31
–
23
–
15
–
7
ETRGS
30
–
22
–
14
–
6
LDRBS
29
–
21
–
13
–
5
LDRAS
28
–
20
–
12
–
4
CPCS
27
–
19
–
11
–
3
CPBS
10
–
2
CPAS
26
–
18
–
25
–
17
–
9
–
1
LOVRS
24
–
16
–
8
–
0
COVFS
• COVFS: Counter Overflow
0 = The Counter Overflow Interrupt is disabled.
1 = The Counter Overflow Interrupt is enabled.
• LOVRS: Load Overrun
0 = The Load Overrun Interrupt is disabled.
1 = The Load Overrun Interrupt is enabled.
• CPAS: RA Compare
0 = The RA Compare Interrupt is disabled.
1 = The RA Compare Interrupt is enabled.
• CPBS: RB Compare
0 = The RB Compare Interrupt is disabled.
1 = The RB Compare Interrupt is enabled.
• CPCS: RC Compare
0 = The RC Compare Interrupt is disabled.
1 = The RC Compare Interrupt is enabled.
• LDRAS: RA Loading
0 = The Load RA Interrupt is disabled.
1 = The Load RA Interrupt is enabled.
• LDRBS: RB Loading
0 = The Load RB Interrupt is disabled.
1 = The Load RB Interrupt is enabled.
• ETRGS: External Trigger
0 = The External Trigger Interrupt is disabled.
1 = The External Trigger Interrupt is enabled.
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36.7.12 TC Block Control Register
Name:
Address:
Access:
TC_BCR
0xF80080C0 (0), 0xF800C0C0 (1)
Write-only
15
–
7
–
31
–
23
–
14
–
6
–
30
–
22
–
13
–
5
–
29
–
21
–
12
–
4
–
28
–
20
–
11
–
3
–
27
–
19
–
10
–
2
–
26
–
18
–
• SYNC: Synchro Command
0 = No effect.
1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
1
–
9
–
25
–
17
–
24
–
16
–
8
–
0
SYNC
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36.7.13 TC Block Mode Register
Name:
Address:
Access:
TC_BMR
0xF80080C4 (0), 0xF800C0C4 (1)
Read-write
15
–
7
–
31
–
23
–
14
–
6
–
30
–
22
–
13
–
5
29
–
21
–
TC2XC2S
12
–
4
28
–
20
–
• TC0XC0S: External Clock Signal 0 Selection
Value
0
1
2
3
Name
TCLK0
–
TIOA1
TIOA2
Description
Signal connected to XC0: TCLK0
Reserved
Signal connected to XC0: TIOA1
Signal connected to XC0: TIOA2
• TC1XC1S: External Clock Signal 1 Selection
11
–
3
27
–
19
–
26
–
18
–
25
–
17
–
10
–
9
–
2 1
TC1XC1S TC0XC0S
8
–
0
24
–
16
–
Value
0
1
2
3
Name
TCLK1
–
TIOA0
TIOA2
Description
Signal connected to XC1: TCLK1
Reserved
Signal connected to XC1: TIOA0
Signal connected to XC1: TIOA2
• TC2XC2S: External Clock Signal 2 Selection
Value
0
1
2
3
Name
TCLK2
–
TIOA1
TIOA2
Description
Signal connected to XC2: TCLK2
Reserved
Signal connected to XC2: TIOA1
Signal connected to XC2: TIOA2
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37.
Pulse Width Modulation Controller (PWM)
37.1 Description
The PWM macrocell controls several channels independently. Each channel controls one square output waveform.
Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock.
All PWM macrocell accesses are made through APB mapped registers.
Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle.
37.2 Embedded characteristics
4 Channels
One 16-bit Counter Per Channel
Common Clock Generator Providing Thirteen Different Clocks
A Modulo n Counter Providing Eleven Clocks
Two Independent Linear Dividers Working on Modulo n Counter Outputs
Independent Channels
Independent Enable Disable Command for Each Channel
Independent Clock Selection for Each Channel
Independent Period and Duty Cycle for Each Channel
Double Buffering of Period or Duty Cycle for Each Channel
Programmable Selection of The Output Waveform Polarity for Each Channel
Programmable Center or Left Aligned Output Waveform for Each Channel Block Diagram
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37.3 Block Diagram
Figure 37-1. Pulse Width Modulation Controller Block Diagram
PWM
Controller
PWMx
Channel
Clock
Selector
Period
Update
Duty Cycle
Counter
Comparator
PWMx
PWMx
PIO
PMC
MCK
PWM0
Channel
Clock
Selector
Period
Update
Duty Cycle
Counter
Comparator
Clock Generator APB Interface Interrupt Generator
PWM0
PWM0
Interrupt Controller
APB
37.4 I/O Lines Description
Each channel outputs one waveform on one external I/O line.
Table 37-1. I/O Line Description
Name Description
PWMx PWM Waveform Output for channel x
Type
Output
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37.5 Product Dependencies
37.5.1 I/O Lines
The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller.
All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs.
Table 37-2. I/O Lines
Instance
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
Signal
PWM0
PWM0
PWM0
PWM1
PWM1
PWM1
PWM2
PWM2
PWM3
PWM3
I/O Line
PB11
PC10
PC18
PB12
PC11
PC19
PB13
PC20
PB14
PC21
Peripheral
B
C
C
C
C
B
B
C
B
C
37.5.2 Power Management
The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management
Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later. In this case, the PWM will resume its operations where it left off.
All the PWM registers except PWM_CDTY and PWM_CPRD can be read without the PWM peripheral clock enabled. All the registers can be written without the peripheral clock enabled.
37.5.3 Interrupt Sources
The PWM interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the PWM interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the PWM interrupt line in edge sensitive mode.
Table 37-3. Peripheral IDs
Instance
PWM
ID
18
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37.6 Functional Description
The PWM macrocell is primarily composed of a clock generator module and 4 channels.
Clocked by the system clock, MCK, the clock generator module provides 13 clocks.
Each channel can independently choose one of the clock generator outputs.
Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers.
37.6.1 PWM Clock Generator
Figure 37-2. Functional View of the Clock Generator Block Diagram
MCK modulo n counter
MCK
MCK/2
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/256
MCK/512
MCK/1024
Divider A clkA
PREA DIVA
PWM_MR
Divider B clkB
PREB DIVB
PWM_MR
Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management
Controller (PMC).
The PWM macrocell master clock, MCK, is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks.
The clock generator is divided in three blocks:
A modulo n counter which provides 11 clocks: F
MCK
F
MCK
/128, F
MCK
/256, F
MCK
/512, F
MCK
/1024
, F
MCK
/2, F
MCK
/4, F
MCK
/8, F
MCK
/16, F
MCK
/32, F
MCK
/64,
Two linear dividers (1, 1/2, 1/3,... 1/255) that provide two separate clocks: clkA and clkB
Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the PWM Mode register (PWM_MR). The resulting clock clkA
(clkB) is the clock selected divided by DIVA (DIVB) field value in the PWM Mode register (PWM_MR).
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After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true when the
PWM master clock is turned off through the Power Management Controller.
37.6.2 PWM Channel
37.6.2.1 Block Diagram
Figure 37-3. Functional View of the Channel Block Diagram
Inp u t s from clock gener a tor
Ch a nnel
Clock
S elector
Intern a l
Co u nter
Comp a r a tor
PWMx o u tp u t w a veform
Inp u t s from
APB bus
Each of the 4 channels is composed of three blocks:
A clock selector which selects one of the clocks provided by the clock generator described in
.
An internal counter clocked by the output of the clock selector. This internal counter is incremented or decremented according to the channel configuration and comparators events. The size of the internal counter is 16 bits.
A comparator used to generate events according to the internal counter value. It also computes the PWMx output waveform according to the configuration.
37.6.2.2 Waveform Properties
The different properties of output waveforms are:
The internal clock selection . The internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the
PWM_CMRx register. This field is reset at 0.
The waveform period . This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
- If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula is:
( ×
MCK
)
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
( X * CPRD * DIVA
MCK
)
or
( X * CPRD * DIVB
MCK
)
If the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula is:
( 2 X CPRD
MCK
)
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By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
( 2* X * CPRD
MCK
* DIVA )
or
( 2* X * CPRD
MCK
* DIVB )
The waveform duty cycle . This channel parameter is defined in the CDTY field of the PWM_CDTYx register.
If the waveform is left aligned then: duty cycle =
( period – 1 fchannel_x_clock
× CDTY period
)
If the waveform is center aligned, then: duty cycle =
( period ⁄
2
)
–
⁄ × CDTY
( period ⁄ 2 )
) )
The waveform polarity.
At the beginning of the period, the signal can be at high or low level. This property is defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level.
The waveform alignment . The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx register. The default mode is left aligned.
Figure 37-4. Non Overlapped Center Aligned Waveforms
No overlap
PWM0
PWM1
Period
Note:
for a detailed description of center aligned waveforms.
When center aligned, the internal channel counter increases up to CPRD and.decreases down to 0. This ends the period.
When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period.
Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel.
Waveforms are fixed at 0 when:
CDTY = CPRD and CPOL = 0
CDTY = 0 and CPOL = 1
Waveforms are fixed at 1 (once the channel is enabled) when:
CDTY = 0 and CPOL = 0
CDTY = CPRD and CPOL = 1
The waveform polarity must be set before enabling the channel. This immediately affects the channel output level.
Changes on channel polarity are not taken into account while the channel is enabled.
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Figure 37-5. Waveform Properties
PWM_MCKx
CHIDx(PWM_SR)
CHIDx(PWM_ENA)
CHIDx(PWM_DIS)
PWM_CCNTx
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
Output Waveform PWMx
CPOL(PWM_CMRx) = 0
Output Waveform PWMx
CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
PWM_CCNTx
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
Output Waveform PWMx
CPOL(PWM_CMRx) = 0
Output Waveform PWMx
CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
Period
Period
Center Aligned
CALG(PWM_CMRx) = 1
Left Aligned
CALG(PWM_CMRx) = 0
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37.6.3 PWM Controller Operations
37.6.3.1 Initialization
Before enabling the output channel, this channel must have been configured by the software application:
Configuration of the clock generator if DIVA and DIVB are required
Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register)
Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx
Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx
Register to update PWM_CPRDx as explained below.
Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register). Writing in PWM_CDTYx
Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx
Register to update PWM_CDTYx as explained below.
Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register)
Enable Interrupts (Writing CHIDx in the PWM_IER register)
Enable the PWM channel (Writing CHIDx in the PWM_ENA register)
It is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several CHIDx bits in the PWM_ENA register.
In such a situation, all channels may have the same clock selector configuration and the same period specified.
37.6.3.2 Source Clock Selection Criteria
The large number of source clocks can make selection difficult. The relationship between the value in the Period Register
(PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can help the user in choosing. The event number written in the Period Register gives the PWM accuracy. The Duty Cycle quantum cannot be lower than 1/PWM_CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy.
For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value between 1 up to 14 in
PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the PWM period.
37.6.3.3 Changing the Duty Cycle or the Period
It is possible to modulate the output waveform duty cycle or period.
To prevent unexpected output waveform, the user must use the update register (PWM_CUPDx) to change waveform parameters while the channel is still enabled. The user can write a new period value or duty cycle value in the update register (PWM_CUPDx). This register holds the new value until the end of the current cycle and updates the value for the next cycle. Depending on the CPD field in the PWM_CMRx register, PWM_CUPDx either updates PWM_CPRDx or
PWM_CDTYx. Note that even if the update register is used, the period must not be smaller than the duty cycle.
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Figure 37-6. Synchronized Period or Duty Cycle Update
User's Writing
PWM_CUPDx Value
1
0
PWM_CMRx. CPD
PWM_CPRDx PWM_CDTYx
To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM
Controller level.
The first method (polling method) consists of reading the relevant status bit in PWM_ISR Register according to the
enabled channel(s). See Figure 37-7
.
The second method uses an Interrupt Service Routine associated with the PWM channel.
Note: Reading the PWM_ISR register automatically clears CHIDx flags.
Figure 37-7. Polling Method
End of Cycle
PWM_ISR Read
Acknowledgement and clear previous register state
Writing in CPD field
Update of the Period or Duty Cycle
CHIDx = 1
YES
Writing in PWM_CUPDx
The last write has been taken into account
Note: Polarity and alignment can be modified only when the channel is disabled.
37.6.3.4 Interrupts
Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is disabled by setting the corresponding bit in the PWM_IDR register.
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37.7 Pulse Width Modulation Controller (PWM) User Interface
Table 37-4. Register Mapping (1)
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20 - 0xFC
0x100 - 0x1FC
0x200 + ch_num * 0x20 + 0x00
0x200 + ch_num * 0x20 + 0x04
0x200 + ch_num * 0x20 + 0x08
Register Name
PWM Mode Register PWM_MR
PWM Enable Register
PWM Disable Register
PWM Status Register
PWM Interrupt Enable Register
PWM_ENA
PWM_DIS
PWM_SR
PWM_IER
PWM Interrupt Disable Register
PWM Interrupt Mask Register
PWM Interrupt Status Register
Reserved
Reserved
PWM Channel Mode Register
PWM Channel Duty Cycle Register
PWM Channel Period Register
PWM_IDR
PWM_IMR
PWM_ISR
–
PWM_CMR
PWM_CDTY
PWM_CPRD
0x200 + ch_num * 0x20 + 0x0C
0x200 + ch_num * 0x20 + 0x10
PWM Channel Counter Register
PWM Channel Update Register
PWM_CCNT
PWM_CUPD
Note: 1. Some registers are indexed with “ch_num” index ranging from 0 to 3.
Access
Read-write
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
–
Read-write
Read-write
Read-write
Read-only
Write-only
Reset
0
0
-
-
-
0
–
-
0
0x0
0x0
0x0
0x0
-
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37.7.1 PWM Mode Register
Name:
Address:
Access:
PWM_MR
0xF8034000
Read/Write
31
–
30
–
23 22
29
–
21
28
–
20
27
19
26
18
PREB
DIVB
15
–
7
14
–
6
13
–
5
12
–
4
11
3
10
2
DIVA
• DIVA, DIVB: CLKA, CLKB Divide Factor
Value
0
1
2-255
Name
CLK_OFF
CLK_DIV1
–
Description
CLKA, CLKB clock is turned off
CLKA, CLKB clock is clock selected by PREA, PREB
CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
• PREA, PREB
PREA
25
17
9
1
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Name
MCK
MCKDIV2
MCKDIV4
MCKDIV8
MCKDIV16
MCKDIV32
MCKDIV64
MCKDIV128
MCKDIV256
MCKDIV512
MCKDIV1024
Description
Master Clock
Master Clock divided by 2
Master Clock divided by 4
Master Clock divided by 8
Master Clock divided by 16
Master Clock divided by 32
Master Clock divided by 64
Master Clock divided by 128
Master Clock divided by 256
Master Clock divided by 512
Master Clock divided by 1024
Values which are not listed in the table must be considered as “reserved”.
8
0
24
16
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37.7.2 PWM Enable Register
Name:
Address:
Access:
PWM_ENA
0xF8034004
Write-only
31
–
30
–
23
–
15
–
7
–
22
–
14
–
6
–
• CHIDx: Channel ID
0 = No effect.
1 = Enable PWM output for channel x.
29
–
21
–
13
–
5
–
37.7.3 PWM Disable Register
Name:
Address:
Access:
PWM_DIS
0xF8034008
Write-only
31
–
30
–
23
–
15
–
7
–
22
–
14
–
6
–
• CHIDx: Channel ID
0 = No effect.
1 = Disable PWM output for channel x.
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
CHID3
26
–
18
–
10
–
2
CHID2
25
–
17
–
9
–
1
CHID1
24
–
16
–
8
–
0
CHID0
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
CHID3
26
–
18
–
10
–
2
CHID2
25
–
17
–
9
–
1
CHID1
24
–
16
–
8
–
0
CHID0
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37.7.4 PWM Status Register
Name:
Address:
Access:
PWM_SR
0xF803400C
Read-only
31
–
30
–
23
–
15
–
7
–
22
–
14
–
6
–
• CHIDx: Channel ID
0 = PWM output for channel x is disabled.
1 = PWM output for channel x is enabled.
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
CHID3
26
–
18
–
10
–
2
CHID2
25
–
17
–
9
–
1
CHID1
24
–
16
–
8
–
0
CHID0
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37.7.5 PWM Interrupt Enable Register
Name:
Address:
Access:
PWM_IER
0xF8034010
Write-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
• CHIDx: Channel ID.
0 = No effect.
1 = Enable interrupt for PWM channel x.
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
CHID3
26
–
18
–
10
–
2
CHID2
25
–
17
–
9
–
1
CHID1
24
–
16
–
8
–
0
CHID0
SAM9X35 [DATASHEET]
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37.7.6 PWM Interrupt Disable Register
Name:
Address:
Access:
PWM_IDR
0xF8034014
Write-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
• CHIDx: Channel ID.
0 = No effect.
1 = Disable interrupt for PWM channel x.
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
CHID3
26
–
18
–
10
–
2
CHID2
25
–
17
–
9
–
1
CHID1
24
–
16
–
8
–
0
CHID0
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37.7.7 PWM Interrupt Mask Register
Name:
Address:
Access:
PWM_IMR
0xF8034018
Read-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
• CHIDx: Channel ID.
0 = Interrupt for PWM channel x is disabled.
1 = Interrupt for PWM channel x is enabled.
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
CHID3
26
–
18
–
10
–
2
CHID2
25
–
17
–
9
–
1
CHID1
24
–
16
–
8
–
0
CHID0
SAM9X35 [DATASHEET]
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37.7.8 PWM Interrupt Status Register
Name:
Address:
Access:
PWM_ISR
0xF803401C
Read-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
CHID3
26
–
18
–
10
–
2
CHID2
• CHIDx: Channel ID
0 = No new channel period has been achieved since the last read of the PWM_ISR register.
1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
Note: Reading PWM_ISR automatically clears CHIDx flags.
25
–
17
–
9
–
1
CHID1
24
–
16
–
8
–
0
CHID0
SAM9X35 [DATASHEET]
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37.7.9 PWM Channel Mode Register
Name:
Address:
Access:
PWM_CMR[0..3]
0xF8034200 [0], 0xF8034220 [1], 0xF8034240 [2], 0xF8034260 [3]
Read/Write
31
–
30
–
29
–
28
–
27
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
20
–
12
–
4
–
19
–
11
–
3
• CPRE: Channel Pre-scaler
0111
1000
1001
1010
1011
1100
Value
0000
0001
0010
0011
0100
0101
0110
Name
MCKDIV2
MCKDIV4
MCKDIV8
MCKDIV16
MCKDIV32
MCKDIV64
MCKDIV128
MCKDIV256
MCKDIV512
MCKDIV1024
CLKA
CLKB
Description
Master Clock divided by 2
Master Clock divided by 4
Master Clock divided by 8
Master Clock divided by 16
Master Clock divided by 32
Master Clock divided by 64
Master Clock divided by 128
Master Clock divided by 256
Master Clock divided by 512
Master Clock divided by 1024
Clock A
Clock B
Values which are not listed in the table must be considered as “reserved”.
• CALG: Channel Alignment
0 = The period is left aligned.
1 = The period is center aligned.
• CPOL: Channel Polarity
0 = The output waveform starts at a low level.
1 = The output waveform starts at a high level.
• CPD: Channel Update Period
0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event.
1 = Writing to the PWM_CUPDx will modify the period at the next period start event.
26
–
18
–
10
CPD
2
CPRE
9
CPOL
1
25
–
17
–
24
–
16
–
8
CALG
0
SAM9X35 [DATASHEET]
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37.7.10 PWM Channel Duty Cycle Register
Name:
Address:
Access:
PWM_CDTY[0..3]
0xF8034204 [0], 0xF8034224 [1], 0xF8034244 [2], 0xF8034264 [3]
Read/Write
31 30 29 28 27
CDTY
23 22 21 20 19
CDTY
15 14 13 12 11
CDTY
26
18
10
7 6 5 4 3 2
CDTY
Only the first 16 bits (internal channel counter size) are significant.
• CDTY: Channel Duty Cycle
Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
25
17
9
1
8
0
24
16
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37.7.11 PWM Channel Period Register
Name:
Address:
Access:
PWM_CPRD[0..3]
0xF8034208 [0], 0xF8034228 [1], 0xF8034248 [2], 0xF8034268 [3]
Read/Write
31 30 29 28 27
CPRD
23 22 21 20 19
CPRD
15 14 13 12 11
CPRD
26
18
10
25
17
9
24
16
8
7 6 5 4 3 2 1 0
CPRD
Only the first 16 bits (internal channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula is:
( ×
MCK
)
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
( CRPD DIVA
MCK
)
or
( ×
MCK
)
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula is:
( 2 X CPRD
MCK
)
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
( 2
CPRD DIVA
MCK
)
or
( 2 × CPRD ×
MCK
DIVB
----------------------------------------------------
)
SAM9X35 [DATASHEET]
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37.7.12 PWM Channel Counter Register
Name:
Address:
Access:
PWM_CCNT[0..3]
0xF803420C [0], 0xF803422C [1], 0xF803424C [2], 0xF803426C [3]
Read-only
31 30 29 28 27
CNT
23 22 21 20 19
CNT
15 14 13 12 11
CNT
7 6 5 4 3
CNT
26
18
10
2
25
17
9
1
• CNT: Channel Counter Register
Internal counter value. This register is reset when:
• The channel is enabled (writing CHIDx in the PWM_ENA register).
• The counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned.
8
0
24
16
SAM9X35 [DATASHEET]
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37.7.13 PWM Channel Update Register
Name:
Address:
Access:
PWM_CUPD[0..3]
0xF8034210 [0], 0xF8034230 [1], 0xF8034250 [2], 0xF8034270 [3]
Write-only
31 30 29 28 27
CUPD
23 22 21 20 19
CUPD
26
18
25
17
24
16
15 14 13 12 11 10 9 8
CUPD
7 6 5 4 3 2 1 0
CUPD
CUPD: Channel Update Register
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle.
Only the first 16 bits (internal channel counter size) are significant.
When CPD field of PWM_CMRx register = 0, the duty-cycle (CDTY of PWM_CDTYx register) is updated with the CUPD value at the beginning of the next period.
When CPD field of PWM_CMRx register = 1, the period (CPRD of PWM_CPRDx register) is updated with the CUPD value at the beginning of the next period.
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38.
Two-wire Interface (TWI)
38.1 Description
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot
Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported.
Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.
Below,
lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full I 2 C compatible device.
Table 38-1. Atmel TWI compatibility with I 2 C Standard
I 2 C Standard Atmel TWI
Standard Mode Speed (100 KHz)
Fast Mode Speed (400 KHz)
7 or 10 bits Slave Addressing
START BYTE
Supported
Supported
Supported
Not Supported
Repeated Start (Sr) Condition
ACK and NACK Management
Slope control and input filtering (Fast mode)
Clock stretching
Multi Master Capability
Supported
Supported
Not Supported
Supported
Supported
Note: 1. START + b000000001 + Ack + Sr
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38.2 Embedded Characteristics
Three TWIs
Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices
One, Two or Three Bytes for Slave Address
Sequential Read-write Operations
Master, Multi-master and Slave Mode Operation
Bit Rate: Up to 400 Kbits
General Call Supported in Slave mode
SMBUS Quick Command Supported in Master Mode
Connection to DMA Controller (DMA) Channel Capabilities optimizes Data Transfers in Master Mode Only
Note:
for details on compatibility with I²C Standard.
38.3 List of Abbreviations
Table 38-2. Abbreviations
Abbreviation
TWI
A
NA
P
S
Sr
SADR
ADR
R
W
Description
Two-wire Interface
Acknowledge
Non Acknowledge
Stop
Start
Repeated Start
Slave Address
Any address except SADR
Read
Write
SAM9X35 [DATASHEET]
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38.4 Block Diagram
Figure 38-1. Block Diagram
APB Bridge
PMC
MCK
Two-wire
Interface
38.5 Application Block Diagram
Figure 38-2. Application Block Diagram
PIO
Interrupt
Controller
38.5.1 I/O Lines Description
Table 38-3. I/O Lines Description
Pin Name Pin Description
TWD
TWCK
Two-wire Serial Data
Two-wire Serial Clock
Type
Input/Output
Input/Output
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38.6 Product Dependencies
38.6.1 I/O Lines
Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see
Figure 38-2 on page 716 ). When the bus is free, both lines are high. The output stages of devices
connected to the bus must have an open-drain or open-collector to perform the wired-AND function.
TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following step:
Program the PIO controller to dedicate TWD and TWCK as peripheral lines.
The user must not program TWD and TWCK as open-drain. It is already done by the hardware.
Table 38-4. I/O Lines
Instance
TWI0
TWI0
TWI1
TWI1
TWI2
TWI2
Signal
TWCK0
TWD0
TWCK1
TWD1
TWCK2
TWD2
I/O Line
PA31
PA30
PC1
PC0
PB5
PB4
Peripheral
A
A
C
C
B
B
38.6.2 Power Management
Enable the peripheral clock.
The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock.
38.6.3 Interrupt
The TWI interface has an interrupt line connected to the Interrupt Controller. In order to handle interrupts, the Interrupt
Controller must be programmed before configuring the TWI.
Table 38-5. Peripheral IDs
Instance ID
TWI0
TWI1
TWI2
9
10
11
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38.7 Functional Description
38.7.1 Transfer Format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see
Each transfer begins with a START condition and terminates with a STOP condition (see
A high-to-low transition on the TWD line while TWCK is high defines the START condition.
A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 38-3. START and STOP Conditions
TWD
TWCK
Start Stop
Figure 38-4. Transfer Format
TWD
TWCK
Start Address R/W Ack
38.7.2 Modes of Operation
The TWI has different modes of operations:
Master transmitter mode
Master receiver mode
Multi-master transmitter mode
Multi-master receiver mode
Slave transmitter mode
Slave receiver mode
These modes are described in the following chapters.
Data Ack Data Ack Stop
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38.8 Master Mode
38.8.1 Definition
The Master is the device that starts a transfer, generates a clock and stops it.
38.8.2 Application Block Diagram
Figure 38-5. Master Mode Typical Application Block Diagram
VDD
Rp Rp
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
Serial EEPROM
Slave 1
I²C RTC
Slave 2
Rp: Pull up value as given by the I²C Standard
I²C LCD
Controller
Slave 3
I²C Temp.
Sensor
Slave 4
38.8.3 Programming Master Mode
The following registers have to be programmed before entering Master mode:
1.
DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to access slave devices in read or write mode.
2.
CKDIV + CHDIV + CLDIV: Clock Waveform.
3.
SVDIS: Disable the slave mode.
4.
MSEN: Enable the master mode.
38.8.4 Master Transmitter Mode
After the master initiates a Start condition when writing into the Transmit Holding Register, TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Not Acknowledge bit (NACK ) in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new write in the
TWI_THR.
While no new data is written in the TWI_THR, the Serial Clock Line is tied low. When new data is written in the TWI_THR, the SCL is released and the data is sent. To generate a STOP event, the STOP command must be performed by writing in the STOP field of TWI_CR.
After a Master Write transfer, the Serial Clock line is stretched (tied low) while no new data is written in the TWI_THR or until a STOP command is performed.
,
.
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Figure 38-6. Master Write with One Data Byte
STOP Command sent (write in TWI_CR)
TWD S
TXCOMP
DADR W A DATA A P
TXRDY
Write THR (DATA)
Figure 38-7. Master Write with Multiple Data Bytes
STOP command performed
(by writing in the TWI_CR)
TWD S DADR W A DATA n A
TWCK
TXCOMP
TXRDY
Write THR (Data n)
DATA n+1 A DATA n+2 A P
Write THR (Data n+1) Write THR (Data n+2)
Last data sent
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Figure 38-8. Master Write with One Byte Internal Address and Multiple Data Bytes
STOP command performed
(by writing in the TWI_CR)
TWD S
TWCK
DADR W A
TXCOMP
IADR A DATA n A DATA n+1 A DATA n+2 A P
TXRDY
Write THR (Data n)
Write THR (Data n+1) Write THR (Data n+2)
Last data sent
38.8.5 Master Receiver Mode
The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case
(MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the master sends an acknowledge condition to notify the slave that the data has been received except for the last data, after
the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
When a single data byte read is performed, with or without internal address ( IADR), the START and STOP bits must be set at the same time. See
Figure 38-9 . When a multiple data byte read is performed, with or without internal address
(
IADR), the STOP bit must be set after the next-to-last data received. See Figure 38-10
. For Internal Address usage see
If the receive holding register (TWI_RHR) is full (RXRDY high) and the master is receiving data, the Serial Clock Line will be tied low before receiving the last bit of the data and until the TWI_RHR register is read. Once the TWI_RHR register is read, the master will stop stretching the Serial Clock Line and end the data reception. See
Warning: When receiving multiple bytes in master read mode, if the next-to-last access is not read (the RXRDY flag remains high), the last access will not be completed until TWI_RHR is read. The last access stops on the next-to-last bit
(clock stretching). When the TWI_RHR register is read there is only half a bit period to send the stop bit command, else another read access might occur (spurious access).
A possible workaround is to raise the STOP BIT command before reading the TWI_RHR on the next-to-last access
(within IT handler).
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Figure 38-9. Master Read with One Data Byte
TWD S DADR R A DATA N P
TXCOMP
Write START &
STOP Bit
RXRDY
Read RHR
Figure 38-10. Master Read with Multiple Data Bytes
TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P
TXCOMP
RXRDY
Write START Bit
Read RHR
DATA n
Read RHR
DATA (n+1)
Read RHR
DATA (n+m)-1
Read RHR
DATA (n+m)
Write STOP Bit after next-to-last data read
Figure 38-11. Master Read Clock Stretching with Multiple Data Bytes
S TOP comm a nd performed
( b y writing in the TWI_CR)
Clock S treching
TWD S DADR W A DATA n A DATA n+1 A DATA n+2 A P
TWCK
TXCOMP
RXRDY
Re a d RHR (D a t a n) Re a d RHR (D a t a n+1) Re a d RHR (D a t a n+2)
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38.8.6 Internal Address
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices.
38.8.6.1 7-bit Slave Addressing
When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. When performing read operations with an internal address, the TWI performs a write operation to set the internal address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is sometimes called “repeated start” (Sr) in I 2 C fully-compatible devices. See
Figure 38-13 . See Figure 38-12 and
for Master Write operation with internal address.
The three internal address bytes are configurable through the Master Mode register (TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to 0.
In the figures below the following abbreviations are used:
S
Sr
P
W
R
A
N
DADR
IADR
Start
Repeated Start
Stop
Write
Read
Acknowledge
Not Acknowledge
Device Address
Internal Address
Figure 38-12. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
TWD
Three bytes internal address
S DADR W
TWD
Two bytes internal address
S DADR W
A
A
IADR(23:16)
IADR(15:8)
A
A
IADR(15:8)
IADR(7:0)
A
A
IADR(7:0)
DATA
A
A
TWD
One byte internal address
S DADR W A IADR(7:0) A DATA A P
P
DATA A P
Figure 38-13. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
TWD
Three bytes internal address
S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A Sr DADR
DATA
TWD
Two bytes internal address
S DADR W
TWD
One byte internal address
S DADR W
A IADR(15:8) A
A IADR(7:0) A
IADR(7:0)
Sr DADR
A
R
Sr
A
DADR
DATA
R A
N P
DATA
R A
N P
N P
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38.8.6.2 10-bit Slave Addressing
For a slave address higher than 7 bits, the user must configure the address size ( IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and
IADR[23:16] can be used the same as in 7-bit Slave Addressing.
Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
1.
Program IADRSZ = 1,
2.
Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3.
Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address)
addresses to access the device.
Figure 38-14. Internal Address Usage
S
T
A
R
T
Device
Address
0
M
S
B
W
R
I
T
E
FIRST
WORD ADDRESS
SECOND
WORD ADDRESS
L
S
B
R
/
W
A
C
K
M
S
B
A
C
K
L
S
B
A
C
K
DATA
A
C
K
S
T
O
P
38.8.7 Using the DMA Controller
The use of the DMA significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequence.
38.8.7.1 Data Transmit with the DMA
1.
Initialize the DMA (channels, memory pointers, size, etc.);
2.
Configure the master mode (DADR, CKDIV, etc.).
3.
Enable the DMA.
4.
Wait for the DMA BTC flag.
5.
Disable the DMA.
38.8.7.2 Data Receive with the DMA
The PDC transfer size must be defined with the buffer size minus 2. The two remaining characters must be managed without PDC to ensure that the exact number of bytes are received whatever the system bus latency conditions encountered during the end of buffer transfer period.
1.
Initialize the DMA (channels, memory pointers, size -2, etc.);
2.
Configure the master mode (DADR, CKDIV, etc.).
3.
Enable the DMA.
4.
Wait for the DMA BTC flag.
5.
Disable the DMA.
6.
Wait for the RXRDY flag in the TWI_SR register
7.
Set the STOP command in TWI_CR
8.
Read the penultimate character in TWI_RHR
9.
Wait for the RXRDY flag in the TWI_SR register
10. Read the last character in TWI_RHR
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38.8.8 SMBUS Quick Command (Master Mode Only)
The TWI interface can perform a Quick Command:
1.
Configure the master mode (DADR, CKDIV, etc.).
2.
Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to be sent.
3.
Start the transfer by setting the QUICK bit in the TWI_CR.
Figure 38-15. SMBUS Quick Command
TWD S DADR R/W A P
TXCOMP
TXRDY
Write QUICK command in TWI_CR
38.8.9 Read-write Flowcharts
The following flowcharts shown in
,
give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register
(TWI_IER) be configured first.
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Figure 38-16. TWI Write Operation with Single Data Byte without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Transfer direction bit
Write ==> bit MREAD = 0
Load Transmit register
TWI_THR = Data to send
Write STOP Command
TWI_CR = STOP
Read Status register
TXRDY = 1?
Yes
Read Status register
TXCOMP = 1?
Yes
Transfer finished
No
No
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Figure 38-17. TWI Write Operation with Single Data Byte and Internal Address
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Figure 38-18. TWI Write Operation with Multiple Data Bytes with or without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Write ==> bit MREAD = 0
Internal address size = 0?
Yes
Load Transmit register
TWI_THR = Data to send
No
Set the internal address
TWI_IADR = address
Read Status register
TWI_THR = data to send
No
Yes
TXRDY = 1?
Yes
Data to send?
Write STOP Command
TWI_CR = STOP
Read Status register
Yes
TXCOMP = 1?
No
END
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Figure 38-19. TWI Read Operation with Single Data Byte without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Transfer direction bit
Read ==> bit MREAD = 1
Start the transfer
TWI_CR = START | STOP
Read status register
No
RXRDY = 1?
Yes
Read Receive Holding Register
Read Status register
TXCOMP = 1?
Yes
END
No
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Figure 38-20. TWI Read Operation with Single Data Byte and Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (IADRSZ)
- Transfer direction bit
Read ==> bit MREAD = 1
Set the internal address
TWI_IADR = address
Start the transfer
TWI_CR = START | STOP
Read Status register
RXRDY = 1?
Yes
Read Receive Holding register
No
Read Status register
TXCOMP = 1?
Yes
END
No
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Figure 38-21. TWI Read Operation with Multiple Data Bytes with or without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Read ==> bit MREAD = 1
Internal address size = 0?
Yes
Start the transfer
TWI_CR = START
Read Status register
RXRDY = 1?
Yes
Read Receive Holding register (TWI_RHR)
No
No
Last data to read but one?
Yes
Stop the transfer
TWI_CR = STOP
Read Status register
RXRDY = 1?
Yes
Read Receive Holding register (TWI_RHR)
No
Set the internal address
TWI_IADR = address
Read status register
No
TXCOMP = 1?
Yes
END
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38.9 Multi-master Mode
38.9.1 Definition
More than one master may handle the bus at the same time without data corruption by using arbitration.
Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero.
As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration.
Arbitration is illustrated in
38.9.2 Different Multi-master Modes
Two multi-master modes may be distinguished:
1.
TWI is considered as a Master only and will never be addressed.
2.
TWI may be either a Master or a Slave and may be addressed.
Note: In both Multi-master modes arbitration is supported.
38.9.2.1 TWI as Master Only
In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with the
ARBLST (ARBitration Lost) flag in addition.
If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer.
If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically waits
for a STOP condition on the bus to initiate the transfer (see Figure 38-22 on page 733 ).
Note: The state of the bus (busy or free) is not indicated in the user interface.
38.9.2.2 TWI as Master or Slave
The automatic reversal from Master to Slave is not supported in case of a lost arbitration.
Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multi-master mode described in the steps below.
1.
Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if TWI is addressed).
2.
If TWI has to be set in Master mode, wait until TXCOMP flag is at 1.
3.
Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR).
4.
As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the bus is considered as free, TWI initiates the transfer.
5.
As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the user must monitor the ARBLST flag.
6.
If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case where the
Master that won the arbitration wanted to access the TWI.
7.
If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode.
Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR.
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Figure 38-22. Programmer Sends Data While the Bus is Busy
TWCK
TWD
STOP sent by the master
DATA sent by a master
Bus is busy
Bus is free
TWI DATA transfer
Transfer is kept
START sent by the TWI
DATA sent by the TWI
A transfer is programmed
(DADR + W + START + Write THR)
Bus is considered as free
Transfer is initiated
Figure 38-23. Arbitration Cases
TWCK
TWD
TWCK
Data from a Master
Data from TWI
TWD
S 1 0 0 1 1
S 1 0 1
Arbitration is lost
TWI stops sending data
S 1 0 0 1 1 Data from the master
P
P
S 1 0 1
Arbitration is lost
The master stops sending data
S 1 0 0 1 1
S 1 0 0 1 1 Data from the TWI
ARBLST
Bus is busy Bus is free
TWI DATA transfer Transfer is kept
A transfer is programmed
(DADR + W + START + Write THR)
Transfer is stopped
Transfer is programmed again
(DADR + W + START + Write THR)
Bus is considered as free
Transfer is initiated
The flowchart shown in
gives an example of read and write operations in Multi-master mode.
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Figure 38-24. Multi-master Flowchart
START
Programm the SLAVE mode:
SADR + MSDIS + SVEN
Read Status Register
No
No
No
SVACC = 1 ?
No
EOSACC = 1 ?
Yes
TXCOMP = 1 ?
Yes
Need to perform a master access ?
Yes
Yes
GACC = 1 ?
No
SVREAD = 1 ?
Yes
No
RXRDY= 1 ?
Yes
Read TWI_RHR
No
GENERAL CALL TREATMENT
Decoding of the programming sequence
Prog seq
OK ?
Change SADR
No
TXRDY= 1 ?
Yes
Write in TWI_THR
No
Program the Master mode
DADR + SVDIS + MSEN + CLK + R / W
Read Status Register
Yes
ARBLST = 1 ?
Read TWI_RHR
No
Yes
Yes
Yes
RXRDY= 0 ?
No
Data to read?
No
MREAD = 1 ?
No
TXRDY= 0 ?
No
Data to send ?
Yes
Yes
No
Write in TWI_THR
Stop Transfer
TWI_CR = STOP
Yes
Read Status Register
TXCOMP = 0 ?
No
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38.10 Slave Mode
38.10.1 Definition
The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master.
In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master).
38.10.2 Application Block Diagram
Figure 38-25. Slave Mode Typical Application Block Diagram
VDD
R R
Master
Host with
TWI
Interface
TWD
TWCK
Host with TWI
Interface
Slave 1
Host with TWI
Interface
Slave 2
LCD Controller
Slave 3
38.10.3 Programming Slave Mode
The following fields must be programmed before entering Slave mode:
1.
SADR (TWI_SMR): The slave device address is used in order to be accessed by master devices in read or write mode.
2.
MSDIS (TWI_CR): Disable the master mode.
3.
SVEN (TWI_CR): Enable the slave mode.
As the device receives the clock, values written in TWI_CWGR are not taken into account.
38.10.4 Receiving Data
After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave ACCess) flag is set and SVREAD (Slave
READ) indicates the direction of the transfer.
SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected,
EOSACC (End Of Slave ACCess) flag is set.
38.10.4.1 Read Sequence
In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR (TWI Transmit Holding
Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset.
As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set.
Note that a STOP or a repeated START always follows a NACK.
.
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38.10.4.2 Write Sequence
In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the
TWI_RHR.
TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset.
.
38.10.4.3 Clock Synchronization Sequence
In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization.
Clock stretching information is given by the SCLWS (Clock Wait state) bit.
and
38.10.4.4 General Call
In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set.
After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new address programming sequence.
.
38.10.5 Data Transfer
38.10.5.1 Read Operation
The read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address
(SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
Figure 38-26 on page 736 describes the write operation.
Figure 38-26. Read Access Ordered by a MASTER
SADR does not match,
TWI answers with a NACK
SADR matches,
TWI answers with an ACK
ACK/NACK from the Master
TWD
TXRDY
NACK
SVACC
SVREAD
S ADR R NA DATA NA P/S/Sr SADR R A DATA A
Write THR
A DATA NA S/Sr
Read RHR
SVREAD has to be taken into account only while SVACC is active
EOSVACC
Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged.
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38.10.5.2 Write Operation
The write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
Figure 38-27 on page 737 describes the Write operation.
Figure 38-27. Write Access Ordered by a Master
SADR does not match,
TWI answers with a NACK
SADR matches,
TWI answers with an ACK
Read RHR
TWD
RXRDY
SVACC
SVREAD
S ADR W NA DATA NA P/S/Sr SADR W A DATA A A DATA NA S/Sr
SVREAD has to be taken into account only while SVACC is active
EOSVACC
Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read.
38.10.5.3 General Call
The general call is performed in order to change the address of the slave.
If a GENERAL CALL is detected, GACC is set.
After the detection of General Call, it is up to the programmer to decode the commands which come afterwards.
In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches.
Figure 38-28 on page 737 describes the General Call access.
Figure 38-28. Master Performs a General Call
0000000 + W
RESET command = 00000110X
WRITE command = 00000100X
TXD S A Reset or write DADD A DATA1 A DATA2
New SADR
Programming sequence
A New SADR A P
GCACC
Reset after read
SVACC
Note: This method allows the user to create an own programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the master.
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38.10.5.4 Clock Synchronization
In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented.
Clock Synchronization in Read Mode
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded.
Figure 38-29 on page 738 describes the clock synchronization in Read mode.
Figure 38-29. Clock Synchronization in Read Mode
TWI_THR 1 DATA1 DATA2
SADR R A DATA0 A DATA1 A XXXXXXX
2
DATA2 NA S
TWCK
CLOCK is tied low by the TWI as long as THR is empty
Write THR
SCLWS
TXRDY
SVACC
SVREAD
TXCOMP
1
2
As soon as a START is detected
TWI_THR is transmitted to the shift register Ack or Nack from the master
The data is memorized in TWI_THR until a new value is written
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
Notes: 1. TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged.
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR.
3. SCLWS is automatically set when the clock synchronization mechanism is started.
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Clock Synchronization in Write Mode
The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read.
Figure 38-30 on page 739 describes the clock synchronization in Read mode.
Figure 38-30. Clock Synchronization in Write Mode
TWCK
TWD S SADR W A DATA0
CLOCK is tied low by the TWI as long as RHR is full
A DATA1 A DATA2 NA S ADR
TWI_RHR DATA0 is not read in the RHR DATA1 DATA2
SCLWS
RXRDY
SCL is stretched on the last bit of DATA1
Rd DATA0
Rd DATA1
Rd DATA2
SVACC
SVREAD
TXCOMP
As soon as a START is detected
Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR.
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished.
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38.10.5.5 Reversal after a Repeated Start
Reversal of Read to Write
The master initiates the communication by a read command and finishes it by a write command.
Figure 38-31 on page 740 describes the repeated start + reversal from Read to Write mode.
Figure 38-31. Repeated Start + Reversal from Read to Write Mode
TWI_THR
DATA0 DATA1
TWD
S SADR R A DATA0 A DATA1 NA Sr SADR W A DATA2 A DATA3 A P
TWI_RHR
SVACC
SVREAD
TXRDY
RXRDY
EOSACC
TXCOMP As soon as a START is detected
Cleared after read
DATA2 DATA3
Note: 1. TXCOMP is only set at the end of the transmission because after the repeated start, SAD is detected again.
Reversal of Write to Read
The master initiates the communication by a write command and finishes it by a read command.
740 describes the repeated start + reversal from Write to Read mode.
Figure 38-32. Repeated Start + Reversal from Write to Read Mode
TWI_THR DATA2 DATA3
TWD
TWI_RHR
SVACC
SVREAD
TXRDY
RXRDY
EOSACC
TXCOMP
S SADR W A DATA0 A DATA1 A Sr SADR R A DATA2 A DATA3 NA P
Read TWI_RHR
As soon as a START is detected
DATA0 DATA1
Cleared after read
Notes: 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before the ACK.
2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
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38.10.6 Read Write Flowcharts
The flowchart shown in
gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first.
Figure 38-33. Read Write Flowchart in Slave Mode
Set the SLAVE mode:
SADR + MSDIS + SVEN
Read Status Register
No
SVACC = 1 ?
No
EOSACC = 1 ?
No
TXCOMP = 1 ?
END
GACC = 1 ?
No
SVREAD = 0 ?
No
TXRDY= 1 ?
No
Write in TWI_THR
RXRDY= 0 ?
Read TWI_RHR
GENERAL CALL TREATMENT
Decoding of the programming sequence
Prog seq
OK ?
No
Change SADR
No
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38.11 Write Protection System
In order to bring security to the TWI, a write protection system has been implemented.
The write protection mode prevents the write of
“TWI Clock Waveform Generator Register”
and
Write Protection Status Register”
and the register write request is canceled. When a write protection error occurs the
WPROTERR flag is set and the address of the corresponding canceled register write is available in the WPROTADRR field of the TWI_WPROT_STATUS register.
Due to the nature of the write protection feature, enabling and disabling the write protection mode requires the use of a security code. Thus when enabling or disabling the write protection mode the SECURITY_CODE field of the
canceled.
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38.12 Two-wire Interface (TWI) User Interface
Table 38-6. Register Mapping
Offset Register
0x00 Control Register
0x04
0x08
0x0C
0x10
Master Mode Register
Slave Mode Register
Internal Address Register
Clock Waveform Generator Register
0x14 - 0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0xE4
Reserved
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Receive Holding Register
Transmit Holding Register
Protection Mode Register
Name
TWI_CR
TWI_MMR
TWI_SMR
TWI_IADR
TWI_CWGR
–
TWI_SR
TWI_IER
TWI_IDR
TWI_IMR
TWI_RHR
TWI_THR
TWI_WPROT_MODE
0xE8
Protection Status Register
Reserved
Note: 1. All unlisted offset values are considered as “reserved”.
TWI_WPROT_STATUS
–
Access Reset
Write-only N / A
Read-write
Read-write
Read-write
Read-write
0x00000000
0x00000000
0x00000000
0x00000000
–
Read-only
Write-only
Write-only
Read-only
Read-only
Write-only
Read-write
Read-only
–
–
0x0000F009
N / A
N / A
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
–
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38.12.1 TWI Control Register
Name: TWI_CR
Address: 0xF8010000 (0), 0xF8014000 (1), 0xF8018000 (2)
Access: Write-only
Reset: 0x00000000
31
–
30
–
29
–
28
–
23
–
22
–
21
–
20
–
15
–
7
SWRST
14
–
6
QUICK
13
–
5
SVDIS
12
–
4
SVEN
27
–
19
–
11
–
3
MSDIS
10
–
2
MSEN
26
–
18
–
9
–
1
STOP
25
–
17
–
24
–
16
–
8
–
0
START
• START: Send a START Condition
0 = No effect.
1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR).
• STOP: Send a STOP Condition
0 = No effect.
1 = STOP Condition is sent just after completing the current byte transmission in master read mode.
– In single data byte master read, the START and STOP must both be set.
– In multiple data bytes master read, the STOP must be set after the last data received but one.
– In master read mode, if a NACK bit is received, the STOP is automatically performed.
– In master data write operation, a STOP condition will be sent after the transmission of the current data is finished.
• MSEN: TWI Master Mode Enabled
0 = No effect.
1 = If MSDIS = 0, the master mode is enabled.
Note: Switching from Slave to Master mode is only permitted when TXCOMP = 1.
• MSDIS: TWI Master Mode Disabled
0 = No effect.
1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling.
• SVEN: TWI Slave Mode Enabled
0 = No effect.
1 = If SVDIS = 0, the slave mode is enabled.
Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1.
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• SVDIS: TWI Slave Mode Disabled
0 = No effect.
1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation.
In write operation, the character being transferred must be completely received before disabling.
• QUICK: SMBUS Quick Command
0 = No effect.
1 = If Master mode is enabled, a SMBUS Quick Command is sent.
• SWRST: Software Reset
0 = No effect.
1 = Equivalent to a system reset.
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38.12.2 TWI Master Mode Register
Name: TWI_MMR
Address: 0xF8010004 (0), 0xF8014004 (1), 0xF8018004 (2)
Access: Read-write
Reset: 0x00000000
31
–
30
–
29
–
28
–
23
–
22 21 20
15
–
7
–
14
–
6
–
13
–
5
–
12
MREAD
4
–
27
–
19
DADR
11
–
3
–
26
–
18
10
–
2
–
25
–
17
1
–
9
IADRSZ
8
0
–
• IADRSZ: Internal Device Address Size
Value
0
1
2
3
Name
NONE
1_BYTE
2_BYTE
3_BYTE
Description
No internal device address
One-byte internal device address
Two-byte internal device address
Three-byte internal device address
• MREAD: Master Read Direction
0 = Master write direction.
1 = Master read direction.
• DADR: Device Address
The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode.
24
–
16
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38.12.3 TWI Slave Mode Register
Name: TWI_SMR
Address: 0xF8010008 (0), 0xF8014008 (1), 0xF8018008 (2)
Access: Read-write
Reset: 0x00000000
31
–
30
–
29
–
28
–
23
–
22 21 20
27
–
19
SADR
26
–
18
25
–
17
15
–
7
–
14
–
6
–
13
–
5
–
12
–
4
–
11
–
3
–
10
–
2
–
9
1
–
.
• SADR: Slave Address
The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode.
SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect.
8
0
–
24
–
16
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38.12.4 TWI Internal Address Register
Name: TWI_IADR
Address: 0xF801000C (0), 0xF801400C (1), 0xF801800C (2)
Access: Read-write
Reset: 0x00000000
31
–
30
–
29
–
28
–
23 22 21 20
IADR
15 14 13 12
IADR
7 6 5 4
IADR
• IADR: Internal Address
0, 1, 2 or 3 bytes depending on IADRSZ.
27
–
19
11
3
10
2
26
–
18
9
1
25
–
17
8
0
24
–
16
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38.12.5 TWI Clock Waveform Generator Register
Name: TWI_CWGR
Address: 0xF8010010 (0), 0xF8014010 (1), 0xF8018010 (2)
Access: Read-write
Reset: 0x00000000
31
–
30
–
29
–
28
–
23 22 21 20
27
–
19
26
–
18
15 14 13 12 11 10 9
CHDIV
7 6 5 4 3 2
CLDIV
.
TWI_CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
T low
= ( ( CLDIV × 2
CKDIV
) + 4 ) × T
MCK
1
25
–
17
CKDIV
• CHDIV: Clock High Divider
The SCL high period is defined as follows:
T high
= ( ( CHDIV × 2
CKDIV ) + 4 ) × T
MCK
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
8
0
24
–
16
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38.12.6 TWI Status Register
Name: TWI_SR
Address: 0xF8010020 (0), 0xF8014020 (1), 0xF8018020 (2)
Access: Read-only
Reset: 0x0000F009
31
–
30
–
29
–
28
–
23
–
22
–
21
–
20
–
15
7
–
14
6
OVRE
13
5
GACC
12
4
SVACC
27
–
19
–
11
EOSACC
3
SVREAD
26
–
18
–
10
SCLWS
2
TXRDY
25
–
17
–
9
ARBLST
1
RXRDY
24
–
16
–
8
NACK
0
TXCOMP
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode
can be seen in Figure 38-8 on page 721 and in
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode
can be seen in Figure 38-29 on page 738 ,
740 and Figure 38-32 on page 740
.
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in
RXRDY behavior in Slave mode
can be seen in Figure 38-27 on page 737 ,
and
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode
can be seen in Figure 38.8.4 on page 719
.
TXRDY used in Slave mode:
0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK).
1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged.
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If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it.
TXRDY behavior in Slave mode
can be seen in Figure 38-26 on page 736 ,
,
and
• SVREAD: Slave Read (automatically set / reset)
This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
0 = Indicates that a write access is performed by a Master.
1 = Indicates that a read access is performed by a Master.
SVREAD behavior can be seen in
, Figure 38-31 on page 740 and Figure
• SVACC: Slave Access (automatically set / reset)
This bit is only used in Slave mode.
0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected.
1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected.
SVACC behavior can be seen in
,
, Figure 38-31 on page 740 and Figure 38-
• GACC: General Call Access (clear on read)
This bit is only used in Slave mode.
0 = No General Call has been detected.
1 = A General Call has been detected. After the detection of General Call, if need be, the programmer may acknowledge this access and decode the following bytes and respond according to the value of the bytes.
GACC behavior
can be seen in Figure 38-28 on page 737
.
• OVRE: Overrun Error (clear on read)
This bit is only used in Master mode.
0 = TWI_RHR has not been loaded while RXRDY was set
1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
• NACK: Not Acknowledged (clear on read)
NACK used in Master mode:
0 = Each data byte has been correctly received by the far-end side TWI slave component.
1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.
NACK used in Slave Read mode:
0 = Each data byte has been correctly received by the Master.
1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill
TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it.
Note that in Slave Write mode all data are acknowledged by the TWI.
• ARBLST: Arbitration Lost (clear on read)
This bit is only used in Master mode.
0: Arbitration won.
1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.
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• SCLWS: Clock Wait State (automatically set / reset)
This bit is only used in Slave mode.
0 = The clock is not stretched.
1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character.
SCLWS behavior can be seen in
• EOSACC: End Of Slave Access (clear on read)
This bit is only used in Slave mode.
0 = A slave access is being performing.
1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset.
EOSACC behavior
can be seen in Figure 38-31 on page 740
and
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38.12.7 TWI Interrupt Enable Register
Name: TWI_IER
Address: 0xF8010024 (0), 0xF8014024 (1), 0xF8018024 (2)
Access: Write-only
Reset: 0x00000000
31
–
30
–
29
–
28
–
23
–
22
–
21
–
20
–
15
7
–
14
6
OVRE
13
5
GACC
12
4
SVACC
27
–
19
–
11
EOSACC
3
–
• TXCOMP: Transmission Completed Interrupt Enable
• RXRDY: Receive Holding Register Ready Interrupt Enable
• TXRDY: Transmit Holding Register Ready Interrupt Enable
• SVACC: Slave Access Interrupt Enable
• GACC: General Call Access Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• NACK: Not Acknowledge Interrupt Enable
• ARBLST: Arbitration Lost Interrupt Enable
• SCL_WS: Clock Wait State Interrupt Enable
• EOSACC: End Of Slave Access Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
26
–
18
–
10
SCL_WS
2
TXRDY
25
–
17
–
9
ARBLST
1
RXRDY
24
–
16
–
8
NACK
0
TXCOMP
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38.12.8 TWI Interrupt Disable Register
Name: TWI_IDR
Address: 0xF8010028 (0), 0xF8014028 (1), 0xF8018028 (2)
Access: Write-only
Reset: 0x00000000
31
–
30
–
29
–
28
–
23
–
22
–
21
–
20
–
15
7
–
14
6
OVRE
13
5
GACC
12
4
SVACC
27
–
19
–
11
EOSACC
3
–
• TXCOMP: Transmission Completed Interrupt Disable
• RXRDY: Receive Holding Register Ready Interrupt Disable
• TXRDY: Transmit Holding Register Ready Interrupt Disable
• SVACC: Slave Access Interrupt Disable
• GACC: General Call Access Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• NACK: Not Acknowledge Interrupt Disable
• ARBLST: Arbitration Lost Interrupt Disable
• SCL_WS: Clock Wait State Interrupt Disable
• EOSACC: End Of Slave Access Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
26
–
18
–
10
SCL_WS
2
TXRDY
25
–
17
–
9
ARBLST
1
RXRDY
24
–
16
–
8
NACK
0
TXCOMP
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38.12.9 TWI Interrupt Mask Register
Name: TWI_IMR
Address: 0xF801002C (0), 0xF801402C (1), 0xF801802C (2)
Access: Read-only
Reset: 0x00000000
31
–
30
–
29
–
28
–
23
–
22
–
21
–
20
–
15
7
–
14
6
OVRE
13
5
GACC
12
4
SVACC
27
–
19
–
11
EOSACC
3
–
• TXCOMP: Transmission Completed Interrupt Mask
• RXRDY: Receive Holding Register Ready Interrupt Mask
• TXRDY: Transmit Holding Register Ready Interrupt Mask
• SVACC: Slave Access Interrupt Mask
• GACC: General Call Access Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• NACK: Not Acknowledge Interrupt Mask
• ARBLST: Arbitration Lost Interrupt Mask
• SCL_WS: Clock Wait State Interrupt Mask
• EOSACC: End Of Slave Access Interrupt Mask
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
26
–
18
–
10
SCL_WS
2
TXRDY
25
–
17
–
9
ARBLST
1
RXRDY
24
–
16
–
8
NACK
0
TXCOMP
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38.12.10 TWI Receive Holding Register
Name: TWI_RHR
Address: 0xF8010030 (0), 0xF8014030 (1), 0xF8018030 (2)
Access: Read-only
Reset: 0x00000000
31
–
23
–
15
–
7
30
–
22
–
14
–
6
29
–
21
–
13
–
5
28
–
20
–
12
–
4
RXDATA
11
–
3
27
–
19
–
• RXDATA: Master or Slave Receive Holding Data
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
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38.12.11 TWI Transmit Holding Register
Name: TWI_THR
Address: 0xF8010034 (0), 0xF8014034 (1), 0xF8018034 (2)
Access: Read-write
Reset: 0x00000000
31
–
23
–
15
–
7
30
–
22
–
14
–
6
29
–
21
–
13
–
5
28
–
20
–
12
–
4
TXDATA
11
–
3
27
–
19
–
• TXDATA: Master or Slave Transmit Holding Data
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
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38.12.12 TWI Write Protection Mode Register
Name:
Address:
Access:
TWI_WPROT_MODE
0xF80100E4 (0), 0xF80140E4 (1), 0xF80180E4 (2)
Read-write
31 30 29 28 27
SECURITY_CODE
23 22 21
15
7
–
14
6
–
13
5
–
20 19
SECURITY_CODE
12 11
SECURITY_CODE
4
–
3
–
26
18
10
2
–
25
17
9
1
–
24
16
8
0
WPROT
• SECURITY_CODE: Write protection mode security code
for details).
Must be filled with 0x545749 (ASCII code for TWI).
• WPROT: Write protection bit
Enables/Disables write protection mode.
The write protected registers are:
“TWI Clock Waveform Generator Register”
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38.12.13 TWI Write Protection Status Register
Name:
Address:
Access:
TWI_WPROT_STATUS
0xF80100E8 (0), 0xF80140E8 (1), 0xF80180E8 (2)
Read-only
31 30 29 28
WPROTADDR
27
23 22 21
15
7
–
14
6
–
13
5
–
20
WPROTADDR
19
12
WPROTADDR
11
4
–
3
–
• WPROTADDR: Write Protection Error Address
Indicates the address of the register write request which generated the error.
• WPROTERR: Write Protection Error
Indicates a write protection error.
10
2
–
26
18
9
1
–
25
17
24
16
8
0
WPROTERR
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39.
Universal Synchronous Asynchronous Receiver Transmitter (USART)
39.1 Description
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485, LIN, and SPI buses, with ISO7816 T = 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS.
The USART supports the connection to the DMA Controller, which enables data transfers to the transmitter and from the receiver. The DMAC provides chained buffer management without any intervention of the processor.
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39.2 Embedded Characteristics
Programmable Baud Rate Generator
5-bit to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
Parity Generation and Error Detection
Framing Error Detection, Overrun Error Detection
MSB-first or LSB-first
Optional Break Generation and Detection
By-8 or by-16 Over-sampling Receiver Frequency
Optional Hardware Handshaking RTS-CTS
Receiver Time-out and Transmitter Timeguard
Optional Multidrop Mode with Address Generation and Detection
RS485 with Driver Control Signal
ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
NACK Handling, Error Counter with Repetition and Iteration Limit
IrDA Modulation and Demodulation
Communication at up to 115.2 Kbps
SPI Mode
Master or Slave
Serial Clock Programmable Phase and Polarity
SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
LIN Mode
Compliant with LIN 1.3 and LIN 2.0 specifications
Master or Slave
Processing of frames with up to 256 data bytes
Response Data length can be configurable or defined automatically by the Identifier
Self synchronization in Slave node configuration
Automatic processing and verification of the “Synch Break” and the “Synch Field”
The “Synch Break” is detected even if it is partially superimposed with a data byte
Automatic Identifier parity calculation/sending and verification
Parity sending and verification can be disabled
Automatic Checksum calculation/sending and verification
Checksum sending and verification can be disabled
Support both “Classic” and “Enhanced” checksum types
Full LIN error checking and reporting
Frame Slot Mode: the Master allocates slots to the scheduled frames automatically.
Generation of the Wakeup signal
Test Modes
Remote Loopback, Local Loopback, Automatic Echo
Supports Connection of:
Two DMA Controller Channels (DMAC)
Offers Buffer Transfer without Processor Intervention
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39.3 Block Diagram
Figure 39-1. USART Block Diagram
(Peripheral) DMA
Controller
Channel Channel
USART
Interrupt
Controller
USART
Interrupt
Receiver
Transmitter
PMC
MCK
DIV
MCK/DIV
SLCK
APB
Baud Rate
Generator
User Interface
PIO
Controller
Table 39-1. SPI Operating Mode
PIN USART
RXD
TXD
RXD
TXD
RTS
CTS
RTS
CTS
SPI Slave
MOSI
MISO
–
CS
SPI Master
MISO
MOSI
CS
–
RXD
RTS
TXD
CTS
SCK
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39.4 Application Block Diagram
Figure 39-2. Application Block Diagram
PPP
Serial
Driver
Field Bus
Driver
EMV
Driver
USART
IrLAP
IrDA
Driver
LIN
Driver
SPI
Driver
RS232
Drivers
RS485
Drivers
Serial
Port
Differential
Bus
Smart
Card
Slot
IrDA
Transceivers
LIN
Transceiver
SPI
Bus
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39.5 I/O Lines Description
Table 39-2. I/O Line Description
Name Description
SCK Serial Clock
TXD
RXD
CTS
RTS
Transmit Serial Data or Master Out Slave In (MOSI) in SPI Master Mode or Master In Slave Out (MISO) in SPI Slave Mode
Receive Serial Data or Master In Slave Out (MISO) in SPI Master Mode or Master Out Slave In (MOSI) in SPI Slave Mode
Clear to Send or Slave Select (NSS) in SPI Slave Mode
Request to Send or Slave Select (NSS) in SPI Master Mode
Type
I/O
I/O
Input
Input
Output
Active Level
Low
Low
39.6 Product Dependencies
39.6.1 I/O Lines
The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the
PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the hardware handshaking feature is used, the internal pull up on TXD must also be enabled.
Table 39-3. I/O Lines
Instance
USART0
USART0
USART0
USART0
USART0
USART1
USART1
USART1
USART1
USART1
USART2
USART2
USART2
USART2
USART2
RTS1
RXD1
SCK1
TXD1
CTS2
RTS2
RXD2
SCK2
TXD2
Signal
CTS0
RTS0
RXD0
SCK0
TXD0
CTS1
PC27
PA6
PC29
PA5
PB1
PB0
PA8
PB2
PA7
I/O Line
PA3
PA2
PA1
PA4
PA0
PC28
A
B
B
B
A
C
A
C
A
Peripheral
A
A
A
C
A
A
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Table 39-3. I/O Lines
USART3
USART3
USART3
USART3
USART3
CTS3
RTS3
RXD3
SCK3
TXD3
PC25
PC24
PC23
PC26
PC22
B
B
B
B
B
39.6.2 Power Management
The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management
Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off.
Configuring the USART does not require the USART clock to be enabled.
39.6.3 Interrupt
The USART interrupt line is connected on one of the internal sources of the Interrupt Controller. using the USART interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode.
Peripheral IDs
Instance
USART0
USART1
USART2
USART3
6
7
ID
5
8
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39.7 Functional Description
The USART is capable of managing several types of serial synchronous or asynchronous communications.
It supports the following communication modes:
5-bit to 9-bit full-duplex asynchronous serial communication
MSB-first or LSB-first
1, 1.5 or 2 stop bits
Parity even, odd, marked, space or none
By-8 or by-16 over-sampling receiver frequency
Optional hardware handshaking
Optional break management
Optional multidrop serial communication
High-speed 5- to 9-bit full-duplex synchronous serial communication
MSB-first or LSB-first
1 or 2 stop bits
Parity even, odd, marked, space or none
By-8 or by-16 over-sampling frequency
Optional hardware handshaking
Optional break management
Optional multidrop serial communication
RS485 with driver control signal
ISO7816, T0 or T1 protocols for interfacing with smart cards
NACK handling, error counter with repetition and iteration limit
InfraRed IrDA Modulation and Demodulation
SPI Mode
Master or Slave
Serial Clock Programmable Phase and Polarity
SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
LIN Mode
Compliant with LIN 1.3 and LIN 2.0 specifications
Master or Slave
Processing of frames with up to 256 data bytes
Response Data length can be configurable or defined automatically by the Identifier
Self synchronization in Slave node configuration
Automatic processing and verification of the “Synch Break” and the “Synch Field”
The “Synch Break” is detected even if it is partially superimposed with a data byte
Automatic Identifier parity calculation/sending and verification
Parity sending and verification can be disabled
Automatic Checksum calculation/sending and verification
Checksum sending and verification can be disabled
Support both “Classic” and “Enhanced” checksum types
Full LIN error checking and reporting
Frame Slot Mode: the Master allocates slots to the scheduled frames automatically.
Generation of the Wakeup signal
Test modes
Remote loopback, local loopback, automatic echo
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39.7.1 Baud Rate Generator
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between:
The Master Clock MCK
A division of the Master Clock, the divider being product dependent, but generally set to 8
The external clock, available on the SCK pin
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate
Generator Register (US_BRGR). If CD is programmed to 0, the Baud Rate Generator does not generate any clock. If CD is programmed to 1, the divider is bypassed and becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK in USART mode, or 6 times lower in SPI mode.
Figure 39-3. Baud Rate Generator
USCLKS
CD
CD MCK
MCK/DIV
SCK
Reserved
2
3
0
1
16-bit Counter
0
>1
1
0
0
1
OVER
FIDI
Sampling
Divider
0
SCK
SYNC
Baud Rate
Clock
1
SYNC
USCLKS = 3
Sampling
Clock
39.7.1.1 Baud Rate in Asynchronous Mode
If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock.
The following formula performs the calculation of the Baud Rate.
Baudrate =
( ( – Over ) CD )
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed to 1.
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Baud Rate Calculation Example
shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error.
Table 39-4. Baud Rate Example (OVER = 0)
Source Clock
MHz
Expected Baud
Rate
Bit/s
Calculation Result
3 686 400
4 915 200
5 000 000
7 372 800
8 000 000
12 000 000
38 400
38 400
38 400
38 400
38 400
38 400
6.00
8.00
8.14
12.00
13.02
19.53
12 288 000
14 318 180
14 745 600
18 432 000
24 000 000
24 576 000
25 000 000
32 000 000
32 768 000
33 000 000
40 000 000
50 000 000
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
20.00
23.30
24.00
30.00
39.06
40.00
40.69
52.08
53.33
53.71
65.10
81.38
CD
39
40
40
52
20
23
24
30
53
54
65
81
12
13
20
6
8
8
Actual Baud Rate
Bit/s
38 400.00
38 400.00
39 062.50
38 400.00
38 461.54
37 500.00
38 400.00
38 908.10
38 400.00
38 400.00
38 461.54
38 400.00
38 109.76
38 461.54
38 641.51
38 194.44
38 461.54
38 580.25
Error
0.00%
1.31%
0.00%
0.00%
0.16%
0.00%
0.76%
0.16%
0.00%
0.00%
1.70%
0.00%
0.16%
2.40%
0.63%
0.54%
0.16%
0.47%
The baud rate is calculated with the following formula:
BaudRate =
⁄ × 16
The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%.
Error = 1 –
ExpectedBaudRate
ActualBaudRate
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39.7.1.2 Fractional Baud Rate in Asynchronous Mode
The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register
(US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula:
Baudrate
= -----------------------------------------------------------------
(
SelectedClock
– Over )
CD +
8
The modified architecture is presented below:
Figure 39-4. Fractional Baud Rate Generator
FP
U S CLK S
CD
Mod u l us
Control
FP
MCK
MCK/DIV
S CK
Re s erved
0
1
2
3
16b it Co u nter
Glitch-free
Logic
0
CD
>1
1
0
0
FIDI
OVER
Sa mpling
Divider
0
S CK
S YNC
1
B au d R a te
Clock
1
S YNC
U S CLK S = 3
Sa mpling
Clock
39.7.1.3 Baud Rate in Synchronous Mode or SPI Mode
If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in
US_BRGR.
BaudRate =
CD
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the
USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. In synchronous mode master (USCLKS = 0 or 1, CLK0 set to 1), the receive part limits the SCK maximum frequency to MCK/4.5 in USART mode, or MCK/6 in SPI mode.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the
Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd.
39.7.1.4 Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
B =
Di
Fi
× f
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where:
B is the bit rate
Di is the bit-rate adjustment factor
Fi is the clock frequency division factor f is the ISO7816 clock frequency (Hz)
Di is a binary value encoded on a 4-bit field, named DI, as represented in
Table 39-5. Binary and Decimal Values for Di
DI field 0001 0010
Di (decimal) 1 2
0011
4
0100
8
0101
16
0110
32
Fi is a binary value encoded on a 4-bit field, named FI, as represented in
Table 39-6. Binary and Decimal Values for Fi
FI field 0000 0001 0010 0011
Fi (decimal) 372 372 558 744
0100
1116
0101
1488
0110
1860
1001
512
1010
768
1000
12
1001
20
1011
1024
1100
1536
1101
2048
shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock.
Table 39-7. Possible Values for the Fi/Di Ratio
Fi/Di 372 558 774 1116
1
2
372
186
558
279
744
372
1116
558
16
32
4
8
12
20
93
46.5
23.25
11.62
31
18.6
139.5
69.75
34.87
17.43
46.5
27.9
186
93
46.5
23.25
62
37.2
279
139.5
69.75
34.87
93
55.8
1488
1488
744
372
186
93
46.5
124
74.4
1806
1860
930
465
232.5
116.2
58.13
155
93
512
512
256
128
64
32
16
42.66
25.6
768
768
384
192
96
48
24
64
38.4
1024
1024
512
256
128
64
32
85.33
51.2
1536
1536
768
384
192
96
48
128
76.8
2048
2048
1024
512
256
128
64
170.6
102.4
If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in
US_MR.
This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value.
The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1).
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Figure 39-5. Elementary Time Unit (ETU)
FI_DI_RATIO
ISO7816 Clock Cycles
ISO7816 Clock on SCK
ISO7816 I/O Line on TXD
1 ETU
39.7.2 Receiver and Transmitter Control
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register
(US_CR). However, the receiver registers can be programmed before the receiver clock is enabled.
After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR).
However, the transmitter registers can be programmed before being enabled.
The Receiver and the Transmitter can be enabled together or independently.
At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped.
The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in
US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally.
39.7.3 Synchronous and Asynchronous Modes
39.7.3.1 Transmitter Operations
The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1).
One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in
US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written to 1, the most significant bit is sent first. If written to 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only.
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Figure 39-6. Character Transmit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock
TXD
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7 Parity
Bit
Stop
Bit
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and
TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and
US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost.
Figure 39-7. Transmitter Status
Baud Rate
Clock
TXD
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity Stop Start
Bit Bit Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity Stop
Bit Bit
Write
US_THR
TXRDY
TXEMPTY
39.7.3.2 Manchester Encoder
When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase
Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of
Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder.
Figure 39-8 illustrates this coding scheme.
Figure 39-8. NRZ to Manchester Encoding
1 NRZ encoded data
Manchester encoded data
Txd
0 1 1 0 0 0 1
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The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE,
ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register, the field TX_PL is used to configure the preamble length.
illustrates and defines the valid patterns. To improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the US_MAN register. If the TX_MPOL field is set to zero
(default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition.
Figure 39-9. Preamble Patterns, Default Polarity Assumed
Manchester encoded data
Txd
SFD DATA
8 bit width "ALL_ONE" Preamble
Manchester encoded data
Txd
SFD DATA
8 bit width "ALL_ZERO" Preamble
Manchester encoded data
Txd
SFD
DATA
8 bit width "ZERO_ONE" Preamble
Manchester encoded data
Txd
SFD DATA
8 bit width "ONE_ZERO" Preamble
A start frame delimiter is to be configured using the ONEBIT field in the US_MR register. It consists of a user-defined pattern that indicates the beginning of a valid data.
illustrates these patterns. If the start frame delimiter, also known as the start bit, is one bit, (ONEBIT to 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync
(ONEBIT to 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the MODSYNC field in the
US_MR register is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the MODSYNC field can be immediately updated with a modified character located in memory.
To enable this mode, VAR_SYNC field in US_MR register must be set to 1. In this case, the MODSYNC field in US_MR is bypassed and the sync configuration is held in the TXSYNH in the US_THR register. The USART character format is modified and includes sync information.
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Figure 39-10. Start Frame Delimiter
Preamble Length is set to 0
Manchester encoded data
Txd
SFD
DATA
One bit start frame delimiter
SFD
Manchester encoded data
Txd
DATA
Command Sync start frame delimiter
Manchester encoded data
Txd
SFD
DATA
Data Sync start frame delimiter
Drift Compensation
Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift.
To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the
RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken.
Figure 39-11. Bit Resynchronization
Oversampling
16x Clock
RXD
Sampling point
Synchro.
Error
Synchro.
Jump
Expected edge
Tolerance Sync
Jump
Synchro.
Error
39.7.3.3 Asynchronous Receiver
If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line.
The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register
(US_MR).
The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16, (OVER to 0), a start is detected at the eighth sample to 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER to 1), a start bit is detected at the fourth sample to 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e.
respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no
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effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit.
mode.
Figure 39-12. Asynchronous Start Detection
Baud Rate
Clock
Sampling
Clock (x16)
RXD
Sampling
1 2 3 4 5 6 7 8
Start
Detection
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D0
Sampling
RXD
Sampling
1 2 3 4 5 6 7 0 1 2 3 4
Start
Rejection
Figure 39-13. Asynchronous Character Reception
Example: 8-bit, Parity Enabled
Baud Rate
Clock
RXD
Start
Detection
16 samples
16 samples
16 samples
16 samples
16 samples
16 samples
16 samples
16 samples
16 samples
16 samples
D0 D1 D2 D3 D4 D5 D6 D7 Parity
Bit
Stop
Bit
39.7.3.4 Manchester Decoder
When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data.
An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use
RX_PL in US_MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in
US_MAN register. Depending on the desired application the preamble pattern matching is to be defined via the RX_PP field in US_MAN. See
for available preamble patterns.
Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If
rejection mechanism applies.
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In order to increase the compatibility the RXIDLV bit in the US_MAN register allows to inform the USART block of the Rx line idle state value (Rx line undriven), it can be either level one (pull-up) or level zero (pull-down). By default this bit is set to one (Rx line is at level 1 if undriven).
Figure 39-14. Asynchronous Start Bit Detection
Sampling
Clock
(16 x)
Manchester encoded data
Txd
Start
Detection
1 2 3 4
The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver resynchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time.
If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into
NRZ data and passed to USART for processing.
illustrates Manchester pattern mismatch. When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a lack of transition in the middle of a bit cell. In this case, MANE flag in US_CSR register is raised. It is cleared by writing
the Control Register (US_CR) with the RSTSTA bit to 1. See Figure 39-16
for an example of Manchester error detection during data phase.
Figure 39-15. Preamble Pattern Mismatch
Preamble Mismatch
Manchester coding error
Preamble Mismatch invalid pattern
Manchester encoded data
Txd
SFD DATA
Preamble Length is set to 8
Figure 39-16. Manchester Error Flag
Preamble Length is set to 4
SFD
Elementary character bit time
Manchester encoded data
Txd
Entering USART character area sampling points
Preamble subpacket and Start Frame Delimiter were successfully decoded
Manchester
Coding Error detected
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When the start frame delimiter is a sync pattern (ONEBIT field to 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register.
As the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-to-one transition.
39.7.3.5 Radio Interface: Manchester Encoded USART Application
This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART.
These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes.
The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the configuration in
.
Figure 39-17. Manchester Encoded Characters RF Transmission
Fup frequency Carrier
Upstream
Emitter
Fdown frequency Carrier
Downstream
Receiver
ASK/FSK
Upstream Receiver
LNA
VCO
RF filter
Demod control bi-dir line
ASK/FSK downstream transmitter
PA
RF filter
Mod
VCO control
Serial
Configuration
Interface
Manchester decoder
Manchester encoder
USART
Receiver
USART
Emitter
The USART module is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See
for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See
From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver switches to receiving mode. The demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration.
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Figure 39-18. ASK Modulator Output
1
NRZ stream
Manchester encoded data default polarity unipolar output
ASK Modulator
Output
Uptstream Frequency F0
Txd
Figure 39-19. FSK Modulator Output
1
NRZ stream
Manchester encoded data default polarity unipolar output
FSK Modulator
Output
Uptstream Frequencies
[F0, F0+offset]
Txd
0
0
0
0 1
1
39.7.3.6 Synchronous Receiver
In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.
Figure 39-20 illustrates a character reception in synchronous mode.
Figure 39-20. Synchronous Mode Character Reception
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock
RXD
Sampling
Start D0 D1 D2 D3 D4 D5 D6 D7
Parity Bit
Stop Bit
39.7.3.7 Receiver Operations
When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
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Figure 39-21. Receiver Status
Baud Rate
Clock
RXD
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity Stop Start
Bit Bit Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity Stop
Bit Bit
RSTSTA = 1
Write
US_CR
Read
US_RHR
RXRDY
OVRE
39.7.3.8 Parity
The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see
. Even and odd parity bit generation and error detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit to 1 if a number of 1s in the character data bit is even, and to 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit to 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 0. If the space parity is used, the parity generator of the transmitter drives the parity bit to 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error.
configuration of the USART. Because there are two bits to 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even.
Table 39-8. Parity Bit Examples
Character
A
Hexa
0x41
A
A
A
A
0x41
0x41
0x41
0x41
Binary
0100 0001
0100 0001
0100 0001
0100 0001
0100 0001
Parity Bit
1
0
1
0
None
Parity Mode
Odd
Even
Mark
Space
None
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR).
The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit to 1.
the parity bit status setting and clearing.
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Figure 39-22. Parity Error
Baud Rate
Clock
RXD
Write
US_CR
PARE
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Bad
Parity
Stop
Bit
Bit
RXRDY
RSTSTA = 1
39.7.3.9 Multidrop Mode
If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop
Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit to
0 and addresses are transmitted with the parity bit to 1.
If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit to 1.
To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA to 1.
The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command
SENDA is transmitted normally with the parity to 0.
39.7.3.10 Transmitter Timeguard
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed to zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits.
As illustrated in
Figure 39-23 , the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a
timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains to 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted.
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Figure 39-23. Timeguard Operations
TG = 4 TG = 4
Baud Rate
Clock
TXD
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity Stop
Bit Bit
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity Stop
Bit Bit
Write
US_THR
TXRDY
TXEMPTY
indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate.
Table 39-9. Maximum Timeguard Length Depending on Baud Rate
Baud Rate
Bit/sec
Bit time
µs
1 200
9 600
833
104
14400 69.4
19200 52.1
28800
33400
56000
57600
115200
34.7
29.9
17.9
17.4
8.7
Timeguard ms
212.50
26.56
17.71
13.28
8.85
7.63
4.55
4.43
2.21
39.7.3.11 Receiver Time-out
The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the
RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame.
The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the
Receiver Time-out Register (US_RTOR). If the TO field is programmed to 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains to 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises.
Then, the user can either:
Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit to 1. In this case, the idle state on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received.
Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit to 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.
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If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected.
If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.
Figure 39-24 shows the block diagram of the Receiver Time-out feature.
Figure 39-24. Receiver Time-out Block Diagram
Baud Rate
Clock
TO
16-bit
Value
STTTO
1 D Q Clock 16-bit Time-out
Counter
= TIMEOUT
Load 0
Clear
Character
Received
RETTO
Table 39-10 gives the maximum time-out period for some standard baud rates.
Table 39-10. Maximum Time-out Period
Baud Rate bit/sec
600
1 200
2 400
4 800
9 600
14400
19200
28800
33400
56000
57600
200000
18
17
5
69
52
35
30
Bit Time
µs
1 667
833
417
208
104
4 551
3 413
2 276
1 962
1 170
1 138
328
Time-out ms
109 225
54 613
27 306
13 653
6 827
39.7.3.12 Framing Error
The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized.
A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit to 1.
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Figure 39-25. Framing Error Status
Baud Rate
Clock
RXD
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity Stop
Bit Bit
Write
US_CR
FRAME
RXRDY
RSTSTA = 1
39.7.3.13 Transmit Break
The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits to 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed.
A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit to 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the
TXD line is held low.
Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed.
The break condition is removed by writing US_CR with the STPBRK bit to 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes.
The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is to 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed.
Writing US_CR with both STTBRK and STPBRK bits to 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored.
After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period.
After holding the TXD line for this period, the transmitter resumes normal operations.
illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line.
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Figure 39-26. Break Transmission
Baud Rate
Clock
TXD
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity Stop
Bit Bit
STTBRK = 1
Write
US_CR
TXRDY
TXEMPTY
Break Transmission
STPBRK = 1
End of Break
39.7.3.14 Receive Break
The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data to 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the
Control Register (US_CR) with the bit RSTSTA to 1.
An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit.
39.7.3.15 Hardware Handshaking
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with
the remote device, as shown in Figure 39-27 .
Figure 39-27. Connection with a Remote Device for Hardware Handshaking
USART
TXD
RXD
CTS
RTS
Remote
Device
RXD
TXD
RTS
CTS
Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode
Register (US_MR) to the value 0x2.
The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the DMAC channel for reception. The transmitter can handle hardware handshaking in any case.
transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls.
Figure 39-28. Transmitter Behavior when Operating with Hardware Handshaking
CTS
TXD
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39.7.4 ISO7816 Mode
The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and
Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the
ISO7816 specification are supported.
Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1.
39.7.4.1 ISO7816 Mode Overview
The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of
the clock provided to the remote device (see “Baud Rate Generator” on page 767
).
The USART connects to a smart card as shown in
Figure 39-29 . The TXD line becomes bidirectional and the Baud Rate
Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver.
The USART is considered as the master of the communication as it generates the clock.
Figure 39-29. Connection of a Smart Card to the USART
USART
SCK
CLK
Smart
Card
I/O
TXD
When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields.
MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode.
Refer to
“USART Mode Register” on page 815 and
“PAR: Parity Type” on page 816
.
The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results.
The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the
I/O line at their negative value.
39.7.4.2 Protocol T = 0
In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time.
If no parity error is detected, the I/O line remains to 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in
.
. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time.
When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding
Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error.
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Figure 39-30. T = 0 Protocol without Parity Error
Baud Rate
Clock
RXD
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7 Parity
Bit
Guard
Time 1
Guard
Time 2
Next
Start
Bit
Figure 39-31. T = 0 Protocol with Parity Error
Baud Rate
Clock
I/O
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Error
Parity
Bit
Guard
Time 1
Guard
Time 2
Start
Bit
D0
Repetition
D1
Receive Error Counter
The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register.
The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field.
Receive NACK Inhibit
The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode
Register (US_MR). If INACK is to 1, no error signal is driven on the I/O line even if a parity bit is detected.
Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred and the RXRDY bit does rise.
Transmit Character Repetition
When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in
MAX_ITERATION.
When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register
(US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared.
The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit to 1.
Disable Successive Receive NACK
The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set.
39.7.4.3 Protocol T = 1
When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit.
The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the
Channel Status Register (US_CSR).
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39.7.5 IrDA Mode
The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the
The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s.
The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8.
The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated.
Figure 39-32. Connection to IrDA Transceivers
Receiver
USART
Demodulator
RXD RX
IrDA
Transceivers
TX
Transmitter Modulator
TXD
The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed.
To receive IrDA signals, the following needs to be done:
Disable TX and Enable RX
Configure the TXD pin as PIO and set it as an output to 0 (to avoid LED emission). Disable the internal pull-up
(better for power consumption).
Receive data
39.7.5.1 IrDA Modulation
For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in
Table 39-11. IrDA Pulse Duration
Baud Rate
2.4 Kb/s
9.6 Kb/s
19.2 Kb/s
38.4 Kb/s
57.6 Kb/s
115.2 Kb/s
Pulse Duration (3/16)
78.13 µs
19.53 µs
9.77 µs
4.88 µs
3.26 µs
1.63 µs
Figure 39-33 shows an example of character transmission.
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Figure 39-33. IrDA Modulation
Transmitter
Output
TXD
Start
Bit
0 1 0 1
Data Bits
0 0 1 1 0
Stop
Bit
1
Bit Period
3
16
Bit Period
39.7.5.2 IrDA Baud Rate
gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ± 1.87% must be met.
Table 39-12. IrDA Baud Rate Error
Peripheral Clock
3 686 400
Baud Rate
115 200
20 000 000
32 768 000
40 000 000
3 686 400
115 200
115 200
115 200
57 600
20 000 000
32 768 000
40 000 000
3 686 400
20 000 000
32 768 000
40 000 000
3 686 400
57 600
57 600
57 600
38 400
38 400
38 400
38 400
19 200
20 000 000
32 768 000
40 000 000
3 686 400
20 000 000
32 768 000
40 000 000
3 686 400
20 000 000
32 768 000
19 200
19 200
19 200
9 600
9 600
9 600
9 600
2 400
2 400
2 400
65
12
65
107
43
6
33
53
22
4
22
36
CD
2
11
18
260
96
521
853
130
24
130
213
Baud Rate Error
0.00%
1.38%
1.25%
1.38%
0.00%
1.38%
1.25%
0.93%
0.00%
1.38%
0.63%
0.16%
0.00%
0.16%
0.31%
0.16%
0.00%
0.16%
0.16%
0.16%
0.00%
0.03%
0.04%
4.88
9.77
9.77
9.77
3.26
4.88
4.88
4.88
Pulse Time
1.63
1.63
1.63
1.63
3.26
3.26
3.26
9.77
19.53
19.53
19.53
19.53
78.13
78.13
78.13
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39.7.5.3 IrDA Demodulator
The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the
Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time.
Figure 39-34 illustrates the operations of the IrDA demodulator.
Figure 39-34. IrDA Demodulator Operations
MCK
RXD
Counter
Value 6 5 4 3 2 6
Pulse
Rejected
6 5 4 3 2
Pulse
Accepted
1 0
Receiver
Input
As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly.
39.7.6 RS485 Mode
The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in
.
Figure 39-35. Typical Connection to a RS485 Bus
USART
RXD
TXD
RTS
Differential
Bus
The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value
0x1.
The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion.
Figure 39-36 gives an example of the
RTS waveform during a character transmission when the timeguard is enabled.
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Figure 39-36. Example of RTS Drive with Timeguard
Baud Rate
Clock
TXD
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity Stop
Bit Bit
Write
US_THR
TXRDY
TXEMPTY
RTS
TG = 4
39.7.7 SPI Mode
The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turns being masters and one master may simultaneously shift data into multiple slaves. (Multiple Master Protocol is the opposite of Single Master Protocol, where one CPU is always the master while all of the others are always slaves.) However, only one slave may drive its output to write data back to the master at any given time.
A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can address only one SPI Slave because it can generate only one NSS signal.
The SPI system consists of two data lines and two control lines:
Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input of the slave.
Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master.
Serial Clock (SCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is transmitted.
Slave Select (NSS): This control line allows the master to select or deselect the slave.
39.7.7.1 Modes of Operation
The USART can operate in SPI Master Mode or in SPI Slave Mode.
Operation in SPI Master Mode is programmed by writing to 0xE the USART_MODE field in the Mode Register. In this case the SPI lines must be connected as described below:
The MOSI line is driven by the output pin TXD
The MISO line drives the input pin RXD
The SCK line is driven by the output pin SCK
The NSS line is driven by the output pin RTS
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Operation in SPI Slave Mode is programmed by writing to 0xF the USART_MODE field in the Mode Register. In this case the SPI lines must be connected as described below:
The MOSI line drives the input pin RXD
The MISO line is driven by the output pin TXD
The SCK line drives the input pin SCK
The NSS line drives the input pin CTS
In order to avoid unpredicted behavior, any change of the SPI Mode must be followed by a software reset of the
).
39.7.7.2 Baud Rate
In SPI Mode, the baudrate generator operates in the same way as in USART synchronous mode:
Synchronous Mode or SPI Mode” on page 769.
However, there are some restrictions:
In SPI Master Mode:
The external clock SCK must not be selected (USCLKS ≠ 0x3), and the bit CLKO must be set to “1” in the Mode
Register (US_MR), in order to generate correctly the serial clock on the SCK pin.
To obtain correct behavior of the receiver and the transmitter, the value programmed in CD must be superior or equal to 6.
If the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even to ensure a 50:50 mark/space ratio on the SCK pin, this value can be odd if the internal clock is selected (MCK).
In SPI Slave Mode:
The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the Mode Register
(US_MR). Likewise, the value written in US_BRGR has no effect, because the clock is provided directly by the signal on the USART SCK pin.
To obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at least
6 times lower than the system clock.
39.7.7.3 Data Transfer
Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and
CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). The 9 bits are selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI Mode
(Master or Slave).
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Mode Register. The clock phase is programmed with the CPHA bit. These two parameters determine the edges of the clock signal upon which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave.
Table 39-13. SPI Bus Protocol Mode
SPI Bus Protocol Mode
0
1
2
3
CPOL
0
0
1
1
CPHA
1
0
1
0
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Figure 39-37. SPI Transfer Format (CPHA=1, 8 bits per transfer)
SCK cycle (for reference) 1 2 3 4
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
SPI Master ->TXD
SPI Slave -> RXD
MISO
SPI Master ->RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
MSB 6
MSB 6
5
5
4
4
5
3
3
Figure 39-38. SPI Transfer Format (CPHA=0, 8 bits per transfer)
1 2 3
SCK cycle (for reference)
SCK
(CPOL = 0)
4
7 8
2 1 LSB
2 1 LSB
5 6 7 8
SCK
(CPOL = 1)
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MSB 6 5
MISO
SPI Master -> RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
MSB 6 5
39.7.7.4 Receiver and Transmitter Control
See “Receiver and Transmitter Control” on page 771.
4
4
3 2 1 LSB
3 2 1 LSB
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39.7.7.5 Character Transmission
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and
TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and
US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost.
If the USART is in SPI Slave Mode and if a character must be sent while the Transmit Holding Register (US_THR) is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
In SPI Master Mode, the slave select line (NSS) is asserted at low level 1 Tbit (Time bit) before the transmission of the
MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always released between each character transmission and a minimum delay of 3 Tbits always inserted. However, in order to address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can be forced at low level by writing the Control Register (US_CR) with the RTSEN bit to 1. The slave select line (NSS) can be released at high level only by writing the Control Register (US_CR) with the RTSDIS bit to 1 (for example, when all data have been transferred to the slave device).
In SPI Slave Mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a character transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit.
39.7.7.6 Character Reception
When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
To ensure correct behavior of the receiver in SPI Slave Mode, the master device sending the frame must ensure a minimum delay of 1 Tbit between each character transmission. The receiver does not require a falling edge of the slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit.
39.7.7.7 Receiver Timeout
Because the receiver baudrate clock is active only during data transfers in SPI Mode, a receiver timeout is impossible in this mode, whatever the Time-out value is (field TO) in the Time-out Register (US_RTOR).
39.7.8 LIN Mode
The LIN Mode provides Master node and Slave node connectivity on a LIN bus.
The LIN (Local Interconnect Network) is a serial communication protocol which efficiently supports the control of mechatronic nodes in distributed automotive applications.
The main properties of the LIN bus are:
Single Master/Multiple Slaves concept
Low cost silicon implementation based on common UART/SCI interface hardware, an equivalent in software, or as a pure state machine
Self synchronization without quartz or ceramic resonator in the slave nodes
Deterministic signal transmission
Low cost single-wire implementation
Speed up to 20 kbit/s
LIN provides cost efficient bus communication where the bandwidth and versatility of CAN are not required.
The LIN Mode enables processing LIN frames with a minimum of action from the microprocessor.
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39.7.8.1 Modes of Operation
The USART can act either as a LIN Master node or as a LIN Slave node.
The node configuration is chosen by setting the USART_MODE field in the USART Mode register (US_MR):
LIN Master Node (USART_MODE=0xA)
LIN Slave Node (USART_MODE=0xB)
In order to avoid unpredicted behavior, any change of the LIN node configuration must be followed by a software reset of the transmitter and of the receiver (except the initial node configuration after a hardware reset). (See
39.7.8.2 Baud Rate Configuration
See “Baud Rate in Asynchronous Mode” on page 767.
The baud rate is configured in the Baud Rate Generator register (US_BRGR).
39.7.8.3 Receiver and Transmitter Control
See “Receiver and Transmitter Control” on page 771.
39.7.8.4 Character Transmission
See “Transmitter Operations” on page 771.
39.7.8.5 Character Reception
See “Receiver Operations” on page 778.
39.7.8.6 Header Transmission (Master Node Configuration)
All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field.
So in Master node configuration, the frame handling starts with the sending of the header.
The header is transmitted as soon as the identifier is written in the LIN Identifier register (US_LINIR). At this moment the flag TXRDY falls.
The Break Field, the Synch Field and the Identifier Field are sent automatically one after the other.
The Break Field consists of 13 dominant bits and 1 recessive bit, the Synch Field is the character 0x55 and the Identifier corresponds to the character written in the LIN Identifier Register (US_LINIR). The Identifier parity bits can be automatically computed and sent (see
The flag TXRDY rises when the identifier character is transferred into the Shift Register of the transmitter.
As soon as the Synch Break Field is transmitted, the flag LINBK in the Channel Status register (US_CSR) is set to 1.
Likewise, as soon as the Identifier Field is sent, the flag LINID in the Channel Status register (US_CSR) is set to 1. These flags are reset by writing the bit RSTSTA to 1 in the Control register (US_CR).
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Figure 39-39. Header Transmission
Baud Rate
Clock
TXD
Break Field
13 dominant bits (at 0)
Write
US_LINIR
US_LINIR ID
TXRDY
LINBK in US_CSR
LINID in US_CSR
Write RSTSTA=1 in US_CR
Break
Delimiter
1 recessive bit
(at 1)
Start
Bit
1 0 1 0 1 0
Synch Byte = 0x55
1 0
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Stop
Bit
39.7.8.7 Header Reception (Slave Node Configuration)
All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field.
In Slave node configuration, the frame handling starts with the reception of the header.
The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break Field. As long as a Break Field has not been detected, the USART stays idle and the received data are not taken in account.
When a Break Field has been detected, the flag LINBK in the Channel Status register (US_CSR) is set to 1 and the
USART expects the Synch Field character to be 0x55. This field is used to update the actual baud rate in order to stay
synchronized (see Section 39.7.8.8
). If the received Synch character is not 0x55, an Inconsistent Synch Field error is
generated (see
After receiving the Synch Field, the USART expects to receive the Identifier Field.
When the Identifier Field has been received, the flag LINID in the Channel Status register (US_CSR) is set to 1. At this moment the field IDCHR in the LIN Identifier register (US_LINIR) is updated with the received character. The Identifier
parity bits can be automatically computed and checked (see Section 39.7.8.9
).
The flags LINID and LINBK are reset by writing the bit RSTSTA to 1 in the Control register (US_CR).
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Figure 39-40. Header Reception
Baud Rate
Clock
RXD
Break Field
13 dominant bits (at 0)
Break
Delimiter
1 recessive bit
(at 1)
Start
Bit
1 0 1 0 1 0
Synch Byte = 0x55
1 0
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Stop
Bit
LINBK
LINID
US_LINIR
Write RSTSTA=1 in US_CR
39.7.8.8 Slave Node Synchronization
The synchronization is done only in Slave node configuration. The procedure is based on time measurement between falling edges of the Synch Field. The falling edges are available in distances of 2, 4, 6 and 8 bit times.
Figure 39-41. Synch Field
2 Tbit
Synch Field
8 Tbit
2 Tbit 2 Tbit 2 Tbit
Start bit
Stop bit
The time measurement is made by a 19-bit counter clocked by the sampling clock (see
When the start bit of the Synch Field is detected, the counter is reset. Then during the next 8 Tbits of the Synch Field, the counter is incremented. At the end of these 8 Tbits, the counter is stopped. At this moment, the 16 most significant bits of the counter (value divided by 8) give the new clock divider (LINCD) and the 3 least significant bits of this value (the remainder) give the new fractional part (LINFP).
When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are updated in the Baud
Rate Generator register (US_BRGR).
If it appears that the sampled Synch character is not equal to 0x55, then the error flag LINISFE in the Channel Status register (US_CSR) is set to 1. It is reset by writing bit RSTSTA to 1 in the Control register (US_CR).
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Figure 39-42. Slave Node Synchronization
Baud Rate
Clock
RXD
Break Field
13 dominant bits (at 0)
LINIDRX
Synchro Counter
Break
Delimiter
1 recessive bit
(at 1)
Start
Bit
1 0 1 0 1 0
Synch Byte = 0x55
1 0
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Stop
Bit
Reset
000_0011_0001_0110_1101
US_BRGR
Clcok Divider (CD)
US_BRGR
Fractional Part (FP)
US_LINBRR
Clcok Divider (CD)
US_LINBRR
Fractional Part (FP)
Initial CD
Initial FP
Initial CD
Initial FP
0000_0110_0010_1101
101
The accuracy of the synchronization depends on several parameters:
The nominal clock frequency (F
Nom
) (the theoretical slave node clock frequency)
The Baud Rate
The oversampling (Over=0 => 16X or Over=0 => 8X)
The following formula is used to compute the deviation of the slave bit rate relative to the master bit rate after synchronization (F
SLAVE
is the real slave node clock frequency).
Baudrate_deviation =
Baudrate_deviation =
100
×
[ × 8 × ( 2 –
8
Over
×
F
) β
SLAVE
] × Baudrate
%
100 ×
[ ×
8
8
×
× (
F
2 – Over
---------------------------------------
100
) β ] ×
Baudrate xF
Nom
%
– 0.5
≤ ≤ +0.5 -1 β +1
F
TOL_UNSYNCH
is the deviation of the real slave node clock from the nominal clock frequency. The LIN Standard imposes that it must not exceed ± 15%. The LIN Standard imposes also that for communication between two nodes, their bit rate must not differ by more than ±2%. This means that the Baudrate_deviation must not exceed ±1%.
It follows from that, a minimum value for the nominal clock frequency:
F
NOM
( min
)
=
100
×
[ 0.5
× 8 ×
8
2
×
– Over )
– 15
1
100
+
+ 1
×
] × Baudrate
1 %
Hz
Examples:
Baudrate = 20 kbit/s, Over=0 (Oversampling 16X) => F
Nom
(min) = 2.64 MHz
Baudrate = 20 kbit/s, Over=1 (Oversampling 8X) => F
Nom
(min) = 1.47 MHz
Baudrate = 1 kbit/s, Over=0 (Oversampling 16X) => F
Nom
(min) = 132 kHz
Baudrate = 1 kbit/s, Over=1 (Oversampling 8X) => F
Nom
(min) = 74 kHz
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39.7.8.9 Identifier Parity
A protected identifier consists of two sub-fields; the identifier and the identifier parity. Bits 0 to 5 are assigned to the identifier and bits 6 and 7 are assigned to the parity.
The USART interface can generate/check these parity bits, but this feature can also be disabled. The user can choose between two modes by the PARDIS bit of the LIN Mode register (US_LINMR):
PARDIS = 0:
During header transmission, the parity bits are computed and sent with the 6 least significant bits of the IDCHR field of the LIN Identifier register (US_LINIR). The bits 6 and 7 of this register are discarded.
During header reception, the parity bits of the identifier are checked. If the parity bits are wrong, an Identifier Parity error
). Only the 6 least significant bits of the IDCHR field are updated with the received Identifier.
The bits 6 and 7 are stuck to 0.
PARDIS = 1:
During header transmission, all the bits of the IDCHR field of the LIN Identifier register (US_LINIR) are sent on the bus.
During header reception, all the bits of the IDCHR field are updated with the received Identifier.
39.7.8.10 Node Action
In function of the identifier, the node is concerned, or not, by the LIN response. Consequently, after sending or receiving the identifier, the USART must be configured. There are three possible configurations:
PUBLISH: the node sends the response.
SUBSCRIBE: the node receives the response.
IGNORE: the node is not concerned by the response, it does not send and does not receive the response.
).
Example: a LIN cluster that contains a Master and two Slaves:
Data transfer from the Master to the Slave 1 and to the Slave 2:
NACT(Master)=PUBLISH
NACT(Slave1)=SUBSCRIBE
NACT(Slave2)=SUBSCRIBE
Data transfer from the Master to the Slave 1 only:
NACT(Master)=PUBLISH
NACT(Slave1)=SUBSCRIBE
NACT(Slave2)=IGNORE
Data transfer from the Slave 1 to the Master:
NACT(Master)=SUBSCRIBE
NACT(Slave1)=PUBLISH
NACT(Slave2)=IGNORE
Data transfer from the Slave1 to the Slave2:
NACT(Master)=IGNORE
NACT(Slave1)=PUBLISH
NACT(Slave2)=SUBSCRIBE
Data transfer from the Slave2 to the Master and to the Slave1:
NACT(Master)=SUBSCRIBE
NACT(Slave1)=SUBSCRIBE
NACT(Slave2)=PUBLISH
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39.7.8.11 Response Data Length
The LIN response data length is the number of data fields (bytes) of the response excluding the checksum.
The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier
(compatibility to LIN Specification 1.1). The user can choose between these two modes by the DLM bit of the LIN Mode register (US_LINMR):
DLM = 0: the response data length is configured by the user via the DLC field of the LIN Mode register
(US_LINMR). The response data length is equal to (DLC + 1) bytes. DLC can be programmed from 0 to 255, so the response can contain from 1 data byte up to 256 data bytes.
DLM = 1: the response data length is defined by the Identifier (IDCHR in US_LINIR) according to the table below.
The DLC field of the LIN Mode register (US_LINMR) is discarded. The response can contain 2 or 4 or 8 data bytes.
Table 39-14. Response Data Length if DLM = 1
IDCHR[5]
0
0
IDCHR[4]
0
1
1
1
0
1
Response Data Length [bytes]
2
2
4
8
Figure 39-43. Response Data Length
User configuration: 1 - 256 data fields (DLC+1)
Identifier configuration: 2/4/8 data fields
Sync
Break
Sync
Field
Identifier
Field
Data
Field
Data
Field
Data
Field
Data
Field
Checksum
Field
39.7.8.12 Checksum
The last field of a frame is the checksum. The checksum contains the inverted 8- bit sum with carry, over all data bytes or all data bytes and the protected identifier. Checksum calculation over the data bytes only is called classic checksum and it is used for communication with LIN 1.3 slaves. Checksum calculation over the data bytes and the protected identifier byte is called enhanced checksum and it is used for communication with LIN 2.0 slaves.
The USART can be configured to:
Send/Check an Enhanced checksum automatically (CHKDIS = 0 & CHKTYP = 0)
Send/Check a Classic checksum automatically (CHKDIS = 0 & CHKTYP = 1)
Not send/check a checksum (CHKDIS = 1)
This configuration is made by the Checksum Type (CHKTYP) and Checksum Disable (CHKDIS) fields of the LIN Mode register (US_LINMR).
If the checksum feature is disabled, the user can send it manually all the same, by considering the checksum as a normal data byte and by adding 1 to the response data length (see
39.7.8.13 Frame Slot Mode
This mode is useful only for Master nodes. It respects the following rule: each frame slot shall be longer than or equal to
TFrame_Maximum.
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If the Frame Slot Mode is enabled (FSDIS = 0) and a frame transfer has been completed, the TXRDY flag is set again only after TFrame_Maximum delay, from the start of frame. So the Master node cannot send a new header if the frame slot duration of the previous frame is inferior to TFrame_Maximum.
If the Frame Slot Mode is disabled (FSDIS = 1) and a frame transfer has been completed, the TXRDY flag is set again immediately.
The TFrame_Maximum is calculated as below:
If the Checksum is sent (CHKDIS = 0):
THeader_Nominal = 34 x Tbit
TResponse_Nominal = 10 x (NData + 1) x Tbit
TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1) (Note:)
TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1 + 1) + 1) x Tbit
TFrame_Maximum = (77 + 14 x DLC) x Tbit
If the Checksum is not sent (CHKDIS = 1):
THeader_Nominal = 34 x Tbit
TResponse_Nominal = 10 x NData x Tbit
TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1
TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1) + 1) x Tbit
TFrame_Maximum = (63 + 14 x DLC) x Tbit
Note: The term “+1” leads to an integer result for TFrame_Max (LIN Specification 1.3).
Figure 39-44. Frame Slot Mode
Header
Frame slot = TFrame_Maximum
Frame
Data3
Response space
Response
Interframe space
Break Synch Protected
Identifier
Data 1 Data N-1 Data N Checksum
TXRDY
Frame Slot Mode
Disabled
Frame Slot Mode
Enabled
Write
US_LINID
Write
US_THR
LINTC
Data 1 Data 2 Data 3 Data N
39.7.8.14 LIN Errors
Bit Error
This error is generated in Master of Slave node configuration, when the USART is transmitting and if the transmitted value on the Tx line is different from the value sampled on the Rx line. If a bit error is detected, the transmission is aborted at the next byte border.
This error is reported by flag LINBE in the Channel Status Register (US_CSR).
Inconsistent Synch Field Error
This error is generated in Slave node configuration, if the Synch Field character received is other than 0x55.
This error is reported by flag LINISFE in the Channel Status Register (US_CSR).
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Identifier Parity Error
This error is generated in Slave node configuration, if the parity of the identifier is wrong. This error can be generated only if the parity feature is enabled (PARDIS = 0).
This error is reported by flag LINIPE in the Channel Status Register (US_CSR).
Checksum Error
This error is generated in Master of Slave node configuration, if the received checksum is wrong. This flag can be set to
“1” only if the checksum feature is enabled (CHKDIS = 0).
This error is reported by flag LINCE in the Channel Status Register (US_CSR).
Slave Not Responding Error
This error is generated in Master of Slave node configuration, when the USART expects a response from another node
(NACT = SUBSCRIBE) but no valid message appears on the bus within the time given by the maximum length of the
message frame, TFrame_Maximum (see Section 39.7.8.13
). This error is disabled if the USART does not expect any
message (NACT = PUBLISH or NACT = IGNORE).
This error is reported by flag LINSNRE in the Channel Status Register (US_CSR).
39.7.8.15 LIN Frame Handling
Master Node Configuration
Write TXEN and RXEN in US_CR to enable both the transmitter and the receiver.
Write USART_MODE in US_MR to select the LIN mode and the Master Node configuration.
Write CD and FP in US_BRGR to configure the baud rate.
Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM, FSDIS and DLC in US_LINMR to configure the frame transfer.
Check that TXRDY in US_CSR is set to “1”
Write IDCHR in US_LINIR to send the header
What comes next depends on the NACT configuration:
Case 1: NACT = PUBLISH, the USART sends the response
Wait until TXRDY in US_CSR rises
Write TCHR in US_THR to send a byte
If all the data have not been written, redo the two previous steps
Wait until LINTC in US_CSR rises
Check the LIN errors
Case 2: NACT = SUBSCRIBE, the USART receives the response
Wait until RXRDY in US_CSR rises
Read RCHR in US_RHR
If all the data have not been read, redo the two previous steps
Wait until LINTC in US_CSR rises
Check the LIN errors
Case 3: NACT = IGNORE, the USART is not concerned by the response
Wait until LINTC in US_CSR rises
Check the LIN errors
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Figure 39-45. Master Node Configuration, NACT = PUBLISH
Header
Frame slot = TFrame_Maximum
Frame
Data3
Response space
Interframe space
Response
Break Synch Protected
Identifier
Data 1
TXRDY
RXRDY
Write
US_LINIR
Write
US_THR
LINTC
Data 1 Data 2 Data 3
Figure 39-46. Master Node Configuration, NACT=SUBSCRIBE
Header
Frame slot = TFrame_Maximum
Frame
Data3
Response space
Break Synch Protected
Identifier
Data 1
TXRDY
RXRDY
Write
US_LINIR
Read
US_RHR
LINTC
Data N-1 Data N Checksum
FSDIS=1 FSDIS=0
Data N
Response
Interframe space
Data N-1 Data N Checksum
FSDIS=1 FSDIS=0
Data 1 Data N-2 Data N-1 Data N
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Figure 39-47. Master Node Configuration, NACT=IGNORE
Header
Frame slot = TFrame_Maximum
Frame
Data3
Response space
Interframe space
Response
Break Synch Protected
Identifier
Data 1 Data N-1 Data N Checksum
TXRDY
RXRDY
Write
US_LINIR
LINTC
FSDIS=1 FSDIS=0
Slave Node Configuration
Write TXEN and RXEN in US_CR to enable both the transmitter and the receiver.
Write USART_MODE in US_MR to select the LIN mode and the Slave Node configuration.
Write CD and FP in US_BRGR to configure the baud rate.
Wait until LINID in US_CSR rises
Check LINISFE and LINPE errors
Read IDCHR in US_RHR
Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM and DLC in US_LINMR to configure the frame transfer.
IMPORTANT : If the NACT configuration for this frame is PUBLISH, the US_LINMR register, must be write with NACT =
PUBLISH even if this field is already correctly configured, in order to set the TXREADY flag and the corresponding write transfer request.
What comes next depends on the NACT configuration:
Case 1: NACT = PUBLISH, the LIN controller sends the response
Wait until TXRDY in US_CSR rises
Write TCHR in US_THR to send a byte
If all the data have not been written, redo the two previous steps
Wait until LINTC in US_CSR rises
Check the LIN errors
Case 2: NACT = SUBSCRIBE, the USART receives the response
Wait until RXRDY in US_CSR rises
Read RCHR in US_RHR
If all the data have not been read, redo the two previous steps
Wait until LINTC in US_CSR rises
Check the LIN errors
Case 3: NACT = IGNORE, the USART is not concerned by the response
Wait until LINTC in US_CSR rises
Check the LIN errors
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Figure 39-48. Slave Node Configuration, NACT = PUBLISH
Break Synch Protected
Identifier
Data 1
TXRDY
RXRDY
LINIDRX
Read
US_LINID
Write
US_THR
LINTC
Data 1 Data 2
Figure 39-49. Slave Node Configuration, NACT = SUBSCRIBE
Data 3
Break Synch Protected
Identifier
Data 1
TXRDY
RXRDY
LINIDRX
Read
US_LINID
Read
US_RHR
LINTC
Figure 39-50. Slave Node Configuration, NACT = IGNORE
Data 1
Data N-1
Data N
Data N-1
Data N-2 Data N-1
Data N Checksum
Data N Checksum
Data N
Break Synch Protected
Identifier
Data 1 Data N-1 Data N Checksum
TXRDY
RXRDY
LINIDRX
Read
US_LINID
Read
US_RHR
LINTC
39.7.8.16 LIN Frame Handling With The DMAC
The USART can be used in association with the DMAC in order to transfer data directly into/from the on- and off-chip memories without any processor intervention.
The DMAC uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The DMAC always writes in the
Transmit Holding register (US_THR) and it always reads in the Receive Holding register (US_RHR). The size of the data written or read by the DMAC in the USART is always a byte.
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Master Node Configuration
The user can choose between two DMAC modes by the PDCM bit in the LIN Mode register (US_LINMR):
PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the DMAC in the Transmit
Holding register US_THR (instead of the LIN Mode register US_LINMR). Because the DMAC transfer size is limited to a byte, the transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS,
CHKTYP, DLM and FSDIS are written. During the second access the 8-bit DLC field is written.
PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by the user in the LIN
Mode register (US_LINMR).
The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response (NACT = PUBLISH).
The READ buffer contains the DATA if the USART receives the response (NACT = SUBSCRIBE).
Figure 39-51. Master Node with DMAC (PDCM = 1)
WRITE BUFFER
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
WRITE BUFFER
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
DLC
DLC
IDENTIFIER
DATA 0
(Peripheral) DMA
Controller
APB bus
NODE ACTION = PUBLISH
USART3
LIN CONTROLLER
TXRDY
IDENTIFIER
READ BUFFER
DATA 0
(Peripheral) DMA
Controller
APB bus
NODE ACTION = SUBSCRIBE
RXRDY
USART3
LIN CONTROLLER
TXRDY
|
|
|
|
|
|
|
|
DATA N
DATA N
Figure 39-52. Master Node with DMAC (PDCM = 0)
WRITE BUFFER
IDENTIFIER
DATA 0
|
|
|
|
(Peripher a l) DMA
Controller
WRITE BUFFER
IDENTIFIER
APB bus
NODE ACTION = PUBLI S H
U S ART 3
LIN CONTROLLER
TXRDY
READ BUFFER
DATA 0
DATA N
|
|
|
|
DATA N
(Peripher a l) DMA
Controller
APB bus
NODE ACTION = S UB S CRIBE
RXRDY
U S ART 3
LIN CONTROLLER
TXRDY
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Slave Node Configuration
In this configuration, the DMAC transfers only the DATA. The Identifier must be read by the user in the LIN Identifier register (US_LINIR). The LIN mode must be written by the user in the LIN Mode register (US_LINMR).
The WRITE buffer contains the DATA if the USART sends the response (NACT=PUBLISH).
The READ buffer contains the DATA if the USART receives the response (NACT=SUBSCRIBE).
Figure 39-53. Slave Node with DMAC
WRITE BUFFER READ BUFFER
DATA 0 DATA 0
NACT = SUBSCRIBE
|
|
|
|
APB bus
(Peripheral) DMA
Controller
TXRDY
USART3
LIN CONTROLLER
|
|
|
|
APB bus
(Peripheral) DMA
Controller
RXRDY
USART3
LIN CONTROLLER
DATA N DATA N
39.7.8.17 Wake-up Request
Any node in a sleeping LIN cluster may request a wake-up.
In the LIN 2.0 specification, the wakeup request is issued by forcing the bus to the dominant state from 250 µs to 5 ms.
For this, it is necessary to send the character 0xF0 in order to impose 5 successive dominant bits. Whatever the baud rate is, this character respects the specified timings.
Baud rate min = 1 kbit/s -> Tbit = 1ms -> 5 Tbits = 5 ms
Baud rate max = 20 kbit/s -> Tbi t= 50 µs -> 5 Tbits = 250 µs
In the LIN 1.3 specification, the wakeup request should be generated with the character 0x80 in order to impose 8 successive dominant bits.
The user can choose by the WKUPTYP bit in the LIN Mode register (US_LINMR) either to send a LIN 2.0 wakeup request (WKUPTYP=0) or to send a LIN 1.3 wakeup request (WKUPTYP=1).
A wake-up request is transmitted by writing the Control Register (US_CR) with the LINWKUP bit to 1. Once the transfer is completed, the LINTC flag is asserted in the Status Register (US_SR). It is cleared by writing the Control Register
(US_CR) with the RSTSTA bit to 1.
39.7.8.18 Bus Idle Time-out
If the LIN bus is inactive for a certain duration, the slave nodes shall automatically enter in sleep mode. In the LIN 2.0
specification, this time-out is fixed at 4 seconds. In the LIN 1.3 specification, it is fixed at 25000 Tbits.
In Slave Node configuration, the Receiver Time-out detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver to go into sleep mode.
The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the
Receiver Time-out Register (US_RTOR). If the TO field is programmed to 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains to 0. Otherwise, the receiver loads a 17-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises.
If STTTO is performed, the counter clock is stopped until a first character is received.
If RETTO is performed, the counter starts counting down immediately from the value TO.
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Table 39-15. Receiver Time-out Programming
LIN Specification Baud Rate
1 000 bit/s
2 400 bit/s
2.0
9 600 bit/s
19 200 bit/s
1.3
20 000 bit/s
-
Time-out period
4s
25 000 Tbits
TO
4 000
9 600
38 400
76 800
80 000
25 000
39.7.9 Test Modes
The USART can be programmed to operate in three different test modes. The internal loopback capability allows onboard diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally.
39.7.9.1 Normal Mode
Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin.
Figure 39-54. Normal Mode Configuration
RXD
Receiver
TXD
Transmitter
39.7.9.2 Automatic Echo Mode
Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in
receiver input, thus the receiver remains active.
Figure 39-55. Automatic Echo Mode Configuration
RXD
Receiver
TXD
Transmitter
39.7.9.3 Local Loopback Mode
Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in
.
The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state.
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Figure 39-56. Local Loopback Mode Configuration
Receiver
RXD
TXD
Transmitter
1
39.7.9.4 Remote Loopback Mode
Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in
. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission.
Figure 39-57. Remote Loopback Mode Configuration
RXD
Receiver
1
TXD
Transmitter
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39.7.10 Write Protection Registers
To prevent any single software error that may corrupt USART behavior, certain address spaces can be write-protected by setting the WPEN bit in the USART Write Protect Mode Register (US_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the USART Write Protect Status Register
(US_WPSR) is set and the WPVSRC field indicates in which register the write access has been attempted.
The WPVS flag is automatically reset by reading the USART Write Protect Mode Register (US_WPMR) with the appropriate access key, WPKEY.
The protected registers are:
“USART Baud Rate Generator Register”
“USART Receiver Time-out Register”
“USART Transmitter Timeguard Register”
“USART Manchester Configuration Register”
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39.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface
Table 39-16. Register Mapping
Offset Register
0x0000 Control Register
0x0004
0x0008
0x000C
0x0010
Mode Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x2C - 0x3C
0x0040
Channel Status Register
Receiver Holding Register
Transmitter Holding Register
Baud Rate Generator Register
Receiver Time-out Register
Transmitter Timeguard Register
Reserved
FI DI Ratio Register
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
0xE4
Number of Errors Register
Reserved
IrDA Filter Register
Manchester Encoder Decoder Register
LIN Mode Register
LIN Identifier Register
LIN Baud Rate Register
Write Protect Mode Register
0xE8
0x5C - 0xFC
Write Protect Status Register
Reserved
Notes: 1. Write is possible only in LIN Master node configuration.
Name
US_CR
US_MR
US_IER
US_IDR
US_IMR
US_CSR
US_RHR
US_THR
US_BRGR
US_RTOR
US_TTGR
–
US_FIDI
US_NER
–
US_IF
US_MAN
US_LINMR
US_LINIR
US_LINBRR
US_WPMR
US_WPSR
–
Read-only
–
Read-write
Read-write
Read-write
Read-write
Read-only
Read-write
Read-only
–
Access Reset
Write-only –
Read-write
Write-only
Write-only
Read-only
–
–
–
0x0
Read-only
Read-only
Write-only
Read-write
Read-write
Read-write
–
Read-write
–
0x0
–
0x0
0x0
0x0
–
0x174
–
–
0x0
0xB0011004
0x0
0x0
0x0
0x0
0x0
–
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39.8.1 USART Control Register
Name:
Address:
Access:
US_CR
0xF801C000 (0), 0xF8020000 (1), 0xF8024000 (2), 0xF8028000 (3)
Write-only
31
–
30
–
29
–
28
–
27
–
23
–
15
RETTO
22
–
14
RSTNACK
21
LINWKUP
13
RSTIT
20
LINABT
12
SENDA
19
RTSDIS
11
STTTO
26
–
18
RTSEN
10
STPBRK
2
RSTRX
7
TXDIS
6
TXEN
5
RXDIS
4
RXEN
3
RSTTX
For SPI control, see
“USART Control Register (SPI_MODE)” on page 813
.
• RSTRX: Reset Receiver
0: No effect.
1: Resets the receiver.
25
–
17
–
9
STTBRK
1
–
24
–
16
–
8
RSTSTA
0
–
• RSTTX: Reset Transmitter
0: No effect.
1: Resets the transmitter.
• RXEN: Receiver Enable
0: No effect.
1: Enables the receiver, if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: Disables the receiver.
• TXEN: Transmitter Enable
0: No effect.
1: Enables the transmitter if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: Disables the transmitter.
• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits PARE, FRAME, OVRE, MANERR, LINBE, LINISFE, LINIPE, LINCE, LINSNRE, LINID, LINTC, LINBK and RXBRK in US_CSR.
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• STTBRK: Start Break
0: No effect.
1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted.
No effect if a break is already being transmitted.
• STPBRK: Stop Break
0: No effect.
1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted.
• STTTO: Start Time-out
0: No effect.
1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.
• SENDA: Send Address
0: No effect.
1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.
• RSTIT: Reset Iterations
0: No effect.
1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.
• RSTNACK: Reset Non Acknowledge
0: No effect
1: Resets NACK in US_CSR.
• RETTO: Rearm Time-out
0: No effect
1: Restart Time-out
• RTSEN: Request to Send Enable
0: No effect.
1: Drives the pin RTS to 0.
• RTSDIS: Request to Send Disable
0: No effect.
1: Drives the pin RTS to 1.
• LINABT: Abort LIN Transmission
0: No effect.
1: Abort the current LIN transmission.
• LINWKUP: Send LIN Wakeup Signal
0: No effect:
1: Sends a wakeup signal on the LIN bus.
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39.8.2 USART Control Register (SPI_MODE)
Name:
Address:
Access:
US_CR (SPI_MODE)
0xF801C000 (0), 0xF8020000 (1), 0xF8024000 (2), 0xF8028000 (3)
Write-only
31
–
30
–
29
–
28
–
27
–
23
–
15
–
22
–
14
–
21
–
13
–
20
–
12
–
19
RCS
11
–
26
–
18
FCS
10
–
7
TXDIS
6
TXEN
5
RXDIS
4
RXEN
3
RSTTX
2
RSTRX
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 815 .
• RSTRX: Reset Receiver
0: No effect.
1: Resets the receiver.
25
–
17
–
9
–
1
–
• RSTTX: Reset Transmitter
0: No effect.
1: Resets the transmitter.
• RXEN: Receiver Enable
0: No effect.
1: Enables the receiver, if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: Disables the receiver.
• TXEN: Transmitter Enable
0: No effect.
1: Enables the transmitter if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: Disables the transmitter.
• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits OVRE, UNRE in US_CSR.
24
–
16
–
8
RSTSTA
0
–
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• FCS: Force SPI Chip Select
– Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE):
FCS = 0: No effect.
FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer).
• RCS: Release SPI Chip Select
– Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE):
RCS = 0: No effect.
RCS = 1: Releases the Slave Select Line NSS (RTS pin).
SAM9X35 [DATASHEET]
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814
Value
0x0
0x1
0x2
0x4
0x6
0x8
0xA
0xB
0xE
0xF
39.8.3 USART Mode Register
Name:
Address:
Access:
US_MR
0xF801C004 (0), 0xF8020004 (1), 0xF8024004 (2), 0xF8028004 (3)
Read-write
31
ONEBIT
30
MODSYNC
29
MAN
28
FILTER
27
–
23
–
22
VAR_SYNC
15
CHMODE
14
7 6
CHRL
21
DSNACK
20
INACK
13
NBSTOP
12
5 4
USCLKS
19
OVER
11
3
26
18
CLKO
10
PAR
25
MAX_ITERATION
17
MODE9
9
2
USART_MODE
1
For SPI configuration, see
“USART Mode Register (SPI_MODE)” on page 818 .
• USART_MODE: USART Mode of Operation
Name
NORMAL
RS485
HW_HANDSHAKING
IS07816_T_0
IS07816_T_1
IRDA
LIN_MASTER
LIN_SLAVE
SPI_MASTER
SPI_SLAVE
• USCLKS: Clock Selection
Description
Normal mode
RS485
Hardware Handshaking
IS07816 Protocol: T = 0
IS07816 Protocol: T = 1
IrDA
LIN Master
LIN Slave
SPI Master
SPI Slave
Value
0
1
3
Name
MCK
DIV
SCK
Description
Master Clock MCK is selected
Internal Clock Divided MCK/DIV (DIV=8) is selected
Serial Clock SLK is selected
24
16
MSBF
8
SYNC
0
SAM9X35 [DATASHEET]
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• CHRL: Character Length.
Value
0
1
2
3
Name
5_BIT
6_BIT
7_BIT
8_BIT
Description
Character length is 5 bits
Character length is 6 bits
Character length is 7 bits
Character length is 8 bits
• SYNC: Synchronous Mode Select
0: USART operates in Asynchronous Mode.
1: USART operates in Synchronous Mode.
• PAR: Parity Type
Value
0
1
2
3
4
6
Name
ODD
SPACE
MARK
NO
MULTIDROP
• NBSTOP: Number of Stop Bits
Description
Odd parity
Parity forced to 0 (Space)
Parity forced to 1 (Mark)
No parity
Multidrop mode
Value
0
1
2
Name
1_BIT
1_5_BIT
2_BIT
• CHMODE: Channel Mode
Description
1 stop bit
1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
2 stop bits
Value
0
1
2
3
Name
NORMAL
AUTOMATIC
LOCAL_LOOPBACK
Description
Normal Mode
Automatic Echo. Receiver input is connected to the TXD pin.
Local Loopback. Transmitter output is connected to the Receiver Input.
REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin.
• MSBF: Bit Order
0: Least Significant Bit is sent/received first.
1: Most Significant Bit is sent/received first.
• MODE9: 9-bit Character Length
0: CHRL defines character length.
1: 9-bit character length.
SAM9X35 [DATASHEET]
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• CLKO: Clock Output Select
0: The USART does not drive the SCK pin.
1: The USART drives the SCK pin if USCLKS does not select the external clock SCK.
• OVER: Oversampling Mode
0: 16x Oversampling.
1: 8x Oversampling.
• INACK: Inhibit Non Acknowledge
0: The NACK is generated.
1: The NACK is not generated.
• DSNACK: Disable Successive NACK
0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a
NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted.
• VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter
0: User defined configuration of command or data sync field depending on MODSYNC value.
1: The sync field is updated when a character is written into US_THR register.
• MAX_ITERATION: Maximum Number of Automatic Iteration
0 - 7: Defines the maximum number of iterations in mode ISO7816, protocol T= 0.
• FILTER: Infrared Receive Line Filter
0: The USART does not filter the receive line.
1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
• MAN: Manchester Encoder/Decoder Enable
0: Manchester Encoder/Decoder are disabled.
1: Manchester Encoder/Decoder are enabled.
• MODSYNC: Manchester Synchronization Mode
0:The Manchester Start bit is a 0 to 1 transition
1: The Manchester Start bit is a 1 to 0 transition.
• ONEBIT: Start Frame Delimiter Selector
0: Start Frame delimiter is COMMAND or DATA SYNC.
1: Start Frame delimiter is One Bit.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
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39.8.4 USART Mode Register (SPI_MODE)
Name:
Address:
Access:
US_MR (SPI_MODE)
0xF801C004 (0), 0xF8020004 (1), 0xF8024004 (2), 0xF8028004 (3)
Read-write
31
–
30
–
29
–
28
–
27
–
23
–
15
–
7
22
–
14
–
6
21
–
20
WRDBT
13
–
5
USCLKS
12
–
4
19
11
–
3
26
–
18
–
10
–
2
USART_MODE
1
9
–
25
–
17
CHRL
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 815 .
• USART_MODE: USART Mode of Operation
Value
0xE
0xF
Name
SPI_MASTER
SPI_SLAVE
• USCLKS: Clock Selection
Description
SPI Master
SPI Slave
24
–
16
CPOL
8
CPHA
0
Value
0
1
3
• CHRL: Character Length.
Name
MCK
DIV
SCK
Description
Master Clock MCK is selected
Internal Clock Divided MCK/DIV (DIV=8) is selected
Serial Clock SLK is selected
Value
3
Name
8_BIT
Description
Character length is 8 bits
• CPHA: SPI Clock Phase
– Applicable if USART operates in SPI Mode (USART_MODE = 0xE or 0xF):
CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with
CPOL to produce the required clock/data relationship between master and slave devices.
SAM9X35 [DATASHEET]
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• CHMODE: Channel Mode
Value
0
1
2
3
Name
NORMAL
AUTOMATIC
LOCAL_LOOPBACK
Description
Normal Mode
Automatic Echo. Receiver input is connected to the TXD pin.
Local Loopback. Transmitter output is connected to the Receiver Input.
REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin.
• CPOL: SPI Clock Polarity
– Applicable if USART operates in SPI Mode (Slave or Master, USART_MODE = 0xE or 0xF):
CPOL = 0: The inactive state value of SPCK is logic level zero.
CPOL = 1: The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required clock/data relationship between master and slave devices.
• WRDBT: Wait Read Data Before Transfer
0: The character transmission starts as soon as a character is written into US_THR register (assuming TXRDY was set).
1: The character transmission starts when a character is written and only if RXRDY flag is cleared (Receiver Holding Register has been read).
SAM9X35 [DATASHEET]
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39.8.5 USART Interrupt Enable Register
Name:
Address:
Access:
US_IER
0xF801C008 (0), 0xF8020008 (1), 0xF8024008 (2), 0xF8028008 (3)
Write-only
31
–
30
–
29
–
28
–
27
–
23
–
15
–
22
–
14
–
21
–
13
NACK
20
–
12
–
19
CTSIC
11
–
26
–
18
–
10
ITER
7
PARE
6
FRAME
5
OVRE
4
–
3
–
2
RXBRK
For SPI specific configuration, see
“USART Interrupt Enable Register (SPI_MODE)” on page 821
.
For LIN specific configuration, see “USART Interrupt Enable Register (LIN_MODE)” on page 822
.
25
–
17
–
9
TXEMPTY
1
TXRDY
• RXRDY: RXRDY Interrupt Enable
• TXRDY: TXRDY Interrupt Enable
• RXBRK: Receiver Break Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Enable
• PARE: Parity Error Interrupt Enable
• TIMEOUT: Time-out Interrupt Enable
• TXEMPTY: TXEMPTY Interrupt Enable
• ITER: Max number of Repetitions Reached Interrupt Enable
• NACK: Non Acknowledge Interrupt Enable
• CTSIC: Clear to Send Input Change Interrupt Enable
• MANE: Manchester Error Interrupt Enable
0: No effect
1: Enables the corresponding interrupt.
24
MANE
16
–
8
TIMEOUT
0
RXRDY
SAM9X35 [DATASHEET]
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39.8.6 USART Interrupt Enable Register (SPI_MODE)
Name:
Address:
Access:
US_IER (SPI_MODE)
0xF801C008 (0), 0xF8020008 (1), 0xF8024008 (2), 0xF8028008 (3)
Write-only
31
–
30
–
29
–
28
–
27
–
23
–
15
–
22
–
14
–
21
–
13
–
20
–
12
–
19
–
11
–
26
–
18
–
10
UNRE
7
–
6
–
5
OVRE
4
–
3
–
2
–
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 815 .
• RXRDY: RXRDY Interrupt Enable
• TXRDY: TXRDY Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• TXEMPTY: TXEMPTY Interrupt Enable
• UNRE: SPI Underrun Error Interrupt Enable
25
–
17
–
9
TXEMPTY
1
TXRDY
0: No effect
1: Enables the corresponding interrupt.
24
–
16
–
8
–
0
RXRDY
SAM9X35 [DATASHEET]
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821
39.8.7 USART Interrupt Enable Register (LIN_MODE)
Name:
Address:
Access:
US_IER (LIN_MODE)
0xF801C008 (0), 0xF8020008 (1), 0xF8024008 (2), 0xF8028008 (3)
Write-only
31
–
30
–
29
LINSNRE
28
LINCE
27
LINIPE
26
LINISFE
23
–
15
LINTC
7
PARE
22
–
14
LINID
6
FRAME
21
–
13
LINBK
5
OVRE
20
–
12
–
4
–
19
–
11
–
3
–
18
–
10
–
2
–
This configuration is relevant only if USART_MODE=0xA or 0xB in “USART Mode Register” on page 815 .
• RXRDY: RXRDY Interrupt Enable
• TXRDY: TXRDY Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Enable
• PARE: Parity Error Interrupt Enable
• TIMEOUT: Time-out Interrupt Enable
• TXEMPTY: TXEMPTY Interrupt Enable
• LINBK: LIN Break Sent or LIN Break Received Interrupt Enable
• LINID: LIN Identifier Sent or LIN Identifier Received Interrupt Enable
• LINTC: LIN Transfer Completed Interrupt Enable
• LINBE: LIN Bus Error Interrupt Enable
• LINISFE: LIN Inconsistent Synch Field Error Interrupt Enable
• LINIPE: LIN Identifier Parity Interrupt Enable
• LINCE: LIN Checksum Error Interrupt Enable
• LINSNRE: LIN Slave Not Responding Error Interrupt Enable
25
LINBE
17
–
9
TXEMPTY
1
TXRDY
0: No effect
1: Enables the corresponding interrupt.
24
–
16
–
8
TIMEOUT
0
RXRDY
SAM9X35 [DATASHEET]
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39.8.8 USART Interrupt Disable Register
Name:
Address:
Access:
US_IDR
0xF801C00C (0), 0xF802000C (1), 0xF802400C (2), 0xF802800C (3)
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
23
–
15
–
7
PARE
22
–
14
–
6
FRAME
21
–
13
NACK
5
OVRE
20
–
12
–
4
–
19
CTSIC
11
–
3
–
18
–
10
ITER
2
RXBRK
For SPI specific configuration, see
“USART Interrupt Disable Register (SPI_MODE)” on page 824
.
For LIN specific configuration, see “USART Interrupt Disable Register (LIN_MODE)” on page 825 .
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• RXBRK: Receiver Break Interrupt Disable
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Disable
• PARE: Parity Error Interrupt Disable
• TIMEOUT: Time-out Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• ITER: Max Number of Repetitions Reached Interrupt Disable
• NACK: Non Acknowledge Interrupt Disable
• CTSIC: Clear to Send Input Change Interrupt Disable
• MANE: Manchester Error Interrupt Disable
25
–
17
–
9
TXEMPTY
1
TXRDY
0: No effect
1: Disables the corresponding interrupt.
24
MANE
16
–
8
TIMEOUT
0
RXRDY
SAM9X35 [DATASHEET]
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823
39.8.9 USART Interrupt Disable Register (SPI_MODE)
Name:
Address:
Access:
US_IDR (SPI_MODE)
0xF801C00C (0), 0xF802000C (1), 0xF802400C (2), 0xF802800C (3)
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
OVRE
20
–
12
–
4
–
19
–
11
–
3
–
18
–
10
UNRE
2
–
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 815 .
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• UNRE: SPI Underrun Error Interrupt Disable
25
–
17
–
9
TXEMPTY
1
TXRDY
0: No effect
1: Disables the corresponding interrupt.
24
–
16
–
8
–
0
RXRDY
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
824
39.8.10 USART Interrupt Disable Register (LIN_MODE)
Name:
Address:
Access:
US_IDR (LIN_MODE)
0xF801C00C (0), 0xF802000C (1), 0xF802400C (2), 0xF802800C (3)
Write-only
31
–
30
–
29
LINSNRE
28
LINCE
27
LINIPE
26
LINISFE
23
–
15
LINTC
7
PARE
22
–
14
LINID
6
FRAME
21
–
13
LINBK
5
OVRE
20
–
12
–
4
–
19
–
11
–
3
–
18
–
10
–
2
–
This configuration is relevant only if USART_MODE=0xA or 0xB in “USART Mode Register” on page 815 .
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• FRAME: Framing Error Interrupt Disable
• PARE: Parity Error Interrupt Disable
• TIMEOUT: Time-out Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• LINBK: LIN Break Sent or LIN Break Received Interrupt Disable
• LINID: LIN Identifier Sent or LIN Identifier Received Interrupt Disable
• LINTC: LIN Transfer Completed Interrupt Disable
• LINBE: LIN Bus Error Interrupt Disable
• LINISFE: LIN Inconsistent Synch Field Error Interrupt Disable
• LINIPE: LIN Identifier Parity Interrupt Disable
• LINCE: LIN Checksum Error Interrupt Disable
• LINSNRE: LIN Slave Not Responding Error Interrupt Disable
25
LINBE
17
–
9
TXEMPTY
1
TXRDY
0: No effect
1: Disables the corresponding interrupt.
24
–
16
–
8
TIMEOUT
0
RXRDY
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
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39.8.11 USART Interrupt Mask Register
Name:
Address:
Access:
US_IMR
0xF801C010 (0), 0xF8020010 (1), 0xF8024010 (2), 0xF8028010 (3)
Read-only
31
–
30
–
29
–
28
–
27
–
23
–
15
–
22
–
14
–
21
–
13
NACK
20
–
12
–
19
CTSIC
11
–
26
–
18
–
10
ITER
7
PARE
6
FRAME
5
OVRE
4
–
3
–
2
RXBRK
For SPI specific configuration, see
“USART Interrupt Mask Register (SPI_MODE)” on page 827 .
For LIN specific configuration, see “USART Interrupt Mask Register (LIN_MODE)” on page 828
.
25
–
17
–
9
TXEMPTY
1
TXRDY
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• RXBRK: Receiver Break Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• FRAME: Framing Error Interrupt Mask
• PARE: Parity Error Interrupt Mask
• TIMEOUT: Time-out Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• ITER: Max Number of Repetitions Reached Interrupt Mask
• NACK: Non Acknowledge Interrupt Mask
• CTSIC: Clear to Send Input Change Interrupt Mask
• MANE: Manchester Error Interrupt Mask
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
24
MANE
16
–
8
TIMEOUT
0
RXRDY
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826
39.8.12 USART Interrupt Mask Register (SPI_MODE)
Name:
Address:
Access:
US_IMR (SPI_MODE)
0xF801C010 (0), 0xF8020010 (1), 0xF8024010 (2), 0xF8028010 (3)
Read-only
31
–
30
–
29
–
28
–
27
–
23
–
15
–
22
–
14
–
21
–
13
–
20
–
12
–
19
–
11
–
26
–
18
–
10
UNRE
7
–
6
–
5
OVRE
4
–
3
–
2
–
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 815 .
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• UNRE: SPI Underrun Error Interrupt Mask
25
–
17
–
9
TXEMPTY
1
TXRDY
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
24
–
16
–
8
–
0
RXRDY
SAM9X35 [DATASHEET]
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39.8.13 USART Interrupt Mask Register (LIN_MODE)
Name:
Address:
Access:
US_IMR (LIN_MODE)
0xF801C010 (0), 0xF8020010 (1), 0xF8024010 (2), 0xF8028010 (3)
Read-only
31
–
30
–
29
LINSNRE
28
LINCE
27
LINIPE
26
LINISFE
23
–
15
LINTC
7
PARE
22
–
14
LINID
6
FRAME
21
–
13
LINBK
5
OVRE
20
–
12
–
4
–
19
–
11
–
3
–
18
–
10
–
2
–
This configuration is relevant only if USART_MODE=0xA or 0xB in “USART Mode Register” on page 815 .
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• FRAME: Framing Error Interrupt Mask
• PARE: Parity Error Interrupt Mask
• TIMEOUT: Time-out Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• LINBK: LIN Break Sent or LIN Break Received Interrupt Mask
• LINID: LIN Identifier Sent or LIN Identifier Received Interrupt Mask
• LINTC: LIN Transfer Completed Interrupt Mask
• LINBE: LIN Bus Error Interrupt Mask
• LINISFE: LIN Inconsistent Synch Field Error Interrupt Mask
• LINIPE: LIN Identifier Parity Interrupt Mask
• LINCE: LIN Checksum Error Interrupt Mask
• LINSNRE: LIN Slave Not Responding Error Interrupt Mask
25
LINBE
17
–
9
TXEMPTY
1
TXRDY
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
24
–
16
–
8
TIMEOUT
0
RXRDY
SAM9X35 [DATASHEET]
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828
39.8.14 USART Channel Status Register
Name:
Address:
Access:
US_CSR
0xF801C014 (0), 0xF8020014 (1), 0xF8024014 (2), 0xF8028014 (3)
Read-only
31
–
30
–
29
–
28
–
27
–
23
CTS
15
–
22
–
14
–
21
–
20
–
13 12
NACK –
19
CTSIC
11
–
26
–
18
–
10
ITER
25
–
17
–
9
TXEMPTY
1
TXRDY
24
MANERR
16
–
8
TIMEOUT
0
RXRDY
7
PARE
6
FRAME
5
OVRE
4
–
3
–
2
RXBRK
For SPI specific configuration, see
“USART Channel Status Register (SPI_MODE)” on page 831
.
For LIN specific configuration, see “USART Channel Status Register (LIN_MODE)” on page 832 .
• RXRDY: Receiver Ready
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1: There is no character in the US_THR.
• RXBRK: Break Received/End of Break
0: No Break received or End of Break detected since the last RSTSTA.
1: Break Received or End of Break detected since the last RSTSTA.
• OVRE: Overrun Error
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
0: No stop bit has been detected low since the last RSTSTA.
1: At least one stop bit has been detected low since the last RSTSTA.
• PARE: Parity Error
0: No parity error has been detected since the last RSTSTA.
1: At least one parity error has been detected since the last RSTSTA.
• TIMEOUT: Receiver Time-out
0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0.
1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
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• TXEMPTY: Transmitter Empty
0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1: There are no characters in US_THR, nor in the Transmit Shift Register.
• ITER: MaxNumber of Repetitions Reached
0: Maximum number of repetitions has not been reached since the last RSTSTA.
1: Maximum number of repetitions has been reached since the last RSTSTA.
• NACK: Non Acknowledge Interrupt
0: Non Acknowledge has not been detected since the last RSTNACK.
1: At least one Non Acknowledge has been detected since the last RSTNACK.
• CTSIC: Clear to Send Input Change Flag
0: No input change has been detected on the CTS pin since the last read of US_CSR.
1: At least one input change has been detected on the CTS pin since the last read of US_CSR.
• CTS: Image of CTS Input
0: CTS is set to 0.
1: CTS is set to 1.
• MANERR: Manchester Error
0: No Manchester error has been detected since the last RSTSTA.
1: At least one Manchester error has been detected since the last RSTSTA.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
830
39.8.15 USART Channel Status Register (SPI_MODE)
Name:
Address:
Access:
US_CSR (SPI_MODE)
0xF801C014 (0), 0xF8020014 (1), 0xF8024014 (2), 0xF8028014 (3)
Read-only
31
–
30
–
29
–
28
–
27
–
23
–
15
–
22
–
14
–
21
–
13
–
20
–
12
–
19
–
11
–
26
–
18
–
10
UNRE
25
–
17
–
9
TXEMPTY
1
TXRDY
24
–
16
–
8
–
0
RXRDY
7
–
6
–
5
OVRE
4
–
3
–
2
–
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 815 .
• RXRDY: Receiver Ready
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1: There is no character in the US_THR.
• OVRE: Overrun Error
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty
0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1: There are no characters in US_THR, nor in the Transmit Shift Register.
• UNRE: Underrun Error
0: No SPI underrun error has occurred since the last RSTSTA.
1: At least one SPI underrun error has occurred since the last RSTSTA.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
831
39.8.16 USART Channel Status Register (LIN_MODE)
Name:
Address:
Access:
US_CSR (LIN_MODE)
0xF801C014 (0), 0xF8020014 (1), 0xF8024014 (2), 0xF8028014 (3)
Read-only
31
–
30
–
29
LINSNRE
28
LINCE
27
LINIPE
26
LINISFE
23
LINBLS
15
LINTC
7
PARE
22
–
14
LINID
6
FRAME
21
–
13
LINBK
5
OVRE
20
–
12
–
4
–
19
–
11
–
3
–
18
–
10
–
2
–
25
LINBE
17
–
9
TXEMPTY
1
TXRDY
24
–
16
–
8
TIMEOUT
0
RXRDY
This configuration is relevant only if USART_MODE=0xA or 0xB in “USART Mode Register” on page 815 .
• RXRDY: Receiver Ready
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1: There is no character in the US_THR.
• OVRE: Overrun Error
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
0: No stop bit has been detected low since the last RSTSTA.
1: At least one stop bit has been detected low since the last RSTSTA.
• PARE: Parity Error
0: No parity error has been detected since the last RSTSTA.
1: At least one parity error has been detected since the last RSTSTA.
• TIMEOUT: Receiver Time-out
0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0.
1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• TXEMPTY: Transmitter Empty
0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1: There are no characters in US_THR, nor in the Transmit Shift Register.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
832
• LINBK: LIN Break Sent or LIN Break Received
– Applicable if USART operates in LIN Master Mode (USART_MODE = 0xA):
0: No LIN Break has been sent since the last RSTSTA.
1:At least one LIN Break has been sent since the last RSTSTA
– If USART operates in LIN Slave Mode (USART_MODE = 0xB):
0: No LIN Break has received sent since the last RSTSTA.
1:At least one LIN Break has been received since the last RSTSTA.
• LINID: LIN Identifier Sent or LIN Identifier Received
– If USART operates in LIN Master Mode (USART_MODE = 0xA):
0: No LIN Identifier has been sent since the last RSTSTA.
1:At least one LIN Identifier has been sent since the last RSTSTA.
– If USART operates in LIN Slave Mode (USART_MODE = 0xB):
0: No LIN Identifier has been received since the last RSTSTA.
1:At least one LIN Identifier has been received since the last RSTSTA
• LINTC: LIN Transfer Completed
0: The USART is idle or a LIN transfer is ongoing.
1: A LIN transfer has been completed since the last RSTSTA.
• LINBLS: LIN Bus Line Status
0: LIN Bus Line is set to 0.
1: LIN Bus Line is set to 1.
• LINBE: LIN Bit Error
0: No Bit Error has been detected since the last RSTSTA.
1: A Bit Error has been detected since the last RSTSTA.
• LINISFE: LIN Inconsistent Synch Field Error
0: No LIN Inconsistent Synch Field Error has been detected since the last RSTSTA
1: The USART is configured as a Slave node and a LIN Inconsistent Synch Field Error has been detected since the last RSTSTA.
• LINIPE: LIN Identifier Parity Error
0: No LIN Identifier Parity Error has been detected since the last RSTSTA.
1: A LIN Identifier Parity Error has been detected since the last RSTSTA.
• LINCE: LIN Checksum Error
0: No LIN Checksum Error has been detected since the last RSTSTA.
1: A LIN Checksum Error has been detected since the last RSTSTA.
• LINSNRE: LIN Slave Not Responding Error
0: No LIN Slave Not Responding Error has been detected since the last RSTSTA.
1: A LIN Slave Not Responding Error has been detected since the last RSTSTA.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
833
39.8.17 USART Receive Holding Register
Name:
Address:
Access:
US_RHR
0xF801C018 (0), 0xF8020018 (1), 0xF8024018 (2), 0xF8028018 (3)
Read-only
31
–
30
–
29
–
28
–
27
–
23
–
15
RXSYNH
7
22
–
14
–
6
21
–
13
–
5
20
–
12
–
4
RXCHR
19
–
11
–
3
• RXCHR: Received Character
Last character received if RXRDY is set.
• RXSYNH: Received Sync
0: Last Character received is a Data.
1: Last Character received is a Command.
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
RXCHR
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
834
39.8.18 USART Transmit Holding Register
Name:
Address:
Access:
US_THR
0xF801C01C (0), 0xF802001C (1), 0xF802401C (2), 0xF802801C (3)
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
23
–
15
TXSYNH
7
22
–
14
–
6
21
–
13
–
5
20
–
12
–
4
19
–
11
–
3
18
–
10
–
2
TXCHR
• TXCHR: Character to be Transmitted
Next character to be transmitted after the current character if TXRDY is not set.
• TXSYNH: Sync Field to be Transmitted
0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.
1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.
25
–
17
–
9
–
1
24
–
16
–
8
TXCHR
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
835
39.8.19 USART Baud Rate Generator Register
Name:
Address:
Access:
US_BRGR
0xF801C020 (0), 0xF8020020 (1), 0xF8024020 (2), 0xF8028020 (3)
Read-write
31
–
30
–
29
–
28
–
27
–
23
–
15
22
–
14
21
–
13
20
–
12
19
–
11
CD
7 6 5 4 3
CD
26
–
18
10
2
25
–
17
FP
9
1
24
–
16
8
0
• CD: Clock Divider
CD
0
1 to 65535
OVER = 0
USART_MODE
≠
ISO7816
SYNC = 0
SYNC = 1 or
USART_MODE = SPI
(Master or Slave)
OVER = 1
Baud Rate Clock Disabled
Baud Rate =
Selected Clock/(16*CD)
Baud Rate =
Selected Clock/(8*CD)
Baud Rate =
Selected Clock /CD
USART_MODE =
ISO7816
Baud Rate = Selected
Clock/(FI_DI_RATIO*CD)
• FP: Fractional Part
0: Fractional divider is disabled.
1 - 7: Baud rate resolution, defined by FP x 1/8.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
836
39.8.20 USART Receiver Time-out Register
Name:
Address:
Access:
US_RTOR
0xF801C024 (0), 0xF8020024 (1), 0xF8024024 (2), 0xF8028024 (3)
Read-write
31
–
30
–
29
–
28
–
27
–
23
–
15
22
–
14
21
–
13
20
–
12
19
–
11
TO
26
–
18
–
10
25
–
17
–
9
7 6 5 4 3 2 1
TO
• TO: Time-out Value
0: The Receiver Time-out is disabled.
1 - 131071: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
24
–
16
TO
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
837
39.8.21 USART Transmitter Timeguard Register
Name:
Address:
Access:
US_TTGR
0xF801C028 (0), 0xF8020028 (1), 0xF8024028 (2), 0xF8028028 (3)
Read-write
31
–
30
–
29
–
28
–
27
–
23
–
15
–
7
22
–
14
–
6
21
–
13
–
5
20
–
12
–
4
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
TG
• TG: Timeguard Value
0: The Transmitter Timeguard is disabled.
1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
24
–
16
–
8
–
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
838
39.8.22 USART FI DI RATIO Register
Name:
Address:
Access:
US_FIDI
0xF801C040 (0), 0xF8020040 (1), 0xF8024040 (2), 0xF8028040 (3)
Read-write
Reset Value: 0x174
31
–
30
–
29
–
28
–
27
–
23
–
22
–
21
–
20
–
19
–
26
–
18
–
25
–
17
–
15
–
7
14
–
6
13
–
5
12
–
11
–
4
FI_DI_RATIO
3
10
2
9
FI_DI_RATIO
1
• FI_DI_RATIO: FI Over DI Ratio Value
0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal.
1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO.
24
–
16
–
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
839
39.8.23 USART Number of Errors Register
Name:
Address:
Access:
US_NER
0xF801C044 (0), 0xF8020044 (1), 0xF8024044 (2), 0xF8028044 (3)
Read-only
31
–
30
–
29
–
28
–
27
–
23
–
15
–
7
22
–
14
–
6
21
–
13
–
5
20
–
12
–
4
NB_ERRORS
3
19
–
11
–
26
–
18
–
10
–
2
This register is relevant only if USART_MODE=0x4 or 0x6 in
“USART Mode Register” on page 815
.
• NB_ERRORS: Number of Errors
Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
25
–
17
–
9
–
1
24
–
16
–
8
–
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
840
39.8.24 USART IrDA FILTER Register
Name:
Address:
Access:
US_IF
0xF801C04C (0), 0xF802004C (1), 0xF802404C (2), 0xF802804C (3)
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
23
–
15
–
7
22
–
14
–
6
21
–
13
–
5
20
–
12
–
4
IRDA_FILTER
3
19
–
11
–
18
–
10
–
2
25
–
17
–
9
–
1
This register is relevant only if USART_MODE=0x8 in “USART Mode Register” on page 815 .
• IRDA_FILTER: IrDA Filter
Sets the filter of the IrDA demodulator.
24
–
16
–
8
–
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
841
39.8.25 USART Manchester Configuration Register
Name:
Address:
Access:
US_MAN
0xF801C050 (0), 0xF8020050 (1), 0xF8024050 (2), 0xF8028050 (3)
Read-write
31
–
30
DRIFT
29
ONE
28
RX_MPOL
27
–
19 23
–
15
–
22
–
14
–
21
–
13
–
20
–
12
TX_MPOL
11
–
26
–
18
RX_PL
25
17
RX_PP
10
–
9
TX_PP
7
–
6
–
5
–
4
–
3 2 1
TX_PL
• TX_PL: Transmitter Preamble Length
0: The Transmitter Preamble pattern generation is disabled
1 - 15: The Preamble Length is TX_PL x Bit Period
• TX_PP: Transmitter Preamble Pattern
The following values assume that TX_MPOL field is not set:
Value
00
01
10
11
Name
ALL_ONE
ALL_ZERO
ZERO_ONE
ONE_ZERO
Description
The preamble is composed of ‘1’s
The preamble is composed of ‘0’s
The preamble is composed of ‘01’s
The preamble is composed of ‘10’s
24
16
8
0
• TX_MPOL: Transmitter Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• RX_PL: Receiver Preamble Length
0: The receiver preamble pattern detection is disabled
1 - 15: The detected preamble length is RX_PL x Bit Period
• RX_PP: Receiver Preamble Pattern Detected
The following values assume that RX_MPOL field is not set:
Value
00
01
10
11
Name
ALL_ONE
ALL_ZERO
ZERO_ONE
ONE_ZERO
Description
The preamble is composed of ‘1’s
The preamble is composed of ‘0’s
The preamble is composed of ‘01’s
The preamble is composed of ‘10’s
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
842
• RX_MPOL: Receiver Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• ONE: Must Be Set to 1
Bit 29 must always be set to 1 when programming the US_MAN register.
• DRIFT: Drift Compensation
0: The USART can not recover from an important clock drift
1: The USART can recover from clock drift. The 16X clock mode must be enabled.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
843
39.8.26 USART LIN Mode Register
Name:
Address:
Access:
US_LINMR
0xF801C054 (0), 0xF8020054 (1), 0xF8024054 (2), 0xF8028054 (3)
Read-write
31
–
30
–
29
–
28
–
27
–
23
–
15
22
–
14
21
–
13
20
–
12
19
–
11
DLC
26
–
18
–
10
25
–
17
–
9
24
–
16
PDCM
8
7
WKUPTYP
6
FSDIS
5
DLM
4
CHKTYP
3
CHKDIS
2
PARDIS
1
NACT
This register is relevant only if USART_MODE=0xA or 0xB in “USART Mode Register” on page 815
.
0
• NACT: LIN Node Action
Value
00
01
10
Name
PUBLISH
SUBSCRIBE
IGNORE
Description
The USART transmits the response.
The USART receives the response.
The USART does not transmit and does not receive the response.
Values which are not listed in the table must be considered as “reserved”.
• PARDIS: Parity Disable
0: In Master node configuration, the Identifier Parity is computed and sent automatically. In Master node and Slave node configuration, the parity is checked automatically.
1:Whatever the node configuration is, the Identifier parity is not computed/sent and it is not checked.
• CHKDIS: Checksum Disable
0: In Master node configuration, the checksum is computed and sent automatically. In Slave node configuration, the checksum is checked automatically.
1: Whatever the node configuration is, the checksum is not computed/sent and it is not checked.
• CHKTYP: Checksum Type
0: LIN 2.0 “Enhanced” Checksum
1: LIN 1.3 “Classic” Checksum
• DLM: Data Length Mode
0: The response data length is defined by the field DLC of this register.
1: The response data length is defined by the bits 5 and 6 of the Identifier (IDCHR in US_LINIR).
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
844
• FSDIS: Frame Slot Mode Disable
0: The Frame Slot Mode is enabled.
1: The Frame Slot Mode is disabled.
• WKUPTYP: Wakeup Signal Type
0: Setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal.
1: Setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal.
• DLC: Data Length Control
0 - 255: Defines the response data length if DLM=0,in that case the response data length is equal to DLC+1 bytes.
• PDCM: DMAC Mode
0: The LIN mode register US_LINMR is not written by the DMAC.
1: The LIN mode register US_LINMR (excepting that flag) is written by the DMAC.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
845
39.8.27 USART LIN Identifier Register
Name:
Address:
Access:
US_LINIR
0xF801C058 (0), 0xF8020058 (1), 0xF8024058 (2), 0xF8028058 (3)
Read-write or Read-only
31
–
30
–
29
–
28
–
27
–
23
–
15
–
7
22
–
14
–
6
21
–
13
–
5
20
–
12
–
4
19
–
11
–
3
26
–
18
–
10
–
2
IDCHR
This register is relevant only if USART_MODE=0xA or 0xB in “USART Mode Register” on page 815
.
• IDCHR: Identifier Character
If USART_MODE=0xA (Master node configuration):
IDCHR is Read-write and its value is the Identifier character to be transmitted.
If USART_MODE=0xB (Slave node configuration):
IDCHR is Read-only and its value is the last Identifier character that has been received.
25
–
17
–
9
–
1
24
–
16
–
8
–
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
846
39.8.28 USART LIN Baud Rate Register
Name:
Address:
Access:
US_LINBRR
0xF801C05C (0), 0xF802005C (1), 0xF802405C (2), 0xF802805C (3)
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
18 23
–
15
22
–
14
21
–
13
20
–
12
19
–
11 10
LINCD
7 6 5 4 3 2
LINCD
This register is relevant only if USART_MODE=0xA or 0xB in “USART Mode Register” on page 815
.
Returns the baud rate value after the synchronization process completion.
• LINCD: Clock Divider after Synchronization
• LINFP: Fractional Part after Synchronization
25
–
17
LINFP
9
1
8
0
24
–
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
847
39.8.29 USART Write Protect Mode Register
Name:
Address:
Access:
Reset:
US_WPMR
0xF801C0E4 (0), 0xF80200E4 (1), 0xF80240E4 (2), 0xF80280E4 (3)
Read-write
See
31 30 29 28 27
WPKEY
26
23 22 21 20 19 18
WPKEY
15 14 13 12 11 10
WPKEY
7
—
6
—
5
—
4
—
3
—
2
—
25
17
9
24
16
8
1
—
0
WPEN
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII).
Protects the registers:
•
“USART Mode Register” on page 815
•
“USART Baud Rate Generator Register” on page 836
•
“USART Receiver Time-out Register” on page 837
•
“USART Transmitter Timeguard Register” on page 838
•
“USART FI DI RATIO Register” on page 839
•
“USART IrDA FILTER Register” on page 841
•
“USART Manchester Configuration Register” on page 842
• WPKEY: Write Protect KEY
Should be written at value 0x555341 (“USA” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
848
39.8.30 USART Write Protect Status Register
Name:
Address:
Access:
Reset:
US_WPSR
0xF801C0E8 (0), 0xF80200E8 (1), 0xF80240E8 (2), 0xF80280E8 (3)
Read-only
See
31
—
30
—
29
—
28
—
27
—
26
—
23 22 21 20
WPVSRC
19 18
15
7
—
14
6
—
13
5
—
12
WPVSRC
11
4
—
3
—
10
2
—
25
—
17
9
24
—
16
8
1
—
0
WPVS
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the US_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the US_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted.
Note: Reading US_WPSR automatically clears all fields.
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40.
Universal Asynchronous Receiver Transmitter (UART)
40.1 Description
The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions.
Moreover, the association with DMA controller permits packet handling for these tasks with processor time reduced to a minimum.
40.2 Embedded Characteristics
Two-pin UART
Independent Receiver and Transmitter with a Common Programmable Baud Rate Generator
Even, Odd, Mark or Space Parity Generation
Parity, Framing and Overrun Error Detection
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Interrupt Generation
Support for Two DMA Channels with Connection to Receiver and Transmitter
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40.3 Block Diagram
Figure 40-1. UART Functional Block Diagram
Peripher a l
Bridge
Power
M a n a gement
Controller
APB
MCK
UART
B au d R a te
Gener a tor
DMA Controller
Tr a n s mit
Receive
Interr u pt
Control
Table 40-1. UART Pin Description
Pin Name
URXD
UTXD
Description
UART Receive Data
UART Transmit Data
Type
Input
Output
UTXD
P a r a llel
Inp u t/
O u tp u t ua rt_ir q
URXD
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40.4 Product Dependencies
40.4.1 I/O Lines
The UART pins are multiplexed with PIO lines. The programmer must first configure the corresponding PIO Controller to enable I/O line operations of the UART.
Table 40-2. I/O Lines
Instance
UART0
UART0
UART1
UART1
Signal
URXD0
UTXD0
URXD1
UTXD1
I/O Line
PC9
PC8
PC17
PC16
Peripheral
C
C
C
C
40.4.2 Power Management
The UART clock is controllable through the Power Management Controller. In this case, the programmer must first configure the PMC to enable the UART clock. Usually, the peripheral identifier used for this purpose is 1.
40.4.3 Interrupt Source
The UART interrupt line is connected to one of the interrupt sources of the Interrupt Controller. Interrupt handling requires programming of the Interrupt Controller before configuring the UART.
40.5 UART Operations
The UART operates in asynchronous mode only and supports only 8-bit character handling (with parity). It has no clock pin.
The UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator.
Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible with those of a standard USART.
40.5.1 Baud Rate Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in UART_BRGR (Baud Rate
Generator Register). If UART_BRGR is set to 0, the baud rate clock is disabled and the UART remains inactive.
The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud rate is Master
Clock divided by (16 x 65536).
Baud Rate =
MCK
16 × CD
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Figure 40-2. Baud Rate Generator
CD
CD
MCK 16-bit Counter
OUT
0
>1
1
0
Divide by 16
Baud Rate
Clock
Receiver
Sampling Clock
40.5.2 Receiver
40.5.2.1 Receiver Reset, Enable and Disable
After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register UART_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
The programmer can disable the receiver by writing UART_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation.
The programmer can also put the receiver in its reset state by writing UART_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost.
40.5.2.2 Start Detection and Data Sampling
The UART only supports asynchronous operations, and this affects only its receiver. The UART receiver detects the start of a received character by sampling the URXD signal until it detects a valid start bit. A low level (space) on URXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the URXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 40-3. Start Bit Detection
Sampling Clock
URXD
True Start
Detection
D0
Baud Rate
Clock
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Figure 40-4. Character Reception
Example: 8-bit, parity enabled 1 stop
0.5 bit period
1 bit period
URXD
Sampling D2 D3 D4 D5 D6 D7
Parity Bit
Stop Bit
40.5.2.3 Receiver Ready
When a complete character is received, it is transferred to the UART_RHR and the RXRDY status bit in UART_SR
(Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register UART_RHR is read.
Figure 40-5. Receiver Ready
D0 D1
True Start Detection
URXD S D0 D1 D2 D3 D4 D5 D6 D7 P S D0 D1 D2 D3 D4 D5 D6 D7 P
RXRDY
Read UART_RHR
40.5.2.4 Receiver Overrun
If UART_RHR has not been read by the software (or the Peripheral Data Controller or DMA Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in UART_SR is set. OVRE is cleared when the software writes the control register UART_CR with the bit RSTSTA (Reset Status) at 1.
Figure 40-6. Receiver Overrun
URXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY
OVRE
RSTSTA
40.5.2.5 Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field
PAR in UART_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in
UART_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register UART_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1.
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Figure 40-7. Parity Error
URXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY
PARE
Wrong Parity Bit
RSTSTA
40.5.2.6 Receiver Framing Error
When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UART_SR is set at the same time the
RXRDY bit is set. The FRAME bit remains high until the control register UART_CR is written with the bit RSTSTA at 1.
Figure 40-8. Receiver Framing Error
URXD
RXRDY
S D0 D1 D2 D3 D4 D5 D6 D7 P stop
FRAME
Stop Bit
Detected at 0
RSTSTA
40.5.3 Transmitter
40.5.3.1 Transmitter Reset, Enable and Disable
After device reset, the UART transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register UART_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register (UART_THR) before actually starting the transmission.
The programmer can disable the transmitter by writing UART_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped.
The programmer can also put the transmitter in its reset state by writing the UART_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters.
40.5.3.2 Transmit Format
The UART transmitter drives the pin UTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown in the following figure. The field PARE in the mode register UART_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit.
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Figure 40-9. Character Transmission
Example: Parity enabled
Baud Rate
Clock
UTXD
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7 Parity
Bit
Stop
Bit
40.5.3.3 Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register UART_SR. The transmission starts when the programmer writes in the Transmit Holding Register (UART_THR), and after the written character is transferred from UART_THR to the Shift Register. The TXRDY bit remains high until a second character is written in UART_THR. As soon as the first character is completed, the last character written in UART_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty.
When both the Shift Register and UART_THR are empty, i.e., all the characters written in UART_THR have been processed, the TXEMPTY bit rises after the last stop bit has been completed.
Figure 40-10.Transmitter Control
UART_THR Data 0 Data 1
Shift Register Data 0 Data 1
UTXD
S Data 0 P stop S Data 1 P stop
TXRDY
TXEMPTY
Write Data 0 in UART_THR
Write Data 1 in UART_THR
40.5.4 DMA Support
Both the receiver and the transmitter of the UART are connected to a DMA Controller (DMAC) channel.
The DMA Controller channels are programmed via registers that are mapped within the DMAC user interface.
40.5.5 Test Modes
The UART supports three test modes. These modes of operation are programmed by using the field CHMODE (Channel
Mode) in the mode register (UART_MR).
The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the URXD line, it is sent to the
UTXD line. The transmitter operates normally, but has no effect on the UTXD line.
The Local Loopback mode allows the transmitted characters to be received. UTXD and URXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The URXD pin level has no effect and the
UTXD line is held high, as in idle state.
The Remote Loopback mode directly connects the URXD pin to the UTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission.
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Figure 40-11.Test Modes
Automatic Echo
Receiver RXD
Transmitter
Disabled
TXD
Local Loopback
Receiver
Transmitter
Remote Loopback
Receiver
V
DD
Disabled
Disabled
RXD
V
DD
Disabled
TXD
RXD
Transmitter
Disabled
TXD
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40.6 Universal Asynchronous Receiver Transmitter (UART) User Interface
Table 40-3. Register Mapping
Offset Register
0x0000 Control Register
0x0004
0x0008
0x000C
0x0010
Mode Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
0x0014
0x0018
0x001C
0x0020
Status Register
Receive Holding Register
Transmit Holding Register
Baud Rate Generator Register
0x0024 - 0x003C Reserved
0x004C - 0x00FC Reserved
Name
UART_CR
UART_MR
UART_IER
UART_IDR
UART_IMR
UART_SR
UART_RHR
UART_THR
UART_BRGR
–
–
Access Reset
Write-only –
Read-write
Write-only
Write-only
Read-only
0x0
–
–
0x0
Read-only
Read-only
Write-only
Read-write
–
–
–
0x0
–
0x0
–
–
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40.6.1 UART Control Register
Name:
Address:
Access:
UART_CR
0xF8040000 (0), 0xF8044000 (1)
Write-only
31
–
30
–
29
–
23
–
15
–
7
TXDIS
22
–
14
–
6
TXEN
21
–
13
–
5
RXDIS
28
–
20
–
12
–
4
RXEN
27
–
19
–
11
–
3
RSTTX
26
–
18
–
10
–
2
RSTRX
• RSTRX: Reset Receiver
0 = No effect.
1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
• RSTTX: Reset Transmitter
0 = No effect.
1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.
25
–
17
–
9
–
1
–
24
–
16
–
8
RSTSTA
0
–
• RXEN: Receiver Enable
0 = No effect.
1 = The receiver is enabled if RXDIS is 0.
• RXDIS: Receiver Disable
0 = No effect.
1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped.
• TXEN: Transmitter Enable
0 = No effect.
1 = The transmitter is enabled if TXDIS is 0.
• TXDIS: Transmitter Disable
0 = No effect.
1 = The transmitter is disabled. If a character is being processed and a character has been written in the UART_THR and RSTTX is not set, both characters are completed before the transmitter is stopped.
• RSTSTA: Reset Status Bits
0 = No effect.
1 = Resets the status bits PARE, FRAME and OVRE in the UART_SR.
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40.6.2 UART Mode Register
Name:
Address:
Access:
UART_MR
0xF8040004 (0), 0xF8044004 (1)
Read-write
31
–
30
–
29
–
23
–
15
7
–
CHMODE
22
–
14
6
–
21
–
13
–
5
–
• PAR: Parity Type
Value
0
1
2
3
4
Name
EVEN
ODD
SPACE
MARK
NO
28
–
20
–
12
–
4
–
Description
Even Parity
Odd Parity
Space: parity forced to 0
Mark: parity forced to 1
No Parity
• CHMODE: Channel Mode
Value
0
1
2
3
Name
NORMAL
AUTOMATIC
Description
Normal Mode
Automatic Echo
LOCAL_LOOPBACK Local Loopback
REMOTE_LOOPBACK
Remote Loopback
27
–
19
–
11
3
–
26
–
18
–
10
PAR
2
–
25
–
17
–
9
1
–
24
–
16
–
8
–
0
–
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40.6.3 UART Interrupt Enable Register
Name:
Address:
Access:
UART_IER
0xF8040008 (0), 0xF8044008 (1)
Write-only
31
–
30
–
29
–
23
–
15
–
7
PARE
22
–
14
–
6
FRAME
21
–
13
–
5
OVRE
• RXRDY: Enable RXRDY Interrupt
• TXRDY: Enable TXRDY Interrupt
• OVRE: Enable Overrun Error Interrupt
• FRAME: Enable Framing Error Interrupt
• PARE: Enable Parity Error Interrupt
• TXEMPTY: Enable TXEMPTY Interrupt
0 = No effect.
1 = Enables the corresponding interrupt.
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
TXEMPTY
1
TXRDY
24
–
16
–
8
–
0
RXRDY
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40.6.4 UART Interrupt Disable Register
Name:
Address:
Access:
UART_IDR
0xF804000C (0), 0xF804400C (1)
Write-only
31
–
30
–
29
–
23
–
15
–
7
PARE
22
–
14
–
6
FRAME
21
–
13
–
5
OVRE
• RXRDY: Disable RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• OVRE: Disable Overrun Error Interrupt
• FRAME: Disable Framing Error Interrupt
• PARE: Disable Parity Error Interrupt
• TXEMPTY: Disable TXEMPTY Interrupt
0 = No effect.
1 = Disables the corresponding interrupt.
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
TXEMPTY
1
TXRDY
24
–
16
–
8
–
0
RXRDY
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40.6.5 UART Interrupt Mask Register
Name:
Address:
Access:
UART_IMR
0xF8040010 (0), 0xF8044010 (1)
Read-only
31
–
30
–
29
–
23
–
15
–
7
PARE
22
–
14
–
6
FRAME
21
–
13
–
5
OVRE
• RXRDY: Mask RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• OVRE: Mask Overrun Error Interrupt
• FRAME: Mask Framing Error Interrupt
• PARE: Mask Parity Error Interrupt
• TXEMPTY: Mask TXEMPTY Interrupt
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
TXEMPTY
1
TXRDY
24
–
16
–
8
–
0
RXRDY
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40.6.6 UART Status Register
Name:
Address:
Access:
UART_SR
0xF8040014 (0), 0xF8044014 (1)
Read-only
31
–
30
–
29
–
23
–
15
–
7
PARE
22
–
14
–
6
FRAME
21
–
13
–
5
OVRE
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
TXEMPTY
1
TXRDY
• RXRDY: Receiver Ready
0 = No character has been received since the last read of the UART_RHR or the receiver is disabled.
1 = At least one complete character has been received, transferred to UART_RHR and not yet read.
• TXRDY: Transmitter Ready
0 = A character has been written to UART_THR and not yet transferred to the Shift Register, or the transmitter is disabled.
1 = There is no character written to UART_THR not yet transferred to the Shift Register.
24
–
16
–
8
–
0
RXRDY
• OVRE: Overrun Error
0 = No overrun error has occurred since the last RSTSTA.
1 = At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
0 = No framing error has occurred since the last RSTSTA.
1 = At least one framing error has occurred since the last RSTSTA.
• PARE: Parity Error
0 = No parity error has occurred since the last RSTSTA.
1 = At least one parity error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty
0 = There are characters in UART_THR, or characters being processed by the transmitter, or the transmitter is disabled.
1 = There are no characters in UART_THR and there are no characters being processed by the transmitter.
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40.6.7 UART Receiver Holding Register
Name:
Address:
Access:
UART_RHR
0xF8040018 (0), 0xF8044018 (1)
Read-only
31
–
30
–
29
–
23
–
15
–
7
22
–
14
–
6
21
–
13
–
5
• RXCHR: Received Character
Last received character if RXRDY is set.
28
–
20
–
12
–
4
RXCHR
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
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40.6.8 UART Transmit Holding Register
Name:
Address:
Access:
UART_THR
0xF804001C (0), 0xF804401C (1)
Write-only
31
–
30
–
29
–
23
–
15
–
7
22
–
14
–
6
21
–
13
–
5
28
–
20
–
12
–
4
27
–
19
–
11
–
3
TXCHR
• TXCHR: Character to be Transmitted
Next character to be transmitted after the current character if TXRDY is not set.
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
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40.6.9 UART Baud Rate Generator Register
Name:
Address:
Access:
UART_BRGR
0xF8040020 (0), 0xF8044020 (1)
Read-write
31
–
30
–
29
–
23
–
15
22
–
14
21
–
13
7 6 5
28
–
20
–
12
4
CD
CD
• CD: Clock Divisor
0 = Baud Rate Clock is disabled
1 to 65,535 = MCK / (CD x 16)
27
–
19
–
11
3
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
–
8
0
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41.
Controller Area Network (CAN) Programmer Datasheet
41.1 Description
The CAN controller provides all the features required to implement the serial communication protocol CAN defined by
Robert Bosch GmbH, the CAN specification as referred to by ISO/11898A (2.0 Part A and 2.0 Part B) for high speeds and ISO/11519-2 for low speeds. The CAN Controller is able to handle all types of frames (Data, Remote, Error and
Overload) and achieves a bitrate of 1 Mbit/sec.
CAN controller accesses are made through configuration registers. 8 independent message objects (mailboxes) are implemented.
Any mailbox can be programmed as a reception buffer block (even non-consecutive buffers). For the reception of defined messages, one or several message objects can be masked without participating in the buffer feature. An interrupt is generated when the buffer is full. According to the mailbox configuration, the first message received can be locked in the
CAN controller registers until the application acknowledges it, or this message can be discarded by new received messages.
Any mailbox can be programmed for transmission. Several transmission mailboxes can be enabled in the same time. A priority can be defined for each mailbox independently.
An internal 16-bit timer is used to stamp each received and sent message. This timer starts counting as soon as the CAN controller is enabled. This counter can be reset by the application or automatically after a reception in the last mailbox in
Time Triggered Mode.
The CAN controller offers optimized features to support the Time Triggered Communication (TTC) protocol.
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41.2 Embedded Characteristics
Fully Compliant with CAN 2.0 Part A and 2.0 Part B
Bit Rates up to 1Mbit/s
8 Object Oriented Mailboxes with the Following Properties:
CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object Configurable in Receive (with Overwrite or Not) or Transmit Modes
Independent 29-bit Identifier and Mask Defined for Each Mailbox
32-bit Access to Data Registers for Each Mailbox Data Object
Uses a 16-bit Timestamp on Receive and Transmit Messages
Hardware Concatenation of ID Masked Bitfields To Speed Up Family ID Processing
16-bit Internal Timer for Timestamping and Network Synchronization
Programmable Reception Buffer Length up to 8 Mailbox Objects
Priority Management between Transmission Mailboxes
Autobaud and Listening Mode
Low Power Mode and Programmable Wake-up on Bus Activity or by the Application
Data, Remote, Error and Overload Frame Handling
Write Protected Registers
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41.3 Block Diagram
Figure 41-1. CAN Block Diagram
Controller Area Network
CAN Protocol Controller
PIO
Control
&
Status
Error Counter
Mailbox
Priority
Encoder
MB0
MB1
MCK
PMC
MBx
(x = number of mailboxes - 1)
User Interface
CAN Interrupt
CANRX
CANTX
Internal Bus
41.4 Application Block Diagram
Figure 41-2. Application Block Diagram
L
a
yer
s
CANbas ed Profile s
CANbas ed Applic a tion L a yer
CAN D a t a Link L a yer
CAN Phy s ic a l L a yer
Implement
a
tion
S oftw a re
S oftw a re
CAN Controller
Tr a n s ceiver
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41.5 I/O Lines Description
Table 41-1. I/O Lines Description
Name Description
CANRX
CANTX
CAN Receive Serial Data
CAN Transmit Serial Data
Type
Input
Output
41.6 Product Dependencies
41.6.1 I/O Lines
The pins used for interfacing the CAN may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired CAN pins to their peripheral function. If I/O lines of the CAN are not used by the application, they can be used for other purposes by the PIO Controller.
Table 41-2. I/O Lines
Instance
CAN0
CAN0
CAN1
CAN1
Signal
CANRX0
CANTX0
CANRX1
CANTX1
I/O Line
PA9
PA10
PA6
PA5
Peripheral
B
B
B
B
41.6.2 Power Management
The programmer must first enable the CAN clock in the Power Management Controller (PMC) before using the CAN.
A Low-power Mode is defined for the CAN controller. If the application does not require CAN operations, the CAN clock can be stopped when not needed and be restarted later. Before stopping the clock, the CAN Controller must be in Lowpower Mode to complete the current transfer. After restarting the clock, the application must disable the Low-power Mode of the CAN controller.
41.6.3 Interrupt
The CAN interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the CAN interrupt requires the AIC to be programmed first. Note that it is not recommended to use the CAN interrupt line in edgesensitive mode.
Table 41-3. Peripheral IDs
Instance
CAN0
CAN1
ID
29
30
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41.7 CAN Controller Features
41.7.1 CAN Protocol Overview
The Controller Area Network (CAN) is a multi-master serial communication protocol that efficiently supports real-time control with a very high level of security with bit rates up to 1 Mbit/s.
The CAN protocol supports four different frame types:
Data frames: They carry data from a transmitter node to the receiver nodes. The overall maximum data frame length is 108 bits for a standard frame and 128 bits for an extended frame.
Remote frames: A destination node can request data from the source by sending a remote frame with an identifier that matches the identifier of the required data frame. The appropriate data source node then sends a data frame as a response to this node request.
Error frames: An error frame is generated by any node that detects a bus error.
Overload frames: They provide an extra delay between the preceding and the successive data frames or remote frames.
The Atmel CAN controller provides the CPU with full functionality of the CAN protocol V2.0 Part A and V2.0 Part B. It minimizes the CPU load in communication overhead. The Data Link Layer and part of the physical layer are automatically handled by the CAN controller itself.
The CPU reads or writes data or messages via the CAN controller mailboxes. An identifier is assigned to each mailbox.
The CAN controller encapsulates or decodes data messages to build or to decode bus data frames. Remote frames, error frames and overload frames are automatically handled by the CAN controller under supervision of the software application.
41.7.2 Mailbox Organization
The CAN module has 8 buffers, also called channels or mailboxes. An identifier that corresponds to the CAN identifier is defined for each active mailbox. Message identifiers can match the standard frame identifier or the extended frame identifier. This identifier is defined for the first time during the CAN initialization, but can be dynamically reconfigured later so that the mailbox can handle a new message family. Several mailboxes can be configured with the same ID.
Each mailbox can be configured in receive or in transmit mode independently. The mailbox object type is defined in the
MOT field of the CAN_MMRx register.
41.7.2.1 Message Acceptance Procedure
If the MIDE field in the CAN_MIDx register is set, the mailbox can handle the extended format identifier; otherwise, the mailbox handles the standard format identifier. Once a new message is received, its ID is masked with the CAN_MAMx value and compared with the CAN_MIDx value. If accepted, the message ID is copied to the CAN_MIDx register.
Figure 41-3. Message Acceptance Procedure
CAN_MIDx CAN_MAMx Message Received
& &
==
Message Accepted
Yes
CAN_MFIDx
No
Message Refused
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If a mailbox is dedicated to receiving several messages (a family of messages) with different IDs, the acceptance mask defined in the CAN_MAMx register must mask the variable part of the ID family. Once a message is received, the application must decode the masked bits in the CAN_MIDx. To speed up the decoding, masked bits are grouped in the family ID register (CAN_MFIDx).
For example, if the following message IDs are handled by the same mailbox:
ID0 101000100100010010000100 0 11 00b
ID1 101000100100010010000100 0 11 01b
ID2 101000100100010010000100 0 11 10b
ID3 101000100100010010000100 0 11 11b
ID4 101000100100010010000100 1 11 00b
ID5 101000100100010010000100 1 11 01b
ID6 101000100100010010000100 1 11 10b
ID7 101000100100010010000100 1 11 11b
The CAN_MIDx and CAN_MAMx of Mailbox x must be initialized to the corresponding values:
CAN_MIDx = 001 101000100100010010000100 x 11 xxb
CAN_MAMx = 001 111111111111111111111111 0 11 00b
If Mailbox x receives a message with ID6, then CAN_MIDx and CAN_MFIDx are set:
CAN_MIDx = 001 101000100100010010000100 1 11 10b
CAN_MFIDx = 00000000000000000000000000000110b
If the application associates a handler for each message ID, it may define an array of pointers to functions: void (*pHandler[8])(void);
When a message is received, the corresponding handler can be invoked using CAN_MFIDx register and there is no need to check masked bits: unsigned int MFID0_register;
MFID0_register = Get_CAN_MFID0_Register();
// Get_CAN_MFID0_Register() returns the value of the CAN_MFID0 register pHandler[MFID0_register]();
41.7.2.2 Receive Mailbox
When the CAN module receives a message, it looks for the first available mailbox with the lowest number and compares the received message ID with the mailbox ID. If such a mailbox is found, then the message is stored in its data registers.
Depending on the configuration, the mailbox is disabled as long as the message has not been acknowledged by the application (Receive only), or, if new messages with the same ID are received, then they overwrite the previous ones
(Receive with overwrite).
It is also possible to configure a mailbox in Consumer Mode. In this mode, after each transfer request, a remote frame is automatically sent. The first answer received is stored in the corresponding mailbox data registers.
Several mailboxes can be chained to receive a buffer. They must be configured with the same ID in Receive Mode, except for the last one, which can be configured in Receive with Overwrite Mode. The last mailbox can be used to detect a buffer overflow.
Table 41-4.
Mailbox Object Type
Receive
Receive with overwrite
Consumer
Description
The first message received is stored in mailbox data registers. Data remain available until the next transfer request.
The last message received is stored in mailbox data register. The next message always overwrites the previous one. The application has to check whether a new message has not overwritten the current one while reading the data registers.
A remote frame is sent by the mailbox. The answer received is stored in mailbox data register.
This extends Receive mailbox features. Data remain available until the next transfer request.
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41.7.2.3 Transmit Mailbox
When transmitting a message, the message length and data are written to the transmit mailbox with the correct identifier.
For each transmit mailbox, a priority is assigned. The controller automatically sends the message with the highest priority first (set with the field PRIOR in CAN_MMRx register).
It is also possible to configure a mailbox in Producer Mode. In this mode, when a remote frame is received, the mailbox data are sent automatically. By enabling this mode, a producer can be done using only one mailbox instead of two: one to detect the remote frame and one to send the answer.
Table 41-5.
Mailbox Object Type
Transmit
Producer
Description
The message stored in the mailbox data registers will try to win the bus arbitration immediately or later according to or not the Time Management Unit configuration (see
The application is notified that the message has been sent or aborted.
The message prepared in the mailbox data registers will be sent after receiving the next remote frame. This extends transmit mailbox features.
41.7.3 Time Management Unit
The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the bit clock of the CAN bus line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR register). It is automatically cleared in the following cases:
After a reset
When the CAN controller is in Low-power Mode is enabled (LPM bit set in the CAN_MR and SLEEP bit set in the
CAN_SR)
After a reset of the CAN controller (CANEN bit in the CAN_MR register)
In Time-triggered Mode, when a message is accepted by the last mailbox (rising edge of the MRDY signal in the
CAN_MSR last_mailbox_number
register).
The application can also reset the internal timer by setting TIMRST in the CAN_TCR register. The current value of the internal timer is always accessible by reading the CAN_TIM register.
When the timer rolls-over from FFFFh to 0000h, TOVF (Timer Overflow) signal in the CAN_SR register is set. TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register. Depending on the corresponding interrupt mask in the
CAN_IMR register, an interrupt is generated while TOVF is set.
In a CAN network, some CAN devices may have a larger counter. In this case, the application can also decide to freeze the internal counter when the timer reaches FFFFh and to wait for a restart condition from another device. This feature is enabled by setting TIMFRZ in the CAN_MR register. The CAN_TIM register is frozen to the FFFFh value. A clear condition described above restarts the timer. A timer overflow (TOVF) interrupt is triggered.
To monitor the CAN bus activity, the CAN_TIM register is copied to the CAN _TIMESTP register after each start of frame or end of frame and a TSTP interrupt is triggered. If TEOF bit in the CAN_MR register is set, the value is captured at each
End Of Frame, else it is captured at each Start Of Frame. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while TSTP is set in the CAN_SR. TSTP bit is cleared by reading the CAN_SR register.
The time management unit can operate in one of the two following modes:
Timestamping mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame
Time Triggered mode: A mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger
Timestamping Mode is enabled by clearing TTM field in the CAN_MR register. Time Triggered Mode is enabled by setting TTM field in the CAN_MR register.
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41.7.4 CAN 2.0 Standard Features
41.7.4.1 CAN Bit Timing Configuration
All controllers on a CAN bus must have the same bit rate and bit length. At different clock frequencies of the individual controllers, the bit rate has to be adjusted by the time segments.
The CAN protocol specification partitions the nominal bit time into four different segments:
Figure 41-4. Partition of the CAN Bit Time
SYNC_SEG
NOMINAL BIT TIME
PROP_SEG PHASE_SEG1 PHASE_SEG2
Sample Point
TIME QUANTUM
The TIME QUANTUM (TQ) is a fixed unit of time derived from the MCK period. The total number of TIME QUANTA in a bit time is programmable from 8 to 25.
SYNC SEG: SYNChronization Segment.
This part of the bit time is used to synchronize the various nodes on the bus. An edge is expected to lie within this segment. It is 1 TQ long.
PROP SEG: PROPagation Segment.
This part of the bit time is used to compensate for the physical delay times within the network. It is twice the sum of the signal’s propagation time on the bus line, the input comparator delay, and the output driver delay. It is programmable to be 1,2,..., 8 TQ long.
This parameter is defined in the PROPAG field of the
.
PHASE SEG1, PHASE SEG2: PHASE Segment 1 and 2.
The Phase-Buffer-Segments are used to compensate for edge phase errors. These segments can be lengthened
(PHASE SEG1) or shortened (PHASE SEG2) by resynchronization.
Phase Segment 1 is programmable to be 1,2,..., 8 TQ long.
Phase Segment 2 length has to be at least as long as the Information Processing Time (IPT) and may not be more than the length of Phase Segment 1.
These parameters are defined in the PHASE1 and PHASE2 fields of the ”CAN Baudrate Register”
.
INFORMATION PROCESSING TIME:
The Information Processing Time (IPT) is the time required for the logic to determine the bit level of a sampled bit. The
IPT begins at the sample point, is measured in TQ and is fixed at 2 TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, PHASE SEG2 shall not be less than the IPT.
SAMPLE POINT:
The SAMPLE POINT is the point in time at which the bus level is read and interpreted as the value of that respective bit.
Its location is at the end of PHASE_SEG1.
SJW: ReSynchronization Jump Width.
The ReSynchronization Jump Width defines the limit to the amount of lengthening or shortening of the Phase Segments.
SJW is programmable to be the minimum of PHASE SEG1 and 4 TQ.
If the SMP field in the CAN_BR register is set, then the incoming bit stream is sampled three times with a period of half a
CAN clock period, centered on sample point.
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In the CAN controller, the length of a bit on the CAN bus is determined by the parameters (BRP, PROPAG, PHASE1 and
PHASE2).
t
BIT
= t
CSC
+ t
PRS
+ t
PHS1
The time quantum is calculated as follows:
+ t
PHS2 t
CSC
= ( BRP + 1 ) ⁄ MCK
Note: The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized.
t
PRS t
PHS1 t
PHS2
=
=
= t
CSC
× (
PROPAG + 1
) t
CSC
× t
CSC
×
( PHASE1 + 1
( PHASE2 + 1 )
)
To compensate for phase shifts between clock oscillators of different controllers on the bus, the CAN controller must resynchronize on any relevant signal edge of the current transmission. The resynchronization shortens or lengthens the bit time so that the position of the sample point is shifted with regard to the detected edge. The resynchronization jump width (SJW) defines the maximum of time by which a bit period may be shortened or lengthened by resynchronization.
t
SJW
= t
CSC
× (
SJW + 1
)
Figure 41-5. CAN Bit Timing
MCK
CAN Clock t
CSC t
PRS t
PHS1 t
PHS2
NOMINAL BIT TIME
SYNC_
SEG
PROP_SEG PHASE_SEG1 PHASE_SEG2
Sample Point Transmission Point
Example of bit timing determination for CAN baudrate of 500 Kbit/s:
MCK = 48MHz
CAN baudrate= 500kbit/s => bit time= 2us
Delay of the bus driver: 50 ns
Delay of the receiver: 30ns
Delay of the bus line (20m): 110ns
The total number of time quanta in a bit time must be comprised between 8 and
25. If we fix the bit time to 16 time quanta:
Tcsc = 1 time quanta = bit time / 16 = 125 ns
=> BRP = (Tcsc x MCK) - 1 = 5
The propagation segment time is equal to twice the sum of the signal’s propagation time on the bus line, the receiver delay and the output driver delay:
Tprs = 2 * (50+30+110) ns = 380 ns = 3 Tcsc
=> PROPAG = Tprs/Tcsc - 1 = 2
The remaining time for the two phase segments is:
Tphs1 + Tphs2 = bit time - Tcsc - Tprs = (16 - 1 - 3)Tcsc
Tphs1 + Tphs2 = 12 Tcsc
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Because this number is even, we choose Tphs2 = Tphs1 (else we would choose Tphs2
= Tphs1 + Tcsc)
Tphs1 = Tphs2 = (12/2) Tcsc = 6 Tcsc
=> PHASE1 = PHASE2 = Tphs1/Tcsc - 1 = 5
The resynchronization jump width must be comprised between 1 Tcsc and the minimum of 4 Tcsc and Tphs1. We choose its maximum value:
Tsjw = Min(4 Tcsc,Tphs1) = 4 Tcsc
=> SJW = Tsjw/Tcsc - 1 = 3
Finally: CAN_BR = 0x00053255
CAN Bus Synchronization
Two types of synchronization are distinguished: “hard synchronization” at the start of a frame and “resynchronization” inside a frame. After a hard synchronization, the bit time is restarted with the end of the SYNC_SEG segment, regardless of the phase error. Resynchronization causes a reduction or increase in the bit time so that the position of the sample point is shifted with respect to the detected edge.
The effect of resynchronization is the same as that of hard synchronization when the magnitude of the phase error of the edge causing the resynchronization is less than or equal to the programmed value of the resynchronization jump width
(t
SJW
).
When the magnitude of the phase error is larger than the resynchronization jump width and
The phase error is positive, then PHASE_SEG1 is lengthened by an amount equal to the resynchronization jump width.
The phase error is negative, then PHASE_SEG2 is shortened by an amount equal to the resynchronization jump width.
Figure 41-6. CAN Resynchronization
THE PHASE ERROR IS POSITIVE
(the transmitter is slower than the receiver)
Received data bit
Nominal
Sample point
Sample point after resynchronization
Nominal bit time
(before resynchronization)
SYNC_
SEG
PROP_SEG PHASE_SEG1 PHASE_SEG2
SYNC_
SEG
Phase error (max Tsjw)
Bit time with resynchronization
SYNC_
SEG
Phase error
PROP_SEG PHASE_SEG1 PHASE_SEG2
SYNC_
SEG
Received data bit
Nominal bit time
(before resynchronization)
THE PHASE ERROR IS NEGATIVE
(the transmitter is faster than the receiver)
PHASE_SEG2
SYNC_
SEG after resynchronization
PROP_SEG
Sample point
PHASE_SEG1
Nominal
Sample point
PHASE_SEG2
SYNC_
SEG
Bit time with resynchronization
Phase error
PHASE_
SEG2
SYNC_
SEG
PROP_SEG PHASE_SEG1 PHASE_SEG2
SYNC_
SEG
Phase error (max Tsjw)
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Autobaud Mode
The autobaud feature is enabled by setting the ABM field in the CAN_MR register. In this mode, the CAN controller is only listening to the line without acknowledging the received messages. It can not send any message. The errors flags are updated. The bit timing can be adjusted until no error occurs (good configuration found). In this mode, the error counters are frozen. To go back to the standard mode, the ABM bit must be cleared in the CAN_MR register.
41.7.4.2 Error Detection
There are five different error types that are not mutually exclusive. Each error concerns only specific fields of the CAN data frame (refer to the Bosch CAN specification for their correspondence):
CRC error (CERR bit in the CAN_SR register): With the CRC, the transmitter calculates a checksum for the CRC bit sequence from the Start of Frame bit until the end of the Data Field. This CRC sequence is transmitted in the
CRC field of the Data or Remote Frame.
Bit-stuffing error (SERR bit in the CAN_SR register): If a node detects a sixth consecutive equal bit level during the bit-stuffing area of a frame, it generates an Error Frame starting with the next bit-time.
Bit error (BERR bit in CAN_SR register): A bit error occurs if a transmitter sends a dominant bit but detects a recessive bit on the bus line, or if it sends a recessive bit but detects a dominant bit on the bus line. An error frame is generated and starts with the next bit time.
Form Error (FERR bit in the CAN_SR register): If a transmitter detects a dominant bit in one of the fix-formatted segments CRC Delimiter, ACK Delimiter or End of Frame, a form error has occurred and an error frame is generated.
Acknowledgment error (AERR bit in the CAN_SR register): The transmitter checks the Acknowledge Slot, which is transmitted by the transmitting node as a recessive bit, contains a dominant bit. If this is the case, at least one other node has received the frame correctly. If not, an Acknowledge Error has occurred and the transmitter will start in the next bit-time an Error Frame transmission.
Fault Confinement
To distinguish between temporary and permanent failures, every CAN controller has two error counters: REC (Receive
Error Counter) and TEC (Transmit Error Counter). The two counters are incremented upon detected errors and are decremented upon correct transmissions or receptions, respectively. Depending on the counter values, the state of the node changes: the initial state of the CAN controller is Error Active, meaning that the controller can send Error Active flags. The controller changes to the Error Passive state if there is an accumulation of errors. If the CAN controller fails or if there is an extreme accumulation of errors, there is a state transition to Bus Off.
Figure 41-7. Line Error Mode
Init
TEC < 127 and
REC < 127
ERROR
PASSIVE
ERROR
ACTIVE
128 occurences of 11 consecutive recessive bits or
CAN controller reset
TEC > 127 or
REC > 127
BUS OFF
TEC > 255
An error active unit takes part in bus communication and sends an active error frame when the CAN controller detects an error.
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An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit waits before initiating further transmission.
A bus off unit is not allowed to have any influence on the bus.
For fault confinement, two errors counters (TEC and REC) are implemented. These counters are accessible via the
CAN_ECR register. The state of the CAN controller is automatically updated according to these counter values. If the
CAN controller enters Error Active state, then the ERRA bit is set in the CAN_SR register. The corresponding interrupt is pending while the interrupt is not masked in the CAN_IMR register. If the CAN controller enters Error Passive Mode, then the ERRP bit is set in the CAN_SR register and an interrupt remains pending while the ERRP bit is set in the CAN_IMR register. If the CAN enters Bus Off Mode, then the BOFF bit is set in the CAN_SR register. As for ERRP and ERRA, an interrupt is pending while the BOFF bit is set in the CAN_IMR register.
When one of the error counters values exceeds 96, an increased error rate is indicated to the controller through the
WARN bit in CAN_SR register, but the node remains error active. The corresponding interrupt is pending while the interrupt is set in the CAN_IMR register.
Refer to the Bosch CAN specification v2.0 for details on fault confinement.
Error Interrupt Handler
ERRA, WARN, ERRP and BOFF (CAN_SR) store the key transitions of the CAN bus status as defined in
. The transitions depend on the TEC and REC (CAN_ECR) values as described in
Section “Fault Confinement” on page 878
.
These flags are latched to keep from triggering a spurious interrupt in case these bits are used as the source of an interrupt. Thus, these flags may not reflect the current status of the CAN bus.
The current CAN bus state can be determined by reading the TEC and REC fields of CAN_ECR.
41.7.4.3 Overload
The overload frame is provided to request a delay of the next data or remote frame by the receiver node (“Request overload frame”) or to signal certain error conditions (“Reactive overload frame”) related to the intermission field respectively.
Reactive overload frames are transmitted after detection of the following error conditions:
Detection of a dominant bit during the first two bits of the intermission field
Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant bit by a receiver or a transmitter at the last bit of an error or overload frame delimiter
The CAN controller can generate a request overload frame automatically after each message sent to one of the CAN controller mailboxes. This feature is enabled by setting the OVL bit in the CAN_MR register.
Reactive overload frames are automatically handled by the CAN controller even if the OVL bit in the CAN_MR register is not set. An overload flag is generated in the same way as an error flag, but error counters do not increment.
41.7.5 Low-power Mode
In Low-power Mode, the CAN controller cannot send or receive messages. All mailboxes are inactive.
In Low-power Mode, the SLEEP signal in the CAN_SR register is set; otherwise, the WAKEUP signal in the CAN_SR register is set. These two fields are exclusive except after a CAN controller reset (WAKEUP and SLEEP are stuck at 0 after a reset). After power-up reset, the Low-power Mode is disabled and the WAKEUP bit is set in the CAN_SR register only after detection of 11 consecutive recessive bits on the bus.
41.7.5.1 Enabling Low-power Mode
A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR global register. The CAN controller enters Low-power Mode once all pending transmit messages are sent.
When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR register is set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while SLEEP is set.
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The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. The WAKEUP signal is automatically cleared once SLEEP is set.
Reception is disabled while the SLEEP signal is set to one in the CAN_SR register. It is important to note that those messages with higher priority than the last message transmitted can be received between the LPM command and entry in Low-power Mode.
Once in Low-power Mode, the CAN controller clock can be switched off by programming the chip’s Power Management
Controller (PMC). The CAN controller drains only the static current.
Error counters are disabled while the SLEEP signal is set to one.
Thus, to enter Low-power Mode, the software application must:
Set LPM field in the CAN_MR register
Wait for SLEEP signal rising
Now the CAN Controller clock can be disabled. This is done by programming the Power Management Controller (PMC).
Figure 41-8. Enabling Low-power Mode
Arbitration lost
CAN BUS
LPM
(CAN_MR)
SLEEP
(CAN_SR)
LPEN= 1
WAKEUP
(CAN_SR)
MRDY
(CAN_MSR1)
MRDY
(CAN_MSR3)
Mailbox 1
Mailbox 3
CAN_TIM 0x0
41.7.5.2 Disabling Low-power Mode
The CAN controller can be awake after detecting a CAN bus activity. Bus activity detection is done by an external module that may be embedded in the chip. When it is notified of a CAN bus activity, the software application disables Low-power
Mode by programming the CAN controller.
To disable Low-power Mode, the software application must:
Enable the CAN Controller clock. This is done by programming the Power Management Controller (PMC).
Clear the LPM field in the CAN_MR register
The CAN controller synchronizes itself with the bus activity by checking for eleven consecutive “recessive” bits. Once synchronized, the WAKEUP signal in the CAN_SR register is set.
Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while WAKEUP is set. The
SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. WAKEUP signal is automatically cleared once SLEEP is set.
If no message is being sent on the bus, then the CAN controller is able to send a message eleven bit times after disabling
Low-power Mode.
If there is bus activity when Low-power mode is disabled, the CAN controller is synchronized with the bus activity in the next interframe. The previous message is lost (see
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Figure 41-9. Disabling Low-power Mode
CAN BUS
LPM
(CAN_MR)
SLEEP
(CAN_SR)
WAKEUP
(CAN_SR)
Bus Activity Detected
Message lost Message x
Interframe synchronization
MRDY
(CAN_MSRx)
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41.8 Functional Description
41.8.1 CAN Controller Initialization
After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated by the Power
Management Controller (PMC) and the CAN controller interrupt line must be enabled by the interrupt controller (AIC).
The CAN controller must be initialized with the CAN network parameters. The CAN_BR register defines the sampling point in the bit time period. CAN_BR must be set before the CAN controller is enabled by setting the CANEN field in the
CAN_MR register.
The CAN controller is enabled by setting the CANEN flag in the CAN_MR register. At this stage, the internal CAN controller state machine is reset, error counters are reset to 0, error flags are reset to 0.
Once the CAN controller is enabled, bus synchronization is done automatically by scanning eleven recessive bits. The
WAKEUP bit in the CAN_SR register is automatically set to 1 when the CAN controller is synchronized (WAKEUP and
SLEEP are stuck at 0 after a reset).
The CAN controller can start listening to the network in Autobaud Mode. In this case, the error counters are locked and a mailbox may be configured in Receive Mode. By scanning error flags, the CAN_BR register values synchronized with the network. Once no error has been detected, the application disables the Autobaud Mode, clearing the ABM field in the
CAN_MR register.
Figure 41-10.Possible Initialization Procedure
Enable CAN Controller Clock
(PMC)
Enable CAN Controller Interrupt Line
(AIC)
Configure a Mailbox in Reception Mode
Change CAN_BR value
(ABM == 1 and CANEN == 1)
Errors ?
(CAN_SR or CAN_MSRx)
Yes
No
ABM = 0 and CANEN = 0
CANEN = 1 (ABM == 0)
End of Initialization
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41.8.2 CAN Controller Interrupt Handling
There are two different types of interrupts. One type of interrupt is a message-object related interrupt, the other is a system interrupt that handles errors or system-related interrupt sources.
All interrupt sources can be masked by writing the corresponding field in the CAN_IDR register. They can be unmasked by writing to the CAN_IER register. After a power-up reset, all interrupt sources are disabled (masked). The current mask status can be checked by reading the CAN_IMR register.
The CAN_SR register gives all interrupt source states.
The following events may initiate one of the two interrupts:
Message object interrupt
Data registers in the mailbox object are available to the application. In Receive Mode, a new message was received. In Transmit Mode, a message was transmitted successfully.
A sent transmission was aborted.
System interrupts
Bus off interrupt: The CAN module enters the bus off state.
Error passive interrupt: The CAN module enters Error Passive Mode.
Error Active Mode: The CAN module is neither in Error Passive Mode nor in Bus Off mode.
Warn Limit interrupt: The CAN module is in Error-active Mode, but at least one of its error counter value exceeds 96.
Wake-up interrupt: This interrupt is generated after a wake-up and a bus synchronization.
Sleep interrupt: This interrupt is generated after a Low-power Mode enable once all pending messages in transmission have been sent.
Internal timer counter overflow interrupt: This interrupt is generated when the internal timer rolls over.
Timestamp interrupt: This interrupt is generated after the reception or the transmission of a start of frame or an end of frame. The value of the internal counter is copied in the CAN_TIMESTP register.
All interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and the timestamp interrupt. These interrupts are cleared by reading the CAN_SR register.
41.8.3 CAN Controller Message Handling
41.8.3.1 Receive Handling
Two modes are available to configure a mailbox to receive messages. In Receive Mode, the first message received is stored in the mailbox data register. In Receive with Overwrite Mode, the last message received is stored in the mailbox.
Simple Receive Mailbox
A mailbox is in Receive Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and
Message Acceptance Mask must be set before the Receive Mode is enabled.
After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register.
Message data are stored in the mailbox data register until the software application notifies that data processing has ended. This is done by asking for a new transfer command, setting the MTCR flag in the CAN_MCRx register. This automatically clears the MRDY signal.
The MMI flag in the CAN_MSRx register notifies the software that a message has been lost by the mailbox. This flag is set when messages are received while MRDY is set in the CAN_MSRx register. This flag is cleared by reading the
CAN_MSRs register. A receive mailbox prevents from overwriting the first message by new ones while MRDY flag is set
in the CAN_MSRx register. See Figure 41-11 .
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Figure 41-11.Receive Mailbox
Message ID = CAN_MIDx
CAN BUS
MRDY
(CAN_MSRx)
MMI
(CAN_MSRx)
Message 1 Message 2 lost Message 3
(CAN_MDLx
CAN_MDHx)
MTCR
(CAN_MCRx)
Message 1 Message 3
Reading CAN_MSRx
Reading CAN_MDHx & CAN_MDLx
Writing CAN_MCRx
Note: In the case of ARM architecture, CAN_MSRx, CAN_MDLx, CAN_MDHx can be read using an optimized ldm assembler instruction.
Receive with Overwrite Mailbox
A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx register has been configured.
Message ID and Message Acceptance masks must be set before Receive Mode is enabled.
After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt is masked depending on the mailbox flag in the CAN_IMR global register.
If a new message is received while the MRDY flag is set, this new message is stored in the mailbox data register, overwriting the previous message. The MMI flag in the CAN_MSRx register notifies the software that a message has been dropped by the mailbox. This flag is cleared when reading the CAN_MSRx register.
The CAN controller may store a new message in the CAN data registers while the application reads them. To check that
CAN_MDHx and CAN_MDLx do not belong to different messages, the application must check the MMI field in the
CAN_MSRx register before and after reading CAN_MDHx and CAN_MDLx. If the MMI flag is set again after the data
).
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Figure 41-12.Receive with Overwrite Mailbox
Message ID = CAN_MIDx
CAN BUS
MRDY
(CAN_MSRx)
MMI
(CAN_MSRx)
Message 1 Message 2 Message 3 Message 4
(CAN_MDLx
CAN_MDHx)
MTCR
(CAN_MCRx)
Message 1 Message 2 Message 3 Message 4
Reading CAN_MSRx
Reading CAN_MDHx & CAN_MDLx
Writing CAN_MCRx
Chaining Mailboxes
Several mailboxes may be used to receive a buffer split into several messages with the same ID. In this case, the mailbox with the lowest number is serviced first. In the receive and receive with overwrite modes, the field PRIOR in the
CAN_MMRx register has no effect. If Mailbox 0 and Mailbox 5 accept messages with the same ID, the first message is received by Mailbox 0 and the second message is received by Mailbox 5. Mailbox 0 must be configured in Receive Mode
(i.e., the first message received is considered) and Mailbox 5 must be configured in Receive with Overwrite Mode.
Mailbox 0 cannot be configured in Receive with Overwrite Mode; otherwise, all messages are accepted by this mailbox and Mailbox 5 is never serviced.
If several mailboxes are chained to receive a buffer split into several messages, all mailboxes except the last one (with the highest number) must be configured in Receive Mode. The first message received is handled by the first mailbox, the second one is refused by the first mailbox and accepted by the second mailbox, the last message is accepted by the last
mailbox and refused by previous ones (see Figure 41-13
).
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Figure 41-13.Chaining Three Mailboxes to Receive a Buffer Split into Three Messages
Buffer split in 3 messages
CAN BUS
MRDY
(CAN_MSRx)
MMI
(CAN_MSRx)
Message s1 Message s2 Message s3
MRDY
(CAN_MSRy)
MMI
(CAN_MSRy)
MRDY
(CAN_MSRz)
MMI
(CAN_MSRz)
Reading CAN_MSRx, CAN_MSRy and CAN_MSRz
Reading CAN_MDH & CAN_MDL for mailboxes x, y and z
Writing MBx MBy MBz in CAN_TCR
If the number of mailboxes is not sufficient (the MMI flag of the last mailbox raises), the user must read each data received on the last mailbox in order to retrieve all the messages of the buffer split (see
).
Figure 41-14.Chaining Three Mailboxes to Receive a Buffer Split into Four Messages
Buffer split in 4 messages
Message s1 Message s2 Message s3 Message s4 CAN BUS
MRDY
(CAN_MSRx)
MMI
(CAN_MSRx)
MRDY
(CAN_MSRy)
MMI
(CAN_MSRy)
MRDY
(CAN_MSRz)
MMI
(CAN_MSRz)
Reading CAN_MSRx, CAN_MSRy and CAN_MSRz
Reading CAN_MDH & CAN_MDL for mailboxes x, y and z
Writing MBx MBy MBz in CAN_TCR
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41.8.3.2 Transmission Handling
A mailbox is in Transmit Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and
Message Acceptance mask must be set before Receive Mode is enabled.
After Transmit Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first command is sent. When the MRDY flag is set, the software application can prepare a message to be sent by writing to the CAN_MDx registers. The message is sent once the software asks for a transfer command setting the MTCR bit and the message data length in the CAN_MCRx register.
The MRDY flag remains at zero as long as the message has not been sent or aborted. It is important to note that no access to the mailbox data register is allowed while the MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register.
It is also possible to send a remote frame setting the MRTR bit instead of setting the MDLC field. The answer to the remote frame is handled by another reception mailbox. In this case, the device acts as a consumer but with the help of two mailboxes. It is possible to handle the remote frame emission and the answer reception using only one mailbox configured in Consumer Mode. Refer to the section
“Remote Frame Handling” on page 888 .
Several messages can try to win the bus arbitration in the same time. The message with the highest priority is sent first.
Several transfer request commands can be generated at the same time by setting MBx bits in the CAN_TCR register.
The priority is set in the PRIOR field of the CAN_MMRx register. Priority 0 is the highest priority, priority 15 is the lowest priority. Thus it is possible to use a part of the message ID to set the PRIOR field. If two mailboxes have the same priority, the message of the mailbox with the lowest number is sent first. Thus if mailbox 0 and mailbox 5 have the same priority and have a message to send at the same time, then the message of the mailbox 0 is sent first.
Setting the MACR bit in the CAN_MCRx register aborts the transmission. Transmission for several mailboxes can be aborted by writing MBx fields in the CAN_MACR register. If the message is being sent when the abort command is set, then the application is notified by the MRDY bit set and not the MABT in the CAN_MSRx register. Otherwise, if the message has not been sent, then the MRDY and the MABT are set in the CAN_MSR register.
When the bus arbitration is lost by a mailbox message, the CAN controller tries to win the next bus arbitration with the same message if this one still has the highest priority. Messages to be sent are re-tried automatically until they win the bus arbitration. This feature can be disabled by setting the bit DRPT in the CAN_MR register. In this case if the message was not sent the first time it was transmitted to the CAN transceiver, it is automatically aborted. The MABT flag is set in the CAN_MSRx register until the next transfer command.
Figure 41-15 shows three MBx message attempts being made (MRDY of MBx set to 0).
The first MBx message is sent, the second is aborted and the last one is trying to be aborted but too late because it has already been transmitted to the CAN transceiver.
Figure 41-15.Transmitting Messages
MBx message MBx message CAN BUS
MRDY
(CAN_MSRx)
MABT
(CAN_MSRx)
MTCR
(CAN_MCRx)
MACR
(CAN_MCRx)
Reading CAN_MSRx
Writing CAN_MDHx &
CAN_MDLx
Abort MBx message Try to Abort MBx message
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41.8.3.3 Remote Frame Handling
Producer/consumer model is an efficient means of handling broadcasted messages. The push model allows a producer to broadcast messages; the pull model allows a customer to ask for messages.
Figure 41-16.Producer / Consumer Model
PUSH MODEL
Producer Consumer
Indication(s)
Request CAN Data Frame
PULL MODEL
Producer
Indications
CAN Remote Frame
Consumer
Request(s)
Response
CAN Data Frame
Confirmation(s)
In Pull Mode, a consumer transmits a remote frame to the producer. When the producer receives a remote frame, it sends the answer accepted by one or many consumers. Using transmit and receive mailboxes, a consumer must dedicate two mailboxes, one in Transmit Mode to send remote frames, and at least one in Receive Mode to capture the producer’s answer. The same structure is applicable to a producer: one reception mailbox is required to get the remote frame and one transmit mailbox to answer.
Mailboxes can be configured in Producer or Consumer Mode. A lonely mailbox can handle the remote frame and the answer. With 8 mailboxes, the CAN controller can handle 8 independent producers/consumers.
Producer Configuration
A mailbox is in Producer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and
Message Acceptance masks must be set before Receive Mode is enabled.
After Producer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first transfer command. The software application prepares data to be sent by writing to the CAN_MDHx and the CAN_MDLx registers, then by setting the MTCR bit in the CAN_MCRx register. Data is sent after the reception of a remote frame as soon as it wins the bus arbitration.
The MRDY flag remains at zero as long as the message has not been sent or aborted. No access to the mailbox data register can be done while MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register.
If a remote frame is received while no data are ready to be sent (signal MRDY set in the CAN_MSRx register), then the
MMI signal is set in the CAN_MSRx register. This bit is cleared by reading the CAN_MSRx register.
The MRTR field in the CAN_MSRx register has no meaning. This field is used only when using Receive and Receive with
Overwrite modes.
After a remote frame has been received, the mailbox functions like a transmit mailbox. The message with the highest priority is sent first. The transmitted message may be aborted by setting the MACR bit in the CAN_MCR register. Please refer to the section
“Transmission Handling” on page 887
.
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Figure 41-17.Producer Handling
Remote Frame CAN BUS
MRDY
(CAN_MSRx)
MMI
(CAN_MSRx)
MTCR
(CAN_MCRx)
Message 1 Remote Frame
Reading CAN_MSRx
Remote Frame Message 2
(CAN_MDLx
CAN_MDHx)
Message 1 Message 2
Consumer Configuration
A mailbox is in Consumer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and
Message Acceptance masks must be set before Receive Mode is enabled.
After Consumer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first transfer request command. The software application sends a remote frame by setting the MTCR bit in the CAN_MCRx register or the MBx bit in the global CAN_TCR register. The application is notified of the answer by the MRDY flag set in the
CAN_MSRx register. The application can read the data contents in the CAN_MDHx and CAN_MDLx registers. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register.
The MRTR bit in the CAN_MCRx register has no effect. This field is used only when using Transmit Mode.
After a remote frame has been sent, the consumer mailbox functions as a reception mailbox. The first message received is stored in the mailbox data registers. If other messages intended for this mailbox have been sent while the MRDY flag is set in the CAN_MSRx register, they will be lost. The application is notified by reading the MMI field in the CAN_MSRx register. The read operation automatically clears the MMI flag.
If several messages are answered by the Producer, the CAN controller may have one mailbox in consumer configuration, zero or several mailboxes in Receive Mode and one mailbox in Receive with Overwrite Mode. In this case, the consumer mailbox must have a lower number than the Receive with Overwrite mailbox. The transfer command can be triggered for all mailboxes at the same time by setting several MBx fields in the CAN_TCR register.
Figure 41-18.Consumer Handling
Remote Frame Message x Remote Frame Message y
CAN BUS
MRDY
(CAN_MSRx)
MMI
(CAN_MSRx)
MTCR
(CAN_MCRx)
(CAN_MDLx
CAN_MDHx)
Message x Message y
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41.8.4 CAN Controller Timing Modes
Using the free running 16-bit internal timer, the CAN controller can be set in one of the two following timing modes:
Timestamping Mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame.
Time Triggered Mode: The mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger.
Timestamping Mode is enabled by clearing the TTM bit in the CAN_MR register. Time Triggered Mode is enabled by setting the TTM bit in the CAN_MR register.
41.8.4.1 Timestamping Mode
Each mailbox has its own timestamp value. Each time a message is sent or received by a mailbox, the 16-bit value
MTIMESTAMP of the CAN_TIMESTP register is transferred to the LSB bits of the CAN_MSRx register. The value read in the CAN_MSRx register corresponds to the internal timer value at the Start Of Frame or the End Of Frame of the message handled by the mailbox.
Figure 41-19.Mailbox Timestamp
Start of Frame End of Frame
CAN BUS
CAN_TIM
Message 1
Message 2
TEOF
(CAN_MR)
TIMESTAMP
(CAN_TSTP)
MTIMESTAMP
(CAN_MSRx)
MTIMESTAMP
(CAN_MSRy)
Timestamp 1
Timestamp 1
Timestamp 2
Timestamp 2
41.8.4.2 Time Triggered Mode
In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts with a reference message. Each time a window is defined from the reference message, a transmit operation should occur within a predefined time window. A mailbox must not win the arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time window.
Figure 41-20.Time Triggered Principle
Time Cycle
Reference
Message
Reference
Message
Time Windows for Messages
Global Time
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Time Trigger Mode is enabled by setting the TTM field in the CAN_MR register. In Time Triggered Mode, as in
Timestamp Mode, the CAN_TIMESTP field captures the values of the internal counter, but the MTIMESTAMP fields in the CAN_MSRx registers are not active and are read at 0.
Synchronization by a Reference Message
In Time Triggered Mode, the internal timer counter is automatically reset when a new message is received in the last mailbox. This reset occurs after the reception of the End Of Frame on the rising edge of the MRDY signal in the
CAN_MSRx register. This allows synchronization of the internal timer counter with the reception of a reference message and the start a new time window.
Transmitting within a Time Window
A time mark is defined for each mailbox. It is defined in the 16-bit MTIMEMARK field of the CAN_MMRx register. At each internal timer clock cycle, the value of the CAN_TIM is compared with each mailbox time mark. When the internal timer counter reaches the MTIMEMARK value, an internal timer event for the mailbox is generated for the mailbox.
In Time Triggered Mode, transmit operations are delayed until the internal timer event for the mailbox. The application prepares a message to be sent by setting the MTCR in the CAN_MCRx register. The message is not sent until the
CAN_TIM value is less than the MTIMEMARK value defined in the CAN_MMRx register.
If the transmit operation is failed, i.e., the message loses the bus arbitration and the next transmit attempt is delayed until the next internal time trigger event. This prevents overlapping the next time window, but the message is still pending and is retried in the next time window when CAN_TIM value equals the MTIMEMARK value. It is also possible to prevent a retry by setting the DRPT field in the CAN_MR register.
Freezing the Internal Timer Counter
The internal counter can be frozen by setting TIMFRZ in the CAN_MR register. This prevents an unexpected roll-over when the counter reaches FFFFh. When this occurs, it automatically freezes until a new reset is issued, either due to a message received in the last mailbox or any other reset counter operations. The TOVF bit in the CAN_SR register is set when the counter is frozen. The TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register. Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated when TOVF is set.
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Figure 41-21.Time Triggered Operations
CAN BUS
CAN_TIM
Reference
Message
End of Frame
Message x
Arbitration Lost
Message y
Internal Counter Reset
Cleared by software
MRDY
(CAN_MSRlast_mailbox_number)
Timer Event x
MRDY
(CAN_MSRx)
MTIMEMARKx == CAN_TIM
MTIMEMARKy == CAN_TIM
Timer Event y
MRDY
(CAN_MSRy)
Time Window
Basic Cycle
Message y
Arbitration Win
CAN BUS
CAN_TIM
Reference
Message
End of Frame
Internal Counter Reset
Message x
Message x
Arbitration Win
Cleared by software
MRDY
(CAN_MSRlast_mailbox_number)
Timer Event x
MRDY
(CAN_MSRx)
MTIMEMARKx == CAN_TIM
Time Window
Basic Cycle
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41.8.5 Write Protected Registers
To prevent any single software error that may corrupt CAN behavior, the registers listed below can be write-protected by setting the WPEN bit in the CAN Write Protection Mode Register (CAN_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the CAN Write Protection Status Register
(CAN_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset after reading the CAN Write Protection Status Register (CAN_WPSR).
List of the write-protected registers:
Section 41.9.1 “CAN Mode Register” on page 895
Section 41.9.6 “CAN Baudrate Register” on page 905
Section 41.9.14 “CAN Message Mode Register” on page 913
Section 41.9.15 “CAN Message Acceptance Mask Register” on page 914
Section 41.9.16 “CAN Message ID Register” on page 915
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41.9 Controller Area Network (CAN) User Interface
Table 41-6. Register Mapping
Offset
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C - 0x00E0
0x00E4
0x00E8
0x00EC - 0x01FC
0x0200 + MB * 0x20 + 0x00
0x0200 + MB * 0x20 + 0x04
0x0200 + MB * 0x20 + 0x08
0x0200 + MB * 0x20 + 0x0C
0x0200 + MB * 0x20 + 0x10
0x0200 + MB * 0x20 + 0x14
Register
Mode Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Status Register
Baudrate Register
Timer Register
Timestamp Register
Error Counter Register
Transfer Command Register
Abort Command Register
Reserved
Write Protect Mode Register
Write Protect Status Register
Reserved
Mailbox Acceptance Mask Register
Mailbox ID Register
Mailbox Family ID Register
Mailbox Status Register
Mailbox Data Low Register
0x0200 + MB * 0x20 + 0x18
0x0200 + MB * 0x20 + 0x1C
Mailbox Data High Register
Mailbox Control Register
Note: 1. Mailbox number ranges from 0 to 7.
Name
CAN_MR
CAN_IER
CAN_IDR
CAN_IMR
CAN_SR
CAN_BR
CAN_TIM
CAN_TIMESTP
CAN_ECR
CAN_TCR
CAN_ACR
–
CAN_WPMR
CAN_WPSR
–
CAN_MMR
CAN_MAM
CAN_MID
CAN_MFID
CAN_MSR
CAN_MDL
CAN_MDH
CAN_MCR
Access
Read-write
Write-only
Write-only
Read-only
Read-only
Read-write
Read-only
Read-only
Read-only
Write-only
Write-only
–
Read-write
Read-only
–
Read-write
Read-write
Read-write
Read-only
Read-only
Read-write
Read-write
Write-only
-
-
–
0x0
0x0
0x0
0x0
0x0
Reset
0x0
-
-
0x0
0x0
0x0
0x0
0x0
0x0
0x0
–
0x0
0x0
0x0
-
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41.9.1 CAN Mode Register
Name:
Address:
Access:
CAN_MR
0xF8000000 (0), 0xF8004000 (1)
Read-write
31
–
23
–
15
–
7
DRPT
30
–
22
–
14
–
6
TIMFRZ
13
–
5
TTM
29
–
21
–
28
–
20
–
12
–
4
TEOF
11
–
3
OVL
27
–
19
–
26
18
–
10
–
2
ABM
25
17
–
9
–
1
LPM
24
16
–
8
–
0
CANEN
• CANEN: CAN Controller Enable
0: The CAN Controller is disabled.
1: The CAN Controller is enabled.
• LPM: Disable/Enable Low Power Mode
0: Disable Low Power Mode.
1: Enable Low Power Mode
CAN controller enters Low Power Mode once all pending messages have been transmitted.
• ABM: Disable/Enable Autobaud/Listen mode
0: Disable Autobaud/listen mode.
1: Enable Autobaud/listen mode.
• OVL: Disable/Enable Overload Frame
0: No overload frame is generated.
1: An overload frame is generated after each successful reception for mailboxes configured in Receive with/without overwrite
Mode, Producer and Consumer.
• TEOF: Timestamp Messages at Each End of Frame
0: The value of CAN_TIM is captured in the CAN_TIMESTP register at each Start Of Frame.
1: The value of CAN_TIM is captured in the CAN_TIMESTP register at each End Of Frame.
• TTM: Disable/Enable Time Triggered Mode
0: Time Triggered Mode is disabled.
1: Time Triggered Mode is enabled.
• TIMFRZ: Enable Timer Freeze
0: The internal timer continues to be incremented after it reached 0xFFFF.
1: The internal timer stops incrementing after reaching 0xFFFF. It is restarted after a timer reset. See
• DRPT: Disable Repeat
0: When a transmit mailbox loses the bus arbitration, the transfer request remains pending.
1: When a transmit mailbox lose the bus arbitration, the transfer request is automatically aborted. It automatically raises the MABT and MRDT flags in the corresponding CAN_MSRx.
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41.9.2 CAN Interrupt Enable Register
Name:
Address:
Access:
CAN_IER
0xF8000004 (0), 0xF8004004 (1)
Write-only
31
–
23
TSTP
15
–
7
MB7
30
–
22
TOVF
14
–
6
MB6
29
–
21
WAKEUP
13
–
5
MB5
• MBx: Mailbox x Interrupt Enable
0: No effect.
1: Enable Mailbox x interrupt.
• ERRA: Error Active Mode Interrupt Enable
0: No effect.
1: Enable ERRA interrupt.
• WARN: Warning Limit Interrupt Enable
0: No effect.
1: Enable WARN interrupt.
• ERRP: Error Passive Mode Interrupt Enable
0: No effect.
1: Enable ERRP interrupt.
• BOFF: Bus Off Mode Interrupt Enable
0: No effect.
1: Enable BOFF interrupt.
• SLEEP: Sleep Interrupt Enable
0: No effect.
1: Enable SLEEP interrupt.
• WAKEUP: Wakeup Interrupt Enable
0: No effect.
1: Enable SLEEP interrupt.
• TOVF: Timer Overflow Interrupt Enable
0: No effect.
1: Enable TOVF interrupt.
28
BERR
20
SLEEP
12
–
4
MB4
27
FERR
19
BOFF
11
–
3
MB3
26
AERR
18
ERRP
10
–
2
MB2
25
SERR
17
WARN
9
–
1
MB1
24
CERR
16
ERRA
8
–
0
MB0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
896
• TSTP: TimeStamp Interrupt Enable
0: No effect.
1: Enable TSTP interrupt.
• CERR: CRC Error Interrupt Enable
0: No effect.
1: Enable CRC Error interrupt.
• SERR: Stuffing Error Interrupt Enable
0: No effect.
1: Enable Stuffing Error interrupt.
• AERR: Acknowledgment Error Interrupt Enable
0: No effect.
1: Enable Acknowledgment Error interrupt.
• FERR: Form Error Interrupt Enable
0: No effect.
1: Enable Form Error interrupt.
• BERR: Bit Error Interrupt Enable
0: No effect.
1: Enable Bit Error interrupt.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
897
41.9.3 CAN Interrupt Disable Register
Name:
Address:
Access:
CAN_IDR
0xF8000008 (0), 0xF8004008 (1)
Write-only
31
–
23
TSTP
15
–
7
MB7
30
–
22
TOVF
14
–
6
MB6
29
–
21
WAKEUP
13
–
5
MB5
• MBx: Mailbox x Interrupt Disable
0: No effect.
1: Disable Mailbox x interrupt.
• ERRA: Error Active Mode Interrupt Disable
0: No effect.
1: Disable ERRA interrupt.
• WARN: Warning Limit Interrupt Disable
0: No effect.
1: Disable WARN interrupt.
• ERRP: Error Passive Mode Interrupt Disable
0: No effect.
1: Disable ERRP interrupt.
• BOFF: Bus Off Mode Interrupt Disable
0: No effect.
1: Disable BOFF interrupt.
• SLEEP: Sleep Interrupt Disable
0: No effect.
1: Disable SLEEP interrupt.
• WAKEUP: Wakeup Interrupt Disable
0: No effect.
1: Disable WAKEUP interrupt.
• TOVF: Timer Overflow Interrupt
0: No effect.
1: Disable TOVF interrupt.
28
BERR
20
SLEEP
12
–
4
MB4
27
FERR
19
BOFF
11
–
3
MB3
26
AERR
18
ERRP
10
–
2
MB2
25
SERR
17
WARN
9
–
1
MB1
24
CERR
16
ERRA
8
–
0
MB0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
898
• TSTP: TimeStamp Interrupt Disable
0: No effect.
1: Disable TSTP interrupt.
• CERR: CRC Error Interrupt Disable
0: No effect.
1: Disable CRC Error interrupt.
• SERR: Stuffing Error Interrupt Disable
0: No effect.
1: Disable Stuffing Error interrupt.
• AERR: Acknowledgment Error Interrupt Disable
0: No effect.
1: Disable Acknowledgment Error interrupt.
• FERR: Form Error Interrupt Disable
0: No effect.
1: Disable Form Error interrupt.
• BERR: Bit Error Interrupt Disable
0: No effect.
1: Disable Bit Error interrupt.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
899
41.9.4 CAN Interrupt Mask Register
Name:
Address:
Access:
CAN_IMR
0xF800000C (0), 0xF800400C (1)
Read-only
31
–
23
TSTP
15
–
7
MB7
30
–
22
TOVF
14
–
6
MB6
29
–
21
WAKEUP
13
–
5
MB5
28
BERR
20
SLEEP
12
–
4
MB4
• MBx: Mailbox x Interrupt Mask
0: Mailbox x interrupt is disabled.
1: Mailbox x interrupt is enabled.
• ERRA: Error Active Mode Interrupt Mask
0: ERRA interrupt is disabled.
1: ERRA interrupt is enabled.
• WARN: Warning Limit Interrupt Mask
0: Warning Limit interrupt is disabled.
1: Warning Limit interrupt is enabled.
• ERRP: Error Passive Mode Interrupt Mask
0: ERRP interrupt is disabled.
1: ERRP interrupt is enabled.
• BOFF: Bus Off Mode Interrupt Mask
0: BOFF interrupt is disabled.
1: BOFF interrupt is enabled.
• SLEEP: Sleep Interrupt Mask
0: SLEEP interrupt is disabled.
1: SLEEP interrupt is enabled.
• WAKEUP: Wakeup Interrupt Mask
0: WAKEUP interrupt is disabled.
1: WAKEUP interrupt is enabled.
• TOVF: Timer Overflow Interrupt Mask
0: TOVF interrupt is disabled.
1: TOVF interrupt is enabled.
27
FERR
19
BOFF
11
–
3
MB3
26
AERR
18
ERRP
10
–
2
MB2
25
SERR
17
WARN
9
–
1
MB1
24
CERR
16
ERRA
8
–
0
MB0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
900
• TSTP: Timestamp Interrupt Mask
0: TSTP interrupt is disabled.
1: TSTP interrupt is enabled.
• CERR: CRC Error Interrupt Mask
0: CRC Error interrupt is disabled.
1: CRC Error interrupt is enabled.
• SERR: Stuffing Error Interrupt Mask
0: Bit Stuffing Error interrupt is disabled.
1: Bit Stuffing Error interrupt is enabled.
• AERR: Acknowledgment Error Interrupt Mask
0: Acknowledgment Error interrupt is disabled.
1: Acknowledgment Error interrupt is enabled.
• FERR: Form Error Interrupt Mask
0: Form Error interrupt is disabled.
1: Form Error interrupt is enabled.
• BERR: Bit Error Interrupt Mask
0: Bit Error interrupt is disabled.
1: Bit Error interrupt is enabled.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
901
41.9.5 CAN Status Register
Name:
Address:
Access:
CAN_SR
0xF8000010 (0), 0xF8004010 (1)
Read-only
31
OVLSY
23
TSTP
15
–
7
MB7
30
TBSY
22
TOVF
14
–
6
MB6
29
RBSY
21
WAKEUP
13
–
5
MB5
28
BERR
20
SLEEP
12
–
4
MB4
27
FERR
19
BOFF
11
–
3
MB3
26
AERR
18
ERRP
10
–
2
MB2
25
SERR
17
WARN
9
–
1
MB1
24
CERR
16
ERRA
8
–
0
MB0
• MBx: Mailbox x Event
0: No event occurred on Mailbox x.
1: An event occurred on Mailbox x.
An event corresponds to MRDY, MABT fields in the CAN_MSRx register.
• ERRA: Error Active Mode
0: CAN controller has not reached Error Active Mode since the last read of CAN_SR.
1: CAN controller has reached Error Active Mode since the last read of CAN_SR.
This flag is automatically cleared by reading CAN_SR register.
This flag is set depending on TEC and REC counter values. It is set when a node is neither in Error Passive Mode nor in Bus Off
Mode.
• WARN: Warning Limit
0: CAN controller Warning Limit has not been reached since the last read of CAN_SR.
1: CAN controller Warning Limit has been reached since the last read of CAN_SR.
This flag is automatically cleared by reading CAN_SR register.
This flag is set depending on TEC and REC counter values. It is set when at least one of the counter values has reached a value greater or equal to 96.
• ERRP: Error Passive Mode
0: CAN controller has not reached Error Passive Mode since the last read of CAN_SR.
1: CAN controller has reached Error Passive Mode since the last read of CAN_SR.
This flag is set depending on TEC and REC counters values.
This flag is automatically cleared by reading CAN_SR register.
A node is in error passive state when TEC counter is greater or equal to 128 (decimal) or when the REC counter is greater or equal to 128 (decimal).
• BOFF: Bus Off Mode
0: CAN controller has not reached Bus Off Mode.
1: CAN controller has reached Bus Off Mode since the last read of CAN_SR.
This flag is automatically cleared by reading CAN_SR register.
This flag is set depending on TEC counter value. A node is in bus off state when TEC counter is greater or equal to 256 (decimal).
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
902
• SLEEP: CAN controller in Low power Mode
0: CAN controller is not in low power mode.
1: CAN controller is in low power mode.
This flag is automatically reset when Low power mode is disabled
• WAKEUP: CAN controller is not in Low power Mode
0: CAN controller is in low power mode.
1: CAN controller is not in low power mode.
When a WAKEUP event occurs, the CAN controller is synchronized with the bus activity. Messages can be transmitted or received. The CAN controller clock must be available when a WAKEUP event occurs. This flag is automatically reset when the
CAN Controller enters Low Power mode.
• TOVF: Timer Overflow
0: The timer has not rolled-over FFFFh to 0000h.
1: The timer rolls-over FFFFh to 0000h.
This flag is automatically cleared by reading CAN_SR register.
• TSTP Timestamp
0: No bus activity has been detected.
1: A start of frame or an end of frame has been detected (according to the TEOF field in the CAN_MR register).
This flag is automatically cleared by reading the CAN_SR register.
• CERR: Mailbox CRC Error
0: No CRC error occurred during a previous transfer.
1: A CRC error occurred during a previous transfer.
A CRC error has been detected during last reception.
This flag is automatically cleared by reading CAN_SR register.
• SERR: Mailbox Stuffing Error
0: No stuffing error occurred during a previous transfer.
1: A stuffing error occurred during a previous transfer.
A form error results from the detection of more than five consecutive bit with the same polarity.
This flag is automatically cleared by reading CAN_SR register.
• AERR: Acknowledgment Error
0: No acknowledgment error occurred during a previous transfer.
1: An acknowledgment error occurred during a previous transfer.
An acknowledgment error is detected when no detection of the dominant bit in the acknowledge slot occurs.
This flag is automatically cleared by reading CAN_SR register.
• FERR: Form Error
0: No form error occurred during a previous transfer
1: A form error occurred during a previous transfer
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
903
A form error results from violations on one or more of the fixed form of the following bit fields:
– CRC delimiter
– ACK delimiter
– End of frame
– Error delimiter
– Overload delimiter
This flag is automatically cleared by reading CAN_SR register.
• BERR: Bit Error
0: No bit error occurred during a previous transfer.
1: A bit error occurred during a previous transfer.
A bit error is set when the bit value monitored on the line is different from the bit value sent.
This flag is automatically cleared by reading CAN_SR register.
• RBSY: Receiver busy
0: CAN receiver is not receiving a frame.
1: CAN receiver is receiving a frame.
Receiver busy. This status bit is set by hardware while CAN receiver is acquiring or monitoring a frame (remote, data, overload or error frame). It is automatically reset when CAN is not receiving.
• TBSY: Transmitter busy
0: CAN transmitter is not transmitting a frame.
1: CAN transmitter is transmitting a frame.
Transmitter busy. This status bit is set by hardware while CAN transmitter is generating a frame (remote, data, overload or error frame). It is automatically reset when CAN is not transmitting.
• OVLSY: Overload busy
0: CAN transmitter is not transmitting an overload frame.
1: CAN transmitter is transmitting a overload frame.
It is automatically reset when the bus is not transmitting an overload frame.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
904
41.9.6 CAN Baudrate Register
Name:
Address:
Access:
CAN_BR
0xF8000014 (0), 0xF8004014 (1)
Read-write
15
–
7
–
31
–
23
–
14
–
6
30
–
22
29
–
21
13
5
PHASE1
SJW
12
4
28
–
20
11
–
3
–
27
–
19
BRP
10
2
26
–
18
25
–
17
9
PROPAG
1
PHASE2
24
SMP
16
8
0
Any modification on one of the fields of the CAN_BR register must be done while CAN module is disabled.
• PHASE2: Phase 2 segment
This phase is used to compensate the edge phase error.
t
PHS2
= t
CSC
× ( PHASE2 + 1 )
Warning: PHASE2 value must be different from 0.
• PHASE1: Phase 1 segment
This phase is used to compensate for edge phase error.
t
PHS1
= t
CSC
× ( PHASE1 + 1 )
• PROPAG: Programming time segment
This part of the bit time is used to compensate for the physical delay times within the network.
t
PRS
= t
CSC
× ( PROPAG + 1 )
• SJW: Re-synchronization jump width
To compensate for phase shifts between clock oscillators of different controllers on bus. The controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum of clock cycles a bit period may be shortened or lengthened by re-synchronization.
t
SJW
= t
CSC
× ( SJW + 1 )
• BRP: Baudrate Prescaler.
This field allows user to program the period of the CAN system clock to determine the individual bit timing.
t
CSC
=
(
BRP + 1
) ⁄
MCK
The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized.
• SMP: Sampling Mode
0 (ONCE): The incoming bit stream is sampled once at sample point.
1 (THREE): The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point.
SMP Sampling Mode is automatically disabled if BRP = 0.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
905
41.9.7 CAN Timer Register
Name:
Address:
Access:
CAN_TIM
0xF8000018 (0), 0xF8004018 (1)
Read-only
31
–
23
–
15
7
30
–
22
–
14
6
29
–
21
–
13
5
28
–
20
–
12
4
TIMER
TIMER
27
–
19
–
11
3
• TIMER: Timer
This field represents the internal CAN controller 16-bit timer value.
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
–
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
906
41.9.8 CAN Timestamp Register
Name:
Address:
Access:
CAN_TIMESTP
0xF800001C (0), 0xF800401C (1)
Read-only
31
–
23
–
15
7
30
–
22
–
14
6
29
–
21
–
13
5
28
–
20
–
12
MTIMESTAMP
11
4 3
MTIMESTAMP
27
–
19
–
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
–
8
0
• MTIMESTAMP: Timestamp
This field carries the value of the internal CAN controller 16-bit timer value at the start or end of frame.
If the TEOF bit is cleared in the CAN_MR register, the internal Timer Counter value is captured in the MTIMESTAMP field at each start of frame else the value is captured at each end of frame. When the value is captured, the TSTP flag is set in the CAN_SR register. If the TSTP mask in the CAN_IMR register is set, an interrupt is generated while TSTP flag is set in the CAN_SR register. This flag is cleared by reading the CAN_SR register.
Note: The CAN_TIMESTP register is reset when the CAN is disabled then enabled thanks to the CANEN bit in the
CAN_MR.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
907
41.9.9 CAN Error Counter Register
Name:
Address:
Access:
CAN_ECR
0xF8000020 (0), 0xF8004020 (1)
Read-only
31
–
23
30
–
22
29
–
21
15
–
7
14
–
6
13
–
5
12
–
4
28
–
20
TEC
11
–
3
27
–
19
10
–
2
26
–
18
9
–
1
25
–
17
24
TEC
16
8
–
0
REC
• REC: Receive Error Counter
When a receiver detects an error, REC will be increased by one, except when the detected error is a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG.
When a receiver detects a dominant bit as the first bit after sending an ERROR FLAG, REC is increased by 8.
When a receiver detects a BIT ERROR while sending an ACTIVE ERROR FLAG, REC is increased by 8.
Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or
OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD
FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits, each receiver increases its REC by 8.
After successful reception of a message, REC is decreased by 1 if it was between 1 and 127. If REC was 0, it stays 0, and if it was greater than 127, then it is set to a value between 119 and 127.
• TEC: Transmit Error Counter
When a transmitter sends an ERROR FLAG, TEC is increased by 8 except when:
– The transmitter is error passive and detects an ACKNOWLEDGMENT ERROR because of not detecting a dominant ACK and does not detect a dominant bit while sending its PASSIVE ERROR FLAG.
– The transmitter sends an ERROR FLAG because a STUFF ERROR occurred during arbitration and should have been recessive and has been sent as recessive but monitored as dominant.
When a transmitter detects a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG, the TEC will be increased by 8.
Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or
OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD
FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits every transmitter increases its TEC by 8.
After a successful transmission the TEC is decreased by 1 unless it was already 0.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
908
41.9.10 CAN Transfer Command Register
Name:
Address:
Access:
CAN_TCR
0xF8000024 (0), 0xF8004024 (1)
Write-only
31
TIMRST
23
–
15
–
7
MB7
30
–
22
–
14
–
6
MB6
13
–
5
MB5
29
–
21
–
28
–
20
–
12
–
4
MB4
This register initializes several transfer requests at the same time.
• MBx: Transfer Request for Mailbox x
27
–
19
–
11
–
3
MB3
26
–
18
–
10
–
2
MB2
9
–
1
MB1
25
–
17
–
24
–
16
–
8
–
0
MB0
Mailbox Object Type
Receive
Receive with overwrite
Transmit
Consumer
Producer
Description
It receives the next message.
This triggers a new reception.
Sends data prepared in the mailbox as soon as possible.
Sends a remote frame.
Sends data prepared in the mailbox after receiving a remote frame from a consumer.
This flag clears the MRDY and MABT flags in the corresponding CAN_MSRx register.
When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn, starting with the mailbox with the highest priority. If several mailboxes have the same priority, then the mailbox with the lowest number is sent first (i.e.,
MB0 will be transferred before MB1).
• TIMRST: Timer Reset
Resets the internal timer counter. If the internal timer counter is frozen, this command automatically re-enables it. This command is useful in Time Triggered mode.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
909
41.9.11 CAN Abort Command Register
Name:
Address:
Access:
CAN_ACR
0xF8000028 (0), 0xF8004028 (1)
Write-only
31
–
23
–
15
–
7
MB7
30
–
22
–
14
–
6
MB6
13
–
5
MB5
29
–
21
–
28
–
20
–
12
–
4
MB4
This register initializes several abort requests at the same time.
• MBx: Abort Request for Mailbox x
27
–
19
–
11
–
3
MB3
26
–
18
–
10
–
2
MB2
Mailbox Object Type
Receive
Receive with overwrite
Transmit
Consumer
Producer
Description
No action
No action
Cancels transfer request if the message has not been transmitted to the
CAN transceiver.
Cancels the current transfer before the remote frame has been sent.
Cancels the current transfer. The next remote frame is not serviced.
It is possible to set MACR field (in the CAN_MCRx register) for each mailbox.
9
–
1
MB1
25
–
17
–
24
–
16
–
8
–
0
MB0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
910
41.9.12 CAN Write Protection Mode Register
Name:
Address:
Access:
CAN_WPMR
0xF80000E4 (0), 0xF80040E4 (1)
Read-write
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
WPEN
• WPEN: Write Protection Enable
0: The Write Protection is Disabled
1: The Write Protection is Enabled
• WPKEY: SPI Write Protection Key Password
If a value is written in WPEN, the value is taken into account only if WPKEY is written with “CAN” (CAN written in ASCII Code, ie
0x43414E in hexadecimal).
Protects the registers:
Section 41.9.1 “CAN Mode Register” on page 895
Section 41.9.6 “CAN Baudrate Register” on page 905
Section 41.9.14 “CAN Message Mode Register” on page 913
Section 41.9.15 “CAN Message Acceptance Mask Register” on page 914
Section 41.9.16 “CAN Message ID Register” on page 915
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
911
41.9.13 CAN Write Protection Status Register
Name:
Address:
Access:
CAN_WPSR
0xF80000E8 (0), 0xF80040E8 (1)
Read-only
31
-
30
-
29
-
23
-
15
7
-
22
-
14
6
-
21
-
13
5
-
28
-
20
-
12
WPVSRC
27
-
19
-
11
4
-
3
-
26
-
18
-
10
2
-
25
-
17
-
9
1
-
24
-
16
-
8
0
WPVS
• WPVS: Write Protection Violation Status
0: No Write Protect Violation has occurred since the last read of the CAN_WPSR register.
1: A Write Protect Violation has occurred since the last read of the CAN_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
This Field indicates the offset of the register concerned by the violation
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
912
41.9.14 CAN Message Mode Register
Name:
Address:
CAN_MMRx [x=0..7]
0xF8000200 (0)[0], 0xF8000220 (0)[1], 0xF8000240 (0)[2], 0xF8000260 (0)[3], 0xF8000280 (0)[4],
0xF80002A0 (0)[5], 0xF80002C0 (0)[6], 0xF80002E0 (0)[7], 0xF8004200 (1)[0], 0xF8004220 (1)[1], 0xF8004240
(1)[2], 0xF8004260 (1)[3], 0xF8004280 (1)[4], 0xF80042A0 (1)[5], 0xF80042C0 (1)[6], 0xF80042E0 (1)[7]
Read-write Access:
31
–
23
–
15
7
30
–
22
–
14
6
29
–
21
–
13
5
28
–
20
–
12
MTIMEMARK
27
–
19
11
4 3
MTIMEMARK
26
18
10
2
PRIOR
25
MOT
17
9
1
24
16
8
0
• MTIMEMARK: Mailbox Timemark
This field is active in Time Triggered Mode. Transmit operations are allowed when the internal timer counter reaches the Mailbox
Timemark. See “Transmitting within a Time Window” on page 891 .
In Timestamp Mode, MTIMEMARK is set to 0.
• PRIOR: Mailbox Priority
This field has no effect in receive and receive with overwrite modes. In these modes, the mailbox with the lowest number is serviced first.
When several mailboxes try to transmit a message at the same time, the mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., MBx0 is serviced before MBx 15 if they have the same priority).
• MOT: Mailbox Object Type
This field allows the user to define the type of the mailbox. All mailboxes are independently configurable. Five different types are possible for each mailbox:
Value
0
1
2
3
4
5
6
Name
MB_DISABLED
MB_RX
MB_RX_OVERWRITE
MB_TX
MB_CONSUMER
MB_PRODUCER
–
Description
Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
Transmit mailbox. Mailbox is configured for transmission.
Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit
Mailbox, i.e., it sends a remote frame and waits for an answer.
Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.
Reserved
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
913
41.9.15 CAN Message Acceptance Mask Register
Name:
Address:
CAN_MAMx [x=0..7]
0xF8000204 (0)[0], 0xF8000224 (0)[1], 0xF8000244 (0)[2], 0xF8000264 (0)[3], 0xF8000284 (0)[4],
0xF80002A4 (0)[5], 0xF80002C4 (0)[6], 0xF80002E4 (0)[7], 0xF8004204 (1)[0], 0xF8004224 (1)[1], 0xF8004244
(1)[2], 0xF8004264 (1)[3], 0xF8004284 (1)[4], 0xF80042A4 (1)[5], 0xF80042C4 (1)[6], 0xF80042E4 (1)[7]
Read-write Access:
31
–
23
30
–
22
29
MIDE
21
28
20
27
19
26
MIDvA
18
25
17
24
16
MIDvA MIDvB
15 14 13 12 11 10 9 8
MIDvB
7 6 5 4 3 2 1 0
MIDvB
To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MAMx registers.
• MIDvB: Complementary bits for identifier in extended frame mode
Acceptance mask for corresponding field of the message IDvB register of the mailbox.
• MIDvA: Identifier for standard frame mode
Acceptance mask for corresponding field of the message IDvA register of the mailbox.
• MIDE: Identifier Version
0: Compares IDvA from the received frame with the CAN_MIDx register masked with CAN_MAMx register.
1: Compares IDvA and IDvB from the received frame with the CAN_MIDx register masked with CAN_MAMx register.
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41.9.16 CAN Message ID Register
Name:
Address:
CAN_MIDx [x=0..7]
0xF8000208 (0)[0], 0xF8000228 (0)[1], 0xF8000248 (0)[2], 0xF8000268 (0)[3], 0xF8000288 (0)[4],
0xF80002A8 (0)[5], 0xF80002C8 (0)[6], 0xF80002E8 (0)[7], 0xF8004208 (1)[0], 0xF8004228 (1)[1], 0xF8004248
(1)[2], 0xF8004268 (1)[3], 0xF8004288 (1)[4], 0xF80042A8 (1)[5], 0xF80042C8 (1)[6], 0xF80042E8 (1)[7]
Read-write Access:
31
–
23
30
–
22
29
MIDE
21
28
20
27
19
26
MIDvA
18
25
17
24
16
MIDvA MIDvB
15 14 13 12 11 10 9 8
MIDvB
7 6 5 4 3 2 1 0
MIDvB
To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MIDx registers.
• MIDvB: Complementary Bits for Identifier in Extended Frame Mode
If MIDE is cleared, MIDvB value is 0.
• MIDE: Identifier Version
This bit allows the user to define the version of messages processed by the mailbox. If set, mailbox is dealing with version 2.0
Part B messages; otherwise, mailbox is dealing with version 2.0 Part A messages.
• MIDvA: Identifier for Standard Frame Mode
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41.9.17 CAN Message Family ID Register
Name:
Address:
CAN_MFIDx [x=0..7]
0xF800020C (0)[0], 0xF800022C (0)[1], 0xF800024C (0)[2], 0xF800026C (0)[3], 0xF800028C (0)[4],
0xF80002AC (0)[5], 0xF80002CC (0)[6], 0xF80002EC (0)[7], 0xF800420C (1)[0], 0xF800422C (1)[1],
0xF800424C (1)[2], 0xF800426C (1)[3], 0xF800428C (1)[4], 0xF80042AC (1)[5], 0xF80042CC (1)[6],
0xF80042EC (1)[7]
Read-only Access:
31
–
23
30
–
22
29
–
21
28
20
27
19
26
MFID
18
25
17
MFID
15 14 13 12 11 10 9
MFID
7 6 5 4 3 2 1
MFID
24
16
8
0
• MFID: Family ID
This field contains the concatenation of CAN_MIDx register bits masked by the CAN_MAMx register. This field is useful to speed up message ID decoding. The message acceptance procedure is described below.
As an example:
CAN_MIDx = 0x305A4321
CAN_MAMx = 0x3FF0F0FF
CAN_MFIDx = 0x000000A3
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41.9.18 CAN Message Status Register
Name:
Address:
CAN_MSRx [x=0..7]
0xF8000210 (0)[0], 0xF8000230 (0)[1], 0xF8000250 (0)[2], 0xF8000270 (0)[3], 0xF8000290 (0)[4],
0xF80002B0 (0)[5], 0xF80002D0 (0)[6], 0xF80002F0 (0)[7], 0xF8004210 (1)[0], 0xF8004230 (1)[1], 0xF8004250
(1)[2], 0xF8004270 (1)[3], 0xF8004290 (1)[4], 0xF80042B0 (1)[5], 0xF80042D0 (1)[6], 0xF80042F0 (1)[7]
Read-only Access:
31
–
23
MRDY
15
7
30
–
22
MABT
14
6
29
–
21
–
13
5
28
–
20
MRTR
12
MTIMESTAMP
11
4 3
MTIMESTAMP
27
–
19
26
–
18
10
2
MDLC
25
–
17
9
1
24
MMI
16
8
0
These register fields are updated each time a message transfer is received or aborted.
MMI is cleared by reading the CAN_MSRx register.
MRDY, MABT are cleared by writing MTCR or MACR in the CAN_MCRx register.
Warning: MRTR and MDLC state depends partly on the mailbox object type.
• MTIMESTAMP: Timer value
This field is updated only when time-triggered operations are disabled (TTM cleared in CAN_MR register). If the TEOF field in the
CAN_MR register is cleared, TIMESTAMP is the internal timer value at the start of frame of the last message received or sent by the mailbox. If the TEOF field in the CAN_MR register is set, TIMESTAMP is the internal timer value at the end of frame of the last message received or sent by the mailbox.
In Time Triggered Mode, MTIMESTAMP is set to 0.
• MDLC: Mailbox Data Length Code
Mailbox Object Type
Receive
Receive with overwrite
Transmit
Consumer
Producer
Description
Length of the first mailbox message received
Length of the last mailbox message received
No action
Length of the mailbox message received
Length of the mailbox message to be sent after the remote frame reception
• MRTR: Mailbox Remote Transmission Request
Mailbox Object Type Description
Receive The first frame received has the RTR bit set.
Receive with overwrite The last frame received has the RTR bit set.
Transmit Reserved
Consumer
Producer
Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 1.
Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 0.
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• MABT: Mailbox Message Abort
An interrupt is triggered when MABT is set.
0: Previous transfer is not aborted.
1: Previous transfer has been aborted.
This flag is cleared by writing to CAN_MCRx register
Mailbox Object Type Description
Receive Reserved
Receive with overwrite Reserved
Transmit Previous transfer has been aborted
Consumer
Producer
The remote frame transfer request has been aborted.
The response to the remote frame transfer has been aborted.
• MRDY: Mailbox Ready
An interrupt is triggered when MRDY is set.
0: Mailbox data registers can not be read/written by the software application. CAN_MDx are locked by the CAN_MDx.
1: Mailbox data registers can be read/written by the software application.
This flag is cleared by writing to CAN_MCRx register.
Mailbox Object Type Description
Receive
At least one message has been received since the last mailbox transfer order. Data from the first frame received can be read in the CAN_MDxx registers.
After setting the MOT field in the CAN_MMR, MRDY is reset to 0.
Receive with overwrite
At least one frame has been received since the last mailbox transfer order. Data from the last frame received can be read in the CAN_MDxx registers.
After setting the MOT field in the CAN_MMR, MRDY is reset to 0.
Transmit
Consumer
Producer
Mailbox data have been transmitted.
After setting the MOT field in the CAN_MMR, MRDY is reset to 1.
At least one message has been received since the last mailbox transfer order. Data from the first message received can be read in the CAN_MDxx registers.
After setting the MOT field in the CAN_MMR, MRDY is reset to 0.
A remote frame has been received, mailbox data have been transmitted.
After setting the MOT field in the CAN_MMR, MRDY is reset to 1.
• MMI: Mailbox Message Ignored
0: No message has been ignored during the previous transfer
1: At least one message has been ignored during the previous transfer
Cleared by reading the CAN_MSRx register
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.
Mailbox Object Type
Receive
Receive with overwrite
Transmit
Consumer
Producer
Description
Set when at least two messages intended for the mailbox have been sent. The first one is available in the mailbox data register. Others have been ignored. A mailbox with a lower priority may have accepted the message.
Set when at least two messages intended for the mailbox have been sent. The last one is available in the mailbox data register. Previous ones have been lost.
Reserved
A remote frame has been sent by the mailbox but several messages have been received. The first one is available in the mailbox data register. Others have been ignored. Another mailbox with a lower priority may have accepted the message.
A remote frame has been received, but no data are available to be sent.
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41.9.19 CAN Message Data Low Register
Name:
Address:
Access:
31
CAN_MDLx [x=0..7]
0xF8000214 (0)[0], 0xF8000234 (0)[1], 0xF8000254 (0)[2], 0xF8000274 (0)[3], 0xF8000294 (0)[4],
0xF80002B4 (0)[5], 0xF80002D4 (0)[6], 0xF80002F4 (0)[7], 0xF8004214 (1)[0], 0xF8004234 (1)[1], 0xF8004254
(1)[2], 0xF8004274 (1)[3], 0xF8004294 (1)[4], 0xF80042B4 (1)[5], 0xF80042D4 (1)[6], 0xF80042F4 (1)[7]
Read-write
30 29 28 27 26 25 24
MDL
23 22 21 20 19 18 17 16
MDL
15 14 13 12 11 10 9 8
MDL
7 6 5 4 3 2 1 0
MDL
• MDL: Message Data Low Value
When MRDY field is set in the CAN_MSRx register, the lower 32 bits of a received message can be read or written by the software application. Otherwise, the MDL value is locked by the CAN controller to send/receive a new message.
In Receive with overwrite, the CAN controller may modify MDL value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the
CAN_MSRx register. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the
CAN_MSRx register is set.
Bytes are received/sent on the bus in the following order:
1.
CAN_MDL[7:0]
2.
CAN_MDL[15:8]
3.
CAN_MDL[23:16]
4.
CAN_MDL[31:24]
5.
CAN_MDH[7:0]
6.
CAN_MDH[15:8]
7.
CAN_MDH[23:16]
8.
CAN_MDH[31:24]
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41.9.20 CAN Message Data High Register
Name:
Address:
Access:
31
CAN_MDHx [x=0..7]
0xF8000218 (0)[0], 0xF8000238 (0)[1], 0xF8000258 (0)[2], 0xF8000278 (0)[3], 0xF8000298 (0)[4],
0xF80002B8 (0)[5], 0xF80002D8 (0)[6], 0xF80002F8 (0)[7], 0xF8004218 (1)[0], 0xF8004238 (1)[1], 0xF8004258
(1)[2], 0xF8004278 (1)[3], 0xF8004298 (1)[4], 0xF80042B8 (1)[5], 0xF80042D8 (1)[6], 0xF80042F8 (1)[7]
Read-write
30 29 28 27 26 25 24
MDH
23 22 21 20 19 18 17 16
MDH
15 14 13 12 11 10 9 8
MDH
7 6 5 4 3 2 1 0
MDH
• MDH: Message Data High Value
When MRDY field is set in the CAN_MSRx register, the upper 32 bits of a received message are read or written by the software application. Otherwise, the MDH value is locked by the CAN controller to send/receive a new message.
In Receive with overwrite, the CAN controller may modify MDH value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the
CAN_MSRx register. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the
CAN_MSRx register is set.
Bytes are received/sent on the bus in the following order:
1.
CAN_MDL[7:0]
2.
CAN_MDL[15:8]
3.
CAN_MDL[23:16]
4.
CAN_MDL[31:24]
5.
CAN_MDH[7:0]
6.
CAN_MDH[15:8]
7.
CAN_MDH[23:16]
8.
CAN_MDH[31:24]
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41.9.21 CAN Message Control Register
Name:
Address:
CAN_MCRx [x=0..7]
0xF800021C (0)[0], 0xF800023C (0)[1], 0xF800025C (0)[2], 0xF800027C (0)[3], 0xF800029C (0)[4],
0xF80002BC (0)[5], 0xF80002DC (0)[6], 0xF80002FC (0)[7], 0xF800421C (1)[0], 0xF800423C (1)[1], 0xF800425C
(1)[2], 0xF800427C (1)[3], 0xF800429C (1)[4], 0xF80042BC (1)[5], 0xF80042DC (1)[6], 0xF80042FC (1)[7]
Write-only Access:
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
MTCR
22
MACR
21
–
20
MRTR
19 18
MDLC
17 16
15
–
7
–
14
–
6
–
13
–
5
–
• MDLC: Mailbox Data Length Code
12
–
4
–
11
–
3
–
10
–
2
–
1
–
9
–
0
–
8
–
Mailbox Object Type
Receive
Receive with overwrite
Transmit
Consumer
Producer
Description
No action.
No action.
Length of the mailbox message.
No action.
Length of the mailbox message to be sent after the remote frame reception.
• MRTR: Mailbox Remote Transmission Request
Mailbox Object Type
Receive
Receive with overwrite
Transmit
Consumer
Producer
Description
No action
No action
Set the RTR bit in the sent frame
No action, the RTR bit in the sent frame is set automatically
No action
Consumer situations can be handled automatically by setting the mailbox object type in Consumer. This requires only one mailbox.
It can also be handled using two mailboxes, one in reception, the other in transmission. The MRTR and the MTCR bits must be set in the same time.
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• MACR: Abort Request for Mailbox x
Mailbox Object Type
Receive
Receive with overwrite
Transmit
Consumer
Producer
Description
No action
No action
Cancels transfer request if the message has not been transmitted to the
CAN transceiver.
Cancels the current transfer before the remote frame has been sent.
Cancels the current transfer. The next remote frame will not be serviced.
It is possible to set MACR field for several mailboxes in the same time, setting several bits to the CAN_ACR register.
• MTCR: Mailbox Transfer Command
Mailbox Object Type
Receive
Receive with overwrite
Transmit
Consumer
Producer
Description
Allows the reception of the next message.
Triggers a new reception.
Sends data prepared in the mailbox as soon as possible.
Sends a remote transmission frame.
Sends data prepared in the mailbox after receiving a remote frame from a
Consumer.
This flag clears the MRDY and MABT flags in the CAN_MSRx register.
When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn. The mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e.,
MBx0 will be serviced before MBx 15 if they have the same priority).
It is possible to set MTCR for several mailboxes at the same time by writing to the CAN_TCR register.
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42.
Analog-to-Digital Converter (ADC)
42.1 Description
The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to the Block
Diagram:
of 12 analog lines. The conversions extend from 0V to ADVREF. The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register.
Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are configurable.
The comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a given range or outside the range, thresholds and ranges being fully configurable.
The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a DMA channel. These features reduce both power consumption and processor intervention.
A whole set of reference voltages is generated internally from a single external reference voltage node that may be equal to the analog supply voltage. An external decoupling capacitance is required for noise filtering.
Finally, the user can configure ADC timings, such as Startup Time and Tracking Time.
This ADC Controller includes a Resistive Touchscreen Controller. It supports 4-wire and 5-wire technologies.
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42.2 Embedded Characteristics
10-bit Resolution
440 kHz Conversion Rate
Wide Range Power Supply Operation
Resistive 4-wire and 5-wire Touchscreen Controller
Position and Pressure Measurement for 4-wire screens
Position Measurement for 5-wire screens
Average of up to 8 measures for noise filtering
Programmable Pen Detection sensitivity
Integrated Multiplexer Offering Up to 12 Independent Analog Inputs
Individual Enable and Disable of Each Channel
Hardware or Software Trigger
External Trigger Pin
Internal Trigger Counter
Trigger on Pen Contact Detection
DMA Support
Possibility of ADC Timings Configuration
Two Sleep Modes and Conversion Sequencer
Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all Enabled Channels
Possibility of Customized Channel Sequence
Standby Mode for Fast Wakeup Time Response
Power Down Capability
Automatic Window Comparison of Converted Values
Write Protect Registers
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42.3 Block Diagram
Figure 42-1. Analog-to-Digital Converter Block Diagram with Touchscreen mode
Timer
Counter
Channels
PMC
MCK
ADC Controller
ADTRG
Trigger
Selection
Control
Logic
ADC cell
VDDANA
ADVREF
AD0/XP/UL
Touch Screen
Analog
Inputs
AD1/XM/UR
AD2/YP/LL
AD3/YM/Sense
AD4/LR
PIO
Successive
Approximation
Register
Analog-to-Digital
Converter
User
Interface
Other
Analog
Inputs
AD-
AD-
Touch
Screen
Switches
2
3
0
1
4
CHx AD-
GND
ADC Interrupt
Interrupt
Controller
DMA
System Bus
Peripheral Bridge
APB
42.4 Signal Description
Table 42-1. ADC Pin Description
Pin Name
VDDANA
ADVREF
AD0 - AD
11
ADTRG
Description
Analog power supply
Reference voltage
Analog input channels
External trigger
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42.5 Product Dependencies
42.5.1 Power Management
The ADC Controller is not continuously clocked. The programmer must first enable the ADC Controller MCK in the Power
Management Controller (PMC) before using the ADC Controller. However, if the application does not require ADC operations, the ADC Controller clock can be stopped when not needed and restarted when necessary. Configuring the
ADC Controller does not require the ADC Controller clock to be enabled.
42.5.2 Interrupt Sources
The ADC interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the ADC interrupt requires the interrupt controller to be programmed first.
Table 42-2. Peripheral IDs
Instance ID
ADC 19
42.5.3 Analog Inputs
The analog input pins can be multiplexed with PIO lines. In this case, the assignment of the ADC input is automatically done as soon as the corresponding channel is enabled by writing the register ADC_CHER. By default, after reset, the
PIO line is configured as input with its pull-up enabled and the ADC input is connected to the GND.
42.5.4 I/O Lines
The pin ADTRG may be shared with other peripheral functions through the PIO Controller. In this case, the PIO
Controller should be set accordingly to assign the pin ADTRG to the ADC function.
Table 42-3. I/O Lines
Instance
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
Signal
ADTRG
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
I/O Line
PB18
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB6
PB7
PB8
PB9
PB10
Peripheral
B
X1
X1
X1
X1
X1
X1
X1
X1
X1
X1
X1
X1
42.5.5 Timer Triggers
Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all of the timer counters may be unconnected.
42.5.6 Conversion Performances
For performance and electrical characteristics of the ADC, see the product DC Characteristics section.
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42.6 Functional Description
42.6.1 Analog-to-digital Conversion
The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-bit digital data requires
Tracking Clock cycles as defined in the field TRACKTIM of the
“ADC Mode Register” on page 948
and Transfer Clock cycles as defined in the field TRANSFER of the same register. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR). The tracking phase starts during the conversion of the previous channel. If the tracking time is longer than the conversion time, the tracking phase is extended to the end of the previous conversion.
The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/512, if PRESCAL is set to 255 (0xFF). PRESCAL must be programmed in order to provide an ADC clock frequency according to the parameters given in the product
Electrical Characteristics section.
Figure 42-2. Sequence of ADC conversions
ADCClock
Trigger event
(H a rd or S oft)
ADC_ON
ADC_ S t a rt
ADC_eoc
ADC_ S EL
LCDR
DRDY
CH0 CH1
CH0
CH2
CH1
S t a rt Up Time
( a nd tr a cking of CH0)
Conver s ion of CH0 Tr a cking of CH1 Conver s ion of CH1 Tr a cking of CH2
42.6.2 Conversion Reference
The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between these voltages convert to values based on a linear conversion.
42.6.3 Conversion Resolution
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the LOWRES bit in the ADC
Mode Register (ADC_MR). By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used. By setting the LOWRES bit, the ADC switches to the lowest resolution and the conversion results can be read in the lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding
ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0.
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42.6.4 Conversion Results
When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (ADC_CDRx) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). By setting the TAG option in the
ADC_EMR, the ADC_LCDR presents the channel number associated to the last converted data in the CHNB field.
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected DMA channel, DRDY rising triggers a data transfer request. In any case, either EOC and DRDY can trigger an interrupt.
Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit.
Figure 42-3. EOCx and DRDY Flag Behavior
Write the ADC_CR
with START = 1
Read the ADC_CDRx
Write the ADC_CR
with START = 1
Read the ADC_LCDR
CHx
(ADC_CHSR)
EOCx
(ADC_SR)
DRDY
(ADC_SR)
If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVREx) flag is set in the Overrun Status Register (ADC_OVER).
Likewise, new data converted when DRDY is high sets the GOVRE bit (General Overrun Error) in ADC_SR.
The OVREx flag is automatically cleared when ADC_OVER is read, and GOVRE flag is automatically cleared when
ADC_SR is read.
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Figure 42-4. GOVRE and OVREx Flag Behavior
Trigger event
CH0
(ADC_CHSR)
CH1
(ADC_CHSR)
ADC_LCDR
ADC_CDR0
ADC_CDR1
EOC0
(ADC_SR)
EOC1
(ADC_SR)
Undefined Data
Undefined Data
Undefined Data
Data A
Conversion A
Conversion B
Data A
Data B
Data B
Conversion C
Data C
Data C
Read ADC_CDR0
Read ADC_CDR1
GOVRE
(ADC_SR)
DRDY
(ADC_SR)
OVRE0
(ADC_OVER)
OVRE1
(ADC_OVER)
Read ADC_SR
Read ADC_OVER
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable.
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42.6.5 Conversion Triggers
Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the START bit at 1.
The hardware trigger can be selected by the TRGMOD field in the
between:
Any edge, either rising or falling or both, detected on the external trigger pin, TSADTRG.
The Pen Detect, depending on how the PENDET bit is set in the
“ADC Touchscreen Mode Register”
.
A continuous trigger, meaning the ADC Controller restarts the next sequence as soon as it finishes the current one
A periodic trigger, which is defined by programming the TRGPER field in the
The minimum time between 2 consecutive trigger events must be strictly greater than the duration time of the longest conversion sequence according to configuration of registers ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2,
ADC_TSMR.
If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of the selected signal. Due to asynchronous handling, the delay may vary in a range of 2 MCK clock periods to 1 ADC clock period.
trigger start delay
Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable
(ADC_CHER) and Channel Disable (ADC_CHDR) Registers permit the analog channels to be enabled or disabled independently.
If the ADC is used with a DMA, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly.
42.6.6 Sleep Mode and Conversion Sequencer
The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions. Sleep Mode is selected by setting the SLEEP bit in the Mode Register ADC_MR.
The Sleep mode is automatically managed by a conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption.
This mode can be used when the minimum period of time between 2 successive trigger events is greater than the startup period of Analog-Digital converter (See the product ADC Characteristics section).
When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into account.
The conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. Conversion sequences can be performed periodically using the internal timer (ADC_TRGR register). The periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the DMA.
The sequence can be customized by programming the Sequence Channel Registers, ADC_SEQR1 and ADC_SEQR2 and setting to 1 the USEQ bit of the Mode Register (ADC_MR). The user can choose a specific order of channels and can program up to 12 conversions by sequence. The user is totally free to create a personal sequence, by writing channel numbers in ADC_SEQR1 and ADC_SEQR2. Not only can channel numbers be written in any sequence, channel numbers can be repeated several times. Only enabled sequence bitfields are converted, consequently to program a 15-conversion sequence, the user can simply put a disable in ADC_CHSR[15], thus disabling the 16THCH field of ADC_SEQR2.
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If all ADC channels (i.e. 12) are used on an application board, there is no restriction of usage of the user sequence. But as soon as some ADC channels are not enabled for conversion but rather used as pure digital inputs, the respective indexes of these channels cannot be used in the user sequence fields (ADC_SEQR1, ADC_SEQR2 bitfields). For example, if channel 4 is disabled (ADC_CSR[4] = 0), ADC_SEQR1, ADC_SEQR2 register bitfields USCH1 up to
USCH12 must not contain the value 4. Thus the length of the user sequence may be limited by this behavior.
As an example, if only 4 channels over 12 (CH0 up to CH3) are selected for ADC conversions, the user sequence length cannot exceed 4 channels. Each trigger event may launch up to 4 successive conversions of any combination of channels 0 up to 3 but no more (i.e. in this case the sequence CH0, CH0, CH1, CH1, CH1 is impossible).
A sequence that repeats several times the same channel requires more enabled channels than channels actually used for conversion. For example, a sequence like CH0, CH0, CH1, CH1 requires 4 enabled channels (4 free channels on application boards) whereas only CH0, CH1 are really converted.
Note: The reference voltage pins always remain connected in normal mode as in Sleep Mode.
42.6.7 Comparison Window
The ADC Controller features automatic comparison functions. It compares converted values to a low threshold or a high threshold or both, according to the CMPMODE function chosen in the Extended Mode Register (ADC_EMR). The comparison can be done on all channels or only on the channel specified in CMPSEL field of ADC_EMR. To compare all channels the CMP_ALL parameter of ADC_EMR should be set.
Moreover a filtering option can be set by writing the number of consecutive comparison errors needed to raise the flag.
This number can be written and read in the CMPFILTER field of ADC_EMR.
The flag can be read on the COMPE bit of the Interrupt Status Register (ADC_ISR) and can trigger an interrupt.
The High Threshold and the Low Threshold can be read/write in the Comparison Window Register (ADC_CWR).
If the comparison window is to be used with LOWRES bit in ADC_MR set to 1, the thresholds do not need to be adjusted as adjustment will be done internally. Whether or not the LOWRES bit is set, thresholds must always be configured in consideration of the maximum ADC resolution.
42.6.8 ADC Timings
Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register,
ADC_MR.
A minimal Tracking Time is necessary for the ADC to guarantee the best converted final value between two channel selections. This time has to be programmed through the TRACKTIM bit field in the Mode Register, ADC_MR.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to program a precise value in the TRACKTIM field. See the product ADC Characteristics section.
42.7 Touchscreen
42.7.1 Touchscreen Mode
The TSMODE parameter of
“ADC Touchscreen Mode Register”
is used to enable/disable the Touchscreen functionality, to select the type of screen (4-wire or 5-wire) and, in the case of a 4-wire screen, to activate (or not) the pressure measurement.
In 4-wire mode, channel 0, 1, 2 and 3 must not be used for classic ADC conversions. Likewise, in 5-wire mode, channel
0, 1, 2, 3, and 4 must not be used for classic ADC conversions.
42.7.2 4-wire Resistive Touchscreen Principles
A resistive touchscreen is based on two resistive films, each one being fitted with a pair of electrodes, placed at the top and bottom on one film, and on the right and left on the other. In between, there is a layer acting as an insulator, but also enables contact when you press the screen. This is illustrated in
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The TSADC controller has the ability to perform without external components:
Position Measurement
Pressure Measurement
Pen Detection
Figure 42-5. Touchscreen Position Measurement
Pen
Contact
X
P
Y
M
Y
P
X
M
VDD
X
P
Y
P
VDD
Y
P
X
P
Volt
X
M
Vertical Position Detection
GND
Volt
Y
M
GND
Horizontal Position Detection
42.7.3 4-wire Position Measurement Method
As shown in
resistance of the film, there is a voltage gradient from top to bottom. When a contact is performed on the screen, the voltage propagates at the point the two surfaces come into contact with the second film. If the input impedance on the right and left electrodes sense is high enough, the film does not affect this voltage, despite its resistive nature.
For the horizontal direction, the same method is used, but by applying supply from left to right. The range depends on the supply voltage and on the loss in the switches that connect to the top and bottom electrodes.
In an ideal world (linear, with no loss through switches), the horizontal position is equal to:
VY
M
/ VDD or VY
P
/ VDD.
The implementation with on-chip power switches is shown in
Figure 42-6 . The voltage measurement at the output of the
switch compensates for the switches loss.
It is possible to correct for switch loss by performing the operation:
[VY
P
- VX
M
] / [VX
P
- VX
M
].
This requires additional measurements, as shown in Figure 42-6
.
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Figure 42-6. Touchscreen Switches Implementation
X
P VDDANA
X
M GND
Y
P VDDANA
Y
M GND
2
0
1
3
VDDANA
Switch
Resistor
X
P
To the ADC
VDDANA
Switch
Resistor
Y
P
Y
P
X
P
X
M
Switch
Resistor
GND
Horizontal Position Detection
Y
M
Switch
Resistor
GND
Vertical Position Detection
42.7.4 4-wire Pressure Measurement Method
The method to measure the pressure (Rp) applied to the touchscreen is based on the known resistance of the X-Panel resistance (Rxp).
Three conversions (Xpos, Z1, Z2) are necessary to determine the value of Rp (Zaxis resistance).
Rp = Rxp*(Xpos/1024)*[(Z2/Z1)-1]
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Figure 42-7. Pressure Measurement
VDDANA
Switch
Resistor
X
P
Y
P
Rp
X
P
VDDANA
Switch
Resistor
Y
P
Rp
X
P
Open circuit
VDDANA
Switch
Resistor
Y
P
Rp
X
M
Switch
Resistor
Y
Open circuit
GND
XPos Measure(Yp)
M
X
M
Switch
Resistor
GND
Z1 Measure(Xp)
Y
M
Open circuit
X
M
Switch
Resistor
GND
Z2 Measure(Xp)
Y
M
42.7.5 5-wire Resistive Touchscreen Principles
To make a 5-wire touchscreen, a resistive layer with a contact point at each corner and a conductive layer are used.
The 5-wire touchscreen differs from the 4-wire type mainly in that the voltage gradient is applied only to one layer, the resistive layer, while the other layer is the sense layer for both measurements.
The measurement of the X position is obtained by biasing the upper left corner and lower left corner to V DDANA and the upper right corner and lower right to ground.
To measure along the Y axis, bias the upper left corner and upper right corner to V DDANA and bias the lower left corner and lower right corner to ground.
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Figure 42-8. 5-Wire principle
U
L
Pen
Contact
Resistive layer
U
R
Sense
L
L
Conductive Layer
L
R
U
L
VDDANA
U
R
VDDANA for Yp
GND for Xp
Sense
L
L
VDDANA for Xp
GND for Yp
L
R
GND
42.7.6 5-wire Position Measurement Method
In an application only monitoring clicks, 100 points per second is typically needed. For handwriting or motion detection, the number of measurements to consider is approximately 200 points per second. This must take into account that multiple measurements are included (over sampling, filtering) to compute the correct point.
The 5-wire touchscreen panel works by applying a voltage at the corners of the resistive layer and measuring the vertical or horizontal resistive network with the sense input. The ADC converts the voltage measured at the point the panel is touched.
A measurement of the Y position of the pointing device is made by:
Connecting Upper left (UL) and upper right (UR) corners to VDDANA
Connecting Lower left (LL) and lower right (LR) corners to ground.
The voltage measured is determined by the voltage divider developed at the point of touch (Yposition) and the
SENSE input is converted by ADC.
A measurement of the X position of the pointing device is made by:
Connecting the upper left (UL) and lower left (LL) corners to ground
Connecting the upper right and lower right corners to VDDANA.
The voltage measured is determined by the voltage divider developed at the point of touch (Xposition) and the
SENSE input is converted by ADC.
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Figure 42-9. Touchscreen Switches Implementation
U
L VDDANA
U
R
L
L
GND
VDDANA
GND
VDDANA
SENSE
L
R
GND
0
1
2
3
4
To the ADC
U
L
VDDANA
U
R
VDDANA for Ypos
GND for Xpos
Sense
L
L VDDANA for Xpos
GND for Ypos
L
R
GND
42.7.7 Sequence and Noise Filtering
The ADC Controller can manage ADC conversions and Touchscreen measurement. On each trigger event the sequence of ADC conversions is performed as described in
Section 42.6.6 “Sleep Mode and Conversion Sequencer”
. The
Touchscreen measure frequency can be specified in number of trigger events by writing the TSFREQ parameter in the
Touchscreen sequence is appended to the classic ADC conversion sequence (see
Additionally the user can average multiple Touchscreen measures by writing the TSAV parameter in the
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Figure 42-10. Insertion of Touchscreen sequences (TSFREQ = 2; TSAV = 1)
Trigger event
ADC_ S EL
C T C T C C C T C T C
C: Classic ADC Conversion Sequence - T: Touch Screen Sequence
XRDY
Re a d the
ADC_XPO S R
Re a d the
ADC_XPO S R
YRDY
Re a d the
ADC_YPO S R
Re a d the
ADC_YPO S R
42.7.8 Measured Values, Registers and Flags
As soon as the controller finishes the Touchscreen sequence, XRDY, YRDY and PRDY are set and can generate an interrupt. These flags can be read in the
“ADC Interrupt Status Register”
. They are reset independently by reading in
ADC_XPOSR, ADC_YPOSR and ADC_PRESSR. for classic ADC conversions.
The “ADC Touchscreen X Position Register” presents XPOS (V
X on the 16th bit.
- V
Xmin
) on its LSB and XSCALE (V
XMAX
- V
Xmin
) aligned
“ADC Touchscreen Y Position Register”
Y on the 16th bit.
- V
Ymin
) on its LSB and YSCALE (V
YMAX
- V
Ymin
) aligned
To improve the quality of the measure, the user must calculate: XPOS/XSCALE and YPOS/YSCALE.
V
XMAX,
V
Xmin,
V
YMAX, and V
Ymin
are measured at the first start up of the controller. These values can change during use, so it can be necessary to refresh them. Refresh can be done by writing ‘1’ in the CALIB field of the control register
(ADC_CR).
The “ADC Touchscreen Pressure Register”
presents Z1 on its LSB and Z2 aligned on the 16th bit. See Section 42.7.4
to know how use them.
42.7.9 Pen Detect Method
When there is no contact, it is not necessary to perform a conversion. However, it is important to detect a contact by keeping the power consumption as low as possible.
The implementation polarizes one panel by closing the switch on (X
P resistor connected to Y
M
/U
L
) and ties the horizontal panel by an embedded
/ Sense. This resistor is enabled by a fifth switch. Since there is no contact, no current is flowing and there is no related power consumption. As soon as a contact occurs, a current is flowing in the Touchscreen and a
Schmitt trigger detects the voltage in the resistor.
The Touchscreen Interrupt configuration is entered by programming the PENDET bit in the
trigger.
To complete the circuit, a programmable debouncer is placed at the output of the Schmitt trigger. This debouncer is programmable up to 2 15 ADC clock periods. The debouncer length can be selected by programming the field PENDBC in
“ADC Touchscreen Mode Register”
.
Due to the analog switch’s structure, the debouncer circuitry is only active when no conversion (Touchscreen or classic
ADC channels) is in progress. Thus, if the time between the end of a conversion sequence and the arrival of the next trigger event is lower than the debouncing time configured on PENDBC, the debouncer will not detect any contact.
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Figure 42-11. Touchscreen Pen Detect
X+/U
L
X-/U
R
VDDANA
Y+/L
L
GND
VDDANA
GND
VDDANA
Y-/SENSE
GND
L
R
GND
0
1
2
3
4
To the ADC
PENDBC
Debouncer Pen Interrupt
GND
The Touchscreen Pen Detect can be used to generate an ADC interrupt to wake up the system. The Pen Detect generates two types of status, reported in the
“ADC Interrupt Status Register”
The PEN bit is set as soon as a contact exceeds the debouncing time as defined by PENDBC and remains set until ADC_SR is read.
The NOPEN bit is set as soon as no current flows for a time over the debouncing time as defined by PENDBC and remains set until ADC_SR is read.
Both bits are automatically cleared as soon as the Status Register (ADC_SR) is read, and can generate an interrupt by writing the
“ADC Interrupt Enable Register”
Moreover, the rising of either one of them clears the other, they cannot be set at the same time.
The PENS bit of the ADC_SR indicates the current status of the pen contact.
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42.7.10 Buffer Structure
The DMA read channel is triggered each time a new data is stored in ADC_LCDR register. The same structure of data is repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of operation
(ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2, ADC_TSMR) the structure differs. Each data transferred to DMA buffer, carried on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR register, the 4 most significant bits are carrying the channel number thus allowing an easier post-processing in the DMA buffer or better checking the DMA buffer integrity.
As soon as touchscreen conversions are required, the pen detection function may help the post-processing of the buffer.
To get more details refer to
Section 42.7.10.4 “Pen Detection Status” .
42.7.10.1 Classical ADC Channels Only
When no touchscreen conversion is required (i.e. TSMODE = 0 in ADC_TSMR register), the structure of data within the buffer is defined by the ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2 registers.
If the user sequence is not used (i.e. USEQ is cleared in ADC_MR register) then only the value of ADC_CHSR register defines the data structure. For each trigger event, enabled channels will be consecutively stored in ADC_LCDR register and automatically transferred to the buffer.
When the user sequence is configured (i.e. USEQ is set in ADC_MR register) not only does ADC_CHSR register modify the data structure of the buffer, but ADC_SEQR1, ADC_SEQR2 registers may modify the data structure of the buffer as well.
Figure 42-12. Buffer Structure when TSMODE = 0
A
ssu
ming ADC_CH
S
R = 0x000_01600
ADC_EMR(TAG) = 1
trig.event1
5 ADC_CDR5
DMA B u ffer
S tr u ct u re
6 ADC_CDR6 trig.event2
8
5
6
8
ADC_CDR 8
ADC_CDR5
ADC_CDR6
ADC_CDR 8
BA + 0x08
BA + 0x0A
A
ssu
ming ADC_CH
S
R = 0x000_01600
ADC_EMR(TAG) = 0
DMA Transfer
Base Address (BA) trig.event1
BA + 0x02
DMA B u ffer
S tr u ct u re
BA + 0x04
BA + 0x06 trig.event2
0
0
0
0
0
0
ADC_CDR5
ADC_CDR6
ADC_CDR 8
ADC_CDR5
ADC_CDR6
ADC_CDR 8 trig.eventN
5
6
8
ADC_CDR5
ADC_CDR6
ADC_CDR 8
BA + [(N-1) * 6] trig.eventN
BA + [(N-1) * 6]+ 0x02
BA + [(N-1) * 6]+ 0x04
0
0
0
ADC_CDR5
ADC_CDR6
ADC_CDR 8
42.7.10.2 TouchScreen Channels Only
When only touchscreen conversions are required (i.e. TSMODE differs from 0 in ADC_TSMR register and ADC_CHSR equals 0), the structure of data within the buffer is defined by the ADC_TSMR register.
When TSMODE = 1 or 3, each trigger event adds 2 half-words in the buffer (assuming TSAV = 0), first half-word being
XPOS of ADC_XPOSR register then YPOS of ADC_YPOSR register. If TSAV/TSFREQ differs from 0, the data structure remains unchanged. Not all trigger events add data to the buffer.
When TSMODE = 2, each trigger event adds 4 half-words to the buffer (assuming TSAV=0), first half-word being XPOS of ADC_XPOSR register followed by YPOS of ADC_YPOSR register and finally Z1 followed by Z2, both located in
ADC_PRESSR register.
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When TAG is set (ADC_EMR), the CHNB field (4 most significant bit of the ADC_LCDR) register is set to 0 when XPOS is transmitted and set to 1 when YPOS is transmitted, allowing an easier post-processing of the buffer or better checking buffer integrity. In case 4-wire with pressure mode is selected, Z1 value is transmitted to the buffer along with tag set to 2 and Z2 is tagged with value 3.
XSCALE and YSCALE (calibration values) are not transmitted to the buffer because they are supposed to be constant and moreover only measured at the very first start up of the controller or upon user request.
There is no change in buffer structure whatever the value of PENDET bit configuration in ADC_TSMR register but it is recommended to use the pen detection function for buffer post-processing (refer to
“Pen Detection Status” on page 944
).
Figure 42-13. Buffer Structure when only touchscreen channels are enabled
Assuming ADC_TSMR(TSMOD) = 1 or 3
ADC_TSMR(TSAV) = 0
ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 1
trig.event1
0 ADC_XPO S R
DMA Buffer
Structure trig.event2
1
0
ADC_YPO S R
ADC_XPO S R
Assuming ADC_TSMR(TSMOD) =1 or 3
ADC_TSMR(TSAV) = 0
ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 0
DMA Transfer trig.event1
Base Address (BA)
BA + 0x02
DMA Buffer
Structure trig.event2
BA + 0x04
0
0
0
ADC_XPO
ADC_YPO
ADC_XPO
S
S
S
R
R
R
1 ADC_YPO S R BA + 0x06
0 ADC_YPO S R trig.eventN
0
1
ADC_XPO S R
ADC_YPO S R
BA + [(N-1) * 4] trig.eventN
BA + [(N-1) * 4]+ 0x02
0
0
ADC_XPO
ADC_YPO
S
S
R
R
Assuming ADC_TSMR(TSMOD) = 2
ADC_TSMR(TSAV) = 0
ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 1
trig.event1
0 ADC_XPO S R
Assuming ADC_TSMR(TSMOD) = 2
ADC_TSMR(TSAV) = 0
ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 0
DMA Transfer trig.event1
Base Address (BA) 0 ADC_XPO S R
DMA Buffer
Structure
1
2
ADC_YPO S R
ADC_PRE SS R(Z1)
BA + 0x02
BA + 0x04
DMA Buffer
Structure
0
0
ADC_YPO
ADC_PRE
S R
SS R(Z1) trig.event2
3
0
ADC_PRE SS R(Z2)
ADC_XPO S R
BA + 0x06
BA + 0x08 trig.event2
0
0
ADC_PRE SS R(Z2)
ADC_XPO S R
BA + 0x0A
1
2
ADC_YPO S R
ADC_PRE SS R(Z1) BA + 0x0C
0
0
ADC_YPO S R
ADC_PRE SS R(Z1)
3 ADC_PRE SS R(Z2) BA + 0x0E 0 ADC_PRE SS R(Z2) trig.eventN
0
1
2
3
ADC_XPO
ADC_PRE
S R
ADC_YPO S R
ADC_PRE SS R(Z1)
SS R(Z2) trig.eventN
BA + [(N-1) * 8]
BA + [(N-1) * 8]+ 0x02
BA + [(N-1) * 8]+ 0x04
BA + [(N-1) * 8]+ 0x06
0
0
ADC_XPO S R
ADC_YPO S R
ADC_PRE SS R(Z1)
0
0 ADC_PRE SS R(Z2)
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42.7.10.3 Interleaved Channels
When both classic ADC channels (CH4/CH5 up to CH12 are set in ADC_CHSR) and touchscreen conversions are required (TSMODE differs from 0 in ADC_TSMR register) the structure of the buffer differs according to TSAV and
TSFREQ values.
If TSFREQ differs from 0, not all events generate touchscreen conversions, therefore buffer structure is based on
2 TSFREQ trigger events. Given a TSFREQ value, the location of touchscreen conversion results depends on TSAV value.
When TSFREQ = 0, TSAV must equal 0.
There is no change in buffer structure whatever the value of PENDET bit configuration in ADC_TSMR register but it is recommended to use the pen detection function for buffer post-processing (refer to
“Pen Detection Status” on page 944
).
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Figure 42-14. Buffer Structure when classic ADC and touchscreen channels are interleaved
A
ssu
ming ADC_T
ADC_T
S
ADC_CH
MR(T
S trig.event1
DMA B u ffer
S tr u ct u re trig.event2
S
AV) = ADC_T
R = 0x000_0100 , ADC_EMR(TAG) =1
8
0
1
8
0
1
S
MR(T
S
MOD) = 1
S
MR(T
ADC_CDR
ADC_XPO
ADC_YPO S R
ADC_CDR 8
ADC_XPO
S
8
S
S
FREQ) = 0
R
R
ADC_YPO S R
DMA Transfer
Base Address (BA)
BA + 0x02
BA + 0x04
BA + 0x06
BA + 0x08
BA + 0x0A
A
ssu
ming ADC_T
S
MR(T
S
MOD) = 1
ADC_T
S
MR(T
S
AV) = ADC_T
S
MR(T
S
FREQ) =
ADC_CH
S
R = 0x000_0100 , ADC_EMR(TAG)
trig.event1
DMA B u ffer
S tr u ct u re trig.event2
0
0
0
0
0
0
ADC_CDR
ADC_XPO
ADC_YPO
ADC_CDR
ADC_XPO
ADC_YPO
8
S
S
8
S
S
R
R
R
R trig.eventN
8
0
1
ADC_CDR
ADC_XPO
ADC_YPO
8
S
S
R
R trig.eventN
BA + [(N-1) * 6]
BA + [(N-1) * 6]+ 0x02
BA + [(N-1) * 6]+ 0x04
0
0
0
ADC_CDR
ADC_XPO
ADC_YPO
8
S
S
R
R
A
ssu
ming ADC_T
S
MR(T
S
MOD) = 1
ADC_T
S
MR(T
S
AV) = 0 ADC_T
S
MR(T
S
FREQ) = 1
ADC_CH
S
R = 0x000_0100 , ADC_EMR(TAG) = 1
trig.event1
DMA Transfer
8 ADC_CDR 8 Base Address (BA)
DMA B u ffer
S tr u ct u re
0
1
ADC_XPO S R
ADC_YPO S R
BA + 0x02
BA + 0x04 trig.event2
trig.event3
8
8
ADC_CDR 8
ADC_CDR 8
BA + 0x06
BA + 0x08
BA + 0x0A
0
1
ADC_XPO S R
ADC_YPO S R trig.event4
BA + 0x0c
8 ADC_CDR 8 BA + 0x0e
A
ssu
ming ADC_T
S
MR(T
S
MOD) = 1
ADC_T
S
MR(T
S
AV) = 1 ADC_T
S
MR(T
S
FREQ
ADC_CH
S
R = 0x000_0100 , ADC_EMR(TAG)
trig.event1
8 ADC_CDR 8 trig.event2
DMA B u ffer
S tr u ct u re
8
0
ADC_CDR 8
ADC_XPO S R
1 ADC_YPO S R trig.event3
trig.event4
8
8
ADC_CDR 8
ADC_CDR 8
0
1
ADC_XPO
ADC_YPO
S
S
R
R trig.eventN
trig.eventN+1
8
0
1
8
ADC_CDR
ADC_XPO
ADC_YPO
ADC_CDR
8
S
S
8
R
R trig.eventN
BA + [(N-1) * 8] trig.eventN+1
BA + [(N-1) * 8]+ 0x02
BA + [(N-1) * 8]+ 0x04
BA + [(N-1) * 8]+ 0x06
8
8
0
1
ADC_CDR 8
ADC_CDR 8
ADC_XPO S R
ADC_YPO S R
SAM9X35 [DATASHEET]
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943
42.7.10.4 Pen Detection Status
If the pen detection measure is enabled (PENDET is set in ADC_TSMR register), the XPOS, YPOS, Z1, Z2 values transmitted to the buffer through ADC_LCDR register are cleared (including the CHNB field), if the PENS flag of
ADC_ISR register is 0. When the PENS flag is set, XPOS, YPOS, Z1, Z2 are normally transmitted.
Therefore, using pen detection together with tag function eases the post-processing of the buffer, especially to determine which touchscreen converted values correspond to a period of time when the pen was in contact with the screen.
When the pen detection is disabled or the tag function is disabled, XPOS, YPOS, Z1, Z2 are normally transmitted without tag and no relationship can be found with pen status, thus post-processing may not be easy.
Figure 42-15. Buffer Structure with and without pen detection enabled
Assuming ADC_TSMR(TSMOD) = 1, PENDET = 1
ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0
ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) = 1
trig.event1
8 ADC_CDR 8
DMA Transfer
Base Address (BA)
DMA buffer
Structure 0
1
ADC_XPO S R
ADC_YPO S R
BA + 0x02
BA + 0x04 trig.event2
8 ADC_CDR 8 BA + 0x06
0 ADC_XPO S R BA + 0x08
BA + 0x0A
1 ADC_YPO S R
Assuming ADC_TSMR(TSMOD) = 1, PENDET = 1
ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0
ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) =0
trig.event1
DMA buffer
Structure trig.event2
0
0
0
0
0
0
ADC_CDR 8
ADC_XPO S R
ADC_YPO S R
ADC_CDR 8
ADC_XPO S R
ADC_YPO S R trig.eventN
trig.eventN+1
8
0
0
8
0
0
ADC_CDR 8
0
0
ADC_CDR 8
0
0
2 successive tags cleared => PENS = 0
trig.eventN
BA + [(N-1) * 6]
BA + [(N-1) * 6]+ 0x02
BA + [(N-1) * 6]+ 0x04
0
0
0
0
0
0
ADC_CDR
ADC_XPO
ADC_YPO
8
S
S
ADC_CDR 8
R
R
*
*
ADC_XPO S R *
ADC_YPO S R *
ADC_XPO S R * , ADC_YPO S R * c a n b a ny v a l u e when PEN S = 0
SAM9X35 [DATASHEET]
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42.7.11 Write Protected Registers
To prevent any single software error that may corrupt ADC behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “ADC Write Protect Mode Register”
(ADC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Protect Status Register
(ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset by reading the ADC Write Protect Status Register (ADC_WPSR).
The protected registers are:
“ADC Mode Register” on page 948
“ADC Channel Sequence 1 Register” on page 950
“ADC Channel Sequence 2 Register” on page 951
“ADC Channel Enable Register” on page 952
“ADC Channel Disable Register” on page 953
“ADC Extended Mode Register” on page 962
“ADC Compare Window Register” on page 963
“ADC Analog Control Register” on page 965
“ADC Touchscreen Mode Register” on page 966
“ADC Trigger Register” on page 971
SAM9X35 [DATASHEET]
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42.8 Analog-to-Digital Converter (ADC) User Interface
Any offset not listed in Table 42-4
must be considered as “reserved”.
0x40
0x44
0x50
0x54
...
0x7C
0x80 - 0x90
0x94
0x98 - 0xAC
0xB0
0xB4
0xB8
0xBC
0xC0
0xC4 - 0xE0
0xE4
0xE8
0xEC - 0xF8
0xFC
Table 42-4. Register Mapping
Offset
0x00
0x04
0x08
Control Register
Mode Register
Register
Channel Sequence Register 1
0x0C
0x10
0x14
Channel Sequence Register 2
Channel Enable Register
Channel Disable Register
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
Channel Status Register
Reserved
Last Converted Data Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Interrupt Status Register
Reserved
Reserved
Overrun Status Register
Extended Mode Register
Compare Window Register
Channel Data Register 0
Channel Data Register 1
...
Channel Data Register 11
Reserved
Analog Control Register
Reserved
Touchscreen Mode Register
Touchscreen X Position Register
Touchscreen Y Position Register
Touchscreen Pressure Register
Trigger Register
Reserved
Write Protect Mode Register
Write Protect Status Register
Reserved
Reserved
ADC_EMR
ADC_CWR
ADC_CDR0
ADC_CDR1
...
ADC_CDR11
–
ADC_ACR
–
ADC_TSMR
ADC_XPOSR
ADC_YPOSR
ADC_PRESSR
ADC_TRGR
–
ADC_WPMR
ADC_WPSR
–
–
Name
ADC_CR
ADC_MR
ADC_SEQR1
ADC_SEQR2
ADC_CHER
ADC_CHDR
ADC_CHSR
–
ADC_LCDR
ADC_IER
ADC_IDR
ADC_IMR
ADC_ISR
–
–
ADC_OVER
0x00000000
0x00000000
0x00000000
0x00000000
...
0x00000000
–
0x00000100
–
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
–
0x00000000
0x00000000
–
–
Reset
–
0x00000000
0x00000000
0x00000000
–
–
0x00000000
–
0x00000000
–
–
0x00000000
0x00000000
–
–
0x00000000
Read-write
Read-write
Read-only
Read-only
...
Read-only
–
Read-write
–
Read-write
Read-only
Read-only
Read-only
Read-write
–
Read-write
Read-only
–
–
Access
Write-only
Read-write
Read-write
Read-write
Write-only
Write-only
Read-only
–
Read-only
Write-only
Write-only
Read-only
Read-only
–
–
Read-only
SAM9X35 [DATASHEET]
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42.8.1 ADC Control Register
Name:
Address:
Access:
ADC_CR
0xF804C000
Write-only
31
–
30
–
23
–
15
–
7
–
22
–
14
–
6
–
13
–
5
–
29
–
21
–
12
–
4
–
28
–
20
–
11
–
3
–
27
–
19
–
26
–
18
–
10
–
2
TSCALIB
25
–
17
–
9
–
1
START
24
–
16
–
8
–
0
SWRST
• SWRST: Software Reset
0 = No effect.
1 = Resets the ADC simulating a hardware reset.
• START: Start Conversion
0 = No effect.
1 = Begins analog-to-digital conversion.
• TSCALIB: Touchscreen Calibration
0 = No effect.
1 = Programs screen calibration (VDD/GND measurement)
The calibration sequence is performed during the next sequence when command is launched during an already started conversion sequence, or at the start of the second conversion sequence located after the TSCALIB command, if it is launched when no conversion is in progress (sleep mode, waiting a trigger event).
TSCALIB measurement sequence does not affect the last data converted register (ADC_LDCR).
SAM9X35 [DATASHEET]
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42.8.2 ADC Mode Register
Name:
Address:
Access:
ADC_MR
0xF804C004
Read-write
31
USEQ
30
–
23
–
15
7
–
22
–
14
6
FWUP
29
–
21
–
13
5
SLEEP
28
–
20
–
12
PRESCAL
4
LOWRES
27
19
11
3
26
TRACKTIM
25
18 17
STARTUP
10 9
2
–
1
• LOWRES: Resolution
Value
0
1
Name
BITS_10
BITS_8
• SLEEP: Sleep Mode
Description
10-bit resolution
8-bit resolution
24
16
8
0
–
Value
0
1
Name
NORMAL
SLEEP
• FWUP: Fast Wake Up
Description
Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions
Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions
Value
0
1
Name
OFF
ON
Description
Normal Sleep Mode: The sleep mode is defined by the SLEEP bit
Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF
• PRESCAL: Prescaler Rate Selection
ADCClock = MCK / ( (PRESCAL+1) * 2 )
• STARTUP: Start Up Time
Value
0
1
2
3
4
Name
SUT0
SUT8
SUT16
SUT24
SUT64
Description
0 periods of ADCClock
8 periods of ADCClock
16 periods of ADCClock
24 periods of ADCClock
64 periods of ADCClock
SAM9X35 [DATASHEET]
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13
14
15
9
10
11
12
Value
5
6
7
8
Name
SUT80
SUT96
SUT112
SUT512
SUT576
SUT640
SUT704
SUT768
SUT832
SUT896
SUT960
Description
80 periods of ADCClock
96 periods of ADCClock
112 periods of ADCClock
512 periods of ADCClock
576 periods of ADCClock
640 periods of ADCClock
704 periods of ADCClock
768 periods of ADCClock
832 periods of ADCClock
896 periods of ADCClock
960 periods of ADCClock
• TRACKTIM: Tracking Time
Tracking Time = (TRACKTIM + 1) * ADCClock periods.
• USEQ: Use Sequence Enable
Value Name
0 NUM_ORDER
1 REG_ORDER
Description
Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index.
User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel.
SAM9X35 [DATASHEET]
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42.8.3 ADC Channel Sequence 1 Register
Name:
Address:
Access:
ADC_SEQR1
0xF804C008
Read-write
31 30 29
USCH8
23 22 21
USCH6
15 14 13
USCH4
7 6 5
USCH2
28
20
12
4
27
19
11
3
26
18
10
2
USCH7
25
17
USCH5
9
USCH3
1
USCH1
24
16
8
0
• USCHx: User Sequence Number x
The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in this field. The allowed range is 0 up to 11. So it is only possible to use the sequencer from CH0 to CH11.
This register activates only if ADC_MR(USEQ) field is set to ‘1’.
Any USCHx field is taken into account only if ADC_CHSR(CHx) register field reads logical ‘1’ else any value written in USCHx does not add the corresponding channel in the conversion sequence.
Configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. This can be done consecutively, or not, according to user needs.
SAM9X35 [DATASHEET]
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42.8.4 ADC Channel Sequence 2 Register
Name:
Address:
Access:
ADC_SEQR2
0xF804C00C
Read-write
31 30 29
USCH16
23 22 21
USCH14
15 14 13
USCH12
7 6 5
USCH10
28
20
12
4
27
19
11
3
26
USCH15
25
18 17
USCH13
10 9
USCH11
2 1
USCH9
24
16
8
0
• USCHx: User Sequence Number x
The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in this field. The allowed range is 0 up to 11. So it is only possible to use the sequencer from CH0 to CH11.
This register activates only if ADC_MR(USEQ) field is set to ‘1’.
Any USCHx field is taken into account only if ADC_CHSR(CHx) register field reads logical ‘1’ else any value written in USCHx does not add the corresponding channel in the conversion sequence.
Configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. This can be done consecutively, or not, according to user needs.
SAM9X35 [DATASHEET]
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42.8.5 ADC Channel Enable Register
Name:
Address:
Access:
ADC_CHER
0xF804C010
Write-only
31
–
30
–
29
–
23
–
15
–
7
CH7
22
–
14
–
6
CH6
21
–
13
–
5
CH5
12
–
4
CH4
28
–
20
–
11
CH11
3
CH3
27
–
19
–
26
–
18
–
10
CH10
2
CH2
9
CH9
1
CH1
25
–
17
–
• CHx: Channel x Enable
0 = No effect.
1 = Enables the corresponding channel.
Note: If USEQ = 1 in ADC_MR register, CHx corresponds to the xth channel of the sequence described in ADC_SEQR1 and
ADC_SEQR2.
8
CH8
0
CH0
24
–
16
–
SAM9X35 [DATASHEET]
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952
42.8.6 ADC Channel Disable Register
Name:
Address:
Access:
ADC_CHDR
0xF804C014
Write-only
31
–
30
–
29
–
23
–
15
–
7
CH7
22
–
14
–
6
CH6
21
–
13
–
5
CH5
12
–
4
CH4
28
–
20
–
11
CH11
3
CH3
27
–
19
–
26
–
18
–
10
CH10
2
CH2
9
CH9
1
CH1
25
–
17
–
8
CH8
0
CH0
24
–
16
–
• CHx: Channel x Disable
0 = No effect.
1 = Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable.
SAM9X35 [DATASHEET]
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42.8.7 ADC Channel Status Register
Name:
Address:
Access:
ADC_CHSR
0xF804C018
Read-only
31
–
30
–
29
–
23
–
15
–
7
CH7
22
–
14
–
6
CH6
21
–
13
–
5
CH5
• CHx: Channel x Status
0 = Corresponding channel is disabled.
1 = Corresponding channel is enabled.
12
–
4
CH4
28
–
20
–
11
CH11
3
CH3
27
–
19
–
26
–
18
–
10
CH10
2
CH2
9
CH9
1
CH1
25
–
17
–
8
CH8
0
CH0
24
–
16
–
SAM9X35 [DATASHEET]
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42.8.8 ADC Last Converted Data Register
Name:
Address:
Access:
ADC_LCDR
0xF804C020
Read-only
31
–
30
–
29
–
23
–
15
22
–
14
21
–
13
CHNB
7 6 5
28
–
20
–
12
4
27
–
19
–
11
3
26
–
18
–
10
LDATA
2
25
–
17
–
9
1
24
–
16
–
8
0
LDATA
• LDATA: Last Data Converted
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
• CHNB: Channel Number
Indicates the last converted channel when the TAG option is set to 1 in the ADC_EMR register. If the TAG option is not set, CHNB
= 0.
SAM9X35 [DATASHEET]
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42.8.9 ADC Interrupt Enable Register
Name:
Address:
Access:
ADC_IER
0xF804C024
Write-only
31
–
30
NOPEN
29
PEN
23
–
15
–
7
EOC7
22
PRDY
14
–
6
EOC6
21
YRDY
13
–
5
EOC5
28
–
20
XRDY
12
–
4
EOC4
• EOCx: End of Conversion Interrupt Enable x
• XRDY: Touchscreen Measure XPOS Ready Interrupt Enable
• YRDY: Touchscreen Measure YPOS Ready Interrupt Enable
• PRDY: Touchscreen Measure Pressure Ready Interrupt Enable
• DRDY: Data Ready Interrupt Enable
• GOVRE: General Overrun Error Interrupt Enable
• COMPE: Comparison Event Interrupt Enable
• PEN: Pen Contact Interrupt Enable
• NOPEN: No Pen Contact Interrupt Enable
27
–
19
–
11
EOC11
3
EOC3
0 = No effect.
1 = Enables the corresponding interrupt.
26
COMPE
18
–
10
EOC10
2
EOC2
25
GOVRE
17
–
9
EOC9
1
EOC1
24
DRDY
16
–
8
EOC8
0
EOC0
SAM9X35 [DATASHEET]
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956
42.8.10 ADC Interrupt Disable Register
Name:
Address:
Access:
ADC_IDR
0xF804C028
Write-only
31
–
30
NOPEN
29
PEN
23
–
15
–
7
EOC7
22
PRDY
14
–
6
EOC6
21
YRDY
13
–
5
EOC5
28
–
20
XRDY
12
–
4
EOC4
• EOCx: End of Conversion Interrupt Disable x
• XRDY: Touchscreen Measure XPOS Ready Interrupt Disable
• YRDY: Touchscreen Measure YPOS Ready Interrupt Disable
• PRDY: Touchscreen Measure Pressure Ready Interrupt Disable
• DRDY: Data Ready Interrupt Disable
• GOVRE: General Overrun Error Interrupt Disable
• COMPE: Comparison Event Interrupt Disable
• PEN: Pen Contact Interrupt Disable
• NOPEN: No Pen Contact Interrupt Disable
27
–
19
–
11
EOC11
3
EOC3
0 = No effect.
1 = Disables the corresponding interrupt.
26
COMPE
18
–
10
EOC10
2
EOC2
25
GOVRE
17
–
9
EOC9
1
EOC1
24
DRDY
16
–
8
EOC8
0
EOC0
SAM9X35 [DATASHEET]
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957
42.8.11 ADC Interrupt Mask Register
Name:
Address:
Access:
ADC_IMR
0xF804C02C
Read-only
31
–
30
NOPEN
29
PEN
23
–
15
–
7
EOC7
22
PRDY
14
–
6
EOC6
21
YRDY
13
–
5
EOC5
28
–
20
XRDY
12
–
4
EOC4
• EOCx: End of Conversion Interrupt Mask x
• XRDY: Touchscreen Measure XPOS Ready Interrupt Mask
• YRDY: Touchscreen Measure YPOS Ready Interrupt Mask
• PRDY: Touchscreen Measure Pressure Ready Interrupt Mask
• DRDY: Data Ready Interrupt Mask
• GOVRE: General Overrun Error Interrupt Mask
• COMPE: Comparison Event Interrupt Mask
• PEN: Pen Contact Interrupt Mask
• NOPEN: No Pen Contact Interrupt Mask
27
–
19
–
11
EOC11
3
EOC3
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
26
COMPE
18
–
10
EOC10
2
EOC2
25
GOVRE
17
–
9
EOC9
1
EOC1
24
DRDY
16
–
8
EOC8
0
EOC0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
958
42.8.12 ADC Interrupt Status Register
Name:
Address:
Access:
ADC_ISR
0xF804C030
Read-only
31
PENS
30
NOPEN
29
PEN
23
–
15
–
7
EOC7
22
PRDY
14
–
6
EOC6
21
YRDY
13
–
5
EOC5
28
–
20
XRDY
12
–
4
EOC4
27
–
19
–
11
EOC11
3
EOC3
26
COMPE
18
–
10
EOC10
2
EOC2
25
GOVRE
17
–
9
EOC9
1
EOC1
24
DRDY
16
–
8
EOC8
0
EOC0
• EOCx: End of Conversion x
0 = Corresponding analog channel is disabled, or the conversion is not finished. This flag is cleared when reading the corresponding ADC_CDRx registers.
1 = Corresponding analog channel is enabled and conversion is complete.
• XRDY: Touchscreen XPOS Measure Ready
0 = No Measure has been performed since the last read of ADC_XPOSR.
1 = At least one Measure has been performed since the last read of ADC_ISR.
• YRDY: Touchscreen YPOS Measure Ready
0 = No Measure has been performed since the last read of ADC_YPOSR.
1 = At least one Measure has been performed since the last read of ADC_ISR.
• PRDY: Touchscreen Pressure Measure Ready
0 = No Measure has been performed since the last read of ADC_PRESSR.
1 = At least one Measure has been performed since the last read of ADC_ISR.
• DRDY: Data Ready
0 = No data has been converted since the last read of ADC_LCDR.
1 = At least one data has been converted and is available in ADC_LCDR.
• GOVRE: General Overrun Error
0 = No General Overrun Error occurred since the last read of ADC_ISR.
1 = At least one General Overrun Error has occurred since the last read of ADC_ISR.
• COMPE: Comparison Error
0 = No Comparison Error since the last read of ADC_ISR.
1 = At least one Comparison Error (defined in the ADC_EMR and ADC_CWR registers) has occurred since the last read of
ADC_ISR.
SAM9X35 [DATASHEET]
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• PEN: Pen contact
0 = No pen contact since the last read of ADC_ISR.
1 = At least one pen contact since the last read of ADC_ISR.
• NOPEN: No Pen contact
0 = No loss of pen contact since the last read of ADC_ISR.
1 = At least one loss of pen contact since the last read of ADC_ISR.
• PENS: Pen detect Status
0 = The pen does not press the screen.
1 = The pen presses the screen.
Note: PENS is not a source of interruption.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
960
42.8.13 ADC Overrun Status Register
Name:
Address:
Access:
ADC_OVER
0xF804C03C
Read-only
31
–
30
–
29
–
23
–
15
–
7
OVRE7
22
–
14
–
6
OVRE6
21
–
13
–
5
OVRE5
28
–
20
–
12
–
4
OVRE4
27
–
19
–
11
OVRE11
3
OVRE3
26
–
18
–
10
OVRE10
2
OVRE2
• OVREx: Overrun Error x
0 = No overrun error on the corresponding channel since the last read of ADC_OVER.
1 = There has been an overrun error on the corresponding channel since the last read of ADC_OVER.
25
–
17
–
9
OVRE9
1
OVRE1
24
–
16
–
8
OVRE8
0
OVRE0
SAM9X35 [DATASHEET]
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961
42.8.14 ADC Extended Mode Register
Name:
Address:
Access:
ADC_EMR
0xF804C040
Read-write
31
–
30
–
29
–
23
–
15
–
7
22
–
14
–
6
21
–
13
CMPFILTER
12
5 4
28
–
20
–
CMPSEL
11
–
3
–
27
–
19
–
10
–
2
–
26
–
18
–
25
–
17
–
9
CMPALL
1
CMPMODE
8
–
0
24
TAG
16
–
• CMPMODE: Comparison Mode
Value
0
1
2
3
Name
LOW
HIGH
IN
OUT
Description
Generates an event when the converted data is lower than the low threshold of the window.
Generates an event when the converted data is higher than the high threshold of the window.
Generates an event when the converted data is in the comparison window.
Generates an event when the converted data is out of the comparison window.
• CMPSEL: Comparison Selected Channel
If CMPALL = 0: CMPSEL indicates which channel has to be compared.
If CMPALL = 1: No effect.
• CMPALL: Compare All Channels
0 = Only channel indicated in CMPSEL field is compared.
1 = All channels are compared.
• CMPFILTER: Compare Event Filtering
Number of consecutive compare events necessary to raise the flag = CMPFILTER+1
When programmed to 0, the flag rises as soon as an event occurs.
• TAG: TAG of the ADC_LDCR register
0 = Sets CHNB to zero in ADC_LDCR.
1 = Appends the channel number to the conversion result in ADC_LDCR register.
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42.8.15 ADC Compare Window Register
Name:
Address:
Access:
ADC_CWR
0xF804C044
Read-write
31
–
30
–
29
–
23
15
–
7
22
14
–
6
21
13
–
5
28
–
27
20
HIGHTHRES
19
12
–
11
4
LOWTHRES
3
26
HIGHTHRES
25
18 17
10
LOWTHRES
9
2 1
24
16
8
0
• LOWTHRES: Low Threshold
Low threshold associated to compare settings of the ADC_EMR register.
If LOWRES is set in ADC_MR, only the 10 LSB of LOWTHRES must be programmed. The 2 LSB will be automatically discarded to match the value carried on ADC_CDR (8-bit).
• HIGHTHRES: High Threshold
High threshold associated to compare settings of the ADC_EMR register.
If LOWRES is set in ADC_MR, only the 10 LSB of HIGHTHRES must be programmed. The 2 LSB will be automatically discarded to match the value carried on ADC_CDR (8-bit).
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42.8.16 ADC Channel Data Register
Name:
Address:
Access:
ADC_CDRx [x=0..11]
0xF804C050
Read-write
31
–
30
–
29
–
23
–
15
–
7
22
–
14
–
6
21
–
13
–
5
12
–
4
28
–
20
–
27
–
19
–
11
3
26
–
18
–
10
2
DATA
25
–
17
–
9
1
24
–
16
–
8
0
DATA
• DATA: Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.
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42.8.17 ADC Analog Control Register
Name:
Address:
Access:
ADC_ACR
0xF804C094
Read-write
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
12
–
4
–
28
–
20
–
11
–
3
–
27
–
19
–
10
–
2
–
26
–
18
–
25
–
17
–
9
–
1
PENDETSENS
0
24
–
16
–
8
• PENDETSENS: Pen Detection Sensitivity
Allows to modify the pen detection input pull-up resistor value. (See the product electrical characteristics for further details).
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42.8.18 ADC Touchscreen Mode Register
Name:
Address:
Access:
ADC_TSMR
0xF804C0B0
Read-write
31 30 29
PENDBC
23
–
15
–
7
–
22
NOTSDMA
14
–
6
–
21
–
13
–
5
TSAV
28
20
–
12
–
4
27
–
19
11
3
–
26
–
18
TSSCTIM
10
25
–
17
9
TSFREQ
2
–
1
TSMODE
24
PENDET
16
8
0
• TSMODE: Touchscreen Mode
Value
0
1
2
3
Name
NONE
4_WIRE_NO_PM
4_WIRE
5_WIRE
Description
No Touchscreen
4-wire Touchscreen without pressure measurement
4-wire Touchscreen with pressure measurement
5-wire Touchscreen
When TSMOD equals 01 or 10 (i.e. 4-wire mode), channel 0, 1, 2 and 3 must not be used for classic ADC conversions. When
TSMOD equals 11 (i.e. 5-wire mode), channel 0, 1, 2, 3, and 4 must not be used.
• TSAV: Touchscreen Average
Value
0
1
2
3
Name
NO_FILTER
AVG2CONV
AVG4CONV
AVG8CONV
Description
No Filtering. Only one ADC conversion per measure
Averages 2 ADC conversions
Averages 4 ADC conversions
Averages 8 ADC conversions
• TSFREQ: Touchscreen Frequency
Defines the Touchscreen Frequency compared to the Trigger Frequency.
TSFREQ must be greater or equal to TSAV.
The Touchscreen Frequency is:
Touchscreen Frequency = Trigger Frequency / 2 TSFREQ
• TSSCTIM: Touchscreen Switches Closure Time
Defines closure time of analog switches necessary to establish the measurement conditions.
The Closure Time is:
Switch Closure Time = (TSSCTIM * 4) ADCClock periods.
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• PENDET: Pen Contact Detection Enable
0: Pen contact detection disable.
1: Pen contact detection enable.
When PENDET = 1, XPOS, YPOS, Z1, Z2 values of ADC_XPOSR, ADC_YPOSR, ADC_PRESSR registers are automatically cleared when PENS = 0 in ADC_ISR.
• NOTSDMA: No TouchScreen DMA
0: XPOS, YPOS, Z1, Z2 are transmitted in ADC_LCDR.
1: XPOS, YPOS, Z1, Z2 are never transmitted in ADC_LCDR, therefore the buffer does not contains touchscreen values.
• PENDBC: Pen Detect Debouncing Period
Debouncing period = 2 PENDBC ADCClock periods.
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42.8.19 ADC Touchscreen X Position Register
Name:
Address:
Access:
ADC_XPOSR
0xF804C0B4
Read-only
31
–
30
–
29
–
23 22 21
15
–
7
14
–
6
13
–
5
28
–
20
12
–
4
27
XSCALE
19
11
3
XPOS
26
XSCALE
25
18 17
10
2
XPOS
9
1
24
16
8
0
• XPOS: X Position
The Position measured is stored here. if XPOS = 0 or XPOS = XSIZE, the pen is on the border.
When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR register), XPOS is tied to 0 while there is no detection of contact on the touchscreen (i.e. when PENS bitfield is cleared in ADC_ISR register).
• XSCALE: Scale of XPOS
Indicates the max value that XPOS can reach. This value should be close to 2 10 .
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42.8.20 ADC Touchscreen Y Position Register
Name:
Address:
Access:
ADC_YPOSR
0xF804C0B8
Read-only
31
–
30
–
29
–
23 22 21
15
–
7
14
–
6
13
–
5
28
–
20
12
–
4
27
YSCALE
19
11
3
YPOS
26
YSCALE
25
18 17
10
2
YPOS
9
1
24
16
8
0
• YPOS: Y Position
The Position measured is stored here. if YPOS = 0 or YPOS = YSIZE, the pen is on the border.
When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR register), YPOS is tied to 0 while there is no detection of contact on the touchscreen (i.e. when PENS bitfield is cleared in ADC_ISR register).
• YSCALE: Scale of YPOS
Indicates the max value that YPOS can reach. This value should be close to 2 10
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42.8.21 ADC Touchscreen Pressure Register
Name:
Address:
Access:
ADC_PRESSR
0xF804C0BC
Read-only
31
–
30
–
29
–
23 22 21
28
–
20
27
19
26
18
Z2
25
17
24
16
Z2
15
–
7
14
–
6
13
–
5
12
–
4
11
3
10
2
Z1
9
1
8
0
Z1
• Z1: Data of Z1 Measurement
Data Z1 necessary to calculate pen pressure.
When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR register), Z1 is tied to 0 while there is no detection of contact on the touchscreen (i.e. when PENS bitfield is cleared in ADC_ISR register).
• Z2: Data of Z2 Measurement
Data Z2 necessary to calculate pen pressure.
When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR register), Z2 is tied to 0 while there is no detection of contact on the touchscreen (i.e. when PENS bitfield is cleared in ADC_ISR register).
Note: these two values are unavailable if TSMODE is not set to 2 in ADC_TSMR register.
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42.8.22 ADC Trigger Register
Name:
Address:
Access:
ADC_TRGR
0xF804C0C0
Read-write
31 30
23 22
15
–
7
–
14
–
6
–
• TRGMOD: Trigger Mode
29
21
13
–
5
–
12
–
4
–
28
TRGPER
27
20 19
TRGPER
11
–
3
–
26
18
10
–
2
25
17
9
–
1
TRGMOD
24
16
8
–
0
4
5
6
7
Value
0
1
2
3
Name
NO_TRIGGER
EXT_TRIG_RISE
EXT_TRIG_FALL
EXT_TRIG_ANY
PEN_TRIG
PERIOD_TRIG
CONTINUOUS
–
Description
No trigger, only software trigger can start conversions
External Trigger Rising Edge
External Trigger Falling Edge
External Trigger Any Edge
Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touchscreen only mode)
Periodic Trigger (TRGPER shall be initiated appropriately)
Continuous Mode
Reserved
• TRGPER: Trigger Period
Effective only if TRGMOD defines a Periodic Trigger.
Defines the periodic trigger period, with the following equation:
Trigger Period = (TRGPER+1) /ADCCLK
The minimum time between 2 consecutive trigger events must be strictly greater than the duration time of the longest conversion sequence according to configuration of registers ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2, ADC_TSMR.
When TRGMOD is set to pen detect trigger (i.e. 100) and averaging is used (i.e. bitfield TSAV differs from 0 in ADC_TSMR register) only 1 measure is performed. Thus, XRDY, YRDY, PRDY, DRDY will not rise on pen contact trigger. To achieve measurement, several triggers must be provided either by software or by setting the TRGMOD on continuous trigger (i.e. 110) until flags rise.
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42.8.23 ADC Write Protect Mode Register
Name:
Address:
Access:
ADC_WPMR
0xF804C0E4
Read-write
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
WPEN
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII).
Protects the registers:
“ADC Mode Register” on page 948
“ADC Channel Sequence 1 Register” on page 950
“ADC Channel Sequence 2 Register” on page 951
“ADC Channel Enable Register” on page 952
“ADC Channel Disable Register” on page 953
“ADC Extended Mode Register” on page 962
“ADC Compare Window Register” on page 963
“ADC Analog Control Register” on page 965
“ADC Touchscreen Mode Register” on page 966
“ADC Trigger Register” on page 971
• WPKEY: Write Protect KEY
Should be written at value 0x414443 (“ADC” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
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42.8.24 ADC Write Protect Status Register
Name:
Address:
Access:
ADC_WPSR
0xF804C0E8
Read-only
31
–
30
–
29
–
23
15
22
14
21
13
28
–
27
–
20
WPVSRC
19
12
WPVSRC
11
4
–
3
–
26
–
18
10
25
–
17
9
24
–
16
8
7
–
6
–
5
–
2
–
1
–
0
WPVS
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the ADC_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the ADC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted.
Reading ADC_WPSR automatically clears all fields.
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43.
Software Modem Device (SMD)
43.1 Description
The Software Modem Device (SMD) is a block for communication via a modem's Digital Isolation Barrier (DIB) with a complementary Line Side Device (HLSD).
SMD and HLSD are two parts of the "Transformer only" solution. The transformer is the only component connecting SMD and HLSD. The transformer is used for power, clock and data transfers. Power and clock are supplied by the SMD and consumed by the HLSD. The data flow is bidirectional. The data transfer is based on pulse width modulation for transmission from the SMD to the HLSD, and for receiving from the HLSD.
There are two channels embedded into the protocol of the DIB link:
Data channel,
Control channel.
Each channel is bidirectional.
The data channel is used to transfer digitized signal samples at a constant rate of 16 bits at 16 kHz.
The control channel is used to communicate with control registers of the HLSD at a maximum rate of 8 bits at 16 kHz.
The SMD performs all protocol-related data conversion for transmission and received data interpretation in both data and control channels of the link.
The SMD incorporates both RX and TX FIFOs, available through the DMAC interface. Each FIFO is able to hold eight 32bit words (equivalent to 16 modem data samples).
43.2 Embedded Characteristics
Modulations and protocols
V.90
V.34
V.32bis, V.32, V.22bis, V.22, V.23, V.21
V.23 reverse, V.23 half-duplex
Bell 212A/Bell 103
V.29 FastPOS
V.22bis fast connect
V.80 Synchronous Access Mode
Data compression and error correction
V.44 data compression (V.92 model)
V.42bis and MNP 5 data compression
V.42 LAPM and MNP 2-4 error correction
EIA/TIA 578 Class 1 and T.31 Class 1.0
Call Waiting (CW) detection and Type II Caller ID decoding during data mode
Type I Caller ID (CID) decoding
Sixty-three embedded and upgradable country profiles
Embedded AT commands
SmartDAA
Extension pick-up detection
Digital line protection
Line reversal detection
Line-in-use detection
Remote hang-up detection
Worldwide compliance
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43.3 Block Diagram
Figure 43-1. Software Modem Device Block Diagram
S MD Controller
S MD Core
Byte P a r a llel
Interf a ce
CPU
Interr u pt
AHB
AHB
Wr a pper
FIFO
Interf a ce
8 x 3 2 (2)
DMA
P a r a llel
Interf a ce
Control
Ch a nnel Logic
Control/ S t a t us
Regi s ter s
Ring
Detection a nd P u l s e
Di a ling
M a chine s
(m as ter s )
DMA Ch a nnel
Logic
FIFO 2x16
FIFO 2x16
DIB
Interf a ce
Circ u itry
X
DIB
P a d s
X
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44.
Synchronous Serial Controller (SSC)
44.1 Description
The Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short
Frame Sync, Long Frame Sync, etc.
The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the
Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal.
The SSC high-level of programmability and its use of DMA permit a continuous high bit rate data transfer without processor intervention.
Featuring connection to the DMA, the SSC permits interfacing with low processor overhead to the following:
CODEC’s in master or slave mode
DAC through dedicated serial interface, particularly I2S
Magnetic card reader
44.2 Embedded Characteristics
Provides Serial Synchronous Communication Links Used in Audio and Telecom Applications
Contains an Independent Receiver and Transmitter and a Common Clock Divider
Interfaced with the DMA Controller (DMAC) to Reduce Processor Overhead
Offers a Configurable Frame Sync and Data Length
Receiver and Transmitter can be Programmed to Start Automatically or on Detection of Different Events on the
Frame Sync Signal
Receiver and Transmitter Include a Data Signal, a Clock Signal and a Frame Synchronization Signal
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44.3 Block Diagram
Figure 44-1. Block Diagram
System
Bus
APB Bridge
DMA
Peripheral
Bus
PMC
MCK
SSC Interface
PIO
Interrupt Control
SSC Interrupt
44.4 Application Block Diagram
Figure 44-2. Application Block Diagram
OS or RTOS Driver
Serial AUDIO Codec
Power
Management
Interrupt
Management
Test
Management
SSC
Time Slot
Management
Frame
Management
Line Interface
RF
RK
RD
TF
TK
TD
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44.5 Pin Name List
Table 44-1. I/O Lines Description
Pin Name Pin Description
RF Receiver Frame Synchro
RK
RD
TF
TK
TD
Receiver Clock
Receiver Data
Transmitter Frame Synchro
Transmitter Clock
Transmitter Data
Type
Input/Output
Input/Output
Input
Input/Output
Input/Output
Output
44.6 Product Dependencies
44.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode.
Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the
SSC peripheral mode.
Table 44-2. I/O Lines
Instance
SSC
SSC
SSC
SSC
SSC
SSC
Signal
RD
RF
RK
TD
TF
TK
I/O Line
PA27
PA29
PA28
PA26
PA25
PA24
Peripheral
B
B
B
B
B
B
44.6.2 Power Management
The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller
(PMC), therefore the programmer must first configure the PMC to enable the SSC clock.
44.6.3 Interrupt
The SSC interface has an interrupt line connected to the interrupt controller. Handling interrupts requires programming the interrupt controller before configuring the SSC.
All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked
SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register.
Table 44-3. Peripheral IDs
Instance
SSC
ID
28
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44.7 Functional Description
This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format,
Start, Transmitter, Receiver and Frame Sync.
The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2.
Figure 44-3. SSC Functional Block Diagram
MCK Clock
Divider
APB
Transmitter
Clock Output
Controller
TK Input
RX clock
TXEN
RX Start
TF
Start
Selector
Transmit Clock
Controller
TX clock
TX Start
Transmit Shift Register
Transmit Holding
Register
Transmit Sync
Holding Register
Frame Sync
Controller
Data
Controller
TK
TF
TD
User
Interface
Receiver
Clock Output
Controller
RK
Interrupt Control
RK Input
Receive Clock
Controller
RX Clock
TX Clock
RXEN
TX Start
RF
RC0R
Start
Selector
RX Start
Receive Shift Register
Receive Holding
Register
Receive Sync
Holding Register
Frame Sync
Controller
Data
Controller
RF
RD
To Interrupt Controller
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44.7.1 Clock Management
The transmitter clock can be generated by:
an external clock received on the TK I/O pad the receiver clock the internal clock divider
The receiver clock can be generated by:
an external clock received on the RK I/O pad the transmitter clock the internal clock divider
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad.
This allows the SSC to support many Master and Slave Mode data transfers.
44.7.1.1 Clock Divider
Figure 44-4. Divided Clock Block Diagram
Clock Divider
SSC_CMR
MCK Divided Clock
/ 2 12-bit Counter
The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive.
When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd.
Figure 44-5. Divided Clock Generation
Master Clock
Divided Clock
DIV = 1
Divided Clock Frequency = MCK/2
Master Clock
Divided Clock
DIV = 3
Divided Clock Frequency = MCK/6
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44.7.1.2 Transmitter Clock Management
The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR.
The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs.
Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results.
Figure 44-6. Transmitter Clock Management
TK (pin)
MUX Tri_state
Controller
Clock
Output
Receiver
Clock
Divider
Clock
CKO Data Transfer
CKS
INV
MUX
Tri-state
Controller
Transmitter
Clock
CKI CKG
44.7.1.3 Receiver Clock Management
The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR.
The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs.
Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results.
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Figure 44-7. Receiver Clock Management
RK (pin)
MUX
Transmitter
Clock
Divider
Clock
CKS
Tri-state
Controller
Clock
Output
CKO
INV
MUX
Data Transfer
Tri-state
Controller
Receiver
Clock
CKI CKG
44.7.1.4 Serial Clock Ratio Considerations
The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is:
Master Clock divided by 2 if Receiver Frame Synchro is input
Master Clock divided by 3 if Receiver Frame Synchro is output
In addition, the maximum clock speed allowed on the TK pin is:
Master Clock divided by 6 if Transmit Frame Synchro is input
Master Clock divided by 2 if Transmit Frame Synchro is output
44.7.2 Transmitter Operations
A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission.
The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR).
To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected.
When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register.
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Figure 44-8. Transmitter Block Diagram
SSC_CRTXEN
SSC_SRTXEN
SSC_CRTXDIS
TXEN
SSC_RCMR.START
SSC_TCMR.START
TXEN
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
SSC_TFMR.DATNB
SSC_TFMR.DATDEF
SSC_TFMR.MSBF
RXEN
TX Start
RF
RC0R
Start
Selector
RX Start
RF
Start
Selector
TX Start
Transmit Shift Register
SSC_TFMR.FSDEN
SSC_TCMR.STTDLY != 0
0 1
TX Controller
Transmitter Clock
TD
SSC_TFMR.DATLEN
SSC_THR SSC_TSHR SSC_TFMR.FSLEN
TX Controller counter reached STTDLY
44.7.3 Receiver Operations
A received frame is triggered by a start event and can be followed by synchronization data before data transmission.
The start event is configured setting the Receive Clock Mode Register (SSC_RCMR).
The frame synchronization is configured setting the Receive Frame Mode Register ( SSC_RFMR
). See “Frame Sync” on page 986.
The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR.
The data is transferred from the shift register depending on the data format selected.
When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in
SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register.
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Figure 44-9. Receiver Block Diagram
SSC_TCMR.START
SSC_RCMR.START
TXEN
RX Start
RF
Start
Selector
RXEN
RF
RC0R
Start
Selector
SSC_RFMR.MSBF
SSC_RFMR.DATNB
RX Start
Receive Shift Register
SSC_CR.RXEN
SSC_SR.RXEN
SSC_CR.RXDIS
RX Controller
RD
SSC_RCMR.STTDLY != 0 load SSC_RSHR load SSC_RHR
SSC_RFMR.FSLEN
SSC_RFMR.DATLEN
RX Controller counter reached STTDLY
Receiver Clock
44.7.4 Start
The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the
Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR.
Under the following conditions the start event is independently programmable:
Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled.
Synchronously with the transmitter/receiver
On detection of a falling/rising edge on TF/RF
On detection of a low level/high level on TF/RF
On detection of a level change or an edge on TF/RF
A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR).
Thus, the start could be on TF (Transmit) or RF (Receive).
Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions.
Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register
(TFMR/RFMR).
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Figure 44-10.Transmit Start Mode
TK
TF
(Input)
Start = Low Level on TF
TD
(Output)
Start = Falling Edge on TF TD
(Output)
Start = High Level on TF
TD
(Output)
Start = Rising Edge on TF TD
(Output)
Start = Level Change on TF
TD
(Output)
Start = Any Edge on TF
TD
(Output)
X BO B1
STTDLY
X
X
X
BO B1
X
BO
X
BO
B1
BO
B1
BO
STTDLY
BO B1
STTDLY
B1
BO
STTDLY
B1
STTDLY
B1
STTDLY
Figure 44-11.Receive Pulse/Edge Start Modes
RK
RF
(Input)
Start = Low Level on RF
RD
(Input)
Start = Falling Edge on RF RD
(Input)
Start = High Level on RF
Start = Rising Edge on RF
RD
(Input)
RD
(Input)
Start = Level Change on RF
RD
(Input)
Start = Any Edge on RF
RD
(Input)
X BO B1
STTDLY
X BO B1
STTDLY
X
X
X BO B1
STTDLY
BO
BO B1
B1 BO
STTDLY
B1
STTDLY
X BO B1 BO B1
STTDLY
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44.7.5 Frame Sync
The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register
(SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform.
Programmable low or high levels during data transfer are supported.
Programmable high levels before the start of data transfers or toggling are also supported.
If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1 bit time up to 256 bit time.
The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider
Selection (PERIOD) field in SSC_RCMR and SSC_TCMR.
44.7.5.1 Frame Sync Data
Frame Sync Data transmits or receives a specific tag during the Frame Sync signal.
During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding
Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16.
Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync
Holding Register through the Receive Shift Register.
The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in
SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted out.
44.7.5.2 Frame Sync Edge Detection
The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals
RF/TF).
44.7.6 Receive Compare Modes
Figure 44-12.Receive Compare Modes
RK
RD
(Input)
CMP0 CMP1 CMP2 CMP3
Start
Ignored B0 B1 B2
FSLEN
Up to 16 Bits
(4 in This Example)
STDLY DATLEN
44.7.6.1 Compare Functions
Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR.
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44.7.7 Data Format
The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode
Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select:
the event that starts the data transfer (START) the delay in number of bit periods between the start event and the first data bit (STTDLY) the length of the data (DATLEN) the number of data to be transferred for each start event (DATNB).
the length of synchronization transferred for each start event (FSLEN) the bit sense: most or lowest significant bit first (MSBF)
Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default
Value (DATDEF) bits in SSC_TFMR.
Table 44-4. Data Frame Registers
Transmitter Receiver
SSC_TFMR SSC_RFMR
SSC_TFMR
SSC_TFMR
SSC_TFMR
SSC_RFMR
SSC_RFMR
SSC_RFMR
SSC_TFMR
SSC_TFMR
SSC_TCMR
SSC_TCMR
SSC_RCMR
SSC_RCMR
Field
DATLEN
DATNB
MSBF
FSLEN
DATDEF
FSDEN
PERIOD
STTDLY
Length
Up to 32
Up to 16
Up to 16
0 or 1
Up to 512
Up to 255
Comment
Size of word
Number of words transmitted in frame
Most significant bit first
Size of Synchro data register
Data default value ended
Enable send SSC_TSHR
Frame size
Size of transmit start delay
Figure 44-13.Transmit and Receive Frame Format in Edge/Pulse Start Modes
Start
PERIOD
TF/RF
(1)
FSLEN
TD
(If FSDEN = 1)
Sync Data Default
From SSC_TSHR FromDATDEF
Data
From SSC_THR
TD
(If FSDEN = 0)
RD
Default
From DATDEF
Ignored Sync Data
To SSC_RSHR
Data
From SSC_THR
Data
To SSC_RHR
Data
From SSC_THR
Data
From SSC_THR
Data
To SSC_RHR
STTDLY DATLEN DATLEN
Start
Default
FromDATDEF
Sync Data
Default
From DATDEF
Ignored Sync Data
DATNB
Note: 1. Example of input on falling edge of TF/RF.
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Figure 44-14.Transmit Frame Format in Continuous Mode
Start
TD
Data
From SSC_THR
DATLEN
Data
From SSC_THR
DATLEN
Default
Start: 1. TXEMPTY set to 1
2. Write into the SSC_THR
Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode.
Figure 44-15.Receive Frame Format in Continuous Mode
Start = Enable Receiver
RD Data
To SSC_RHR
DATLEN
Data
To SSC_RHR
DATLEN
Note: 1. STTDLY is set to 0.
44.7.8 Loop Mode
The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode
(LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK.
44.7.9 Interrupt
Most bits in SSC_SR have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing
SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask
Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the interrupt controller.
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Figure 44-16.Interrupt Block Diagram
Transmitter
TXRDY
TXEMPTY
TXSYNC
Receiver
RXRDY
OVRUN
RXSYNC
SSC_IMR
SSC_IER
Set
SSC_IDR
Clear
Interrupt
Control
SSC Interrupt
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44.8 SSC Application Examples
The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here.
Figure 44-17.Audio Application Block Diagram
Clock SCK
TK
Word Select WS
TF
Data SD
TD
SSC
RD Clock SCK
I2S
RECEIVER
RF
Word Select WS
RK
Data SD MSB
Left Channel
LSB MSB
Right Channel
Figure 44-18.Codec Application Block Diagram
Serial Data Clock (SCLK)
TK
Frame sync (FSYNC)
TF
Serial Data Out
TD
SSC
Serial Data In
RD
RF
RK
Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data In
CODEC
First Time Slot
Dstart Dend
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Figure 44-19.Time Slot Application Block Diagram
SCLK
TK
FSYNC
TF
Data Out
TD
SSC
Data in
RD
RF
RK
CODEC
First
Time Slot
CODEC
Second
Time Slot
Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data in
First Time Slot
Dstart
Second Time Slot
Dend
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44.8.1 Write Protection Registers
To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Protect Status Register
(US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the SSC Write Protect Mode Register (SSC_WPMR) with the appropriate access key,
WPKEY.
The protected registers are:
“SSC Clock Mode Register” on page 995
“SSC Receive Clock Mode Register” on page 996
“SSC Receive Frame Mode Register” on page 998
“SSC Transmit Clock Mode Register” on page 1000
“SSC Transmit Frame Mode Register” on page 1002
“SSC Receive Compare 0 Register” on page 1006
“SSC Receive Compare 1 Register” on page 1006
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44.9 Synchronous Serial Controller (SSC) User Interface
Table 44-5. Register Mapping
Offset Register
0x0 Control Register
0x4
0x8
0xC
0x10
0x14
Clock Mode Register
Reserved
Reserved
Receive Clock Mode Register
Receive Frame Mode Register
0x30
0x34
0x38
0x3C
0x40
0x44
0x18
0x1C
0x20
0x24
0x28
0x2C
Transmit Clock Mode Register
Transmit Frame Mode Register
Receive Holding Register
Transmit Holding Register
Reserved
Reserved
Receive Sync. Holding Register
Transmit Sync. Holding Register
Receive Compare 0 Register
Receive Compare 1 Register
Status Register
Interrupt Enable Register
0x48
0x4C
0xE4
Interrupt Disable Register
Interrupt Mask Register
Write Protect Mode Register
0xE8
0x50-0xFC
Write Protect Status Register
Reserved
0x100-0x124 Reserved
Name
SSC_CR
SSC_CMR
–
–
SSC_RCMR
SSC_RFMR
SSC_TCMR
SSC_TFMR
SSC_RHR
SSC_THR
–
–
SSC_RSHR
SSC_TSHR
SSC_RC0R
SSC_RC1R
SSC_SR
SSC_IER
SSC_IDR
SSC_IMR
SSC_WPMR
SSC_WPSR
–
–
Access
Write-only
Read-write
–
–
Read-write
Read-write
Read-write
Read-write
Read-only
Write-only
–
–
Read-only
Read-write
Read-write
Read-write
Read-only
Write-only
Write-only
Read-only
Read-write
Read-only
–
–
0x0
0x0
0x0
–
–
–
0x0
0x0
0x0
0x0
0x000000CC
–
–
0x0
0x0
0x0
–
–
Reset
–
0x0
–
–
0x0
0x0
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44.9.1 SSC Control Register
Name:
Address:
Access:
SSC_CR:
0xF0010000
Write-only
31
–
30
–
23
–
15
SWRST
7
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
TXDIS
1
RXDIS
• RXEN: Receive Enable
0 = No effect.
1 = Enables Receive if RXDIS is not set.
• RXDIS: Receive Disable
0 = No effect.
1 = Disables Receive. If a character is currently being received, disables at end of current character reception.
• TXEN: Transmit Enable
0 = No effect.
1 = Enables Transmit if TXDIS is not set.
• TXDIS: Transmit Disable
0 = No effect.
1 = Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission.
• SWRST: Software Reset
0 = No effect.
1 = Performs a software reset. Has priority on any other bit in SSC_CR.
24
–
16
–
8
TXEN
0
RXEN
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44.9.2 SSC Clock Mode Register
Name:
Address:
Access:
SSC_CMR
0xF0010004
Read-write
31
–
30
–
29
–
23
–
15
–
7
22
–
14
–
6
21
–
13
–
5
28
–
20
–
12
–
4
27
–
19
–
11
3
26
–
18
–
10
2
DIV
25
–
17
–
9
1
DIV
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• DIV: Clock Divider
0 = The Clock Divider is not active.
Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2.
The minimum bit rate is MCK/2 x 4095 = MCK/8190.
24
–
16
–
8
0
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44.9.3 SSC Receive Clock Mode Register
Name:
Address:
Access:
SSC_RCMR
0xF0010010
Read-write
31 30 29
23
15
–
7
22
14
–
6
21
13
–
5
CKI
28
PERIOD
27
20
STTDLY
19
11 12
STOP
4 3
CKO
26
18
10
2
START
CKG
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• CKS: Receive Clock Selection
Value Name Description
0
1
MCK
TK
Divided Clock
TK Clock signal
2 RK RK pin
25
17
9
1
CKS
24
16
8
0
• CKO: Receive Clock Output Mode Selection
Value Name Description
0 NONE None, RK pin is an input
1
2
CONTINUOUS
TRANSFER
Continuous Receive Clock, RK pin is an output
Receive Clock only during data transfers, RK pin is an output
• CKI: Receive Clock Inversion
0 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge.
1 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge.
CKI affects only the Receive Clock and not the output clock signal.
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• CKG: Receive Clock Gating Selection
Value Name Description
0
1
2
CONTINUOUS
EN_RF_LOW
EN_RF_HIGH
None
Receive Clock enabled only if RF Pin is Low
Receive Clock enabled only if RF Pin is High
• START: Receive Start Selection
Value Name Description
0
7
8
5
6
3
4
1
2
CONTINUOUS
TRANSMIT
RF_LOW
RF_HIGH
RF_FALLING
RF_RISING
RF_LEVEL
RF_EDGE
CMP_0
Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
Transmit start
Detection of a low level on RF signal
Detection of a high level on RF signal
Detection of a falling edge on RF signal
Detection of a rising edge on RF signal
Detection of any level change on RF signal
Detection of any edge on RF signal
Compare 0
• STOP: Receive Stop Selection
0 = After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0.
1 = After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• STTDLY: Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the
Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync
Data) reception.
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
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44.9.4 SSC Receive Frame Mode Register
Name:
Address:
Access:
SSC_RFMR
0xF0010014
Read-write
31 30
FSLEN_EXT
29
23
–
15
–
7
MSBF
22
14
–
6
–
21
FSOS
13
–
5
LOOP
28
20
12
–
4
27
–
19
11
3
26
–
18
10
DATNB
2
DATLEN
FSLEN
9
1
25
–
17
24
FSEDGE
16
8
0
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• DATLEN: Data Length
0 = Forbidden value (1-bit data length not supported).
Any other value: The bit stream contains DATLEN + 1 data bits.
• LOOP: Loop Mode
0 = Normal operating mode.
1 = RD is driven by TD, RF is driven by TF and TK drives RK.
• MSBF: Most Significant Bit First
0 = The lowest significant bit of the data register is sampled first in the bit stream.
1 = The most significant bit of the data register is sampled first in the bit stream.
• DATNB: Data Number per Frame
This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).
• FSLEN: Receive Frame Sync Length
This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the
START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register.
This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal.
Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Receive Clock periods.
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• FSOS: Receive Frame Sync Output Selection
Value Name Description
3
4
5
0
1
2
NONE
NEGATIVE
POSITIVE
LOW
HIGH
TOGGLING
None, RF pin is an input
Negative Pulse, RF pin is an output
Positive Pulse, RF pin is an output
Driven Low during data transfer, RF pin is an output
Driven High during data transfer, RF pin is an output
Toggling at each start of data transfer, RF pin is an output
• FSEDGE: Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
Value Name Description
0 POSITIVE Positive Edge Detection
1 NEGATIVE Negative Edge Detection
• FSLEN_EXT: FSLEN Field Extension
Extends FSLEN field. For details, refer to FSLEN bit description on page 998
.
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44.9.5 SSC Transmit Clock Mode Register
Name:
Address:
Access:
SSC_TCMR
0xF0010018
Read-write
31 30 29
23
15
–
7
22
14
–
6
21
13
–
5
CKI
12
–
4
28
PERIOD
27
20
STTDLY
19
11
3
CKO
26
18
10
2
START
CKG
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• CKS: Transmit Clock Selection
Value Name Description
0
1
MCK
RK
Divided Clock
RK Clock signal
2 TK TK pin
25
17
9
1
CKS
24
16
8
0
• CKO: Transmit Clock Output Mode Selection
Value Name Description
0 NONE None, TK pin is an input
1
2
CONTINUOUS
TRANSFER
Continuous Transmit Clock, TK pin is an output
Transmit Clock only during data transfers, TK pin is an output
• CKI: Transmit Clock Inversion
0 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge.
1 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge.
CKI affects only the Transmit Clock and not the output clock signal.
• CKG: Transmit Clock Gating Selection
Value Name Description
0
1
2
CONTINUOUS
EN_TF_LOW
EN_TF_HIGH
None
Transmit Clock enabled only if TF pin is Low
Transmit Clock enabled only if TF pin is High
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1000
• START: Transmit Start Selection
Value Name Description
0
6
7
4
5
1
2
3
CONTINUOUS
RECEIVE
TF_LOW
TF_HIGH
TF_FALLING
TF_RISING
TF_LEVEL
TF_EDGE
Continuous, as soon as a word is written in the SSC_THR
Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.
Receive start
Detection of a low level on TF signal
Detection of a high level on TF signal
Detection of a falling edge on TF signal
Detection of a rising edge on TF signal
Detection of any level change on TF signal
Detection of any edge on TF signal
• STTDLY: Transmit Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied.
Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG.
• PERIOD: Transmit Period Divider Selection
This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1001
44.9.6 SSC Transmit Frame Mode Register
Name:
Address:
Access:
SSC_TFMR
0xF001001C
Read-write
31 30
FSLEN_EXT
29
22 23
FSDEN
15
–
7
MSBF
14
–
6
–
21
FSOS
13
–
5
DATDEF
28
20
12
–
4
27
–
19
11
26
–
18
10
FSLEN
DATNB
3 2
DATLEN
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• DATLEN: Data Length
0 = Forbidden value (1-bit data length not supported).
Any other value: The bit stream contains DATLEN + 1 data bits. .
25
–
17
9
1
24
FSEDGE
16
8
0
• DATDEF: Data Default Value
This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO
Controller, the pin is enabled only if the SCC TD output is 1.
• MSBF: Most Significant Bit First
0 = The lowest significant bit of the data register is shifted out first in the bit stream.
1 = The most significant bit of the data register is shifted out first in the bit stream.
• DATNB: Data Number per frame
This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1).
• FSLEN: Transmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data
Register if FSDEN is 1.
This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal.
Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Transmit Clock period.
• FSOS: Transmit Frame Sync Output Selection
Value Name Description
0 NONE None, TF pin is an input
1
2
NEGATIVE
POSITIVE
Negative Pulse, TF pin is an output
Positive Pulse,TF pin is an output
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1002
Value
3
4
5
Name
LOW
HIGH
TOGGLING
Description
TF pin Driven Low during data transfer
TF pin Driven High during data transfer
TF pin Toggles at each start of data transfer
• FSDEN: Frame Sync Data Enable
0 = The TD line is driven with the default value during the Transmit Frame Sync signal.
1 = SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
• FSEDGE: Frame Sync Edge Detection
Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
Value Name Description
0 POSITIVE Positive Edge Detection
1 NEGATIVE Negative Edge Detection
• FSLEN_EXT: FSLEN Field Extension
Extends FSLEN field. For details, refer to FSLEN bit description on page 1002
.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1003
44.9.7 SSC Receive Holding Register
Name:
Address:
Access:
SSC_RHR
0xF0010020
Read-only
31 30 29 28 27 26
RDAT
23 22 21 20 19 18
RDAT
15 14 13 12 11 10
RDAT
7 6 5 4 3
RDAT
• RDAT: Receive Data
Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
2
44.9.8 SSC Transmit Holding Register
Name:
Address:
Access:
31
SSC_THR
0xF0010024
Write-only
30 29 28 27 26
TDAT
23 22 21 20 19 18
TDAT
15 14 13 12 11 10
TDAT
7 6 5 4 3
TDAT
• TDAT: Transmit Data
Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
2
9
1
25
17
8
0
24
16
9
1
25
17
8
0
24
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1004
44.9.9 SSC Receive Synchronization Holding Register
Name:
Address:
Access:
SSC_RSHR
0xF0010030
Read-only
31
–
30
–
29
–
28
–
23
–
15
22
–
14
21
–
13
20
–
12
RSDAT
27
–
19
–
11
7 6 5 4 3
RSDAT
• RSDAT: Receive Synchronization Data
44.9.10 SSC Transmit Synchronization Holding Register
Name:
Address:
Access:
31
–
SSC_TSHR
0xF0010034
Read-write
30
–
29
–
28
–
23
–
15
22
–
14
21
–
13
20
–
12
TSDAT
27
–
19
–
11
7 6 5 4 3
TSDAT
• TSDAT: Transmit Synchronization Data
26
–
18
–
10
2
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
–
8
0
25
–
17
–
9
1
24
–
16
–
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1005
44.9.11 SSC Receive Compare 0 Register
Name:
Address:
Access:
SSC_RC0R
0xF0010038
Read-write
31
–
30
–
29
–
23
–
15
22
–
14
21
–
13
28
–
20
–
12
27
–
19
–
11
26
–
18
–
10
CP0
7 6 5 4 3 2
CP0
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• CP0: Receive Compare Data 0
25
–
17
–
9
1
44.9.12 SSC Receive Compare 1 Register
Name:
Address:
Access:
31
–
SSC_RC1R
0xF001003C
Read-write
30
–
29
–
23
–
15
22
–
14
21
–
13
28
–
20
–
12
27
–
19
–
11
26
–
18
–
10
CP1
7 6 5 4 3 2
CP1
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• CP1: Receive Compare Data 1
25
–
17
–
9
1
24
–
16
–
8
0
24
–
16
–
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1006
44.9.13 SSC Status Register
Name:
Address:
Access:
SSC_SR
0xF0010040
Read-only
31
–
30
–
23
–
15
–
7
–
22
–
14
–
6
–
29
–
21
–
13
–
5
OVRUN
28
–
20
–
12
–
4
RXRDY
27
–
19
–
11
RXSYN
3
–
26
–
18
–
10
TXSYN
2
–
25
–
17
RXEN
9
CP1
1
TXEMPTY
• TXRDY: Transmit Ready
0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).
1 = SSC_THR is empty.
• TXEMPTY: Transmit Empty
0 = Data remains in SSC_THR or is currently transmitted from TSR.
1 = Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.
• RXRDY: Receive Ready
0 = SSC_RHR is empty.
1 = Data has been received and loaded in SSC_RHR.
• OVRUN: Receive Overrun
0 = No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.
1 = Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.
• CP0: Compare 0
0 = A compare 0 has not occurred since the last read of the Status Register.
1 = A compare 0 has occurred since the last read of the Status Register.
• CP1: Compare 1
0 = A compare 1 has not occurred since the last read of the Status Register.
1 = A compare 1 has occurred since the last read of the Status Register.
• TXSYN: Transmit Sync
0 = A Tx Sync has not occurred since the last read of the Status Register.
1 = A Tx Sync has occurred since the last read of the Status Register.
• RXSYN: Receive Sync
0 = An Rx Sync has not occurred since the last read of the Status Register.
1 = An Rx Sync has occurred since the last read of the Status Register.
24
–
16
TXEN
8
CP0
0
TXRDY
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1007
• TXEN: Transmit Enable
0 = Transmit is disabled.
1 = Transmit is enabled.
• RXEN: Receive Enable
0 = Receive is disabled.
1 = Receive is enabled.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1008
44.9.14 SSC Interrupt Enable Register
Name:
Address:
Access:
SSC_IER
0xF0010044
Write-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
OVRUN
• TXRDY: Transmit Ready Interrupt Enable
0 = No effect.
1 = Enables the Transmit Ready Interrupt.
• TXEMPTY: Transmit Empty Interrupt Enable
0 = No effect.
1 = Enables the Transmit Empty Interrupt.
• RXRDY: Receive Ready Interrupt Enable
0 = No effect.
1 = Enables the Receive Ready Interrupt.
• OVRUN: Receive Overrun Interrupt Enable
0 = No effect.
1 = Enables the Receive Overrun Interrupt.
• CP0: Compare 0 Interrupt Enable
0 = No effect.
1 = Enables the Compare 0 Interrupt.
• CP1: Compare 1 Interrupt Enable
0 = No effect.
1 = Enables the Compare 1 Interrupt.
• TXSYN: Tx Sync Interrupt Enable
0 = No effect.
1 = Enables the Tx Sync Interrupt.
• RXSYN: Rx Sync Interrupt Enable
0 = No effect.
1 = Enables the Rx Sync Interrupt.
28
–
20
–
12
–
4
RXRDY
27
–
19
–
11
RXSYN
3
–
26
–
18
–
10
TXSYN
2
–
25
–
17
–
9
CP1
1
TXEMPTY
24
–
16
–
8
CP0
0
TXRDY
SAM9X35 [DATASHEET]
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1009
44.9.15 SSC Interrupt Disable Register
Name:
Address:
Access:
SSC_IDR
0xF0010048
Write-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
OVRUN
• TXRDY: Transmit Ready Interrupt Disable
0 = No effect.
1 = Disables the Transmit Ready Interrupt.
• TXEMPTY: Transmit Empty Interrupt Disable
0 = No effect.
1 = Disables the Transmit Empty Interrupt.
• RXRDY: Receive Ready Interrupt Disable
0 = No effect.
1 = Disables the Receive Ready Interrupt.
• OVRUN: Receive Overrun Interrupt Disable
0 = No effect.
1 = Disables the Receive Overrun Interrupt.
• CP0: Compare 0 Interrupt Disable
0 = No effect.
1 = Disables the Compare 0 Interrupt.
• CP1: Compare 1 Interrupt Disable
0 = No effect.
1 = Disables the Compare 1 Interrupt.
• TXSYN: Tx Sync Interrupt Enable
0 = No effect.
1 = Disables the Tx Sync Interrupt.
• RXSYN: Rx Sync Interrupt Enable
0 = No effect.
1 = Disables the Rx Sync Interrupt.
28
–
20
–
12
–
4
RXRDY
27
–
19
–
11
RXSYN
3
–
26
–
18
–
10
TXSYN
2
–
25
–
17
–
9
CP1
1
TXEMPTY
24
–
16
–
8
CP0
0
TXRDY
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1010
44.9.16 SSC Interrupt Mask Register
Name:
Address:
Access:
SSC_IMR
0xF001004C
Read-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
OVRUN
• TXRDY: Transmit Ready Interrupt Mask
0 = The Transmit Ready Interrupt is disabled.
1 = The Transmit Ready Interrupt is enabled.
• TXEMPTY: Transmit Empty Interrupt Mask
0 = The Transmit Empty Interrupt is disabled.
1 = The Transmit Empty Interrupt is enabled.
• RXRDY: Receive Ready Interrupt Mask
0 = The Receive Ready Interrupt is disabled.
1 = The Receive Ready Interrupt is enabled.
• OVRUN: Receive Overrun Interrupt Mask
0 = The Receive Overrun Interrupt is disabled.
1 = The Receive Overrun Interrupt is enabled.
• CP0: Compare 0 Interrupt Mask
0 = The Compare 0 Interrupt is disabled.
1 = The Compare 0 Interrupt is enabled.
• CP1: Compare 1 Interrupt Mask
0 = The Compare 1 Interrupt is disabled.
1 = The Compare 1 Interrupt is enabled.
• TXSYN: Tx Sync Interrupt Mask
0 = The Tx Sync Interrupt is disabled.
1 = The Tx Sync Interrupt is enabled.
• RXSYN: Rx Sync Interrupt Mask
0 = The Rx Sync Interrupt is disabled.
1 = The Rx Sync Interrupt is enabled.
28
–
20
–
12
–
4
RXRDY
27
–
19
–
11
RXSYN
3
–
26
–
18
–
10
TXSYN
2
–
25
–
17
–
9
CP1
1
TXEMPTY
24
–
16
–
8
CP0
0
TXRDY
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1011
44.9.17 SSC Write Protect Mode Register
Name:
Address:
Access:
Reset:
SSC_WPMR
0xF00100E4
Read-write
See
31 30 29
23
15
22
14
21
13
28
WPKEY
27
20 19
WPKEY
12 11
WPKEY
4
—
3
—
26
18
10
25
17
9
24
16
8
7
—
6
—
5
—
2
—
1
—
0
WPEN
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
Protects the registers:
•
“SSC Clock Mode Register” on page 995
•
“SSC Receive Clock Mode Register” on page 996
•
“SSC Receive Frame Mode Register” on page 998
•
“SSC Transmit Clock Mode Register” on page 1000
•
“SSC Transmit Frame Mode Register” on page 1002
•
“SSC Receive Compare 0 Register” on page 1006
•
“SSC Receive Compare 1 Register” on page 1006
• WPKEY: Write Protect KEY
Should be written at value 0x535343 (“SSC” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1012
44.9.18 SSC Write Protect Status Register
Name:
Address:
Access:
Reset:
SSC_WPSR
0xF00100E8
Read-only
See
31
—
30
—
29
—
23
15
22
14
21
13
28
—
27
—
20
WPVSRC
19
12
WPVSRC
11
4
—
3
—
26
—
18
10
25
—
17
9
24
—
16
8
7
—
6
—
5
—
2
—
1
—
0
WPVS
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the SSC_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the SSC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted.
Note: Reading SSC_WPSR automatically clears all fields.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1013
45.
Ethernet MAC 10/100 (EMAC)
45.1 Description
The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface.
The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal.
The statistics register block contains registers for counting various types of event associated with transmit and receive operations. These registers, along with the status words stored in the receive buffer list, enable software to generate network management statistics compatible with IEEE 802.3.
45.2 Embedded Characteristics
Supports RMII Interface to the physical layer
Compatible with IEEE Standard 802.3
10 and 100 Mbit/s Operation
Full- and Half-duplex Operation
Statistics Counter Registers
Interrupt Generation to Signal Receive and Transmit Completion
DMA Master on Receive and Transmit Channels
Transmit and Receive FIFOs
Automatic Pad and CRC Generation on Transmitted Frames
Automatic Discard of Frames Received with Errors
Address Checking Logic Supports Up to Four Specific 48-bit Addresses
Supports Promiscuous Mode Where All Valid Received Frames are Copied to Memory
Hash Matching of Unicast and Multicast Destination Addresses
Physical Layer Management through MDIO Interface
Half-duplex Flow Control by Forcing Collisions on Incoming Frames
Full-duplex Flow Control with Recognition of Incoming Pause Frames
Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and Priority Tagged Frames
Multiple Buffers per Receive and Transmit Frame
Jumbo Frames Up to 10240 bytes Supported
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1014
45.3 Block Diagram
Figure 45-1. EMAC Block Diagram
APB
Slave
Register Interface
Address Checker
Statistics Registers
Control Registers
DMA Interface
RX FIFO TX FIFO
AHB
Master
Ethernet Receive
Ethernet Transmit
MDIO
MII/RMII
SAM9X35 [DATASHEET]
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1015
45.4 Functional Description
The MACB has several clock domains:
System bus clock (AHB and APB): DMA and register blocks
Transmit clock: transmit block
Receive clock: receive and address checker block
The system bus clock must run at least as fast as the receive clock and transmit clock (25 MHz at 100 Mbps, and 2.5
MHZ at 10 Mbps).
Figure 45-1 illustrates the different blocks of the EMAC module.
The control registers drive the MDIO interface, setup up DMA activity, start frame transmission and select modes of operation such as full- or half-duplex.
The receive block checks for valid preamble, FCS, alignment and length, and presents received frames to the address checking block and DMA interface.
The transmit block takes data from the DMA interface, adds preamble and, if necessary, pad and FCS, and transmits data according to the CSMA/CD (carrier sense multiple access with collision detect) protocol. The start of transmission is deferred if CRS (carrier sense) is active.
If COL (collision) becomes active during transmission, a jam sequence is asserted and the transmission is retried after a random back off. CRS and COL have no effect in full duplex mode.
The DMA block connects to external memory through its AHB bus interface. It contains receive and transmit FIFOs for buffering frame data. It loads the transmit FIFO and empties the receive FIFO using AHB bus master operations. Receive data is not sent to memory until the address checking logic has determined that the frame should be copied. Receive or transmit frames are stored in one or more buffers. Receive buffers have a fixed length of 128 bytes. Transmit buffers range in length between 0 and 2047 bytes, and up to 128 buffers are permitted per frame. The DMA block manages the transmit and receive framebuffer queues. These queues can hold multiple frames.
45.4.1 Clock
Synchronization module in the EMAC requires that the bus clock (MCK) runs at the speed of the macb_tx/rx_clk at least, which is 25 MHz at 100 Mbps, and 2.5 MHz at 10 Mbps.
45.4.2 Memory Interface
Frame data is transferred to and from the EMAC through the DMA interface. All transfers are 32-bit words and may be single accesses or bursts of 2, 3 or 4 words. Burst accesses do not cross sixteen-byte boundaries. Bursts of 4 words are the default data transfer; single accesses or bursts of less than four words may be used to transfer data at the beginning or the end of a buffer.
The DMA controller performs six types of operation on the bus. In order of priority, these are:
1.
Receive buffer manager write
2.
Receive buffer manager read
3.
Transmit data DMA read
4.
Receive data DMA write
5.
Transmit buffer manager read
6.
Transmit buffer manager write
SAM9X35 [DATASHEET]
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1016
45.4.2.1 FIFO
The FIFO depths are 1
28 bytes for receive and 1
28 bytes for transmit and are a function of the system clock speed, memory latency and network speed.
Data is typically transferred into and out of the FIFOs in bursts of four words. For receive, a bus request is asserted when the FIFO contains four words and has space for 28 more. For transmit, a bus request is generated when there is space for four words, or when there is space for 27 words if the next transfer is to be only one or two words.
Thus the bus latency must be less than the time it takes to load the FIFO and transmit or receive three words (112 bytes) of data.
At 100 Mbit/s, it takes 8960 ns to transmit or receive 112 bytes of data. In addition, six master clock cycles should be allowed for data to be loaded from the bus and to propagate through the FIFOs. For a 133 MHz master clock this takes
45 ns, making the bus latency requirement 8915 ns.
45.4.2.2 Receive Buffers
Received frames, including CRC/FCS optionally, are written to receive buffers stored in memory. Each receive buffer is
128 bytes long. The start location for each receive buffer is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. The receive buffer start location is a word address. For the first buffer of a frame, the start location can be offset by up to three bytes depending on the value written to bits 14 and 15 of the network configuration register. If the start location of the buffer is offset the available length of the first buffer of a frame is reduced by the corresponding number of bytes.
Each list entry consists of two words, the first being the address of the receive buffer and the second being the receive status. If the length of a receive frame exceeds the buffer length, the status word for the used buffer is written with zeroes except for the “start of frame” bit and the offset bits, if appropriate. Bit zero of the address field is written to one to show the buffer has been used. The receive buffer manager then reads the location of the next receive buffer and fills that with
details of the receive buffer descriptor list.
27
26
25
24
31
30
29
28
23
22
Table 45-1. Receive Buffer Descriptor Entry
Bit
31:2
1
0
Function
Word 0
Address of beginning of buffer
Wrap - marks last descriptor in receive buffer descriptor list.
Ownership - needs to be zero for the EMAC to write data to the receive buffer. The EMAC sets this to one once it has successfully written a frame to memory.
Software has to clear this bit before the buffer can be used again.
Word 1
Global all ones broadcast address detected
Multicast hash match
Unicast hash match
External address match
Reserved for future use
Specific address register 1 match
Specific address register 2 match
Specific address register 3 match
Specific address register 4 match
Type ID match
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1017
Table 45-1. Receive Buffer Descriptor Entry (Continued)
Bit
21 VLAN tag detected (i.e., type id of 0x8100)
20
19:17
16
15
14
13:12
11:0
Function
Priority tag detected (i.e., type id of 0x8100 and null VLAN identifier)
VLAN priority (only valid if bit 21 is set)
Concatenation format indicator (CFI) bit (only valid if bit 21 is set)
End of frame - when set the buffer contains the end of a frame. If end of frame is not set, then the only other valid status are bits 12, 13 and 14.
Start of frame - when set the buffer contains the start of a frame. If both bits 15 and 14 are set, then the buffer contains a whole frame.
Receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address.
Updated with the current values of the network configuration register. If jumbo frame mode is enabled through bit 3 of the network configuration register, then bits 13:12 of the receive buffer descriptor entry are used to indicate bits 13:12 of the frame length.
Length of frame including FCS (if selected). Bits 13:12 are also used if jumbo frame mode is selected.
To receive frames, the buffer descriptors must be initialized by writing an appropriate address to bits 31 to 2 in the first word of each list entry. Bit zero must be written with zero. Bit one is the wrap bit and indicates the last entry in the list.
The start location of the receive buffer descriptor list must be written to the receive buffer queue pointer register before setting the receive enable bit in the network control register to enable receive. As soon as the receive block starts writing received frame data to the receive FIFO, the receive buffer manager reads the first receive buffer location pointed to by the receive buffer queue pointer register.
If the filter block then indicates that the frame should be copied to memory, the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered. If the current buffer pointer has its wrap bit set or is the 1024 th descriptor, the next receive buffer location is read from the beginning of the receive descriptor list. Otherwise, the next receive buffer location is read from the next word in memory.
There is an 11-bit counter to count out the 2048 word locations of a maximum length, receive buffer descriptor list. This is added with the value originally written to the receive buffer queue pointer register to produce a pointer into the list. A read of the receive buffer queue pointer register returns the pointer value, which is the queue entry currently being accessed.
The counter is reset after receive status is written to a descriptor that has its wrap bit set or rolls over to zero after 1024 descriptors have been accessed. The value written to the receive buffer pointer register may be any word-aligned address, provided that there are at least 2048 word locations available between the pointer and the top of the memory.
Section 3.6 of the AMBA 2.0 specification states that bursts should not cross 1K boundaries. As receive buffer manager writes are bursts of two words, to ensure that this does not occur, it is best to write the pointer register with the least three significant bits set to zero. As receive buffers are used, the receive buffer manager sets bit zero of the first word of the descriptor to indicate used . If a receive error is detected the receive buffer currently being written is recovered. Previous buffers are not recovered. Software should search through the used bits in the buffer descriptors to find out how many frames have been received. It should be checking the start-of-frame and end-of-frame bits, and not rely on the value returned by the receive buffer queue pointer register which changes continuously as more buffers are used.
For CRC errored frames, excessive length frames or length field mismatched frames, all of which are counted in the statistics registers, it is possible that a frame fragment might be stored in a sequence of receive buffers. Software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set.
For a properly working Ethernet system, there should be no excessively long frames or frames greater than 128 bytes with CRC/FCS errors. Collision fragments are less than 128 bytes long. Therefore, it is a rare occurrence to find a frame fragment in a receive buffer.
If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the DMA block sets the buffer not available bit in the receive status register and triggers an interrupt.
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If bit zero is set when the receive buffer manager reads the location of the receive buffer and a frame is being received, the frame is discarded and the receive resource error statistics register is incremented.
A receive overrun condition occurs when bus was not granted in time or because HRESP was not OK (bus error). In a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently being written is recovered.
The next frame received with an address that is recognized reuses the buffer.
If bit 17 of the network configuration register is set, the FCS of received frames shall not be copied to memory. The frame length indicated in the receive status field shall be reduced by four bytes in this case.
45.4.2.3 Transmit Buffer
Frames to be transmitted are stored in one or more transmit buffers. Transmit buffers can be between 0 and 2047 bytes long, so it is possible to transmit frames longer than the maximum length specified in IEEE Standard 802.3. Zero length buffers are allowed. The maximum number of buffers permitted for each transmit frame is 128.
The start location for each transmit buffer is stored in memory in a list of transmit buffer descriptors at a location pointed to by the transmit buffer queue pointer register. Each list entry consists of two words, the first being the byte address of the transmit buffer and the second containing the transmit control and status. Frames can be transmitted with or without automatic CRC generation. If CRC is automatically generated, pad is also automatically generated to take frames to a
minimum length of 64 bytes. Table 45-2 on page 1020
defines an entry in the transmit buffer descriptor list. To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits 31 to 0 in the first word of each list entry. The second transmit buffer descriptor is initialized with control information that indicates the length of the buffer, whether or not it is to be transmitted with CRC and whether the buffer is the last buffer in the frame.
After transmission, the control bits are written back to the second word of the first buffer along with the “used” bit and other status information. Bit 31 is the “used” bit which must be zero when the control word is read if transmission is to happen. It is written to one when a frame has been transmitted. Bits 27, 28 and 29 indicate various transmit error conditions. Bit 30 is the “wrap” bit which can be set for any buffer within a frame. If no wrap bit is encountered after 1024 descriptors, the queue pointer rolls over to the start in a similar fashion to the receive queue.
The transmit buffer queue pointer register must not be written while transmit is active. If a new value is written to the transmit buffer queue pointer register, the queue pointer resets itself to point to the beginning of the new queue. If transmit is disabled by writing to bit 3 of the network control, the transmit buffer queue pointer register resets to point to the beginning of the transmit queue. Note that disabling receive does not have the same effect on the receive queue pointer.
Once the transmit queue is initialized, transmit is activated by writing to bit 9, the Transmit Start bit of the network control register. Transmit is halted when a buffer descriptor with its used bit set is read, or if a transmit error occurs, or by writing to the transmit halt bit of the network control register. (Transmission is suspended if a pause frame is received while the pause enable bit is set in the network configuration register.) Rewriting the start bit while transmission is active is allowed.
Transmission control is implemented with a Tx_go variable which is readable in the transmit status register at bit location 3.
The Tx_go variable is reset when:
Transmit is disabled
A buffer descriptor with its ownership bit set is read
A new value is written to the transmit buffer queue pointer register
Bit 10, tx_halt, of the network control register is written
There is a transmit error such as too many retries or a transmit underrun.
To set tx_go, write to bit 9, tx_start, of the network control register. Transmit halt does not take effect until any ongoing transmit finishes. If a collision occurs during transmission of a multi-buffer frame, transmission automatically restarts from the first buffer of the frame. If a “used” bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error. Transmission stops, tx_er is asserted and the FCS is bad.
If transmission stops due to a transmit error, the transmit queue pointer resets to point to the beginning of the transmit queue. Software needs to re-initialize the transmit queue after a transmit error.
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If transmission stops due to a “used” bit being read at the start of the frame, the transmission queue pointer is not reset and transmit starts from the same transmit buffer descriptor when the transmit start bit is written
Table 45-2. Transmit Buffer Descriptor Entry
Bit
31:0
31
Function
Word 0
Byte Address of buffer
Word 1
Used. Needs to be zero for the EMAC to read data from the transmit buffer. The EMAC sets this to one for the first buffer of a frame once it has been successfully transmitted.
Software has to clear this bit before the buffer can be used again.
Note: This bit is only set for the first buffer in a frame unlike receive where all buffers have the Used bit set once used.
30
29
28
27
26:17
16
15
14:11
10:0
Wrap. Marks last descriptor in transmit buffer descriptor list.
Retry limit exceeded, transmit error detected
Transmit underrun, occurs either when hresp is not OK (bus error) or the transmit data could not be fetched in time or when buffers are exhausted in mid frame.
Buffers exhausted in mid frame
Reserved
No CRC. When set, no CRC is appended to the current frame. This bit only needs to be set for the last buffer of a frame.
Last buffer. When set, this bit indicates the last buffer in the current frame has been reached.
Reserved
Length of buffer
45.4.3 Transmit Block
This block transmits frames in accordance with the Ethernet IEEE 802.3 CSMA/CD protocol. Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO a word at a time. Data is transmitted least significant nibble first. If necessary, padding is added to increase the frame length to 60 bytes. CRC is calculated as a 32-bit polynomial. This is inverted and appended to the end of the frame, taking the frame length to a minimum of 64 bytes. If the No CRC bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor CRC are appended.
In full-duplex mode, frames are transmitted immediately. Back-to-back frames are transmitted at least 96 bit times apart to guarantee the interframe gap.
In half-duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to de-assert and then starts transmission after the interframe gap of 96 bit times. If the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retry transmission after the back off time has elapsed.
The back-off time is based on an XOR of the 10 least significant bits of the data coming from the transmit FIFO and a 10bit pseudo random number generator. The number of bits used depends on the number of collisions seen. After the first collision, 1 bit is used, after the second 2, and so on up to 10. Above 10, all 10 bits are used. An error is indicated and no further attempts are made if 16 attempts cause collisions.
If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as jam insertion and the tx_er signal is asserted. For a properly configured system, this should never happen.
If the back pressure bit is set in the network control register in half duplex mode, the transmit block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit-rate mode 64 1s, whenever it sees an incoming frame to force a collision. This provides a way of implementing flow control in half-duplex mode.
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45.4.4 Pause Frame Support
The start of an 802.3 pause frame is as follows:
Table 45-3. Start of an 802.3 Pause Frame
Destination
Address
0x0180C2000001
Source
Address
6 bytes
Type
(Mac Control Frame)
0x8808
Pause
Opcode
0x0001
Pause Time
2 bytes
The network configuration register contains a receive pause enable bit (13). If a valid pause frame is received, the pause time register is updated with the frame’s pause time, regardless of its current contents and regardless of the state of the configuration register bit 13. An interrupt (12) is triggered when a pause frame is received, assuming it is enabled in the interrupt mask register. If bit 13 is set in the network configuration register and the value of the pause time register is nonzero, no new frame is transmitted until the pause time register has decremented to zero.
The loading of a new pause time, and hence the pausing of transmission, only occurs when the EMAC is configured for full-duplex operation. If the EMAC is configured for half-duplex, there is no transmission pause, but the pause frame received interrupt is still triggered.
A valid pause frame is defined as having a destination address that matches either the address stored in specific address register 1 or matches 0x0180C2000001 and has the MAC control frame type ID of 0x8808 and the pause opcode of
0x0001. Pause frames that have FCS or other errors are treated as invalid and are discarded. Valid pause frames received increment the Pause Frame Received statistic register.
The pause time register decrements every 512 bit times (i.e., 128 rx_clks in nibble mode) once transmission has stopped. For test purposes, the register decrements every rx_clk cycle once transmission has stopped if bit 12 (retry test) is set in the network configuration register. If the pause enable bit (13) is not set in the network configuration register, then the decrementing occurs regardless of whether transmission has stopped or not.
An interrupt (13) is asserted whenever the pause time register decrements to zero (assuming it is enabled in the interrupt mask register).
45.4.5 Receive Block
The receive block checks for valid preamble, FCS, alignment and length, presents received frames to the DMA block and stores the frames destination address for use by the address checking block. If, during frame reception, the frame is found to be too long or rx_er is asserted, a bad frame indication is sent to the DMA block. The DMA block then ceases sending data to memory. At the end of frame reception, the receive block indicates to the DMA block whether the frame is good or bad. The DMA block recovers the current receive buffer if the frame was bad. The receive block signals the register block to increment the alignment error, the CRC (FCS) error, the short frame, long frame, jabber error, the receive symbol error statistics and the length field mismatch statistics.
The enable bit for jumbo frames in the network configuration register allows the EMAC to receive jumbo frames of up to
10240 bytes in size. This operation does not form part of the IEEE802.3 specification and is disabled by default. When jumbo frames are enabled, frames received with a frame size greater than 10240 bytes are discarded.
45.4.6 Address Checking Block
The address checking (or filter) block indicates to the DMA block which receive frames should be copied to memory.
Whether a frame is copied depends on what is enabled in the network configuration register, the state of the external match pin, the contents of the specific address and hash registers and the frame’s destination address. In this implementation of the EMAC, the frame’s source address is not checked. Provided that bit 18 of the Network
Configuration register is not set, a frame is not copied to memory if the EMAC is transmitting in half duplex mode at the time a destination address is received. If bit 18 of the Network Configuration register is set, frames can be received while transmitting in half-duplex mode.
Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet frame make up the destination address. The first bit of the destination address, the LSB of the first byte of the frame, is the
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group/individual bit: this is One for multicast addresses and Zero for unicast. The All Ones address is the broadcast address, and a special case of multicast.
The EMAC supports recognition of four specific addresses. Each specific address requires two registers, specific address register bottom and specific address register top. Specific address register bottom stores the first four bytes of the destination address and specific address register top contains the last two bytes. The addresses stored can be specific, group, local or universal.
The destination address of received frames is compared against the data stored in the specific address registers once they have been activated. The addresses are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written. If a receive frame address matches an active address, the frame is copied to memory.
The following example illustrates the use of the address match registers for a MAC address of 21:43:65:87:A9:CB.
Preamble 55
SFD D5
DA (Octet0 - LSB) 21
DA(Octet 1) 43
DA(Octet 2) 65
DA(Octet 3) 87
DA(Octet 4) A9
DA (Octet5 - MSB) CB
SA (LSB) 00
SA 00
SA 00
SA 00
SA 00
SA (MSB) 43
SA (LSB) 21
The sequence above shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom as shown. For a successful match to specific address 1, the following address matching registers must be set up:
Base address + 0x98 0x87654321 (Bottom)
Base address + 0x9C 0x0000CBA9 (Top)
And for a successful match to the Type ID register, the following should be set up:
Base address + 0xB8 0x00004321
45.4.7 Broadcast Address
The broadcast address of 0xFFFFFFFFFFFF is recognized if the ‘no broadcast’ bit in the network configuration register is zero.
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45.4.8 Hash Addressing
The hash address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in hash register bottom and the most significant bits in hash register top.
The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. The destination address is reduced to a 6-bit index into the 64-bit hash register using the following hash function. The hash function is an exclusive or of every sixth bit of the destination address.
hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] da[0] represents the least significant bit of the first byte received, that is, the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received.
If the hash index points to a bit that is set in the hash register, then the frame is matched according to whether the frame is multicast or unicast.
A multicast match is signalled if the multicast hash enable bit is set. da[0] is 1 and the hash index points to a bit set in the hash register.
A unicast match is signalled if the unicast hash enable bit is set. da[0] is 0 and the hash index points to a bit set in the hash register.
To receive all multicast frames, the hash register should be set with all ones and the multicast hash enable bit should be set in the network configuration register.
45.4.9 Copy All Frames (or Promiscuous Mode)
If the copy all frames bit is set in the network configuration register, then all non-errored frames are copied to memory.
For example, frames that are too long, too short, or have FCS errors or rx_er asserted during reception are discarded and all others are received. Frames with FCS errors are copied to memory if bit 19 in the network configuration register is set.
45.4.10 Type ID Checking
The contents of the type_id register are compared against the length/type ID of received frames (i.e., bytes 13 and 14).
Bit 22 in the receive buffer descriptor status is set if there is a match. The reset state of this register is zero which is unlikely to match the length/type ID of any valid Ethernet frame.
Note: A type ID match does not affect whether a frame is copied to memory.
45.4.11 VLAN Support
An Ethernet encoded 802.1Q VLAN tag looks like this:
Table 45-4. 802.1Q VLAN Tag
TPID (Tag Protocol Identifier) 16 bits
0x8100
TCI (Tag Control Information) 16 bits
First 3 bits priority, then CFI bit, last 12 bits VID
The VLAN tag is inserted at the 13 th byte of the frame, adding an extra four bytes to the frame. If the VID (VLAN identifier) is null (0x000), this indicates a priority-tagged frame. The MAC can support frame lengths up to 1536 bytes, 18 bytes more than the original Ethernet maximum frame length of 1518 bytes. This is achieved by setting bit 8 in the network configuration register.
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The following bits in the receive buffer descriptor status word give information about VLAN tagged frames:
Bit 21 set if receive frame is VLAN tagged (i.e. type id of 0x8100)
Bit 20 set if receive frame is priority tagged (i.e. type id of 0x8100 and null VID). (If bit 20 is set bit 21 is set also.)
Bit 19, 18 and 17 set to priority if bit 21 is set
Bit 16 set to CFI if bit 21 is set
45.4.12 PHY Maintenance
The register EMAC_MAN enables the EMAC to communicate with a PHY by means of the MDIO interface. It is used during auto-negotiation to ensure that the EMAC and the PHY are configured for the same speed and duplex configuration.
The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit two is set in the network status register (about 2000 MCK cycles later when bit ten is set to zero, and bit eleven is set to one in the network configuration register). An interrupt is generated as this bit is set.
During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each
MDC cycle. This causes transmission of a PHY management frame on MDIO.
Reading during the shift operation returns the current contents of the shift register. At the end of management operation, the bits have shifted back to their original locations. For a read operation, the data bits are updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bits[31:28] should be written as 0x0011. For a description of MDC generation, see the network configuration register in the
“Network Control Register” on page 1030
.
45.4.13 Physical Interface
Depending on products, the Ethernet MAC is capable of interfacing to RMII or MII Interface. The RMII bit in the
EMAC_USRIO register controls the interface that is selected. When this bit is set, the RMII interface is selected, else the
MII interface is selected.
The MII and RMII interfaces are capable of both 10 Mb/s and 100 Mb/s data rates as described in the IEEE 802.3u
standard. The signals used by the RMII interface are described in Table 45-5
.
Table 45-5. Pin Configuration
Pin Name
ETXCK_EREFCK
ERXDV
ERX0–ERX1
RMII
EREFCK: Reference Clock
ECRSDV: Carrier Sense/Data Valid
ERX0–ERX1: 2-bit Receive Data
ERXER
ETXEN
ETX0–ETX1
ERXER: Receive Error
ETXEN: Transmit Enable
ETX0–ETX1: 2-bit Transmit Data
The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII. It uses two bits for transmit
(ETX0 and ETX1) and two bits for receive (ERX0 and ERX1). There is a Transmit Enable (ETXEN), a Receive Error
(ERXER), a Carrier Sense (ECRS_DV), and a 50 MHz Reference Clock (ETXCK_EREFCK) for 100 Mb/s data rate.
45.4.13.1 RMII Transmit and Receive Operation
The RMII maps the signals in a more pin-efficient manner. The transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. The carrier sense and data valid signals are combined into the ECRSDV signal. This signal contains information on carrier sense, FIFO status, and validity of the data. Transmit error bit (ETXER) and collision detect (ECOL) are not used in RMII mode.
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45.5 Programming Interface
45.5.1 Initialization
45.5.1.1 Configuration
Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the network control register and network configuration register earlier in this document.
To change loop-back mode, the following sequence of operations must be followed:
1.
Write to network control register to disable transmit and receive circuits.
2.
Write to network control register to change loop-back mode.
3.
Write to network control register to re-enable transmit or receive circuits.
Note: These writes to network control register cannot be combined in any way.
45.5.1.2 Receive Buffer List
Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed in another data structure that also resides in main memory. This data structure (receive buffer queue) is a sequence of descriptor entries as defined in
“Receive Buffer Descriptor Entry” on page 1017 . It points to this data structure.
Figure 45-2. Receive Buffer List
Receive Buffer 0
Receive Buffer Queue Pointer
(MAC Register)
Receive Buffer 1
Receive Buffer N
Receive Buffer Descriptor List
(In memory)
(In memory)
To create the list of buffers:
1.
Allocate a number ( n ) of buffers of 128 bytes in system memory.
2.
Allocate an area 2 n words for the receive buffer descriptor entry in system memory and create n entries in this list.
Mark all entries in this list as owned by EMAC, i.e., bit 0 of word 0 set to 0.
3.
If less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit (bit 1 in word 0 set to 1).
4.
Write address of receive buffer descriptor entry to EMAC register receive_buffer queue pointer.
5.
The receive circuits can then be enabled by writing to the address recognition registers and then to the network control register.
45.5.1.3 Transmit Buffer List
Transmit data is read from areas of data (the buffers) in system memory These buffers are listed in another data structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of descriptor
entries (as defined in Table 45-2 on page 1020
) that points to this data structure.
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To create this list of buffers:
1.
Allocate a number ( n ) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. Up to
128 buffers per frame are allowed.
2.
Allocate an area 2 n words for the transmit buffer descriptor entry in system memory and create N entries in this list. Mark all entries in this list as owned by EMAC, i.e. bit 31 of word 1 set to 0.
3.
If fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap bit — bit 30 in word 1 set to 1.
4.
Write address of transmit buffer descriptor entry to EMAC register transmit_buffer queue pointer.
5.
The transmit circuits can then be enabled by writing to the network control register.
45.5.1.4 Address Matching
The EMAC register-pair hash address and the four specific address register-pairs must be written with the required values. Each register-pair comprises a bottom register and top register, with the bottom register being written first. The address matching is disabled for a particular register-pair after the bottom-register has been written and re-enabled when the top register is written.
See “Address Checking Block” on page 1021.
for details of address matching. Each registerpair may be written at any time, regardless of whether the receive circuits are enabled or disabled.
45.5.1.5 Interrupts
There are 14 interrupt conditions that are detected within the EMAC. These are ORed to make a single interrupt.
Depending on the overall system design, this may be passed through a further level of interrupt collection (interrupt controller). On receipt of the interrupt signal, the CPU enters the interrupt handler (Refer to the Interrupt Controller). To ascertain which interrupt has been generated, read the interrupt status register. Note that this register clears itself when read. At reset, all interrupts are disabled. To enable an interrupt, write to interrupt enable register with the pertinent interrupt bit set to 1. To disable an interrupt, write to interrupt disable register with the pertinent interrupt bit set to 1. To check whether an interrupt is enabled or disabled, read interrupt mask register: if the bit is set to 1, the interrupt is disabled.
45.5.1.6 Transmitting Frames
To set up a frame for transmission:
1.
Enable transmit in the network control register.
2.
Allocate an area of system memory for transmit data. This does not have to be contiguous, varying byte lengths can be used as long as they conclude on byte borders.
3.
Set-up the transmit buffer list.
4.
Set the network control register to enable transmission and enable interrupts.
5.
Write data for transmission into these buffers.
6.
Write the address to transmit buffer descriptor queue pointer.
7.
Write control and length to word one of the transmit buffer descriptor entry.
8.
Write to the transmit start bit in the network control register.
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45.5.1.7 Receiving Frames
When a frame is received and the receive circuits are enabled, the EMAC checks the address and, in the following cases, the frame is written to system memory:
If it matches one of the four specific address registers.
If it matches the hash address function.
If it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed.
If the EMAC is configured to copy all frames.
The register receive buffer queue pointer points to the next entry (see
) and the EMAC uses this as the address in system memory to write the frame to. Once the frame has been completely and successfully received and written to system memory, the EMAC then updates the receive buffer descriptor entry with the reason for the address match and marks the area as being owned by software. Once this is complete an interrupt receive complete is set. Software is then responsible for handling the data in the buffer and then releasing the buffer by writing the ownership bit back to 0.
If the EMAC is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is set. If there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer not available is set. If the frame is not successfully received, a statistic register is incremented and the frame is discarded without informing software.
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45.6 Ethernet MAC 10/100 (EMAC) User Interface
0x54
0x58
0x5C
0x60
0x64
0x68
0x6C
0x70
0x34
0x38
0x3C
0x40
0x44
0x48
0x4C
0x50
0x74
0x78
0x7C
0x80
0x84
0x88
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
Table 45-6. Register Mapping
Offset Register Name
0x00 Network Control Register EMAC_NCR
0x04
0x08
0x0C
0x10
Network Configuration Register
Network Status Register
Reserved
Reserved
EMAC_NCFGR
EMAC_NSR
Transmit Status Register
Receive Buffer Queue Pointer Register
Transmit Buffer Queue Pointer Register
Receive Status Register
Interrupt Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
EMAC_TSR
EMAC_RBQP
EMAC_TBQP
EMAC_RSR
EMAC_ISR
EMAC_IER
EMAC_IDR
EMAC_IMR
Phy Maintenance Register
Pause Time Register
Pause Frames Received Register
Frames Transmitted Ok Register
Single Collision Frames Register
Multiple Collision Frames Register
Frames Received Ok Register
Frame Check Sequence Errors Register
Alignment Errors Register
Deferred Transmission Frames Register
Late Collisions Register
Excessive Collisions Register
Transmit Underrun Errors Register
Carrier Sense Errors Register
Receive Resource Errors Register
Receive Overrun Errors Register
Receive Symbol Errors Register
Excessive Length Errors Register
Receive Jabbers Register
Undersize Frames Register
SQE Test Errors Register
Received Length Field Mismatch Register
EMAC_RSE
EMAC_ELE
EMAC_RJA
EMAC_USF
EMAC_STE
EMAC_RLE
EMAC_MAN
EMAC_PTR
EMAC_PFR
EMAC_FTO
EMAC_SCF
EMAC_MCF
EMAC_FRO
EMAC_FCSE
EMAC_ALE
EMAC_DTF
EMAC_LCOL
EMAC_ECOL
EMAC_TUND
EMAC_CSE
EMAC_RRE
EMAC_ROV
Access
Read-write
Read-write
Read-only
Reset
0
0x800
-
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Write-only
Write-only
Read-only
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
-
-
0x0000_3FFF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1028
Table 45-6. Register Mapping (Continued)
Offset
0x90
Register Name
Hash Register Bottom [31:0] Register EMAC_HRB
0x94
0x98
0x9C
0xA0
0xA4
0xA8
Hash Register Top [63:32]
Specific Address 3 Bottom
Register
Specific Address 1 Bottom Register
Specific Address 1 Top Register
Specific Address 2 Bottom Register
Specific Address 2 Top Register
Register
EMAC_HRT
EMAC_SA1B
EMAC_SA1T
EMAC_SA2B
EMAC_SA2T
EMAC_SA3B
0xAC
0xB0
0xB4
0xB8
0xC0
0xC8 - 0xFC
Specific Address 3 Top Register
Specific Address 4 Bottom Register
Specific Address 4 Top Register
Type ID Checking Register
User Input/Output Register
Reserved
EMAC_SA3T
EMAC_SA4B
EMAC_SA4T
EMAC_TID
EMAC_USRIO
–
Access
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
–
Reset
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1029
45.6.1 Network Control Register
Name:
Address:
Access:
EMAC_NCR
0xF802C000
Read-write
31
–
30
–
29
–
23
–
15
–
7
WESTAT
22
–
14
–
6
INCSTAT
21
–
13
–
5
CLRSTAT
28
–
20
–
12
–
4
MPE
27
–
19
–
11
–
3
TE
26
–
18
–
10
THALT
2
RE
25
–
17
–
9
TSTART
1
LLB
• LB: LoopBack
Asserts the loopback signal to the PHY.
• LLB: Loopback Local
Connects txd to rxd
, tx_en to rx_dv
, forces full duplex and drives rx_clk and tx_clk with MCK divided by 4. rx_clk and tx_clk may glitch as the EMAC is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back.
• RE: Receive Enable
When set, enables the EMAC to receive data. When reset, frame reception stops immediately and the receive FIFO is cleared.
The receive queue pointer register is unaffected.
• TE: Transmit Enable
When set, enables the Ethernet transmitter to send data. When reset transmission, stops immediately, the transmit FIFO and control registers are cleared and the transmit queue pointer register resets to point to the start of the transmit descriptor list.
• MPE: Management Port Enable
Set to one to enable the management port. When zero, forces MDIO to high impedance state and MDC low.
• CLRSTAT: Clear Statistics Registers
This bit is write only. Writing a one clears the statistics registers.
• INCSTAT: Increment Statistics Registers
This bit is write only. Writing a one increments all the statistics registers by one for test purposes.
• WESTAT: Write Enable For Statistics Registers
Setting this bit to one makes the statistics registers writable for functional test purposes.
• BP: Back Pressure
If set in half duplex mode, forces collisions on all received frames.
24
–
16
–
8
BP
0
LB
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1030
• TSTART: Start Transmission
Writing one to this bit starts transmission.
• THALT: Transmit Halt
Writing one to this bit halts transmission as soon as any ongoing frame transmission ends.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1031
45.6.2 Network Configuration Register
Name:
Address:
Access:
EMAC_NCFGR
0xF802C004
Read-write
31
–
30
–
29
–
23
–
15
22
–
14
7
UNI
RBOF
6
MTI
21
–
13
PAE
5
NBC
28
–
20
–
12
RTY
4
CAF
27
–
19
IRXFCS
11
CLK
26
–
18
EFRHD
10
3
JFRAME
2
–
25
–
17
DRFCS
9
–
1
FD
24
–
16
RLCE
8
BIG
0
SPD
• SPD: Speed
Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s. The value of this pin is reflected on the speed pin.
• FD: Full Duplex
If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin.
• CAF: Copy All Frames
When set to 1, all valid frames are received.
• JFRAME: Jumbo Frames
Set to one to enable jumbo frames of up to 10240 bytes to be accepted.
• NBC: No Broadcast
When set to 1, frames addressed to the broadcast address of all ones are not received.
• MTI: Multicast Hash Enable
When set, multicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register.
• UNI: Unicast Hash Enable
When set, unicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register.
• BIG: Receive 1536 bytes Frames
Setting this bit means the EMAC receives frames up to 1536 bytes in length. Normally, the EMAC would reject any frame above
1518 bytes.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1032
• CLK: MDC Clock Divider
Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with 802.3, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations).
Value
0
1
2
3
Name
MCK_8
MCK_16
MCK_32
MCK_64
Description
MCK divided by 8 (MCK up to 20 MHz).
MCK divided by 16 (MCK up to 40 MHz).
MCK divided by 32 (MCK up to 80 MHz).
MCK divided by 64 (MCK up to 160 MHz).
• RTY: Retry Test
Must be set to zero for normal operation. If set to one, the back off between collisions is always one slot time. Setting this bit to one helps testing the too many retries condition. Also used in the pause frame tests to reduce the pause counters decrement time from 512 bit times, to every rx_clk cycle.
• PAE: Pause Enable
When set, transmission pauses when a valid pause frame is received.
• RBOF: Receive Buffer Offset
Indicates the number of bytes by which the received data is offset from the start of the first receive buffer.
Value
0
1
2
3
Name
OFFSET_0
OFFSET_1
OFFSET_2
OFFSET_3
Description
No offset from start of receive buffer.
One-byte offset from start of receive buffer.
Two-byte offset from start of receive buffer.
Three-byte offset from start of receive buffer.
• RLCE: Receive Length field Checking Enable
When set, frames with measured lengths shorter than their length fields are discarded. Frames containing a type ID in bytes 13 and 14 — length/type ID = 0600 — are not counted as length errors.
• DRFCS: Discard Receive FCS
When set, the FCS field of received frames is not copied to memory.
• EFRHD
Enable Frames to be received in half-duplex mode while transmitting.
• IRXFCS: Ignore RX FCS
When set, frames with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit must be set to 0.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1033
45.6.3 Network Status Register
Name:
Address:
Access:
EMAC_NSR
0xF802C008
Read-only
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
IDLE
25
–
17
–
9
–
1
MDIO
• MDIO
Returns status of the mdio_in pin. Use the PHY maintenance register for reading managed frames rather than this bit.
• IDLE
0 = The PHY logic is running.
1 = The PHY management logic is idle (i.e., has completed).
24
–
16
–
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1034
45.6.4 Transmit Status Register
Name:
Address:
Access:
EMAC_TSR
0xF802C014
Read-write
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
UND
21
–
13
–
5
COMP
28
–
20
–
12
–
4
BEX
27
–
19
–
11
–
3
TGO
26
–
18
–
10
–
2
RLES
25
–
17
–
9
–
1
COL
This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
• UBR: Used Bit Read
Set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit.
• COL: Collision Occurred
Set by the assertion of collision. Cleared by writing a one to this bit.
• RLES: Retry Limit exceeded
Cleared by writing a one to this bit.
• TGO: Transmit Go
If high transmit is active.
• BEX: Buffers exhausted mid frame
If the buffers run out during transmission of a frame, then transmission stops, FCS shall be bad and tx_er asserted. Cleared by writing a one to this bit.
• COMP: Transmit Complete
Set when a frame has been transmitted. Cleared by writing a one to this bit.
• UND: Transmit Underrun
Set when transmit DMA was not able to read data from memory, either because the bus was not granted in time, because a not
OK hresp(bus error) was returned or because a used bit was read midway through frame transmission. If this occurs, the transmitter forces bad
CRC. Cleared by writing a one to this bit.
24
–
16
–
8
–
0
UBR
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1035
45.6.5 Receive Buffer Queue Pointer Register
Name:
Address:
Access:
EMAC_RBQP
0xF802C018
Read-write
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
7 6 5
ADDR
4 3 2 1
–
0
–
This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list. The lower order bits increment as buffers are used up and wrap to their original values after either 1024 buffers or when the wrap bit of the entry is set.
Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used.
Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits.
Receive buffer writes also comprise bursts of two words and, as with transmit buffer reads, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1K boundary, in violation of section 3.6 of the AMBA specification.
• ADDR: Receive Buffer Queue Pointer Address
Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1036
45.6.6 Transmit Buffer Queue Pointer Register
Name:
Address:
Access:
EMAC_TBQP
0xF802C01C
Read-write
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
7 6 5
ADDR
4 3 2 1
–
0
–
This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list. The lower order bits increment as buffers are used up and wrap to their original values after either 1024 buffers or when the wrap bit of the entry is set. This register can only be written when bit 3 in the transmit status register is low.
As transmit buffer reads consist of bursts of two words, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1K boundary, in violation of section 3.6 of the AMBA specification.
• ADDR: Transmit Buffer Queue Pointer Address
Written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmitted or about to be transmitted.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1037
45.6.7 Receive Status Register
Name:
Address:
Access:
EMAC_RSR
0xF802C020
Read-write
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
OVR
25
–
17
–
9
–
1
REC
24
–
16
–
8
–
0
BNA
This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them.
It is not possible to set a bit to 1 by writing to the register.
• BNA: Buffer Not Available
An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared.
Cleared by writing a one to this bit.
• REC: Frame Received
One or more frames have been received and placed in memory. Cleared by writing a one to this bit.
• OVR: Receive Overrun
The DMA block was unable to store the receive frame to memory, either because the bus was not granted in time or because a not OK hresp(bus error) was returned. The buffer is recovered if this happens.
Cleared by writing a one to this bit.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1038
45.6.8 Interrupt Status Register
Name:
Address:
Access:
EMAC_ISR
0xF802C024
Read-write
31
–
30
–
29
–
23
–
15
–
7
TCOMP
22
–
14
–
6
TXERR
21
–
13
PTZ
5
RLEX
28
–
20
–
12
PFRE
4
TUND
27
–
19
–
11
HRESP
3
TXUBR
26
–
18
–
10
ROVR
2
RXUBR
25
–
17
–
9
–
1
RCOMP
24
–
16
–
8
–
0
MFD
• MFD: Management Frame Done
The PHY maintenance register has completed its operation. Cleared on read.
• RCOMP: Receive Complete
A frame has been stored in memory. Cleared on read.
• RXUBR: Receive Used Bit Read
Set when a receive buffer descriptor is read with its used bit set. Cleared on read.
• TXUBR: Transmit Used Bit Read
Set when a transmit buffer descriptor is read with its used bit set. Cleared on read.
• TUND: Ethernet Transmit Buffer Underrun
The transmit DMA did not fetch frame data in time for it to be transmitted or hresp returned not OK. Also set if a used bit is read mid-frame or when a new transmit queue pointer is written. Cleared on read.
• RLEX: Retry Limit Exceeded
Cleared on read.
• TXERR: Transmit Error
Transmit buffers exhausted in mid-frame - transmit error. Cleared on read.
• TCOMP: Transmit Complete
Set when a frame has been transmitted. Cleared on read.
• ROVR: Receive Overrun
Set when the receive overrun status bit gets set. Cleared on read.
• HRESP: HRESP not OK
Set when the DMA block sees a bus error
. Cleared on read.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1039
• PFRE: Pause Frame Received
Indicates a valid pause has been received. Cleared on a read.
• PTZ: Pause Time Zero
Set when the pause time register, 0x38 decrements to zero. Cleared on a read.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1040
45.6.9 Interrupt Enable Register
Name:
Address:
Access:
EMAC_IER
0xF802C028
Write-only
31
–
30
–
29
–
23
–
15
–
7
TCOMP
22
–
14
–
6
TXERR
21
–
13
PTZ
5
RLE
• MFD: Management Frame sent
Enable management done interrupt.
• RCOMP: Receive Complete
Enable receive complete interrupt.
• RXUBR: Receive Used Bit Read
Enable receive used bit read interrupt.
• TXUBR: Transmit Used Bit Read
Enable transmit used bit read interrupt.
• TUND: Ethernet Transmit Buffer Underrun
Enable transmit underrun interrupt.
• RLE: Retry Limit Exceeded
Enable retry limit exceeded interrupt.
• TXERR
Enable transmit buffers exhausted in mid-frame interrupt.
• TCOMP: Transmit Complete
Enable transmit complete interrupt.
• ROVR: Receive Overrun
Enable receive overrun interrupt.
• HRESP: HRESP not OK
Enable HRESP not OK interrupt.
• PFR: Pause Frame Received
Enable pause frame received interrupt.
28
–
20
–
12
PFR
4
TUND
27
–
19
–
11
HRESP
3
TXUBR
26
–
18
–
10
ROVR
2
RXUBR
25
–
17
–
9
–
1
RCOMP
24
–
16
–
8
–
0
MFD
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1041
• PTZ: Pause Time Zero
Enable pause time zero interrupt.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1042
45.6.10 Interrupt Disable Register
Name:
Address:
Access:
EMAC_IDR
0xF802C02C
Write-only
31
–
30
–
29
–
23
–
15
–
7
TCOMP
22
–
14
–
6
TXERR
21
–
13
PTZ
5
RLE
• MFD: Management Frame sent
Disable management done interrupt.
• RCOMP: Receive Complete
Disable receive complete interrupt.
• RXUBR: Receive Used Bit Read
Disable receive used bit read interrupt.
• TXUBR: Transmit Used Bit Read
Disable transmit used bit read interrupt.
• TUND: Ethernet Transmit Buffer Underrun
Disable transmit underrun interrupt.
• RLE: Retry Limit Exceeded
Disable retry limit exceeded interrupt.
• TXERR
Disable transmit buffers exhausted in mid-frame interrupt.
• TCOMP: Transmit Complete
Disable transmit complete interrupt.
• ROVR: Receive Overrun
Disable receive overrun interrupt.
• HRESP: HRESP not OK
Disable HRESP not OK interrupt.
• PFR: Pause Frame Received
Disable pause frame received interrupt.
28
–
20
–
12
PFR
4
TUND
27
–
19
–
11
HRESP
3
TXUBR
26
–
18
–
10
ROVR
2
RXUBR
25
–
17
–
9
–
1
RCOMP
24
–
16
–
8
–
0
MFD
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1043
• PTZ: Pause Time Zero
Disable pause time zero interrupt.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1044
45.6.11 Interrupt Mask Register
Name:
Address:
Access:
EMAC_IMR
0xF802C030
Read-only
31
–
30
–
23
–
15
–
22
–
14
–
29
–
21
–
13
PTZ
7
TCOMP
6
TXERR
5
RLE
• MFD: Management Frame sent
Management done interrupt masked.
• RCOMP: Receive Complete
Receive complete interrupt masked.
• RXUBR: Receive Used Bit Read
Receive used bit read interrupt masked.
• TXUBR: Transmit Used Bit Read
Transmit used bit read interrupt masked.
• TUND: Ethernet Transmit Buffer Underrun
Transmit underrun interrupt masked.
• RLE: Retry Limit Exceeded
Retry limit exceeded interrupt masked.
• TXERR
Transmit buffers exhausted in mid-frame interrupt masked.
• TCOMP: Transmit Complete
Transmit complete interrupt masked.
• ROVR: Receive Overrun
Receive overrun interrupt masked.
• HRESP: HRESP not OK
HRESP not OK interrupt masked.
• PFR: Pause Frame Received
Pause frame received interrupt masked.
28
–
20
–
12
PFR
4
TUND
27
–
19
–
11
HRESP
3
TXUBR
26
–
18
–
10
ROVR
2
RXUBR
25
–
17
–
9
–
1
RCOMP
24
–
16
–
8
–
0
MFD
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1045
• PTZ: Pause Time Zero
Pause time zero interrupt masked.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1046
45.6.12 PHY Maintenance Register
Name:
Address:
Access:
EMAC_MAN
0xF802C034
Read-write
31 30 29
SOF
23
PHYA
15
7
22
14
6
21
13
5
RW
28 27
20
REGA
12
DATA
4
DATA
19
11
3
• DATA
For a write operation this is written with the data to be written to the PHY.
After a read operation this contains the data read from the PHY.
• CODE:
Must be written to 10. Reads as written.
• REGA: Register Address
Specifies the register in the PHY to access.
• PHYA: PHY Address
• RW: Read-write
10 is read; 01 is write. Any other value is an invalid PHY management frame
• SOF: Start of frame
Must be written 01 for a valid frame.
26
18
10
PHYA
25 24
17
CODE
9
16
8
2 1 0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1047
45.6.13 Pause Time Register
Name:
Address:
Access:
EMAC_PTR
0xF802C038
Read-write
31
–
30
–
23
–
15
7
22
–
14
6
29
–
21
–
13
5
28
–
20
–
12
PTIME
27
–
19
–
11
4 3
PTIME
26
–
18
–
10
2
• PTIME: Pause Time
Stores the current value of the pause time register which is decremented every 512 bit times.
25
–
17
–
9
1
24
–
16
–
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1048
45.6.14 Hash Register Bottom
Name:
Address:
Access:
EMAC_HRB
0xF802C090
Read-write
31 30 29 28 27
ADDR
23 22 21 20 19
ADDR
15 14 13 12 11
ADDR
7 6 5 4 3
ADDR
• ADDR:
Bits 31:0 of the hash address register. See “Hash Addressing” on page 1023 .
10
2
26
18
9
1
25
17
8
0
24
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1049
45.6.15 Hash Register Top
Name:
Address:
Access:
EMAC_HRT
0xF802C094
Read-write
31 30 29 28 27
ADDR
23 22 21 20 19
ADDR
15 14 13 12 11
ADDR
7 6 5 4 3
ADDR
• ADDR:
Bits 63:32 of the hash address register. See
“Hash Addressing” on page 1023 .
10
2
26
18
9
1
25
17
8
0
24
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1050
45.6.16 Specific Address 1 Bottom Register
Name:
Address:
Access:
EMAC_SA1B
0xF802C098
Read-write
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
7 6 5 4 3 2 1 0
ADDR
• ADDR
Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1051
45.6.17 Specific Address 1 Top Register
Name:
Address:
Access:
EMAC_SA1T
0xF802C09C
Read-write
31
–
30
–
29
–
23
–
15
22
–
14
21
–
13
28
–
20
–
12
ADDR
7 6 5 4
ADDR
• ADDR
The most significant bits of the destination address, that is bits 47 to 32.
3
27
–
19
–
11
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
–
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1052
45.6.18 Specific Address 2 Bottom Register
Name:
Address:
Access:
EMAC_SA2B
0xF802C0A0
Read-write
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
7 6 5 4 3 2 1 0
ADDR
• ADDR
Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1053
45.6.19 Specific Address 2 Top Register
Name:
Address:
Access:
EMAC_SA2T
0xF802C0A4
Read-write
31
–
30
–
29
–
23
–
15
22
–
14
21
–
13
28
–
20
–
12
ADDR
7 6 5 4
ADDR
• ADDR
The most significant bits of the destination address, that is bits 47 to 32.
3
27
–
19
–
11
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
–
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1054
45.6.20 Specific Address 3 Bottom Register
Name:
Address:
Access:
EMAC_SA3B
0xF802C0A8
Read-write
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
7 6 5 4 3 2 1 0
ADDR
• ADDR
Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1055
45.6.21 Specific Address 3 Top Register
Name:
Address:
Access:
EMAC_SA3T
0xF802C0AC
Read-write
31
–
30
–
29
–
23
–
15
22
–
14
21
–
13
28
–
20
–
12
ADDR
7 6 5 4
ADDR
• ADDR
The most significant bits of the destination address, that is bits 47 to 32.
3
27
–
19
–
11
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
–
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1056
45.6.22 Specific Address 4 Bottom Register
Name:
Address:
Access:
EMAC_SA4B
0xF802C0B0
Read-write
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
7 6 5 4 3 2 1 0
ADDR
• ADDR
Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1057
45.6.23 Specific Address 4 Top Register
Name:
Address:
Access:
EMAC_SA4T
0xF802C0B4
Read-write
31
–
30
–
29
–
23
–
15
22
–
14
21
–
13
28
–
20
–
12
ADDR
7 6 5 4
ADDR
• ADDR
The most significant bits of the destination address, that is bits 47 to 32.
3
27
–
19
–
11
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
–
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1058
45.6.24 Type ID Checking Register
Name:
Address:
Access:
EMAC_TID
0xF802C0B8
Read-write
31
–
30
–
29
–
23
–
15
22
–
14
21
–
13
28
–
20
–
12
TID
7 6 5 4
TID
• TID: Type ID checking
For use in comparisons with received frames TypeID/Length field.
27
–
19
–
11
3
26
–
18
–
10
2
25
–
17
–
9
1
24
–
16
–
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1059
45.6.25 User Input/Output Register
Name:
Address:
Access:
EMAC_USRIO
0xF802C0C0
Read-write
31
–
30
–
29
–
23
–
15
–
7
–
22
–
14
–
6
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
• RMII: Reduced MII
When set, this bit enables the RMII operation mode.
• CLKEN: Clock Enable
When set, this bit enables the transceiver input clock.
Setting this bit to 0 reduces power consumption when the treasurer is not used.
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
CLKEN
24
–
16
–
8
–
0
RMII
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1060
45.6.26 EMAC Statistic Registers
These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register block contains the following registers.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1061
45.6.26.1 Pause Frames Received Register
Name:
Address:
Access:
EMAC_PFR
0xF802C03C
Read-write
31
–
30
–
29
–
23
–
22
–
21
–
15 14 13
28
–
20
–
12
27
–
19
–
11
26
–
18
–
10
25
–
17
–
9
24
–
16
–
8
FROK
7 6 5 4 3 2 1 0
FROK
• FROK: Pause Frames received OK
A 16-bit register counting the number of good pause frames received. A good frame has a length of 64 to 1518 (1536 if bit 8 set in network configuration register) and has no FCS, alignment or receive symbol errors.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1062
45.6.26.2 Frames Transmitted OK Register
Name:
Address:
Access:
EMAC_FTO
0xF802C040
Read-write
31
–
30
–
29
–
23 22 21
28
–
20
27
–
19
26
–
18
25
–
17
FTOK
15 14 13 12 11 10 9
FTOK
7 6 5 4 3 2 1
FTOK
• FTOK: Frames Transmitted OK
A 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries.
24
–
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1063
45.6.26.3 Single Collision Frames Register
Name:
Address:
Access:
EMAC_SCF
0xF802C044
Read-write
31
–
30
–
29
–
23
–
22
–
21
–
15 14 13
28
–
20
–
12
27
–
19
–
11
26
–
18
–
10
25
–
17
–
9
SCF
7 6 5 4 3 2 1 0
SCF
• SCF: Single Collision Frames
A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun.
24
–
16
–
8
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1064
45.6.26.4 Multicollision Frames Register
Name:
Address:
Access:
EMAC_MCF
0xF802C048
Read-write
31
–
30
–
29
–
23
–
22
–
21
–
15 14 13
28
–
20
–
12
27
–
19
–
11
26
–
18
–
10
25
–
17
–
9
24
–
16
–
8
MCF
7 6 5 4 3 2 1 0
MCF
• MCF: Multicollision Frames
A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e., no underrun and not too many retries.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1065
45.6.26.5 Frames Received OK Register
Name:
Address:
Access:
EMAC_FRO
0xF802C04C
Read-write
31
–
30
–
29
–
23 22 21
28
–
20
27
–
19
26
–
18
25
–
17
24
–
16
FROK
15 14 13 12 11 10 9 8
FROK
7 6 5 4 3 2 1 0
FROK
• FROK: Frames Received OK
A 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory. A good frame is of length 64 to 1518 bytes (1536 if bit 8 set in network configuration register) and has no FCS, alignment or receive symbol errors.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1066
45.6.26.6 Frames Check Sequence Errors Register
Name:
Address:
Access:
EMAC_FCSE
0xF802C050
Read-write
31
–
30
–
29
–
28
–
23
–
22
–
21
–
20
–
15
–
7
14
–
6
13
–
5
12
–
4
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
FCSE
• FCSE: Frame Check Sequence Errors
An 8-bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1067
45.6.26.7 Alignment Errors Register
Name:
Address:
Access:
EMAC_ALE
0xF802C054
Read-write
31
–
30
–
29
–
23
–
22
–
21
–
15
–
7
14
–
6
13
–
5
28
–
20
–
12
–
4
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
ALE
• ALE: Alignment Errors
An 8-bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register).
This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1068
45.6.26.8 Deferred Transmission Frames Register
Name:
Address:
Access:
EMAC_DTF
0xF802C058
Read-write
31
–
30
–
29
–
28
–
23
–
22
–
21
–
20
–
15 14 13 12
27
–
19
–
11
26
–
18
–
10
25
–
17
–
9
24
–
16
–
8
DTF
7 6 5 4 3 2 1 0
DTF
• DTF: Deferred Transmission Frames
A 16-bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit underrun.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1069
45.6.26.9 Late Collisions Register
Name:
Address:
Access:
EMAC_LCOL
0xF802C05C
Read-write
31
–
30
–
29
–
23
–
22
–
21
–
15
–
7
14
–
6
13
–
5
28
–
20
–
12
–
4
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
LCOL
• LCOL: Late Collisions
An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1070
45.6.26.10 Excessive Collisions Register
Name:
Address:
Access:
EMAC_ECOL
0xF802C060
Read-write
31
–
30
–
29
–
23
–
15
–
7
22
–
14
–
6
21
–
13
–
5
28
–
20
–
12
–
4
EXCOL
11
–
3
27
–
19
–
26
–
18
–
10
–
2
25
–
17
–
9
–
1
• EXCOL: Excessive Collisions
An 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions.
24
–
16
–
8
–
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1071
45.6.26.11 Transmit Underrun Errors Register
Name:
Address:
Access:
EMAC_TUND
0xF802C064
Read-write
31
–
30
–
29
–
23
–
22
–
21
–
15
–
7
14
–
6
13
–
5
28
–
20
–
12
–
4
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
TUND
• TUND: Transmit Underruns
An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1072
45.6.26.12 Carrier Sense Errors Register
Name:
Address:
Access:
EMAC_CSE
0xF802C068
Read-write
31
–
30
–
29
–
23
–
22
–
21
–
15
–
7
14
–
6
13
–
5
28
–
20
–
12
–
4
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
CSE
• CSE: Carrier Sense Errors
An 8-bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no underrun). Only incremented in halfduplex mode. The only effect of a carrier sense error is to increment this register. The behavior of the other statistics registers is unaffected by the detection of a carrier sense error.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1073
45.6.26.13 Receive Resource Errors Register
Name:
Address:
Access:
EMAC_RRE
0xF802C06C
Read-write
31
–
30
–
29
–
23
–
22
–
21
–
15 14 13
28
–
20
–
12
27
–
19
–
11
26
–
18
–
10
25
–
17
–
9
RRE
7 6 5 4 3 2 1 0
RRE
• RRE: Receive Resource Errors
A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available.
24
–
16
–
8
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1074
45.6.26.14 Receive Overrun Errors Register
Name:
Address:
Access:
EMAC_ROV
0xF802C070
Read-write
31
–
30
–
29
–
23
–
15
–
7
22
–
14
–
6
21
–
13
–
5
28
–
20
–
12
–
4
ROVR
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
• ROVR: Receive Overrun
An 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1075
45.6.26.15 Receive Symbol Errors Register
Name:
Address:
Access:
EMAC_RSE
0xF802C074
Read-write
31
–
30
–
29
–
23
–
22
–
21
–
15
–
7
14
–
6
13
–
5
28
–
20
–
12
–
4
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
RSE
• RSE: Receive Symbol Errors
An 8-bit register counting the number of frames that had rx_er asserted during reception. Receive symbol errors are also counted as an FCS or alignment error if the frame is between 64 and 1518 bytes in length (1536 if bit 8 is set in the network configuration register). If the frame is larger, it is recorded as a jabber error.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1076
45.6.26.16 Excessive Length Errors Register
Name:
Address:
Access:
EMAC_ELE
0xF802C078
Read-write
31
–
30
–
29
–
23
–
22
–
21
–
15
–
7
14
–
6
13
–
5
28
–
20
–
12
–
4
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
EXL
• EXL: Excessive Length Errors
An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length but do not have either a CRC error, an alignment error nor a receive symbol error.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1077
45.6.26.17 Receive Jabbers Register
Name:
Address:
Access:
EMAC_RJA
0xF802C07C
Read-write
31
–
30
–
29
–
23
–
22
–
21
–
15
–
7
14
–
6
13
–
5
28
–
20
–
12
–
4
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
RJB
• RJB: Receive Jabbers
An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1078
45.6.26.18 Undersize Frames Register
Name:
Address:
Access:
EMAC_USF
0xF802C080
Read-write
31
–
30
–
29
–
23
–
22
–
21
–
15
–
7
14
–
6
13
–
5
28
–
20
–
12
–
4
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
USF
• USF: Undersize frames
An 8-bit register counting the number of frames received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1079
45.6.26.19 SQE Test Errors Register
Name:
Address:
Access:
EMAC_STE
0xF802C084
Read-write
31
–
30
–
29
–
23
–
22
–
21
–
15
–
7
14
–
6
13
–
5
28
–
20
–
12
–
4
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
SQER
• SQER: SQE test errors
An 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode.
SAM9X35 [DATASHEET]
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45.6.26.20 Received Length Field Mismatch Register
Name:
Address:
Access:
EMAC_RLE
0xF802C088
Read-write
31
–
30
–
29
–
28
–
23
–
22
–
21
–
20
–
15
–
7
14
–
6
13
–
5
12
–
4
27
–
19
–
11
–
3
26
–
18
–
10
–
2
25
–
17
–
9
–
1
24
–
16
–
8
–
0
RLFM
• RLFM: Receive Length Field Mismatch
An 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field. Checking is enabled through bit 16 of the network configuration register. Frames containing a type ID in bytes 13 and 14
(i.e., length/type ID = 0x0600) are not counted as length field errors, neither are excessive length frames.
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46.
LCD Controller (LCDC)
46.1 Description
The LCD controller consists of logic for transferring LCD image data from an external display buffer to an LCD module.
The LCD has one display input buffer per overlay that fetches pixels through the AHB master interface and a lookup table to allow palletized display configurations. The LCD controller is programmable on a per overlay basis, and supports different LCD resolution, window size, image format and pixel depth.
The LCD is connected to the ARM Advanced High Performance Bus (AHB) as a master for reading pixel data. It also integrates an APB interface to configure its registers.
46.2 Embedded Characteristics
One AHB Master Interface
Supports Single Scan Active TFT Display
Supports 12-bit, 16-bit, 18-bit and 24-bit Output Mode through the Spatial Dithering Unit
Asynchronous Output Mode Supported
1, 2, 4, 8 bits per pixel (palletized)
12, 16, 18, 19, 24, 25 and 32 bits per pixel (non palletized)
Supports One Base Layer (background)
Supports Ovr1 Layer Window
Supports One High End Overlay (HEO) Window
Supports One Hardware Cursor, Free Ranging up to a size limit of 128x128 pixels
Little Endian Memory Organization
Programmable Timing Engine, with Integer Clock Divider
Programmable Polarity for Data, Line Synchro and Frame Synchro
Hardware Cursor Fixed Size on the following patterns: 32x32, 64x64 and 128x128
Display Size up to 800 x 600
Color Lookup Table with up to 256 entries and Predefined 8-bit Alpha
Programmable Negative and Positive Row Striding for all layers
Programmable Negative and Positive Pixel Striding for all Overlay1 and HEO layers
High End Overlay supports 4:2:0 Planar Mode and Semiplanar Mode
High End Overlay supports 4:2:2 Planar Mode and Packed Memory Mode
High End Overlay includes Chroma Upsampling unit and Programmable Scaler
Integrates Fully Programmable Color Space Conversion
Overlay1 and High End Overlay integrate Rotation Engine: 90, 180, 270
Blender Function Supports Arbitrary 8-bit Alpha value and Chroma Keying
DMA User interface uses Linked List Structure and Add-to-queue Structure
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46.3 Block Diagram
Figure 46-1. Block Diagram
3 2b it
APB Interf a ce
Config u r a tion
Regi s ter s
AHB
B us
3 2b
AHB it
M as ter
Interf a ce
DEAG
Unit
S Y S CTRL
Unit
HCC
L a yer
OVR1
L a yer
HEO
L a yer
CLUT
ROT
CLUT
ROT
C S C
2D S C
CUE
CLUT
B as e
L a yer
CLUT
HEO: High End Overl a y
CUE: Chrom a Up sa mpling Engine
C S C: Color S p a ce Conver s ion
2D S C: Two Dimen s ion S c a ler
DEAG: DMA Engine Addre ss Gener a tion
HCC: H a rdw a re C u r s or Ch a nnel
GAB: Glo ba l Alph a Blender
LTE: LCD Timing Engine
ROT: H a rdw a re Rot a tion
GAB
Unit
LTE
Unit
LCD_DAT[2 3 :0]
LCD_V S YNC
LCD_H S YNC
LCD_PCLK
LCD_DEN
LCD_PWM
LCD_DI S P
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46.4 I/O Lines Description
Table 46-1. I/O Lines Description
Name
LCD_PWM
LCD_HSYNC
Description
Contrast control signal, using Pulse Width Modulation
Horizontal Synchronization Pulse
LCD_VSYNC
LCD_DAT[23:0]
LCD_DEN
LCD_DISP
LCD_PCLK
Vertical Synchronization Pulse
LCD 24-bit data bus
Data Enable
Display Enable signal
Pixel Clock
Type
Output
Output
Output
Output
Output
Output
Output
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46.5 Product Dependencies
46.5.1 I/O Lines
The pins used for interfacing the LCD Controller may be multiplexed with PIO lines. The programmer must first program the PIO Controller to assign the pins to their peripheral function. If I/O lines of the LCD Controller are not used by the application, they can be used for other purposes by the PIO Controller.
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
Table 46-2. I/O Lines
Instance
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Peripheral
A
A
A
A
A
A
A
PC23
PC29
PC24
PC28
PC30
PC26
PC27
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
I/O Line
PC0
PC1
PC2
PC3
PC4
PC5
PC6
LCDDAT15
LCDDAT16
LCDDAT17
LCDDAT18
LCDDAT19
LCDDAT20
LCDDAT21
LCDDAT22
LCDDAT23
LCDDEN
LCDDISP
LCDHSYNC
LCDPCK
LCDPWM
LCDVSYNC
Signal
LCDDAT0
LCDDAT1
LCDDAT2
LCDDAT3
LCDDAT4
LCDDAT5
LCDDAT6
LCDDAT7
LCDDAT8
LCDDAT9
LCDDAT10
LCDDAT11
LCDDAT12
LCDDAT13
LCDDAT14
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46.5.2 Power Management
The LCD Controller is not continuously clocked. The user must first enable the LCD Controller clock in the Power
Management Controller before using it (PMC_PCER).
46.5.3 Interrupt Sources
The LCD Controller interrupt line is connected to one of the internal sources of the Advanced Interrupt Controller. Using the LCD Controller interrupt requires prior programming of the AIC.
Table 46-3. Peripheral IDs
Instance
LCDC
ID
25
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46.6 Functional Description
The LCD module integrates the following digital blocks:
DMA Engine Address Generation (DEAG). This block performs data prefetch and requests access to the AHB interface.
Input FIFO, stores the stream of pixels.
Color Lookup Table (CLUT). These 256 RAM-based lookup table entries are selected when the color depth is set to 1, 2, 4 or 8 bpp.
Chroma Upsampling Engine (CUE). This block is selected when the input image sampling format is YUV (Y’CbCr)
4:2:0 and converts it to higher quality 4:4:4 image.
Color Space Conversion (CSC), changes the color space from YUV to RGB.
Two Dimension Scaler (2DSC), resizes the image.
Global Alpha Blender (GAB), performs programmable 256 level alpha blending.
Output FIFO, stores the pixel prior to display.
LCD Timing Engine, provides a fully programmable HSYNC-VSYNC interface.
The DMA controller reads the image through the AHB master interface. The LCD controller engine formats the display data, then the GAB performs alpha blending if required, and writes the final pixel into the output FIFO. The programmable timing engine drives a valid pixel onto the LCD_DAT[23:0] display bus.
46.6.1 Timing Engine Configuration
46.6.1.1 Pixel Clock Period Configuration
The pixel clock (PCLK) generated by the timing engine is the source clock (SCLK) divided by the field CLKDIV in the
LCDC_LCDCFG0 register. The source clock can be selected between the system clock and the 2x system clock with the field CLKSEL located in the LCDC_LCDCFG0 register. The Pixel Clock period formula is given below:
PCLK = --------------------------------
+ 2
The Pixel Clock polarity is also programmable.
46.6.1.2 Horizontal and Vertical Synchronization Configuration
The following fields are used to configure the timing engine:
HSPW field
VSPW field
VFPW field
VBPW field
HFPW field
HBPW field
PPL field
RPF field
The polarity of output signals is also programmable.
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46.6.1.3 Timing Engine Power Up Software Operation
The following sequence is used to enable the display:
1.
Configure LCD timing parameters, signal polarity and clock period.
2.
Enable the Pixel Clock by writing one to the CLKEN field of the LCDC_LCDEN register.
3.
Poll CLKSTS field of the LCDC_LCDSR register to check that the clock is running.
4.
Enable Horizontal and Vertical Synchronization by writing one to the SYNCEN field of the LCDC_LCDEN register.
5.
Poll LCDSTS field of the LCDC_LCDSR register to check that the synchronization is up.
6.
Enable the display power signal writing one to the DISPEN field of the LCDC_LCDEN register.
7.
Poll DISPSTS field of the LCDC_LCDSR register to check that the power signal is activated.
The GUARDTIME field of the LCDC_LCDCFG5 register is used to configure the number of frames before the assertion of the DISP signal.
46.6.1.4 Timing Engine Power Down Software Operation
The following sequence is used to disable the display:
1.
Disable the DISP signal writing DISPDIS field of the LCDC_LCDDIS register.
2.
Poll DISPSTS field of the LCDC_LCDSR register to verify that the DISP is no longer activated.
3.
Disable the hsync and vsync signals by writing one to SYNCDIS field of the LCDC_LCDDIS register.
4.
Poll LCDSTS field of the LCDC_LCDSR register to check that the synchronization is off.
5.
Disable the Pixel clock by writing one in the CLKDIS field of the LCDC_LCDDIS register.
46.6.2 DMA Software Operations
46.6.2.1 DMA Channel Descriptor (DSCR) Alignment and Structure
The DMA Channel Descriptor (DSCR) must be word aligned.
The DMA Channel Descriptor structure contains three fields:
DSCR.CHXADDR: Frame Buffer base address register
DSCR.CHXCTRL: Transfer Control register
DSCR.CHXNEXT: Next Descriptor Address register
Table 46-4. DMA Channel Descriptor Structure
System Memory
DSCR + 0x0
DSCR + 0x4
DSCR + 0x8
Structure Field for channel CHX
ADDR
CTRL
NEXT
46.6.2.2 Programming a DMA Channel
1.
Check the status of the channel reading the CHXCHSR register.
2.
Write the channel descriptor (DSCR) structure in the system memory by writing DSCR.CHXADDR Frame base address, DSCR.CHXCTRL channel control and DSCR.CHXNEXT next descriptor location.
3.
If more than one descriptor is expected, the DFETCH field of DSCR.CHXCTRL is set to one to enable the descriptor fetch operation.
4.
Write the DSCR.CHXNEXT register with the address location of the descriptor structure and set DFETCH field of the DSCR.CHXCTRL register to one.
5.
Enable the relevant channel by writing one to the CHEN field of the CHXCHER register.
6.
An interrupt may be raised if unmasked when the descriptor has been loaded.
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46.6.2.3 Disabling a DMA channel
1.
Clear the DFETCH bit in the DSCR.CHXCTRL field of the DSCR structure will disable the channel at the end of the frame.
2.
Set the DSCR.CHXNEXT field of the DSCR structure will disable the channel at the end of the frame.
3.
Writing one to the CHDIS field of the CHXCHDR register will disable the channel at the end of the frame.
4.
Writing one to the CHRST field of the CHXCHDR register will disable the channel immediately. This may occur in the middle of the image.
5.
Poll CHSR field in the CHXCHSR register until the channel is successfully disabled.
46.6.2.4 DMA Dynamic Linking of a New Transfer Descriptor
1.
Write the new descriptor structure in the system memory.
2.
Write the address of the new structure in the CHXHEAD register.
3.
Add the new structure to the queue of descriptors by writing one to the A2QEN field of the CHXCHER register.
4.
The new descriptor will be added to the queue on the next frame.
5.
An interrupt will be raised if unmasked, when the head descriptor structure has been loaded by the DMA channel.
46.6.2.5 DMA Interrupt Generation
The DMA controller operation sets the following interrupt flags in the interrupt status register CHXISR:
DMA field indicates that the DMA transfer is completed.
DSCR field indicates that the descriptor structure is loaded in the DMA controller.
ADD field indicates that a descriptor has been added to the descriptor queue.
DONE field indicates that the channel transfer has terminated and the channel is automatically disabled.
46.6.2.6 DMA Address Alignment Requirements
When programming the DSCR.CHXADDR field of the DSCR structure the following requirement must be met.
Table 46-5. DMA address alignment when CLUT Mode is selected
CLUT Mode DMA Address Alignment
1 bpp
2 bpp
4 bpp
8 bpp
8 bit
8 bit
8 bit
8 bit
Table 46-6. DMA address alignment when RGB Mode is selected
RGB Mode
12 bpp RGB 444 16 bit
DMA Address Alignment
16 bpp ARGB 4444
16 bpp RGBA 4444
16 bpp RGB 565
16 bpp TRGB 1555
16 bit
16 bit
16 bit
16 bit
18 bpp RGB 666
18 bpp RGB 666 PACKED
19 bpp TRGB 1666
19 bpp TRGB 1666
24 bpp RGB 888
32 bit
8 bit
32 bit
8 bit
32 bit
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Table 46-6. DMA address alignment when RGB Mode is selected
RGB Mode DMA Address Alignment
24 bpp RGB 888 PACKED 8 bit
25 bpp TRGB 1888
32 bpp ARGB 8888
32 bpp RGBA 8888
32 bit
32 bit
32 bit
Table 46-7. DMA address alignment when YUV Mode is selected
YUV Mode
32 bpp AYCrCb
16 bpp YCrCb 4:2:2
DMA Address Alignment
32 bit
32 bit
Y 8 bit
16 bpp semiplanar YCrCb 4:2:2
CrCb 16 bit
Y 8 bit
16 bpp planar YCrCb 4:2:2
12 bpp YCrCb 4:2:0
Cr 8 bit
Cb 8 bit
Y 8 bit
CrCb 16 bit
12 bpp YCrCb 4:2:0
Y 8 bit
Cr 8 bit
Cb 8 bit
46.6.3 Display Software Configuration
46.6.3.1 System Bus Access Attributes
These attributes are defined to improve bandwidth of the pixel stream.
LOCKDIS field: when set to one the AHB lock signal is not asserted when the PSTRIDE value is different from zero (rotation in progress).
ROTDIS field: when set to one the Pixel Striding optimization is disabled.
DLBO field: when set to one only defined burst lengths are performed when the DMA channel retrieves the data from the memory.
BLEN field: defines the maximum burst length of the DMA channel.
SIF field: defines the targeted DMA interface.
46.6.3.2 Color Attributes
CLUTMODE field: selects the color lookup table mode
RGBMODE field: selects the RGB mode.
YUVMODE field: selects the Luminance Chrominance mode.
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46.6.3.3 Window Position, Size, Scaling and Striding Attributes
XPOS, YPOS: fields define the position of the overlay window.
XSIZE, YSIZE: fields define the size of the displayed window.
XMEM_SIZE,YMEM_SIZE: fields define the size of the image frame buffer.
XSTRIDE, PSTRIDE: fields define the line and pixel striding.
XFACTOR, YFACTOR: fields define the scaling ratio.
The position and size attributes are to be programmed to keep the window within the display area.
When the color lookup mode is enabled the following restrictions apply on the horizontal and vertical window size:
Table 46-8. Color Lookup Mode and Window Size
CLUT Mode x-y Size Requirement
1 bpp
2 bpp multiple of 8 pixels multiple of 4 pixels
4 bpp
8 bpp multiple of 2 pixels free size
Pixel striding is disabled when CLUT mode is enabled.
When YUV mode is enabled the following restrictions apply on the window size:
Table 46-9. YUV Mode and Window Size
YUV Mode x-y Requirement,
Scaling Turned Off
AYUV
YUV 4:2:2 packed
YUV 4:2:2 semiplanar free size xsize is greater than 2 pixels xsize is greater than 2 pixels
YUV 4:2:2 planar
YUV 4:2:0 semiplanar
YUV 4:2:0 planar xsize is greater than 2 pixels xsize is greater that 2 pixels xsize is greater than 2 pixels
In RGB mode, there is no restriction on the line length.
x-y Requirement,
Scaling Turned On x-y size is greater than 5 x-y size is greater than 5 x-y size is greater than 5 x-y size is greater than 5 x-y size is greater than 5 x-y size is greater than 5
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46.6.3.4 Overlay Blender Attributes
When two or more video layers are used, alpha blending is performed to defined the final image displayed. Each window has its own blending attributes.
CRKEY Field: enables the chroma keying and match logic.
INV Field: performs bit inversion at pixel level.
ITER2BL Field: when set the iterated data path is selected.
ITER Field.
REVALPHA Field: uses the reverse alpha value.
GAEN Field: enables the global alpha value in the data path.
LAEN Field: enables the local alpha value from the pixel.
OVR Field: when set the overlay is selected as an input of the blender.
DMA Field: the DMA data path is activated.
REP Field: enables the bit replication to fill the 24-bit internal data path.
DSTKEY Field: when set, Destination keying is enabled.
GA Field: defines the global alpha value.
46.6.3.5 Window Attributes Software Operation
1.
When required, write the overlay attributes configuration registers.
2.
Set UPDATEEN field of the CHXCHER register.
3.
Poll UPDATESR field in the CHXCHSR, the update applies when that field is reset.
46.6.4 RGB Frame Buffer Memory Bitmap
46.6.4.1 1 bpp Through Color Lookup Table
Table 46-10. 1 bpp memory mapping, little endian organization
Mem addr 0x3 0x2 0x1 0x0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pixel 1 bpp p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0
46.6.4.2 2 bpp Through Color Lookup Table
Table 46-11. 2 bpp memory mapping, little endian organization
Mem addr 0x3
Bit
Pixel 2 bpp
0x2 0x1 0x0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0
46.6.4.3 4 bpp Through Color Lookup Table
Table 46-12. 4 bpp memory mapping, little endian organization
Mem addr 0x3
Bit
0x2 0x1 0x0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pixel 4 bpp p7 p6 p5 p4 p3 p2 p1 p0
46.6.4.4 8 bpp Through Color Lookup Table
Table 46-13. 8 bpp memory mapping, little endian organization
Mem addr 0x3 0x2
Bit
Pixel 8 bpp
0x1 0x0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p3 p2 p1 p0
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46.6.4.5 12 bpp Memory Mapping, RGB 4:4:4
Table 46-14. 12 bpp memory mapping, little endian organization
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 12 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
– R1[3:0] G1[3:0] B1[3:0] – R0[3:0] G0[3:0] B0[3:0]
46.6.4.6 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4
Table 46-15. 16 bpp memory mapping, little endian organization
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 16 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A1[3:0] R1[3:0] G1[3:0] B1[3:0] A0[3:0] R0[3:0] G0[3:0] B0[3:0]
46.6.4.7 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4
Table 46-16. 16 bpp memory mapping, little endian organization
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 16 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R1[3:0] G13:0] B1[3:0] A1[3:0] R0[3:0] G0[3:0] B0[3:0] A0[3:0]
46.6.4.8 16 bpp Memory Mapping with Alpha Channel, RGB 5:6:5
Table 46-17. 16 bpp memory mapping, little endian organization
Mem addr 0x3 0x2
Bit
Pixel 16bpp
0x1 0x0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R1[4:0] G1[5:0] B1[4:0] R0[4:0] G0[5:0] B0[4:0]
46.6.4.9 16 bpp Memory Mapping with Transparency Bit, ARGB 1:5:5:5
Table 46-18. 16 bpp memory mapping, little endian organization
Mem addr 0x3 0x2 0x1 0x0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pixel 4 bpp A1 R1[4:0] G1[4:0] B1[4:0] A0 R0[4:0] G0[4:0] B0[4:0]
46.6.4.10 18 bpp Unpacked Memory Mapping with Transparency Bit, RGB 6:6:6
Table 46-19. 18 bpp unpacked memory mapping, little endian organization
Mem addr 0x3
Bit
0x2 0x1 0x0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pixel 18 bpp R0[5:0] G0[5:0] B0[5:0]
46.6.4.11 18 bpp Packed Memory Mapping with Transparency Bit, RGB 6:6:6
Table 46-20. 18 bpp packed memory mapping, little endian organization at address 0x0, 0x1, 0x2, 0x3
Mem addr 0x3 0x2 0x1 0x0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pixel 18 bpp G1[1:0] B1[5:0] R0[5:0] G0[5:0] B0[5:0]
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Table 46-21. 18 bpp packed memory mapping, little endian organization at address 0x4, 0x5, 0x6, 0x7
Mem addr 0x7 0x6 0x5 0x4
Bit
Pixel 18 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R2[3:0] G2[5:0] B2[5:0] R1[5:2] G1[5:2]
Table 46-22. 18 bpp packed memory mapping, little endian organization at address 0x8, 0x9, 0xA, 0xB
Mem addr 0xB 0xA 0x9 0x8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pixel 18 bpp G4[1:0] B4[5:0] R3[5:0] G3[5:0] B3[3:0] R2[5:4]
46.6.4.12 19 bpp Unpacked Memory Mapping with Transparency Bit, RGB 1:6:6:6
Table 46-23. 19 bpp unpacked memory mapping, little endian organization
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 19 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A0 R0[5:0] G0[5:0] B0[5:0]
46.6.4.13 19 bpp Packed Memory Mapping with Transparency Bit, ARGB 1:6:6:6
Table 46-24. 19 bpp packed memory mapping, little endian organization at address 0x0, 0x1, 0x2, 0x3
Mem addr 0x3 0x2 0x1 0x0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pixel 19 bpp G1[1:0] B1[5:0] A0 R0[5:0] G0[5:0] B0[5:0]
Table 46-25. 19 bpp packed memory mapping, little endian organization at address 0x4, 0x5, 0x6, 0x7
Mem addr 0x7
Bit
0x6 0x5 0x4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pixel 19 bpp R2[3:0] G2[5:0] B2[5:0] A1 R1[5:2] G1[5:2]
Table 46-26. 19 bpp packed memory mapping, little endian organization at address 0x8, 0x9, 0xA, 0xB
Mem addr 0xB
Bit
0xA 0x9 0x8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pixel 19 bpp G4[1:0] B4[5:0] A3 R3[5:0] G3[5:0] B3[3:0] R2[5:4]
46.6.4.14 24 bpp Unpacked Memory Mapping, RGB 8:8:8
Table 46-27. 24 bpp memory mapping, little endian organization
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 24 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0[7:0] G0[7:0] B0[7:0]
46.6.4.15 24 bpp Packed Memory Mapping, RGB 8:8:8
Table 46-28. 24 bpp packed memory mapping, little endian organization at address 0x0, 0x1, 0x2, 0x3
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 24 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1[7:0] R0[7:0] G0[7:0] B0[7:0]
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Table 46-29. 24 bpp packed memory mapping, little endian organization at address 0x4, 0x5, 0x6, 0x7
Mem addr 0x7 0x6 0x5 0x4
Bit
Pixel 24 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G2[7:0] B2[7:0] R1[7:0] G1[7:0]
46.6.4.16 25 bpp Memory Mapping, ARGB 1:8:8:8
Table 46-30. 25 bpp memory mapping, little endian organization
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 25 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A0 R0[7:0] G0[7:0] B0[7:0]
46.6.4.17 32 bpp Memory Mapping, ARGB 8:8:8:8
Table 46-31. 32 bpp memory mapping, little endian organization
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 32 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A0[7:0] R0[7:0] G0[7:0] B0[7:0]
46.6.4.18 32 bpp Memory Mapping, RGBA 8:8:8:8
Table 46-32. 32 bpp memory mapping, little endian organization
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 32 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0[7:0] G0[7:0] B0[7:0] A0[7:0]
46.6.5 YUV Frame Buffer Memory Mapping
46.6.5.1 AYCbCr 4:4:4 Interleaved Frame Buffer Memory Mapping
Table 46-33. 32 bpp memory mapping, little endian organization
Mem addr 0x3
Bit
0x2 0x1 0x0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pixel 16 bpp A0[7:0] Y0[7:0] Cb0[7:0] Cr0[7:0]
46.6.5.2 4:2:2 Interleaved Mode Frame Buffer Memory Mapping
Table 46-34. 16 bpp memory mapping, little endian organization, Mode 0
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 16 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Cr0[7:0] Y1[7:0] Cb0[7:0] Y0[7:0]
Table 46-35. 16 bpp memory mapping, little endian organization, Mode 1
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 16 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Y1[7:0] Cr0[7:0] Y0[7:0] Cb0[7:0]
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Table 46-36. 16 bpp memory mapping, little endian organization, Mode 2
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 16 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Cb0[7:0] Y1[7:0] Cr0[7:0] Y0[7:0]
Table 46-37. 16 bpp memory mapping, little endian organization, Mode 3
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 16 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Y1[7:0] Cb0[7:0] Y0[7:0] Cr0[7:0]
46.6.5.3 4:2:2 Semiplanar Mode Frame Buffer Memory Mapping
Table 46-38. 4:2:2 Semiplanar Luminance memory mapping with little endian organization for byte 0x0, 0x1, 0x2, 0x3
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 16 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Y3[7:0] Y2[7:0] Y1[7:0] Y0[7:0]
Table 46-39. 4:2:2 Semiplanar Chrominance memory mapping with little endian organization for byte 0x0, 0x1, 0x2, 0x3
Mem addr 0x3 0x2 0x1 0x0
31
Pixel 16 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Cb2[7:0] Cr2[7:0] Cb0[7:0] Cr0[7:0]
46.6.5.4 4:2:2 Planar Mode Frame Buffer Memory Mapping
Table 46-40. 4:2:2 planar mode Luminance memory mapping with little endian organization for byte 0x0, 0x1, 0x2, 0x3
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 16 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Y3[7:0] Y2[7:0] Y1[7:0] Y0[7:0]
Table 46-41. 4:2:2 planar mode Chrominance memory mapping with little endian organization for byte 0x0, 0x1, 0x2, 0x3
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 16 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3[7:0] C2[7:0] C1[7:0] C0[7:0]
46.6.5.5 4:2:0 Planar Mode Frame Buffer Memory Mapping
In Planar Mode, the three video components Y, Cr and Cb are split into 3 memory areas and stored in a raster-scan order. These three memory planes are contiguous and always aligned on a 32-bit boundary.
Table 46-42. 4:2:0 planar mode Luminance memory mapping with little endian organization for byte 0x0, 0x1, 0x2, 0x3
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 12 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Y3[7:0] Y2[7:0] Y1[7:0] Y0[7:0]
Table 46-43. 4:2:0 planar mode Luminance memory mapping with little endian organization for byte 0x4, 0x5, 0x6, 0x7
Mem addr 0x7 0x6 0x5 0x4
Bit
Pixel 12 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Y7[7:0] Y6[7:0] Y5[7:0] Y4[7:0]
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Table 46-44. 4:2:0 planar mode Chrominance memory mapping with little endian organization for byte 0x0, 0x1, 0x2, 0x3
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 12 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C3[7:0] C2[7:0] C1[7:0] C0[7:0]
Table 46-45. 4:2:0 planar mode Chrominance memory mapping with little endian organization for byte 0x4, 0x5, 0x6, 0x7
Mem addr 0x7 0x6 0x5 0x4
Bit
Pixel 12 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C7[7:0] C6:[7:0] C5[7:0] C4[7:0]
46.6.5.6 4:2:0 Semiplanar Frame Buffer memory Mapping
Table 46-46. 4:2:0 semiplanar mode Luminance memory mapping with little endian organization
Mem addr 0x7 0x6 0x5 0x4
Bit
Pixel 12 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Y3[7:0] Y2[7:0] Y1[7:0] Y0[7:0]
Table 46-47. 4:2:0 semiplanar mode Chrominance memory mapping with little endian organization for
Mem addr 0x3 0x2 0x1 0x0
Bit
Pixel 12 bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Cb1[7:0] Cr1[7:0] Cb0[7:0] Cr0[7:0]
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46.6.6 Chrominance Upsampling Unit
Both 4:2:2 and 4:2:0 input formats are supported by the LCD module. In 4:2:2, the two chrominance components are sampled at half the sample rate of the luminance. The horizontal chrominance resolution is halved. When this input format is selected, the chrominance upsampling unit uses two chrominances to interpolate the missing component.
In 4:2:0, Cr and Cb components are subsampled at a factor of two vertically and horizontally. When this input mode is selected, the chrominance upsampling unit uses two and four chroma components to generate the missing horizontal and vertical components.
Figure 46-2. 4:2:2 Upsampling Algorithm
Vertic a l a nd Horizont a l u p sa mpling 4:2:0 to 4:4:4 conver s ion
C[0,0] C[x/2,0] C[x,0]
C[0,y/2] C[x/2,y/2] C[x,y/2]
C[0,y] C[x/2,y] C[x,y]
Y sa mple
Cr C b c a lc u l a ted a t encoding time
Cr C b interpol a ted from 2 Chrom a Component
Cr C b interpol a ted from 4 Chrom a Component
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Figure 46-3. 4:2:2 Packed Memory Upsampling Algorithm
Vertic a l a nd Horizont a l u p sa mpling 4:2:2 to 4:4:4 conver s ion 90 or 270 degree
C[0,0] C[x/2,0] C[x,0]
C[0,y/2] C[x/2,y/2] C[x,y/2]
C[0,y] C[x/2,y] C[x,y]
Y sa mple
Cr C b c a lc u l a ted a t encoding time
Cr C b from the previo us line (interpol a ted)
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Figure 46-4. 4:2:2 Semiplanar and Planar Upsampling Algorithm - 90 or 270 Degree Rotation Activated
Vertic a l a nd Horizont a l u p sa mpling 4:2:2 to 4:4:4 conver s ion 90 or 270 degree
C[0,0] C[x/2,0] C[x,0]
C[0,y/2] C[x/2,y/2] C[x,y/2]
C[0,y] C[x/2,y] C[x,y]
Y sample
Cr Cb calculated at encoding time
Cr C b interpol a ted
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Figure 46-5. 4:2:0 Upsampling Algorithm
Vertic a l a nd Horizont a l u p sa mpling 4:2:0 to 4:4:4 conver s ion
C[0,0] C[x/2,0] C[x,0]
C[0,y/2] C[x/2,y/2] C[x,y/2]
C[0,y] C[x/2,y] C[x,y]
Y sa mple
Cr C b c a lc u l a ted a t encoding time
Cr C b interpol a ted from 2 Chrom a Component
Cr C b interpol a ted from 4 Chrom a Component
Chroma x
---
2
,
0 =
Cr [ 0 0 ] + Cr [ 0 , x ]
2
Chroma 0 ,
2
Chroma ---
,
2
=
Cr [ 0 0 ]
+ C [ 0 , y ]
2
=
Cr [ 0 0 ] + [ , 0 ] + [ , 0 ] + [ ]
4
Chroma x ,
2
Chroma x
2
, y
=
Cr x ,
0
]
+
[ ]
2
=
Cr [ 0 , y ] + [ ]
2
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46.6.6.1 Chrominance Upsampling Algorithm
1.
Read line n from chrominance cache and interpolate [x/2,0] chrominance component filling the 1 x 2 kernel with line n. If the chrominance cache is empty, then fetch the first line from external memory and interpolate from the external memory. Duplicate the last chrominance at the end of line.
2.
Fetch line n+1 from external memory, write line n + 1 to chrominance cache, read line n from the chrominance cache. interpolate [0,y/2], [x/2,y/2] and [x, y/2] filling the 2x2 kernel with line n and n+1. Duplicate the last chrominance line to generate the last interpolated line.
3.
Repeat step 1 and step 2.
46.6.7 Line and Pixel Striding
The LCD module includes a mechanism to increment the memory address from a programmable amount when the end of line has been reached, this offset is referred as XSTRIDE and is defined on a per overlay basis. It also contains a
PSTRIDE field that allows a programmable jump at the pixel level. Pixel stride is the value from one pixel to the next.
46.6.7.1 Line Striding
When the end of line has been reached, the DMA address counter points to the next pixel address. The channel DMA address register is added to the XSTRIDE field, and then updated. If XSTRIDE is set to zero, the DMA address register remains unchanged. The XSTRIDE field of the channel configuration register is aligned to the pixel size boundary. The
XSTRIDE field is a two’s complement number.
46.6.7.2 Pixel Striding
The DMA channel engine may optionally fetch non contiguous pixels. The channel DMA address register is added to the
PSTRIDE field and then updated. If PSTRIDE is set to zero, the DMA address register remains unchanged and pixels are contiguous. The PSTRIDE field of the channel configuration register is aligned to the pixel size boundary. The
PSTRIDE is a two’s complement number.
46.6.8 Color Space Conversion Unit
The color space conversion unit converts Luminance Chrominance color space into the Red Green Blue color space.
The conversion matrix is defined below and is fully programmable through the LCD user interface
R
G
B
=
CSCRY CSCRU CSCRV
CSCGY CSCGU CSCGV
CSCBY CSCBU CSCBV
Color space conversion coefficients are defined with the following equation:
CSC ( Note )
=
1
7
⋅
– 2
2
9 ⋅ c
9
+
8
n = 0 c n
⋅ 2 n
Color space conversion coefficients are defined with one sign bit, 2 integer bits and 7 fractional bits. The range of the
CSC coefficients is defined below with a step of 1/128.
– 4 ≤ CSC ( Note ) ≤ 3.9921875
Note: CSC values for all matrix coefficients.
Additionally a set scaling factor {Yoff, Cboff, Croff} can be applied.
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46.6.9 Two Dimension Scaler
The High End Overlay (HEO) data path includes a hardware scaler that allows image resize in both horizontal and vertical direction.
46.6.9.1 Horizontal Scaler
The XMEM_SIZE field of the LCDC_HEOCFG4 register indicates the horizontal size minus one of the image in the system memory. The XSIZE field of the LCDC_HEOCFG3 register contains the horizontal size minus one of the window.
The SCALEN field of the LCDC_HEOCFG13 register is set to one. The scaling factor is programmed in the XFACTOR field of the LCDC_HEOCFG13 register.
XFACTOR = floor
1024
×
(
XMEMSIZE
XSIZE + 1
+ 1
)
46.6.9.2 Vertical Scaler
The YMEM_SIZE field of the LCDC_HEOCFG4 register indicates the vertical size minus one of the image in the system memory. The YSIZE field of the LCDC_HEOCFG3 register contains the vertical size minus one of the window. The
SCALEN field of the LCDC_HEOCFG13 register is set to one. The scaling factor is programmed in the YFACTOR field of the LCDC_HEOCFG13 register.
YFACTOR = floor
1024 ×
(
( YMEMSIZE
YSIZE + 1
)
+ 1
46.6.10 Hardware Cursor
The LCD module integrates a hardware cursor database. This layer features only a minimal set of color among 1, 2, 4 and 8 bpp palletized and 16 bpp to 32 bpp true color. The cursor size is limited to 128 x 128 pixels.
46.6.11 Color Combine Unit
46.6.11.1 Window Overlay
The LCD module provides hardware support for multiple “overlay plane” that can be used to display windows on top of the image without destroying the image located below. The overlay image can use any color depth. Using the overlay alleviates the need to re-render the occluded portion of the image. When pixels are combined together through the alpha blending unit, a new color is created. This new pixel is called an iterated pixel and is passed to the next blending stage.
Then, this pixel may be combined again with another pixel. The VIDPRI field located in the LCDC_HEOCFG12 register configures the video priority algorithm used to display the layers. When VIDPRI field is set to zero the OVR1 layer is located above the HEO layer. When VIDPRI field is set to one, OVR1 is located below the HEO layer.
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Figure 46-6. Overlay Example with two different video prioritization algorithms
HEO width
OVR1 width
B
as
e width o0(x,y)
HEO
o1(x,y)
Overl a y1
HCC
B as e Im a ge
B as e Im a ge
Video Prioritiz a tion Algorithm 1: HCC > OVR1 > HEO > BA S E
HEO
Overl a y1
HCC
B
as
e height
HEO height
OVR1 height
Video Prioritiz a tion Algorithm 2: HCC > HEO > OVR1 > BA S E
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46.6.11.2 Overlay Blending
The blending function requires two pixels (one iterated from the previous blending stage and one from the current overlay color) and a set of blending configuration parameters. These parameters define the color operation.
Figure 46-7. Alpha Blender Function iter[n-1] la ovr
From
Shadow
Registers
GA
OVR
LAEN
REVALPHA
ITER
ITER2BL
CRKEY
INV
DMA
GAEN
RGBKEY
RGBMASK
OVRDEF
Figure 46-8. Alpha Blender Datapath l a blending function iter[n] ovr iter[n-1]
OVR
ITER
OVRDEF
GA
GAEN
DMA
LAEN
REVALPHA
RGBKEY
RGBMA S K
CRKEY
INV
"0"
0
0
"0"
0 0
"0"
0 ovr
Alph a * ovr + (1 - Alph a ) * iter[n-1] ovr iter[n-1]
0
MATCH
LOGIC
0
0 iter[n]
Inverted
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46.6.11.3 Global Alpha Blender
Figure 46-9. Global Alpha Blender base ovr1la ovr1 iter[n-1] la ovr blending function iter[n] heola heo iter[n-1] la ovr blending function iter[n] hcrla hcr iter[n-1] la ovr blending function iter[n] blended pixel
46.6.11.4 Window Blending
Figure 46-10. 256-level Alpha Blending
B as e Im a ge
OVR1 25 %
HEO 75 %
Video Prioritiz a tion Algorithm 1: OVR1 > HEO > BA S E
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46.6.11.5 Color Keying
Color keying involves a method of bit-block image transfer (Blit). This entails blitting one image onto another where not all the pixels are copied. Blitting usually involves two bitmaps, a source bitmap and a destination bitmap. A raster operation
(ROP) is performed to define whether the iterated color or the overlay color is to be visible or not.
Source Color Keying
If the masked overlay color matches the color key then the iterated color is selected. Source Color Keying is activated using the following configuration.
Select the Overlay to Blit
Set DSTKEY field to zero
Activate Color Keying setting CRKEY field to 1
Program Color Key writing RKEY, GKEY and BKEY fields
Program Color Mask writing RKEY, GKEY and BKEY fields
When the Mask register is set to zero, the comparison is disabled and the raster operation is activated.
Destination Color Keying
If the iterated masked color matches the color key then the overlay color is selected. Destination Color Keying is activated using the following configuration:
Select the Overlay to Blit
Set DSTKEY field to one
Activate Color Keying setting CRKEY field to 1
Program Color Key writing RKEY, GKEY and BKEY fields
Program Color Mask writing RKEY, GKEY and BKEY fields
When the Mask register is set to zero, the comparison is disabled and the raster operation is activated.
46.6.12 LCD Overall Performance
46.6.12.1 Color Lookup Table (CLUT)
Table 46-48. CLUT Pixel Performance
CLUT Mode Pixels/Cycle ROTATION
1 bpp
2 bpp
4bpp
8 bpp
32
16
8
4
Not supported
Not supported
Not supported
Not supported
SCALING
Supported
Supported
Supported
Supported
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46.6.12.2 RGB Mode Fetch Performance
Table 46-49. RGB Mode Performance
RGB Mode
Pixels/Cycle
Memory
Burst Mode
12 bpp
16 bpp
18 bpp
18 bpp RGB PACKED
2
2
1
1.333
19 bpp
19 bpp PACKED
24 bpp
24 bpp PACKED
25 bpp
32 bpp
1
1.333
1
1.333
1
1
Rotation Peak Random Memory Access (pixels/cycle)
Rotation Optimization
Normal Mode
1
1
1
1
1
Not supported
1
Not Supported
1
Not Supported
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
Note: 1. Rotation optimization = AHB lock asserted on consecutive single access.
46.6.12.3 YUV Mode Fetch Performance
Table 46-50. Single Stream for 0 Wait State Memory
YUV Mode
Pixels/Cycle
Memory
Burst Mode
ROTATION peak random memory access (pixels/cycle)
Rotation Optimization Normal Mode
32 bpp AYUV
16 bpp 422
1
2
1
Not Supported
0.2
Not Supported
Note: Rotation optimization = AHB lock asserted on consecutive single access
.
Table 46-51. YMultiple Stream for 0 Wait State Memory
YUV Mode
16 bpp 422 semiplanar
Comp/Cycle
Memory
Burst Mode
4 Y, 2 UV
ROTATION peak random memory access (comp/cycle)
Rotation Optimization Normal Mode
1 Y, 1 UV (2 streams)
16 bpp 422 planar 4Y, 4U, 4V 1Y, 1U, 1V (3 streams)
0.2 Y 0.2 UV (2 streams)
0.2 Y, 0.2 U, 0.2 V (3 streams)
12 bpp 4:2:0 semiplanar 4Y, 2UV
12 bpp 4:2:0 planar 4Y, 4U, 4V
1 Y, 1 UV (2 streams)
1Y, 1U, 1V (3 streams)
0.2 Y 0.2 UV (2 streams)
0.2 Y, 0.2 U, 0.2 V (3 streams)
Scaling Burst Mode or
Rotation Optimization
Available
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Scaling Burst Mode or
Rotation Optimization
Available
Supported
Supported
Scaling Burst Mode or
Rotation Optimization
Available
Supported
Supported
Supported
Supported
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Table 46-52. YUV Planar Overall Performance 1 AHB Interface For 0 Wait State Memory
YUV Mode
16 bpp 422 semiplanar
Pixels/Cycle
Memory
Burst Mode
2
ROTATION peak random memory access (pixels/cycle)
Rotation Optimization Normal Mode
0.66
0.132
16 bpp 422 planar 2
12 bpp 4:2:0 semiplanar 2.66
12 bpp 4:2:0 planar 2.66
0.5
0.8
0.66
0.1
0.16
0.132
Scaling Burst Mode or
Rotation Optimization
Available
Supported
Supported
Supported
Supported
Table 46-53. YUV Planar Overall Performance 2 AHB Interface For 0 Wait State Memory
YUV Mode
16 bpp 422 semiplanar
Pixels/Cycle
Memory
Burst mode
4
ROTATION peak random memory access (pixels/cycle) rotation optimization
1
Normal Mode
0.2
16 bpp 422 planar 4
12 bpp 4:2:0 semiplanar 4
12 bpp 4:2:0 planar 4
1
1
1
0.2
0.2
0.2
Scaling Burst Mode or
Rotation Optimization
Available supported supported supported supported
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46.6.13 Output Timing Generation
46.6.13.1 Active Display Timing Mode
Figure 46-11. Active Display Timing
LCD_PCLK
LCD_VSYNC
LCD_HSYNC
LCD_BIAS_DEN
LCD_DAT[23:0]
HSW VSW
LCD_PCLK
LCD_VSYNC
LCD_HSYNC
LCD_BIAS_DEN
LCD_DAT[23:0]
HSW
HBP
LCD_PCLK
LCD_VSYNC
LCD_HSYNC
LCD_BIAS_DEN
LCD_DAT[23:0]
PPL
PPL
VBP
HFP HSW VFP
HBP
HFP HSW HBP
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Figure 46-12. Vertical Synchronization Timing (part 1)
V S PDLY S = 0 V S PDLYE = 0 V S P S U = 0 V S PHO = 0
LCD_PCLK
LCD_V S YNC
LCD_H S YNC
H S W V S W
V S PDLY S = 1 V S PDLYE = 0 V S P S U = 0 V S PHO = 0
LCD_PCLK
LCD_V S YNC
LCD_H S YNC
H S W V S W
V S PDLY S = 0 V S PDLYE = 1 V S P S U = 0 V S PHO = 0
LCD_PCLK
LCD_V S YNC
LCD_H S YNC
H S W V S W
V S PDLY S = 1 V S PDLYE = 1 V S P S U = 0 V S PHO = 0
LCD_PCLK
LCD_V S YNC
LCD_H S YNC
H S W V S W
V S PDLY S = 1 V S PDLYE = 0 V S P S U = 1 V S PHO = 0
LCD_PCLK
LCD_V S YNC
LCD_H S YNC
H S W V S W
VBP HBP
VBP HBP
VBP HBP
VBP HBP
VBP HBP
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1111
Figure 46-13. Vertical Synchronization Timing (part 2)
V S PDLY S = 1 V S PDLYE = 0 V S P S U = 0 V S PHO = 1
LCD_PCLK
LCD_V S YNC
LCD_H S YNC
H S W V S W
V S PDLY S = 1 V S PDLYE = 0 V S P S U = 1 V S PHO = 1
LCD_PCLK
LCD_V S YNC
LCD_H S YNC
H S W V S W
VBP
HBP
VBP HBP
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1112
Figure 46-14. DISP Signal Timing Diagram
VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 0
LCD_PCLK
LCD_V S YNC
LCD_H S YNC
LCD_DI S P lcd display off lcd display on
VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 0
LCD_PCLK
LCD_V S YNC
LCD_H S YNC
LCD_DI S P lcd display on
VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 1
LCD_PCLK
LCD_V S YNC
LCD_H S YNC
LCD_DI S P lcd display off lcd display on lcd display off
VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 1
LCD_PCLK
LCD_V S YNC
LCD_H S YNC
LCD_DI S P lcd display on lcd display off
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1113
46.6.14 Output Format
46.6.14.1 Active Mode Output Pin Assignment
Table 46-54. Active Mode Output with 24-bit Bus Interface Configuration
Pin ID TFT 24 bit TFT 18 bit TFT 16 bit
LCD_DAT[23]
LCD_DAT[22]
LCD_DAT[21]
LCD_DAT[20]
R[7]
R[6]
R[5]
R[4]
–
–
–
–
–
–
–
–
LCD_DAT[19]
LCD_DAT[18]
LCD_DAT[17]
LCD_DAT[16]
LCD_DAT[15]
LCD_DAT[14]
LCD_DAT[13]
LCD_DAT[12]
R[3]
R[2]
R[1]
R[0]
G[7]
G[6]
G[5]
G[4]
–
–
R[5]
R[4]
R[3]
R[2]
R[1]
R[0]
–
–
–
–
R[4]
R[3]
R[2]
R[1]
LCD_DAT[11]
LCD_DAT[10]
LCD_DAT[9]
LCD_DAT[8]
LCD_DAT[7]
LCD_DAT[6]
LCD_DAT[5]
LCD_DAT[4]
LCD_DAT[3]
LCD_DAT[2]
LCD_DAT[1]
LCD_DAT[0]
G[3]
G[2]
G[1]
G[0]
B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
G[5]
G[4]
G[3]
G[2]
G[1]
G[0]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
G[2]
G[1]
G[0]
B[4]
R[0]
G[5]
G[4]
G[3]
B[3]
B[2]
B[1]
B[0]
–
–
R[3]
R[2]
–
–
–
–
–
–
–
–
TFT 12 bit
–
–
G[1]
G[0]
B[3]
B[2]
R[1]
R[0]
G[3]
G[2]
B[1]
B[0]
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1114
46.7 LCD Controller (LCDC) User Interface
0x00000038
0x0000003C
0x00000040
0x00000044
0x00000048
0x0000004C
0x00000050
0x00000054
0x00000058
0x0000005C
0x00000060
0x00000064
0x00000068
0x0000006C
0x00000070
0x00000074
Table 46-55. Register Mapping
Offset Register
0x00000000
0x00000004
LCD Controller Configuration Register 0
LCD Controller Configuration Register 1
0x00000008
0x0000000C
0x00000010
0x00000014
LCD Controller Configuration Register 2
LCD Controller Configuration Register 3
LCD Controller Configuration Register 4
LCD Controller Configuration Register 5
0x00000018
0x0000001C
0x00000020
0x00000024
0x00000028
0x0000002C
0x00000030
0x00000034
LCD Controller Configuration Register 6
Reserved
LCD Controller Enable Register
LCD Controller Disable Register
LCD Controller Status Register
LCD Controller Interrupt Enable Register
LCD Controller Interrupt Disable Register
LCD Controller Interrupt Mask Register
0x00000078
0x0000007C
0x80-0xFC
0x00000100
0x00000104
0x00000108
0x0000010C
0x00000110
LCD Controller Interrupt Status Register
Reserved
Base Layer Channel Enable Register
Base Layer Channel Disable Register
Base Layer Channel Status Register
Base Layer Interrupt Enable Register
Base Layer Interrupt Disabled Register
Base Layer Interrupt Mask Register
Base Layer Interrupt status Register
Base Layer DMA Head Register
Base Layer DMA Address Register
Base Layer DMA Control Register
Base Layer DMA Next Register
Base Layer Configuration Register 0
Base Layer Configuration Register 1
Base Layer Configuration Register 2
Base Layer Configuration Register 3
Base Layer Configuration Register 4
Reserved
Overlay 1 Channel Enable Register
Overlay 1 Channel Disable Register
Overlay 1 Channel Status Register
Overlay 1 Interrupt Enable Register
Overlay 1 Interrupt Disable Register
Name
LCDC_LCDCFG0
LCDC_LCDCFG1
LCDC_LCDCFG2
LCDC_LCDCFG3
LCDC_LCDCFG4
LCDC_LCDCFG5
LCDC_LCDCFG6
–
LCDC_LCDEN
LCDC_LCDDIS
LCDC_LCDSR
LCDC_LCDIER
LCDC_LCDIDR
LCDC_LCDIMR
LCDC_LCDISR
–
LCDC_BASECHER
LCDC_BASECHDR
LCDC_BASECHSR
LCDC_BASEIER
LCDC_BASEIDR
LCDC_BASEIMR
LCDC_BASEISR
LCDC_BASEHEAD
LCDC_BASEADDR
LCDC_BASECTRL
LCDC_BASENEXT
LCDC_BASECFG0
LCDC_BASECFG1
LCDC_BASECFG2
LCDC_BASECFG3
LCDC_BASECFG4
–
LCDC_OVRCHER1
LCDC_OVRCHDR1
LCDC_OVRCHSR1
LCDC_OVRIER1
LCDC_OVRIDR1
–
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Access
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
–
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read-write
–
Write-only
Write-only
Read-only
Write-only
Write-only
–
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
–
–
–
0x00000000
-
-
0x00000000
0x00000000
0x00000000
–
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1115
Table 46-55. Register Mapping (Continued)
Offset Register
0x00000114
0x00000118
0x0000011C
0x00000120
Overlay 1 Interrupt Mask Register
Overlay 1 Interrupt Status Register
Overlay 1 DMA Head Register
Overlay 1 DMA Address Register
0x00000124
0x00000128
0x0000012C
0x00000130
0x00000134
0x00000138
0x0000013C
0x00000140
Overlay1 DMA Control Register
Overlay1 DMA Next Register
Overlay 1 Configuration 0 Register
Overlay 1 Configuration 1 Register
Overlay 1 Configuration 2 Register
Overlay 1 Configuration 3 Register
Overlay 1 Configuration 4 Register
Overlay 1 Configuration 5 Register
0x00000144
0x00000148
0x0000014C
0x00000150
0x154-0x27C
0x00000280
0x00000284
0x00000288
0x0000028C
0x00000290
0x00000294
0x00000298
0x0000029C
0x000002A0
0x000002A4
0x000002A8
Overlay 1 Configuration 6 Register
Overlay 1 Configuration 7 Register
Overlay 1 Configuration 8 Register
Overlay 1 Configuration 9 Register
Reserved
High End Overlay Channel Enable Register
High End Overlay Channel Disable Register
High End Overlay Channel Status Register
High End Overlay Interrupt Enable Register
High End Overlay Interrupt Disable Register
High End Overlay Interrupt Mask Register
High End Overlay Interrupt Status Register
High End Overlay DMA Head Register
High End Overlay DMA Address Register
High End Overlay DMA Control Register
High End Overlay DMA Next Register
0x000002AC
0x000002B0
0x000002B4
0x000002B8
0x000002BC
0x000002C0
0x000002C4
0x000002C8
0x000002CC
0x000002D0
0x000002D4
High End Overlay U DMA Head Register
High End Overlay U DMA Address Register
High End Overlay U DMA Control Register
High End Overlay U DMA Next Register
High End Overlay V DMA Head Register
High End Overlay V DMA Address Register
High End Overlay V DMA Control Register
High End Overlay VDMA Next Register
High End Overlay Configuration Register 0
High End Overlay Configuration Register 1
High End Overlay Configuration Register 2
Name
LCDC_OVRIMR1
LCDC_OVRISR1
LCDC_OVRHEAD1
LCDC_OVRADDR1
LCDC_OVRCTRL1
LCDC_OVRNEXT1
LCDC_OVR1CFG0
LCDC_OVR1CFG1
LCDC_OVR1CFG2
LCDC_OVR1CFG3
LCDC_OVR1CFG4
LCDC_OVR1CFG5
LCDC_OVR1CFG6
LCDC_OVR1CFG7
LCDC_OVR1CFG8
LCDC_OVR1CFG9
–
LCDC_HEOCHER
LCDC_HEOCHDR
LCDC_HEOCHSR
LCDC_HEOIER
LCDC_HEOIDR
LCDC_HEOIMR
LCDC_HEOISR
LCDC_HEOHEAD
LCDC_HEOADDR
LCDC_HEOCTRL
LCDC_HEONEXT
LCDC_HEOUHEAD
LCDC_HEOUADDR
LCDC_HEOUCTRL
LCDC_HEOUNEXT
LCDC_HEOVHEAD
LCDC_HEOVADDR
LCDC_HEOVCTRL
LCDC_HEOVNEXT
LCDC_HEOCFG0
LCDC_HEOCFG1
LCDC_HEOCFG2
Read-write
Read-write
–
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Access
Read-only
Read-only
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
0x00000000
0x00000000
–
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1116
Table 46-55. Register Mapping (Continued)
Offset Register
0x000002D8
0x000002DC
0x000002E0
0x000002E4
High End Overlay Configuration Register 3
High End Overlay Configuration Register 4
High End Overlay Configuration Register 5
High End Overlay Configuration Register 6
0x000002E8
0x000002EC
0x000002F0
0x000002F4
0x000002F8
0x000002FC
0x00000300
0x00000304
High End Overlay Configuration Register 7
High End Overlay Configuration Register 8
High End Overlay Configuration Register 9
High End Overlay Configuration Register 10
High End Overlay Configuration Register 11
High End Overlay Configuration Register 12
High End Overlay Configuration Register 13
High End Overlay Configuration Register 14
0x00000308
0x0000030C
0x310-0x33C
0x00000340
0x00000344
0x00000348
0x0000034C
0x00000350
0x00000354
0x00000358
0x0000035C
0x00000360
0x00000364
0x00000368
0x0000036C
0x00000370
High End Overlay Configuration Register 15
High End Overlay Configuration Register 16
Reserved
Hardware Cursor Channel Enable Register
Hardware Cursor Channel Disable Register
Hardware Cursor Channel Status Register
Hardware Cursor Interrupt Enable Register
Hardware Cursor Interrupt Disable Register
Hardware Cursor Interrupt Mask Register
Hardware Cursor Interrupt Status Register
Hardware Cursor DMA Head Register
Hardware cursor DMA Address Register
Hardware Cursor DMA Control Register
Hardware Cursor DMA NExt Register
Hardware Cursor Configuration 0 Register
Hardware Cursor Configuration 1 Register
0x00000374
0x00000378
0x0000037C
0x00000380
0x00000384
0x00000388
0x0000038C
0x00000390
Hardware Cursor Configuration 2 Register
Hardware Cursor Configuration 3 Register
Hardware Cursor Configuration 4 Register
Reserved
Hardware Cursor Configuration 6 Register
Hardware Cursor Configuration 7 Register
Hardware Cursor Configuration 8 Register
Hardware Cursor Configuration 9 Register
0x394-0x3FC Reserved
0x400 Base CLUT Register 0
...
...
Name
LCDC_HEOCFG3
LCDC_HEOCFG4
LCDC_HEOCFG5
LCDC_HEOCFG6
LCDC_HEOCFG7
LCDC_HEOCFG8
LCDC_HEOCFG9
LCDC_HEOCFG10
LCDC_HEOCFG11
LCDC_HEOCFG12
LCDC_HEOCFG13
LCDC_HEOCFG14
LCDC_HEOCFG15
LCDC_HEOCFG16
–
LCDC_HCRCHER
LCDC_HCRCHDR
LCDC_HCRCHSR
LCDC_HCRIER
LCDC_HCRIDR
LCDC_HCRIMR
LCDC_HCRISR
LCDC_HCRHEAD
LCDC_HCRADDR
LCDC_HCRCTRL
LCDC_HCRNEXT
LCDC_HCRCFG0
LCDC_HCRCFG1
LCDC_HCRCFG2
LCDC_HCRCFG3
LCDC_HCRCFG4
–
LCDC_HCRCFG6
LCDC_HCRCFG7
LCDC_HCRCFG8
LCDC_HCRCFG9
–
LCDC_BASECLUT0
...
–
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Access
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
–
Read-write
Read-write
Read-write
Read-write
–
Read-write
...
–
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
–
0x00000000
0x00000000
0x00000000
0x00000000
–
0x00000000
...
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1117
Table 46-55. Register Mapping (Continued)
Offset
0x7FC
0x800
Register
Base CLUT Register 255
...
0xBFC
...
Overlay 1 CLUT Register 255
0xC00-0xFFC Reserved
0x1000 High End Overlay CLUT Register 0
...
0x13FC
...
High End Overlay CLUT Register 255
Hardware Cursor CLUT Register 0
0x1400
...
0x17FC
0x1800-0x1FE4 Reserved
...
Hardware Cursor CLUT Register 255
0x1FEC
0x1FF0
Address Size Register
IP Name1 Register
0x1FF4
0x1FF8
0x1FFC
IP Name2 Register
Features Register
Version Register
Note: 1. The CLUT registers are located in RAM.
Name
LCDC_BASECLUT255
LCDC_OVR1CLUT0
...
LCDC_OVR1CLUT255
–
LCDC_HEOCLUT0
...
LCDC_HEOCLUT255
LCDC_HCRCLUT0
...
LCDC_HCRCLUT255
–
LCDC_ADDRSIZE
LCDC_IPNAME1
LCDC_IPNAME2
LCDC_FEATURES
LCDC_VERSION
Access
Read-write
...
Read-write
–
Read-write
...
Read-write
Read-write
...
Read-write
–
Read-only
Read-only
Read-only
Read-only
Read-only
Reset
0x00000000
...
0x00000000
–
0x00000000
...
0x00000000
0x00000000
...
0x00000000
–
0x
0x
0x
0x
0x
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1118
46.7.1 LCD Controller Configuration Register 0
Name:
Address:
Access:
Reset:
15
–
7
–
31
–
23
LCDC_LCDCFG0
0xF8038000
Read-write
0x00000000
14
–
6
–
30
–
22
13
–
5
–
29
–
21
28
–
27
–
20 19
CLKDIV
12
CGDISHCR
11
CGDISHEO
4
–
3
CLKPWMSEL
26
–
18
10
–
2
CLKSEL
25
–
17
24
–
16
9 8
CGDISOVR1 CGDISBASE
1
–
0
CLKPOL
• CLKPOL: LCD Controller Clock Polarity
0: Data/Control signals are launched on the rising edge of the Pixel Clock.
1: Data/Control signals are launched on the falling edge of the Pixel Clock.
• CLKSEL: LCD Controller Clock Source Selection
0: The Asynchronous output stage of the LCD controller is fed by MCK.
1: The Asynchronous output state of the LCD controller is fed by 2x MCK.
• CLKPWMSEL: LCD Controller PWM Clock Source Selection
0: The slow clock is selected and feeds the PWM module.
1: The system clock is selected and feeds the PWM module.
• CGDISBASE: Clock Gating Disable Control for the Base Layer
0: Automatic Clock Gating is enabled for the Base Layer.
1: Clock is running continuously.
• CGDISOVR1: Clock Gating Disable Control for the Overlay 1 Layer
0: Automatic Clock Gating is enabled for the Overlay 1 Layer.
1: Clock is running continuously.
• CGDISHEO: Clock Gating Disable Control for the High End Overlay
0: Automatic Clock Gating is enabled for the High End Overlay Layer.
1: Clock is running continuously.
• CGDISHCR: Clock Gating Disable Control for the Hardware Cursor Layer
0: Automatic Clock Gating is enabled for the Hardware Cursor Layer.
1: Clock is running continuously.
• CLKDIV: LCD Controller Clock Divider
8 bit width clock divider for pixel clock LCD_PCLK.
pixel_clock = selected_clock/(CLKDIV+2)
Where selected_clock is equal to system_clock when CLKSEL field is set to 0 and system_clock2x when CLKSEL is set to one.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1119
46.7.2 LCD Controller Configuration Register 1
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_LCDCFG1
0xF8038004
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
13
–
5
12
–
4
28
–
20
27
–
19
11
–
3
VSPW
HSPW
10
–
2
26
–
18
• HSPW: Horizontal Synchronization Pulse Width
Width of the LCD_HSYNC pulse, given in pixel clock cycles. Width is (HSPW+1) LCD_PCLK cycles.
• VSPW: Vertical Synchronization Pulse Width
Width of the LCD_VSYNC pulse, given in number of lines. Width is (VSPW+1) lines.
25
–
17
9
–
1
24
–
16
8
–
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1120
46.7.3 LCD Controller Configuration Register 2
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_LCDCFG2
0xF8038008
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
13
–
5
12
–
4
28
–
20
27
–
19
11
–
3
VBPW
VFPW
10
–
2
26
–
18
25
–
17
9
–
1
• VFPW: Vertical Front Porch Width
This field indicates the number of lines at the end of the Frame. The blanking interval is equal to (VFPW+1) lines.
• VBPW: Vertical Back Porch Width
This field indicates the number of lines at the beginning of the Frame. The blanking interval is equal to VBPW lines.
24
–
16
8
–
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1121
46.7.4 LCD Controller Configuration Register 3
Name:
Address:
Access:
Reset:
31
–
23
LCDC_LCDCFG3
0xF803800C
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
15
–
7
14
–
6
13
–
5
12
–
4
HBPW
27
–
19
11
–
3
HFPW
26
–
18
10
–
2
25
–
17
9
–
1
• HFPW: Horizontal Front Porch Width
Number of pixel clock cycles inserted at the end of the active line. The interval is equal to (HFPW+1) LCD_PCLK cycles.
• HBPW: Horizontal Back Porch Width
Number of pixel clock cycles inserted at the beginning of the line. The interval is equal to (HBPW+1) LCD_PCLK cycles.
24
–
16
8
–
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1122
46.7.5 LCD Controller Configuration Register 4
Name:
Address:
Access:
Reset:
31
–
23
LCDC_LCDCFG4
0xF8038010
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
15
–
7
14
–
6
13
–
5
12
–
4
RPF
27
–
19
11
–
3
26
18
10
2
PPL
• RPF: Number of Active Rows Per Frame
Number of active lines in the frame. The frame height is equal to (RPF+1) lines.
• PPL: Number of Pixels Per Line
Number of pixels in the frame. The number of active pixels in the frame is equal to (PPL+1) pixels.
25
RPF
17
9
PPL
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1123
46.7.6 LCD Controller Configuration Register 5
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
DISPDLY
LCDC_LCDCFG5
0xF8038014
Read-write
0x00000000
30
–
22
–
14
–
6
DITHER
29
–
21
–
13
VSPHO
5
–
28
–
20
12
VSPSU
4
DISPPOL
27
–
19
11
–
3
VSPDLYE
26
–
18
GUARDTIME
10
–
2
VSPDLYS
25
–
17
24
–
16
9
1
VSPOL
MODE
8
0
HSPOL
• HSPOL: Horizontal Synchronization Pulse Polarity
0: Active High
1: Active Low
• VSPOL: Vertical Synchronization Pulse Polarity
0: Active High
1: Active Low
• VSPDLYS: Vertical Synchronization Pulse Start
0: The first active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal pulse.
1: The first active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse.
• VSPDLYE: Vertical Synchronization Pulse End
0: The second active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal pulse.
1: The second active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse.
• DISPPOL: Display Signal Polarity
0: Active High
1: Active Low
• DITHER: LCD Controller Dithering
0: Dithering logical unit is disabled.
1: Dithering logical unit is activated.
• DISPDLY: LCD Controller Display Power Signal Synchronization
0: The LCD_DISP signal is asserted synchronously with the second active edge of the horizontal pulse.
1: The LCD_DISP signal is asserted asynchronously with both edges of the horizontal pulse.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1124
• MODE: LCD Controller Output Mode
Value
0
1
2
3
Name
OUTPUT_12BPP
OUTPUT_16BPP
OUTPUT_18BPP
OUTPUT_24BPP
Description
LCD output mode is set to 12 bits per pixel
LCD output mode is set to 16 bits per pixel
LCD output mode is set to 18 bits per pixel
LCD output mode is set to 24 bits per pixel
• VSPSU: LCD Controller Vertical Synchronization Pulse Setup Configuration
0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge.
1: The vertical synchronization pulse is asserted one pixel clock cycle before the horizontal pulse.
• VSPHO: LCD Controller Vertical Synchronization Pulse Hold Configuration
0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge.
1: The vertical synchronization pulse is held active one pixel clock cycle after the horizontal pulse.
• GUARDTIME: LCD DISPLAY Guard Time
Number of frames inserted during start up before LCD_DISP assertion.
Number of frames inserted after LCD_DISP reset.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1125
46.7.7 LCD Controller Configuration Register 6
Name:
Address:
Access:
Reset:
31
–
23
–
15
7
–
LCDC_LCDCFG6
0xF8038018
Read-write
0x00000000
30
–
22
–
14
6
–
29
–
21
–
13
5
–
28
–
20
–
12
PWMCVAL
4
PWMPOL
27
–
19
–
11
3
–
26
–
18
–
10
2
25
–
17
–
9
1
PWMPS
24
–
16
–
8
0
• PWMPS: PWM Clock Prescaler
3-bit value. Selects the configuration of the counter prescaler module. The PWMPS field decoding is listed below.
1
1
1
0
0
0
0
Value
0
0
0
0
1
1
1
0
1
0
0
1
0
1
Name
DIV_1
DIV_2
DIV_4
DIV_8
DIV_16
DIV_32
DIV_64
Description
The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK
The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/2
The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/4
The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/8
The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/16
The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/32
The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/64
• PWMPOL: LCD Controller PWM Signal Polarity
This bit defines the polarity of the PWM output signal. If set to one, the output pulses are high level (the output will be high whenever the value in the counter is less than the value CVAL) If set to zero, the output pulses are low level.
• PWMCVAL: LCD Controller PWM Compare Value
PWM compare value. Used to adjust the analog value obtained after an external filter to control the contrast of the display.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1126
46.7.8 LCD Controller Enable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_LCDEN
0xF8038020
Write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
PWMEN
26
–
18
–
10
–
2
DISPEN
25
–
17
–
9
–
1
SYNCEN
• CLKEN: LCD Controller Pixel Clock Enable
0: Writing this field to zero has no effect.
1: When set to one the pixel clock logical unit is activated.
• SYNCEN: LCD Controller Horizontal and Vertical Synchronization Enable
0: Writing this field to zero has no effect.
1: When set to one, both horizontal and vertical synchronization (LCD_VSYNC and LCD_HSYNC) signals are generated.
• DISPEN: LCD Controller DISP Signal Enable
0: Writing this field to zero has no effect.
1: When set to one, LCD_DISP signals is generated.
• PWMEN: LCD Controller Pulse Width Modulation Enable
0: Writing this field to zero has no effect.
1: When set to one, the PWM is enabled.
24
–
16
–
8
–
0
CLKEN
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1127
46.7.9 LCD Controller Disable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_LCDDIS
0xF8038024
Write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
PWMRST
3
PWMDIS
• CLKDIS: LCD Controller Pixel Clock Disable
0: No effect.
1: Disable the pixel clock.
• SYNCDIS: LCD Controller Horizontal and Vertical Synchronization Disable
0: No effect.
1: Disable the synchronization signals after the end of the frame.
• DISPDIS: LCD Controller DISP Signal Disable
0: No effect.
1: Disable the DISP signal.
• PWMDIS: LCD Controller Pulse Width Modulation Disable
0: No effect.
1: Disable the pulse width modulation signal.
• CLKRST: LCD Controller Clock Reset
0: No effect.
1: Reset the pixel clock generator module. The pixel clock duty cycle may be violated.
• SYNCRST: LCD Controller Horizontal and Vertical Synchronization Reset
0: No effect.
1: Reset the timing engine. Both Horizontal and vertical pulse width are violated.
• DISPRST: LCD Controller DISP Signal Reset
0: No effect.
1: Reset the DISP signal.
• PWMRST: LCD Controller PWM Reset
0: No effect.
1: Reset the PWM module, the duty cycle may be violated.
26
–
18
–
10
DISPRST
2
DISPDIS
25
–
17
–
9
SYNCRST
1
SYNCDIS
24
–
16
–
8
CLKRST
0
CLKDIS
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1128
46.7.10 LCD Controller Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_LCDSR
0xF8038028
Read-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
SIPSTS
27
–
19
–
11
–
3
PWMSTS
26
–
18
–
10
–
2
DISPSTS
25
–
17
–
9
–
1
LCDSTS
24
–
16
–
8
–
0
CLKSTS
• CLKSTS: Clock Status
0: Pixel Clock is disabled.
1: Pixel Clock is running.
• LCDSTS: LCD Controller Synchronization status
0: Timing Engine is disabled.
1: Timing Engine is running.
• DISPSTS: LCD Controller DISP Signal Status
0: DISP is disabled.
1: DISP signal is activated.
• PWMSTS: LCD Controller PWM Signal Status
0: PWM is disabled.
1: PWM signal is activated.
• SIPSTS: Synchronization In Progress
0: Clock domain synchronization is terminated.
1: A double domain synchronization is in progress, access to the LCDC_LCDEN and LCDC_LCDDIS registers has no effect.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1129
46.7.11 LCD Controller Interrupt Enable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_LCDIER
0xF803802C
Write-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
FIFOERRIE
27
–
19
–
11
HCRIE
3
–
• SOFIE: Start of Frame Interrupt Enable Register
0: No effect.
1: Enable the interrupt.
• DISIE: LCD Disable Interrupt Enable Register
0: No effect.
1: Enable the interrupt.
• DISPIE: Power UP/Down Sequence Terminated Interrupt Enable Register
0: No effect.
1: Enable the interrupt.
• FIFOERRIE: Output FIFO Error Interrupt Enable Register
0: No effect.
1: Enable the interrupt.
• BASEIE: Base Layer Interrupt Enable Register
0: No effect.
1: Enable the interrupt.
• OVR1IE: Overlay 1 Interrupt Enable Register
0: No effect.
1: Enable the interrupt.
• HEOIE: High End Overlay Interrupt Enable Register
0: No effect.
1: Enable the interrupt.
• HCRIE: Hardware Cursor Interrupt Enable Register
0: No effect.
1: Enable the interrupt.
26
–
18
–
10
HEOIE
2
DISPIE
25
–
17
–
9
OVR1IE
1
DISIE
24
–
16
–
8
BASEIE
0
SOFIE
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1130
46.7.12 LCD Controller Interrupt Disable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_LCDIDR
0xF8038030
Write-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
FIFOERRID
27
–
19
–
11
HCRID
3
–
• SOFID: Start of Frame Interrupt Disable Register
0: No effect.
1: Disable the interrupt.
• DISID: LCD Disable Interrupt Disable Register
0: No effect.
1: Disable the interrupt.
• DISPID: Power UP/Down Sequence Terminated Interrupt Disable Register
0: No effect.
1: Disable the interrupt.
• FIFOERRID: Output FIFO Error Interrupt Disable Register
0: No effect.
1: Disable the interrupt.
• BASEID: Base Layer Interrupt Disable Register
0: No effect.
1: Disable the interrupt.
• OVR1ID: Overlay 1 Interrupt Disable Register
0: No effect.
1: Disable the interrupt.
• HEOID: High End Overlay Interrupt Disable Register
0: No effect.
1: Disable the interrupt.
• HCRID: Hardware Cursor Interrupt Disable Register
0: No effect.
1: Disable the interrupt.
26
–
18
–
10
HEOID
2
DISPID
25
–
17
–
9
OVR1ID
1
DISID
24
–
16
–
8
BASEID
0
SOFID
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1131
46.7.13 LCD Controller Interrupt Mask Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_LCDIMR
0xF8038034
Read-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
FIFOERRIM
27
–
19
–
11
HCRIM
3
–
• SOFIM: Start of Frame Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• DISIM: LCD Disable Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• DISPIM: Power UP/Down Sequence Terminated Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• FIFOERRIM: Output FIFO Error Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• BASEIM: Base Layer Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• OVR1IM: Overlay 1 Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• HEOIM: High End Overlay Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• HCRIM: Hardware Cursor Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
26
–
18
–
10
HEOIM
2
DISPIM
25
–
17
–
9
OVR1IM
1
DISIM
24
–
16
–
8
BASEIM
0
SOFIM
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1132
46.7.14 LCD Controller Interrupt Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_LCDISR
0xF8038038
Read-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
FIFOERR
27
–
19
–
11
HCR
3
–
26
–
18
–
10
HEO
2
DISP
25
–
17
–
9
OVR1
1
DIS
24
–
16
–
8
BASE
0
SOF
• SOF: Start of Frame Interrupt Status Register
When set to one, this flag indicates that a start of frame event has been detected. This flag is reset after a read operation.
• DIS: LCD Disable Interrupt Status Register
When set to one, this flag indicates that the horizontal and vertical timing generator has been successfully disabled. This flag is reset after a read operation.
• DISP: Power-up/Power-down Sequence Terminated Interrupt Status Register
When set to one, this flag indicates whether the power-up sequence or power-down sequence has terminated. This flag is reset after a read operation.
• FIFOERR: Output FIFO Error
When set to one, this flag indicates that an underflow occurs in the output FIFO. This flag is reset after a read operation.
• BASE: Base Layer Raw Interrupt Status Register
When set to one, this flag indicates that a Base layer interrupt is pending. This flag is reset as soon as the BASEISR register is read.
• OVR1: Overlay 1 Raw Interrupt Status Register
When set to one, this flag indicates that an Overlay 1 layer interrupt is pending. This flag is reset as soon as the OVR1ISR register is read.
• HEO: High End Overlay Raw Interrupt Status Register
When set to one, this flag indicates that a Hi End layer interrupt is pending. This flag is reset as soon as the HEOISR register is read.
• HCR: Hardware Cursor Raw Interrupt Status Register
When set to one, this flag indicates that a Hardware Cursor layer interrupt is pending. This flag is reset as soon as the HCRISR register is read.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1133
46.7.15 Base Layer Channel Enable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_BASECHER
0xF8038040
Write-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
A2QEN
25
–
17
–
9
–
1
UPDATEEN
24
–
16
–
8
–
0
CHEN
• CHEN: Channel Enable Register
0: No effect.
1: Enable the DMA channel.
• UPDATEEN: Update Overlay Attributes Enable Register
0: No effect.
1: Update windows attributes on the next start of frame.
• A2QEN: Add Head Pointer Enable Register
Write this field to one to add the head pointer to the descriptor list. This field is reset by hardware as soon as the head register is added to the list.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1134
46.7.16 Base Layer Channel Disable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_BASECHDR
0xF8038044
Write-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
• CHDIS: Channel Disable Register
When set to one, this field disables the layer at the end of the current frame. The frame is completed.
• CHRST: Channel Reset Register
When set to one, this field resets the layer immediately. The frame is aborted.
25
–
17
–
9
–
1
–
24
–
16
–
8
CHRST
0
CHDIS
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1135
46.7.17 Base Layer Channel Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_BASECHSR
0xF8038048
Read-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
A2QSR
• CHSR: Channel Status Register
When set to one, this field disables the layer at the end of the current frame.
• UPDATESR: Update Overlay Attributes In Progress
When set to one, this bit indicates that the overlay attributes will be updated on the next frame.
• A2QSR: Add To Queue Pending Register
When set to one, this bit indicates that the head pointer is still pending.
25
–
17
–
9
–
1
UPDATESR
24
–
16
–
8
–
0
CHSR
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1136
46.7.18 Base Layer Interrupt Enable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_BASEIER
0xF803804C
Write-only
0x00000000
30
–
22
–
14
–
6
OVR
29
–
21
–
13
–
5
DONE
28
–
20
–
12
–
4
ADD
• DMA: End of DMA Transfer Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• DSCR: Descriptor Loaded Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• ADD: Head Descriptor Loaded Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• DONE: End of List Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• OVR: Overflow Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
27
–
19
–
11
–
3
DSCR
26
–
18
–
10
–
2
DMA
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1137
46.7.19 Base Layer Interrupt Disable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_BASEIDR
0xF8038050
Write-only
0x00000000
30
–
22
–
14
–
6
OVR
29
–
21
–
13
–
5
DONE
28
–
20
–
12
–
4
ADD
• DMA: End of DMA Transfer Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• DSCR: Descriptor Loaded Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• ADD: Head Descriptor Loaded Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• DONE: End of List Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• OVR: Overflow Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
27
–
19
–
11
–
3
DSCR
26
–
18
–
10
–
2
DMA
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1138
46.7.20 Base Layer Interrupt Mask Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_BASEIMR
0xF8038054
Read-only
0x00000000
30
–
22
–
14
–
6
OVR
29
–
21
–
13
–
5
DONE
28
–
20
–
12
–
4
ADD
• DMA: End of DMA Transfer Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• DSCR: Descriptor Loaded Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• ADD: Head Descriptor Loaded Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• DONE: End of List Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• OVR: Overflow Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
27
–
19
–
11
–
3
DSCR
26
–
18
–
10
–
2
DMA
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1139
46.7.21 Base Layer Interrupt Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_BASEISR
0xF8038058
Read-only
0x00000000
30
–
22
–
14
–
6
OVR
29
–
21
–
13
–
5
DONE
28
–
20
–
12
–
4
ADD
27
–
19
–
11
–
3
DSCR
26
–
18
–
10
–
2
DMA
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
• DMA: End of DMA Transfer
When set to one, this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation.
• DSCR: DMA Descriptor Loaded
When set to one, this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation.
• ADD: Head Descriptor Loaded
When set to one, this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation.
• DONE: End of List Detected
When set to one, this flag indicates that an End of List condition has occurred. This flag is reset after a read operation.
• OVR: Overflow Detected
When set to one, this flag indicates that an overflow occurred. This flag is reset after a read operation.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1140
46.7.22 Base Layer Head Register
Name:
Address:
Access:
Reset:
31
LCDC_BASEHEAD
0xF803805C
Read-write
0x00000000
30 29
23
15
7
22
14
6
21
13
5
• HEAD: DMA Head Pointer
The Head Pointer points to a new descriptor.
HEAD
28
20
12
4
HEAD
HEAD
HEAD
27
19
11
3
26
18
10
2
25
17
9
1
–
24
16
8
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1141
46.7.23 Base Layer Address Register
Name:
Address:
Access:
Reset:
31
LCDC_BASEADDR
0xF8038060
Read-write
0x00000000
30 29
23
15
7
22
14
6
21
13
5
• ADDR: DMA Transfer Start Address
Frame buffer base address.
28
20
12
4
ADDR
ADDR
ADDR
ADDR
27
19
11
3
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1142
46.7.24 Base Layer Control Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_BASECTRL
0xF8038064
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
DONEIEN
28
–
20
–
12
–
4
ADDIEN
• DFETCH: Transfer Descriptor Fetch Enable
0: Transfer Descriptor fetch is disabled.
1: Transfer Descriptor fetch is enabled.
• LFETCH: Lookup Table Fetch Enable
0: Lookup Table DMA fetch is disabled.
1: Lookup Tabled DMA fetch is enabled.
• DMAIEN: End of DMA Transfer Interrupt Enable
0: DMA transfer completed interrupt is enabled.
1: DMA transfer completed interrupt is disabled.
• DSCRIEN: Descriptor Loaded Interrupt Enable
0: Transfer descriptor loaded interrupt is enabled.
1: Transfer descriptor loaded interrupt is disabled.
• ADDIEN: Add Head Descriptor to Queue Interrupt Enable
0: Transfer descriptor added to queue interrupt is enabled.
1: Transfer descriptor added to queue interrupt is disabled.
• DONEIEN: End of List Interrupt Enable
0: End of list interrupt is disabled.
1: End of list interrupt is enabled.
27
–
19
–
11
–
3
DSCRIEN
26
–
18
–
10
–
2
DMAIEN
25
–
17
–
9
–
1
LFETCH
24
–
16
–
8
–
0
DFETCH
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1143
46.7.25 Base Layer Next Register
Name:
Address:
Access:
Reset:
31
LCDC_BASENEXT
0xF8038068
Read-write
0x00000000
30 29
23
15
7
22
14
6
21
13
5
28
20
12
4
NEXT
NEXT
NEXT
NEXT
27
19
11
3
• NEXT: DMA Descriptor Next Address
DMA Descriptor next address, this address must be word aligned.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1144
46.7.26 Base Layer Configuration 0 Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_BASECFG0
0xF803806C
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
BLEN
28
–
20
–
12
–
4
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
DLBO
0
–
• BLEN: AHB Burst Length
Value Name
0
1
2
3
AHB_SINGLE
AHB_INCR4
AHB_INCR8
AHB_INCR16
Description
AHB Access is started as soon as there is enough space in the FIFO to store one 32-bit data.
SINGLE, INCR, INCR4, INCR8 and INCR16 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of four
32-bit data. An AHB INCR4 Burst is preferred. SINGLE, INCR and INCR4 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of eight
32-bit data. An AHB INCR8 Burst is preferred. SINGLE, INCR, INCR4 and INCR8 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of sixteen 32-bit data. An AHB INCR16 Burst is preferred. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts can be used. INCR is used for a burst of 2 and 3 beats.
• DLBO: Defined Length Burst Only For Channel Bus Transaction.
0: Undefined length INCR burst is used for a burst of 2 and 3 beats.
1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16).
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1145
46.7.27 Base Layer Configuration 1 Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
LCDC_BASECFG1
0xF8038070
Read-write
0x00000000
30
–
22
–
14
29
–
21
–
13
–
7 6 5
RGBMODE
28
-
20
–
12
4
27
–
19
–
11
–
3
–
• CLUTEN: Color Lookup Table Enable
0: RGB mode is selected.
1: Color lookup table is selected.
• RGBMODE: RGB Input Mode Selection
5
6
3
4
1
2
Value
0
7
8
9
10
11
12
13
Name
12BPP_RGB_444
16BPP_ARGB_4444
16BPP_RGBA_4444
Description
12 bpp RGB 444
16 bpp ARGB 4444
16 bpp RGBA 4444
16BPP_RGB_565
16BPP_TRGB_1555
16 bpp RGB 565
16 bpp TRGB 1555
18BPP_RGB_666 18 bpp RGB 666
18BPP_RGB_666_PACKED 18 bpp RGB 666 PACKED
19BPP_TRGB_1666
19BPP_TRGB_PACKED
19 bpp TRGB 1666
19 bpp TRGB 1666 PACKED
24BPP_RGB_888 24 bpp RGB 888
24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED
25BPP_TRGB_1888
32BPP_ARGB_8888
25 bpp TRGB 1888
32 bpp ARGB 8888
32BPP_RGBA_8888 32 bpp RGBA 8888
2
3
0
1
• CLUTMODE: Color Lookup Table Input Mode Selection
Value Name
1BPP
2BPP
4BPP
8BPP
Description color lookup table mode set to 1 bit per pixel color lookup table mode set to 2 bits per pixel color lookup table mode set to 4 bits per pixel color lookup table mode set to 8 bits per pixel
26
–
18
–
10
–
2
–
25
–
17
–
9
1
–
24
–
16
–
8
CLUTMODE
0
CLUTEN
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1146
46.7.28 Base Layer Configuration 2 Register
Name:
Address:
Access:
Reset:
31
LCDC_BASECFG2
0xF8038074
Read-write
0x00000000
30 29
23
15
7
22
14
6
21
13
5
28 27
XSTRIDE
20
XSTRIDE
19
12 11
XSTRIDE
4 3
XSTRIDE
26
18
10
2
• XSTRIDE: Horizontal Stride
XSTRIDE represents the memory offset, in bytes, between two rows of the image memory.
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1147
46.7.29 Base Layer Configuration 3 Register
Name:
Address:
Access:
Reset:
31
–
23
15
7
LCDC_BASECFG3
0xF8038078
Read-write
0x00000000
14
6
30
–
22
13
5
29
–
21
• RDEF: Red Default
Default Red color when the Base DMA channel is disabled.
• GDEF: Green Default
Default Green color when the Base DMA channel is disabled.
• BDEF: Blue Default
Default Blue color when the Base DMA channel is disabled.
12
4
28
–
20
RDEF
GDEF
BDEF
11
3
27
–
19
10
2
26
–
18
9
1
25
–
17
8
0
24
–
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1148
46.7.30 Base Layer Configuration 4 Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_BASECFG4
0xF803807C
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
REP
1
–
• DMA: Use DMA Data Path
0: The default color is used on the Base Layer.
1: The DMA channel retrieves the pixels stream from the memory.
• REP: Use Replication logic to expand RGB color to 24 bits
0: When the selected pixel depth is less than 24 bpp, the pixel is shifted and least significant bits are set to 0.
1: When the selected pixel depth is less than 24 bpp, the pixel is shifted and the least significant bit replicates the MSB.
24
–
16
–
8
DMA
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1149
46.7.31 Overlay 1 Layer Channel Enable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_OVRCHER1
0xF8038100
Write-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
A2QEN
25
–
17
–
9
–
1
UPDATEEN
24
–
16
–
8
–
0
CHEN
• CHEN: Channel Enable Register
0: No effect.
1: Enable the DMA channel.
• UPDATEEN: Update Overlay Attributes Enable Register
0: No effect.
1: Update windows attributes on the next start of frame.
• A2QEN: Add Head Pointer Enable Register
Write this field to one to add the head pointer to the descriptor list. This field is reset by hardware as soon as the head register is added to the list.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1150
46.7.32 Overlay 1 Layer Channel Disable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_OVRCHDR1
0xF8038104
Write-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
• CHDIS: Channel Disable Register
When set to one, this field disables the layer at the end of the current frame. The frame is completed.
• CHRST: Channel Reset Register
When set to one, this field resets the layer immediately. The frame is aborted.
25
–
17
–
9
–
1
–
24
–
16
–
8
CHRST
0
CHDIS
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1151
46.7.33 Overlay 1 Layer Channel Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_OVRCHSR1
0xF8038108
Read-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
A2QSR
• CHSR: Channel Status Register
When set to one, this field disables the layer at the end of the current frame.
• UPDATESR: Update Overlay Attributes In Progress
When set to one, this bit indicates that the overlay attributes will be updated on the next frame.
• A2QSR: Add to Queue Pending Register
When set to one, this bit indicates that the head pointer is still pending.
25
–
17
–
9
–
1
UPDATESR
24
–
16
–
8
–
0
CHSR
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1152
46.7.34 Overlay 1 Layer Interrupt Enable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_OVRIER1
0xF803810C
Write-only
0x00000000
30
–
22
–
14
–
6
OVR
29
–
21
–
13
–
5
DONE
28
–
20
–
12
–
4
ADD
• DMA: End of DMA Transfer Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• DSCR: Descriptor Loaded Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• ADD: Head Descriptor Loaded Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• DONE: End of List Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• OVR: Overflow Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
27
–
19
–
11
–
3
DSCR
26
–
18
–
10
–
2
DMA
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1153
46.7.35 Overlay 1 Layer Interrupt Disable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_OVRIDR1
0xF8038110
Write-only
0x00000000
30
–
22
–
14
–
6
OVR
29
–
21
–
13
–
5
DONE
28
–
20
–
12
–
4
ADD
• DMA: End of DMA Transfer Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• DSCR: Descriptor Loaded Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• ADD: Head Descriptor Loaded Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• DONE: End of List Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• OVR: Overflow Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
27
–
19
–
11
–
3
DSCR
26
–
18
–
10
–
2
DMA
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1154
46.7.36 Overlay 1 Layer Interrupt Mask Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_OVRIMR1
0xF8038114
Read-only
0x00000000
30
–
22
–
14
–
6
OVR
29
–
21
–
13
–
5
DONE
28
–
20
–
12
–
4
ADD
• DMA: End of DMA Transfer Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• DSCR: Descriptor Loaded Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• ADD: Head Descriptor Loaded Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• DONE: End of List Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• OVR: Overflow Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
27
–
19
–
11
–
3
DSCR
26
–
18
–
10
–
2
DMA
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1155
46.7.37 Overlay 1 Layer Interrupt Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_OVRISR1
0xF8038118
Read-only
0x00000000
30
–
22
–
14
–
6
OVR
29
–
21
–
13
–
5
DONE
28
–
20
–
12
–
4
ADD
27
–
19
–
11
–
3
DSCR
26
–
18
–
10
–
2
DMA
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
• DMA: End of DMA Transfer
When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation.
• DSCR: DMA Descriptor Loaded
When set to one, this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation.
• ADD: Head Descriptor Loaded
When set to one, this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation.
• DONE: End of List Detected Register
When set to one, this flag indicates that an End of List condition has occurred. This flag is reset after a read operation.
• OVR: Overflow Detected
When set to one, this flag indicates that an overflow occurred. This flag is reset after a read operation.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1156
46.7.38 Overlay 1 Layer Head Register
Name:
Address:
Access:
Reset:
31
LCDC_OVRHEAD1
0xF803811C
Read-write
0x00000000
30 29
23
15
7
22
14
6
21
13
5
HEAD
28
20
12
4
HEAD
HEAD
HEAD
27
19
11
3
• HEAD: DMA Head Pointer
The Head Pointer points to a new descriptor.
26
18
10
2
25
17
9
1
–
24
16
8
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1157
46.7.39 Overlay 1 Layer Address Register
Name:
Address:
Access:
Reset:
31
LCDC_OVRADDR1
0xF8038120
Read-write
0x00000000
30 29
23
15
7
22
14
6
21
13
5
• ADDR: DMA Transfer Overlay 1 Address
Overlay 1 frame buffer base address.
28
20
12
4
ADDR
ADDR
ADDR
ADDR
27
19
11
3
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1158
46.7.40 Overlay 1 Layer Control Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_OVRCTRL1
0xF8038124
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
DONEIEN
28
–
20
–
12
–
4
ADDIEN
• DFETCH: Transfer Descriptor Fetch Enable
0: Transfer Descriptor fetch is disabled.
1: Transfer Descriptor fetch is enabled.
• LFETCH: Lookup Table Fetch Enable
0: Lookup Table DMA fetch is disabled.
1: Lookup Tabled DMA fetch is enabled.
• DMAIEN: End of DMA Transfer Interrupt Enable
0: DMA transfer completed interrupt is enabled.
1: DMA transfer completed interrupt is disabled.
• DSCRIEN: Descriptor Loaded Interrupt Enable
0: Transfer descriptor loaded interrupt is enabled.
1: Transfer descriptor loaded interrupt is disabled.
• ADDIEN: Add Head Descriptor to Queue Interrupt Enable
0: Transfer descriptor added to queue interrupt is enabled.
1: Transfer descriptor added to queue interrupt is disabled.
• DONEIEN: End of List Interrupt Enable
0: End of list interrupt is disabled.
1: End of list interrupt is enabled.
27
–
19
–
11
–
3
DSCRIEN
26
–
18
–
10
–
2
DMAIEN
25
–
17
–
9
–
1
LFETCH
24
–
16
–
8
–
0
DFETCH
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1159
46.7.41 Overlay 1 Layer Next Register
Name:
Address:
Access:
Reset:
31
LCDC_OVRNEXT1
0xF8038128
Read-write
0x00000000
30 29
23
15
7
22
14
6
21
13
5
28
20
12
4
NEXT
NEXT
NEXT
NEXT
27
19
11
3
• NEXT: DMA Descriptor Next Address
DMA Descriptor next address, this address must be word aligned.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1160
46.7.42 Overlay 1 Layer Configuration 0 Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_OVR1CFG0
0xF803812C
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
LOCKDIS
5
BLEN
28
–
20
–
12
ROTDIS
4
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
DLBO
0
–
• BLEN: AHB Burst Length
Value Name
0
1
2
3
AHB_SINGLE
AHB_INCR4
AHB_INCR8
AHB_INCR16
Description
AHB Access is started as soon as there is enough space in the FIFO to store one 32-bit data.
SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are preferred. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of four
32-bit data. An AHB INCR4 Burst is preferred. SINGLE, INCR and INCR4 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of eight
32-bit data. An AHB INCR8 Burst is preferred. SINGLE, INCR, INCR4 and INCR8 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of sixteen 32-bit data. An AHB INCR16 Burst is preferred. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts can be used. INCR is used for a burst of 2 and 3 beats.
• DLBO: Defined Length Burst Only for Channel Bus Transaction.
0: Undefined length INCR burst is used for a burst of 2 and 3 beats.
1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16).
• ROTDIS: Hardware Rotation Optimization Disable
0: Rotation optimization is enabled.
1: Rotation optimization is disabled.
• LOCKDIS: Hardware Rotation Lock Disable
0: AHB lock signal is asserted when a rotation is performed.
1: AHB lock signal is cleared when a rotation is performed.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1161
46.7.43 Overlay 1 Layer Configuration 1 Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
LCDC_OVR1CFG1
0xF8038130
Read-write
0x00000000
30
–
22
–
14
–
6
29
–
21
–
13
–
5
28
–
20
–
12
–
4
RGBMODE
27
–
19
–
11
–
3
–
• CLUTEN: Color Lookup Table Enable
0: RGB mode is selected.
1: Color lookup table is selected.
• RGBMODE: RGB Input Mode Selection
5
6
3
4
1
2
Value
0
7
8
9
10
11
12
13
Name
12BPP_RGB_444
16BPP_ARGB_4444
16BPP_RGBA_4444
Description
12 bpp RGB 444
16 bpp ARGB 4444
16 bpp RGBA 4444
16BPP_RGB_565
16BPP_TRGB_1555
16 bpp RGB 565
16 bpp TRGB 1555
18BPP_RGB_666 18 bpp RGB 666
18BPP_RGB_666_PACKED 18 bpp RGB 666 PACKED
19BPP_TRGB_1666
19BPP_TRGB_PACKED
19 bpp TRGB 1666
19 bpp TRGB 1666 PACKED
24BPP_RGB_888 24 bpp RGB 888
24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED
25BPP_TRGB_1888
32BPP_ARGB_8888
25 bpp TRGB 1888
32 bpp ARGB 8888
32BPP_RGBA_8888 32 bpp RGBA 8888
2
3
0
1
• CLUTMODE: Color Lookup table input mode selection
Value Name
1BPP
2BPP
4BPP
8BPP
Description color lookup table mode set to 1 bit per pixel color lookup table mode set to 2 bits per pixel color lookup table mode set to 4 bits per pixel color lookup table mode set to 8 bits per pixel
26
–
18
–
10
–
2
–
25
–
17
–
9
1
–
24
–
16
–
8
CLUTMODE
0
CLUTEN
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1162
46.7.44 Overlay 1 Layer Configuration 2 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_OVR1CFG2
0xF8038134
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
15
–
7
14
–
6
13
–
5
12
–
4
YPOS
XPOS
27
–
19
11
–
3
• XPOS: Horizontal Window Position
Overlay 1 Horizontal window position.
• YPOS: Vertical Window Position
Overlay 1 Vertical window position.
26
18
10
2
25
YPOS
17
9
XPOS
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1163
46.7.45 Overlay 1 Layer Configuration 3 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_OVR1CFG3
0xF8038138
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
15
–
7
14
–
6
13
–
5
12
–
4
YSIZE
27
–
19
11
–
3
XSIZE
• XSIZE: Horizontal Window Size
Overlay 1 window width in pixels. The window width is set to (XSIZE+1).
The following constraint must be met:
≤ PPL
• YSIZE: Vertical Window Size
Overlay 1 window height in pixels. The window height is set to (YSIZE+1).
The following constrain must be met:
≤ RPF
26
18
10
2
25
YSIZE
17
9
XSIZE
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1164
46.7.46 Overlay 1 Layer Configuration 4 Register
Name:
Address:
Access:
Reset:
31
LCDC_OVR1CFG4
0xF803813C
Read-write
0x00000000
30 29 28
23
15
7
22
14
6
21
13
5
27
XSTRIDE
20
XSTRIDE
19
12 11
XSTRIDE
4 3
XSTRIDE
• XSTRIDE: Horizontal Stride
XSTRIDE represents the memory offset, in bytes, between two rows of the image memory.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1165
46.7.47 Overlay 1 Layer Configuration 5 Register
Name:
Address:
Access:
Reset:
31
LCDC_OVR1CFG5
0xF8038140
Read-write
0x00000000
30 29 28
23
15
7
22
14
6
21
13
5
27
PSTRIDE
20
PSTRIDE
19
12 11
PSTRIDE
4 3
PSTRIDE
• PSTRIDE: Pixel Stride
PSTRIDE represents the memory offset, in bytes, between two pixels of the image.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1166
46.7.48 Overlay 1 Layer Configuration 6 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_OVR1CFG6
0xF8038144
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
15
7
14
6
13
5
12
4
RDEF
GDEF
BDEF
11
3
27
–
19
• RDEF: Red Default
Default Red color when the Overlay 1 DMA channel is disabled.
• GDEF: Green Default
Default Green color when the Overlay 1 DMA channel is disabled.
• BDEF: Blue Default
Default Blue color when the Overlay 1 DMA channel is disabled.
10
2
26
–
18
9
1
25
–
17
8
0
24
–
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1167
46.7.49 Overlay 1 Layer Configuration 7 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_OVR1CFG7
0xF8038148
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
15
7
14
6
13
5
12
4
RKEY
GKEY
BKEY
11
3
27
–
19
• RKEY: Red Color Component Chroma Key
Reference Red chroma key used to match the Red color of the current overlay.
• GKEY: Green Color Component Chroma Key
Reference Green chroma key used to match the Green color of the current overlay.
• BKEY: Blue Color Component Chroma Key
Reference Blue chroma key used to match the Blue color of the current overlay.
10
2
26
–
18
9
1
25
–
17
8
0
24
–
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1168
46.7.50 Overlay 1 Layer Configuration 8 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_OVR1CFG8
0xF803814C
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
15
7
14
6
13
5
RMASK
12
GMASK
11
4 3
BMASK
27
–
19
• RMASK: Red Color Component Chroma Key Mask
Red Mask used when the compare function is used. If a bit is set then this bit is compared.
• GMASK: Green Color Component Chroma Key Mask
Green Mask used when the compare function is used. If a bit is set then this bit is compared.
• BMASK: Blue Color Component Chroma Key Mask
Blue Mask used when the compare function is used. If a bit is set then this bit is compared.
10
2
26
–
18
9
1
25
–
17
8
0
24
–
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1169
46.7.51 Overlay1 Layer Configuration 9 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_OVR1CFG9
0xF8038150
Read-write
0x00000000
30
–
22
29
–
21
15
–
7
OVR
14
–
6
LAEN
13
–
5
GAEN
28
–
20
12
–
4
REVALPHA
GA
27
–
19
11
–
3
ITER
• CRKEY: Blender Chroma Key Enable
0: Chroma key matching is disabled.
1: Chroma key matching is enabled.
• INV: Blender Inverted Blender Output Enable
0: Iterated pixel is the blended pixel.
1: Iterated pixel is the inverted pixel.
• ITER2BL: Blender Iterated Color Enable
0: Final adder stage operand is set to 0.
1: Final adder stage operand is set to the iterated pixel value.
• ITER: Blender Use Iterated Color
0: Pixel difference is set to 0.
1: Pixel difference is set to the iterated pixel value.
• REVALPHA: Blender Reverse Alpha
0: Pixel difference is multiplied by alpha.
1: Pixel difference is multiplied by 1 - alpha.
• GAEN: Blender Global Alpha Enable
0: Global alpha blending coefficient is disabled.
1: Global alpha blending coefficient is enabled.
• LAEN: Blender Local Alpha Enable
0: Local alpha blending coefficient is disabled.
1: Local alpha blending coefficient is enabled.
• OVR: Blender Overlay Layer Enable
0: Overlay pixel color is set to the default overlay pixel color.
1: Overlay pixel color is set to the DMA channel pixel color.
26
–
18
10
DSTKEY
2
ITER2BL
25
–
17
9
REP
1
INV
24
–
16
8
DMA
0
CRKEY
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1170
• DMA: Blender DMA Layer Enable
0: The default color is used on the Overlay 1 Layer.
1: The DMA channel retrieves the pixels stream from the memory.
• REP: Use Replication logic to expand RGB color to 24 bits
0: When the selected pixel depth is less than 24 bpp, the pixel is shifted and least significant bits are set to 0.
1: When the selected pixel depth is less than 24 bpp, the pixel is shifted and the least significant bit replicates the MSB.
• DSTKEY: Destination Chroma Keying
0: Source Chroma keying is enabled.
1: Destination Chroma keying is used.
• GA: Blender Global Alpha
Global alpha blender for the current layer.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1171
46.7.52 High End Overlay Layer Channel Enable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HEOCHER
0xF8038280
Write-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
A2QEN
25
–
17
–
9
–
1
UPDATEEN
24
–
16
–
8
–
0
CHEN
• CHEN: Channel Enable Register
0: No effect.
1: Enable the DMA channel.
• UPDATEEN: Update Overlay Attributes Enable Register
0: No effect.
1: Update windows attributes on the next start of frame.
• A2QEN: Add Head Pointer Enable Register
Write this field to one to add the head pointer to the descriptor list. This field is reset by hardware as soon as the head register is added to the list.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1172
46.7.53 High End Overlay Layer Channel Disable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HEOCHDR
0xF8038284
Write-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
• CHDIS: Channel Disable Register
When set to one, this field disables the layer at the end of the current frame. The frame is completed.
• CHRST: Channel Reset Register
When set to one, this field resets the layer immediately. The frame is aborted.
25
–
17
–
9
–
1
–
24
–
16
–
8
CHRST
0
CHDIS
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1173
46.7.54 High End Overlay Layer Channel Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HEOCHSR
0xF8038288
Read-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
A2QSR
• CHSR: Channel Status Register
When set to one, this bit indicates that the channel is enabled.
• UPDATESR: Update Overlay Attributes In Progress
When set to one, this bit indicates that the overlay attributes will be updated on the next frame.
• A2QSR: Add To Queue Pending Register
When set to one, this bit indicates that the head pointer is still pending.
25
–
17
–
9
–
1
UPDATESR
24
–
16
–
8
–
0
CHSR
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1174
46.7.55 High End Overlay Layer Interrupt Enable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HEOIER
0xF803828C
Write-only
0x00000000
30
–
22
VOVR
14
UOVR
6
OVR
29
–
21
VDONE
13
UDONE
5
DONE
28
–
20
VADD
12
UADD
4
ADD
27
–
19
VDSCR
11
UDSCR
3
DSCR
26
–
18
VDMA
10
UDMA
2
DMA
• DMA: End of DMA Transfer Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• DSCR: Descriptor Loaded Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• ADD: Head Descriptor Loaded Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• DONE: End of List Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• OVR: Overflow Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• UDMA: End of DMA Transfer for U or UV Chrominance Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• UDSCR: Descriptor Loaded for U or UV Chrominance Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• UADD: Head Descriptor Loaded for U or UV Chrominance Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1175
• UDONE: End of List for U or UV Chrominance Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• UOVR: Overflow for U or UV Chrominance Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• VDMA: End of DMA for V Chrominance Transfer Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• VDSCR: Descriptor Loaded for V Chrominance Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• VADD: Head Descriptor Loaded for V Chrominance Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• VDONE: End of List for V Chrominance Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• VOVR: Overflow for V Chrominance Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1176
46.7.56 High End Overlay Layer Interrupt Disable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HEOIDR
0xF8038290
Write-only
0x00000000
30
–
22
VOVR
14
UOVR
6
OVR
29
–
21
VDONE
13
UDONE
5
DONE
28
–
20
VADD
12
UADD
4
ADD
27
–
19
VDSCR
11
UDSCR
3
DSCR
26
–
18
VDMA
10
UDMA
2
DMA
25
–
17
–
9
–
1
–
• DMA: End of DMA Transfer Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• DSCR: Descriptor Loaded Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• ADD: Head Descriptor Loaded Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• DONE: End of List Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• OVR: Overflow Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• UDMA: End of DMA Transfer for U or UV Chrominance Component Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• UDSCR: Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• UADD: Head Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
24
–
16
–
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1177
• UDONE: End of List Interrupt for U or UV Chrominance Component Disable Register
0: No effect.
1: Interrupt source is disabled.
• UOVR: Overflow Interrupt for U or UV Chrominance Component Disable Register
0: No effect.
1: Interrupt source is disabled.
• VDMA: End of DMA Transfer for V Chrominance Component Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• VDSCR: Descriptor Loaded for V Chrominance Component Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• VADD: Head Descriptor Loaded for V Chrominance Component Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• VDONE: End of List for V Chrominance Component Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• VOVR: Overflow for V Chrominance Component Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1178
46.7.57 High End Overlay Layer Interrupt Mask Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HEOIMR
0xF8038294
Read-only
0x00000000
30
–
22
VOVR
14
UOVR
6
OVR
29
–
21
VDONE
13
UDONE
5
DONE
28
–
20
VADD
12
UADD
4
ADD
27
–
19
VDSCR
11
UDSCR
3
DSCR
26
–
18
VDMA
10
UDMA
2
DMA
• DMA: End of DMA Transfer Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• DSCR: Descriptor Loaded Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• ADD: Head Descriptor Loaded Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• DONE: End of List Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• OVR: Overflow Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• UDMA: End of DMA Transfer for U or UV Chrominance Component Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• UDSCR: Descriptor Loaded for U or UV Chrominance Component Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• UADD: Head Descriptor Loaded for U or UV Chrominance Component Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1179
• UDONE: End of List for U or UV Chrominance Component Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• UOVR: Overflow for U Chrominance Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• VDMA: End of DMA Transfer for V Chrominance Component Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• VDSCR: Descriptor Loaded for V Chrominance Component Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• VADD: Head Descriptor Loaded for V Chrominance Component Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• VDONE: End of List for V Chrominance Component Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• VOVR: Overflow for V Chrominance Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1180
46.7.58 High End Overlay Layer Interrupt Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HEOISR
0xF8038298
Read-only
0x00000000
30
–
22
VOVR
14
UOVR
6
OVR
29
–
21
VDONE
13
UDONE
5
DONE
28
–
20
VADD
12
UADD
4
ADD
27
–
19
VDSCR
11
UDSCR
3
DSCR
26
–
18
VDMA
10
UDMA
2
DMA
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
• DMA: End of DMA Transfer
When set to one, this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation.
• DSCR: DMA Descriptor Loaded
When set to one, this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation.
• ADD: Head Descriptor Loaded
When set to one, this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation.
• DONE: End of List Detected
When set to one, this flag indicates that an End of List condition has occurred. This flag is reset after a read operation.
• OVR: Overflow Detected
When set to one, this flag indicates that an overflow occurred. This flag is reset after a read operation.
• UDMA: End of DMA Transfer for U Component
When set to one, this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation.
• UDSCR: DMA Descriptor Loaded for U Component
When set to one, this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation.
• UADD: Head Descriptor Loaded for U Component
When set to on, this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation.
• UDONE: End of List Detected for U Component
When set to one, this flag indicates that an End of List condition has occurred. This flag is reset after a read operation.
• UOVR: Overflow Detected for U Component
When set to one, this flag indicates that an overflow occurred. This flag is reset after a read operation.
• VDMA: End of DMA Transfer for V Component
When set to one, this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1181
• VDSCR: DMA Descriptor Loaded for V Component
When set to one, this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation.
• VADD: Head Descriptor Loaded for V Component
When set to one, this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation.
• VDONE: End of List Detected for V Component
When set to one, this flag indicates that an End of List condition has occurred. This flag is reset after a read operation.
• VOVR: Overflow Detected for V Component
When set to one, this flag indicates that an overflow occurred. This flag is reset after a read operation.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1182
46.7.59 High End Overlay Layer Head Register
Name:
Address:
Access:
Reset:
31
LCDC_HEOHEAD
0xF803829C
Read-write
0x00000000
30 29 28
23
15
7
22
14
6
21
13
5
20
12
4
HEAD
HEAD
HEAD
HEAD
27
19
11
3
• HEAD: DMA Head Pointer
The Head Pointer points to a new descriptor.
26
18
10
2
25
17
9
1
–
24
16
8
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1183
46.7.60 High End Overlay Layer Address Register
Name:
Address:
Access:
Reset:
31
LCDC_HEOADDR
0xF80382A0
Read-write
0x00000000
30 29 28
23
15
7
22
14
6
21
13
5
20
12
4
ADDR
ADDR
ADDR
ADDR
27
19
11
3
• ADDR: DMA Transfer start Address
Frame Buffer Base Address.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1184
46.7.61 High End Overlay Layer Control Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HEOCTRL
0xF80382A4
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
DONEIEN
28
–
20
–
12
–
4
ADDIEN
• DFETCH: Transfer Descriptor Fetch Enable
0: Transfer Descriptor fetch is disabled.
1: Transfer Descriptor fetch is enabled.
• LFETCH: Lookup Table Fetch Enable
0: Lookup Table DMA fetch is disabled.
1: Lookup Tabled DMA fetch is enabled.
• DMAIEN: End of DMA Transfer Interrupt Enable
0: DMA transfer completed interrupt is enabled.
1: DMA transfer completed interrupt is disabled.
• DSCRIEN: Descriptor Loaded Interrupt Enable
0: Transfer descriptor loaded interrupt is enabled.
1: Transfer descriptor loaded interrupt is disabled.
• ADDIEN: Add Head Descriptor to Queue Interrupt Enable
0: Transfer descriptor added to queue interrupt is enabled.
1: Transfer descriptor added to queue interrupt is disabled.
• DONEIEN: End of List Interrupt Enable
0: End of list interrupt is disabled.
1: End of list interrupt is enabled.
27
–
19
–
11
–
3
DSCRIEN
26
–
18
–
10
–
2
DMAIEN
25
–
17
–
9
–
1
LFETCH
24
–
16
–
8
–
0
DFETCH
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1185
46.7.62 High End Overlay Layer Next Register
Name:
Address:
Access:
Reset:
31
LCDC_HEONEXT
0xF80382A8
Read-write
0x00000000
30 29 28
23
15
7
22
14
6
21
13
5
20
12
4
NEXT
NEXT
NEXT
NEXT
27
19
11
3
• NEXT: DMA Descriptor Next Address
DMA Descriptor next address, this address must be word aligned.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1186
46.7.63 High End Overlay Layer U-UV Head Register
Name:
Address:
Access:
Reset:
31
LCDC_HEOUHEAD
0xF80382AC
Read-write
0x00000000
30 29 28
UHEAD
23 22 21 20
UHEAD
15 14 13 12
UHEAD
7 6 5 4
UHEAD
27
19
11
3
• UHEAD: DMA Head Pointer
The Head Pointer points to a new descriptor.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1187
46.7.64 High End Overlay Layer U-UV Address Register
Name:
Address:
Access:
Reset:
31
LCDC_HEOUADDR
0xF80382B0
Read-write
0x00000000
30 29 28
UADDR
23 22 21 20
UADDR
15 14 13 12
UADDR
7 6 5 4
UADDR
27
19
11
3
• UADDR: DMA Transfer Start Address for U or UV Chrominance
U or UV frame buffer address.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1188
46.7.65 High End Overlay Layer U-UV Control Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HEOUCTRL
0xF80382B4
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
UDONEIEN
28
–
20
–
12
–
4
UADDIEN
• UDFETCH: Transfer Descriptor Fetch Enable
0: Transfer Descriptor fetch is disabled.
1: Transfer Descriptor fetch is enabled.
• UDMAIEN: End of DMA Transfer Interrupt Enable
0: DMA transfer completed interrupt is enabled.
1: DMA transfer completed interrupt is disabled.
• UDSCRIEN: Descriptor Loaded Interrupt Enable
0: Transfer descriptor loaded interrupt is enabled.
1: Transfer descriptor loaded interrupt is disabled.
• UADDIEN: Add Head Descriptor to Queue Interrupt Enable
0: Transfer descriptor added to queue interrupt is enabled.
1: Transfer descriptor added to queue interrupt is disabled.
• UDONEIEN: End of List Interrupt Enable
0: End of list interrupt is disabled.
1: End of list interrupt is enabled.
27
–
19
–
11
–
3
UDSCRIEN
26
–
18
–
10
–
2
UDMAIEN
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
UDFETCH
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1189
46.7.66 High End Overlay Layer U-UV Next Register
Name:
Address:
Access:
Reset:
31
LCDC_HEOUNEXT
0xF80382B8
Read-write
0x00000000
30 29 28
UNEXT
23 22 21 20
UNEXT
15 14 13 12
UNEXT
7 6 5 4
UNEXT
27
19
11
3
• UNEXT: DMA Descriptor Next Address
DMA Descriptor next address, this address must be word aligned.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1190
46.7.67 High End Overlay Layer V Head Register
Name:
Address:
Access:
Reset:
31
LCDC_HEOVHEAD
0xF80382BC
Read-write
0x00000000
30 29 28
23
15
22
14
21
13
27
20
VHEAD
VHEAD
19
12 11
VHEAD
7 6 5 4 3
VHEAD
• VHEAD: DMA Head Pointer
The Head Pointer points to a new descriptor.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1191
46.7.68 High End Overlay Layer V Address Register
Name:
Address:
Access:
Reset:
31
LCDC_HEOVADDR
0xF80382C0
Read-write
0x00000000
30 29 28
VADDR
23 22 21 20
VADDR
15 14 13 12
VADDR
7 6 5 4
VADDR
27
19
11
3
• VADDR: DMA Transfer Start Address for V Chrominance
Frame Buffer Base Address.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1192
46.7.69 High End Overlay Layer V Control Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HEOVCTRL
0xF80382C4
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
VDONEIEN
28
–
20
–
12
–
4
VADDIEN
• VDFETCH: Transfer Descriptor Fetch Enable
0: Transfer Descriptor fetch is disabled.
1: Transfer Descriptor fetch is enabled.
• VDMAIEN: End of DMA Transfer Interrupt Enable
0: DMA transfer completed interrupt is enabled.
1: DMA transfer completed interrupt is disabled.
• VDSCRIEN: Descriptor Loaded Interrupt Enable
0: Transfer descriptor loaded interrupt is enabled.
1: Transfer descriptor loaded interrupt is disabled.
• VADDIEN: Add Head Descriptor to Queue Interrupt Enable
0: Transfer descriptor added to queue interrupt is enabled.
1: Transfer descriptor added to queue interrupt is disabled.
• VDONEIEN: End of List Interrupt Enable
0: End of list interrupt is disabled.
1: End of list interrupt is enabled.
27
–
19
–
11
–
3
VDSCRIEN
26
–
18
–
10
–
2
VDMAIEN
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
VDFETCH
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1193
46.7.70 High End Overlay Layer V Next Register
Name:
Address:
Access:
Reset:
31
LCDC_HEOVNEXT
0xF80382C8
Read-write
0x00000000
30 29 28
23
15
7
22
14
6
21
13
5
20
12
4
27
VNEXT
VNEXT
19
11
VNEXT
3
VNEXT
• VNEXT: DMA Descriptor Next Address
Frame Buffer Base Address.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1194
46.7.71 High End Overlay Layer Configuration 0 Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
LCDC_HEOCFG0
0xF80382CC
Read-write
0x00000000
BLENUV
30
–
22
–
14
–
6
29
–
21
–
13
LOCKDIS
5
BLEN
28
–
20
–
12
ROTDIS
4
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
DLBO
0
–
• BLEN: AHB Burst Length
Value
0
1
2
3
Name
AHB_SINGLE
AHB_INCR4
AHB_INCR8
AHB_INCR16
Description
AHB Access is started as soon as there is enough space in the FIFO to store one 32-bit data. SINGLE,
INCR, INCR4, INCR8 and INCR16 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of four 32-bit data. An AHB INCR4 Burst is preferred. SINGLE, INCR and INCR4 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of eight 32-bit data. An AHB INCR8 Burst is preferred. SINGLE, INCR, INCR4 and INCR8 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of sixteen
32-bit data. An AHB INCR16 Burst is preferred. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts can be used. INCR is used for a burst of 2 and 3 beats.
• BLENUV: AHB Burst Length for U-V Channel
Value
0
1
2
3
Name
AHB_SINGLE
AHB_INCR4
AHB_INCR8
AHB_INCR16
Description
AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR,
INCR4, INCR8 and INCR16 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of four 32-bit data. An AHB INCR4 Burst is preferred. SINGLE, INCR and INCR4 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An
AHB INCR8 Burst is preferred. SINGLE, INCR, INCR4 and INCR8 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of sixteen
32-bit data. An AHB INCR16 Burst is preferred. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts can be used. INCR is used for a burst of 2 and 3 beats.
• DLBO: Defined Length Burst Only For Channel Bus Transaction
0: Undefined length INCR burst is used for a burst of 2 and 3 beats.
1: Only defined length burst is used (SINGLE, INCR4, INCR8 and INCR16).
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1195
• ROTDIS: Hardware Rotation Optimization Disable
0: Rotation optimization is enabled.
1: Rotation optimization is disabled.
• LOCKDIS: Hardware Rotation Lock Disable
0: AHB lock signal is asserted when a rotation is performed.
1: AHB lock signal is cleared when a rotation is performed.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1196
46.7.72 High End Overlay Layer Configuration 1 Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
LCDC_HEOCFG1
0xF80382D0
Read-write
0x00000000
30
–
22
–
14
29
–
21
–
13
28
–
20
–
12
YUVMODE
7 6 5 4
RGBMODE
• CLUTEN: Color Lookup Table Enable
0: RGB mode is selected.
1: Color Lookup table is selected.
• YUVEN: YUV Color Space Enable
0: Color space is RGB
1: Color Space is YUV
• RGBMODE: RGB input mode selection
7
8
9
11
12
13
3
4
5
1
2
Value
0
6
10
Name
12BPP_RGB_444
16BPP_ARGB_4444
16BPP_RGBA_4444
16BPP_RGB_565
16BPP_TRGB_1555
18BPP_RGB_666
18BPP_RGB_666_PACKE
D
19BPP_TRGB_1666
19BPP_TRGB_PACKED
24BPP_RGB_888
24BPP_RGB_888_PACKE
D
25BPP_TRGB_1888
32BPP_ARGB_8888
32BPP_RGBA_8888
Description
12 bpp RGB 444
16 bpp ARGB 4444
16 bpp RGBA 4444
16 bpp RGB 565
16 bpp TRGB 1555
18 bpp RGB 666
18 bpp RGB 666 PACKED
19 bpp TRGB 1666
19 bpp TRGB 1666 PACKED
24 bpp RGB 888
24 bpp RGB 888 PACKED
25 bpp TRGB 1888
32 bpp ARGB 8888
32 bpp RGBA 8888
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
24
–
17 16
YUV422SWP YUV422ROT
9 8
CLUTMODE
1
YUVEN
0
CLUTEN
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1197
2
3
0
1
• CLUTMODE: Color Lookup table input mode selection
Value Name
1BPP
2BPP
4BPP
8BPP
Description color lookup table mode set to 1 bit per pixel color lookup table mode set to 2 bits per pixel color lookup table mode set to 4 bits per pixel color lookup table mode set to 8 bits per pixel
• YUVMODE: YUV input mode selection
4
5
6
7
8
1
2
3
Value
0
Name
32BPP_AYCBCR
16BPP_YCBCR_MODE0
16BPP_YCBCR_MODE1
16BPP_YCBCR_MODE2
Description
32 bpp AYCbCr 444
16 bpp Cr(n)Y(n+1)Cb(n)Y(n) 422
16 bpp Y(n+1)Cr(n)Y(n)Cb(n) 422
16 bpp Cb(n)Y(+1)Cr(n)Y(n) 422
16BPP_YCBCR_MODE3 16 bpp Y(n+1)Cb(n)Y(n)Cr(n) 422
16BPP_YCBCR_SEMIPLANAR 16 bpp Semiplanar 422 YCbCr
16BPP_YCBCR_PLANAR 16 bpp Planar 422 YCbCr
12BPP_YCBCR_SEMIPLANAR 12 bpp Semiplanar 420 YCbCr
12BPP_YCBCR_PLANAR 12 bpp Planar 420 YCbCr
• YUV422ROT: YUV 4:2:2 Rotation
When set to one this bit indicates that the Chroma Upsampling kernel is configured to use the 4:2:2 Rotation Algorithm.
• YUV422SWP: YUV 4:2:2 SWAP
When set to one the Y component of the YUV 4:2:2 packed memory data stream is swapped.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1198
46.7.73 High End Overlay Layer Configuration 2 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_HEOCFG2
0xF80382D4
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
YPOS
15
–
7
14
–
6
13
–
5
12
–
4
XPOS
27
–
19
11
–
3
• XPOS: Horizontal Window Position
High End Overlay Horizontal window position.
• YPOS: Vertical Window Position
High End Overlay Vertical window position.
26
18
10
2
25
YPOS
17
9
XPOS
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1199
46.7.74 High End Overlay Layer Configuration 3 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_HEOCFG3
0xF80382D8
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
YSIZE
15
–
7
14
–
6
13
–
5
12
–
4
XSIZE
27
–
19
11
–
3
• XSIZE: Horizontal Window Size
High End Overlay window width in pixels. The window width is set to (XSIZE+1).
The following constraint must be met:
≤ PPL
• YSIZE: Vertical Window Size
High End Overlay window height in pixels. The window height is set to (YSIZE+1).
The following constrain must be met:
≤ RPF
26
18
10
2
25
YSIZE
17
9
XSIZE
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1200
46.7.75 High End Overlay Layer Configuration 4 Register
Name:
Address:
Access:
Reset:
15
–
7
31
–
23
LCDC_HEOCFG4
0xF80382DC
Read-write
0x00000000
14
–
6
30
–
22
13
–
5
29
–
21
28
–
20
YMEM_SIZE
12
–
4
XMEM_SIZE
11
–
3
27
–
19
• XMEM_SIZE: Horizontal image Size in Memory
High End Overlay image width in pixels. The image width is set to (XMEM_SIZE+1).
• YMEM_SIZE: Vertical image Size in Memory
High End Overlay image height in pixels. The image height is set to (YMEM_SIZE+1).
26
18
10
2
25
YMEM_SIZE
17
9
XMEM_SIZE
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1201
46.7.76 High End Overlay Layer Configuration 5 Register
Name:
Address:
Access:
Reset:
31
LCDC_HEOCFG5
0xF80382E0
Read-write
0x00000000
30 29 28
XSTRIDE
23 22 21 20
XSTRIDE
15 14 13 12
XSTRIDE
7 6 5 4
XSTRIDE
27
19
11
3
• XSTRIDE: Horizontal Stride
XSTRIDE represents the memory offset, in bytes, between two rows of the image memory.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1202
46.7.77 High End Overlay Layer Configuration 6 Register
Name:
Address:
Access:
Reset:
31
LCDC_HEOCFG6
0xF80382E4
Read-write
0x00000000
30 29 28
PSTRIDE
23 22 21 20
PSTRIDE
15 14 13 12
PSTRIDE
7 6 5 4
PSTRIDE
27
19
11
3
• PSTRIDE: Pixel Stride
PSTRIDE represents the memory offset, in bytes, between two pixels of the image memory.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1203
46.7.78 High End Overlay Layer Configuration 7 Register
Name:
Address:
Access:
Reset:
31
23
15
7
LCDC_HEOCFG7
0xF80382E8
Read-write
0x00000000
30
22
14
6
29
21
13
5
28 27
20
UVXSTRIDE
12
UVXSTRIDE
19
11
UVXSTRIDE
4 3
UVXSTRIDE
26
18
10
2
• UVXSTRIDE: UV Horizontal Stride
UVXSTRIDE represents the memory offset, in bytes, between two rows of the image memory.
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1204
46.7.79 High End Overlay Layer Configuration 8 Register
Name:
Address:
Access:
Reset:
31
23
15
7
LCDC_HEOCFG8
0xF80382EC
Read-write
0x00000000
30
22
14
6
29
21
13
5
28 27
20
UVPSTRIDE
12
UVPSTRIDE
19
11
UVPSTRIDE
4 3
UVPSTRIDE
26
18
10
2
• UVPSTRIDE: UV Pixel Stride
UVPSTRIDE represents the memory offset, in bytes, between two pixels of the image memory.
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1205
46.7.80 High End Overlay Layer Configuration 9 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_HEOCFG9
0xF80382F0
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
RDEF
15 14 13 12
GDEF
7 6 5 4
BDEF
11
3
27
–
19
• RDEF: Red Default
Default Red color when the High End Overlay DMA channel is disabled.
• GDEF: Green Default
Default Green color when the High End Overlay DMA channel is disabled.
• BDEF: Blue Default
Default Blue color when the High End Overlay DMA channel is disabled.
10
2
26
–
18
9
1
25
–
17
8
0
24
–
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1206
46.7.81 High End Overlay Layer Configuration 10 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_HEOCFG10
0xF80382F4
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
RKEY
15 14 13 12
GKEY
7 6 5 4
BKEY
11
3
27
–
19
• RKEY: Red Color Component Chroma Key
Reference Red chroma key used to match the Red color of the current overlay.
• GKEY: Green Color Component Chroma Key
Reference Green chroma key used to match the Green color of the current overlay.
• BKEY: Blue Color Component Chroma Key
Reference Blue chroma key used to match the Blue color of the current overlay.
10
2
26
–
18
9
1
25
–
17
8
0
24
–
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1207
46.7.82 High End Overlay Layer Configuration 11 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_HEOCFG11
0xF80382F8
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
RMASK
15 14 13 12
GMASK
7 6 5 4
BMASK
27
–
19
11
3
• RMASK: Red Color Component Chroma Key Mask
Red Mask used when the compare function is used. If a bit is set then this bit is compared.
• GMASK: Green Color Component Chroma Key Mask
Green Mask used when the compare function is used. If a bit is set then this bit is compared.
• BMASK: Blue Color Component Chroma Key Mask
Blue Mask used when the compare function is used. If a bit is set then this bit is compared.
10
2
26
–
18
9
1
25
–
17
8
0
24
–
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1208
46.7.83 High End Overlay Layer Configuration 12 Register
Name:
Address:
Access:
Reset:
31
–
23
15
–
7
OVR
LCDC_HEOCFG12
0xF80382FC
Read-write
0x00000000
30
–
22
14
–
6
LAEN
29
–
21
13
–
5
GAEN
28
–
20
12
VIDPRI
4
REVALPHA
GA
27
–
19
11
–
3
ITER
• CRKEY: Blender Chroma Key Enable
0: Chroma key matching is disabled.
1: Chroma key matching is enabled.
• INV: Blender Inverted Blender Output Enable
0: Iterated pixel is the blended pixel.
1: Iterated pixel is the inverted pixel.
• ITER2BL: Blender Iterated Color Enable
0: Final adder stage operand is set to 0.
1: Final adder stage operand is set to the iterated pixel value.
• ITER: Blender Use Iterated Color
0: Pixel difference is set to 0.
1: Pixel difference is set to the iterated pixel value.
• REVALPHA: Blender Reverse Alpha
0: Pixel difference is multiplied by alpha.
1: Pixel difference is multiplied by 1 - alpha.
• GAEN: Blender Global Alpha Enable
0: Global alpha blending coefficient is disabled.
1: Global alpha blending coefficient is enabled.
• LAEN: Blender Local Alpha Enable
0: Local alpha blending coefficient is disabled.
1: Local alpha blending coefficient is enabled.
• OVR: Blender Overlay Layer Enable
0: Overlay pixel color is set to the default overlay pixel color.
1: Overlay pixel color is set to the DMA channel pixel color.
26
–
18
10
DSTKEY
2
ITER2BL
25
–
17
9
REP
1
INV
24
–
16
8
DMA
0
CRKEY
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1209
• DMA: Blender DMA Layer Enable
0: The default color is used on the Overlay 1 Layer.
1: The DMA channel retrieves the pixels stream from the memory.
• REP: Use Replication logic to expand RGB color to 24 bits
0: When the selected pixel depth is less than 24 bpp the pixel is shifted and least significant bits are set to 0.
1: When the selected pixel depth is less than 24 bpp the pixel is shifted and the least significant bit replicates the MSB.
• DSTKEY: Destination Chroma Keying
0: Source Chroma keying is enabled.
1: Destination Chroma keying is used.
• VIDPRI: Video Priority
0: HEO layer is located below Overlay 1.
1: HEO layer is located above Overlay 1.
• GA: Blender Global Alpha
Global alpha blender for the current layer.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1210
46.7.84 High End Overlay Layer Configuration 13 Register
Name:
Address:
Access:
Reset:
31
SCALEN
23
LCDC_HEOCFG13
0xF8038300
Read-write
0x00000000
30
–
22
29
–
21
28
20
YFACTOR
15
–
7
14
–
6
13
–
5
12
4
XFACTOR
27
19
11
3
• SCALEN: Hardware Scaler Enable
0: Scaler is disabled
1: Scaler is enabled.
• YFACTOR: Vertical Scaling Factor
Scaler Vertical Factor.
• XFACTOR: Horizontal Scaling Factor
Scaler Horizontal Factor.
26
YFACTOR
18
10
XFACTOR
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1211
46.7.85 High End Overlay Layer Configuration 14 Register
Name:
Address:
Access:
Reset:
31
–
23
15
LCDC_HEOCFG14
0xF8038304
Read-write
0x00000000
30
CSCYOFF
22
CSCRV
14
29
21
13
28
20
12
CSCRU
7 6 5 4
CSCRY
27
19
11
3
CSCRV
26
18
10
2
CSCRU
25
17
9
1
CSCRY
24
16
8
0
• CSCRY: Color Space Conversion Y coefficient for Red Component 1:2:7 format
Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits.
• CSCRU: Color Space Conversion U coefficient for Red Component 1:2:7 format
Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits.
• CSCRV: Color Space Conversion V coefficient for Red Component 1:2:7 format
Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits.
• CSCYOFF: Color Space Conversion Offset
0: Offset is set to 0.
1: Offset is set to 16.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1212
46.7.86 High End Overlay Layer Configuration 15 Register
Name:
Address:
Access:
Reset:
31
–
23
15
LCDC_HEOCFG15
0xF8038308
Read-write
0x00000000
30
CSCUOFF
22
CSCGV
14
29
21
13
28
20
12
CSCGU
7 6 5 4
CSCGY
27
19
11
3
CSCGV
26
18
10
2
CSCGU
25
17
9
1
CSCGY
24
16
8
0
• CSCGY: Color Space Conversion Y Coefficient for Green Component 1:2:7 Format
Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits.
• CSCGU: Color Space Conversion U Coefficient for Green Component 1:2:7 Format
Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits.
• CSCGV: Color Space Conversion V Coefficient for Green Component 1:2:7 Format
Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits.
• CSCUOFF: Color Space Conversion Offset
0: Offset is set to 0.
1: Offset is set to 128.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1213
46.7.87 High End Overlay Layer Configuration 16 Register
Name:
Address:
Access:
Reset:
31
–
23
15
LCDC_HEOCFG16
0xF803830C
Read-write
0x00000000
30
CSCVOFF
22
CSCBV
14
29
21
13
28
20
12
CSCBU
7 6 5 4
CSCBY
27
19
11
3
CSCBV
26
18
10
2
CSCBU
25
17
9
1
CSCBY
24
16
8
0
• CSCBY: Color Space Conversion Y Coefficient for Blue Component 1:2:7 Format
Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits.
• CSCBU: Color Space Conversion U Coefficient for Blue Component 1:2:7 Format
Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits.
• CSCBV: Color Space Conversion V Coefficient for Blue Component 1:2:7 Format
Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits.
• CSCVOFF: Color Space Conversion Offset
0: Offset is set to 0.
1: Offset is set to 128.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1214
46.7.88 Hardware Cursor Layer Channel Enable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HCRCHER
0xF8038340
Write-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
A2QEN
25
–
17
–
9
–
1
UPDATEEN
24
–
16
–
8
–
0
CHEN
• CHEN: Channel Enable Register
0: No effect.
1: Enable the DMA channel.
• UPDATEEN: Update Overlay Attributes Enable Register
0: No effect.
1: Update windows attributes on the next start of frame.
• A2QEN: Add Head Pointer Enable Register
Write this field to one to add the head pointer to the descriptor list. This field is reset by hardware as soon as the head register is added to the list.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1215
46.7.89 Hardware Cursor Layer Channel Disable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HCRCHDR
0xF8038344
Write-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
• CHDIS: Channel Disable Register
When set to one, this field disables the layer at the end of the current frame. The frame is completed.
• CHRST: Channel Reset Register
When set to one, this field resets the layer immediately. The frame is aborted.
25
–
17
–
9
–
1
–
24
–
16
–
8
CHRST
0
CHDIS
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1216
46.7.90 Hardware Cursor Layer Channel Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HCRCHSR
0xF8038348
Read-only
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
A2QSR
• CHSR: Channel Status Register
When set to one, this field disables the layer at the end of the current frame.
• UPDATESR: Update Overlay Attributes In Progress
When set to one, this bit indicates that the overlay attributes will be updated on the next frame.
• A2QSR: Add To Queue Pending Register
When set to one, this bit indicates that the head pointer is still pending.
25
–
17
–
9
–
1
UPDATESR
24
–
16
–
8
–
0
CHSR
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1217
46.7.91 Hardware Cursor Layer Interrupt Enable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HCRIER
0xF803834C
Write-only
0x00000000
30
–
22
–
14
–
6
OVR
29
–
21
–
13
–
5
DONE
28
–
20
–
12
–
4
ADD
• DMA: End of DMA Transfer Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• DSCR: Descriptor Loaded Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• ADD: Head Descriptor Loaded Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• DONE: End of List Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
• OVR: Overflow Interrupt Enable Register
0: No effect.
1: Interrupt source is enabled.
27
–
19
–
11
–
3
DSCR
26
–
18
–
10
–
2
DMA
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1218
46.7.92 Hardware Cursor Layer Interrupt Disable Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HCRIDR
0xF8038350
Write-only
0x00000000
30
–
22
–
14
–
6
OVR
29
–
21
–
13
–
5
DONE
28
–
20
–
12
–
4
ADD
27
–
19
–
11
–
3
DSCR
• DMA: End of DMA Transfer Interrupt Disable Register
0: No effect.
1: interrupt source is disabled.
• DSCR: Descriptor Loaded Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• ADD: Head Descriptor Loaded Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• DONE: End of List Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• OVR: Overflow Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
26
–
18
–
10
–
2
DMA
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1219
46.7.93 Hardware Cursor Layer Interrupt Mask Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HCRIMR
0xF8038354
Read-only
0x00000000
30
–
22
–
14
–
6
OVR
29
–
21
–
13
–
5
DONE
28
–
20
–
12
–
4
ADD
• DMA: End of DMA Transfer Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• DSCR: Descriptor Loaded Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• ADD: Head Descriptor Loaded Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• DONE: End of List Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
• OVR: Overflow Interrupt Mask Register
0: Interrupt source is disabled.
1: Interrupt source is enabled.
27
–
19
–
11
–
3
DSCR
26
–
18
–
10
–
2
DMA
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1220
46.7.94 Hardware Cursor Layer Interrupt Status Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HCRISR
0xF8038358
Read-only
0x00000000
30
–
22
–
14
–
6
OVR
29
–
21
–
13
–
5
DONE
28
–
20
–
12
–
4
ADD
27
–
19
–
11
–
3
DSCR
26
–
18
–
10
–
2
DMA
25
–
17
–
9
–
1
–
24
–
16
–
8
–
0
–
• DMA: End of DMA Transfer
When set to one, this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation.
• DSCR: DMA Descriptor Loaded
When set to one, this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation.
• ADD: Head Descriptor Loaded
When set to one, this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation.
• DONE: End of List Detected
When set to one, this flag indicates that an End of List condition has occurred. This flag is reset after a read operation.
• OVR: Overflow Detected
When set to one, this flag indicates that an Overflow has occurred. This flag is reset after a read operation.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1221
46.7.95 Hardware Cursor Layer Head Register
Name:
Address:
Access:
Reset:
31
LCDC_HCRHEAD
0xF803835C
Read-write
0x00000000
30 29 28
23
15
7
22
14
6
21
13
5
20
12
4
HEAD
HEAD
HEAD
HEAD
27
19
11
3
• HEAD: DMA Head Pointer
The Head Pointer points to a new descriptor.
26
18
10
2
25
17
9
1
–
24
16
8
0
–
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1222
46.7.96 Hardware Cursor Layer Address Register
Name:
Address:
Access:
Reset:
31
LCDC_HCRADDR
0xF8038360
Read-write
0x00000000
30 29 28
23
15
7
22
14
6
21
13
5
20
12
4
ADDR
ADDR
ADDR
ADDR
27
19
11
3
• ADDR: DMA Transfer start address
Frame Buffer Start Address.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1223
46.7.97 Hardware Cursor Layer Control Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HCRCTRL
0xF8038364
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
DONEIEN
28
–
20
–
12
–
4
ADDIEN
• DFETCH: Transfer Descriptor Fetch Enable
0: Transfer Descriptor fetch is disabled.
1: Transfer Descriptor fetch is enabled.
• LFETCH: Lookup Table Fetch Enable
0: Lookup Table DMA fetch is disabled.
1: Lookup Tabled DMA fetch is enabled.
• DMAIEN: End of DMA Transfer Interrupt Enable
0: DMA transfer completed interrupt is enabled.
1: DMA transfer completed interrupt is disabled.
• DSCRIEN: Descriptor Loaded Interrupt Enable
0: Transfer descriptor loaded interrupt is enabled.
1: Transfer descriptor loaded interrupt is disabled.
• ADDIEN: Add Head Descriptor to Queue Interrupt Enable
0: Transfer descriptor added to queue interrupt is enabled.
1: Transfer descriptor added to queue interrupt is disabled.
• DONEIEN: End of List Interrupt Enable
0: End of list interrupt is disabled.
1: End of list interrupt is enabled.
27
–
19
–
11
–
3
DSCRIEN
26
–
18
–
10
–
2
DMAIEN
25
–
17
–
9
–
1
LFETCH
24
–
16
–
8
–
0
DFETCH
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1224
46.7.98 Hardware Cursor Layer Next Register
Name:
Address:
Access:
Reset:
31
LCDC_HCRNEXT
0xF8038368
Read-write
0x00000000
30 29 28
23
15
7
22
14
6
21
13
5
20
12
4
NEXT
NEXT
NEXT
NEXT
27
19
11
3
• NEXT: DMA Descriptor Next Address
DMA Descriptor next address, this address must be word aligned.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1225
46.7.99 Hardware Cursor Layer Configuration 0 Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HCRCFG0
0xF803836C
Read-write
0x00000000
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
BLEN
28
–
20
–
12
–
4
27
–
19
–
11
–
3
–
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
–
24
–
16
–
8
DLBO
0
–
• BLEN: AHB Burst Length
Value
0
1
2
3
Name
AHB_SINGLE
AHB_INCR4
AHB_INCR8
AHB_INCR16
Description
AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR,
INCR4, INCR8 and INCR16 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of four 32-bit data. An AHB INCR4 Burst is preferred. SINGLE, INCR and INCR4 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of eight 32-bit data. An AHB INCR8 Burst is preferred. SINGLE, INCR, INCR4 and INCR8 bursts can be used. INCR is used for a burst of 2 and 3 beats.
AHB Access is started as soon as there is enough space in the FIFO to store a total amount of sixteen
32-bit data. An AHB INCR16 Burst is preferred. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts can be used. INCR is used for a burst of 2 and 3 beats.
• DLBO: Defined Length Burst Only for Channel Bus Transaction.
0: Undefined length INCR burst is used for a burst of 2 and 3 beats.
1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16).
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1226
46.7.100 Hardware Cursor Layer Configuration 1 Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
LCDC_HCRCFG1
0xF8038370
Read-write
0x00000000
30
–
22
–
14
29
–
21
–
13
28
–
20
–
12
–
7 6 5 4
RGBMODE
27
–
19
–
11
–
3
–
• CLUTEN: Color Lookup Table Enable
0: RGB mode is selected.
1: Color Lookup table is selected.
• RGBMODE: RGB input mode selection
5
6
3
4
1
2
Value
0
7
8
9
10
11
12
13
Name
12BPP_RGB_444
16BPP_ARGB_4444
16BPP_RGBA_4444
Description
12 bpp RGB 444
16 bpp ARGB 4444
16 bpp RGBA 4444
16BPP_RGB_565
16BPP_TRGB_1555
16 bpp RGB 565
16 bpp TRGB 1555
18BPP_RGB_666 18 bpp RGB 666
18BPP_RGB_666_PACKED 18 bpp RGB 666 PACKED
19BPP_TRGB_1666
19BPP_TRGB_PACKED
19 bpp TRGB 1666
19 bpp TRGB 1666 PACKED
24BPP_RGB_888 24 bpp RGB 888
24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED
25BPP_TRGB_1888
32BPP_ARGB_8888
25 bpp TRGB 1888
32 bpp ARGB 8888
32BPP_RGBA_8888 32 bpp RGBA 8888
2
3
0
1
• CLUTMODE: Color Lookup table input mode selection
Value Name
1BPP
2BPP
4BPP
8BPP
Description color lookup table mode set to 1 bit per pixel color lookup table mode set to 2 bits per pixel color lookup table mode set to 4 bits per pixel color lookup table mode set to 8 bits per pixel
26
–
18
–
10
–
2
–
25
–
17
–
9
1
–
24
–
16
–
8
CLUTMODE
0
CLUTEN
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1227
46.7.101 Hardware Cursor Layer Configuration 2 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_HCRCFG2
0xF8038374
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
YPOS
15
–
7
14
–
6
13
–
5
12
–
4
XPOS
27
–
19
11
–
3
• XPOS: Horizontal Window Position
Hardware Cursor Horizontal window position.
• YPOS: Vertical Window Position
Hardware Cursor Vertical window position.
26
18
10
2
25
YPOS
17
9
XPOS
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1228
46.7.102 Hardware Cursor Layer Configuration 3 Register
Name:
Address:
Access:
Reset:
31
–
23
–
15
–
7
–
LCDC_HCRCFG3
0xF8038378
Read-write
0x00000000
30
–
22
14
–
6
29
–
21
13
–
5
28
–
20
12
–
4
27
–
19
YSIZE
11
–
3
XSIZE
• XSIZE: Horizontal Window Size
Hardware cursor width is limited to 128 pixels.
Hardware Cursor window width in pixels. The window width is set to (XSIZE+1).
The following constraint must be met:
≤ PPL
• YSIZE: Vertical Window Size
Hardware cursor height is limited to 128 pixels
Hardware Cursor window height in pixels. The window height is set to (YSIZE+1).
The following constrain must be met:
≤ RPF
26
–
18
10
–
2
25
–
17
9
–
1
24
–
16
8
–
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1229
46.7.103 Hardware Cursor Layer Configuration 4 Register
Name:
Address:
Access:
Reset:
31
LCDC_HCRCFG4
0xF803837C
Read-write
0x00000000
30 29 28
XSTRIDE
23 22 21 20
XSTRIDE
15 14 13 12
XSTRIDE
7 6 5 4
XSTRIDE
27
19
11
3
• XSTRIDE: Horizontal Stride
XSTRIDE represents the memory offset, in bytes, between two rows of the image memory.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1230
46.7.104 Hardware Cursor Layer Configuration 6 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_HCRCFG6
0xF8038384
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
RDEF
15 14 13 12
GDEF
7 6 5 4
BDEF
11
3
27
–
19
• RDEF: Red Default
Default Red color when the Hardware Cursor DMA channel is disabled.
• GDEF: Green Default
Default Green color when the Hardware Cursor DMA channel is disabled.
• BDEF: Blue Default
Default Blue color when the Hardware Cursor DMA channel is disabled.
10
2
26
–
18
9
1
25
–
17
8
0
24
–
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1231
46.7.105 Hardware Cursor Layer Configuration 7 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_HCRCFG7
0xF8038388
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
RKEY
15 14 13 12
GKEY
7 6 5 4
BKEY
11
3
27
–
19
• RKEY: Red Color Component Chroma Key
Reference Red chroma key used to match the Red color of the current overlay.
• GKEY: Green Color Component Chroma Key
Reference Green chroma key used to match the Green color of the current overlay.
• BKEY: Blue Color Component Chroma Key
Reference Blue chroma key used to match the Blue color of the current overlay.
10
2
26
–
18
9
1
25
–
17
8
0
24
–
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1232
46.7.106 Hardware Cursor Layer Configuration 8 Register
Name:
Address:
Access:
Reset:
31
–
23
LCDC_HCRCFG8
0xF803838C
Read-write
0x00000000
30
–
22
29
–
21
28
–
20
RMASK
15 14 13 12
GMASK
7 6 5 4
BMASK
27
–
19
11
3
• RMASK: Red Color Component Chroma Key Mask
Red Mask used when the compare function is used. If a bit is set then this bit is compared.
• GMASK: Green Color Component Chroma Key Mask
Green Mask used when the compare function is used. If a bit is set then this bit is compared.
• BMASK: Blue Color Component Chroma Key Mask
Blue Mask used when the compare function is used. If a bit is set then this bit is compared.
10
2
26
–
18
9
1
25
–
17
8
0
24
–
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1233
46.7.107 Hardware Cursor Layer Configuration 9 Register
Name:
Address:
Access:
Reset:
31
–
23
15
–
7
OVR
LCDC_HCRCFG9
0xF8038390
Read-write
0x00000000
30
–
22
14
–
6
LAEN
29
–
21
13
–
5
GAEN
28
–
20
12
–
4
REVALPHA
GA
27
–
19
11
–
3
ITER
• CRKEY: Blender Chroma Key Enable
0: Chroma key matching is disabled.
1: Chroma key matching is enabled.
• INV: Blender Inverted Blender Output Enable
0: Iterated pixel is the blended pixel.
1: Iterated pixel is the inverted pixel.
• ITER2BL: Blender Iterated Color Enable
0: final adder stage operand is set to 0.
1: Final adder stage operand is set to the iterated pixel value.
• ITER: Blender Use Iterated Color
0: Pixel difference is set to 0.
1: Pixel difference is set to the iterated pixel value.
• REVALPHA: Blender Reverse Alpha
0: Pixel difference is multiplied by alpha.
1: Pixel difference is multiplied by 1 - alpha.
• GAEN: Blender Global Alpha Enable
0: Global alpha blending coefficient is disabled.
1: Global alpha blending coefficient is enabled.
• LAEN: Blender Local Alpha Enable
0: Local alpha blending coefficient is disabled.
1: Local alpha blending coefficient is enabled.
• OVR: Blender Overlay Layer Enable
0: Overlay pixel color is set to the default overlay pixel color.
1: Overlay pixel color is set to the DMA channel pixel color.
26
–
18
10
DSTKEY
2
ITER2BL
25
–
17
9
REP
1
INV
24
–
16
8
DMA
0
CRKEY
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1234
• DMA: Blender DMA Layer Enable
0: The default color is used on the Overlay 1 Layer.
1: The DMA channel retrieves the pixels stream from the memory.
• REP: Use Replication logic to expand RGB color to 24 bits
0: When the selected pixel depth is less than 24 bpp, the pixel is shifted and least significant bits are set to 0.
1: When the selected pixel depth is less than 24 bpp, the pixel is shifted and the least significant bit replicates the MSB.
• DSTKEY: Destination Chroma Keying
0: Source Chroma keying is enabled.
1: Destination Chroma keying is used.
• GA: Blender Global Alpha
Global alpha blender for the current layer.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1235
46.7.108 Base CLUT Register x Register
Address: 0xF8038400
Reset:
31
–
23
15
7
0x00000000
30
–
22
14
6
13
5
29
–
21
28
–
20
12
RCLUT
GCLUT
4
BCLUT
27
–
19
11
3
• BCLUT: Blue Color Entry
This field indicates the 8 bit width Blue color of the color lookup table.
• GCLUT: Green Color Entry
This field indicates the 8 bit width Green color of the color lookup table.
• RCLUT: Red Color Entry
This field indicates the 8 bit width Red color of the color lookup table.
10
2
26
–
18
9
1
25
–
17
8
0
24
–
16
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1236
46.7.109 Overlay 1 CLUT Register x Register
Address: 0xF8038800
Reset:
31
23
15
7
0x00000000
30
22
14
6
29
21
13
5
28
20
12
4
27
ACLUT
RCLUT
19
11
GCLUT
3
BCLUT
• BCLUT: Blue Color Entry
This field indicates the 8-bit width Blue color of the color lookup table.
• GCLUT: Green Color Entry
This field indicates the 8-bit width Green color of the color lookup table.
• RCLUT: Red Color Entry
This field indicates the 8-bit width Red color of the color lookup table.
• ACLUT: Alpha Color Entry
This field indicates the 8-bit width Alpha channel of the color lookup table.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1237
46.7.110 High End Overlay CLUT Register x Register
Address: 0xF8039000
Reset:
31
23
15
7
0x00000000
30
22
14
6
29
21
13
5
28
20
12
4
27
ACLUT
RCLUT
19
11
GCLUT
3
BCLUT
• BCLUT: Blue Color Entry
This field indicates the 8-bit width Blue color of the color lookup table.
• GCLUT: Green Color Entry
This field indicates the 8-bit width Green color of the color lookup table.
• RCLUT: Red Color Entry
This field indicates the 8-bit width Red color of the color lookup table.
• ACLUT: Alpha Color Entry
This field indicates the 8-bit width Alpha channel of the color lookup table.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1238
46.7.111 Hardware Cursor CLUT Register x Register
Address: 0xF8039400
Reset:
31
23
15
7
0x00000000
30
22
14
6
29
21
13
5
28
20
12
4
27
ACLUT
RCLUT
19
11
GCLUT
3
BCLUT
• BCLUT: Blue Color Entry
This field indicates the 8-bit width Blue color of the color lookup table.
• GCLUT: Green Color Entry
This field indicates the 8-bit width Green color of the color lookup table.
• RCLUT: Red Color Entry
This field indicates the 8-bit width Red color of the color lookup table.
• ACLUT: Alpha Color Entry
This field indicates the 8-bit width Alpha channel of the color lookup table.
26
18
10
2
25
17
9
1
24
16
8
0
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1239
47.
Electrical Characteristics
47.1 Absolute Maximum Ratings
Table 47-1. Absolute Maximum Ratings*
Operating Temperature (Industrial)..............-40 ° C to + 85 ° C
Junction Temperature..................................................125°C
Storage Temperature.................................-60°C to + 150°C
Voltage on Input Pins with Respect to Ground....-0.3V to VDDIO + 0.3V(+ 4V max)
Maximum Operating Voltage
(VDDCORE, VDDPLLA, VDDUTMIC)............................1.2V
(VDDIOM0).....................................................................2.0V
(VDDIOM1, VDDIOPx, VDDUTMII, VDDOSC,
VDDANA and VDDBU)...................................................4.0V
Total DC Output Current on all I/O lines....................350 mA
*NOTICE: Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SAM9X35 [DATASHEET]
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1240
47.2 DC Characteristics
The following characteristics are applicable to the operating temperature range: T
A
= -40°C to +85°C, unless otherwise specified.
Table 47-2. DC Characteristics
Symbol Parameter
V
DDCORE
V
DDCORErip
V
DDUTMIC
DC Supply Core
V
DDCORE
ripple
DC Supply UDPHS and
UHPHS UTMI+ Core
V
V
V
V
V
V
V
V
V
V
DDUTMII
DDBU
DDBUrip
DDPLLA
DDPLLArip
DDOSC
DDOSCrip
DDIOM
DDNF
DDIOP0
V
DDIOP1
V
DDANA
DC Supply UDPHS and
UHPHS UTMI+ Interface
DC Supply Backup
V
DDBU
ripple
DC Supply PLLA
V
DDPLLA
ripple
DC Supply Oscillator
V
DDOSC
ripple
DC Supply EBI I/Os
DC Supply NAND Flash
I/Os
DC Supply Peripheral I/Os
DC Supply Peripheral I/Os
DC Supply Analog
V
IL
V
IH
Low-level Input Voltage
High-level Input Voltage
Conditions Min
0.9
0.9
3.0
1.8
0.9
1.65
1.65/3.0
1.65/3.0
1.65
1.65
3.0
-0.3
-0.3
2
0.7 × V
DDIO
Typ
1.0
1.0
3.3
1.0
1.8/3.3
1.8/3.3
3.3
Max
1.1
20
1.1
3.6
3.6
30
1.1
10
3.6
30
1.95/3.6
1.95/3.6
3.6
3.6
3.6
0.8
0.3 × V
DDIO
V
DDIO
+ 0.3
V
DDIO
+ 0.3
0.4
Unit
V mVrms
V
V
V
V
V
V
V
V
V
V
V mVrms
V mVrms
V mVrms
V
V
V
OL
V
OH
V
T-
V
T+
Low-level Output Voltage
High-level Output Voltage
Schmitt trigger Negative going threshold Voltage
Schmitt trigger Positive going threshold Voltage
V
DDIO
from 3.0V to 3.6V
V
DDIO
from 1.65V to 1.95V
V
DDIO from 3.0V to 3.6V
V
DDIO from 1.65V to 1.95V
I
O
Max, V
DDIO from 3.0V to 3.6V
CMOS (I
O
< 0.3 mA), V
1.65V to 1.95V
DDIO
from
TTL (I
O
1.95V
Max), V
DDIO
from 1.65V to
I
O
Max, V
DDIO
from 3.0V to 3.6V
CMOS (I
O
< 0.3 mA), V
1.65V to 1.95V
DDIO
from
TTL (I
O
1.95V
Max), V
DDIO
from 1.65V to
I
O
Max, V
DDIO from 3.0V to 3.6V
TTL (I
O
1.95V
Max), V
DDIO
from 1.65V to
I
O
Max, V
DDIO
from 3.0V to 3.6V
TTL (I
O
1.95V
Max), V
DDIO
from 1.65V to
V
DDIO
- 0.4
V
DDIO
- 0.1
V
DDIO
- 0.4
0.8
0.3 × V
DDIO
1.1
1.6
0.1
0.4
0.3 × V
DDIO
2.0
V
V
V
V
V
V
V
V
V
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1241
Table 47-2. DC Characteristics (Continued)
Symbol
V
HYS
Parameter
Schmitt trigger Hysteresis
Conditions
V
DDIO from 3.0V to 3.6V
V
DDIO from 1.65V to 1.95V
PA0–PA31 PB0–PB31 PC0–PC31
NTRST and NRST
R
PULLUP
Pull-up/Pull-down
Resistance
I
O
Output Current
PD0–PD21 V
DDIOM in 1.8V range
PD0–PD21 V
DDIOM1 in 3.3V range
PA0–PA31 PB0–PB31 PD0–PD31
PE0–PE31
PC0–PC31 V
DDIOM1 in 1.8V range
PC0–PC31 V
DDIOM1 in 3.3V range
On V
DDCORE
= 1.0V,
MCK = 0 Hz, excluding
POR
T
A
= 25°C
I
Z
SC
IN
Static Current
Input impedance
All inputs driven TMS,
TDI, TCK, NRST = 1
On V
DDBU
= 3.3V,
Logic cells consumption, excluding
POR
All inputs driven
WKUP = 0
V
DDIO
= 3.3V
V
DDIO
= 1.8V
T
T
T
A
A
A
= 85°C
= 25°C
= 85°C
Min
0.5
0.28
40
80
120
Typ
75
14
8
3.3
1.8
Max
0.75
0.6
190
300
350
8
2
4
46
18
Unit
V
V k Ω mA mA
µ
A
M Ω
M Ω
47.3 Power Consumption
Typical power consumption of PLLs, Slow Clock and Main Oscillator.
Power consumption of power supply in four different modes: Active, Idle, Ultra Low-power and Backup.
Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock.
47.3.1 Power Consumption versus Modes
The values in
Table 47-3 and Table 47-4 are estimated values of the power consumption with operating conditions as
follows:
V
DDIOM
= 1.8V
V
DDIOP0 and V
DDIOP1
= 3.3V
V
DDPLLA
= 1.0V
V
DDCORE
= 1.0V
V
DDBU
= 3.3V
T
A
= 25°C
There is no consumption on the I/Os of the device.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1242
Figure 47-1. Measures Schematics
VDDBU
AMP1
VDDCORE
AMP2
These figures represent the power consumption estimated on the power supplies.
Table 47-3. Power Consumption for Different Modes
Mode Conditions
Active
ARM Core clock is 400 MHz.
MCK is 133 MHz.
All peripheral clocks activated.
onto AMP2
Idle
Ultra low power
Backup
Idle state, waiting an interrupt.
All peripheral clocks de-activated.
onto AMP2
ARM Core clock is 500 Hz.
All peripheral clocks de-activated.
onto AMP2
Device only V
DDBU onto AMP1
powered
Consumption
109
38
8
8
Unit mA mA mA
µ A
Table 47-4. Power Consumption by Peripheral in Active Mode
Peripheral
PIO Controller
USART
UHPHS
UDPHS
ADC
TWI
SPI
PWM
HSMCI
SSC
Timer Counter Channels
DMA
SMD
CAN
Consumption
1
6
5
2
60
22
12
1
14
17
28
5
3
6
Unit
µ
EMAC
LCD
39
30
Note: 1. Reference frequency is peripheral frequency. It can be a division (1,2,4,8) of MCK. Refer to PMC section for more details.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1243
47.4 Clock Characteristics
47.4.1 Processor Clock Characteristics
Table 47-5. Processor Clock Waveform Parameters
Symbol Parameter Conditions Min
1/(t
CPPCK
) Processor Clock Frequency V
DDCORE
= 0.9V, T
A
= 85°C 125
Note: 1. For DDR2 usage only, there are no limitations to LP-DDR, SDRAM and mobile SDRAM.
Max
400
Unit
MHz
47.4.2 Master Clock Characteristics
The master clock is the maximum clock at which the system is able to run. It is given by the smallest value of the internal bus clock and EBI clock.
Table 47-6. Master Clock Waveform Parameters
Symbol Parameter Conditions Min
1/(t
CPMCK
) Master Clock Frequency V
DDCORE
= 0.9V, T
A
= 85°C 125
Note: 1. For DDR2 usage only, there are no limitations to LP-DDR, SDRAM and mobile SDRAM.
Max
133
Unit
MHz
47.5 Main Oscillator Characteristics
Table 47-7. Main Oscillator Characteristics
Symbol
1/(t
CPMAIN
)
C
Parameter
Crystal Oscillator Frequency
Crystal Load Capacitance t
I
C
LEXT
ST
DDST
P
ON
Conditions
External Load Capacitance
C
CRYSTAL
C
CRYSTAL
Duty Cycle
Startup Time
Standby Current Consumption Standby mode
Drive Level
I
DD ON
Current Dissipation
@ 12 MHz
@ 16 MHz
Min
12
15
40
Typ
27
32
0.52
0.7
Max
16
20
60
2
1
150
0.55
1.1
µ W mA mA
% ms
µ
A
Unit
MHz pF pF pF
Note: 1. The C
CRYSTAL
value is specified by the crystal manufacturer. In our case, C
CRYSTAL
must be between 15 pF and 20 pF.
All parasitic capacitance, package and board, must be calculated in order to reach 15 pF (minimum targeted load for the oscillator) by taking into account the internal load C
INT
. So, to target the minimum oscillator load of 15 pF, external capacitance must be: 15 pF - 4 pF = 11 pF which means that 22 pF is the target value (22 pF from XIN to GND and
22 pF from XOUT to GND). If 20 pF load is targeted, the sum of pad, package, board and external capacitances must be 20 pF - 4 pF = 16 pF which means 32 pF (32 pF from XIN to GND and 32 pF from XOUT to GND).
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1244
Figure 47-2. Main Oscillator Schematics
XIN
C
LEXT
C
CRY S TAL
1K
C
LEXT
XOUT
GNDPLL
Note: A 1K resistor must be added on XOUT pin for crystals with frequencies lower than 8 MHz.
47.5.1 Crystal Oscillator Characteristics
The following characteristics are applicable to the operating temperature range: T
A
= -40°C to 85°C and worst case of power supply, unless otherwise specified.
Table 47-8. Crystal Characteristics
Symbol Parameter Min Typ Unit
ESR
C
M
C
S
Equivalent Series Resistor Rs
Motional Capacitance
Shunt Capacitance
Conditions
@ 16 MHz
@ 12 MHz C
CRYSTAL
Max
@ 12 MHz C
CRYSTAL
Min
5
Max
80
90
110
9
7
Ω fF pF
47.5.2 XIN Clock Characteristics
Table 47-9. XIN Clock Electrical Characteristics
Symbol Parameter Conditions Min Max Unit
1/(t
CPXIN
) t
CPXIN t
CHXIN t
CLXIN
C
IN
R
IN
V
IN
XIN Clock Frequency
XIN Clock Period
XIN Clock High Half-period
XIN Clock Low Half-period
XIN Input Capacitance
XIN Pulldown Resistor
XIN Voltage
20
0.4 × t
CPXIN
0.4 × t
CPXIN
V
DDOSC
50
0.6 × t
CPXIN
0.6 × t
CPXIN
25
500
V
DDOSC
MHz ns ns ns pF k Ω
V
Note: 1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBY-
PASS = 1) in the CKGR_MOR. See “PMC Clock Generator Main Oscillator Register” in the PMC section.
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1245
47.6 12 MHz RC Oscillator Characteristics
Table 47-10. 12 MHz RC Oscillator Characteristics
Symbol Parameter Conditions f0
Duty
Nominal Frequency
I t
DD ON
ST
I
DD STDBY
Duty Cycle
Power Consumption Oscillation
Without trimming
After trimming sequence
Startup time
Standby consumption
Min
8.4
45
86
86
6
Typ
12
50
47.7 32 kHz Oscillator Characteristics
Table 47-11. 32 kHz Oscillator Characteristics
Symbol Parameter Conditions
1/(t
CP32KHz
)
C
CRYSTAL32
C
Crystal Oscillator Frequency
Load Capacitance
External Load Capacitance
Crystal @ 32.768 kHz
C
CRYSTAL32
= 6 pF
C
CRYSTAL32
= 12.5 pF
Duty Cycle t
ST
Startup Time
R
S
= 50 k Ω
R
S
= 100 k Ω
C
CRYSTAL32
= 6 pF
C
CRYSTAL32
= 12.5 pF
C
CRYSTAL32
= 6 pF
C
CRYSTAL32
= 12.5 pF
Min
6
40
Typ
32 768
Notes: 1. R
S
is the equivalent series resistance.
2. C
LEXT32
is determined by taking into account internal, parasitic and package load capacitance.
Figure 47-3. 32 kHz Oscillator Schematics
6
19
50
Max
15.6
55
140
125
10
22
Max
12.5
60
400
900
600
1200 ms ms ms pF
% ms
Unit kHz pF pF
Unit
MHz
%
µA
µs
µA
XIN 3 2
C
CRY S TAL 3 2
XOUT 3 2 GNDBU
C
LEXT 3 2
C
LEXT 3 2
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1246
47.7.1 32 kHz Crystal Characteristics
Table 47-12. 32 kHz Crystal Characteristics
Symbol Parameter
ESR
C
M
C
S
Equivalent Series Resistor Rs
Motional Capacitance
Shunt Capacitance
I
DD ON
Current dissipation
Conditions
Crystal @ 32.768 kHz
Crystal @ 32.768 kHz
Crystal @ 32.768 kHz
R
S
= 50 k Ω
CRYSTAL32
= 6 pF
R
S
= 50 k Ω
CRYSTAL32
= 12.5 pF
R
S
= 100 k Ω
C
CRYSTAL32
= 6 pF
R
S
= 100 k Ω
C
CRYSTAL32
= 12.5 pF
Min
0.6
0.6
Typ
50
0.55
0.85
0.7
1.1
1.3
1.6
2.0
2.2
0.3
Max
100
3
2
I
DD STDBY
Standby consumption
47.7.2 XIN32 Clock Characteristics
Table 47-13. XIN32 Clock Characteristics
Symbol Parameter
1/(t
CPXIN32
) t
CPXIN32 t
CHXIN32 t
CLXIN32 t
CLCH32 t
CLCL32
C
IN32
R
IN32
V
IN32
V
INIL32
V
INIH32
XIN32 Clock Frequency
XIN32 Clock Period
XIN32 Clock High Half-period
XIN32 Clock Low Half-period
XIN32 Clock Rise time
XIN32 Clock Fall time
XIN32 Input Capacitance
XIN32 Pulldown Resistor
XIN32 Voltage
XIN32 Input Low Level Voltage
XIN32 Input High Level Voltage
Conditions
Min
22
11
11
400
400
V
DDBU
-0.3
0.7 × V
DDBU
Max
44
6
4
V
DDBU
0.3 × V
DDBU
V
DDBU
+ 0.3
Unit kHz
µs
µs
µs ns ns pF
M Ω
V
V
V
Note: 1. These characteristics apply only when the 32.768 kHz Oscillator is in bypass mode (i.e., when RCEN = 0,
OSC32EN = 0, OSCSEL = 1 and OSC32BYP = 1) in the Slow Clock Controller Configuration Register (SCKC_CR).
See “Slow Clock Selection” in the PMC section.
µA
µA
µA
µA
Unit k Ω fF pF
µA
47.8 32 kHz RC Oscillator Characteristics
Table 47-14. 32 kHz RC Oscillator Characteristics
Symbol Parameter Conditions
1/(t
CPRCz
) Crystal Oscillator Frequency
Duty Cycle t
ST
I
DD ON
I
DD STDBY
Startup Time
Power Consumption Oscillation
Standby consumption
After startup time
Min
20
45
Typ
32
1.1
Max
44
55
75
2.1
0.4
Unit kHz
%
µ s
µA
µA
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47.9 PLL Characteristics
Table 47-15. PLLA Characteristics
Symbol Parameter f
OUT f
IN
Output Frequency
Input Frequency
Current Consumption I
PLL t
ST
Startup Time
Conditions
Refer to following table
Active mode
Standby mode
Min
400
2
Typ
7
Max
800
32
9
1
50
Unit
MHz
MHz mA
µA
µs
The following configuration of bit PMC_PLLICPR.ICPLLA and field CKGR_PLLAR.OUTA must be done for each PLLA frequency range.
Table 47-16. PLLA Frequency Regarding ICPLLA and OUTA
PLL Frequency Range (MHz)
745–800
PMC_PLLICPR.ICPLLA Value
0
695–750
645–700
595–650
545–600
0
0
0
1
495–550
445–500
400–450
1
1
1
CKGR_PLLAR.OUTA Value
00
01
10
11
00
01
10
11
47.9.1 UTMI PLL Characteristics
Table 47-17. Phase Lock Loop Characteristics
Symbol Parameter f
IN f
OUT
Input Frequency
Output Frequency
Conditions
I
PLL
Current Consumption
Active mode
Standby mode t
ST
Startup Time
Min
4
450
Typ
12
480
5
Max
32
600
8
1.5
50
Unit
MHz
MHz mA
µA
µs
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47.10 I/Os
Criteria used to define the maximum frequency of the I/Os:
Output duty cycle (40%–60%)
Minimum output swing: 100 mV to V
DDIO
- 100 mV
Addition of rising and falling time inferior to 75% of the period
Table 47-18. I/O Characteristics
Symbol Parameter f max
V
DDIOP
powered pins frequency
Conditions
Min
100 (Low Drive)
50 (Low Drive)
Notes: 1. 3.3V domain: V
DDIOP from 3.0V to 3.6V, maximum external capacitor = 20 pF
2. 1.8V domain: V
DDIOP from 1.65V to 1.95V, maximum external capacitor = 20 pF
Max
200 (High Drive)
166 (High Drive)
47.11 USB HS Characteristics
Table 47-19. USB HS Electrical Characteristics
Symbol
R
PUI
Parameter Conditions
Bus Pull-up Resistor on Upstream Port (idle bus) In LS or FS Mode
R
PUA
Bus Pull-up Resistor on Upstream Port
(upstream port receiving)
In LS or FS Mode t
Settling time
BIAS t
OSC t
SETTLING
Bias settling time
Oscillator settling time
Settling time
With Crystal 12 MHz f
IN
= 12 MHz
Table 47-21. USB HS Dynamic Power Consumption
Symbol Parameter
I
BIAS
Bias current consumption on VBG
HS Transceiver current consumption
I
VDDUTMII
HS Transceiver current consumption
LS / FS Transceiver current consumption
LS / FS Transceiver current consumption
LS / FS Transceiver current consumption
Conditions
HS transmission
HS reception
FS reception
I
VDDUTMIC
PLL, Core and Oscillator current consumption
Note: 1. Including 1mA due to Pull-up/Pull-down current consumption.
Min
Table 47-20. USB HS Static Power Consumption
Symbol Parameter
I
BIAS
I
VDDUTMII
Conditions
Bias current consumption on VBG
HS Transceiver and I/O current consumption
LS / FS Transceiver and I/O current consumption
Min
I
VDDUTMIC
Core, PLL, and Oscillator current consumption
Note: 1. If cable is connected add 200 µA (Typical) due to Pull-up/Pull-down current consumption.
Min
Typ
1.5
15
0.3
Typ
Typ
0.7
47
18
4
26
3
5.5
Max
20
2
0.5
Max
1
8
3
2
Max
0.8
60
27
6
30
4.5
9
Unit
MHz
MHz
Unit k Ω k Ω
µs ms ms
Unit
µA
µA
µA
µA
Unit mA mA mA mA mA mA mA
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47.12 USB Transceiver Characteristics
Table 47-22. USB Transceiver Electrical Characteristics
Symbol Parameter Conditions
Input Levels
V
IL
V
IH
V
DI
V
CM
Low-evel Input Voltage
High-level Input Voltage
Differential Input Sensitivity
Differential Input Common Mode
Range
I
C
IN lkg
R
EXT
Transceiver capacitance
Hi-Z State Data Line Leakage
Recommended External USB Series
Resistor
Output Levels
V
OL
V
OH
Low-level Output Voltage
High-level Output Voltage
V
CRS
Output Signal Crossover Voltage
Pull-up and Pull-down Resistor
|(D+) - (D-)|
Capacitance to ground on each line
0V < V
IN
< 3.3V
In series with each USB pin with
Measured with R
L
Measured with R
L
±
5%
of 1.425 k Ω tied to 3.6V
of 14.25 k Ω tied to GND
Measure conditions described in Figure 47-4
R
R
R
PUI
PUA
PD
Bus Pull-up Resistor on Upstream
Port (idle bus)
Bus Pull-up Resistor on Upstream
Port (upstream port receiving)
Bus Pull-down resistor
Figure 47-4. USB Data Signal Rise and Fall Times
Rise Time
V
CRS
10%
Differential
Data Lines t
R
90%
Fall Time t
F
10%
(a)
R
EXT
=27 ohms
Fosc = 6 MHz/750 kHz
C load
Buffer
(b)
Min
2.0
0.2
0.8
- 10
0.0
2.8
1.3
0.900
1.425
14.25
Typ
27
Max Unit
0.8
2.5
9.18
+ 10
V
V
V
V pF
µA
Ω
0.3
3.6
2.0
1.575
3.090
24.8
k Ω k Ω k Ω
V
V
V
Table 47-23. In Full Speed
Symbol Parameter t
FR t
FE t
FRFM
Transition Rise Time
Transition Fall Time
Rise/Fall time Matching
Conditions
C
LOAD
= 50 pF
C
LOAD
= 50 pF
Min
4
4
90
Typ Max
20
20
111.11
Unit ns ns
%
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47.13 Analog-to-Digital Converter (ADC)
Table 47-24. Channel Conversion Time and ADC Clock
Parameter Conditions
ADC Clock Frequency 10-bit resolution mode
Min
Startup Time
Track and Hold Acquisition Time (TTH)
Conversion Time (TCT)
Throughput Rate
Return from Idle Mode
ADC Clock = 13.2 MHz
ADC Clock = 13.2 MHz
ADC Clock = 13.2 MHz
0.5
Note: 1. The Track-and-Hold Acquisition Time is given by: TTH (ns) = 500 + (0.12 × Z
IN
)( Ω )
Typ Max
13.2
40
1.74
4.6
440
192
Unit
MHz
µ s
µ s
µs kSPS
The ADC internal clock is divided by 2 in order to generate a clock with a duty cycle of 75%. So the maximum conversion time is given by:
=
23
(
MHz f clk
)
The full speed is obtained for an input source impedance of < 50 Ω maximum, or TTH = 500 ns.
In order to make the TSADC work properly, the SHTIM field in TSADCC Mode Register is to be calculated according to this Track and Hold Acquisition Time (also called Sampled and Hold Time).
Table 47-25. External Voltage Reference Input
Parameter
ADVREF Input Voltage Range
Conditions
ADVREF Average Current
Current Consumption on VDDANA
Table 47-26. Analog Inputs
Parameter
Input Voltage Range
Input Peak Current
Input Capacitance
Input Impedance
Table 47-27. Transfer Characteristics
Parameter
Resolution
Integral Non-linearity
Conditions
Conditions
Differential Non-linearity
ADC Clock = 13.2 MHz
ADC Clock = 5 MHz
Offset Error
Gain Error
ADC Clock = 13.2 MHz
ADC Clock = 5 MHz
Min
2.4
Min
0
Typ Max
VDDANA
600
600
Unit
V
µA
µA
Typ
7
50
Max
ADVREF
2.5
10
Unit
V mA pF
Ω
Min Typ
10
Max
±
2
± 2
±
0.9
± 10
±
3
± 2
Unit bit
LSB
LSB mV
LSB
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Table 47-28. Pen Detection Sensitivity
ADC_ACR [1:0]
0
Resistor (k Ω )
200
1
2
150
100 (default)
3 50
The Pen Detection Sensitivity is programmable by an ADC internal resistor. This resistor is set depending on the value of the PENDETSENS field in ADC_ACR, offset 0x94 in the ADC User Interface.
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47.14 POR Characteristics
A general presentation of Power-On-Reset (POR) characteristics is provided in
Figure 47-5. General Presentation of POR Behavior
V
DD
V th+
V th-
Vop
Vnop
NRST
Static Dynamic t res
When a very slow (versus t
RES
) supply rising slope is applied on POR VDD pin, the reset time becomes negligible and the reset signal is released when V
DD
rises higher than V th+
.
When a very fast (versus t
RES
) supply rising slope is applied on POR VDD pin, the voltage threshold becomes negligible and the reset signal is released after t
RES
time. It is the smallest possible reset time.
47.14.1 Core Power Supply POR Characteristics
Table 47-29. Core Power Supply POR Characteristics
Symbol
V th+
V tht
RES
I
DD
Parameter
Threshold Voltage Rising
Threshold Voltage Falling
Reset Time
Current consumption
Conditions
Minimum Slope of +2.0V/30ms
Minimum Slope of +2.0V/30ms
After t
RES
Min
0.5
0.4
30
Typ
0.7
0.6
70
3
Max
0.89
0.85
130
7
Unit
V
V
µ s
µ A
47.14.2 Backup Power Supply POR Characteristics
Table 47-30. Backup Power Supply POR Characteristics
Symbol
V th+
V th-
Parameter
Threshold Voltage Rising
Threshold Voltage Falling
Conditions
Minimum Slope of +2.0V/30ms
I t
RES
DD
Reset Time
Current consumption
Minimum Slope of +2.0V/30ms
V
DDBU
is 3.3V
V
DDBU
is 1.8V
After t
RES
Min
1.42
1.35
30
40
Typ
4.52
1.45
80
100
6
Max
1.62
1.55
220
330
8.5
Unit
V
V
µ s
µ
A
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47.15 Power Sequence Requirements
The AT91 board design must comply with the power-up guidelines below to guarantee reliable operation of the device.
Any deviation from these sequences may prevent the device from booting.
47.15.1 Power-Up Sequence
Figure 47-6. V
DDCORE
and V
DDIO
Constraints at Startup
V
DD
(V)
VDDIOtyp
V
OH
V
DDIO
V
DDIO
> V
OH
V
DDIO
> V
IH
V
IH
V
DDCORE
VDDCOREtyp
V th+ t t res t
1 t
2
Core Supply POR Output
SLCK
V
DDCORE
and V
DDBU
are controlled by internal POR (Power-On-Reset) to guarantee that these power sources reach their target values prior to the release of POR.
V
DDIOP
V
must be ≥ V
IH
(refer to DC characteristics, Table 47-2
, for more details), (t
DDCORE
has reached V th+
.
RES
+ t
V
DDIOM
V
must reach V
OH
(refer to DC characteristics, Table 47-2
, for more details), (t
DDCORE
has reached V th+
RES
1
) at the latest, after
+ t
1
+ t
2
) at the latest, after
t
RES
is a POR characteristic t
1
= 3 × t
SLCK t
2
= 16 × t
SLCK
The t
SLCK
min (22 µs) is obtained for the maximum frequency of the internal RC oscillator (44 kHz).
t
RES
= 30 µs
t
1
= 66 µs
t
2
= 352 µs
V
DDPLL
is to be established prior to V
DDCORE
to ensure the PLL is powered once enabled into the ROM code.
As a conclusion, establish V
DDIOP device.
and V
DDIOM
first, then V
DDPLL
, and V
DDCORE
last, to ensure a reliable operation of the
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47.16 SMC Timings
47.16.1 Timing Conditions
SMC Timings are given for MAX corners.
Timings are given assuming a capacitance load on data, control and address pads.
Table 47-31. Capacitance Load
Corner
Supply
3.3V
1.8V
Max
50 pF
30 pF
Min
5 pF
5 pF
In the following tables, t
CPMCK is MCK period.
47.16.2 Timing Extraction
47.16.2.1 Zero Hold Mode Restrictions
Table 47-32. Zero Hold Mode Use Maximum System Clock Frequency (MCK)
Symbol f max
Parameter
MCK frequency
Max
VDDIOM supply 1.8V
VDDIOM supply 3.3V
66 66
Unit
MHz
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47.16.2.2
Read Timings
Table 47-33. SMC Read Signals - NRD Controlled (READ_MODE = 1)
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
1
2
3
4
5
6
7
Min
Parameter VDDIOM supply 1.8V
NO HOLD SETTINGS (nrd hold = 0)
13.6
VDDIOM supply 3.3V
Data Setup before NRD High 11.7
Data Hold after NRD High
Data Setup before NRD High
Data Hold after NRD High
0
HOLD SETTINGS (nrd hold ≠ 0)
10.9
0
0
9.0
0
NBS0/A0, NBS1, NBS2/A1, NBS3, A2–A25
Valid before NRD High
HOLD or NO HOLD SETTINGS (nrd hold ≠ 0, nrd hold =0)
(nrd setup + nrd pulse) × t
CPMCK
- 4.7
(nrd setup + nrd pulse)
- 4.7
× t
CPMCK
NCS low before NRD High
NRD Pulse Width
(nrd setup + nrd pulse - ncs rd setup) × t
CPMCK
- 4.3
nrd pulse × t
CPMCK
- 3.2
(nrd setup + nrd pulse - ncs rd setup) × t
CPMCK
- 4.4
nrd pulse × t
CPMCK
- 3.3
Unit ns ns ns ns ns ns ns
Table 47-34. SMC Read Signals - NCS Controlled (READ_MODE = 0)
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
8
9
10
11
12
13
14
Min
Parameter VDDIOM supply 1.8V
NO HOLD SETTINGS (ncs rd hold = 0)
VDDIOM supply 3.3V
Data Setup before NCS High
Data Hold after NCS High
26.9
0
25.0
0
Data Setup before NCS High
Data Hold after NCS High
HOLD SETTINGS (ncs rd hold ≠ 0)
12.3
0
10.4
0
NBS0/A0, NBS1, NBS2/A1, NBS3, A2–A25 valid before NCS High
HOLD or NO HOLD SETTINGS (ncs rd hold ≠ 0, ncs rd hold = 0)
(ncs rd setup + ncs rd pulse) × t
CPMCK
- 18.4
(ncs rd setup + ncs rd pulse) t
CPMCK
- 18.4
×
NRD low before NCS High
NCS Pulse Width
(ncs rd setup + ncs rd pulse - nrd setup) × t
CPMCK
- 2.0
ncs rd pulse length × t
CPMCK
4.0
-
(ncs rd setup + ncs rd pulse - nrd setup) × t
CPMCK
- 2.1
ncs rd pulse length × t
4.0
CPMCK
-
Unit ns ns ns ns ns ns ns
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47.16.2.3 Write Timings
Table 47-35. SMC Write Signals - NWE Controlled (WRITE_MODE = 1)
Min
1.8 V
Supply
Max
3.3 V
Supply Symbol
SMC
15
SMC
16
SMC
17
SMC
18
SMC
19
SMC
20
Parameter 1.8V Supply 3.3V Supply
HOLD or NO HOLD SETTINGS (nwe hold ≠ 0, nwe hold = 0)
Data Out Valid before NWE High nwe pulse × t
CPMCK
- 3.9
nwe pulse × t
CPMCK
- 3.9
NWE Pulse Width nwe pulse × t
CPMCK
- 3.2
nwe pulse × t
CPMCK
- 3.2
NBS0/A0 NBS1, NBS2/A1, NBS3,
A2–A25 valid before NWE low nwe setup × t
CPMCK
- 4.2
nwe setup × t
CPMCK
- 4.0
NCS low before NWE high
(nwe setup - ncs rd setup
+ nwe pulse) × t
CPMCK
4.2
-
(nwe setup - ncs rd setup
+ nwe pulse) × t
CPMCK
HOLD SETTINGS (nwe hold ≠ 0)
4.2
-
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2–A25 change nwe hold × t
CPMCK
- 4.8
nwe hold × t
CPMCK
- 4.0
NWE High to NCS Inactive
(nwe hold - ncs wr hold)
× t
CPMCK
- 4.0
(nwe hold - ncs wr hold)
× t
CPMCK
NO HOLD SETTINGS (nwe hold = 0)
- 3.5
Unit ns ns ns ns ns ns
SMC
21
SMC
21b
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2–A25,
NCS change
Min Period/Max Frequency with
No Hold settings
1.9
11.4
1.5
9.7
87 103 ns ns/
MHz
Notes: 1. xxxhold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr hold length” or “NWE hold length”.
Table 47-36. SMC Write NCS Controlled (WRITE_MODE = 0)
Symbol
SMC
22
SMC
23
SMC
SMC
SMC
SMC
24
25
26
27
Parameter
Data Out Valid before NCS High
NCS Pulse Width
NBS0/A0 NBS1, NBS2/A1, NBS3, A2–
A25 valid before NCS low
NWE low before NCS high
NCS High to Data Out, NBS0/A0, NBS1,
NBS2/A1, NBS3, A2 - A25, change
NCS High to NWE Inactive
1.8V Supply ncs wr pulse × t
CPMCK
- 2.9
ncs wr pulse × t
CPMCK
- 4.0
ncs wr setup × t
CPMCK
- 3.6
(ncs wr setup - nwe setup + ncs pulse) × t
CPMCK
- 4.6
ncs wr hold × t
CPMCK
- 5.4
(ncs wr hold - nwe hold) × t
CPMCK
- 4.2
Min
3.3V Supply ncs wr pulse × t
CPMCK
- 3.0
ncs wr pulse × t
CPMCK
- 4.0
ncs wr setup × t
CPMCK
- 3.5
(ncs wr setup - nwe setup + ncs pulse) × t
CPMCK
- 4.6
ncs wr hold × t
CPMCK
- 4.5
(ncs wr hold - nwe hold) × t
CPMCK
- 3.8
Unit ns ns ns ns ns ns
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Figure 47-7. SMC Timings - NCS Controlled Read and Write
S MC12 S MC26
S MC12 S MC24
A0/A1/NB S [ 3 :0]
/A2-A25
NRD
S MC1 3 S MC1 3
NC S
S MC14
S MC 8
S MC9
S MC14
S MC10 S MC11
S MC2 3
S MC22 S MC26
D0 - D15
S MC25 S MC27
NWE
NC S Controlled READ with NO HOLD
NC S Controlled READ with HOLD
Figure 47-8. SMC Timings - NRD Controlled Read and NWE Controlled Write
S MC21 S MC5
S MC5 S MC17
A0/A1/NB S [ 3 :0]
/A2-A25
S MC6
S MC1 8 S MC21 S MC6
NC S
NRD
S MC7
S MC1 S MC2 S MC15 S MC21
S MC7
S MC 3 S MC4
D0 - D 3 1
NWE
S MC16
NC S Controlled WRITE
S MC17
S MC1 8
S MC15 S MC19
S MC16
S MC20
NRD Controlled READ with NO HOLD
NWE Controlled WRITE with NO HOLD
NRD Controlled READ with HOLD
NWE Controlled WRITE with HOLD
47.17 DDRSDRC Timings
The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR modules.
DDR2, LP-DDR and SDR timings are specified by the JEDEC standard.
Supported speed grade limitations:
DDR2-400 limited at 133 MHz clock frequency (1.8V, 30 pF on data/control, 10 pF on CK/CK#)
LP-DDR limited at 133 MHz clock frequency (1.8V, 30 pF on data/control, 10 pF on CK)
SDR-100 (3.3V, 50 pF on data/control, 10 pF on CK)
SDR-133 (3.3V, 50 pF on data/control, 10 pF on CK)
LP-SDR-133 (1.8V, 30 pF on data/control, 10 pF on CK)
S MC19
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47.18 Peripheral Timings
47.18.1 SPI
47.18.1.1 Maximum SPI Frequency
The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write modes.
Master Write Mode
The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI
2
(or SPI
5
)
timing. Since it gives a maximum frequency above the maximum pad speed (see Section 47.10 “I/Os”
), the maximum SPI frequency is the one from the pad.
Master Read Mode f
SPCK
Max =
SPI
0
( or SPI
3
)
+ t valid t valid is the slave time response to output data after deleting an SPCK edge. For Atmel SPI DataFlash
(AT45DB642D), t valid
(or t v
) is 12 ns Max.
This gives f
SPCK
Max = 39 MHz @ V
DDIO
= 3.3V.
Slave Read Mode
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by setup and hold timings
SPI
7
/SPI
8
(or SPI
10
/SPI given by SPCK pad.
11
). Since this gives a frequency well above the pad limit, the limit in slave read mode is
Slave Write Mode f
SPCK
Max =
SPI
6
( or SPI
9
)
+ t setup t setup is the setup time from the master before sampling data (12 ns).
This gives f
SPCK
Max = 39 MHz @ V
DDIO
= 3.3V.
47.18.1.2 Timing Conditions
Timings are given assuming a capacitance load on MISO, SPCK and MOSI :
Table 47-37. Capacitance Load for MISO, SPCK and MOSI (product dependent)
Corner
Supply Max
3.3V
1.8V
40 pF
20 pF
Min
5 pF
5 pF
47.18.1.3 Timing Extraction
Figure 47-9. SPI Master mode 1 and 2
SPCK
SPI
0
SPI
1
MISO
SPI
2
MOSI
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Figure 47-10.SPI Master mode 0 and 3
SPCK
MISO
MOSI
Figure 47-11.SPI Slave mode 0 and 3
NPCS0
SPI
12
SPCK
MISO
SPI
5
SPI
6
SPI
3
SPI
7
SPI
8
MOSI
Figure 47-12.SPI Slave mode 1 and 2
NPCS0
SPI
12
SPCK
MISO
SPI
9
SPI
10
SPI
11
MOSI
SPI
4
SPI
13
SPI
13
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Figure 47-13.SPI Slave mode - NPCS timings
SPI
14
SPI
6
SPCK
(CPOL = 0)
SPI
12
SPI
9
SPCK
(CPOL = 1)
SPI
16
MISO
Table 47-38. SPI Timings with 3.3V Peripheral Supply
Symbol Parameter
SPI
6
SPI
7
SPI
8
SPI
9
SPI
10
SPI
11
SPI
12
SPI
13
SPI
SPCK
SPI
0
SPI
1
SPI
2
SPI
3
SPI
4
SPI
5
SPI
14
SPI
15
SPI
16
SPI Clock
MISO Setup time before SPCK rises
MISO Hold time after SPCK rises
SPCK rising to MOSI
MISO Setup time before SPCK falls
MISO Hold time after SPCK falls
SPCK falling to MOSI
SPCK falling to MISO
MOSI Setup time before SPCK rises
MOSI Hold time after SPCK rises
SPCK rising to MISO
MOSI Setup time before SPCK falls
MOSI Hold time after SPCK falls
NPCS0 setup to SPCK rising
NPCS0 hold after SPCK falling
NPCS0 setup to SPCK falling
NPCS0 hold after SPCK rising
NPCS0 falling to MISO valid
SPI
15
SPI
13
Conditions
Master Mode
Slave Mode
Min
1.7
0
3.8
0
3.5
0
2.9
2.0
0
2.7
13.3
0
0
12.8
0
0
Max
66
7.4
7.6
12.7
13.3
15.4
ns ns ns ns ns ns ns ns ns ns ns ns
Unit
MHz ns ns ns ns ns
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Table 47-39. SPI Timings with 1.8V Peripheral Supply
Symbol Parameter
SPI
7
SPI
8
SPI
9
SPI
10
SPI
11
SPI
12
SPI
13
SPI
14
SPI
15
SPI
16
SPI
3
SPI
4
SPI
5
SPI
6
SPI
SPCK
SPI
0
SPI
1
SPI
2
SPI Clock
MISO Setup time before SPCK rises
MISO Hold time after SPCK rises
SPCK rising to MOSI
MISO Setup time before SPCK falls
MISO Hold time after SPCK falls
SPCK falling to MOSI
SPCK falling to MISO
MOSI Setup time before SPCK rises
MOSI Hold time after SPCK rises
SPCK rising to MISO
MOSI Setup time before SPCK falls
MOSI Hold time after SPCK falls
NPCS0 setup to SPCK rising
NPCS0 hold after SPCK falling
NPCS0 setup to SPCK falling
NPCS0 hold after SPCK rising
NPCS0 falling to MISO valid
Conditions
Master Mode
Slave Mode
Figure 47-14.Minimum and Maximum Access Time for SPI Output Signal
SPCK
SPI
0
SPI
1
MISO
SPI
2max
MOSI
SPI
2min
Min
3.5
1.8
0.2
4.0
0
3.8
2.2
0
15.9
0
0
14.8
0
0
3.6
0
Max
66
6.7
6.8
16.0
15.8
17.9
ns ns ns ns ns ns ns ns ns ns ns ns
Unit
MHz ns ns ns ns ns
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47.18.2 SSC
47.18.2.1 Timing conditions
Timings are given assuming a capacitance load as defined in
.
Table 47-40. Capacitance Load
Corner
Supply
3.3V
1.8V
47.18.2.2 Timing Extraction
Figure 47-15.SSC Transmitter, TK and TF in output
Max
30 pF
20 pF
TK (CKI =0)
TK (CKI =1)
TF/TD
Figure 47-16.SSC Transmitter, TK in input and TF in output
TK (CKI =0)
SSC
0
TK (CKI =1)
TF/TD
SSC
1
Min
5 pF
5 pF
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Figure 47-17.SSC Transmitter, TK in output and TF in input
TK (CKI=0)
TK (CKI=1)
TF
TD
Figure 47-18.SSC Transmitter, TK and TF in input
TK (CKI=1)
SSC
2
SSC
4
SSC
3
TK (CKI=0)
TF
TD
Figure 47-19.SSC Receiver RK and RF in input
RK (CKI=0)
RK (CKI=1)
RF/RD
SSC
8
SSC
9
SSC
5
SSC
7
SSC
6
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Figure 47-20.SSC Receiver, RK in input and RF in output
RK (CKI=1)
RK (CKI=0)
RD
RF
Figure 47-21.SSC Receiver, RK and RF in output
RK (CKI=1)
RK (CKI=0)
RD
RF
Figure 47-22.SSC Receiver, RK in ouput and RF in input
RK (CKI=0)
SSC
8
SSC
10
SSC
9
SSC
11
SSC
13
SSC
12
RK (CKI=1)
SSC
11
RF/RD
Table 47-41. SSC Timings
Symbol Parameter
SSC
0
SSC
1
TK edge to TF/TD (TK output, TF output)
TK edge to TF/TD (TK input, TF output)
Conditions
Transmitter
1.8V domain
3.3V domain
1.8V domain
3.3V domain
SSC
12
Min
-5.6
-4.6
3.0
2.3
Max
5.8
4.9
15.7
11.4
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Unit ns ns
Table 47-41. SSC Timings (Continued)
Symbol Parameter
SSC
2
SSC
3
SSC
4
SSC
5
SSC
6
TF setup time before TK edge (TK output)
TF hold time after TK edge (TK output)
TK edge to TD (TK output, TF input)
TF setup time before TK edge (TK input)
TF hold time after TK edge (TK input)
Conditions
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
Min
14.0
9.9
0
0
-5.6 (+2 × t
CPMCK
-4.6 (+2 × t
CPMCK
0 t
CPMCK
Max
5.7 (+2 × t
CPMCK
)
4.7 (+2 × t
CPMCK
)
Unit ns ns ns ns ns
SSC
7
TK edge to TD (TK input, TF input)
3.0 (+3 × t
CPMCK
)
2.3 (+3 × t
CPMCK
)
15.5(+3 × t
CPMCK
)
11.1(+3 × t
CPMCK
)
ns
SSC
8
SSC
9
RF/RD setup time before RK edge (RK input)
RF/RD hold time after RK edge (RK input)
Receiver
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
0 t
CPMCK ns ns
SSC
10
RK edge to RF (RK input)
2.6
2.0
15.2
10.9
ns
SSC
11
RF/RD setup time before RK edge (RK output)
1.8V domain
3.3V domain
14.1 - t
CPMCK
10.0 - t
CPMCK ns
SSC
12
RF/RD hold time after RK edge (RK output)
1.8V domain
3.3V domain
t
CPMCK
- 2.5
t
CPMCK
- 1.8
ns
SSC
13
RK edge to RF (RK output)
1.8V domain
3.3V domain
-5.9
-4.9
5.2
4.3
ns
Notes: 1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or
5 or 7 (Receive Start Selection), two Periods of the MCK must be added to timings.
2. For output signals (TF, TD, RF), minimum and maximum access times are defined. The minimum access time is the time between the TK (or RK) edge and the signal change. The maximum access time is the time between the TK edge and the signal stabilization.
illustrates minimum and maximum accesses for SSC0. The same applies to SSC1, SSC4, and SSC7, SSC10 and SSC13.
3. 1.8V domain: V
DDIO
from 1.65V to 1.95V, maximum external capacitor = 20 pF.
4. 3.3V domain: V
DDIO
from 3.0V to 3.6V, maximum external capacitor = 30 pF.
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Figure 47-23.Minimum and Maximum Access Time of Output Signals
TK (CKI =1)
TK (CKI =0)
TF/TD
SSC
0min
SSC
0max
47.18.3 HSMCI
The High Speed MultiMedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD
Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
47.18.4 EMAC
47.18.4.1 Timing conditions
Table 47-42. Capacitance Load on Data, Clock Pads
Supply
3.3V
1.8V
47.18.4.2 Timing constraints
MAX
20 pF
20 pF
Corner
Typical Voltage High
Temperature
20 pF
20 pF
MIN
0 pF
0 pF
Table 47-43. EMAC Signals Relative to EMDC
Symbol Parameter Min (ns) Max (ns)
EMAC
1
EMAC
2
Setup for EMDIO from EMDC rising
Hold for EMDIO from EMDC rising
10
10
EMAC
3
EMDIO toggling from EMDC rising 0
Note: 1. For EMAC output signals, minimum and maximum access times are defined. The minimum access time is the time between the EDMC rising edge and the signal change. The maximum access timing is the time between the EDMC rising edge and the signal stabilizes.
Figure 47-24 illustrates minimum and maximum
accesses for EMAC3.
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Figure 47-24.minimum and maximum access time of EMAC output signals
EMDC
EMAC
1
EMAC
2
EMDIO
EMAC
4
EMAC
5
47.18.4.3 RMII Mode
Table 47-44. EMAC RMII Timings
Symbol Parameter
EMAC
21
EMAC
22
EMAC
23
EMAC
24
EMAC
25
EMAC
26
EMAC
27
ETXEN toggling from EREFCK rising
ETX toggling from EREFCK rising
Setup for ERX from EREFCK rising
Hold for ERX from EREFCK rising
Setup for ERXER from EREFCK rising
Hold for ERXER from EREFCK rising
Setup for ECRSDV from EREFCK rising
EMAC
28
Hold for ECRSDV from EREFCK rising
Note:
.
Figure 47-25.EMAC RMII Mode Signals
EREFCK
ETXEN
ETX[1:0]
ERX[1:0]
ERXER
ECRSDV
EMAC
23
EMAC
24
EMAC
25
EMAC
26
EMAC
27
EMAC
28
EMAC
3 max
EMAC
3 min
EMAC
21
EMAC
22
Min (ns)
4
2
4
2
4
2
Max (ns)
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47.18.5 USART in SPI Mode Timings
47.18.5.1 T iming conditions
Timings are given assuming a capacitance load as defined in
.
Table 47-45. Capacitance Load
Corner
Supply
3.3V
1.8V
47.18.5.2 Timing extraction
Figure 47-26.USART SPI Master Mode
Max
40 pF
20 pF
N SS
S PI
3
CPOL=1
S CK
CPOL=0
S PI
4
MI S O
MO S I
M S B
S PI
4
S PI
1
S PI
2
S PI
0
L S B
S PI
5
Min
5 pF
5 pF
Figure 47-27.USART SPI Slave mode: (Mode 1 or 2)
N SS
S PI
12
S CK
S PI
6
MI S O
S PI
7
MO S I
S PI
8
S PI
1 3
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Figure 47-28.USART SPI Slave mode: (Mode 0 or 3)
N SS
S PI
15
S CK
S PI
9
MI S O
S PI
10
MO S I
S PI
11
Table 47-46. USART SPI Timings
Symbol
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
0
1
2
3
4
5
6
7
8
9
Parameter
SCK Period
Input Data Setup Time
Input Data Hold Time
Chip Select Active to Serial Clock
Output Data Setup Time
Serial Clock to Chip Select Inactive
SCK falling to MISO
MOSI Setup time before SCK rises
MOSI Hold time after SCK rises
SCK rising to MISO
Conditions
Master Mode
Slave Mode
Min
MCK/6
0.5 × MCK + 4.1
0.5 × MCK + 3.8
1.5 × MCK + 0.9
1.5 × MCK + 1.1
1.5 × SCK - 2.0
1.5 × SCK - 2.6
0
0
1 × SCK - 6.7
1 × SCK - 7.5
3.7
2.9
2 × MCK + 3.4
2 × MCK + 3.1
1.6
1.4
3.4
2.7
S PI
14
Max Unit
7.6
8.0
ns ns ns ns ns ns
19.9
16.9
19.4
16.5
ns ns ns ns
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Table 47-46. USART SPI Timings (Continued)
Symbol
SPI
10
SPI
11
Parameter
MOSI Setup time before SCK falls
MOSI Hold time after SCK falls
Conditions
Min
2 × MCK + 2.9
2 × MCK + 2.8
2.1
1.8
SPI
12
NPCS0 setup to SCK rising
2.5 × MCK + 1.4
2.5 × MCK + 1.2
SPI
13
NPCS0 hold after SCK falling
1.5 × MCK + 2.5
1.5 × MCK + 2.2
SPI
14
NPCS0 setup to SCK falling
2.5 × MCK + 0.9
2.5 × MCK + 0.8
SPI
15
NPCS0 hold after SCK rising
1.5 × MCK + 2.1
1.5 × MCK + 1.9
Notes: 1. 1.8V domain: V
DDIO
from 1.65V to 1.95V, maximum external capacitor = 20 pF
2. 3.3V domain: V
DDIO
from 3.0V to 3.6V, maximum external capacitor = 40 pF.
Max ns ns ns
Unit ns ns ns
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47.19 Two-wire Interface Characteristics
Table 47-47 describes the requirements for devices connected to the Two-wire Serial Bus.
For timing symbols, please refer to Figure 47-29
.
Table 47-47. Two-wire Serial Bus Requirements
Symbol Parameter
V
IL
V
IH
V
HYS
V
OL t
R
Input Low-voltage
Input High-voltage
Hysteresis of Schmitt Trigger Inputs
Output Low-voltage
Rise Time for both TWD and TWCK
Conditions
—
—
—
3 mA sink current
Min
-0.3
0.7 × V
DDIO
0.150
—
20 + 0.1C
b
t
OF
C i
f
TWCK
Rp t
LOW t
HIGH t
HD;STA t
SU;STA t
HD;DAT t
SU;DAT t
SU;STO t
HD;STA
Output Fall Time from V
IHmin
to V
ILmax
Capacitance for each I/O Pin
TWCK Clock Frequency
Value of Pull-up Resistor
Low Period of the TWCK Clock
High Period of the TWCK Clock
Hold Time (repeated) START condition
Set-up Time for a Repeated START condition
Data Hold Time
Data Setup Time
Setup Time for STOP condition
Bus free time between a STOP and START condition
10 pF < C b
< 400 pF
—
— f
TWCK
≤ 100 kHz f
TWCK
> 100 kHz f
TWCK
≤ 100 kHz f
TWCK
> 100 kHz f
TWCK
≤ 100 kHz f
TWCK
> 100 kHz f
TWCK
≤ 100 kHz f
TWCK
> 100 kHz f
TWCK
≤ 100 kHz f
TWCK
> 100 kHz f
TWCK
≤ 100 kHz f
TWCK
> 100 kHz f
TWCK
≤ 100 kHz f
TWCK
> 100 kHz f
TWCK
≤ 100 kHz f
TWCK
> 100 kHz f
TWCK
≤ 100 kHz f
TWCK
> 100 kHz
20 + 0.1C
b
—
0
(V
DDIO
- 0.4V) ÷ 3mA
(V
DDIO
- 0.4V) ÷ 3mA
t
HIGH t
HIGH t
HIGH t
HIGH
0
0 t
LOW
- 3 × t
t
LOW
- 3 × t
t
HIGH t
HIGH t
HIGH t
HIGH
Notes: 1. Required only for f
TWCK
> 100 kHz.
2. C b
= capacitance of one bus line in pF. Per I2C Standard, C b
Max = 400 pF
3. The TWCK low period is defined as follows: t low
= ((CLDIV × 2 CKDIV ) + 4) × t
MCK
4. The TWCK high period is defined as follows: t high
= ((CHDIV × 2 CKDIV ) + 4 × t
MCK
5. t
CP_MCK
= MCK bus period.
Max
0.3 × V
DDIO
V
CC
+ 0.3
–
0.4
300
250
10
400
1000ns ÷ C b
300ns ÷ C b
—
—
—
—
—
—
—
—
3 × t
3 × t
—
—
—
—
—
— ns
µ s ns ns
µ s
µ s
µ s
µ s
µ s
µ s
µ s
µ s
µ s pF kHz
Ω
Ω
µ s
µ s
µ s
µ s
Unit
V
V
V
V ns
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Figure 47-29.Two-wire Serial Bus Timing t of t
LOW
SCL t
SU;STA t
HD;STA
SDA t
HIGH t
HD;DAT t
LOW t
SU;DAT t r t
SU;STO t
BUF
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48.
Mechanical Overview
48.1 217-ball BGA Package
Figure 48-1. 217-ball BGA Package Drawing
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Table 48-2. 217-ball BGA Package Characteristics
Moisture Sensitivity Level
Table 48-3. Package Reference
JEDEC Drawing Reference
JESD97 Classification
3
MO-205 e1
Table 48-1. Device and 217-ball BGA Package Maximum Weight
450 mg
Table 48-4. Package Information
Ball Land
Solder Mask Opening
0.43 mm
0.30 mm
±
±
0.05
0.05
48.2 Marking
All devices are marked with the Atmel logo and the ordering code.
Additional marking may be in one of the following formats:
YYWW V
XXXXXXXXX
ARM where
“YY”: manufactory year
“WW”: manufactory week
“V”: revision
“XXXXXXXXX”: lot number
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49.
SAM9X35 Ordering Information
Table 49-1. SAM9X35 Ordering Information
Ordering Code Package
AT91SAM9X35-CU BGA217
Package Type
Green
Temperature Operating Range
Industrial
-40°C to 85°C
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50.
SAM9X35 Errata
50.1 External Bus Interface (EBI)
50.1.1 EBI: Data lines are Hi-Z after reset
Data lines are Hi-Z after reset. This does not affect boot capabilities neither on NOR nor on NAND memories.
Problem Fix/Workaround
None.
50.2 Reset Controller (RSTC)
50.2.1 RSTC: Reset during SDRAM Accesses
When a Reset occurs (user reset, software reset) the SDRAM clock is turned off. Inopportunately, if this occurs at the same time as a SDRAM read access, the SDRAM maintains the data until the restart of the SDRAM clock.
This leads to a data bus conflict and affects adversely the boot memories connected on the EBI:
NAND Flash boot functionality, if the system boots out of the internal ROM.
NOR Flash boot, if the system boots on an external memory connected on the EBI CS0.
Problem Fix/Workaround
Two workarounds are available:
1.
Boot from Serial Flash or Data Flash on SPI.
2.
Connect the NAND Flash on D16-D23 and set NFD0_ON_D16 to 1 in the CCFG_EBICSA register.
Warning!
Due to databus sharing, workaround 2 prohibits connecting another device on the EBI, even if VDDNF equals
VDDIOM.
50.3 Static Memory Controller (SMC)
50.3.1 SMC: SMC DELAY I/O Registers are write-only
Contrary to what is stated in the datasheet, the SMC DELAY I/O Registers are Write-only.
Problem Fix/Workaround
None.
50.4 USB High Speed Host Port (UHPHS) and Device Port (UDPHS)
50.4.1 UHPHS/UDPHS: Bad Lock of the USB High speed transceiver DLL
The DLL used to oversample the incoming bitstream may not lock in the correct phase, leading to a bad reception of the incoming packets.
This issue may occur after the USB device resumes from the Suspend mode.
The DLL is used only in the High Speed mode, meaning the Full Speed mode is not impacted by this issue.
This issue may occur on the USB device after a reset leading to a SAM-BA connection issue.
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Problem Fix/Workaround:
To prevent a SAM-BA execution issue, the USB device must be connected via a USB Full Speed hub to the PC.
At application level, the DLL can be re-initialized in the correct state by toggling the BIASEN bit (high -> low -> high) when resuming from the Suspend mode.
The BIASEN bit is located in the CKGR_UCKR register in PMC user interface.
The function below can be used to generate the pulse on the bias signal.
void generate_pulse_bias(void)
{ unsigned int * pckgr_uckr = (unsigned int *) 0xFFFFFC1C;
* pckgr_uckr &= ~AT91_PMC_BIASEN;
* pckgr_uckr |= AT91_PMC_BIASEN;
}
In the USB device driver, the generate_pulse_bias function must be implemented in the “USB end of reset” and “USB end of resume” interrupts.
50.5 Timer Counter (TC)
50.5.1 TC: The TIOA5 signal is not well connected
The TIOA5 enable signal is not well connected internally, it is shared with the TIOB5 enable signal.
TIOB5 is working normally.
TIOA5 is working normally in Capture Mode.
Waveform Mode is not available for TIOA5 if the TC_CMR.ETRGEDG bit is set to 1, 2 or 3.
Problem Fix/Workaround
None.
50.6 LCD Controller (LCDC)
50.6.1 LCDC: LCDC PWM is not usable
When slow clock is selected as the source clock to feed PWM with (CLKPWMSEL in LCDC_LCDCFG0), the output waveform generated is corrupted. When the MCK is selected, the prescaler (PWMPS in LCDC_LCDCFG6) is not sized to generate the PWM output in a range of 200 Hz - 1 kHz.
Problem fix/Workaround
Use standalone PWM output instead of LCDC embedded PWM.
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50.7 Boot Strategy
50.7.1 NAND Flash Boot Detection using ONFI parameters does not work
During NAND Flash initialization, the ONFI parameters detection may not work correctly.
This can lead to an incorrect configuration of ECC settings, reading wrong data from the NAND Flash memory, and the unability to boot from this memory.
Problem Fix/Workaround
When programming the bootable program in the NAND Flash, always use the header method, with any NAND Flash memory, ONFI compliant or not.
50.8 Real Time Clock (RTC)
50.8.1 RTC: Interrupt Mask Register cannot be used
Interrupt Mask Register read always returns 0.
Problem Fix/Workaround
None.
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Revision History
In the tables that follow, the most recent version of the document appears first.
Doc. Rev.
11055E Comments
General editorial and formatting changes throughout document
Updated first line of document title on page 1
(was “AT91SAM ARM-based Embedded MPU”; is “ARM-based Embedded
MPU”)
Figure 2-1 “SAM9X35 Block Diagram”
: flipped diagram right for ease of viewing
Section 4. “Package and Pinout”
Table 4-2 “SAM9X35 I/O Type Assignment and Frequency”
:
- GPIO: replaced “All PIO lines except the following” with “All PIO lines except GPIO_CLK, GPIO_CLK2, and GPIO_ANA”
- EBI: replaced “All Data lines (Input/output) except the following” with “All data lines (Input/output)”
- EBI_O: replaced “All Address and control lines (output only) except the following” with “All address and control lines
(output only) except EBI_CLK”
Table 4-3 “Pin Description BGA217” : removed “PU” reset state for SHDN signal
Section 5. “Power Considerations”
Figure 6-1 “SAM9X35 Memory Mapping” : replaced “SCKCR” with “SCKC_CR”; replaced “BSCR” with “BSC_CR”
Section 7. “System Controller”
“BSC_CR”
Configuration Register (SCKC_CR)”; corrected instance of “BSCR” to “BSC_CR”
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Section 25. “Bus Matrix (MATRIX)”
Updated Table 25-1 “List of Bus Matrix Masters” :
- Master 9 (was ISI DMA; is LCD DMA)
- added Master 11 (Reserved)
Section 25.6 “Register Write Protection”
: changed title (was “Write Protect Registers”) and revised contents
Deleted section “Chip Configuration User Interface” (register CCFG_EBICSA is now found in
Table 25-4 “Register Mapping” :
- defined offset 0x002C as reserved
- defined offsets 0x0104–0x011C as reserved
- at offset 0x0120, inserted register CCFG_EBICSA
- defined offsets 0x0124–0x01FC as reserved
Section 25.7.2 “Bus Matrix Slave Configuration Registers”
: inserted sentence about write protection
Section 25.7.3 “Bus Matrix Priority Registers A For Slaves” :
- updated register range in Name (was MATRIX_PRAS0...MATRIX_PRAS8; is MATRIX_PRAS0...MATRIX_PRAS9)
- inserted sentence about write protection
Section 25.7.4 “Bus Matrix Priority Registers B For Slaves” :
- updated register range in Name (was MATRIX_PRBS0...MATRIX_PRBS8; is MATRIX_PRBS0...MATRIX_PRBS9)
- inserted sentence about write protection
Section 25.7.5 “Bus Matrix Master Remap Control Register” : inserted sentence about write protection
Section 25.7.6 “EBI Chip Select Assignment Register”
: changed reset value from 0x00000000 to 0x00000200; updated
NFD0_ON_D16 and DDR_MP_EN bit descriptions
Updated Section 25.7.7 “Write Protection Mode Register”
Updated Section 25.7.8 “Write Protection Status Register”
Section 26. “External Bus Interface (EBI)”
Minor formatting and editorial changes throughout
Controller”
Section 26.5.3.4 “Power supplies”
: in second paragraph, replaced instance of “D16-D32” with “D16–D31”
Section 45. “Ethernet MAC 10/100 (EMAC)”
Table 45-5 “Pin Configuration”
: replaced MII configuration with RMII configuration
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Section 47. “Electrical Characteristics”
Table 47-2 “DC Characteristics”
: added input impedance characteristics
Table 47-5 “Processor Clock Waveform Parameters”
: added footnote “For DDR2 usage only, there are no limitations to LP-
DDR, SDRAM and mobile SDRAM”
frequencies lower than 8 MHz” below figure
Table 47-18 “I/O Characteristics”
: added values; replaced “40 pF” with “20 pF” in footnote defining 3.3V domain
47.14.2 “Backup Power Supply POR Characteristics”
Table 47-29 “Core Power Supply POR Characteristics”
: added conditions to parameter “Threshold Voltage Falling”
Promoted Section 47.15 “Power Sequence Requirements” to heading level 2 (was level 3)
Table 47-32 “Zero Hold Mode Use Maximum System Clock Frequency (MCK)”
: in values columns, changed header “Min” to “Max”
Added Section 47.19 “Two-wire Interface Characteristics”
Updated Section 50.2.1 “RSTC: Reset during SDRAM Accesses”
Added Section 50.7 “Boot Strategy”
Added Section 50.8 “Real Time Clock (RTC)”
Change
Request
Ref.
Doc. Rev.
11055D Comments
Introduction:
Section 1. “Features” , added DBGU in the Peripherals list.
Section 8.2 “Peripheral Identifiers”
, added data on System Controller Interrupt in
MATRIX:
Section 25.7.6.1 “EBI Chip Select Assignment Register” , updated the description of a warning note in
“DDR_MP_EN: DDR Multi-port Enable” .
DMAC:
Added Section 31.2.1 “DMA Controller 0” and
Section 31.2.2 “DMA Controller 1” .
SPI:
Added references on SPKC in Section 35.2 “Embedded Characteristics”
.
Errata:
Added Section 50.5 “Timer Counter (TC)” .
rfo
8516
8532
8526
8541
8517
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Change
Request
Ref.
Introduction:
Section 6.3.3 “DDR2SDR Controller”
, replaced LPDDR2 with LPDDR.
Added “Write Protected Registers” in the peripherals list in Section 1. “Features” .
Added “4-bank” references to the DDR2 characteristics in
Section 1. “Features” , Section 1. “Features”
and
Section 6.3.3 “DDR2SDR Controller”
.
8213
8282
8368
list.
8403
Section 6.3.2 “Static Memory Controller”
, replaced “8- or 16-bit Data Bus” with “8-, 16-, or 32-bit Data Bus”.
8420
Replaced TSADVREF with ADVREF in Figure 2-1 “SAM9X35 Block Diagram” .
8146
8454
Boot Startegies:
, added
Table 11-1 “External Clock and Crystal Frequencies allowed for Boot
Sequence (in MHz)” and the corresponding text below the table.
Section 11.4.1 “NVM Boot Sequence” , replaced “Boot Sequence Register (BSCR)” with “Boot Sequence
Configuration Register (BSC_CR)” and updated the acronym of this register in the entire section.
Added a reference to the “Boot Sequence Controller (BSC)” section.
Replaced “BSCR value” with “BOOT Value” in the heading line in
Table 11-2 “Boot Sequence Configuration
.
8269 rfo
BSC:
Section 12.4.1 “Boot Sequence Configuration Register” :
- updated the BSC_CR register table
- added a reference to the “NVM Boot Sequence” section in
Section 12.2 “Embedded Characteristics”
, removed “Product-dependent order” line.
Added Section 12.3 “Product Dependencies”
.
Updated the acronym of Boot Sequence Configuration Register from “BSCR” to “BSC_CR”.
7996
8184 rfo
AIC:
8017
RSTC:
register in
.
8271
RTC:
Section 15.6 “Real-time Clock (RTC) User Interface”
, updated the peripheral name from “Real Time Clock” to
“Real-time Clock” and replaced the Reserved Register line “0x30-0xF8” with two lines “0x30–0xC4” and “0xC8–
0xF8” (Reserved Register) in Table 15-1 “Register Mapping”
.
WDT:
Added the 4th paragraph “If the watchdog is restarted...” in Section 17.4 “Functional Description”
.
Section 17.5.3 “Watchdog Timer Status Register”
, added a note in
.
Updated Section 17.2 “Embedded Characteristics”
.
SHDWC:
Removed AMBA references from Section 18.2 “Embedded Characteristics”
.
, removed redundant Figure 18-2. Sutdown Controller Block Diagram.
8280
8128:
8218 rfo
8454
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11055C Comments
GPBR:
register table and in the description below.
Change
Request
Ref. (1)
7990
SCKC:
are located not in Slow Clock Control Register (SCKCR) but in Slow Clock Configuration Register (SCKC_CR).
8322
Fixed Figure 20-1 “Block Diagram” for better representation.
rfo
CKGR:
Section 21.6.2 “Switch from Internal 12 MHz RC Oscillator to the 12 MHz Crystal”
, fixed a typo in the sequence order: MAINRDY --> MOSCXTS .
reference in
Figure 21-6 “Divider and PLLA Block Diagram” .
Updated Crystal Oscillator range from “3 to 20 MHz” to “12 to 16 MHz” in Section 21.2 “Embedded
,
,
Figure 21-3 “Main Clock Block Diagram”
,
Section 21.6.7 “Main Clock Oscillator Selection” , and Section 21.6.8 “Main Clock
8327
8401
8413
PMC:
, removed the “/1, /2” divider block in
Figure 22-2 “General Clock Block Diagram”
.
Section 22.13 “Power Management Controller (PMC) User Interface” , updated the CKGR_MOR reset value
(0x0100_0008 --> 0x0000_0008) in Table 22-3 “Register Mapping”
.
PIO:
Section 23.4.4 “Interrupt Generation”
, updated the 1st paragraph.
Section 23.5.10 “Input Edge/Level Interrupt”
, replaced “...to the Advanced Interrupt Controller (AIC)” with “...to the interrupt controller” in the paragraph “When an input Edge or Level is detected...”.
8401
8447
8324
EBI:
Section 26.5.1 “Hardware Interface”
, fixed typos in Table 26-4 “EBI Pins and External Device Connections”
: the power supply of A20, A23, A24, A25, NCS2, NCS4 and NCS5 is VDDNF and not VDDIOM.
Updated EBIx pin data in Table 26-2 “EBI Pins and Memory Controllers I/O Lines Connections”
and added A13 as SDRAMC pin in the A15 line in
Table 26-4 “EBI Pins and External Device Connections” .
PMERRLOC:
PMERRLOC_SIGMAx [x=0..24] register table.
8179 rfo
PMECC:
Figure 27-2 “Software/Hardware Multibit Error Correction Dataflow” , “READ PAGE” and “PROGRAM PAGE”
positions swapped in the flow chart.
7495
set to Zero.”
Section 27.2 “Embedded Characteristics”
, added a line about supporting 8-bit Nand Flash data bus.
PMECC_ISR register table.
8403 rfo
8339
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11055C Comments
DDRSDRC:
Section 30.2 “Embedded Characteristics”
, removed duplicate reference to DDR2-SDRAM.
Change
Request
Ref. (1)
SMC:
Controlled by NWE (WRITE_MODE = 1)” and
Section 29.9.4.2 “Write is Controlled by NCS (WRITE_MODE =
.
7925
8146
DMAC:
.
Updated names:
- ‘Buffer Complete Interrupt’ --> ‘Buffer Transfer Completed Interrupt’
- ‘Chained Buffer Interrupt’ --> ‘Chained Buffer Transfer Completed Interrupt’
7393
- ‘Transfer Complete Interrupt’ --> ‘Chained Buffer Transfer Completed Interrupt’
- KEEPON[n] --> KEEPx, STALLED[n] --> STALx, ENABLE[n] --> ENAx, SUSPEND[n] --> SUSPx, RESUME[n] -
-> RESx, EMPTY[n] --> EMPTx.
- Read the Channel Enable register --> Read the Channel Handler Status register.
Detailed bitfield acronyms when missing.
Updated Section 31.2 “Embedded Characteristics”
:
- updated the list of embedded characteristics
- removed Section 31.2.1 DMA Controller 0 and Section 31.2.1 DMA Controller 1.
rfo
replaced the wrong values 0x444D4143 and 0x50494F with 0x444D41, and replaced ‘(“DMAC” in ASCII)’ with
‘(“DMA” in ASCII)’.
8143
8404
Section 31.7.2 “DMAC Enable Register” ,
Section 31.7.15 “DMAC Channel x [x = 0..7] Descriptor Address
, Section 31.7.16 “DMAC Channel x [x = 0..7] Control A Register” , and
rfo
- “ENABLE: General Enable of DMA”
- “DSCR_IF: Descriptor Interface Selection”
- “DONE: Current Descriptor Stop Command and Transfer Completed Memory Indicator”
Updated the last paragraph in
Section 31.4.4.3 “Ending Multi-buffer Transfers” .
8441
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11055C Comments
Change
Request
Ref. (1)
UDPHS:
Section 32.4 “Typical Connection”
, completed a note below
Figure 32-2 “Board Schematic” .
Section 32.7 “USB High Speed Device Port (UDPHS) User Interface”
, removed duplicated names in fields and created separated view for UDPHS Control and Status Registers in:
-
Section 32.7.9 “UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)”
-
Section 32.7.10 “UDPHS Endpoint Control Enable Register (Isochronous Endpoints)”
-
Section 32.7.11 “UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints)”
- Section 32.7.12 “UDPHS Endpoint Control Disable Register (Isochronous Endpoint)”
- Section 32.7.13 “UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints)”
- Section 32.7.14 “UDPHS Endpoint Control Register (Isochronous Endpoint)”
- Section 32.7.15 “UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints)”
- Section 32.7.16 “UDPHS Endpoint Set Status Register (Isochronous Endpoint)”
- Section 32.7.17 “UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints)”
- Section 32.7.18 “UDPHS Endpoint Clear Status Register (Isochronous Endpoint)”
- Section 32.7.19 “UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)”
- Section 32.7.20 “UDPHS Endpoint Status Register (Isochronous Endpoint)”
Renamed ER_CRC_NTR bitfield to ERR_CRC_NTR.
Added ISOENDPT right-hand side qualifier to alternate register definitions in
,
,
,
. Fixed typos.
7986
8396
8405
Section 32.2 “Embedded Characteristics”
: removed Figure 32-1. USB Selection and Table 32-1. UDPHS
Endpoint Description (see
instead).
Added Section 32.6.1 “UTMI Transceivers Sharing”
(extracted from
Section 32.2 “Embedded Characteristics”
).
notes and the text below (extracted from Section 32.2 “Embedded Characteristics” ).
rfo
UHPHS:
33.2.2 OHCI including Figure 33-2 Board Schematics to Interface UHP Device Controller.
8104,
8236
Added Section 33.4 “Typical Connection” and
Section 33.6 “Functional Description”
(extracted from
Schematic to Interface UHP High-speed Host Controller” .
HSMCI:
Section 34.14.12 “HSMCI Status Register” , removed the first phrase in the “NOTBUSY: HSMCI Not Busy”
bitfield description (not only for Write operations now).
8394
Section 34.6.3 “Interrupt” , replaced references to NVIC/AIC with “interrupt controller”.
Section 34.14.7 “HSMCI Block Register”
, replaced BCNT bitfield table with the corresponding description and updated Warning note in
“BCNT: MMC/SDIO Block Count - SDIO Byte Count”
.
.
and 4 now), and updated the description of this bitfield in
“CHKSIZE: DMA Channel Read and Write Chunk Size”
8431
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11055C Comments
Change
Request
Ref. (1)
SPI:
Replaced references to “Advanced Interrupt Controller” with “Interrupt Controller”.
updated the table in
: reserved bits are from 9 to 15.
Section 35.7.3.5 “Peripheral Selection”
, corrected a cross-reference for the footnote.
with “WPEN” and added a list of write-protected registers.
Section 35.8.11 “SPI Write Protection Status Register”
, replaced “SPIWPVSRC” with “WPVSRC” and
“SPIWPVS” with “WPVS” and updated the description of “WPVS: Write Protection Violation Status”
.
Section 35.2 “Embedded Characteristics”
, removed redundant text line and updated the line “Programmable
Transfer Delay Between Consecutive ...”.
Section 35.8.1 “SPI Control Register”
, removed the last phrase in
.
TC:
The number of identical 32-bit Timer Counter channels is not three anymore but six.
Section 36.2 “Embedded Characteristics”
, updated the line on input/output signals.
Table 36-5 “Register Mapping” .
Updated the order of register description sections to match the order in
.
7513
7931
8025
8136
8210
8362
8648 rfo
PWM:
Section 37.5.2 “Power Management”
, updated the second paragraph.
Section 37.2 “Embedded characteristics”
, updated the last line of the list.
8105 rfo
TWI:
Section 38.1 “Description” , fixed a typo: removed “20” at the end of the 1st paragraph.
Added three paragraphs in
Section 38.8.5 “Master Receiver Mode”
.
Added Table 38-11 “Master Read Clock Stretching with Multiple Data Bytes” .
Added Section 38.11 “Write Protection System”
.
Added Section 38.8.7.1 “Data Transmit with the DMA” and Section 38.8.7.2 “Data Receive with the DMA”
.
Updated Section 38.12 “Two-wire Interface (TWI) User Interface”
:
-
- added Section 38.12.12 “TWI Write Protection Mode Register” and
Section 38.12.13 “TWI Write Protection
- added a phrase specifying when the TWI_SMR and TWI_CWGR registers can be written in
and Section 38.12.5 “TWI Clock Waveform Generator Register”
.
7921
8426
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Doc. Rev.
11055C Comments
Change
Request
Ref. (1)
USART:
Section 39.8 “Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface” :
- updated descriptions of US_CR, US_MR, US_IER, US_IDR, US_IMR, and US_CSR registers in:
Section 39.8.1 “USART Control Register”
Section 39.8.3 “USART Mode Register”
Section 39.8.5 “USART Interrupt Enable Register”
Section 39.8.8 “USART Interrupt Disable Register”
Section 39.8.11 “USART Interrupt Mask Register”
Section 39.8.14 “USART Channel Status Register”
- added sections:
Section 39.8.2 “USART Control Register (SPI_MODE)”
8012
Section 39.8.4 “USART Mode Register (SPI_MODE)”
Section 39.8.6 “USART Interrupt Enable Register (SPI_MODE)”
Section 39.8.7 “USART Interrupt Enable Register (LIN_MODE)”
Section 39.8.9 “USART Interrupt Disable Register (SPI_MODE)”
Section 39.8.10 “USART Interrupt Disable Register (LIN_MODE)”
Section 39.8.12 “USART Interrupt Mask Register (SPI_MODE)”
Section 39.8.13 “USART Interrupt Mask Register (LIN_MODE)”
Section 39.8.15 “USART Channel Status Register (SPI_MODE)”
Section 39.8.16 “USART Channel Status Register (LIN_MODE)”
Section 39.7.4.1 “ISO7816 Mode Overview”
, removed the last phrase about missing ISO7816 inverted mode support.
Section 39.8.3 “USART Mode Register” , updated the MAX_ITERATION field description.
“ONE” and added the corresponding description.
Added Section 39.8.28 “USART LIN Baud Rate Register” .
8097
8212
8398
Figure 39-39 “Header Transmission” and
Figure 39-42 “Slave Node Synchronization”
reformatted for readability.
introduction text.
Section 39.6 “Product Dependencies” , added rows for USART3 in Table 39-3 “I/O Lines”
.
rfo
UART:
Section 40.4.3 “Interrupt Source”
, replaced the term “Nested Vectored Interrupt Controller” and/or its acronym
“NVIC” with “Interrupt Controller”.
Section 39.2 “Embedded Characteristics”
, removed the 2nd line with redundant information.
Section 39.1 “Description” , updated the 2nd paragraph.
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11055C Comments
Change
Request
Ref. (1)
CAN:
Added information on Write Protected Registers:
- added a line in Section 41.2 “Embedded Characteristics”
- added rows for Write Protect Mode Register (CAN_WPMR) and Write Protect Status Register (CAN_WPSR) in
- added Section 41.8.5 “Write Protected Registers” ,
Section 41.9.12 “CAN Write Protection Mode Register”
and
Section 41.9.13 “CAN Write Protection Status Register”
- added a phrase specifying when a register can be written (restricted by CAN Write Protection Mode Register) in:
8215
Section 41.9.1 “CAN Mode Register”
Section 41.9.6 “CAN Baudrate Register”
Section 41.9.14 “CAN Message Mode Register”
Section 41.9.15 “CAN Message Acceptance Mask Register”
Section 41.9.16 “CAN Message ID Register”
Updated offsets for reserved registers in
Table 41-6 “Register Mapping” :
- 0x002C - 0x01FC --> 0x002C - 0x00E0
- added a row: - 0x00EC - 0x01FC
Updated the register table and the corresponding bitfield name in:
Section 41.9.7 “CAN Timer Register”
Section 41.9.8 “CAN Timestamp Register”
Section 41.9.14 “CAN Message Mode Register”
Section 41.9.18 “CAN Message Status Register”
Section 41.9.1 “CAN Mode Register” , fixed a typo in “LPM: Disable/Enable Low Power Mode”
(‘w’ --> ‘0’).
.
Section 41.6.1 “I/O Lines” , added Table 41-2 “I/O Lines”
.
ADC:
Section 42.8.15 “ADC Compare Window Register”
, added two paragraphs about programming LOWTHRES and
HIGHTHRES bitfields depending on the LOWRES bitfield settings (ADC Mode Register).
8045
Increased the size of XPOS/XSCALE/YPOS/YSCALE fields from 10 to 12-bit in
Touchscreen X Position Register”
,
Section 42.8.20 “ADC Touchscreen Y Position Register”
“ADC Touchscreen Pressure Register”
.
8229
the last phrase of the third paragraph.
8357
Section 42.2 “Embedded Characteristics”
, added the value of Conversion Rate in the 2nd line.
8385
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11055C Comments
SSC:
Section 44.7.1.1 “Clock Divider”
, removed Table 43-4 related to
Figure 44-5 “Divided Clock Generation”
(duplicated data in Section 44.7.1.4 “Serial Clock Ratio Considerations”
).
Section 44.6.3 “Interrupt” , replaced AIC references with “interrupt controller”.
Section 44.9 “Synchronous Serial Controller (SSC) User Interface”
:
- updated descriptions of CKS, CKO, and CKG bitfields in:
Section 44.9.3 “SSC Receive Clock Mode Register”
Section 44.9.5 “SSC Transmit Clock Mode Register”
- updated register tables and a description of FSOS bitfield in:
Section 44.9.4 “SSC Receive Frame Mode Register”
Section 44.9.6 “SSC Transmit Frame Mode Register”
Section 44.9.14 “SSC Interrupt Enable Register”
, fixed a typo (0=0= --> 0=).
Change
Request
Ref.
7303
8466
Electrical Characteristics:
8098
Table 47-8 “Crystal Characteristics” .
Section 47.2 “DC Characteristics” , updated RPULLUP parameter characteristics in Table 47-2 “DC
.
Replaced “Input Leakage Current” with “Input Peak Current” in Table 47-26 “Analog Inputs”
.
8147 rfo
Mechanical Overview:
Updated the table title in
Table 48-4 “Package Information”
.
8186
Errata:
Section 50.1 “External Bus Interface (EBI)”
, updated the problem description and fix/ workaround.
Removed “Boot Sequence Controller (BSC)” section (see “Boot Strategies” and “BSC” above for the related modifications).
8250
Removed sections concerning PIO and RTC.
Added Section 50.2 “Reset Controller (RSTC)” , Section 50.3 “Static Memory Controller (SMC)”
, and
“USB High Speed Host Port (UHPHS) and Device Port (UDPHS)” .
Added Section 50.6 “LCD Controller (LCDC)” .
8321 rfo
(1)
Doc. Rev.
11055B Comments
System Controller:
,
“SAM9X35 System Controller Block Diagram”
, DDR sysclk --> DDRCK.
ADC:
Section 42. “Analog-to-Digital Converter (ADC)” updated to show Touchscreen information
DMAC:
FIFO size table removed from
Section 31.1 “Description” , as the size depends on DMAC0 (see
Section 31.2.1
“DMA Controller 0” ) and DMAC1 (see Section 31.2.2 “DMA Controller 1” ).
MATRIX:
Section 25.7.6.1 “EBI Chip Select Assignment Register” , description of NFD0_ON_D16 bitfield updated.
Change
Request
Ref.
rfo
7987
8004
8008
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Doc. Rev.
11055B Comments
Change
Request
Ref. (1)
PMC:
Section 22.2 “Embedded Characteristics”
, 266 MHz DDR system clock --> 133 MHz DDR system clock
Then DDR system clock --> DDR clock.
Figure 22-2 “General Clock Block Diagram”
:
- Prescaler /1,/2,/4,.../64 --> Prescaler /1,/2,/3,/4,.../64 (for Master Clock Controller).
- SysClk DDR --> 2x MCK, and connection added above with /2 block and DDRCK.
Section 22.3 “Master Clock Controller”
, ...and the division by 6 --> ...and the division by 3
Section 22.7 “LP-DDR/DDR2 Clock”
, sentences with ‘ SysClk’ removed.
Section 22.13.11 “PMC Master Clock Register” :
- Value 7 for PRES field no more reserved, now with CLOCK_DIV3, Selected clock divided by 3.
- MDIV field, references to ‘SysClk DDR’ removed (x4).
UHPHS:
“OHCI” , Figure 32-2 “Board Schematics to Interface UHP Device Controller” added, with an introducing sentence.
7975 rfo
7974
8006
8016
Electrical Characteristics:
Section 47.12 “USB Transceiver Characteristics”
added (extracted from SAM9G20 - 6384E: Section 41.7, Figure
41-23 and Table 41-46).
8016
Errata:
Section 50.1 “Boot Sequence Controller (BSC)” added as the BSC_CR register does not conply with the programmer description.
Section 50.5 “USB High Speed Host Port (UHPHS)” removed.
7996 rfo
Doc. Rev.
11055A Comments
1st issue
Note: 1. “rfo” indicates changes requested during the document review and approval loop.
Change
Request
Ref.
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Table of Contents
4. Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Overview of the 217-ball BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5. Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Peripheral Signal Multiplexing on I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9. ARM926EJ-S™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10. Debug and Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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12. Boot Sequence Controller (BSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.4 Boot Sequence Controller (BSC) User Interface . . . . . . . . . . . . . . . . . . . . . . 67
13. Advanced Interrupt Controller (AIC) . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.10 Advanced Interrupt Controller (AIC) User Interface . . . . . . . . . . . . . . . . . . . . 82
14. Reset Controller (RSTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
15. Real-time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
16. Periodic Interval Timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
17. Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
17.5 Watchdog Timer (WDT) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
18. Shutdown Controller (SHDWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
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18.7 Shutdown Controller (SHDWC) User Interface. . . . . . . . . . . . . . . . . . . . . . . 155
19. General Purpose Backup Registers (GPBR) . . . . . . . . . . . . . . . . . 159
19.3 General Purpose Backup Registers (GPBR) User Interface . . . . . . . . . . . . 160
20. Slow Clock Controller (SCKC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
20.4 Slow Clock Configuration (SCKC) User Interface . . . . . . . . . . . . . . . . . . . . 164
21. Clock Generator (CKGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
21.8 UTMI Phase Lock Loop Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
22. Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . 175
22.13 Power Management Controller (PMC) User Interface . . . . . . . . . . . . . . . . . 185
23. Parallel Input/Output (PIO) Controller . . . . . . . . . . . . . . . . . . . . . . 209
23.7 Parallel Input/Output Controller (PIO) User Interface . . . . . . . . . . . . . . . . . . 222
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24. Debug Unit (DBGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
25. Bus Matrix (MATRIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
26. External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
27. Programmable Multibit ECC Controller (PMECC) . . . . . . . . . . . . . 316
27.6 Programmable Multibit ECC Controller (PMECC) User Interface. . . . . . . . . 328
28. Programmable Multibit ECC Error Location Controller
(PMERRLOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
28.5 Programmable Multibit ECC Error Location Controller (PMERRLOC) User
29. Static Memory Controller (SMC) . . . . . . . . . . . . . . . . . . . . . . . . . . 358
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29.16 Static Memory Controller (SMC) User Interface . . . . . . . . . . . . . . . . . . . . . . 393
30. DDR SDR SDRAM Controller (DDRSDRC) . . . . . . . . . . . . . . . . . . 402
30.6 Software Interface/SDRAM Organization, Address Mapping . . . . . . . . . . . . 425
30.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface . . . . . . . . . . . . . 429
31. DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
32. USB High Speed Device Port (UDPHS) . . . . . . . . . . . . . . . . . . . . 502
32.7 USB High Speed Device Port (UDPHS) User Interface . . . . . . . . . . . . . . . . 527
33. USB Host High Speed Port (UHPHS) . . . . . . . . . . . . . . . . . . . . . . 570
34. High Speed MultiMedia Card Interface (HSMCI) . . . . . . . . . . . . . . 576
34.8 High Speed MultiMedia Card Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
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34.14 High Speed MultiMedia Card Interface (HSMCI) User Interface . . . . . . . . . 603
35. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . 630
36. Timer Counter (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
37. Pulse Width Modulation Controller (PWM) . . . . . . . . . . . . . . . . . . 692
37.7 Pulse Width Modulation Controller (PWM) User Interface . . . . . . . . . . . . . . 701
38. Two-wire Interface (TWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
39. Universal Synchronous Asynchronous Receiver Transmitter
(USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
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39.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User
40. Universal Asynchronous Receiver Transmitter (UART) . . . . . . . . . 850
40.6 Universal Asynchronous Receiver Transmitter (UART) User Interface . . . . 858
41. Controller Area Network (CAN) Programmer Datasheet . . . . . . . . 868
41.9 Controller Area Network (CAN) User Interface . . . . . . . . . . . . . . . . . . . . . . 894
42. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . 924
42.8 Analog-to-Digital Converter (ADC) User Interface . . . . . . . . . . . . . . . . . . . . 946
43. Software Modem Device (SMD) . . . . . . . . . . . . . . . . . . . . . . . . . . 974
44. Synchronous Serial Controller (SSC) . . . . . . . . . . . . . . . . . . . . . . 976
44.9 Synchronous Serial Controller (SSC) User Interface . . . . . . . . . . . . . . . . . . 993
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45. Ethernet MAC 10/100 (EMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
45.6 Ethernet MAC 10/100 (EMAC) User Interface . . . . . . . . . . . . . . . . . . . . . . 1028
46. LCD Controller (LCDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
47. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240
48. Mechanical Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274
49. SAM9X35 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 1276
50. SAM9X35 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277
50.4 USB High Speed Host Port (UHPHS) and Device Port (UDPHS) . . . . . . . 1277
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Atmel Corporation
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