Vertex Detector Electronics:
ODE Pre-Prototype
User Manual
Issue:
Revision:
1
2
Reference:
Created:
Last modified:
IPHE 2000-008
28 February 2000
28 April 2000
Prepared By:
Yuri Ermoline
Vertex Detector Electronics: ODE Pre-Prototype
User Manual
Abstract
Ref: IPHE 2000-008
Issue: 1 Revision: 2
Date: 28 April 2000
Abstract
This document is a user manual for the ODE pre-prototype module (ODE-PP). The module is
under development and new features are implemented in every new version.
Document Status Sheet
Table 1 Document Status Sheet
1. Document Title: Vertex Detector Electronics: ODE Pre-Prototype
2. Document Reference Number: IPHE 2000-008
3. Issue
page ii
4. Revision
5. Date
6. Implemented features
1
0
2 March 2000
VME slave interface A24/D32, CSR0, CSR1, FIFO,
VME trigger, PDU control, FADC data capture mode
1
1
22 March 2000
VME reset, TTC trigger, added 24-bit trigger counter
1
2
31 March 2000
Changed CSR1 format, added 12-bit FIFO counter,
trigger counter reduced to 12 bits
1
2
28 April 2000
Added IPHE reference number
Vertex Detector Electronics: ODE Pre-Prototype
User Manual
Table of Contents
Ref: IPHE 2000-008
Issue: 1 Revision: 2
Date: 28 April 2000
Table of Contents
1 General description .
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2.1 FADC data capture (MODE = 0) .
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1.1
1.2
1.3
1.4
1.5
1.6
1.7
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Module clock . . . . . .
Module reset . . . . . .
Module triggering . . . . .
VME slave interface . . . .
TTCrx board . . . . . .
FADC card . . . . . . .
FADC clock phase adjustment
2 Module operation .
3 References .
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10
page iii
Vertex Detector Electronics: ODE Pre-Prototype
User Manual
Glossary
Glossary
page iv
FADC
Flash Analog to Digital Converter
FIFO
First-In First-Out
FPGA
Field Programmable Gate Array
ODE
Off-Detector Electronics
TTC
Timing, Trigger and Control
Ref: IPHE 2000-008
Issue: 1 Revision: 2
Date: 28 April 2000
Vertex Detector Electronics: ODE Pre-Prototype
User Manual
1 General description
Ref: IPHE 2000-008
Issue: 1 Revision: 2
Date: 28 April 2000
1 General description
Vertex detector ODE pre-prototype (ODE-PP) module is designed for the read-out of up to 4
analog multiplexed signals from the vertex detector front-end chip(s) at 40 MHz. ODE-PP is a
6U VME module, 2-unit wide. It consists of a main VME board and 3 daughter cards as shown
on the Figure 1.
Config
ch3
FADC
ch2
8
8
FPGA
FLEX10K50
D32
VMEbus
A24
Buffers
TTCrx
32
ch1
FADC
ch0
8
8
32
FIFO
2K*32
5
PDU
Clock
Figure 1
The main VME board provides (see also Figure 2):
•
Altera FLEX PFGA EPF10K50RC240-3 (2880 logic elements and 10 embedded array
blocks of RAM, 2K bit each [1]), connector for FPGA configuration via down-load
cable and socket for the configuration EPROM (EPC1PC8).
•
Data buffers, address comparators and Base address rotary switches for the VMEbus
slave interface (A24/D32) which is used as a control and monitoring interface to the
module.
•
2K*32 bit of FIFO (4 SyncFIFO chips Cypress CY7C4231, 15 ns access time [2]).
•
40 MHz internal clock oscillator, programmable delay unit for FADC clock phase
adjustment (PDU15F-1 from Data Delay Devices [3]), LEMO connector for the BUSY
output signal (TTL open collector, active low), the Reset button and the green LED.
•
Connectors to a TTCrx board carrying a TTCrx chip [4] - the receiver chip of the
Timing, Trigger and Control (TTC) system, CERN microelectronics group design.
•
2 connectors for FADC cards (2-channels, 8-bit, 40 MHz, based on AD9059 from
Analog Devices [5]) and voltage regulators for FADC cards analog power.
One of the FADC cards can be replaced by the ECS interface prototype or the trigger
pre-orocessor interface prototype.
page 1
Vertex Detector Electronics: ODE Pre-Prototype
User Manual
1 General description
TTCrx board connectors
Ref: IPHE 2000-008
Issue: 1 Revision: 2
Date: 28 April 2000
Jumper Osc Conf EPROM FPGA PDU
LED
Rotary
switches
FIFOs
SW2 SW3
BUSY
SW4 SW5
Reset
TTCrx
board
VMEbus
Ch #1
Ch #0
FADC
card
FADC card connectors
Figure 2
page 2
Analog power
Vertex Detector Electronics: ODE Pre-Prototype
User Manual
1 General description
Ref: IPHE 2000-008
Issue: 1 Revision: 2
Date: 28 April 2000
1.1 Module clock
The ODE-PP main board can be driven by internal clock from the 40 MHz clock oscillator or
by the clock, delivered by the TTCrx chip (40 MHz). The clock source can be chosen by the
jumper on the ODE-PP main board (see Figure 2):
•
Jumper inserted - internal 40 MHz clock.
•
Jumper removed - external TTCrx 40 MHz clock.
1.2 Module reset
The ODE-PP main board can be reset by:
•
Pressing push-botton “Reset” on the front panel.
•
Dataless writing into VMERESET register from the VMEbus (see 1.4).
The module registers, counters and FIFO read/write pointers are set to zero.
1.3 Module triggering
PDE-PP module can be triggered:
•
from the VMEbus by writing ‘1’ into CSR1(0).
•
from the TTCrx chip using TTC system (see 1.5).
The triggers are counted by the 12-bit TRIGGER Counter, which can be read from CSR1(15..4).
1.4 VME slave interface
The module uses the P1 and P2 VME connectors and works in A24/D32 mode. Block Transfer
mode is not implemented. The recognized Address Modifier codes are 3E, 3D, 3A, 39
(standard access).
The modules’s 16-bit Base Address (VME address bits A24..A08) can be selected by 4 internal
rotary switches (see Figure 2) in the range (0000-FFFF) hex:
•
SW2: VME address bits A23..A20
•
SW3:VME address bits A19..A16
•
SW4:VME address bits A15..A12
•
SW5:VME address bits A11..A08
The address map of the PDE-PP module is shown below:
page 3
Vertex Detector Electronics: ODE Pre-Prototype
User Manual
1 General description
Ref: IPHE 2000-008
Issue: 1 Revision: 2
Date: 28 April 2000
VME address bits A07..A00
Register
“00” hex
CSR0
“04” hex
CSR1
“08” hex
VMERESET
“10” hex
FIFO
Control/Status Register 0 (CSR0) - $00
Data Bit(s)
Write
Read
Comments
D4..D0
PDU control
PDU status
FADC clock phase adjustment
D7..D5
No action
“000”
D9..D8
MODE control
MODE status
D31..D10
No action
“00..00”
Operation modes
CSR0 provides storage for the static parameters - programmable delay line control value for
the FADC clock phase adjustment (see 1.7) and module operation modes (see 2).
Control/Status Register 1 (CSR1) - $04
Data Bit(s)
Write
Read
Comments
D0
VMETRIG
MODBUSY
Start data acquisition from VMEbus
D3..D1
No action
“000”
D15..D4
No action
TRIGCNTR
12-bit TRIGGER counter
D16
No action
FIFO Full
if ‘1’ - FIFO is full
D17
No action
FIFO Empty
if ‘1’ - FIFO is empty
D19..D18
No action
“00”
D31..D20
No action
FIFOCNTR
12-bit FIFO counter
CSR1 is used to start data acquisition (see 2) and to read the status of the module registers and
memories.
VMERESET Register - $08
Dataless write to this register generates ODE-PP module reset. The CSR0, FIFO read/write
pointers, FIFO and TRIGGER counters are set to zero.
page 4
Vertex Detector Electronics: ODE Pre-Prototype
User Manual
1 General description
Ref: IPHE 2000-008
Issue: 1 Revision: 2
Date: 28 April 2000
FIFO (VME read/write access) - $10
FIFO can be accessed from VMEbus for test purposes.
Data Bit(s)
Write
Read
Comments
D31..D0
VME data
FIFO data
FIFO test
FIFO (FADC data capture / VME data read)
After data acquisition FADC data can be read from the FIFO via VMEbus.
Data Bit(s)
Write
Read
Comments
D7..D0
FADC ch 0
FIFO data
FADC data after data acquisition
D15..D8
FADC ch 1
FIFO data
-”-
D23..D16
FADC ch 2
FIFO data
-”-
D31..D24
FADC ch 3
FIFO data
-”-
1.5 TTCrx board
The TTCrx board contains the TTCrx chip (non radhard ES2 version), the optical connector
with an integrated detector/preamplifier and some other components. The input optical
signal from the TTC transmitter crate carries 40 MHz clock and trigger (TTCTRIG) signals.
In order to operate the TTCrx board the TTC transmitter (TTCvx [6]) and the TTC control
module (TTCvi [7]) are necessary, as shown on the Figure 3.
Clock
TTCvi
TTCvx
ECL
ECL
Ch A
Trigger
ODE-PP
Clock
optical
TTCrx
NIM
Ch B
Trigger
(L0A)
VME (Reset, commands)
Figure 3
The 40.00 MHz clock signals (ECL levels) and the Trigger signal (NIM level) are provided by
the external logic.
page 5
Vertex Detector Electronics: ODE Pre-Prototype
User Manual
1 General description
Ref: IPHE 2000-008
Issue: 1 Revision: 2
Date: 28 April 2000
1.6 FADC card
The 2 channels FADC card contain input link receivers, amplifiers, analog-to-digital converter
AD9059 (dual 8-bit, 60 MSPS A/D converter) and output buffers.
The input signals from the LEMO connectors (EPG.0B.302.HLN) are differential in the range
from 0 to 1 Volts. The upper LEMO connector on the upper FADC card corresponds to FADC
channel #3 and the lower LEMO connector on the lower FADC cardon - to FADC channel #0.
The 50-pin connector provides the digital and analog power, clock and data enable signals for
the FADC card from the ODE-PP main board and the 2*8-bit output data from the FADC card
output buffers to the ODE-PP main board. The connector layout is shown below:
page 6
Signal
Pin #
Pin #
Signal
-5V_ANALOG
1
2
-5V_ANALOG
CND_ANALOG
3
4
GND_ANALOG
+5V_ANALOG
5
6
+5V_ANALOG
CLOCK
7
8
-
ENABLE_B
9
10
FADC_B(7)
FADC_B(6)
11
12
FADC_B(5)
FADC_B(4)
13
14
FADC_B(3)
FADC_B(2)
15
16
FADC_B(1)
FADC1_B0)
17
18
-
-
19
20
-
-
21
22
-
-
23
24
-
-
25
26
-
POWER_DOWN
27
28
-
-
29
30
-
-
31
32
-
ENABLE_A
33
34
FADC_A(0)
FADC_A(1)
35
36
FADC_A(2)
FADC_A(3)
37
38
FADC_A(4)
FADC_A(5)
39
40
FADC_A(6)
FADC0_A7)
41
42
-
-
43
44
-
GND_DIGITAL
45
46
GND_DIGITAL
-
47
48
-
+5V_DIGITAL
49
50
+5V_DIGITAL
Vertex Detector Electronics: ODE Pre-Prototype
User Manual
1 General description
Ref: IPHE 2000-008
Issue: 1 Revision: 2
Date: 28 April 2000
1.7 FADC clock phase adjustment
The clock phase for both FADC cards can be adjusted using programmable delay unit
(PDU15F-1, 5-bit digitally programmable delay line) on the ODE-PP main board. The delay
from the input clock to the PDU (clock on the ODE-PP main board) to the output clock to the
FADC cards depends on the PDU control code - CSR0(4-0):
Delay = Inherent Delay + Increment Delay * Control Code
where Inherent Delay = 9 ns, Increment Delay = 1 ns. The codes for different delay values are
given in the table below:
Delay(ns)
Code
Delay(ns)
Code
Delay(ns)
Code
0
10
9
00
18
09
1
11
10
01
19
0A
2
12
11
02
20
0B
3
13
12
03
21
0C
4
14
13
04
22
0D
5
15
14
05
23
0E
6
16
15
06
24
0F
7
17
16
07
25
10
8
18
17
08
The PDU control code is set to zero after power on and reset.
page 7
Vertex Detector Electronics: ODE Pre-Prototype
User Manual
2 Module operation
Ref: IPHE 2000-008
Issue: 1 Revision: 2
Date: 28 April 2000
2 Module operation
Before starting data acquisition the following parameters have to be set:
•
PDU control code - CSR0(4..0) - defines the FADC clock delay relatively to the main
board clock.
•
ODE-PP operation mode - CSR0(9..8). The following modes are valid:
•
MODE=0 - FADC data capture
•
MODE=1 - reserved.
•
MODE=2 - reserved.
•
MODE=3 - reserved.
The data acquisition is started by sending the trigger signal to the module from two possible
sources:
•
VMETRIG is generated by writing ‘1’ into CSR1(0) from the VMEbus.
•
TTCTRIG is generated by the TTCrx chip upon receiving the trigger signal from the
TTC transmitter (see 1.5).
The triggers are counted by the 12-bit TRIGGER Counter, which can be read from CSR1(15..4).
The trigger signals also set to zero the 12-bit FIFO counter.
During the data acquisition:
•
The VME write to CSR0, CSR1 and FIFO and VME read from FIFO is disabled
(however module responds to these VME cycles). VME read from CSR0 and CSR1 is
allowed.
•
CSR0: write - disabled, read - allowed.
•
CSR1: write - disabled, read - allowed.
•
FIFO: write - disabled, read - disabled.
•
VMERESET: write - allowed.
•
MODBUSY is asserted and can be checked by reading CSR1(0).
•
BUSY output signal (TTL open collector, active low) on the front panel LEMO
connector is asserted.
•
12-bit FIFO counter counts a number of data words, written into FIFO and can be
read via CSR1(31..20).
2.1 FADC data capture (MODE = 0)
During this mode the output data from the FADC cards are written into the FIFO every clock
cycle until the FIFO is full (after 2K clock cycles or 51.2 µs).
The status of the ODE-PP module (MODBUSY) and the FIFO (FIFO full, FIFO empty and
page 8
Vertex Detector Electronics: ODE Pre-Prototype
User Manual
2 Module operation
Ref: IPHE 2000-008
Issue: 1 Revision: 2
Date: 28 April 2000
FIFO counter) can be checked via CSR1 during and after data capture. The FADC data can be
read from the FIFO via the VMEbus interface after data capture.
page 9
Vertex Detector Electronics: ODE Pre-Prototype
User Manual
3 References
Ref: IPHE 2000-008
Issue: 1 Revision: 2
Date: 28 April 2000
3 References
[1]
FLEX 10K Embedded Programmable Logic Family Data Sheet, ver. 4.01, June 1999.
http://www.altera.com/document/ds/dsf10k.pdf
[2]
CYPRESS, CY7C4231 2Kx9 Sync FIFO.
http://www.cypress.com/cypress/prodgate/fifo/cy7c4231.html
[3]
5-Bit Programmable Delay Line.
http://www.datadelay.com/pdu15f.pdf
[4]
TTCrx Reference Manual. J.Christiansen, A.Marchioro and P.Moreira, Version 2.2.
http://pcvlsi5.cern.ch:80/MicDig/ttc/MANUAL22.PDF
[5]
Analog Devices. Products & Datasheets. Selection Guides.
http://www.analog.com/support/standard_linear/selection_guides/adc_high.html
[6]
TTCvx. Technical description and users manual. P.Gallno, Draft, May 21, 1999.
http://www.cern.ch/TTC/TTCvxManual1a.pdf
[7]
TTCvi. TTC-VMEbus INTERFACE, Ph.Farthouat, P.Gallno, Rev. 1.5.
http://www.cern.ch/TTC/TTCviSpec.pdf
page 10