STD 7000 7803 Z-80 Processor Card USER`S MANUAL

STD 7000
7803
Z-80 Processor Card
USER'S MANUAL
o
o
NOTICE
The information in this document is provided for reference only. Pro-Log does not assume any
liability arising out of the application or use of the information or products described herein.
This document may contain or reference information and products protected by copyrights or
patents and does not convey any license under the patent rights of Pro-Log, nor the rights of
others.
Printed in U.S.A. Copyright © 1981 by Pro-Log Corporation, Monterey, CA 93940. All rights
reserved. However, any part of this document may be reproduced with Pro-Log Corporation
cited as the source.
o
()
7803
Z-80 Processor Card
USER'S MANUAL
c
•
11/81
o
7803 USER'S MANUAL
TABLE OF CONTENTS
SECTION
1
2
3
4
5
6
7
TITLE
PRODUCT OVERVIEW
THE STO BUS
STO BUS Summary
7803 Pin Utilization
Control Bus Signal Table
Processor Status Signals
Dynamic RAM Control
7803 SPECIFICATIONS
Power Requirements
Drive Capability and Loading
Clock Generator
Timing Specifications and Waveforms
Mechanical
Environmental
Z80 ARCHITECTURE AND INSTRUCTION SET
Z80 Programming Model
Program Compatibility with 8080, 8085
STD Instruction Mnemonics
Z80 Instruction Set
Interrupts
PROGRAM INSTRUCTION TIMING
Introduction
Machine Cycles
WAIT States
DMA Mode
Instruction Timing Table
Instruction Timing Example
MEMORY.AND I/O MAPPING AND CONTROL
Memory Addressing
12K-Byte Onboard Memory
Input/Output Port Addressing
PROGRAM AND HARDWARE DEBUGGING
Microprocessor Logic State Analysis
Ins tructi on 0 i agnos tic Tab l-es
M824 System Analyzer
PAGE
1
2
6
18
32
o
39
44
APPENDIX A
7803 STRAPPING OPTIONS
52
APPENDIX B
SCHEMATIC AND ASSEMBLY DIAGRAMS
55
o
7803
Z-80 PROCESSOR CARD
This card combines a buffered and fully expandable
Z-80 microprocessor with onboard RAM and PROM
sockets.
The 7803 includes 1K byte of RAM with sockets for
up to 4K bytes and sockets for up to 8K bytes of
ROM or EPROM. An STD BUS system using the
7803 card can be expanded to the full Z-80 memory
and 1/0 capability. The 7803 STD BUS interface
may be disabjed for DMA app 1 tea t ions.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
o
Z-80 Processor
4096 bytes RAM capacity (2114)
1024 bytes RAM included
8192 bytes ROM capacity on board (2716
EPROPt1)
3 State Address, Data, Control Bus
Crystal controlled 400 ns clock
Power-on reset or pushbutton reset input
Dynamic RAM refresh control
All IC's socketed
Single +5V operation
Use Pro-Log 01004 1Kx8 memories
(two 2114L's)
DATA lUI
(Do.D7)
AODREII.US
(Ao.A15)
~
DATA.US
..
MeMRO·
NMIRO·o--.....- C l
IORO"
RAM
3Kd
INTAO·o--.....-CI
PflOCIISOR
R!FRESH"
RO"
ZIO
IUIRO·o--.....-CI
WR·
ADDRESS
WAITRO" o - -.....- C I
INTAK"
t
IUIAK"
MCSYNC"
ITATUI'"
CN".L·
(EXT CLK)
IYSRESI!T"
MIM!X·
3-STATE
IUS IUFnRS
PeRUn-o-----<l
•
7103
"'NDICAns ACTIVE LOW LOGIC
PROCESSOR
SHADING INDICATES SOCKETS ONLY
FIGURE ,
7803 BLOCK DIAGRAM
1
loup·
SECTION TWO -
o
THE STO BUS
The STO BUS standardizes the physical and electrical aspects of modular a-bit
microprocessor card systems, providing a dedicated, orderly interconnect scheme,
The STO BUS is dedicated to internal communication and power distribution between
cards, with all external communication made via I/O connectors which are suitable
to the application.
The standardized pinout and 56-pin connector lends itself
to a bussed motherboard that al lows any card to work in any slot.
As the system processor and primary system control card, the 7803 is responsible
for maintaining the signal functionality defined by the STO BUS standard.
A complete copy df the STO BUS standard is contained in the SERIES 7000 STO BUS
TECHNICAL MANUAL, available from Pro Log Corporation, 2411 Garden Road, Monterey,
California 93940.
STO BUS Summary
The 56-pin STO BUS is organized into five functional groups of backplane signals:
1- Logic Power Bus
2. Data Bus
3. Address Bus
4. Control Bus
5. Auxi lary Power
pins
pins
pins
pins
pins
1-6
7-14
15-30
31-52
53-56
Figure ~ shows the organization and pinout of the STD BUS with mnemonic function
and signal flow relative to the 7803 Processor card:
""
LOGIC
,
.-oWER
3
aus
5
OATA
1
9
aus
AGDRESS
aus
''nn
'1
13
03
02
01
00
In,Out
In'Out
'n,Out
In/Out
1S
A7
11
19
21
23
A8
A5
Out
Out
Out
A4I
Out
A3
A2
A1
Out
Out
Out
25
27
29
CONTROL
aus
Out
Low Order
L.ow Order
L.ow Order
L.ow Order
Low Order
L.ow Order
Add,... Bus
Adar_ Bus
~ Bus
~ Bus
Addr. . Bus
20
A9
Out
AddreIs Bua
30
32
RO'
~
Oul
Out
CPU Status
40
Out
Out
Sus Acknowtedge
Interrupt Actlnowiedge
Walt Request
50
MEMRO'
MEMEX'
MCSVNC·
STATUS O·
SUSRO·
INTRO'
NMIRO·
PBRESET'
CNTRL"
Out
Out
Write to Memory or I/O
I/O Add,... Select
I/O ExpansIOn (GN Q)
Ref,.." Tim,n,
52
PCI
54
56
.lUX GNO
.lUX-V
Out
'"
SVSRESET'
Out
CLOCK'
PeO
Oul
POW.R
eua
07
De
Out
ar.-
System Reset
Cloca trom Processor
PrM)"ty Cha.n Out
AUX a'ound (8ulMd)
AUX Poe..... ('12 V~t. DC)
'L.ow 1....,.. Act've InGec.MOt
2
22
24
28.
28
3&
38
42
"
46
48
os
AI
+5 Votts OC f Bussed)
-5 Volts OC
A15
A1 ..
A13
A12
A11
A10
Out
Oul
41
·5V
18
11
WA'
45
47
49
51
a
Oiglt.. GtOu"'O I Bussed)
L.OW'Order Addr. . Bua
Low Ora. Addr_ Bu.
'OAO·
43
e
'Inn
0..
31
39
GNO
DESCJUPTION
141
33
10EXp·
.5V
~
A.OW
10
12
Ou,
REFRESH'
STATUS l'
SUSAK'
INTAK'
WAITRO·
2
IIGMI.
Low Order 0 ... Sua
Low Order Oaaa Sua
Low
0 •• Sua
Low Order o.a Bus
AO
lS
37
.s von. DC (SuIMd)
Oigit.. Ground (Buu.d)
·5 Votta DC
_UIOMIC
4[)
'n'Out
In'Out
In'Out
'n'Out
Out
Out
Out
Out
Out
Out
Out
Out
In
'"'"
'"
''nn
HiQft Order Oata
Hi;ft Order Oata
Higf'l Order Oata
Hq. Order Oata
Bus
Bus
Bus
Bus
High Order AC:dress
Hign Order Address
High Order Address
Hi9" Order Address
Hi9ft Order AOdress
Hi9" Order AOdress
Hi9ft Order Address
High Order Address
Sua
Sua
Sus
au.
au.
Sus
Sus
Bu.
Read to Memory or '/0
Memory Aemr.SI Select
Memory E"oanslon (GN 0)
CPU M.cnlne CyCle Sync
CPU Status
Bus Request
'nterruot Reauest
Non·Maskaci~ tnr.rrlJC:II
Pus" Button
~eut
.lUX Timing <Ey;r c.\..Ol.~}
Priority CtI~I'" In
AUX Ground
AUX ~''''
BUSSed)
12 I/on, DCI
o
W,/,I, JI+i:"'.l4tH'b
STD BUS Pin Utilization by 7803
Since the STD BUS standard does not specify timing or require that all available
pins be used, the timing and signal allocation assumes many of the characteristics
of the microprocessor type used.
The timIng characteristics of the 7803 are those
of its Z80 microprocessor, with LSTTL buffering added to enhance the card's drive
capability.
The allocation of STO BUS lines for the 7803 is given below.
1. Logic Power Bus: +5V (pins 1,2) and Logic Ground (Pins 3,4) supply operating
power to the 7803. Pins 5 and 6 are open.
2. Data Bus: Pins 7 through 14 form an 8-bit bidirectional 3-state data bus as
shown in Figure 2 . High level active data flows between the 7803 and its
peripheral cards over this bus. When the 7803 fetches data from its onboard
memory sockets, this data also appears on the STO Data Bus.
Except during Direct Memory Access (DMA) operations, the 7803 controls the
direct i on of data flow wi th its 11EHRQ,*, I ORQ*, RO*, WR*, and I NTAK* contro I
signal outputs. Peripheral cards are required to release the data bus to the
high impedance state except when addressed and directed to drive the data bus
by the 7803.
c
TRe 7·803 re 1eases the Data Bus when SUSAK* is act i ve in reSDonse to RIISRn*,
os· in DMA operat ions.
3. Address Bus: Pins 15 through 30 form a 16-bit 3-state address bus as shown in
Figure
• The 7803 drives high level active 16-bit memory addresses over
these lines, and 8-bit I/O port addresses over the eight low-order address
lines (AO through A7 on pins IS, 17, 19, 21, 23, 25, 27 and 29).
The 7803 releases the Address Bus when BUSAK* is active in response to BUSRQ,*,
as in DMA operations.
4. Control Bus:
Pins 31 through 52 provide control signals for memory, I/O,
interrupt, and fundamental system operations.
Figure 3 summarizes these
signals and shows how they are derived fromZ80
signals.
The 7803 releases the Control Bus during BUSAK* in response to BUSRQ,*, except
for the following output signals: MEHEX*, 10EXP*, BUSAK*, PCO, CLOCK*.
5. Auxilary Power Bus: Pins 53 through 56 are not used by the 7803 and are
electrically open.
The 7803 meets all of the signal requirements of the STO BUS standard.
timing information and specifications are in Section 5
•
3
Detailed
o
MNEMONIC
WR-;':
RO-;'c
IORQ*
MEMRQ*
PIN
IN/OUT
31
32
33
34
Out#
Out#
Out#
OUt#
FUNCTION
HOW
Write to memory or I/O
Read from memory or I/O
AO-A7 hold valid I/O address
AO-Al5 hold valid memory
~ss
IOEXP*
MEMEX*
REFRESH*
MCSYNC*
STATUS 1*
STATUS 0*
BUSAK*
BUSRQ*
INTAK*
DERIVE~
Z80 NAME
[\.JR* ]
[RO*]
[I ORQ*]
[MEMRQ*]
I/O expansion control
Memory expansion control
Dynamic RAM refresh control
One pulse per machine cycle
User-removeabJe ground
User-removeable qround
37
38
Out
Out
Out#
Out#
39
Out#
Active during opcode fetch
(Not used)
Acknowledges BUSRQ*
[Ml*]
E1ec t rica 11y open
[BUSAK*]
35
36
40
-
4r
Out
42
In
Bus request for DMA;
synchronous processor halt and
3-state driver disable
Acknowledges INTRQ* and
rep 1aces [( RO*)- MEMRQ*)] to read
interrupt vector
Maskable interrupt request
Synchronous processor halt
Nonmaskable interrupt request
System power-on and pushbutton
reset output
Pushbutton reset input
Time state clock (1/2 crystal
frequency)
Outl
43
INTRQ*
44
~AITRQ*
45
NMIIiQ*
46
~YSRESET*
47
PBRESET*
CLOCK*
48
49
In
Out
CNTRL*
50
In
External clock input (2 times
desired time state frequency)
JPC I/PCO
52/51
In/Out
Priori ty chain
In
'lIn
In
Out#
[RFSH*]
[RO*]+[WR*]+
( ( IORQ*) (M 1*) ]
[BUSRQ*]
[ ( IORQ*) (M 1*) ]
o
[INT*]
[WA IT*]
[NMI*]
Onboard one-shot
Onboard oscillator
PCI shorted to PCO; no
,other 7803 connection
* Low level active
# OU%put buffer disabled when BUSAK* active
[] Denotes equivalent Z80 signal name
FIGURE
3
7803 CONTROL BUS SIGNALS
4
o
o
7803 Processor Status:
MCSYNC*, STATUS 1*
HCSYNC* and STATUS 1* signals provide status information which is peculiar
to the z80 microprocessor. These signals are useful for displaying processor
status in logic signal analyzers, and can be used to drive Z80 peripheral
chips and systems designed to work with the z80 specifically. The use of these
signals is not recommended in systems where microprocessor device-type independence
is a design goal.
HCSYNC* is obtained by ORing the read, write, and interrupt acknowledge signals.
Thus HCSYNC* occurs once in each machine cycle (Section 3 ), and can be used
to allow a logic signal analyzer to select a specific cycle within a multi-cycle
instruction for analysis. The timing of MCSYNC* varies according to machine
cyc 1e type.
STATUS 1* is equivalent to the z80's H1 signal, which denotes the opcode fetch
or interrupt acknowledge cycle (M~ is ANDed with 10RQ* internally to produce tNTAK,
and externally ~ith. MEMRQ* to denote oQcode fetch.).
Note that the Z~O has both l-byte and 2-byte opcoaes (2-byte opcodes are identified
by a first byte equal to CB, DO, ED, or FD hexadecimal). Accordingly, the
processor asserts STATUS 1* in each opcode byte, or twice per instruction cycle
for these instructions.
Dynamic RAM Control:
REFRESH*
The Z80 microprocessor chip is specifically designed for refreshing standard
l6-oin dynamic RAM chips with multiplexed address lines
and 4K x 1 or 16K x 1 internal organization. These devices can be refreshed
trans~arently
~uring the opcode fetch memory cycle without complex processor
synchronization circuitry and without delaying processor ~nstruction execution
time.
The REFRESH* output signal occurs during T3 and T4 of the opcode fetch cycle,(fJg_~ 8}
and is used to Indicate that a memory refresh address is present on the Address Bus.
The address is composed of a presettable, autocounting 7-bit address (AO-A6) which
is the lower seven bits of the Z80's R (Refresh) Register, and an eighth bit (A7)
which is the R Register's most significant bit and is program-settable in the
high or low state.
Eor_ more_information on dvnamjc RAM refreshing,
following publications:
refer to the
Interfacing 16 Pin Dynamic RAMs to the Z80A Microprocessor
available from Zilog, 10460 Bubb Road, Cupertino, CA 95014
Z80 Dynamic RAM Interfacing Techniques
available from Mostek, 1215 W. Crosby Rd., Carrollton, TX 75006
e
5
--=iWi=_C"QAIiiA
e
'ii at
1'1
P¥¥ 44 R
SECTION
o
7803 SPECIFICATIONS
3
Power Reguirements
RECOMMENDED OPERAT I NG LI MITS
i PARAMETER
MIN
TYP I MAX
Vcc (Note 1)
Icc (Note 2)
NOTES:
4.75
I
j
-
!
5.00· 5.25
I
1. 15
1. 65
I
ABSOLUTE NONOPERATING LIMITS
UNITS
MAX
MIN
0
5.50
Vol ts
-
-
Ampere
FIGURE 4: 7803 POWER SUPPLY SPECIFICATION
1. In order to guarantee correct operation, the
following power supply considerations apply:
a. Vcc rise must be monotonic, rising from
+O~50 Volt to +4.75 Volts in 10 ms or
less ..
b. If Vee drops below +4.75 Volts at any
time it must be reduced· to less than
+0.50 Volt before restoration to the
specified operating range.
2. Icc specification assumes that all EPROM and
RAM sockets on the 7803 are loaded. Subtract
75 mA per 27.16 EPROM and '50 mA per 2114L RAM
for each device not used.
o
The 2114L devices require 10 milliseconds minimum after initial
power-on for stabilization of internal bias oscillators. The 7803's power-on
reset one-shot provides adequate stabilization delay only if Vee risetime is
less than 10 milliseconds.
Drive Capability and Loading
The 7803's STO BUS Edg.e Connector Pin List (Fis.ure 5 ) gjyes i..oput toading
and output driv~ capability in LSTTL loads as defined by the SERIES .7.0004TECHNICAL MANUAL.
In general, input lines and disabled 3-stateoutputs present 5 lSTTL lODut loads
maximum (one LSTTL or MOS input plus 4.7K pullup resistor). Output lines can drive
a minimum of 50 LSTTl loads. Pins whiCh are unspecified in Figure· 5.
are electrically open.
Exceptions to the general loading rules are:
a.
PBRESET* input, which is 15 LSTTL loads.
b.
CLOCK* output, which can drive 10 LSTTL loads
c.
PCI and PCO, which are connected together
but to nothing else on the 7803.
6
o
o
F IGURE 5
7803 STD BUS EDGE CONNECTOR PINOUT AND LOADING
STDneo 3 EDGE CONNECTOR PIN LIST
PIN NUMBER
PIN NUMBER
OUTPUT (LSTTL DRIVE)
INPUT (LSTTL LOADS)
OUTPUT (LSTTL DRIVE)
INPUT (LSTTL LOADS)
MNEMONIC
MNEMONIC
+5 VOLTS
IN
2
1
IN
GROUND
IN
4
3
IN
6
8
10
5
7
-5V
Ii
~n
D6
5
50
05
;
liD
04
5
c:n
12
14
A15
5
~n
16
A14
5
1i0
A13
5
A12
5
5
5
5
5
5
5
50
50
50
50
50
50
50
50
34
50
50
19 50
21
50
23
50
25 50
27 50
29 50
31 5:>
33 5)
OUT
36
35
OUT
50
38
37
40
42
39
41
44
43
50
50
50
50
46
45
Al1
A10
A9
AS
RD·
MEMRO'
MEMEX·
(GROUND)
MCSYNC·
5
STATUS O'
BUSAO'
PBRESET'
CNTRl· - EXT ClK IN
5
5
5
15
5
PCI
IN
INTRO'
NMIRQ·
•
-5V
D7
11
50
50
50
13
50
9
15
17
18
20
22
24
26
28
30
32
+5 VOLTS
GROUND
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
03
02
01
DO
A7
A6
AS
A4
A3
A2
A1
AO
WR*
IORO'
IOEXp·
(GROUND)
REFRESH'
STATUS 1·
BUSAK*
INTAK'
-5
WAITRO·
5
SYSRESET'
48
47
50
50
49
10
52
51 OUT
PCO
AUX GNO
54
53
AUX -V
56
55
AUX GNO
AUX +V
·Oesignates Active Low Level Logic
7
CLOCK'
>< • • • • • • • _ _ • • • _ _ • • • • • • • • • • • • • • -
•• - . - ••• - ••••••••••• - .
_
•• _ - • • _ _ • • • • • _
••• _ _ •••• _ ••••••••••
o
Clock Generator
The 7803's clock oscillator serves as the primary timing element in a 7803-based
system. The osci 11ator ' s output is divided by two to drive the ZaO microprocessor,
producing the time state clock. The time state clock's period is the shortest
program-related period of interest in the system. Instruction execution times
are computed as whole multiples of the time state clock period ~ectton 51~
The 7803 is shipped with a crystal installed which sets the system's time state
period. If desired, the user can substitute a slower crys·tal or replace the
crystal with a TTL-compatible clock signal generated elsewhere. Details of this
option are given in Appendtx A.
CRYSTAL OR
EXTERNAL CLOCK
FREQUENCY
RESULTING
TIME STATE
PERIOD
COMMENT
5 MHz
400 ns
7803 time state;
fastest allowable
rate for Z80 device
1 MHz
2000 ns
Slowest recommended
rate for ZaO device
FIGURE 6
o
CLOCK OSC t LLATO·R FREQUENCY RANGE
o
8
1»';6". *
o
Bus Timing Specifications
An understanding of the 7803's signal timing characteristics is necessary
for the selection of speed-compatible memory devices, I/O functions,
other peripheral STO BUS cards, and for real-time logic analysis of
7803-based STO BUS card systems.
The 7803's timing characteristics are established by its Z80 microprocessor,
with additional delays added by LSTTL buffers. The basic operations performed
by the 7803 and the signals controlling these operations are shown in
Fi gure 7
SIGNALS
OPERATION
Read from memory
Figures
8 and 9
MEMRQ*, WR1:
AO-A15
Write to memory
Figure 9
10RQ*, RO*
AO-A7
Read from an input port
Figure \0
IORQ* t WR*
AO-A7
Write to an output port
Fi gure \0
I NTAK*
Read an interrupt instruction vector
(in res~nse to INTRQ* only)
Fi gure \\
r MEMRQ*, RO*
AO-A15
c
WAVEFORM
FIGURE 7
BAS:~C
7803 OPERATIONS
The waveforms on the following pages show timing measurements as as-letter
code as follows:
,...------ First letter is always T for Timing measurement.
second letter is the abbreviation of the signal which
starts the measurement. (C-Clock)
Third letter is the condition of the start signal. (H=High)
I
Fourth letter is the abbreviation of -the signal which
,
ends the measurement. (A-Address bus)
TCHAV.
Fifth letter is the condition of the end signal. (V-Valid)
Fj
For example, TCHAV stands for Time from Clock High until Address Valid.
Specific abbreviations are given in the Legend-on each page of the specification.
•
In the case af the Clock, it is necessary to note which time state is of interest;
refer to figures 8 through 13 .
9
MACHINE CYCLE
T1
T4
T3
T2
T1
CLOCK*
o
\10000_ _...{
i
r
i
......TAVML
ADDRESS BUS~ ,----------------\jr----------------..
INSTRUCTJON ADDRESS
REFRESH ADDRESS
AO-A15
: -.r
TM~MH 1---.~!'. .
~____~I____~+
MEMRQ*
I
_--+-_ _ _,1 .......- - - TRLRH
b
RO*
I
AVRl
!
r----
.~ TMlMH2 -.I
~
tr-----------
~~
1
~~-TR-L-DZ----~-'--Ir-TClDX
DATA BUS
00-07
I
---+----~
!+-
TDVCl:
P-------fo
OPCODE IN
r----------------------------------
-1
TCLFL
I
__~----__----------------------__ I~----------TFLFH--------~-~l __---REFRESH*
o
TSLAV
14-----TSLSH
STATUS 1*
LEGEND
~' AO-A15
:0 ' 00-07
~M :, MEMRQ*
'R! RD*
iF i REFRESH*
SI STATUS 1*
it'
I CLOCK*
LI Low state
H High state
'V I Va lid
ZI High
impE!dance
X' Don't care
Low active
*"
NANOSECONDS
SYMBOL
PARAMETER
TYP I MAX
MIN
580
TAVDV I Address va 1i d before data valid (access time)
550
75
TAVMC - Address val id before MEMRQ.* active
1 (Opcode Fetch)
600
TMLMH
MEMRQ* pulse width
400
2(Refresh)
TAVRl
Address valid before RD* active
165
TRLRH
RD* pulse width
370
Data Bus in high impedance read
TRLllZ
100
mode after RD* active
50
TDVCL
Data· Bus setup time before clock
transition ends T2
85
TClDX
Data Bus hold time after T2
0
- 200
TCLFL
REFRESH* active after start of T3
TFLFH
REFRESH* pulse width
770
T9LAV
STATUS 1* active after address val id
0
TSLSH
STATUS J* pulse width
800
Address
va)
id
after
start
of
T1
in
any
memory
or
TCCAtI
160
I/O machine cycle (Fioures
through
1
FIGURE ~
OPCODE FETCH AND MEMORY REFRESH MACHINE CYCLE
I
10
o
0
\
/
\
/
'\
T3
T2
T1
CLOCK*
~I
MACHINE CYCLE
a4I
\
f
ADDRESS BUS ~ -MEMORY ADDRESS
AO-A15
---'
T1
I
r
~
~TAVML'"
MEMRQ*
TMLMH
:41
~
1\
I
~TAVRL~
•
TRLRH
7'r-
~
RD*
1\
TRLDZ....
DATA BUS
TDVCH -...
~
\
00-07
I
~.....-.-TAVWL
TAVDV
WR*
"c
]. .__.1-------- TAVWH
DATA BUS
00-07
~
TWLWH ,
--=:i
4
JI'=TAVDV -i~II't4--'
SYMBOL II
TAVDV II
TAVWH I
TAVML,
TMLMH i
TAVRL'
TRLRH i
TRLOZ
TDVCHj
TCHDXU
TAVWL,
TWLWHI
TAVDVj
TOVWH
TWHDX'
TOVWH
- - - - -......
1 ....
TWHDX
~ -~~~~:~~~_
NANOSECONDS
I
PARAMETER
MIN
Address va 1 id to data valid (read cycle access time) 745
Address va 1 i d to wr i te h i~_h (wr i te cye 1e access time 740
Address val id to MEMRQ* active
I
MEMRQ* pulse width
Address valid to RD* active
RO* pulse width
Data Bus in hiqh impedance read mode after RD* low
Input data setup time before clock high in T3
95
Input data hold time after clock hIgh in T3
0
Address valid to WR* active
WR* pulse width
Output data valid after ,address valid
Output data setup time before WR* risino edge,
Output data hold time after WR* rising edge
11';
FIGURE C\
•
-+1"~TCHDX
I
\,DATA IN ~K
_-,-_ _ _!OATA OUT
---
LEGEND
A AO-Al5
0 00-07
M MEMRQ*
R RO*
W, WR*
C CLOCK*
* Low act.ive
L Low state
H Hioh state
V Val id
7
High
impedance
X Don I t care
"
MEMORY READ (EXCEPT OPCODE) AND MEMORY WRITE
MACHINE CYCLES
11
I
I
TYP
!
75
I
!
~OO
f
!
:
,
MAX
! 1SO I
I 765
I 50 100
!
I
1550
J 400 I
I
300
! 650
I
1
---
--------------------------------
o
Note: fn onboard memory- read operations (Sectfon bl, the D'ata Bus does- not
enter the high impedance read mode. tnstead the 7803 drives data fetched from
the onboard memory sockets onto the- sro Data Bus to fac j-J i tate logic sta~e
analysis at the motherboard. The access time for onboard memory devices may not
exceed the values shown for TAVDV in Figure 8. The state of the Data Bus
prior to TOVeL is unspecified for an on6oard read operation.
o
o
12
-~------
-------------~~---
..
"
MACHINE CYCLE
CLOCK*
I
\
TW
(NC-re.')
T2
Tl
\
/
/
\
.1
\
I
"'-TAVIL~'
--
TAVRL-...,
I
,
DATA BUS
00-07
-..
~
~
,
TDVCH
.,
.....
TWLWH
..
)~
IN
..
TDVWH
~
-
j~
DATA OUT
If\,
TAVWH
~I
PARAMETER
TAVDV(E Address val id to da ta va 1 i d (input cycle)
TAVWH" Add res s va lid to WR* high (output cycle.)
TAVIL
Address valid to 10RQ* active
TILIH
10RQ* pu 1se wid th
TAVRL
Address valid to RD* active
TRLRH
RD* pulse width
TRLDZ
Data Bus in high impedance read mode after RD* low
TDVCH
Input data setup time before clock high in T3
TCHDX
Input data hold time after clock high in T3
TAVWL
Address valid to WR* active
TWLWH
WR* pu I se wid th
Output data valid after address valid
TAVD~
TDVWH
Output data setup time before WR* rising edge
TWHDX
Output data hold time after WR* rising edge
~YMBOL
Note:
/
nJHOX~
-
l
~~TCHDX
1-
~TAVDV®
-?
--J
~DATA
-r\
WR*
I
I
TAVDV<l)
~TAVWL~
•
I
TRLRH
~
-r-
TRLDZ --...
!LEGEND
A AO-A7
0 00-07
I 10RQ*
R RO*
W WR*
C CLOCK*
* Low act i ve
L Low state
H High state
V Val id
Z High
Impedance
X Don I t care
f"F.
~
RD*
DATA BUS
00-07
II
TILIH
\
-r~
r
\
~
\
ADDRESS BUS
v PORT ADDRESS
AO-A7
--I1\
I:QRQ*
T1
T3
NANOSECONDS
MIN
TYP
MAX
1100
1530
300
345
1000
300
355
1000
100
50
95
0
300
335
1000
300
1070
a
TW (WAIT state) insetted automatically by Z80 in I/O cycles.·
FIGURE \0
INPUT PORT READ AND OUTPUT' PORT WRITE MACHINE CYCLES
13
I-
I
TLAST
TLAST- 1
I
o
MACHINE CYCLE
Tl
T2
I
1'\/A
1'\/8
I
T3
L/Lf\.J\-.1LJ
I
CLOCK*
l
INTRQ*
TCHKL-..j
r--
·
-_____~~i
TDVCL~ --,t-.}='
..
INTAK*
i
TKLKH
'1
TCI
]
TKLDZ
DATA BUS - - - - - - - - - - - - - - - - - - - - - - - - \
oX
I [I
00-07
_______________________________________________
~!
rvECTOR ott .
I\oPCODE.
!lA!lOSECOllDS
LEGEND
~"ciJ5CK*-
IQ
K
D
*
L
H
-
INTRQ*
INTAK*
DATA BUS
Low active
Low level
High level
"'1
High
'impedance
X Don't care
I SYMBOL
IrQLCL
TCLQL
rCHKL
IrKLKH
IrKLOZ
trOVCl
trClDX
Notes:
PARAMETER
INTRQ* setup time prior to last time state in
instruction cycle prior to interrupt
.INTRQ* hold time after clock low
I NTAK* asserted in first TW after clock high
INTAK* pulse width
Data Bus in high impedance read mode after
INTAK* low
Data Bus setup time prior to clock low
Data Bus hold time afte·r clock 'low
MIN
TYP
MAX
;
I
130
O.
-
o
145
C;qO
35
75
100
0
(TWA and TWB)
1. Two WAJT states I
are automatically inserted by
the ZaO to allow for priori/ty chai·n propagation time.
2. In interrupt mode I, INTAK* is asserted but the data
bus is ignored.
3. The above time state sequence assumes that the ENI
(enable interrupt) instruction is in effect.
4. INTAK* = [('11*) (IORQ*)] plus buffer delays.
FIGURE 1I
INTERRUPT REQUEST/ACKNOWLEDGE CYCLE
o
14
M..fh'j
,/!
WAIT REQUEST
The WAITRQ* input allows the 7803 to enter the WAIT s'ttte
or interrupt acknow1 edge cyc 1e whi 1e a s low' memory dev ice
a control function such as an analog-to-digital converter
can also be used to single-step the 7803. Figure It shows
for the WAITRQ* input.
I....
~II-
________________
T2
Tl
---
CLOCK*"\ , - ,
/
TQLCH
in any memory, tlO
responds, or unt i 1
finishes! WAfTRQ.*
the requi'red timing
MACHI NE
TWAIT
---
CYCL~E
I
(\J SER IlJS~R~'r ~
T3
\----
\----
WA1TRQ*
~I:--TCHQX
~
o
!LEGEND
~I WAITRQ*
CI CLOCK*
*1 Low act ive
L Low state
IH High state
X Donlt care
SYMBOL
TQLCH
TQHCH
TCHQX
WAITRQ* setup time prior to clock high in T2
120
WAITRQ* hold time after clock high in T2
FIGURE 1'2.
•
NANOSECONDS
MIN
PARAMETER
0
WAIT STATE INSERTION IN OPCODE FETCH, MEMORY
READ, AND MEMORY WRITE MACHINE CYCLES
WAIT state insertion in all memory cycles is simi lar to the Opcode Fet.ch,
Memory· Read, and Memory Write cycles shown in Figure.si~9. While WAITRQ*
is sampled halfway through time state T2 in these cycles, however, it is
sampled at different times in I/O and interrupt acknowledge cycles.
I/O machine cycles sample WAITRQ* at the rising edge of CLOCK*
during TW, the single wait state inserted automatically, by
the z80 in I/O cycles. User-inserted wait states occur
after TW and prior to T3.
Interrupt machine cycles sample WAITRQ* at the rising edge of
CLOCK* during TWB, the second wait state inserted automatically
by the z80 during interrupt acknowledge cycles. User-inserted
wait states occur after TWB and prior to T3 •
15
_ _ LUMMUS; Ii,t
,; ;
4
4A4
WIi'A'iW+N.\UMf"iflli,f#
,.f ..
.4,*
o
BUS REQUEST
The BUSRQ* input and BUSAK* output allow Direct Memory Access (PMA) operations,
giving another system controller card access to the 7803's peripheral cards.
Fi gure \3 shows the tim i ng for these signa 1s.
Las.t cycle. of current
instruct~on
I'
CLOCK,l:
TLas t-l
---=i-
,~..
TX
Bus Avai lable
TX
...
Firu ,c:.yc le o£.-
next in!jtrytjoo
Tl
TX
-TQLCL
BUSRQ*
~
BUSAK*
TCLBZ
BUSSES
(note)
iLEGEND
CLOCK*
, ..
;3_ BUSSES
l BUSRQ*
K BUSAK*
~
Low act j ve
L Low state
itt High state
Z Low
impedance
0 Drivers on
~
SYMBOL
TO,LCL
TCLKL
TJKBZ
TCHKH
TKHSO
NOTE:
r
I_TCHKH
I
--,I--TKHBO
FloClting
PARAMETER
BUSRQ* setup time prior to 1as t time state in
in last instruction, last cycle preceding DMA
BUSAK* active after start of first DMA cycle
Busses float after BUSAK* act j ve
BUSAK* inactive after clock rising edge in
last DMA cycle
Busses driven after BUSAK* ,j;nactive
~
0
NANOSEC'O?-lf}S MIN TYP I MAX
130
35
185
65
160
35
65
Busses refers to the Address Bus AO-A15; the Data Bus 00-07;
and the Control Bus lines MEMRQ*, 10RQ*, RD*, WR*, INTAK*,
REFRESH*, MCSYNC*, STATUS 1*, and SYSRESET*. Other Control
Bus lines are not floated.
FI GURE . \3
BUSRQ*/BUSAK* (DMA) MACHINE CYCLES
o
16
o
,Meehan i ca I
The 7803 meets all STO BUS mechanical specifications.
Series 7000 Technical Manual for outline dimensions.
Refer to the
Environmental
PARAMETER
Free Air Ambient
ODeratinQ Temperature
Absolute Nonoperating
Free Air Ambient
Temperature
Relative Humidity,
Noncondensing
Absolute\Nonoperating
Relative Humidity,
Noncondcnsing
FIGURE 14:
17
;u;;
A# #
Ii;; : 4
I
$
TYP
MAX
0
25
55
°Celsius
-40
75
°Celsius
5
95
%
0
100
#l em_;CIM_WID
UNITS
%
'l
ENVIRONMENTAL SPECIFICATIONS
•
$
MIN
SECTION 1.4
o
zaO ARCHITECTURE AND INSTRUCTION SET
~
ACCIMAAtOIt
AU
.... 1
,......
11
s
Z
04,
...... N C
'J
~I
"
"
I: . . . . . . . . . . . ~. . . . . . . . . . . . ~ 11 I~ . . . . . ,. . .,. ,. . . . .
I"
",032'0 ,
•
I
,
1 Z
,a
I"
i 51Z
AU
U_2
,......
04
1 • 1 ,
1 Z • 0 7 ,
1 ,
".--~--------t---------
1 Z ,
0
+ot................--+-I
".._=;:.:IftII==_;;f:;:;.....)_ _ _...l __)...._____
l - - - -..).....- -...: __)
I/O';'"
~
I/O
j
-
IIOGAf.
I
I"
~ ~ I
I'
I
:
~
I
-~
- -'-- -------i-----=.------.~ I '- '~.":.
"
I
'------------------~i
'.501210
c
I/OGAfA
-f
/
:...... N
110--.:
!
~;,
J
',- I----~)•
I
"I
-'"
I
I'"
'I :
Y, I
I
I.".
I
I ...
... 1 :
I
I"'
'l'
1111;,.',3 '2'11,10,'.'
I
'1501,2.'0
I-~
"-
~s'
1-;
"':.
... I-~'
~
.....".
POllY
.....a..,
~I
:
I
I
(IICIIII
,,
o
I
I, , - ___ J ;
(
FIGURE
\s
z80 PROGRAMMING MODEL
o
I"
~!
I
If:
18
o
Z80 Architecture
The Z80 architecture (Figure \S ) consists of a 16-bit Instruction Register,
a l6-bit Program Address Counter, a 16-bit Stack Pointer, two 16-bit Index
Registers, an a-bit Interrupt Page Register, and two bank-selectable sets of
General Purpose Registers plus two bank-selectable Arithmetic/Logical Units (ALUs).
A 6-bit Flag Register (in each ALU bank)' holds processor condition code
information. An a-bit autocounting Refresh Register supports dynamic RAMs.
instruction Register: The 16-bit Instruction. Register provides storage and
decoding for instruction opcodes as they are received from program memory.
The Z80 executes all of the 8080 instructions as a subset of instructions with
a-bit (one byte) opcodes, and adds a large number of additional instructions
of which most have l6-bit (two byte) opcodes. The processor receives the first
opcode byte from memory ~nd decodes it to determine if a second opcode byte
follows. The instructions with 2-byte opcodes are identified by a first byte
equal to hexadecimal CS, DO, ED, or !FD.
The complete instruction word may consist of address or data information in
addition to a 1-byte or 2-byte opcode. The full instruction may be up to four
bytes (32 bits) long. Additional words of multi-byte instructions bypass the
instruction register. These words may be be immediate data for registers,
a memory or I/O port address for direct addressing, or an offset address for
indexed relative addressing.
Program Address Counter (PC): The 16-bit Program Address Counter keeps track of
the location of the next instruction to be executed from the program memory.
The PC increments automatically for each instruction word unless the instruction
is a jump or subroutine return which modifies the count by loading a new address.
Stack Pointer (SP): A J6-bit auto-counting Stack Pointer provides the address
of the subroutine return address stack location in RAM memory. The SP is used
for contro 11 i ng sub rout i nes and interrupts, and can a 1so be used to "push ll and
IIpU 1111 data in memory at high speed.
Subroutine return addresses are automatically stored on the stack when a
jump-to-subroutine instruction is executed, and are retrieved when a returnfrom-subroutine instruction is executed. z80 mode 1 and 2 interrupts are
treated as subroutine jumps, taking advantage of th~ SP's
return address storage and retrieval ability.
All of the General Purpose Register Pairs and the ALU registers can be stored
and retrieved from memory using the SP as an indirect address register. The
resulting l6-bit data movement and automatic increment/decrement of the SP
offer fast memory data manipulation.
The current memory address in the SP can be brought into the HL Register Pair
for arithmetic manipulation, then restored to the SP by the program.
•
General Purpose Registers: Two identical banks of General Purp9se Registers
are provided in the Z80. Each consists of six 8-bit registers (B,C,D,E,H,L)
which can also be treated as three 16-bit Register Pairs (SC, DE, HL). The
banks can be switched by a single instruction, providing fast interrupt response
by saving the time required to store the register content in memory. Or they
can be used as general fast access data storage in non-interrupt appl ications.
19
UP" 1\1# 4131 ( , 'Mi; ,1$#
44
I
#
E
The instr.uction set allows individual a-bit registers to be loaded from any
other register, loaded and stored in memory indirectly, or loaded immediately
from the second byte of the instruction. All registers can be incremented
and decremented, added to or subtracted from the Accumulator, perform logic
with the Accumulator, shifted or rotated arithmetically or logically. Each
bit in each register can be addressed separately for testing, setting, and
clearing. Register C can be used for indirect I/O port addressing.
o
The three 16-bit register pai'rs can be loaded iinmediatelyfrom the second and
third bytes of the instruction, incremented and decremented, stored directly in
memory, added or subtracted to the HL pair and the Index Registers, and used
as indirect address registers for ope'rations with other a-bit registers, memory,
and the Accumulator. In arithmetic operations, carries and borrows are propagated
from the low-order a-bit register into the high-order register automatically.
Ari'thmetic/Logical Unit (ALU): The ALU consists of an a-bit Accumulator Register
(Register A) and a 6-bit condition code or F~ag Register (Register F), plus
arithmetic, logical, shift, and control circuitry needed to execute the program
instructions. The A and F register are treated as the AF Register Pair for
push and pull operations involving the Stack Pointer Register.
The ALU is duplicated in two banks, with bank switching accomplished by a single
instruction similar to the ~eneral Purpose Registers. The enabled ALU provides
add and subtract with or without carry; AND, OR,
~clusive OR, compare,
shift, rotate, and byte oomplement operations. ALU operations are performed
on the Accumulator from other registers or memory, with direct" indirect,
indexed, or inmediate addressiAg. The Accumulator is the primary register for
I/O commun'j ca t j on. The Ac:cumu 1a tor can be dec i ma 11 y ad j us ted and a I lows 4- bit
nibble swap operations with memory for Binary Coded Decimal (BCD) arithmetic.
0
Register F contains the following flags:
C - Carry/Borrow from Accumulator bit 7 (arithmetic or rotate)
D - Carry for BCD arithmetic from Accumulator bit 3
N - Specifies whether last operation was subtract,
allowing different algorithm for BCD operations.
Z - Zero resulted from the last Accumulator operation.
S - Sign for signed binary arithmetic (same as Accumulator bit 7)
PV - Parity/Overflow (signed binary arithmetic); dual
function flag, function'depending on last instruction
PV shows. whether tNT~O* i. s enab.l ed wh.en tes,ted after the
LOAf instruction (Figure 2I1,
.
'
The Ci Z, S, and PV flags can be tested by the conditional jump and subroutine
return instructions. Special instructions allow the C flag to be set, cleared,
and complemented. When pushed/pulled on the Stack via the Stack Pointer as
part of the AF register pair, the F register occupies a bits with the state of
bits 3 and 5 unspecified. The states of the six flags can be preset by pulling
program-prepared bits into Register F; the states of the untestable flags (O,N)
can be determined by pushing Register F onto the Stack, then pulling the Stack
data into a General Purpose register.
Index Registers (IX and IY): The 16-bit Index Registers are used as indirect
memory add-jess registers. The address supplied by IX and IV is modified by a
relative offset which is one byte of the multibyte indexed instructions. The
Index Registers address memory to allow memory bytes to take part in the arithmetic
20
'~-'----,---"--------
0
WPM.,M.W
o
and logical operations described above for the single 8-bit General Purpose Registers.
When ·modifying the address content of the Index Registers, IX and IY are/I~gQted
as Register P·airs. The arithmetic, logical, and load/store operations that can
be performed on the General Purpose Register Pairs can generally be performed on
the Index Registers, although fewer instructions apply to IX and IY than to the
BC, DE, and HL pa~rs.
Input and Output Ports (I/O): I/O is mapped independently of memory with
separate control signals and instructions. The OPA instruction writes data
from the Accumulator to output ports, and the IPA instruction reads data from
input ports to the Accumulator. A specific port is specified by the second
byte of the instruction, allowing up to 256 each 8-bit input. and output ports.
In the 7803, all I/O ports are provided on separate cards.
Communication with the ports can be direct from memory using HL as an .. address pointer
when the z80 l s Compound Instructions (below) are used.
Compound Instructions: The z80 l s instruction set contains several compound
instructions which perform mUltiple functions. w-ith or without automatic looping.
These are impl ied sequence instructions which execute a fixed sequence of other
instructions in the instruction set. They perform block lmultiple byte) moves
within memory, search memory, and input or output to,-or from memory fo the t/O ports.
Register C as a port address pointer and HL as a memory address pointer.
One compound instruction performs automatic count and jump functions for
loop control alone.
.
.
.
1y as muc h 1~lme
~ecutionh·
.
Th e compoun d .Instructions
require
approximate
as t e InstructIon
sequences they replace
, but offer program memory savings by
eliminating instruction storage for common program functions.
Interrupt:
The z80 offers three interrupt modes:
o-
identical to the 8080 interrupt system
(Rest~rt at 0038 always)
2 - supplied vector interrupt, with a single byte
supplied by the interrupting device.
1 - impl ied vector interrupt
In interrupt mode 2, the content of the Interrupt (I) Register IS the
vector page address, and the byte supplied by the interrupting device .s
the vector Tine address. Together they form a l6-bit memory address which is
the indirect address of the interrupt service routine for that device.
MoRE.
I"Tr:.~ltJl'i
,,,l!oll..fIA./tTIO,..
11
Of "1"'H'Cj
cf-IVEAJ A"r TI-4£. ,,"w1)
S;Ee~'OAJ.
Refresh Register (R): The Z80 contains an 8-bit Refresh Register which is used
to address dynamic RAM devices external to the 7803 card.
In conjunction with
the REFRESH* control signal, the processor can automatically refresh dynamic
RAMs
during the opcode fetch portion of the instruction
cycle. This function is applicable primarily to certain dynamic RAM devices
available from the manufacturers of the z80 chip •
•
21
==::X",. 1M I' M,M?'
I
pq ,
4 $ t 44 #
@
,"·.4 ;M. "" . **""'/4ii"'''$IiR4M'II\&I4'!
280 Program Compatibility with 8080, 8085
o
Both the Z80 and the 8085 include all of the 8080 instructions as a subset,
and these instructions are all machine-language compatible. Programs written
exclus1vely in 8080 opcodes will execute on the z80
with
the following considerations:
1.
Execution times of 80BO-identical instructions
vary due to the number of time states required
for execution (some more, some less) in the Z80
and 8085, even if the processors are all operated
at the same clock rate. Consequently, programmed
timing (such as count-and-test time delays) wil J
gene~ally require modification.
2.
Flag Register bit 2 is the PV (Parity/oVerflow)
flag in the zao, and parity only in the 8080/8085.
The added overflow function is for signed binary
arithmetic. Since the parity and overflow functions
are unrelated, occuring at different times in most
programs, in(:ompatibil ity does not usually result.
However the flag's activity is different overall
and the program sh0uld be examined for sensitivity
to the PV flag.
Except for the differences noted, the zaO resets to 8080 compatibility and
its additional features must be deliberately invoked by the program.
o
o
22
o
,. The operator is I unique two letter abbreviation
that suggests the action.
STD INSTRUCTION MNEMONICS
The STO Instruction Mnemonics are a standard set
of processor instruction abbreviations sUitable for
use as an assembly language for writing programs.
2. The locator follows the operator and designates
These mnemonics are standard in that they do not
change but keep 'the same meaning regardless of
the processor they are applied to. They are also
standard in that they are derived from a set of easily
understood rules.
3. The qualifier states the addressing mode or
provides further qualifying information for
compound instructions.
The instruction mnemonic is an abbreviated action
statement containing an operator. a locator and a
qualifier plus a supplemental and separate modifier.
the operand or data to be operated on. Instructions without operands ignore the locator.
4. The modifier carries detailed support information; labels. conditions, addressing and data.
The operator. locator and qualifier letters are strung
together to form the instruction mnemonic. The
modifier. when needed. stands alone either in its
own separate column or separated by spaces or
addttional lines in written text.
OPERATOR
LOCATOR
QUALIFIER
MODIFIER
INSTRUCTION DESCRIPTION
RTS
RT
CLA
CL
A
LOAD
LD
A
LD
A
LOA
B
(aC)
LD
(LABEL)
JS
LOAN
JS
Return from Subroutine
S
A
Clear A
0
Load A Oirect
a
N
(BC)
(LABEL)
Load A with B
Load A indirect using BC
as an Address Pointer
Jump to Subroutine
Located at (LABEL)
Figure III Examples of InstNction Mnemonic StNctUht
•
23
LUiii"...,
"AI U p,
¥¥ 4A
---...-- ....
- - - - - .--.---...................
"'-""-~--.-
-----..
~~.-
---~------
o
The following table lists the STO mnemonic operations, locators, modifiers,
qualifiers, and other notation used in the instruction tables for the Z80
in th i s sec t" ion.
VANDMO ....MOMCS OU.NlTlONS
O""ATIONS
QUAUPlIRS
LOCATORS. ..OOI"I"S
..,
AD (AC) ADO (WITH CARR."
AOolUST OECIMAL
AND
lANK SELICT
C1.E.AR
COMPl.£MENT
COMPARE
OECREMENT
as
OISASLI
EN
ENAau
H'-T
HALT
INCRE_NT
IC
IP
INPUT 'ROM PORT
JI
JU"P TO INnRRUPT
JP
JUMP
JS
JU.... TO SU."OUT1,..
La
LOAD
"OVE ....ORY
NOP
NOO"RATION
OP
OUTPUT TO PORT
OR
INCI.USlve
PUSH. PULL VIA STACX
RLoU
ROTATILUT. RIGHT
RESET
ItT
RETURN VIA STACK
SIIE
SllET
ST
STORI
SU (SC) SUaTRACT (WITH CAR"'"
Ta
TUT
xc
DCMAMaIE
AN
IS
C1.
C..
CP
OC
.."
.......
".
A..ACC
a.c.o)
E.H.1.
,
c
d
%
•
"fjIY
1.0
:~l
·OE
HL
IX}
I"
It...
I
II
III
.
I
S
PC
SIll
"
ACCUMULATO" REGISTER
GENIRAL ..alT REGISTERS
FlAG REGISnR
C.-y " "
0 ..... " "
Z... " ..
Si9ft FIa9
s.t .. Sulllr_
PIrity/O"",ow Fa-.
5.... eM iftcIaMd ' ...
ACCUMULATOR. A..AGS PAIRED
GINIRAL RIGISTE" PA"'.
(1 ....T DATA. POINTER••
C
J
0
I
N
X
R
T
,.
WfI
IF
W.
A
..
I.
INDO RIGlan...
ANY REGISTE" PAIR
AN" SINGU ReGlSnR
llllIIOR". ADO...5S10 INDIRICT\. 'f
CONTENTS Off A lllIIOR" 1.0c:AT10N
INT'I,",UPT
NONIIASlCA8LlINT'I!"""PT
SU8ROUTINI
,...OGR.... COUNTI"
STACK POINTeR
.............GIS1'IJI
MlSCa&.ANIOUS
....
UN
Nlitl
I.sa
Ca
...,..
rr&lfIIJ
..."
Co. .
FIGURE 17:
sro
WITH CAR""
ANO JUMP
OtRECT ADO"ESS. OR OECIMA1.
IMMIDIA T! OATA
INDIRECT ADDRESS
INDEXED ADDRESS
RELATIVE ADDRESS
TOP OF STACX
WO"O FORWARC
ILOCX 'ORWARD
WORD IACXWARO
ILOCX IACXWARC
ARITHMeTIC
1.0GlCAL
MODI OR INL TIPU
UNCONOtT10NAL
NONMAS«A.... INT'IRAUPT
MOST SlGJlllFICANT liT
L£AST SJGHI"CANT .,T
JU_ CONDITION
110 ~T ADORESS
U'"
...MO""
ADDRESS
11-41fT ADORISS
"ILAT1VE OfIISIET
....TOATA
11081T OATA
o
Mnemonics
o
24
- - - - - - - -----~----~~---- - - - - -
o
The z80 Instruction Set
Figures 18, 19 and 20 show the full z80 instruction set with STO mnemonics
and hexadecimal operation codes. The tables are grouped by 8-bit register
operations, 16-bit register pair operations, ALU (Accumulator and Carry),
program address control, I/O, machine control, and compound instructions.
Figure 21 shows the bit organization of the 8-bit and 16-bit registers,
the effect of the shift and rotate instructions, the allocation of memory
by certain instructions, and the action of the flags (instructions not listed
in the Flag Summary have no effect on the flags). Figure 22 shows relative
addressing constants .
....T LOAD. STOAE
....'"'
~It
A
a
a
LOA
U.
LDC
D
I
7t
71
40
41
.
1'1
"
7C
~
44
.
."
47
•a
•
a
a
a
SF
.7
.,
II
(ttL)
77
70
LDD
LOE
&.OM
LOL
STaN
STaN
naN
LOMI
LDMI
Lo",
•
C
(IX)
(IT)
50
51
10
57
0077" 007Qfr
'077" '07Qfr
7A
42
••
"
5.
"
52
SA
12
IA
72
It
•
C
. ..
53
51
13
Sol
Ie
Ie:
7.
n
7'
007'" OO~ oonrr 007""
F07'" ,onrr ,onrr '07."
L
7D
41
40
$5
,_.
....
IICIX)
III(IYl
?!
DO?!"
FO?!"
~
51
51
004lfr .
D04IIf
OOMn'
0051"
ODelrr
ODIE"
.•
)
50
IS
ID
IE
75
0075fr DO""
F075fr
•
F04IIf
FOMn'
FOil"
jrOIIrr
'OtE"
.. alT ..".THMETIC
M
lC
04
OC
1C
30
'1
05
00
11
10
10
.,
,.
M
",
II
II
IC
t?
to
"II
...a •
2C
2D
15
10
•
Ie
to
•
I'
MIT LOGIC
A....
IR"
A7
AI
AI
OIIIA
II
11
~
I'
.
1E.
21.
••
003efr . .
'03efr.
(11')
"0"
..CA
SUA
SCA
..
••
,
10
I.
13
t2
M
..,
t2
...
u
AS
AI
I'
I •.
IJ
IA
II
A2
13
2.
.
.
25
...
..
AC
_ IC
II
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
"EGISTER
"EGIITER
IlEGIITER
REGISTER
MGISTER
MOIlTE"
MOISTE"
A
a
C
0
E
104
L
lI. .
(IX)
ICa
DCa
••
••
STORE "EGISTIR INDIRECT
'0""
(HL)
ONllAn(JN
DIATE
J4
00J4"
002'"
DO.."
DOli"
DO.."
1I
•
•
•
'03o.tn
'OHfY
'0.."
FOil"
'DtIfr
c ••
ca.
~
•
DO_"
FD."
oe ..
FD..."
FDAI"
'0..,.,
'Oil"
EI.
El ....
AI
AI
OOA,"
"0
II
10
..E
at
OO"E"
ooa.,.,
ooal"
C805
caoo
CI"
CI,D
cazs
cam
cam
ca.
ea.
CI,.
CI,I!
CI.
CI.
ca.
ooea".
Doca".
ooca",.
OOC.",E
OOCI".
00CI"2I
DOC.".
It
Fl.
'1 del
LOAD MEMOR' l....olATi
INCREMENT MGIITIR
OICREMINT REGISTE ..
"00 TO ACC
ADO ./CA"'" TO ACC
_'''QM''CC
sue .1II0000RO. ~II Ace
.. NO WITH .. ee
neLUllYE OR WITH ..ce
OR WITH ACC
CO .._ .... E MTH ACC
"OTATE. lMen
".....
..R.....
ItLIC
....
"Rae:
"'8A
SAa
.'OAa
•
•
•
•
•
•
•
•
CIIG7
C. .
can
C11'
caZ7
CI2F
CI.
CIllO
ca.
ca10
CII,.
ca20
caa
ca.
ClIO'
CIIOt
CIIOZ
caM
. cln
CI"
C111 ..
CI,.
cau
CI21
ca2A
call
eat
caM
II IN ...nt. IIODIAIIt WILL. a. Etn4ER
FIGURE
18
(ttLa;
caa
ca04
CI.
can
ca,.
can
can
ca.
CIOC
ca14
CI'C
cal'
C112C
cae
IIX.oft': OR
('Y,,,,
Z80 INSTRUCTION SET
25
,Dca".
'OCI".
'Dca", •
fIOCa""
'Dca".
fIOCI"2I
,oe.".
"OTATI "'GISnR .....TH..ITIC
II liT; SETS 'LAGS)
"OT.. n "l!a'STE" AND CARRY
A"'THMETIC I' .IT: SETS 'LAOS)
SMI" "R'THMETIC
SHIFT "IGHT LOGICAL.
....
.".
~
•
"
C
.......
TSI
.&
c:..7
c::8.e
~,
CMI
c:aG
CSM
TS1
6
c.-
ca..
CMe
ca.a
ca.-
CM1
ca.
ca.
caa
call
cau
cae
caM
CIlIA
CMt
CIIM
C1172
ca1A
CII_
c:ac
TU
TU
TSe
TSI
.,
TSI
TS1
ItS.
ItSI
~
Its.
u.
"SI
"S1
sao
sa,
sa
..
sa
sa.
sal
sa7
•
~ caar
•
•
•
•
•
can
canr
.,
caa.
C8C'1
CSCO
cac:P
CIO'
cae.
CIOO
CIO'
caD.
cao.
ca..
caOP
caE7
CIIEP
c:.E1
CHI
CRt
can cwo
CW,
ca.,
c.r.
ca. .
ca.
caM
DOC8frM
~
caM
~
ca.
DOC8mI
DOC.....
FOe.".
FOa..-
c:a..
cal.
ca1C
ca7S
ca70
caM
CIIIC
a ..
calC
CII'"
CBAC
C8I5
CMD
C8Ie
ca.
calD
a.
caA5
ClAD
'cue
CM.1
CIA.
caa
ca. .
cac~
C8C8
cao~
e.-
ca.
caM
can
ca.c
cae..
C8CC
CacM
ea.o
escs
acD
caos
caE.
alc
e ...
AO~
ACP
leP
AOP
AOP
ICP'
DCP
LOAN
STAN
1.0Pt
~OPO
STPO
p~It
"'It
I"
ISP
lCP
~OP
lCPT
a.c:
U
......
01
NL.a
.......
10"
'La
I".••
0001
FOOl
cau
CaP,
C. . .
ewe
••
••
••
02
"
21
lOlA
ED12
1.
I.
OA
..••••
..••
02
a1c1L.dH
"
!D. ......,..~
1A
12
CS
C1
01
....
0'
.,
OC.HL
ca. .
ca.E
cae.
cacz
ClOt
caGE
caE.
fIOCa~
oocafY"
'OCarY,.
OOC8fY~
FOCafY~
DOC.".
DOC.....
0DC8rrta
DOC. . . .
ODCBfYAI
oocafYAI!
DOC.,...
OOCarnlE
ODCaftC.
OOcam:e
DOCafY06
FOC.'....
AJelfftl
FOCafYlO
OOC~
ooca"u
DOC.trEE
DOC.",'
CHI
C. .,
caP!
OD~
..
flOC......
JrOC8rfM
FOClfYAE
FOcanel
FOCa"eE
FOeaftC.
FOCarrC!
FOCarrOl
FOCartOE
FOCatrEt
FOCatrEl
R2C.m:,
R2Cam:£
n
~
28
III
"t
0021
F021
ron
DOn
0028
FDa
0021C1LdH
OOZAmt."'''
0022"",,,,"
DOIS
0011
F021CILcIH
FOZAmt."'"
'022...",..
FOE5
FOE'
Don
OOEl
,on
11
,.
21 .......
l14LdH
ZA~
ED.,.",,-","
EDnmLmP
22mt.mP
U
11
Ft
n
dHrtfM
Z"..
............. t:Mt·0.
Nt .... Z". .
RESET liT
0_1t
eSe. . . . . . . . . . .,..
.
SET liT
1_1t
s.ct... ~.,..
I"
It
ED1A
Eon
DOlt
FOlt
nST I.T
D--Z
............. t:Mt:1.
OPERATION
IX
~
....
EDIllmI.Jft4t
EOOmLmP
05
01
ED~
"
N.L
I~
oa
'5
D..I
EDIA
ID52
001.
F01.
ED"2
caM
au
CUD
c . .,
C.PO
.,.....
INSTIt
CII,.
c.n:
ca.
aoc caoa
c_
CUJ
rt
IX
C8ID
CMD
au
c.rA
AJeIlmE
CIIM
a..
call
ca_
C8C2
CKA
cacn
C8DA
CH2
CHA
CaP2
CSC1
C8Q
~
~
CMC
c:aa
cae,
can cau
ca••
~
a.
c:aa
caM
caM
CIIAJ
CIIAA
CIIa
QMa
QMO
o
OPERATIO"
•
ea.-
CIlIa
can
ca18
ca.
Cft1
CII.
ClA1
CIIAt
CIllO
c:8M
C8AI
aM
caw
.
can
CU1
C8IO
ClA1
CUF
CII.'
I
an
caa.
ca.
caw
•
•
..•
•
•
•
•
•
•
CMI
can
CIII'
C. .
at7
•
cae,
CMI
caM
C1170
CM7
c.-
•
ca.,
L
!
D
'OFt
ADD ...... TO THE H L PAUt
ADO ......./ColR .." TO H L
SUBTRACT P.....,CAR.. ,. FROM H L
ADO .. AI .. TO INDEX AIGISn .. II
ADD "A'A TO INOll "EGIST!" I.,
INCREMENT "EGIST'R "AUt
DECREMENT "EGISTIJII "A'R
LOAD ACC INO'RICT
STORE Ace INDIRECT
LOAO PA,R IMMEOIATt
LOAO .. A.R O'AECT 'ROM MEMOAY
STORE "A'R OlfillCT IN MEMOAY
~'H "A'A. STACK ·2
"ULL "A'R, STACX -2
IAN" SELICT "IG'ITlR' A.F
IAN" SELICT IIIEG "A'RS IC.DE.HI.
EXCHANGE , •• R 01 w'TH HL
LOAO STACK ~'''TI'' W'TH ....,I'
EXCHANGE PAIR ..ITH TOP 0' STACK
o
J.,... INDtMCT
INSTR
",...
..
MOO
HI..
IX
IY
U
DO.'
trW,
...
O. .UnON
I...".
1IlOO
JI
•
Ju.. TO AOOMSS IN IIIbIC)RY PAGE oa
311
18
211
a
»
• C,•
JU-INOIMCT
(
.~
C7
1.
DJ
~,.
' ...TR
JP
JPtIt
J..
"TS
UN
Ca
Ca
C.
C.
1_
C~mP
Z'D
>
co
C~
O~
i*0
ODO
,.,.
...
so
E2IRf..IMJ
,~~
20It
."
CO.......- C......,.... 0 ........ E........
el
CO
DO
10
FI GURE lq
,........
"'
OIl
17
Ell
"
FP
O"RAnON
:0
Z1
~
.....
2trr
C~
ca
<
OW
C,
,."
11
OAML..... EAMUMt 'A..........
lIrr
DC.......... IC.......... 'C~
01
II
zaO LNSTRUCTION SET
26
....ITH..EnC
"
,"OQICA&.
JU_ ON ·CONOITIO.. TO /ftL",,.
JUMP "ILA TIYI TO PC • "
SU,ROUTI", 0 .. CONOITION AT
"(TU.... '''OM aU'''OUTINI
rM.~
o
-.
()
MACHINE
ACCUMULA TOR. CARRY CONTROL
INSTA
IIOD
CODE
C~OL
INSTA
OPERATION
IlOO
ENI
INSTRUCTIONS
OPERATION
CODE
F.
ENA8LEINTERRUPT
F3
DISABLE INTERRUPT
ED4I
INTERRUPT MODE 0
CUC
AF
CLEAR Ace. CARRY
CLC
B7
CLEAR CARRY FLAG
DSI
SEC
37
SE.T CARRY FLAG
CMC
3F
COMPLEMENT CARRY
SEIM
SEIM
0
1
CMAL
CM. .
2F
SEIM
ED ...
COMPLEMENT Ace LOGICAL
COMPLEMENT Ace ARITHMETIC
LOA
AJAD
27
RLA
07
ADJUST Ace DECIMALLY
ROTATE Ace
LOI
RTI
2
I
A
RRA
OF
(I BIT)
RTN
ED45
RETURN FROM NMIRO
RLAC
RRAC
17
ROTATE Ace AND CARRY
HOP
HLT
00
NO OPERATION
HALT
RLAM
RRAM
1F
(HL)
(HL)
LOA
R
LOR
A
LOAD
STAD
INS'"
I...
.......
ROTATE ACC MULTIPLE
WITH MEMORY
EDSF
ED.
LOAD ACC FROM REFSH
32mLmP
MOD
...
~
...
ca.-
INSTIl
MOD
e
ED7'
ED...
ED..
10M
1051
10"
11M1
aMI
IDS'
roll
Olpp
0-.
A
LOR
A
INTERRUPT MODE 2
LOAD Ace FROM INTERRUPT REG
EDU
LOAD INTERRUPT REG FROM Ace
EDC
RETURN FROM INTRO
11
EDSF
ED4F
LOAD Ace FROM REFRESH REG
LOAD REFRESH REG FROM Ace
LOAD ACC DIRECT
STORE ACC DIRECT
•
A
LOA
INTE1'RUPT MODE 1
EDSE
ED57
STORE ACC IN REFSH
3AmL1ftP
(C).a
o.-A
(9 BIT)
ED.
EDI7
EDY
I
D
OUAU""
WORD
WORD
'LOCK
FO"WAM) FO....RD IACKWARO
u _
,
1070
O"MTIOM
"
&.
EDIG
1011
IDI'
lDei
I...-uT O.".CT '''OM ~"T h TO ACC.
INPUT INDIRICT '''0Il ~RT DI"NID . , Ie) TO ".Glna" ""'ED.
ou~T DIRECT ""011 ~CC TQ ~T ~
~ IIiIOIMCT "'OIl MGlS,.." ...-0 TO ~T DVtMD • ., Ie).
'LOCK
IACKWAIIO
ONMnOM
a
.laU
.laWI
a: . .
.."..
10M
EDIt
IOAI
!DII
IIOVE _IIOR., WORO 'ROIl CHL) TO (DE):
INCRE..,.,. FORWARD OR DECRIIiENT IACKWARO DE AHO HL;
DEallMINT (COUNT) Ie; ., I&.OCX. "I"AT UNTIL elC) : 0-
c.-a
IDA1
1011
IDAI
roee
CO. . . . ACe WI1M (MI.~ RESULT TO ,:
INCM.....,. 'OIN.IIID 0" DEeM_NT IACX.AIIID HL:
DECM...., (COUNT) Ie: IF I&.OCX......AT """'- ACC : (ttL} OR Ie : 0-
m.u
roa
IDAA
mIlA
.....". PWOII ..atrr oefl1NG) I" fe). STOM IN IHI.):
I~MIJff FCMWAIIID OR DECMIII!NT UCX." HL;
DECM...., eowtr
ILOCK . .NAT UIIT'IL I : ..
10M
0U'fNT DATA IIWOII (MI.) TO .-oIff DV1N!D IT let
INC"11ImfT 'ORWAM) OR DICMllENT IACX....O HL;
OECMIIDIT I; " ILOCK. MNAT UNnL I : ..
-~
...
.
10AJ
mea
IDAa
-= "
I OECM..-n' Ei
FIGURE 2..0
I' 5 , .. ~ TO (IIC~.
z80 INSTRUCTION SET
•
27
••"".,"_'''',: ,.:1
*44 i
in
$
:WWM
4
WQ\i4i1U; 4 #. ¢ #
p,
%
.
; ,.:;;
-
o
StWT. "OTAn SUMMARY
DATA
INST'MIC'TION
.II. .Is.
ANY
INTeRRUPT
now
.....~. . . 1)
..,.....,.
(~
ANY RaT
RUC.I'RaC
RUC.I'RAC
t lIlT JIOTATE
e.
dL""EGISTlRS F. C.
L
. .-REGISTERS A. I. O. H
c:L.......ftIi..IIIP
PUtIPSP
ANY flEGISTIA
fIILIIIp.,
PAl..
IN 1IIDIOII1'
SLM
NOTE: This table shows how the processor
allocates memory automatically when certain
instructions are executed. For example,
the PLP instruction pulls a line address or
low-order register (C,E,F,L); increments
the SP, then pulls a page address or highorder register (A,8,O,H); and increments
the SP again, leaving the SP two counts
higher than its initial value.
S
%
S
S
S
S
%
%
%
%
%1
%
%
%
Z
Z
so
•
S
S
S
S
•
0
0
0
01
DO
00
01
0
0
DO
D
•
"."
N
C
V
V
P
P
P1
NO
C
•
V
V
IFF
P
01
•
sac
00
M.A. MA. RUe. "RAC
IILaA. "Ru. RuC. RIbC
SUA. SAu. _JIlL
I".I"N
.LO..
ACJt
SCP
INI'. INa. OPW. OPWB
IPeF. IPe8. OPeF. 0 . . .
MYWP. MVW8
IIV8F.MW8
CPWF.CPWe.C~F.CP88
DO
S
S
S
Z
Z
%
S
S
Z
Z
%
%1
••
•
•• ••
%
00
00
DO
••
••
•
00
00
•
P
P
P
N1
NO
NO
NO
SIbI~
~.
. LOGIC
IHIIIT RIGHT
....
•
bOil·
L
R.
...
R
•
L
R•
@J
\.
...
bO~
R.
bOt---@]
It •
bOt---@]
·S7
Ib7
• •L
"TH~"
"I": "I
Ib7
I
L
•
R
t
~
,.
R
Alla7
LIJrT/RIGHT
I
811H~
L
It
C
CII
CO
CO
o
NO
NO
N1
NO
REQISTER ORGANtU TION
C
N1
NO
NO
NO
NO
A.8.C.D.E.H.L.I.A. Ports
C
C1
C
C
NO
NO
NO
V NO
V N1
N1
N1
Cn. NO
PVO NO
•
•
C
C
C
en. N'
FIGURE 2..1
S. Z. o. P. V. C: FUG CHANGIS ACCOROIHG TO OPERA nON RESULT
II. 1:
FLAG ASSUIIES SNC.FtC LOGIC STATE SHOWN
IIIP:
"." FLAG: 1 IF ENtiN IFnCT. ELSe ' 0
C'TW:
"." FLAG = 1 IF COUNTIR (lie) : 0. lUll ' 0
e:
I
M""nt'U
NOTES:
ILANIC:
SlId
AIII~
SttIPT RIGHT
RUM
ROTATE ACC
FLAG SUIiMARY
Ib7
~b7
. .IfITLEFT
.lOA.ACA
SUA. seA. CPA. CMAA
ANA
ORA. XAA. C1.C
CUC
Ts.
lea
DCa
LOA I. LOA"
AJA
CIIAL
CIIC
Ib7
I
AIU1'HIIETIC
INSTRUCTION
...•
R
I
SP+ZAFTER
(
t.OAOISTO....
RLaARRd
RLA.RRA
• liT ROTATE
SP-Z AFTER
_~SP-Z)
SHIFT DIREenON
INSTRUCTION
COMMENT
SUPPLIMENTARY INSTRUCTION
INFORMATION
FLAG UNOIFtNID
NO CHANQa
·0
28
I,
•
t
I
FORWARD RILATlYE O"IET
r
~
~
r--
.--
00
16
10
32
20
48
30
64
40
80
50
98
80
112
70
I
01
17
11
33
21
49
31
65
41
81
51
97
81
113
11
2
02
18
12
304
22
50
32
86
42
82
52
98
82
114
72
3
03
19
13
35
23
51
33
67
43
83
53
99
63
115
13
4
eM
20
14
36
24
52
34
68
44
B<l
54
100
64
118
14
5
05
21
15
37
25
53
35
89
45
85
55
101
85
117
75
8
01
22
18
38
2S
54
36
70
46
86
58 102
86
118
18
7
07
23
17
38
27
55
37
71
47
87
51
103.
87
119
n
,a
01
24
,8
40
21
58
38
72
q
88
58 '04
88
120
78
01
25
19
4,
2t
57
38
13
4t
S9
59
lOS
sa
121
79
7A
10
CIA
2e
1A
42
2A
58
~
14
oM
eo
SA
lOS
SA
122
I,
os 27
1B
43
2B
59
38
75
48
91
58 ,07
88
123
7B
12
OC
28
IC
44
2C .80
3C
76
4C
92
5C 108
8C
124
7C
13
DO
29
10
45
2D
81
3D
n
40
!a3
50 109
GO
125
~
14
OE
30
1E
q
2E
82
3E
78
4E
94
5E
110
6E
128
7E
IS
(IF
31
IF
47
2F
63
3F
79
4F
95
SF
111
SF
127
I..-
o
~ESS FOR~Hf1IU 1%7 ~TS
~
0
~
1
2
~
FF
FE
L...-
CO~ZI!AO A~OND A;esS AI"TE~_ MN~IC
17
~
EF
18
EE
33
~SS'OA~l21~
OF
34
OE
41
CF
50
CE
65
BF
86
BE
81
n:
~
'7
9F
--,,3
SF
ge
114
BE
r-AF
~
82
AE
98
3
Fe
19
EO
35
00
51
CO
67
BO
83
AD
99
90
lIS
so
4
FC
20
EC
38
OC
52
CC
88
Be
14
AC 100
tC
,,8
8C
5
Fa
21
ea.
31
OB
53
C8
sa
BB
85
AB 101
9B
117
88
8
FA
22
EA
38
OA
54
CA
70
SA
88
AA
102
9A
118
SA
7
Fe
23
Et
3t
09
55
C9
7,
Bt
87
All 103
99
"9
89
8
,
F'
24
E8
40
08
58
C8
12
88
88
AI 104
98
120
88
F1
25
E7
41
07
57
C7
73
B7
89
A7
lOS
'7
,21
87
,0
Fe
2e
EtI
42
06
58
C6
74
B8
90
AS lOS
98
122
86
27
es
43
05
51
C5
75
85
91
AS 107
95
'23
85
"
F5
12
F4
28
E4
44
04
80
C4
78
B4
92
A4
loa
94
124
14
13
F3
29
E3
45
03
81
C3
n
B3
93
A3
109
!a3
'25
83
14
F2
30
E2
46
02
82
C2
78
B2
94
A2 "0
92
128
82
15
Fl
31
El
47
01
63
C1
79
81
95
Al
"I
91
,27
81
FO
32
eo
q
00
64
co eo
so
98
AO
112
eo
'28
18
l..-
-- ---
--
I..-..
~
COUNT ONE AT ',AST ADDA!SS ioniA JUM~ MNEMONIC
L...-
80
I--
r
\'
•
_F_IG_U_R_E_l_~
______D~E~C~IM~A_L_/_HE~X~ADECIMAL
RELATIVE OFFSET TABLES
29
,,,u,,a=a,U'IM,,; ;
_ _ _IW&iiA&ii=-i\&Z'UIMMii# :;;AIA"M"; ::;,• •,,,,,,_••
o
Interrupts
The 7803 has two interrupt request inputs which are accessable at the STO BUS
backplane: NMIRQ* (pin 46) and INTRQ.* (pin 44). The characteristics of these
interrupts are:
NMIRQ* -.
Nonmaskable interrupt request cannot be disabled by the program.
The processor stores the address of the
next instruction in its program on the Stack using the SP as a memory pointer,
then jumps to memory address location 0066 hexadecimal. Any return-from-subroutine instruction may be used to resume the inte.rrupted program, but a special
RTN (Return from nonmaskable interrupt) instruction is included to inform any
z80 peripheral chips in the system that the interrupt is over.
INTRQ* - Maskable interrupt request can be disabled and enabled by the program,
and can operate in one of three modes:
1. Mode 0 is identical to the 8080 interrupt system.
The processor issues INTAK* (interr.upt acknowledge),
which is used as an enable signal by the interrupting
device. During INTAK* the interrupting device places
an instruction opcode on the 7803 Data Bus, which the
processor will execute. Either a I-byte or 2-byte
opcode may be used. If the opcode is part of a multibyte instruction, one or two additional bytes must be
placed on the Bus following the opcode (for example,
a jump instruction consists of a I-byte opcode and
two addional bytes of jump-address information).
o
Note: The Z80 will execute one interrupt acknowledge
cycle and issue one INTAK* pulse for a one-byte
opcode, or two cycles with two INTAK* pulses for a
2-byte opcode. However, it will not generate INTAK*
during any subsequent
cycles that may be required
by the specific ins~ruction being executed.
2. Mode 1 is the implied vector mode, with the implied
vector address equal to 0038 hexadecimal. In Mode 1,
any INTRQ* results in a subroutine jump 'to 0038.
3. Mode 2 is the supplied vector mode.
The user preloads
Register I with the page address of an interrupt vector
lookup table which is part of the program. When the
interrupt is acknowledged by the processor, a single
INTAK* pulse is issued which causes the interrupting
devic e to place the correct memory line number of the
interrupt vector lookup table onto the STO Data Bus.
The processor will then go to the lookup table at the
address supplied by the peripheral; read a 16-bit memory
address from two sequential entries in the tabie (line
address followed by page address); and jump to that
location in memory.
o
30
o
INTRQ* is enabled by the ENI instruction, and disabled by any of the fOllowing:
a.
b.
c.
d.
Power-on or reset
The OSI instruction
Previous response to INTRQ*
Previous response to NMfRQ*
Z80 Peripheral Chip Considerations: When used with z80 peripheral chips, such
as the- PIO or 510, these considerations and othe~ may apply:
a. In Mode 2, the I-byte vector supplied by the interrupting device
must be an even number with bit 0 = O. This is a requirement of
the peripheral chips, not the 7803 which will accept odd or even
vectors.
b. In Mode 0 with either JS or JI instructions inserted, and in Modes
land 2, the interrupt routine should be terminated with RTI (for
INTRQ*) or RTN (for NMIRQ*) instructions. These execute like RTS
in the 7803, but the special opcodes inform th~ peripheral chips
that the interrupt routine is over. The peripheral chips then
respond by restoring the state of the serial Priority Chain.
It is recommended that the user thorough~ acquaint himself with all the
characteristics of~r peripheral chips~~fore attempting the program design.
o
•
31
5
SECTION
o
PROGRAM INSTRUCTION TIMING
Introduction
The execution of a program instruction is a sequential process. The time state
clock
is used to step the z80 through a specific sequence for
each instruction type.
The execution time for each instruction is the total of
the time states needed by the instruction, with the time state period set by the
processor's clock oscillator.
An understanding of the Z80's instruction execution timing is importarit
in real time programming, where the program's execution rate is precisely matched
to the speed requirements of the application. When using a signal or logic
analyzer, a knowledge of the time state sequence makes it possible to
predict the data and control states present on the STO BUS backpJane and at the
z80 chip pins at any given instant in the execution of a program (Fi'gure 311~
Machine Cycles
Each transaction between the z80 and its memory and I/O ports requires a distinct
time period called a machine cycle. Machine cycles are composed in turn of
time states, with specific activity occurring in each time state. Although the
number of time states and machine cycles vary among different types of instructions,l
they are precisely predictable for any given instruction.
Figure 23 is a timing diagram for the STAD (STore Accumulator Direct) instruction.
This instruction requires four machine cycles (Ml through M4) with a total of 13
time states. Four machine cycles are necessary because the instr'uction accesses
memory four times.
~
0
____________________________ I~UcnONCY~----------------------------~
MAQ4I..- \e-_ _ _ _ _oM. _ _ _ _ _~_--M2---~-----M:I---~~---AM----~
CYCI.E
TtMI STATE
T2
T3
T1
T4
T3
T2
T1
T2
T3
T1
T2
T3
CLOCK'':
TYPE OF
MACHINE CYCI.E
ADORESS BUS
DATA8US
MEMORY READ
MEMORY READ
THE ADDRESS (CONTENTS OF THE
P"OGRAM COUNTER) POINTS TO
THE FIRST BYTE (OPCODE) OF THE
INSTRUcnON
INSTRucnON OPCODE (HEX 32)
FIGURE 23
THE ADDRESS (PC +1)
POINTS TO THE SECOND
8~OFTHE
INSTAucnON
I
1..41" ORDER 8YT1! Of'
THE DIRECT ADDRESS
MEMORY WRITE
MEMORY READ
THE ADORESS (pc • 2)
POINTS TO THE THIRO
BYTE OF THE
INSTRUCTION
THE ADDRESS IS THE
DIRECT ADDRESS
ACCESSED IN M2 AND M3
HIGH ORDER BYTE OF
THE DIRECT ADORESS
output to memor
CONTENTS OF THE
ACCUMULATOR
PROCESSOR TIMING FOR STAD INSTRUCTION
32
o
•
The first machine cycle in the instruction (Ml in Figure 13 ) is used to read
and decode the operation code (opcode) from program memory. Ml is called the
oe code fetch cycle, and can be identified by an active pulse on the STATUS 1*
output from the 7803 (also at the Ml* pin on the z80 chip).
Many z80 instructions use 2-byte opcodes. If the first byte has a hexadecimal
value of CB, DO, ED, or FD, a second byte is r~quired. The Program Counter
is incremented and the Ml cycle is repeated to read the rest of the opcode.
STATUS 1* is asserted a second time.
Each Ml cycle requires a minimum of four time states (Tl through T4 in Figure 25),
but this may be stretched to up to 11 time states in some instructions, allowing
time for the instruction to fully execute if no additional machine cycles are
needed. The shortest instructions use one machine cycle with four time states;
the longest require six machine·cycles (two Ml opcode fetches plus M2 through M5
for additional memory accesses) with a total of 23 time states.
When the Z80 interprets the first opcode byte during Ml, it will add additional
machine cycles to the instruction if it finds that:
a. The instruction has a 2-byte opcode; and/or
b. The instruction has 1 or 2 additional by.tes of data,
memory address, port address, or relative offset appended
to the opcode; and/or
o
c. The instruction requires the processor to access memory
or an I/O port as part of the function performed by the
instruction.
For example, the STAD instruction in Figure ~ is a 3-byte instruction (l-byte
opcode plus 16-bit memory address in the two bytes appended to the opcode), and
STAD is an ins truct i on whose funct i on is to sto.re aa·ta i.n memory; Therefore
STAD requires 4 machine cycles with Ml used to read the opcode, M2 and M3 used
to read the specified memory address, ·and M4 used to perform the operation of
storing data in memory.
WAIT States
Although the minimum number of time states in any given machine cycle is fixed,
the user can insert one or more WAIT states in the cycle. WAIT states are added
by driving the 7803 1 s WAITRQ* line active during the T2 time state in the machine
cycle where the WAIT state is desired (Section ~ for timing). The WAIT state
is a do-nothing time period that ·can be used to interface slow memoryes to the
7803, or to cause the processor to pause while a slow system function (such as an
analog~to-digital converter or arithmetic processor) completes its task.
The
effect of holding WAITRQ* active indefinitely is to halt the processor; when
WAITRQ* is released, the processor resumes operation with no change in its internal
data or control states.
Note that the Z80 adds one WAIT state to all I/O access machine cycles automatically.
Additional WAIT states can be added by the user if desired.
•
Naturally the addition of WAIT states must be included in the computation of pr.ogram
execution time in real-time control applications. Each WAIT state requires one
full time state clock period •
33
,#
n
o
DMA Mode
Direct Memory Access (DMA) operations are controlled by driving the 7803's
BUSRQ* line active when sampled at the end of any time state. The processor
will complete the current instruction, then float its Data Bus, Address Bus,
BUSAK* then goes active.
and many Control Bus lines (Figure 3).
The BUSAK* output signifies that the 7803's 3-state bus drivers are in the
OFF condition, allowing an alternate system controller card to operate the 7803's
memory, I/O, and other peripheral cards. Internally, the z80 is halted in a manner
similar to the WAIT state, with internal data and control states unaffected by
the DMA operation. BUSRQ* can be held active indefinitely, but the dynamic RAM
refresh operation is halted during DMA operations.
Note: the 7803's onboard memory sockets are not accessable in DMA mode, and
the processor can't be inter.rupted by INTRQ* or NMIRQ*.
Instruction Timing Table
The table in Figure ~~ shows the actual number of memory bytes, machine cycles and
time states required for all of the z80 instructions. ~ Two time state periods
are included for convenience with the full execution time of the instructions
shown for each.
o
o
34
o
<
~
<
=
,
D "'"
2
l
2
T
28
"2
13
,
,
76
76
I
2
19
19
9
1
2
2
5
1
7
2
3
5
12
1
2
5
,.•
1.1
3.2
1.2
15
23
'.0
t.2
I.GO
2.00
'.50
175
5.75
•
•
INCl'CII8fT. DICRNINT 'A'" IXCI" II Ott '"
INCRIMeNT. DleRlMlNT II OR ."
2
LOAD
<
~
<
Q
LOAD ......DIATI TO Ie. 01. He.. •
LOAD I.....DIATI TO II Ott ,V
LOAD HL TO OR "'OM MIMO"" D'''ICT
LOAD K. DE. •• II Ott ." TO 0" '''0il 111110"" D'''ICT
LOAD. WITH HL
"
I
•5
•,
~
LO.o P WITH .1 OR '"
2
2
0
.......
-
3
I
3
•3
I
2
1
•
•
1
2
3
3
•
...
'.0
'.0
2. •
10
"0
,.'0
'.0
5.'
,.
20
•
'0
11
2.75
175
1.0
U
...
10
'.0
lANK SlUCT
"EGISTE" lANK U OR KIGE,"L
I
1
EICHANGE
01 W'TH HL
T~ OF STACK WITH HI.
I
I
I
5
T~ OF STACK WITH I. OR '"
2
IMIUT OR OUTPUT DtMCT
INPUT OR OUTttUT 'NO'MCT (C)
2
2
•
"
It
•
23
3
11
l
12
1.50
2.50
'.0
•••
3
,.
2.75
3.75
3.75
2.50
150
'.GO
5.00
1.50
2.50
'.0
•
Fl GURE 24 A:
11
'5
IS
15
2
OUTttUT
"
•
I'ULL II OR ."
'WUT
2.00
100
5.00
1
2
2
I
U. IC. Of. HL
1.2
•
INCReMENT
QlCMMINT
~LL
•
•••
1.0
2.00
3.75
5.75
2
2
~
20
1.00
2.75
5.75
3.2
'.0
'.2
"
A'. Ie. 01. HI.
•
1.1
15
23
2
2
~SHlllORI"
1.00
1.15
1.75
'.15
•
•
2
2
"IGII"'''
111110"" INO'''ICT (HL)
111110"" INOEXID ('") 0" 11'1,
~SH
16
2.1
2.1
7.1
'.2
.00 TO HI.
.00. _TRACT WITH CM"" TO HL
AGO TO .ll OR ..,
~
1.00
2.00
23
"
325
, 75
1 75
2.50
, 75
16
3.2
•
3
"
11
100
, 75
"5
2.25
,..
I
3
2
2
•
025".
H
11
I
I
AOO
aulTRACT
...
i
I
I
"l
I
21
2
1
:I
ACCUMULATOR
"IGISTI"
ACCUMULATO" IlULn"-l W.TH MillO"" (HL)
IIIIID"" INO'''ICT (HL)
111110'" 'NDEXED (Ill) OR ('Y)
28
, 0
AIGIITI"
IMMID.ATI
MIMO'" INO'''ICT (HL)
111110"'1 INOIXIO "ll) 0" (''1,
IHIfI'T.
"OTAT!
S2
7
.00.
SUIT"ACT.
LOG'CAL
"IGIITI"
111110"" INO'''ICT (ML)
MEllO"" INOIDO (Ill) 0" (I'"
I
10
,
IIIIG'ITI"
111110'" INO'''ICT (ML)
111110"" INOIIID (Ill) OR (''''
' 6
I
2
3
5
5
2
2
3
"I
leT. CUA" I.T
•
.0
7
1
2
TlST lIT
i
STATES
1
2
I
•
,
""AD. CMAL. CUC. CLC. SIC
CMU
CD
o
CYCLES
,
ACCUMULA TOA.
CAAAY
INCRIMENT
DECREIIENT
I
IYTES
AI GIS TEl' TO AIGISTIR
IMMEDIATE TO AEGISTER
ACCUMULA TOA TO OA FAOM MEMOIilY DIRECT
ACCUMULATOR TO OR FROM MEMOIilY INDIRICT flC) fDElfH1.1
IIIEGIITER TO OR FAOM MEMORY IND.RECT fHL)
IMMEDIATE TO MIMo,n INOIAICT (HL)
RIGISTIR TO OA FROM MIMO"Y .NDElID fll) OR (IY)
IMMED.A TI TO MIMOAY INDElIO ('X) OR (''1)
ACCUMULATOR TO OA 'ROM INnRAUI'T OR RI,RISH
0
t::
I
OESCAU'TION
INSTAUCTION
1.0AD
STOAE
5.1
2.50
l.50
1.1
1.00
1.1
7.6
9.2
1.GO
'.75
5.75
..•...
2.75
l.OO
zaO INSTRUCTION TIMING SUMMARY
35
_
"u,,;;,;;"".
Olsc.,n,o..
1. . .TltUCT10..
JU ....
en
en
W
CONOIT1ON:
CONOIT1Q1t:
SU.ROU"'"
..ITU....
LOOP
aLOCK
LOAD
COHDtT1ON:
Dc...B~
'LOCK
SEA..C"
aLOCK
INltUT 'OUTItUT
'''TI"""..T
W
~
%
(J
4(
:I
MIT
NOT MIT
1
1
M'SC.
G
0
., Ie 0
~ IF Ie" G
I
llLOCK
co.........
MEIIO"Y
INltUT 0" OUTPUT
TO 1111110""
I
.oJIQ
I
WOIltO
NO..
HALT
LOAD . . . . . . . MGISTE" TO OR
24
B:
2
1
2
2
2
•
•5
2
2
2
2
2
I " I '0
aLOCK
,F 1/0
""* ACCUMULATOR
"l
STATU
G.'''.
•
1.1
1
n
lG
12
12
1
•
•5
•
•
--
"5
'.4
2.0
1
12
2.0.
13
U
11
21
"
I..
I..
1.4
11
11
I..
I..
,.
11
1
1
4
2
,.•
2
t
1
1
1
2
2
U.
1.00
1..
1.71
••25
2.10
2.1'5
t.25
n
•
•
•
...
1.4
1.4
1.4
1.'
1.2
$.I
11
1.'
1.'
1.
o
1.75
"0
2
1
1. •
10
21
•
1..
"10
5
2
2
~2
•••
'.0
...•••
I US ...
1.1
I..
I..
.. 0
,7
1
2
2
2
IIFIC'OO"A'M
I "IC/OO.. A,M
a"ocx
E.....UIOtSA.U '''TI".. UPT
SET 'NTl""UPT 11001
..1TU.... ' ..OMINTlRRUPT$
LOAD INft"RUI'T UGlSTt" TO OR AtO.. ACCUMULATOR
FI GURE
I
.0..0
MOW
.....OR.,
0
(J
1
I' •
., a
Z
:::)
U..
MET
NOT MIT
U..
4(
0
Q.
:I
0
MIT
NOT MIT
1
2
J
l
l
l
2
5
5
l
l
l
INOlltICT: LOAD ~ WITH HL
LOAD ~ WITH IX Olt "
.IU. . TO ...TI....U ..T
O.ltICT A..Y CONOITIO ..
QUTIVI
ex
~
C.,CUS
1
Z
1
J
2
2
2
2
l
l
u..
0
C
.-CC
rn
IYns
"25
U.
...•••
......
...
1.25
s.2I
5.25
'.00
5.25
1. •
2..
UtI
2.25
U.
1. •
2021
o
Z80 INSTRUCTION TIMING SUMMARY
o
36
o
Instruction Timing Example
The execution time for any routine or program segment is found by totalling al I
of the time states in all of the instructions executed. The factors affecting the
execution time of a program segment are:
a. The clock frequency, which determines
the time state period (Section '3 ).
b. The specific instructions used, which
determine: the number of time states in
the segment (Figure 2.,4 ).
c. The instantaneous Flag (Regi$ter F) bit
s ta tes wh i ch 5 umma r i ze proces sor cond i; t ions
when the conditional instructions (jump,
jump-to-subroutine, return-from-subroutine)
are executed (Figure 2..1 ).
d. The number of instruction loops within
the instruction sequence, and the number of
times each loop is executed (loop iterations).
o
e. If the program segment has more than one
entrance or exit, every combination of routes
through the segment that are used by the
program should be considered.
The following example shows how to compute execution times in a program segment.
The Z80
is programmed to generate a series of five short pulses at an output
port bit line. Determine the overall execution time of the program segment and
the period of the pulses generated (the output port bit lines are low when the
segment is entered; only the bit 7 line is of interest).
••
•
WAVEFORM GENERATED
PUt.-Sa ~N"
\..\J-lE
ONee
•
,,
_<:.rr
j l.
os
OP"
~~
4
,f!)A14
}blfr ~
~c!JS
'"p
D
It'!LAl!
,
OPA
I
oJ
FIGURE
2£:
37
.~
~".r!Y'l
-"r.t::'
.~
~
~/\JI" """
A,r '1 •
.LiUiiLH..
I
~
7
"'U7"'~IJ_
~~ ('ju~r
.~~
•
•
..•
•
c
"'''''UJr
I/v\P
I ,,!,~
11"
1t!.LAt!
L~II
J
I
•
',7:
L..1I~
..,r
~_
~OA
G:JZi
T
,.%.0
j .. ,,-Cl'
r
-
.tP;N"~~2i
•
~A 1'1&'
c,rr'tJr
?()Al~.a".,.~
T
I!aM
~
...
I NSTRUCTI ON SEGMENT TI MI NG EXAMPLE
,,0:)....
_
__
~
~
_
__
~
~
·
___
•• _ •• ,w • • • • •
.- ---------------_.. _-_.---------------_._._------------------.--------------------------
In the example in Figure
,six of the program segment's nine instructions are
within the loop and are executed five times each. Three of the instructions
(LOBI, CLAC, OPA) are outside the loop and executed only once.
FLOW DIAGRAM
FUNC·TION
Set loop
count
5
Pu 1se outpu t
line once
_Tlf1ES
:-.PERFORMEO
INSTRUCTIONS
Once
TIME
STATES
2.8 us
4
1.6 us
11
4.4 us
7
2.8 us
11
4.4 us
4
1.6 us
10
4.0 us
CLAC
74
1.6 us
OPA
PORT 00
11
4.4 us
05
:II
Five
times
CLAC
OPA
PORT 00
LOAI
80
LOOP
--
DeB
times
Leave
output 1 ine
low
JP
Once
,FIGURE lJo :
The total
OPA
PORT 00
- - -- - - - - - - Five
Test for
end
execu~ion
EXECUT10N TIME IN
400 NS 7803 SYSTEM
7
LOBI
o
ZO
LOOP
o
SAMPLE TIMING CALCULAT10N
time for the instructions performed once, outside the loop, is
2.8 + 1.6 + 4.4:11
8.8 us.
One pass through the loop requires
1.6 + 4.4 + 2.8 + 4.4 + 1.6 + 4.0
:II
18.8 us.
The loop is repeated five times, so the total execution time for the program
segment is
8.8 + [(5) (18.8)] :a 102.8 us.
The period of the pulses is found by adding the time the pulse is low to the
time the pulse is high. The pulse is low from the end of the first OPA
instruction to the end of the second:
2.8 + 4.4
7.2 us.
==
The pulse is high from the end of the second OPA instruction until the end of
the first (around the loop) or until the end of the third OPA (the fifth time
through the loop):
1 .6 + 4.0 + "I .6 + 4.4 =- 11.6 us.
The total period of each pulse is
7 . 2 + 11.6
==
18.8 us.
38
o
o
10
SECTION
Memory
- MEMORY AND I/O MAPPING AND CONTROL
Addressing
The 7803 1 s 16-bit Address Bus can directly address a 65,536-byte (64K) memory.
A specific memory location is addressed when these conditions are met:
a.
The Address Bus contains the specific address of
the memory 1oca t ion (0000 th rough FFFF hexad.ec i rna I ) ;
b.
MEMRQ~': (memory reques t) and RD* (read) or WR* (wr i te)
control signals are active;
c.
MEMEX~':
(memory expansion) is act i vee
Other factors affecti ng the 7803'5 control of its memory are:
a. In the Interrupt Acknowledge Cycle ..
the 7803·· issues INTAK* in pJa~e of the memory enable
signals, when responding to INTRQ*. This causes the
interrupting device to provide an i"struction or vector to the 7803
over the STD Data Bus.
b. The 7803 can pause to wait for a slow memory-mapped
device,or be single-stepped,by inserting WAIT states
in memory access machine cycles. See UAIT~Q*, Section
o
c. The 7803 can disconnect from the STO BUS and enter the
WAIT state while Direct Memory Access (OMA) operations
are conducted by an alternate system controller card.
OMA is controlled .by the BUSRQ*/BUSAK* (Bus Request/
Bus Acknowledge) si~nals.
A tyl' i ca 1 memory imp 1eUltm~a tlon 1 S c;shown in Fi gure 2..S
12K-Byte Onboard Memory
The 7803 card :,as a combined ~PRc.,M/ROM and RAM memory on the card which is large
enough to store the program and variable data required in many applications, without
the nee~ for aJ~i tional ext~rnCll memory cards. The card is shipped \'1i th lK of ~:.
and socke ts wh i ch a 11 ow the user to add up to 8K of EPROM or masked :~OM dev ices and 1b
expand the RAM to 4K. The onboard memory sockets have addressing restrictions
(Figure 2.7) and are not accessal:·le in OHA operations.
The onboard memory is organized as fol1~~s:
a. EPROM/ROM sockets: provide capacity for four 2716
single +5V supply EPROM devices which can be mixed
with 2316E or equivalent masked ROMs. Each device
read-only memory for a total capacity of 8192 (8K)
these devices are supplied by the user.
•
Figure
,~
or equivalent
in any combination
is a 2048-byte (2K)
bytes. All of
b. RAM and RAM Sockets: provides two 2114L or equivalent RAM devices
organized as a l024-byte (lK) memory, and sockets for six additional
user-supplied 2114 RAMs. The 2114 is a 1024x4 devic~ and two chips
are required for each lK of RAM added to the card. The total RAM
capacity of the 7803 with all sockets loaded is 4096 (4K) bytes.
summarizes the addressing options for each of the memory chip sockets .
39
# 4
WW**,,_:::mI4TM i#i# ;;;, ....\
r "
•
* .
q
"R",#"4 4*, RAW
« $ ..•
o
MEMORY DEVICE
DESIGNATION
J::.
u
-
'-0
10
IU
--.-
,.....~
NN
ROM
ROM
ROM
ROM
RAM
J::.
RAM
-J U
.::r co
- u RAM
N~
RAM
10
0-
--
-
0
1
2
FULL HEXADECIMAL ADDRESS FIELD
USER OPTION (Note 1)
AS SHIPPED
-
C7FF
CFFF
17FF
lFFF
COOO
c800
0000
0800
23FF (Note 2)
27FF
2BFF
2FFF
EOOO
E400
E800
ECOO
-
E3FF
E7FF
EBFF
EFFF
-
07FF
OFFF
3
0000
0800
1000
1800
U20,U24
U19,U23
U18,U22
U17,U21
2000
2400
2800
2COO
-
UNUSABLE
(Note 3)
Notes:
FIGURE 2..'1
3000 - 3FFF
D7FF
DFFF
FOOO - FFFF
1. Refer to Appendix}\ for remapping option.
2. lK of RAM (two 2114L deviees) mapped in
addresses 2000-23FF are supplied with the
7803.
3. Maximum 7803 addressing range is 60K (12K onboard
memory plus 48K on external memory cards) when
the 7803 onboard memory is used. If the onboard
memory is disabled (Appendix A ), maximum system
memory size without bank selection is 64K and no
mapping restrictions are imposed by the 7803.
o
7803 ONBOARD MEMORY SOCKETS ADDRESS MAPPING
o
40
•
•
o
-----.---------..
w..-:x •
~
CI
0
IQ't
II,
I
AI'
"'..
(~
Iii
loI\.
CHlPllElECT
OCOlXlER~
1110
......
All
Ait
~
.....
@--l!r
A"
A1
AI
A'
A:t
PCI
~-"g
-tr
•
~_
I
A',
I
~
"'t
I
II
Aa'
~-J
I~.--1Lt
@}-_ _ ..
t-'
'L~TI
"~
~
...
~t--1---
¥
110".
¥
I--+--'
-
(!)-
_"0
~
II I t.V
lit
oott.._.®--------I ~--;1tav
-~
~
P<O@-II ...
U~
IS
&--
.
' c:.A.... I':.-~t
~-- J -•• v
lOY
U\I
&JtlMPER
_5_ '
''''/f I!UU.S
ASUtllILY
102714
PAIlTS LIST
lOl. 715
()
Inout/Output (I/O) Port Addressing
The 7803 can address up to 2S6 each input ports and output ports. The port
address appears on the low-order half of the Address Bus (AO-A7) and is
repeated on the high-order half of the Address Bus (A8-AJS). A specific
.1/0 port is addressed when the following conditions are met:
a. The Address Bus (AO-A7) contains the specific address
of the I/O port (00 through FF hexadecimal);
b. 10RQ* (I/O Request) is active
c. IOEXP* (I/O Expansion) is active
d. RO* (read) is active to select an input port, or
WR* (write) is active to select an output port.
The a-bit input ports provide a means for reading data or status lines into
the processor to take part in programmed operations. The a-bit output ports
provide a means for outputting program-generated data or control states. Typical
input and output port circuits are shown in Figure ~q .
o
o
42
o
47
BUS
RSi.Jt
U7
07
B
10
0:'
04
12
\4
i
02
01
DO
~
II
13
~
II
.....
13
......
15
......
I'
'\
e
'\
BUFFERS
,/
2
~
UI
7t\oLStt\o4
"
..L..,.- D1 ~
....
13
~
~
~
OUi
....
1'5
~
~
""""- , .
B-
~
....
......
......
Y
IS
IZ
57
0
13
74LS4~
C.
S5
54-
AiD
17
14
~
S~
SZ
15
AS
A
"
0
03
IA-
02
.....
0--..
.....
~
01
~
15 DO
-.........L
33
Alit-
t,
A~
2~
SI
SO
~
!'Z
X"l
0
7 16 _
IJ;:l.
XS
(a
,~
S~
~
)
AD
27
~
o!
7
C~
9
e!
13
"
o!.
I~
0
1
~
S~
~A
\~
74LS42.~"
C.
5S
14
I~
~
S3
IN
sz
A
51
~
I~7.
7
t'5(.~
ID
tS3-
S
I~4"
4-
r!)~.
3 152.
2
tSI-
I IS01
.:...-.
GLI TCHFREE USER
:t..-. OUTPUTS
!1..,.....
P
~~
I'
~
18
f!4.-.
RSi•
()7
'I '7fUl#
7.
.,.
'"
O~
~
0..-
12-
' YO.-..
"-
0;
q
~
.........
0'2.
,
"-
01
S
IS'
00
3
I' .,
l YI
SO
INPUT PORT
O~
n
3 12_
SI
.,....-...
~ LATCHED,
~
.. Y3
5Z
Z 1.1
,
Sy
r:=
~.JU7~
"
,,,
-~
~
(,.yp)
-)J-
e
II
11
.'P
GATED
USER
INPUTS
~
-....
.....
rep
rso~
i4LS32
PORT SELECT DECODER:;
SO
•
...
•
~
-
S4
AI
o•
r 't
ss ~
Co
It
I XO
pl-
S4
4-U
~
~
Sf.
~
~c US 57
25
""""-
oso""'"
I~ i4L~3Z
AZ
~ 1ff..S113 '2.
A
S7
74t,54Z
514-
WIU 31
RO_ 32
0"7
00
11~
.&
IORQl
~
r'\.
......
II
OUTPUT PORT
CARD SELEC,T DEC.()DERS
U.3 Sf.
A7
12,
,
/
"
~s
o.
0--..
\~
fIJ
41~
lOEXPt
~
~
~
~Oo
'2.
,~
~
~
~
4
;
.~
7 O~
~
IS 05
~
¥
'\
~'\
U2.
'4l5Z_411-
~
s
,
~
C
U~
S7
51.
13 74L54,
C.
5S
,.
I~
-
54~
OS7~
7
os~.
1II
05S~
IS OS'"
4- 053-
c:.;
~
OUT sz
A
~
ClSZ-
2 (,51l
SI
~o
I 051)
*
-
FIGURE 29: TYPICAL INPUT & OUTPUT PORT IMPLEMENTATION
This figure illustrates the Bus interface and I/O port address decoding circuitry
and device types typically used to implement I/O ports. Pro Logls 7500, 7600, and
7900 Series I/O modules are similar to this example.
43
SECT' ON 7
- PROGRAM AND HARDWARE OEBUGG I NG
o
Microprocessor Logic State Analysis
An attempt at monitoring the execution of a microprocessor program in real time
using a conventional multitrace oscilloscope will be found to be impossible for
practical purposes. The capacity of the scope and the operator will be quickly
exhausted by the following characteristics:
a.
b.
c.
Parallel data and addresses. Data is transferred as byte-parallel
information (the address bus is 2 bytes wide). Individual bits on
these busses have little meaning in program debugging. ft is necessary to see the full content of both busses at once, and a hexadecimal
display of numeric values is much more meaningful than binary waveforms.
Disola Trj er ualification. As many as 20 signals (combined
address and control signals may be used simultaneously to qualify
the enabling of a peripheral memory card, for example. In order
to capture this event, the test instrumentati"on must also be
trigger-qualified by the same group of signals. Conventional
oscilloscopes lack the number of trigger channels and operating
modes needed to interface with a processor system such as the 7803.
Data Bus v~ttage Levels and Timing. The 7803 and all of its peripheral
cards in a given system will drive the Data Bus at different times, and
will do so with a variety of logic high and logic low levels, all of
which are different but within specification.
This presents two problems:
1.
2.
The operator will find it difficult to identify the source of any
given waveform on the scope display.
In order to see a specific data segment on the Data Bus, the operator
will find it necessary to synchronize the display with the processor's
software program rather than with the voltage output of anyone element
of system hardware.
o
The logic state analyzer solves these problems by displaying formatted
high/low or numeric logic states rather than analog waveforms, and by
offering enough trigger channels andcoincedence logic to allow literal
program/display synchronization.
A logic state analyzer is considered an essential troubleshooting aid for both
program development and system maintenance in any 7803-based system where the
needs of the Manufacturing Test and Field Service organizations are important
considerations.
The logic state analyzer performs these basic functions:
a.
b.
c.
Tracks the actual instruction sequence as the program executes,
facilitating program debugging.
Monitors control states and data passing between the processor and
the system it controis,allowing the system external to the processor
card to be observed at the same time as the program fl~, using the
same display.
Provides a multi-qualified trigger to a conventional oscilloscope when
analog measurements are unavoidable (e.g. propagation delay through a
suspected memory device).
44
c:>
l
o
6,"'
blf..bId
,ut!Ji¥6:t
1..!tl!+UtLJ
"!
'!
"Mil!
Instruction Diagnostic Tables
The Instruction Diagnostic Tables on the following pages are used
with a logic signal analyzer. They show the type of data on the
Data Bus for time states Tl, T2, and T3 within each machine cycle, and the
mach i ne cyc 1es wi th in any g i yen i. ns t ruct i,on.
This information is useful when debugging a program or troubleshooting the
7803 or any hardware under the 7803' s control.
.
In addition to expected data and processor status for T1, T2, and T3, the
TIME STATES column in each machine cycle shows the total number of time
states for that cycle. If there are one or more time states after T3, the
processor is performing an internal operation; th.e signals at the
z80 chip pins are either unchanged from T3 or undefined, with no new information
avai lable unti 1 the next Tlo
Because of the size of the z80 instruction set, the Instruction Diagnostic
Tables are separated into the following sheets by instruction type:
INSTRUCTION CATEGORY
8-Bit
Register
Memory
Data
Load/Store
I
Accumulator &
Carry
Arithmetic &
Logical
Increment &
Decrement
Bit Test/Set/Clear
Shift & Rotate
&
o
16-Bit
Register
Memory
Data
INSTRUCTION TYPE
Add & Subtract
Increment &
Decrement
Load & Store
Push & Pull
Bank Select
Exchange
&
I/O
Input & Output
Address
Compound
Jump & Return
Loop
Block Memory
Move E- Search
Block I/O
Machine Control
FIGURE 30:
Interrupt
Halt, NOP
FtGURE
31A
31A
31A
31B
31B
31B
3IC
31C
31 C
31 C
31C
-)T C
310
310
310
31 D
31 0 E
9
31 E
~lE
INSTRUCT' ON 0 IAGNOST I C TABLES INDEX
•
45
--
III' .u
_cYCUl
__
__
_
fffr¥.
Inr~:-..:::.
,1,111 L_ _ _ to_...._
alal,IL_ _ _ _n
MACHINI CYClEI
_
.. 1.,..",,1
fC
PC
.:::.1_.. 1""",,1
...., ..
==:.1:_
1::...1=-
I
I
I pc.,
......
MACHINE CYClEt
..
.fA1'I.
.......' ... 1
t=.J:fC ••
-.-,-...
~I.I.I. -.--...
1m
_nl'O
Maea,. . tOtflMlll
·.....
.p..
0)
0«
i
~
.....
,
,
•
_._.... I . I
~:::::0..
pc.,
=:'.I5"=.. -
•
I
,
-.,
,--
.e. ,
U_'ACcwa&Al'_
t ' • ,.
• fAn.
..l'c....,
pc
pc
_c:.
"".OII.lIOII.c.
fC
""._lIOII.c.lIIl1O.'
II ... ",..1M ACC&IIIUUIOIO
pc
u
_.
...-......
=~=cial:~ria
:MIMOA,
I. I
I=: I--",t-.-
~,oc-;-at_Ail-+O'C..MO., 1-..c.•• 10.0110
I' 1..._",-..o..'D.U
I-f--
1-
........._IOOI.c. ......' ..
pc
AQlloa.aoa.CP.""
til. , ..... MOCUoIULAIOIo
I.'
I '.11
U
, .11
'OAI"
Ol.
---+---I
liOiiI+wiiin+CiPt---.wiD--f----;-----1
!III
-.--~5=t12·1:::Pc.MiMit1
..
CAltD'
c.....
J------I--
.. I
_
..._
1-----pc
d- h--
_..
,
-~--
.A'A
J!&l
.c.,
OH.......
--All
•...-,-. - - -
•
m1~~~=1-·j-n-ct
I I 1=1 I I
~t-I--t----f--t---+-~
1."
1---1-
_110M
_,COOl
_ Aec:uMUU'"
u,
'-II
1----+---1
--I-----t-----I
ONIIA'''*
_.-
.. ---_.-
---t-------
::"'J=-
wmtOll
_Ml_'-"ILI
_
ADO _ _
MIlt 010 WlfttOU1
_.u:CUIOUl.., . .
1-----1-
f----f--I
,~
.c
.. AO
ADOCMI_nw:J
n.
MIlt
010 wnllOU'l'C......
_
_
.u:CU"lIl"'" _~_ _~____+-:,.,.
A"8o.eue Ml.IrillUAV,a. '.
",m.oalMTttOUTC_.
laTen.
=1::c:..1fu~~----I----I--~-------t---I--I--+-
pc., MAo- MW"-
..-, :,n
J--I---I--f--'---~
----- t-
Il-WI
I--+---I-----~----+----~--I--------I--I--
~---I-----J-
FIGURE 31A:
o
--.1--1
1 • I
f-I-_~AC.CuMUU'CMI
•
.,
..... CMI _ _ _ C'
.--.__ ~
I
... I 1__
fC
MAO
I ' ,.
.:::.1"""....1" ..""
_IIC_ ....e
CLCICII ClClCli
=~I=-,t..~-
=~I=..,I=:-
I I I I
'-:.,
=:f~'
_~TCIII
iI
fC . .
~'_IO.AQM
ACaJIIUlA'OIO
...
'=..1:......11.
~
fC
DITI _ _ _
.
.::.I_..'.TA"", ".,•
'=..1:::-
pc •• IMADI~
• -
=-
'"
.... , ..
0ItuA1IOM
Nc.u...L.,
;2i '
i 3'
•
'O....-1.'
_'. __
aIMeIIIIA. .
fC"
.=u:.•
I_~"C.
_
INSTRUCTION DIAGNOSTIC TABLE
o
o
o
o
rrrrrr _nil.
_. .
_c:_ c:,a.11
...
"011011_""""
I I . ' _ I I..nl
,~
_
•
I
Va•
..
II
.. I "......
PC
OIII'O""OM 1II000na
U
I
PC
ADDOIII . . . . fAOM
MlltOIty. . . . .CT-H ...
~,I='-
::....1=-=",I=:~
..,
....
:o.,g:,-:'~:::'.
PC-'
PC
a' a'" • ::.::~.= ......
~
""'-J
I Ie 1'1'1_1 :..:.~-'
"~
Q
~I 1.1-
II ::::'MlMOAt
.,. .
IT'
i a•
II
i
1==-,1:"_
=:.1:".1
:::-uPOll"
PC',
PC
1:::"',1='IITlfn
pc., 1::".1 g::'-
I · I--'IIIIAD tON.......
_
.. _ _ , .....
,.all
r~
=.~I::...,I
,.all
.Ioa "
t--
fIIOD- II"
PC
H: ••
1-1-._.na.
--,-
~
....n.
d
_IIIORY COOl
~
--.----.---1---1
;o-;;1;;
..•
_ •• 1__
....4
.ONiAiiON-J-·-t...," pc.,
el-""lIOII
I-~--f------l--l
-lo;;
DA'__
" -t-,1------1
IITlfll
,_
""'_
--.c.I' .......
MAO 0;0...- 1-'-'MI;O;;I;;U;-l~'
, COOl
AIIO........MOIIy OAtA
_.n.
=:.1:::"'.1
:::-0
111·1)
_110., OAIA
=. ,1:'_
PC
I:::",I=~
iiMD t~.--.
-;C;;--
_MOttl" COOl
itt
_.,",oulI ..en
J-t-I-I-I-t---
PC
iC;,
........
_ _ , C:ODI
MAD
_ _ , DU ..
IMAO
1....uca..Nt I
. . . . . _ , 0 .....
f----;--;~
FIGURE 31B:
-I
--t'
-..---,}-... !:--",,-...
_
1--1----
IItUI
... _ , CODI
__"1.,,
MaA. MIlA. .Ie, ,",IC.
..
••T . . . .
MO"'."
ka ........n
-f
..._,CODl
PC
l'
=:-u-
..•
~---f
f----t
,. a II
Pc. ......- iiNiiATiiiilI---.-t--t--t------t---
IIL ............C.MIC.
=~I::::",I
... ,. ...e:.
iTTiii
:=... I~=I~=
1:... ' _.......,...
1...
1__--+-:--1
__......
•• __,0",,,
:::-u_.na
-~-""~
__ __
..._,0",,,
.... I · fpc·· 1-~-""~
I~...N'
...-,.......
ej-""lIOII
MAOo;.-;;;;;;--t--.-1-;;c.a-t
_....
t
...... ""U......C.M.C
... tIO~' ....
OA'"
~
l1lilI0II'1 COOl
..........a ...1l
: :... 1 _.. '".......
_....
_',1I
-~-""'-
M .. MaA. MAC. MAC
................n
,
--'1-1--
"'lI
....".
_.nl
I
,
_11_,0..,..
"'4
I-'oa·.,
_ '_""lION
"'-'If:':...
. . . - , 0""",I0Il
CODI
--,;c.t1_
I
antHIU
-.. .... ...
.IICUf1IMI
MACHINe CYCU.
:0-::.'.)::',1 :::-u-
:",1:'I0Il
"'-'C:ODI
II
OA'"
r_
........
:::'",1 =:'-
. al" I·al =:;..-::~.
!I aI •I 1..'· .....' ..._·
=. . _. . ,. . . ,
MACHINI CYClI.
~_aOl''''IIUC~_
o
----
-.c:l'IM.OiI.
JIII.o-'-Jo;.liAr.o;;-r-1;;;o;;·I---P~
CON
•
. . . .•• _MOA, ••1A
''''',n
11·1)
:O-:-:.I::-'::",I:::-U"ul
INSTRUCTION DIAGNOSTIC TABLE
I' .._.
ADIHII"
p."
;;;n+cWW;;--J-.
=.:o.'fJ~..,,,
""
Ii· . -:i~. ., .
.~g
:
::
..
:
:
:
:
;
:
:
:
..
!
/.;
!i
.a
~
ilil
i
1!1I
Ii
i-
:
:
I
iL
In
!
I!~I
:~I
il.
1-:
!
•
III
~u
III.
j
~
:I
I
!llr
:1 •
I!
,
Ii
n
u
i
;
;
:
:
:
I ..
~0
a~1
h
IF
I
I &
I
i
II
I
Ii::
I
d£
... ..
II
•
IS I:_
1
I
I
1= = .
!
'~'
K
.
..
K
:
.. .. .. ..
I
I
j
.
:
-
:
II
II.!h.
i
I
d I=iII
, I,
.
!
I
-
I
I
Ilil
-
r
I
I
I
I:
I'
55
Ii
I
Iii
Ii
I·
i
it
IIi
II
, /. , Ii'
· .. . I- .. ... /- · . . I-
...
Z
c::J
«
"
I-
I-
l-
Z
u
~
0::
I
,
-
V')
0
0
1
i,i
~i
iii II
I.
u
l-
I
i :-
I
iii
c.c
«
I-
Q
t it
:13
Ii.f
1,1
,d 'I
I
It
Iii
L&J
..J
1,1
!I
..
I-!
I·
It
I=i
iii
d
Ii
i:-
It Ii
I
iill
i
Ii i-
/1.
,ii
,
.
I.
... .i. ·
Ie
I
1
·
/-
I=i
,II
I
I.
K
... ...
:
I. In
:Ie
t
Ii
a iii
Ii ~ Iii "Ii i,j
\11
••
i
liii Iii IiI
. I-
:
iI
I I
1
:
I
/
I Ii~ij
I
~
'\
·
I
:
I
I
I
-:
!
:
I
!
I.
Ii Id II Ii
Ii Ii
§
:
5
1
I
ii
I:
Sa
o
5i
!.
..
!
I
:
'i . Iii iii
!d
Iii ill II
i=
U
:
il •
!
~
:
I;
.. i
•
:
j-
Ii
...
:
It15i
I
I
:
: -r :
I
.. -
:'
I·
V')
0
Z
..
U
("t"\
L&J
0::
~
c::J
L&..
I
=
I ell !! II~i~r Ii o;! ,
.. i il II; Iii II IJilln
II =15 I I;llii II II Illb il 11111 II hlll II 5.. II lilil~t
.. SII I
:~i
~iroi ~i ii/,j II ,j ~j "i
!= ~I II II dIi iii II Ii ld Ii 'Ii ai ,i Ii I,j gi u!i
un
!
I:
~ Ii'
!i
!i
Ii ~ !i
I
=
I
I I !! I e I
I I =11 e
I.
I
I
I
I ' 1 .1 ..
II!
II
! I !I I
I II .1
I
il ! I I I =i!
~I
IU
II
II II
!-
2
K
I~
K 2
I
2
K
I-
:2
i ':
K
2
2
n.,o.LIe tL
48
K
K
2
2
2
2
2
'2
o
o
1~~~!~'!_54-_:-+_:~:~:~5~:+-_:-+_:r:~:~51~!_5~:~'~+-_:-+_:~1~~-:-+-:__r-~~
li.u.
• ·"0"
:
::: :::
:
::':1::;:::2
!
:
Ie .
• ~~~~~~+-~~~Ii~~+-~~~~~-+-;~~+-~
i
II
I
LIJ
-..I
CQ
I
I
a=
..
•
..
<:
. .
..
l-
.
lV)
0
iii
!i
%
t!7
I
ii
II d
<:
II
Ii
Q
%
0
l-
. . .
!
Ii·
...
•
M!
d
~
u
I
i
i
•~
~:I
d
· · .
~I·
i i
: ...
II!
II!
II!
II!
!
I
I
I
II!
I~
II!
I·
1:1
il
II! I Bs
soo
a ala
II!
II!
II!
t
1111
I~
'--- .
II!
UWM
011
II!
II!
~
I
·
Iii .
Ii
Ii
Iii
II
II
.
.
Iii
ii
Ii
u Ii
I I
I IIII eI i I eI II eI eI e
~I
Ilh
11=
I~
.~:
=!
~
II;
- .. · .· . . . -. .
• f.
I-lie
II II II Iii iii :ltlllr
5 i 5 I Ili,lIi Iii Iii IlIlillr
;I I
Iii Ii Ii II II II II Ii II dd II Iii
Ii
Ii
II!
II!
II!
II!
II!
II!
II!
II!
II!
II!
II!
i
:
I
s
I
I
II II ;..-• t I
2
I
: !- :
.. . ..
I
It
10
rII aiI.·i'
.. ...
.. ·. ·. - - 1«)0'1
I
#WItt
snMGCIY
t
I
n
as
I
GWO'I/IOIftI
I ;;
...
~
Ii".s
III.
..
...
!•
I
t
lIW.U1O UWNI
ONn04..O:;'
49
as
t..)
~
1
i
,
II!
~
II
. l
·
.
i~
, •
.
I f (~ i i I, P. I I
;; !
! •! .1 •
,
.• il• •
I! I!
I
lIW.U1O
II!
E'
h. I
ii~
.., .. ... !rl..... -
2i
II!
f
I
I
I!
II:EIi
II!
.
lei
Ii ...
a...
II II II
IIi I.i
,
I i I~L~
. . . . . . . I- · · .
!E •
= I I I e I I I I I ell eI I I
II iii Iii II II II II :lrlllr
I =I I II II III
5"
! i
i
; I. Ii lsi II II II II II Ii Ii II Ii
_
•
!'III Inlli! II Iii IiIi
Ii Ii
I'
f
Ii
iii n
II
•
•
I
"4
lidddil
o
-
t..)
• II
I
II
;g
•••s
...
;;
~
a::
lV)
%
Q.
rt'\
LIJ
c::::
~
t!7
-
L.t..
o
.u •..
.
I!
al
.:;
.~g
..
;
i:$
~
::
5 ::
~
,:
..
:z
:!
:!
:
:
:
:
!!
::
:
..
!
Ie
~
I
.i
:I
i~f
I
I.
I
II:1'
~
,
.•~
u
u
i
..
I
I
!
I
Ii
illi
I I
..
I
,I
i
Iii! I
d I
I;
.-,
~
I I
Ii
I·
.. .. .. ..
.. i
I
Iii
'Ii
!
..
.....
Ii!
Ii!
,
..
.. .. .. ..
..
I
Ii
i
il !Ii
Ii
. i 'Ii
Ii
..• ! Id-.
u
I II;
»-
U
I I
EI
ii
~
I
V)
0
%
c.:3
c:(
Q
Z
0
-u
I-
ex:
I
!I
Iii ii
V)
Z
a=1•
..
Ii
LU
,
.. .. .. .. .
('W"\
.
~
Ell.
II·g! I
.1 II
aaa
I
~ !i
LU
ex:
:::l
-
~
I EI E I-
.. i I'; Iii II Ilillll III i i i Ili,11i II
I Ii Ii Ii II id Ii II' d Ii Ii !d II
II
0
:::l
l-
il
, , i', ,
. .. . .
IF:0 ..
-.....
Ii!
,,,,
!
u
;
Itil=
c !!~
iill
..
I
-oJ
cz::l
c:(
il
liil
II II d it III I
II"
rI
~
L&J
I
I
'Iii
I
Ii
II
I
I
~
I
I
I
!
~
~
LL.
~
i
If II I
I
h
Iii iias .i ;1 IiUI I I I.i
=
~ .. - .-. .. ... . . ... II
I
lI::IOW
~
II
:
:;
-
-
I
I
!II
t
I
S
..
-
I
'~
~...,.
JNMmII
50
o
o
Pro Log M824 System Analyzer
The M824 is a logic signal analyzer designed specifically for program debugging
and hardware troubleshooting in Z80-based systems such as the 7803 Processor.
Figure 32 below summarizes the ability of the M824 to capture, format, and display
the information available from all the time states within a z80 machine cycle at
any instruction step in the program. The M824 operates in dynamic, single-step, and
breakpoint modes; tracks interrupts and DMA operations; can pick instructions out
of nested loops for display; and can trigger other tes·t equipment w'ith
program instruction synchronization.
The M824 is portable and clips onto the Z80 on the 7803, eliminating the need for
test probes and a long setup procedure.
(M2)
MACHINE CYCLE ONE (M1)
ADA
STATUS
IIdM
EUCUTE
AOR
(M3)
STATUS
...M AOR
STATUS
(M4)
_M
AOR
(M5)
ADA
MeM
STATUS
STATUS
MeM
EXECUTE
,
,,I
I
I
I
I
-- --...: --- ....
...
...
--- --- ---
,~--------------------------------~-~-~
MACHINe CYCU ONE (M1) •
T1
T5
IlACHIN£
CYCU:
FI GURE 32:
M824 ANALYZER
~.c.
o
M824
~------_\_---V----------------D-----~
SYSTEM ANALYZER
Z80 MICROPROCESSOR
\
MI ,
r - - $TATUS----.,
o
MfMOIIY
WlllTE
8
MEMOli,.
IIf&O
0,0-11'1 OIOIlt!&O
•
o
o
AOOIIES$
INnllllU~T
'v
III" a_ ~
.:-" .. ~ I .~'O'"
CLOCK
O"""T
OSU5&CK
r
PAGE - , ,LINE,
............·
··....·· :·· .......
.
··· ·
~OA.TA"""
O· o·
O' O'
0 0
0' 0'
2
2
rOATA-,
• o
: ...:
:.....
: ..
RUN
RESET
If
o
o
o
0410'&
S'NC
OUT
~
51
_"."P''''AS
;; ''',#4M$#47
¥Q;
qt.
:;. .»"....,(
APPENDIX A
7803 USER STRAPPING OPTIONS
o
In new 7803 applications, system characteristics such as memory mapping are
often arbitrary. The as-shipped configuration of the 7803 is reconmended to
minimize system assembly co~ts as well as field service and repair documentation
efforts. Most ot.her Pr.o-Log.- Series 7000 cards can b.e used with the 7e03 w-ithout
any jumper changes.
Jumper-wire strapping options are provided on the 7803 to allow processor upgrading
in existing appl ications, firtmNare~ and compatibi I ity with simi lar cards from
other manufacturers.
The strapping options for the 7803 are iden-tified by the letters A through F
on the Schematic (Pro Log document #103218), Assembly Diagram (#~03219) and by
silkscreened letters ~n the 7803 circuit card. The options include:
a. Clock (jumpers A and F): output clock to STD BUS, or input
external clock signal in place of the 7803's crystal.
b. Mapping and Bank Control (jumpers B-E): remap or disable the
onboard RAM and EPROM memory sockets, and allow external
control of I/O and memory bank selection (IOEXP* and MEMEX*
lines) .
Clock (Figure 331
Output: Some devices and instruments require access to the system clock. Jumper A
(Figure
) places the system clock on STO BUS pin 43. Note that the clock output
driver is not floated during DNA operations.
0
Input: an external clock can be used, to drive the 7803's clock oscillator.
Th i s shou ld be a TTL-compat i b I e s i g-na 1 in the range' of 1 to 5 MHz wi th a 25% to
75% duty cycle. The 7803's cloc~ circuit will divide this signal's frequency in
half, producing time states in the range 2000 ns to 400 ns.
The external clock input signal is assigned STO BUS pin 50 (CNTRL*). Remove the
following components from the 7803: Crystal Y1; 2.2K resistors R3 and R4; 1000 pF
capacitor C5. Rep.~ace C5 with a wire jumper. Add wire jumper F.
Figure
shows the clock circuit before and after the:lexternal clock input
modification.
Mapping
(Figure 34)
The 7803's onboard memory sockets can occupy the lower quadrant of memory (00003FFF hexadecimal, as shipped) or the upper quadrant (COOO-FFFF), or be disabled.
Figure
them.
summarizes these selections and shows the jumpers required to obtain
Bank Selection (Figure 33)
Jumpers D and E hold MEMEX* and 10EXP*, respectively, active by connecting the
bus traces to ground on the 7803 card. At least one additional 64K memory bank
and one 256-1/0 port bank could be enabled on the same motherboard by employing
memory and I/O cards which regard MEMEX* and ILEXP* as high level active signals.
52
4:)
o
RS
Schematic
coordinates
B6,7,8
PCO~
R'I
PCI®--J
22~
J.: CRt
I tN5S8
~tt9,~------~
Internal .clock with clock output on
s.ro
¢
BUS
Ute.
aae
o
R6
PCO~
PCI S
CLOCKt@
3!~
R'?
22.Ao
6
CRt
IN5S8
A
0
¢
~
External clock drive wi th clock output removed from
FI GURE
~3
sro
BUS
:
Jumper options for external
clock drive and clock output
•
Note: Some 7803 versions
prior to May 1980 use
El,E2,E3 ... jumper notation
instead of A,B,C •.•.
Jumper pad locations
l),~ JUt'" P eil..S 6.fIJ C,Altp ~J/t.INe. SIJ:)E:.,
53
-.-- .....- ..- -.-_____ .. ___ .. __ .•. _ ..•. _ ... _. ___
. ..,._"--'_ •.-'--._
w"'~_._~_.~,~,~.,.-
",~-,_
.~.:.
....• _._ .•..• _.... __
._~_~,.,
•...,.. ........
~
_~
__... _........ ___
~
___ .-.. _. __ ......
JUMPER WIRES
MEMORY ADDRESS ASStGNMENT
EPROM
RAM
UNUSABLE ,
6
C
0OOO-lFFF 2000-2FFF
JUMPER
3000-3FFF I OPEN
I
o
I
~OOO-OFFF
EOOO-EFFF
DISABLED
DISABLED
FOOO-FFFF
NONE
JUMPER
OPEN
OPEN
OPEN
+ 7...S3Z
AI5'
&
" ...' 5 UI3
C ....otJ
~
'AIs'~6 Ys
AI+~
5
Schematic coordinates 64,5
74LSD4
Jumper shown in C (asshipped) position .
.sv
R25
",.7K.
o
Co
FIGURE
3~
ONBOARD MEMORY MAPPING OPTIONS
o
54
o
APPENDIX
B:
o
o
55
DOCUMENTATION
o
Q
ii
~
~
.. .
; i
0
•
~
'
..
Q
cc
.
..
cc
j
~
e
"-
<3
l
~
i
;;
0
::I
i
..
lC
~
~
~:~:
~
i!
...
~
i=
J!
~--------~------~--~~----~~--~~----~--~
56
;
o
•
o
•
7
6
5
o
..
J
2
D
D
c
c
(Jl
.......
P!g:~f.i=4-F.
,I
8
,I.",...
18
CR'
,..' ••••• a•
• 10.. '"
. , 1"6
IIfTWOIIII IN,t.,·"'"
....::
1--
,\
u
.-,
Ij~:l:
-tiiA
Iw.-ii
.~
lit
5'
Ie'
,:',': ft'
U!!I DlSCI"IIOI I 4;;~~1IiJiii=l A
A
8CH(_1C NO 103el.
""RTa I.I6T NO lO3eeo
Li.·'NllIlllIl'EI '". MC1 10f SOCOIEU (lYP}
t fOR ""1 PRQCEOUIlU 6(10' "'100'.
"OTl&: UHl Ur. OT HE RW"! V£ClfI!O.
1Il':t~
•
7
6
5
..
J
2
PRO-lOG i CORPORATION
___ _
~_==-
o
o
o
•
•
•
o
o
USER'S MANUAL
2411 Garden Road
Monterey, California 93940
Telephone: (408) 372-4593
TWX: 910-360-7082
o
106777 8 400 11/81
1