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Freescale Semiconductor
Technical Data
Document Number: MPC603E7TEC
Rev. 5, 09/2011
PowerPC 603e RISC Microprocessor Family:
PID7t-603e Hardware Specifications
The PowerPC™ 603e microprocessor is an implementation of the PowerPC family of reduced instruction set computing
(RISC) microprocessors. In this document, the term ‘603e’ is used as an abbreviation for the PowerPC 603e microprocessor. The PowerPC 603e microprocessors are available from Freescale as MPC603e.
The 603e is implemented in several semiconductor fabrication processes. Different processes may require different supply voltages and may have other electrical differences but will have the same functionality. As a technical designator to distinguish between 603e implementations in various processes, a prefix composed of the processor version register (PVR) value and a process identifier (PID) is assigned to the various implementations as shown in
.
This document describes the pertinent physical characteristics of the PID7t-603e from Freescale. For functional characteristics of the 603e, refer to the PowerPC
603e RISC Microprocessor User’s Manual.
To locate any published errata or updates for this document, refer to the website at www.freescale.com.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. Electrical and Thermal Characteristics . . . . . . . . . . . . 4
5. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6. Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7. Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 17
8. System Design Information . . . . . . . . . . . . . . . . . . . . 20
9. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 29
10. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
© Freescale Semiconductor, Inc., 2011. All rights reserved.
2
Overview
Table 1. PowerPC 603e Microprocessors from Freescale
Technical
Designator
Process
PID6-603e 0.5 µm CMOS, 4LM
PID7v-603e 0.35 µm CMOS, 5LM
PID7t-603e 0.29 µm CMOS, 5LM
Core Voltage
(V)
I/O Voltage
(V)
5-Volt
Tolerant
3.3
2.5
2.5
3.3
3.3
3.3
Yes
Yes
Yes
Part Number
MPC603E
XPC603P (end-of-life)
MPC603R
1 Overview
The 603e is a low-power implementation of the PowerPC microprocessor family of RISC microprocessors. The 603e implements the 32-bit portion of the PowerPC architecture specification that provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.
The 603e provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep) are static in nature, and progressively reduce the amount of power dissipated by the processor. The fourth is a dynamic power management mode that causes the functional units in the 603e to automatically enter a low-power mode when the functional units are idle without affecting operational performance, software execution, or any external hardware.
The 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock.
Instructions can execute out of order for increased performance; however, the 603e makes completion appear sequential.
The 603e integrates five execution units—an integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for 603e-based systems. Most integer instructions execute in one clock cycle.
The FPU is pipelined, so a single-precision multiply-add instruction can be issued every clock cycle.
The 603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (MMUs). The
MMUs contain 64-entry, two-way, set-associative data and instruction translation lookaside buffers
(DTLB and ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block translation. The TLBs and caches use a least-recently used (LRU) replacement algorithm. The 603e also supports block address translation through the use of two independent instruction and data block address translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.
The 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603e interface protocol allows multiple masters to compete for system resources through a central external arbiter. The 603e provides a three-state coherency protocol that supports the exclusive, modified, and invalid cache states.
This protocol is a compatible subset of the MESI (modified/exclusive/shared/invalid) four-state protocol
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
Features
and operates coherently in systems that contain four-state caches. The 603e supports single-beat and burst data transfers for memory accesses, and supports memory-mapped I/O.
The 603e uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface compatibility with TTL devices. The PID7t-603e is offered in both PBGA and CBGA packages. The
CBGA package supports speed bins of 200, 266, and 300 MHz. The PBGA package is a pin-compatible drop in replacement for the CBGA; however, this package only supports speeds up to 200 MHz.
2 Features
This section summarizes features of the 603e’s implementation of the PowerPC architecture. Major features of the 603e are as follows:
• High-performance, superscalar microprocessor
— As many as three instructions issued and retired per clock
— As many as five instructions in execution per clock
— Single-cycle execution for most instructions
— Pipelined FPU for all single-precision and most double-precision operations
• Five independent execution units and two register files
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision operations
— LSU for data transfer between data cache and GPRs and FPRs
— SRU that executes condition register (CR), special-purpose register (SPR) instructions, and integer add/compare instructions
— 32 GPRs for integer operands
— 32 FPRs for single- or double-precision operands
• High instruction and data throughput
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
— A six-entry instruction queue that provides lookahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 16-Kbyte data cache—four-way, set-associative physically addressed; LRU replacement algorithm
— 16-Kbyte instruction cache—four-way, set-associative physically addressed; LRU replacement algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
— BPU that performs CR lookahead operations
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte segment size
Freescale Semiconductor
PID7t-603e Hardware Specifications, Rev. 5
3
4
General Parameters
— A 64-entry two-way, set-associative ITLB
— A 64-entry two-way, set-associative DTLB
— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
— Software table search operations and updates supported through fast trap mechanism
— 52-bit virtual and 32-bit physical address
• Facilities for enhanced system performance
— A 32- or 64-bit split-transaction external data bus with burst transfers
— Support for one-level address pipelining and out-of-order bus transactions
• Integrated power management
— Low-power 2.5/3.3-volt design
— Internal processor/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, and 6:1 ratios
— Three power-saving modes: doze, nap, and sleep
— Automatic dynamic power reduction when internal functional units are idle
• In-system testability and debugging features through JTAG boundary-scan capability
3 General Parameters
The following list provides a summary of the general parameters of the PID7t-603e:
Technology
Die size
0.29
µ m CMOS, five-layer metal
5.65 mm x 7.7 mm (44 mm
2
)
Transistor count
Logic design
Package
2.6 million
Fully-static
255 ceramic ball grid array (CBGA) or 225 thin map plastic ball grid array (PBGA)
Core power supply
I/O power supply
2.5 ± 5% V dc
3.3 ± 5% V dc
4 Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
PID7t-603e.
4.1
DC Electrical Characteristics
The tables in this section describe the PID7t-603e DC electrical characteristics. This table provides the absolute maximum ratings.
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 2. Absolute Maximum Ratings
Characteristic Symbol Value Unit
Core supply voltage
PLL supply voltage
I/O supply voltage
Input voltage
V dd
AV dd
OV dd
V in
–0.3 to 2.75
–0.3 to 2.75
–0.3 to 3.6
–0.3 to 5.5
V
V
V
V
Storage temperature range T stg
–55 to 150 °C
Note:
1. Functional and tested operating conditions are given in Table 3
. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. Caution: V in
must not exceed OV dd
by more than 2.5 V at any time, including during power-on reset.
3. Caution: OV dd
must not exceed V dd
/AV dd
by more than 1.2 V at any time, including during power-on reset.
4. Caution: V dd
/AV dd
must not exceed OV dd
by more than 0.4 V at any time, including during power-on reset.
This table provides the recommended operating conditions for the PID7t-603e.
Table 3. Recommended Operating Conditions
Characteristic Symbol Value Unit
Core supply voltage
PLL supply voltage
I/O supply voltage
Input voltage
V dd
AV dd
OV dd
V in
Tj
2.375 to 2.625
2.375 to 2.625
3.135 to 3.465
GND to 5.5
V
V
V
V
Die-junction temperature 0 to 105 °C
Note: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
This table provides the package thermal characteristics for the PID7t-603e.
Table 4. Package Thermal Characteristics
Characteristic Symbol
Value
CBGA
Package die junction-to-case thermal resistance (typical)
Package die junction-to-ball thermal resistance (typical)
JC
JB
0.095
Note: For more about thermal management, see Section 8, “System Design Information
.”
3.5
Value
PBGA
8.0
13
Rating
°C/W
°C/W
Freescale Semiconductor
PID7t-603e Hardware Specifications, Rev. 5
5
Electrical and Thermal Characteristics
This table provides the DC electrical characteristics for the PID7t-603e.
Table 5. DC Electrical Specifications
V dd
= AV dd
= 2.5 ± 5% V dc, OV dd
= 3.3 ± 5% V dc, GND = 0 V dc, 0
Tj
105 °C
Characteristic Symbol Min Max Unit Note
Input high voltage (all inputs except SYSCLK)
Input low voltage (all inputs except SYSCLK)
SYSCLK input high voltage
SYSCLK input low voltage
V
IH
V
IL
CV
IH
CV
IL
2.0
GND
2.4
GND
5.5
0.8
5.5
0.4
V
V
V
V
—
—
—
—
Input leakage current, V in
= 3.465 V
V in
= 5.5 V
I in
I in
—
—
30
300
µA
µA
1, 2
1, 2
Hi-Z (off-state) leakage current, V in
= 3.465 V
V in
= 5.5 V
Output high voltage, I
OH
= –7 mA
I
I
TSI
TSI
—
—
30
300
µA
µA
1, 2
1, 2
Output low voltage, I
OL
= 7 mA
Capacitance, V in
= 0 V, f = 1 MHz (excludes TS, ABB, DBB, and ARTRY)
Capacitance, V in
= 0 V, f = 1 MHz (for TS, ABB, DBB, and ARTRY)
V
OH
V
C
OL
C in in
2.4
—
—
—
—
0.4
10.0
15.0
V
V pF pF
—
—
3
3
Notes:
1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals).
2. The leakage is measured for nominal OV dd
and V dd
or both OV dd
and V dd
must vary in the same direction (for example, both
OV dd
and V dd
vary by either +5% or -5%).
3. Capacitance is periodically sampled rather than 100% tested.
This table provides the power consumption for the PID7t-603e.
Table 6. Power Consumption
Processor (CPU) Frequency
100 MHz 133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
Full-On Mode (DPM Enabled)
Typical 1.1
Maximum
Doze Mode
1.6
0.55
Typical
Nap Mode
Typical
Sleep Mode
50
Typical
Sleep Mode—PLL Disabled
45
1.6
2.4
0.7
60
50
2.1
3.2
0.9
75
55
2.5
4.0
1.1
85
65
3.0
4.6
1.3
100
75
3.5
5.3
1.5
120
90
4.0
6.0
1.8
130
100
Unit
W
W
W mW mW
6
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 6. Power Consumption (continued)
Processor (CPU) Frequency
Unit
100 MHz 133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
Typical 40
Sleep Mode—PLL and SYSCLK Disabled
40
Typical
Maximum
15
25
15
25
40
15
25
40
15
25
40
15
25
40
15
80
40
15
100 mW mW mW
Note:
1. These values apply for all valid PLL_CFG[0–3] settings and do not include output driver power (OV dd
) or analog supply power (AV dd
). OV dd
power is system dependent but is typically
10% of V dd
. Worst-case AV dd
= 15 mW.
2. Typical power is an average value measured at V dd
= AV dd
= 2.5 V, OV dd
= 3.3V, in a system executing typical applications and benchmark sequences.
3. Maximum power is measured at 2.625 V using a worst-case instruction mix.
4.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the PID7t-603e. These specifications are for 200,
266, and 300 MHz processor speed grades. The processor core frequency is determined by the bus
(SYSCLK) frequency and the settings of the PLL_CFG[0–3] signals. All timings are specified respective to the rising edge of SYSCLK. PLL_CFG signals should be set prior to power up and not altered afterwards.
4.2.1
Clock AC Specifications
This table provides the clock AC timing specifications as defined in
. After fabrication, parts are sorted by maximum processor core frequency as shown in
Section 4.2.1, “Clock AC Specifications
,” and tested for conformance to the AC specifications for that frequency. Parts are sold by maximum processor
core frequency; see Section 9, “Ordering Information
.”
Table 7. Clock AC Timing Specifications
V dd
= AV dd
= 2.5 ± 5% V dc, OV dd
= 3.3 ± 5% V dc, GND = 0 V dc
,
0
Tj
105 °C
200 MHz
CBGA
266 MHz
CBGA
300 MHz
CBGA
200 MHz
PBGA
Num Characteristic
Min Max
Processor frequency
VCO frequency
1
SYSCLK frequency
SYSCLK cycle time
2, 3 SYSCLK rise and fall time
4 SYSCLK duty cycle measured at 1.4 V
100
300
25
13.3
200
400
66.67
40
— 2.0
40.0
60.0
Min
80
300
25
13.3
—
40.0
Max
200
400
66.67
40
2.0
60.0
Min
150
300
25
13.3
—
40.0
Max
266
532
75
40
2.0
60.0
Min
180
360
33.3
13.3
—
40.0
Max
300
600
75
30
2.0
60.0
Unit
MHz
MHz
MHz ns ns
%
Note
1, 6
1
1
2
3
Freescale Semiconductor
PID7t-603e Hardware Specifications, Rev. 5
7
Electrical and Thermal Characteristics
Table 7. Clock AC Timing Specifications (continued)
V dd
= AV dd
= 2.5 ± 5% V dc, OV dd
= 3.3 ± 5% V dc, GND = 0 V dc
,
0
Tj
105 °C
200 MHz
PBGA
200 MHz
CBGA
266 MHz
CBGA
300 MHz
CBGA
Num Characteristic Unit Note
Min Max Min Max Min Max Min Max
SYSCLK jitter
PID7t internal PLL-relock time
—
—
±150
100
—
—
±150
100
—
—
±150
100
—
—
±150
100 ps
s
4
3, 5
Note:
1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description in
Section 8, “System Design Information ,” for valid
PLL_CFG[0–3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design. The total input jitter (short term and long term combined) must be under
±150 ps to guarantee the input/output timing of
Section 4.2.2, “Input AC Specifications ,” and
.”
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum time required for PLL lock after a stable V dd
, OV dd
, AV dd
, and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time (100
s) during the power-on reset sequence.
additional information.
This figure provides the SYSCLK input timing diagram.
SYSCLK
VM
4
1
4
CVih
VM VM
CVil
VM = Midpoint Voltage (1.4 V)
Figure 1. SYSCLK Input Timing Diagram
2 3
4.2.2
Input AC Specifications
This table provides the input AC timing specifications for the PID7t-603e as defined in
and
.
8
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 8. Input AC Timing Specifications
1
V dd
= AV dd
= 2.5 ± 5% V dc, OV dd
= 3.3 ± 5% V dc, GND = 0 V dc
,
0
Tj
105° C
200, 266, 300 MHz
Num Characteristic Unit Notes
Min Max
10a
10b
10c
Address/data/transfer attribute inputs valid to SYSCLK (input setup)
All other inputs valid to SYSCLK (input setup)
Mode select inputs valid to HRESET (input setup)
(for DRTRY, QACK and TLBISYNC)
2.5
3.5
8
—
—
— t ns ns sysclk
2
3
4, 5, 6, 7
11a
11b
SYSCLK to address/data/transfer attribute inputs invalid (input hold)
SYSCLK to all other inputs invalid (input hold)
1.0
1.0
—
— ns ns
2
3
11c HRESET to mode select inputs invalid (input hold)
(for DRTRY, QACK, and TLBISYNC)
0 — ns 4, 6, 7
Note:
1. Input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of the rising edge of the input SYSCLK. Input and output timings are measured at the pin.
2. Address/data/transfer attribute input signals are composed of the following—A[0–31], AP[0–3], TT[0–4], TC[0–1], TBST,
TSIZ[0–2], GBL, DH[0–31], DL[0–31], DP[0–7].
3. All other input signals are composed of the following—TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA,
DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3
).
5. t sysclk
is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
This figure provides the input timing diagram for the PID7t-603e.
VM
SYSCLK
10a
10b
ALL INPUTS
11a
11b
VM = Midpoint Voltage (1.4 V)
Figure 2. Input Timing Diagram
Freescale Semiconductor
PID7t-603e Hardware Specifications, Rev. 5
9
Electrical and Thermal Characteristics
This figure provides the mode select input timing diagram for the PID7t-603e.
VM
HRESET
10c
11c
MODE PINS
VM = Midpoint Voltage (1.4 V)
Figure 3. Mode Select Input Timing Diagram
18
19
20
21
14b
15
16
17
12
13a
13b
14a
4.2.3
Output AC Specifications
This table provides the output AC timing specifications for the PID7t-603e as defined in
.
Table 9. Output AC Timing Specifications
1
V dd
= AV dd
= 2.5
5% V dc, OV dd
= 3.3 ± 5%, GND = 0 V dc, 0
Tj
105 °C, CL = 50 pF (unless otherwise noted)
200, 266, 300 MHz
Num Characteristic Unit
Min Max
Note
SYSCLK to output driven (output enable time)
SYSCLK to output valid (5.5 V to 0.8 V—TS, ABB, ARTRY, DBB)
SYSCLK to output valid (TS, ABB, ARTRY, DBB)
SYSCLK to output valid (5.5 V to 0.8 V—all except TS, ABB,
ARTRY, DBB)
1.0
—
—
—
SYSCLK to output valid (all except TS, ABB, ARTRY, DBB)
SYSCLK to output invalid (output hold)
SYSCLK to output high impedance (all except ARTRY, ABB, DBB)
SYSCLK to ABB, DBB, high impedance after precharge
SYSCLK to ARTRY high impedance before precharge
SYSCLK to ARTRY precharge enable
Maximum delay to ARTRY precharge
SYSCLK to ARTRY high impedance after precharge
—
1.0
—
—
—
0.2 * t sysclk
+ 1.0
—
—
7.5
—
1.0
2.0
9.0
—
8.0
1.0
—
9.0
8.0
11.0
ns ns ns t sysclk ns ns t sysclk t sysclk ns ns ns ns
5
3
—
3
5
2
—
4, 6
—
2, 4, 7
4, 7
5, 7
10
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 9. Output AC Timing Specifications
1
(continued)
V dd
= AV dd
= 2.5
5% V dc, OV dd
= 3.3 ± 5%, GND = 0 V dc, 0
Tj
105 °C, CL = 50 pF (unless otherwise noted)
200, 266, 300 MHz
Num Characteristic Unit Note
Min Max
Note:
1. All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V or 2.0 V) of the
signal in question. Both input and output timings are measured at the pin (see Figure 4 ).
2. This minimum parameter assumes CL = 0 pF.
3. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external voltage from 5.5 V to 0.8 V instead of from V dd
to 0.8 V (5-V CMOS levels instead of 3.3-V CMOS levels).
4. t sysclk
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
5. Output signal transitions from GND to 2.0 V or V dd
to 0.8 V.
6. Nominal precharge width for ABB and DBB is 0.5 t sysclk
.
7. Nominal precharge width for ARTRY is 1.0 t sysclk
.
This figure provides the output timing diagram for the PID7t-603e.
VM VM
SYSCLK
VM
14
15
16
ALL OUTPUTS
(Except TS, ABB,
DBB, ARTRY)
12
13
13 15
16
TS
17
ABB, DBB
21
18
20
19
ARTRY
VM = Midpoint Voltage (1.4 V)
Figure 4. Output Timing Diagram
4.3
JTAG AC Timing Specifications
This table provides the JTAG AC timing specifications as defined in
Freescale Semiconductor
PID7t-603e Hardware Specifications, Rev. 5
11
Electrical and Thermal Characteristics
Table 10. JTAG AC Timing Specifications
V dd
= AV dd
= 2.5 ± 5% V dc, OV dd
= 3.3 ± 5%, GND = 0 V dc, 0
Tj
105° C, C
L
= 50 pF
Num Characteristic Min Max Unit
1
2
3
4
5
6
7
8
9
10
11
12
13
TCK frequency of operation
TCK cycle time
TCK clock pulse width measured at 1.4 V
TCK rise and fall times
TRST setup time to TCK rising edge
TRST assert time
Boundary scan input data setup time
Boundary scan input data hold time
TCK to output data valid
TCK to output high impedance
TMS, TDI data setup time
TMS, TDI data hold time
TCK to TDO data valid
TCK to TDO high impedance
0
62.5
25
0
13
40
6
27
4
3
0
25
4
3
16
—
—
3
—
—
—
—
25
24
—
—
24
15
Note:
1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Non-test signal input timing with respect to TCK.
3. Non-test signal output timing with respect to TCK.
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
This figure provides the JTAG clock input timing diagram.
1
2
2
TCK
VM
VM
3
3
VM
Note
—
—
3
3
—
—
2
2
1
—
—
—
—
—
VM = Midpoint Voltage (1.4 V)
Figure 5. JTAG Clock Input Timing Diagram
12
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
Electrical and Thermal Characteristics
This figure provides the TRST timing diagram.
TCK
VM
4
TRST
5
Figure 6. TRST Timing Diagram
This figure provides the boundary-scan timing diagram.
TCK
VM
VM
Data Inputs
6 7
Input Data Valid
8
Data Outputs
Output Data Valid
9
Data Outputs
8
Data Outputs
Output Data Valid
Figure 7. Boundary-Scan Timing Diagram
This figure provides the test access port timing diagram.
TCK
VM
TDI, TMS
VM
10 11
Input Data Valid
12
TDO
Output Data Valid
13
TDO
TDO
Freescale Semiconductor
12
Output Data Valid
Figure 8. Test Access Port Timing Diagram
PID7t-603e Hardware Specifications, Rev. 5
13
Pin Assignments
5 Pin Assignments
Part A of Figure 9 shows the pinout of the CBGA package as viewed from the top surface. Part B shows
the side profile of the CBGA package to indicate the direction of the top surface view. The PBGA package has an identical pinout. Part C shows the side profile of the PBGA package to indicate the direction of the top surface view.
Part A
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16
A
H
J
K
F
G
L
M
N
P
R
T
B
C
D
E
Not to Scale
Part B
View
Substrate Assembly
Encapsulant
Die
14
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
Pinout Listings
Part C
Substrate Assembly
Mold Compound
View
Die
Figure 9. Pinout of the CBGA and PBGA Packages as Viewed from the Top Surface
AACK
ABB
AP[0–3]
APE
ARTRY
AV
DD
BG
BR
CI
CKSTP_IN
CKSTP_OUT
CLK_OUT
CSE[0–1]
DBB
DBG
DBDIS
DBWO
DH[0–31]
6 Pinout Listings
This table provides the pinout listing for the 603e CBGA and PBGA packages.
Table 11. Pinout Listing for the 255-Pin CBGA and PBGA Packages
Signal Name
A[0–31]
DL[0–31]
Pin Number
L01
B06
E01
D08
A06
D07
B01, B05
J14
C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, GO2, E15, H01, E16, H02,
F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15, P01
L02
K04
C01, B04, B03, B02
A04
J04
A10
N01
H15
G04
P14, T16, R15, T15, R13, R12, P11, N11, R11,T12, T11, R10, P09, N09, T10, R09, T09,
P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, T04
K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15,
R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04, T03, R04
Active I/O
High I/O
High I/O
High
Low
Low
Low
Low
Low
Low
—
Low
High
Low
—
Low
Low
Low
Low
High
Low
O
I/O
I
I
O
O
O
I
I
I/O
I/O
—
I
O
I
I/O
I/O
O
Freescale Semiconductor
PID7t-603e Hardware Specifications, Rev. 5
15
Pinout Listings
Table 11. Pinout Listing for the 255-Pin CBGA and PBGA Packages (continued)
Signal Name Pin Number
TBEN
TBST
TC[0–1]
TCK
TDI
TDO
TEA
TLBISYNC
TMS
TRST
DP[0–7]
DPE
DRTRY
GBL
GND
M02, L03, N02, L04, R01, P02, M04, R02
A05
G16
F01
C05, C12, E03, E06, E08, E09, E11, E14, F05, F07, F10, F12, G06, G08, G09, G11,
H05, H07, H10, H12, J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10, L12, M03,
M06, M08, M09, M11, M14, P05, P12
HRESET
INT
L1_TSTCLK
1
L2_TSTCLK
1
LSSD_MODE
1
A07
B15
D11
D12
MCP
B10
C13
NC (No-Connect) B07, B08, C03, C06, C08, D05, D06, H04, J16
OV
DD
C07, E05, E07, E10, E12, G03, G05, G12, G14, K03, K05, K12, K14, M05, M07, M10,
M12, P07, P10
PLL_CFG[0–3]
QACK
QREQ
RSRV
SMI
SRESET
SYSCLK
TA
A08, B09, A09, D09
D03
J03
D01
A16
B14
C09
H14
A11
A12
H13
C04
C02
A14
A02, A03
C11
B11
C10
Active I/O
High
Low
Low
Low
—
I/O
O
I
I/O
—
Low
Low
—
—
Low
Low
—
—
High
Low
High
—
High
High
Low
Low
High
Low
Low
Low
—
Low
High
Low
Low
Low
—
—
I
I
I
I
I
I
I
I
I
O
I
I/O
O
I
I
I
I
I
I
I
O
O
I
I
16
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
Package Descriptions
Table 11. Pinout Listing for the 255-Pin CBGA and PBGA Packages (continued)
Signal Name Pin Number Active I/O
TS
TSIZ[0–2]
J13
A13, D10, B12
Low
High
I/O
O
TT[0–4]
WT
V
DD
2
B13, A15, B16, C14, C15
D02
F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08, J09, J11, K07, K10, L06,
L08, L09, L11
F03
High
Low
—
I/O
O
—
VOLTDETGND
3
Low O
Note:
1. These are test signals for factory use only and must be pulled up to OV dd
for normal machine operation.
2. OV dd
inputs supply power to the I/O drivers and V dd
inputs supply power to the processor core.
3. NC (no-connect) in the PID6-603e; internally tied to GND in the PID7v-603e and PID7t-603e CBGA and PBGA package to indicate to the power supply that a low-voltage processor is present.
7 Package Descriptions
The following sections provide the CBGA and PBGA package parameters and the mechanical dimensions for the 603e.
7.1
CBGA Package Description
The following sections provide the package parameters and mechanical dimensions for the CBGA package.
7.1.1
Package Parameters
The package parameters are as provided in the following list. The package type is 21 mm x 21 mm,
255-lead ceramic ball grid array (CBGA).
Package outline
Interconnects
21 mm x 21 mm
255
Pitch
Package height
Ball diameter
Maximum heat sink force
1.27 mm (50 mil)
Minimum: 2.45 mm
Maximum: 3.00 mm
0.89 mm (35 mil)
10 lbs
Freescale Semiconductor
PID7t-603e Hardware Specifications, Rev. 5
17
Package Descriptions
7.1.2
Mechanical Dimensions of the CBGA Package
This figure provides the mechanical dimensions and bottom surface nomenclature of the CBGA package.
A1 CORNER
A
2X
0.200
– E –
– T –
0.150 T
B
P
2X
0.200
– F –
K
N
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
C
H
H
K
D
G
N
P
A
B
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
MILLIMETERS INCHES
DIM
MIN MAX MIN MAX
21.000 BSC
21.000 BSC
2.450
3.000
0.820
0.930
1.270 BSC
0.790
0.990
0.635 BSC
5.000
5.000
0.827 BSC
0.827 BSC
0.097
0.118
0.032
0.036
0.050 BSC
0.031
0.039
0.025 BSC
16.000
0.197
0.630
16.000
0.197
0.630
G
K
255X
D
0.300
0.150
S
S
T
T
E
S
F
S
Figure 10. Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package
7.2
PBGA Package Description
The following sections provide the package parameters and mechanical dimensions.
7.2.1
Package Parameters
The package type is 23 mm x 23 mm, 255-lead plastic ball grid array (PBGA).
Package outline 23 mm x 23 mm
18
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
Package Descriptions
Interconnects
Pitch
Package height
Ball diameter
Maximum heat sink force
255
1.27 mm (50 mil)
Minimum: 2.1 mm; Maximum: 2.6 mm
0.76 mm (30 mil)
5 lbs
7.2.2
Mechanical Dimensions of the PBGA Package
This figure shows the non-JEDEC package mechanical dimensions and bottom surface nomenclature.
256X
0.20 C
0.35 C
A
D
D2
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2.
DIMENSIONS IN MILLIMETERS.
3.
DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO PRIMARY
DATUM C.
4.
PRIMARY DATUM C AND THE SEATING PLANE ARE
4X
0.20
E E2
(D1)
15X e
D1
D2
E
E1
A2
A3 b
D
MILLIMETERS
DIM MIN MAX
A
A1
2.10
0.50
1.10
0.50
0.60
19.40
2.60
0.70
1.20
0.70
0.90
23.00 BSC
19.05 REF
19.60
23.00 BSC
19.05 REF
E2
19.40
19.60
e
1.27 BSC
A1
A
C
SEATING
PLANE
SIDE VIEW
A2
A3
B
TOP VIEW
15X e
(E1)
4X e /2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
BOTTOM VIEW
256X b
0.30
0.15
M
M
C A B
C
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Figure 11. Package Dimensions for the Plastic Ball Grid Array (PBGA)—non-JEDEC Standard
Note that
lists the pinout to this non-JEDEC standard in order to be consistent with the CBGA pinout. This figure shows the JEDEC package dimensions of the PBGA package.
Freescale Semiconductor
PID7t-603e Hardware Specifications, Rev. 5
19
System Design Information
256X
0.20 C
0.35 C
E
A
E2
D
D2
A1
A
C
SEATING
PLANE
SIDE VIEW
A2
A3
4X
0.20
TOP VIEW
B
15X e
(E1)
4X e /2
(D1)
15X e
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
BOTTOM VIEW
256X b
0.30
0.15
M
M
C A B
C
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2.
DIMENSIONS IN MILLIMETERS.
3.
DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO PRIMARY
DATUM C.
4.
PRIMARY DATUM C AND THE SEATING PLANE ARE
MILLIMETERS
D
D1
D2
E
DIM MIN
A
A1
A2
A3 b
2.10
0.50
MAX
2.60
0.70
1.20
1.10
0.50
0.60
0.70
0.90
23.00 BSC
19.05 REF
19.40
19.60
E1
23.00 BSC
E2
19.40
19.60
e
19.05 REF
1.27 BSC
CASE 1167-01
Figure 12. Package Dimensions for the Plastic Ball Grid Array (PBGA)—JEDEC Standard
Note that the pin numberings shown in Figure 12 do not match
; the pinout of the non-JEDEC
standard package (and the CBGA pinout) is shown in Figure 11 . Note that Figure 11 should be used in
conjunction with
for the complete pinout description.
8 System Design Information
This section provides electrical and thermal design recommendations for successful application of 603e.
20
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
System Design Information
8.1
PLL Configuration
The 603e PLL is configured by the PLL_CFG[0–3] signals. For a given SYSCLK (bus) frequency, the
PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the PID7t-603e is shown in this table for nominal frequencies.
Table 12. PLL Configuration
CPU Frequency in MHz (VCO Frequency in MHz)
PLL_CFG[0:3]
Bus-to-Core
Multiplier
Core-to-VCO
Multiplier
Bus
25 MHz
Bus
33.33 MHz
Bus
40 MHz
Bus
50 MHz
Bus
60 MHz
Bus
66.67 MHz
Bus
75 MHz
0100
0101
0110
1000
1110
1010
0111
1011
1001
2x
2x
2.5x
3x
3.5x
4x
4.5x
5x
5.5x
2x
4x
2x
2x
2x
2x
2x
2x
2x
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
150
(300)
166
(333)
183 (366)
—
80
(320)
—
—
—
4
160
(320)
180
(360)
200
(400)
220
(440)
240
(480)
—
100
(400)
—
150
(300)
175
(350)
200
(400)
225
(450)
250
(500)
275
(550)
300
(600)
—
120
(480)
150
(300)
180
(360)
210
(420)
240
(480)
270
(540)
300
(600)
—
—
133
(532)
166
(333)
200
(400)
233 (466)
267 (533)
300 (600)
—
—
150
(300)
150
(600)
187
(375)
225
(450)
263
(525)
300
(600)
—
—
—
1101 6x 2x 150
(300)
200
(400)
— — —
0011
1111
PLL bypass
Clock off
Note:
1. Some PLL configurations may select bus, CPU, or VCO frequencies which are not supported; see
AC Specifications ,” for valid SYSCLK and VCO frequencies.
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
3. In clock-off mode, no clocking occurs inside the 603e regardless of the SYSCLK input.
4. 80 MHz operation is not supported for the PBGA package (see
8.2
PLL Power Supply Filtering
The AV dd
power signal is provided on the 603e to provide power to the clock generation phase-locked loop. To ensure stability of the internal clock, the power supplied to the AV dd
input signal should be filtered
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor 21
System Design Information
the AV dd the AV dd
pin to ensure it filters out as much noise as possible. The 0.1 µF capacitor should be closest to
pin, followed by the 10 µF capacitor, and finally the 10
resistor to V dd
. These traces should be kept short and direct.
10
V dd
AV dd
10 µF 0
.
1 µF
GND
Figure 13. PLL Power Supply Filter Circuit
8.3
Decoupling Recommendations
Due to the 603e’s dynamic power management feature, large address, data buses, and high-operating frequencies, it can generate transient power surges and high-frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the 603e system. It requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer places at least one decoupling capacitor at each V dd
and OV dd
pin of the 603e. It is also recommended that these decoupling capacitors receive their power from separate
V dd
, OV dd
, and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should vary in value from 220 pF to 10
F to provide both high- and low-frequency filtering, and should be placed as close as possible to their associated V dd
or OV dd
pin. Suggested values for the V dd
pins are: 220 pF (ceramic), 0.01 µF (ceramic), and 0.1 µF (ceramic). Suggested values for the
OV dd
pins are: 0.01 µF (ceramic), 0.1 µF (ceramic), and 10 µF (tantalum). Only SMT capacitors should be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the V dd
and OV dd
planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should also have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100 µF (AVX TPS tantalum) or 330 µF (AVX TPS tantalum).
8.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to V dd
. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external V dd
, OV dd
, and GND pins of the 603e.
22
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
System Design Information
8.5
Pull-up Resistor Requirements
The 603e requires high-resistive (weak: 10 K
) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the 603e or other bus master. These signals are: TS, ABB, DBB, and ARTRY.
In addition, the 603e has three open-drain style outputs that require pull-up resistors (weak or stronger:
4.7 K
–10 K) if they are used by the system. These signals are: APE, DPE, and CKSTP_OUT.
During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may float in the high-impedance state for relatively long periods of time. Since the 603e must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the 603e. It is recommended that these signals be pulled up through weak (10 K
) pull-up resistors or restored in some manner by the system. The snooped address and transfer attribute inputs are—A[0–31], AP[0–3], TT[0–4], TBST, and GBL.
The data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus.
8.6
Thermal Management Information
This section provides thermal management information for the CBGA and PBGA packages for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level design—the heat sink, airflow and thermal interface material.
This figure shows the upper and lower limits of the die junction-to-ambient thermal resistance for both package styles. The lower limit is shown for the case of a densely populated PCB with high thermal loading of adjacent and neighboring components.
Freescale Semiconductor
PID7t-603e Hardware Specifications, Rev. 5
23
System Design Information
.
40
35
30
25
20
15
10
Ty pical Upp er Li mit
Ty pical Low er Li mit
5
0
0 0.5
1
Airf low Velocit y (m / s)
1.5
Figure 14. Typical Die Junction-to-Ambient Thermal Resistance
(21 mm CBGA and 23 mm WB-PBGA)
2
To reduce the die-junction temperature, heat sinks may be attached to the package by several methods—adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (both CBGA and PGBA packages); see
.
CAUTION
While choosing a heat sink attachment method, any attachment mechanism should not degrade the package structural integrity and/or the package-to-board interconnect reliability. For additional general information, see this paper—Investigation of Heat Sink Attach Methodologies and the Effects on Package
Structural Integrity and Interconnect Reliability.
24
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
Heat Sink
Heat Sink
Clip
Adhesive or
Thermal Interface Material
CBGA Package
Printed-Circuit Board Option
Heat Sink
Heat Sink
Clip
Adhesive or
Thermal Interface Material
PBGA Package
System Design Information
Printed-Circuit Board Option
Figure 15. Package Exploded Cross-Sectional View with Heat Sink
The board designer can choose between several types of commercially available heat sinks to place on the
603e. Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
Freescale Semiconductor
PID7t-603e Hardware Specifications, Rev. 5
25
System Design Information
8.6.1
Internal Package Conduction Resistance
external thermal resistance paths are shown in this figure for a package with an attached heat sink mounted to a PCB.
External Resistance Radiation Convection
Heat Sink
Internal Resistance
Printed-Circuit Board
Thermal Interface Material
Die/Package
Die Junction
Package/Leads
Radiation Convection
External Resistance
(Note the internal versus external package resistance)
Figure 16. Package with Heat Sink Mounted to a Printed-Circuit Board
8.6.2
Thermal Interface Materials
A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip
mechanism, as shown in Figure 17 . The thermal performance of three thin-sheet thermal-interface
materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. Therefore, the synthetic grease offers the best thermal performance, considering the low-interface pressure. Of course, the selection of any thermal interface material depends on many factors—thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc.
26
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
2
1.5
System Design Information
Silicone Sheet (0.006 inch)
Bare Joint
Floroether Oil Sheet (0.007 inch)
Graphite/Oil Sheet (0.005 inch)
Synthetic Grease
1
0.5
0
0 10 20 30 40 50
Contact Pressure (psi)
60 70
Figure 17. Thermal Performance of Select Thermal Interface Material
80
The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements.
8.6.3
Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
T j
= T a
+ T r
+ (
jc
+
int
+
sa
) * P d
Eqn. 1
where:
T j is the die-junction temperature
T a
is the inlet cabinet ambient temperature
T r
is the air temperature rise within the computer cabinet
jc
is the die junction-to-case thermal resistance
int is the adhesive or interface material thermal resistance
sa
is the heat sink base-to-ambient thermal resistance
P d is the power dissipated by the device
Freescale Semiconductor
PID7t-603e Hardware Specifications, Rev. 5
27
System Design Information
During operation the die-junction temperatures (T j
) should be maintained less than the value specified in
. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T a
) may range from 30 to 40 °C. The air temperature rise within a cabinet (T r
) may be in the range of 5 to 10 °C. The thermal resistance of the thermal interface material (
1 °C/W. Assuming a T a
of 30 °C, a T r of 5 °C a CBGA package
jc
=
0.095
int
) is typically about
, and a power consumption (P d
) of 3.0 Watts, the following expression for T j
is obtained:
Die-junction temperature: T j
= 30 °C + 5 °C + (0.095 °C/W + 1.0 °C/W + R sa
) * 3.0 W. For example, the heat sink-to-ambient thermal resistance (R sa
) versus airflow velocity is shown in this figure.
8
7
Example: Pin-fin Heat Sink
(25 x 28 x 15 mm)
6
5
4
3
2
1
0 0.5
1 1.5
2 2.5
Approach Air Velocity (m/s)
3 3.5
Figure 18. Example of Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity
Assuming an air velocity of 0.5 m/s, we have an effective R sa
of 7 °C/W, thus
T j
= 30°C + 5°C + (0.095 °C/W +1.0 °C/W + 7 °C/W) * 3.0 W, Eqn. 2
resulting in a die-junction temperature of approximately 60 °C which is well within the maximum operating temperature of the component.
For a PBGA package, and assuming a T a
of 30 °C, a T r of 5 °C a PBGA package
jc
= 8, and a power consumption (P d
) of 3.0 Watts, the following expression for die-junction temperature, T j
, is obtained as:
T j
= 30 °C + 5 °C + (8 °C/W + 1.0 °C/W + R sa
) * 3.0 W
Assuming an air velocity of 0.5 m/s, we have an effective R sa
of 7 °C/W, thus
Eqn. 3
28
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
Ordering Information
T j
= 30°C + 5°C + (8 °C/W +1.0 °C/W + 7 °C/W) * 3.0 W, Eqn. 4
resulting in a die-junction temperature of approximately 83 °C that is well within the maximum operating temperature of the component. Commercially available heat sinks have different heat sink-to-ambient thermal resistances, and may or may not need air flow.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component’s power consumption, a number of factors affect the final operating die-junction temperature—airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today’s microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. To expedite system-level thermal analysis, several
“compact” thermal-package models are available within FLOTHERM®. These are available upon request.
9 Ordering Information
This figure provides the part numbering nomenclature for the PID7t-603e. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local
Freescale sales office.
In addition to the processor frequency, the part numbering scheme also consists of a part modifier and application modifier. The part modifier indicates any enhancement(s) in the part from the original design.
The application modifier may specify special bus frequencies or application conditions. Each part number also contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only.
MPC 603 R RX XXX X X
Product Code
Part Identifier
Part Modifier
(R = Remapped, Enhanced, Low-Voltage)
Package
(RX = CBGA without Lid)
(ZT = PBGA Package)
(VG = Polymer Core CBGA without Lid)
Figure 19. Part Number Key
Revision Level
(Contact Freescale Sales Office)
Application Modifier
(L = Any Valid PLL Configuration)
(T = Extended Termperature Range)
Processor Frequency
Freescale Semiconductor
PID7t-603e Hardware Specifications, Rev. 5
29
Revision History
10 Revision History
This table summarizes revision history for this document.
Table 13. Document Revision History
Rev. Number
5
Date
9/2011
Substantive Change(s)
• Updated to new Freescale template.
• Added package info, VG = Polymer Core CBGA without Lid on
• Deleted thermal heat sink and thermal interface vendor details from 8.6/-23
.
30
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
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Document Number: MPC603E7TEC
Rev. 5
09/2011
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