Global Event­identifier Module
USER MANUAL
Inter­University Accelerator Centre Aruna Asaf Ali Marg New Delhi­67
Inter­University Accelerator Centre Aruna Asaf Ali Marg New Delhi­67
Global Event­identifier Module
Features:
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12 bit HitPattern.
Remotely programmable width/delay of all Inputs and outputs.
Remote selection of “Event Of Interest”(EOI) and VETO. Four Prompt outputs. Time Stamp with 10 nS resolution. ~32 nS EOI detection time.
Facilitates Unified, Distributed and Multi­strobe Data Acquisition Systems. “EOI” selection from 48 signals in distributed configuration. General Description:
GEM is a completely programmable 12 channel single width CAMAC module. It is designed to identify a user defined event of interest with the experimental timing window ranges from 50 nS to 128uS. It records a hit pattern at every “Accepted Event Of Interest” (AEOI) and associates a 48 bit time tag of 10 nS resolution and 32 days range to it. It facilitates multi crate and multi strobe system. Block diagram is depicted in Fig.1.
It provides a remote configuration for “Event of Interest” selection (1 of 4), Veto selection (1 of 5), Inputs and output pulse width, Veto width and delays , DAS trigger delay and ADC GATE width through CAMAC commands. (see CAMAC commands for detailed description) Front­end comprises of 12 discriminators which accepts NIM inputs which is actually trigger request from individual detector or group of detectors. A level shifter converts the NIM input to LVDS. All the logic is implemented in a FPGA. At the acceptance of “Event of Interest”, a LVDS Global Trigger signal is generated in the FPGA, which in turn is converted from LVDS to NIM using LVDS­ECL­NIM converters and fanned­out as four “Prompt out” (GT1­GT4) signals which goes as “LatchIN” to other crates (maximum four). Back­end comprises of 5 numbers of RJ45 connector and two Lemo connectors. Lemo connectors are labeled as “CEin” and “CEout”. One of the five RJ45 connectors, provides the “Event Fragment LocalOut” (EFLout) and 100MHz “clockIN” signal and rest works as “Event Fragment GlobalIn”(EFGin) inputs for gathering the local trigger requests from other crates to generate a global trigger request based on users pre­defined conditions and transmitting the 100 MHz clock to all other crates. Global clock enable signal can be distributed in daisy chain fashion through Back panel LEMO “CEin” And “CEout” connectors (ref fig­3).
Four GEM can be connected in “Master/Slave” configuration through UTP cables (CAT5) to facilitate a distributed Data Acquisition System and provides ease of selection of an Event Of Interest from upto 48 signals. “Master” contains an onboard 100MHz crystal Oscillator Module and “Slave” reconstructs the distributed clock signal. Fig­1: front panel
Inter­University Accelerator Centre Aruna Asaf Ali Marg New Delhi­67
Input characteristics: Front Panel:
IN1­IN12
LatchIN TGin : 12 Standard NIM input, Lemo­type connectors. Input impedance 50 ohm. : Standard NIM input, Lemo­type connector. Input impedance 50 ohm. : Standard NIM input, Lemo­type connector. Input impedance 50 ohm. Back Panel:
EFGin1­EFGin4
CE IN : Standard LVDS25 signal, RJ45 connectors (Event Fragment GlobalIN)
: Standard NIM input, Lemo­type connector. Input impedance 50 ohm. Output characteristics:
Front Panel:
DAS GATE
EOI
GT1­GT4 Busy N LED : TTL out (LPCC OUT).
: TTL out (ADC GATE).
: Standard NIM signal, Lemo­type connector.
: 4 Standard NIM signals, Lemo­type connector.
: Open Collector TTL out.(Ored in Distributed DAS).
: flashes whenever a command is accepted.
Back Panel:
EFLout
CE out
: Standard LVDS25 signal, RJ45 connector (Event Fragment Local Out).
: Standard NIM signal, Lemo­type connector.
General Characteristics:
Event Identification Delay : 32 nS + cable delay.
Power supply requirement (Minimum)
+6V @ 1.6A,
­6V @ 1A
Packaging :
Standard single width CAMAC module.
Quality Control:
Standard 72 hours burn­in test.
Inter­University Accelerator Centre Aruna Asaf Ali Marg New Delhi­67
CAMAC commands:
CAMAC status and response:
Z(Initialize)
X and Q
: Clears All the registers, except Time Reference Counter. : X and Q response is generated for each valid CAMAC command.
CAMAC function code:
Read
A(0).F(0)
A(1).F(0) A(2).F(0)
A(3).F(0)
A(4).F(0)
A(5).F(0) : Read Lower 16 bits of 48bit “time stamp” counter.
: Read Middle 16 bits of 48bit “time stamp” counter.
: Read Higher 16 bits of 48bit “time stamp” counter.
: Read 12 bit Hit pattern.
: Read Accepted Event count.
: Read Total Event count.
Write
A(0).F(16)
A(1).F(16)
A(2).F(16)
A(3).F(16)
A(4).F(16)
A(5).F(16)
A(6).F(16)
A(7).F(16)
A(8).F(16) A(0).F(17) : Set the block size for event (1­65535).
: Sets the user defined time window (ranges from 50 nS to 128 uS in steps of 10ns)
: Sets selected “event of interest” width (ranges from 50 nS to 128 us in steps of 10 nS)
: Sets DAS strobe Delay (ranges from 1us to 128 us in steps of 10 nS) : Sets VETO width (ranges from 1us to 128 us in steps of 10 nS)
: Sets VETO delay (ranges from 1us to 128 us in steps of 10 nS)
: Sets GATE width { TTL ADC Strobe) (ranges from 1us to 128 us in steps of 10 nS).
: Select “event of interest” from the four outputs by writing in to EOI selection register.
: Selects Veto from the four output by writing in to VETO selection register.
: GEM enable/disable
Initialise
A(0).F(9) A(0).F(10) A(0).F(24)
A(0).F(26) A(1).F(24)
A(1).F(26)
A(0).F(25) : Reset 48 bit Time reference counter.
: Clear LAM signal.
: Disables LAM (Mask the LAM to assert the L­line). : Enables LAM (allows the LAM to assert the L­line).
: Disable Global Clock Out (CEout) Feature.
: Enable Global Clock Out (CEout) Feature.
: Clear the Module’s Busy signal
Inter­University Accelerator Centre Aruna Asaf Ali Marg New Delhi­67
Block Diagram : Main Blocks of GEM are shown in given Block diagram. Details of all inputs, outputs are given in Section “Input characteristics” and “output characteristics” respectively. A brief of all block is described below. Fig :2 Conceptual Diagram of GEM
Pulse Identification and width control : This block is used to re­stretched the input pulse width.
Local Co­incidence Logic : This block helps in mapping the event fragments as singles, double or triples in individual GEM.
Time Stamp Logic : This is used to mark a 48 bit time stamp on each accepted “event of interest”.
Global Clock Synchronizer : This decides whether to use internal or external “clock enable” signal.
Global Co­incidence logic : This block marks the event fragments as singles, double, triples or quadruple which has been collected from all slaves. Programmable pulse stretcher and selector: Selects the “event of interest” and VETO and stretches the pulse width.
Programmable Veto Delay : This block helps in delaying the veto signal.
System approval : This block checks for the busy status of system. If the system is free, GEM accepts the “event of interest” and provides four fanned­out.
Accepted Event Count: A 16 bit counter keeps track of the “accepted event of interest”.
Total Event counter: A 16 bit counter keeps track of all incoming “event of interest”.
Inter­University Accelerator Centre Aruna Asaf Ali Marg New Delhi­67
Connection Diagram: Back panel connection: Tri Crate setup is shown below, L1 and L2 (Lemo cables) are used for daisy chaining of Global Clock Enable signal. UTP cable are standard Cat­5 cables and used for the distribution of 100MHz clock signal. Fig­3 GEM Back Panel Connections Diagram
NOTE : 1. For proper synchronization, length of UTP1,UTP2 and UTP3 must keep same.
2. Keep minimal length of L1 and L2 cables .
Inter­University Accelerator Centre Aruna Asaf Ali Marg New Delhi­67
Front panel connection: Tri Crate setup is shown below, All the cable used are standard 50 ohm lemo cable. GEM in Crate 1 is configured as “Master”.
Fig­3 GEM Front Panel Connection Diagram
NOTE : For proper synchronization length of cables marked as 1,2,3 must be equal and 4,5,6 should be of same length cable.
Inter­University Accelerator Centre Aruna Asaf Ali Marg New Delhi­67
Programming Details Of Global Event­identifier Module
Read the HitPattern
A(3).F(0)
: Read 12 bit Hit pattern. This should be first signal to be read in CAM file if the system is running in “Hit Pattern based read” mode. (Hardware Zero Suppression would be based on this read out)
Read the Accepted Trigger
A(4).F(0)
: Read Accepted Event count.
Read the Total Trigger
A(5).F(0) : Read Total Event count.. It will be the sum of Accepted event and the event which were rejected due to system busy.
Writing Data
A(1).F(16)
A(2).F(16)
A(3).F(16)
A(4).F(16)
A(5).F(16)
A(6).F(16)
A(7).F(16)*
A(8).F(16) A(0).F(17) : Write the user defined time window or time resolution ranges from 50 nS to 128 uS in steps of 10ns. Default pulse width is 30 ns.
: Write selected “event of interest” width ranges from 50 nS to 128 us in steps of 10 nS. Default pulse width is 30 ns.
: Writet DAS strobe Delay ranges from 1us to 128 us in steps of 10 nS which is processing time for all module ADC/TDC/QDC etc module. Default pulse width is 30 ns.
: Write VETO width ranges from 1us to 128 us in steps of 10 nS. Default pulse width is 30 ns.
: Write VETO delay ranges from 1us to 128 us in steps of 10 nS. Default pulse width is 30 ns.
: Write width for ADC Gate Strobe ranges from 1us to 128 us in steps of 10 nS. Default pulse width is 30 ns.
: Select “event of interest” from the four outputs by writing in to EOI selection register.
EOI
Quadruple
Triple
Double
Single
DATA
3
2
1
0
: Selects Veto from the four output by writing in to VETO selection register.
VETO
Quadruple
Triple
Double
Single
NoVETO
DATA
4
3
2
1
0
: GEM enable/disable
Status
Enable
Disable
DATA
1
0
LAM:
A(0).F(10) A(0).F(24)
A(0).F(26) : Clear LAM signal.
: Disables LAM (Mask the LAM to assert the L­line). : Enables LAM (allows the LAM to assert the L­line).
TimeStamp:
A(0).F(0)
A(1).F(0) : Read Lower 16 bits of 48bit “time stamp” counter.
: Read Middle 16 bits of 48bit “time stamp” counter.
Inter­University Accelerator Centre Aruna Asaf Ali Marg New Delhi­67
A(2).F(0)
A(0).F(9) A(1).F(24)
A(1).F(26)
: Read Higher 16 bits of 48bit “time stamp” counter.
: Reset 48 bit Time reference counter.
: Disable Global Clock Out (CEout) Feature.
: Enable Global Clock Out (CEout) Feature.
Busy:
A(0).F(25) : Clear the Module’s Busy signal
Debug Commands:
A(8).F(0) : Read Digital Clock Manager Status from R3­R0.
bits
Lock/Unlock
status
status
status
1/0
1/0
1/0
1/0
A(9).F(16)** : It provides the selected signal on the monitor output. It is debugging purpose.
Test
LAMclear
ClearBUSY
DASstrobe
ADCgate
IntBUSY
VETO
EOI
DATA
6
5
4
3
2
1
0
NOTE:
* As it has been programmed specifically for INGA requirements but can be changed to other user defined combination for “Event of Interest”
** As the INGA setup needs only 3 crates, the 4th Global Trigger Out (GT4) is used as “Test Out”.
Configuration Examples: Example 1# Suppose the user wants to collect data with the following constraints
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Single crate system
400ns timing window
Doubles mode with singles veto
GEM can be initialised and read with the series of following commands.
Init commands
C=0
C=0
C=0
C=0
C=0
C=0
C=0
C=0
C=0
C=0
C=0
N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 A=1 A=2 A=3 A=4 A=5 A=6 A=1 A=0 A=1 A=7 A=8 Read commands
C=0
N=22
A=3 F=16
F=16
F=16 F=16 F=16 F=16 F=24 F=9
F=26 F=16 F=16 DATA=37
DATA=37
DATA=3000 DATA=33 DATA=197 DATA=1600
DATA=0
DATA=0
DATA=0
DATA=1
DATA=1
(Actual value = ((DATA*10) + 30)ns = 400ns)
(Actual value = ((DATA*10) + 30)ns = 400ns)
(Actual value = ((DATA*10) + 30)ns = 30us)
(Actual value = ((DATA*10) + 30)ns = 360ns)
(Actual value = ((DATA*10) + 30)ns = 2us) (Actual value = ((DATA*10) + 30)ns = 16us)
(Disables Global Clock Out (CEout) Feature)
(Resets 48 bit Time reference counter)
(Enables Global Clock Out (CEout) Feature)
(sets the multiplicity in Doubles)¹
(sets Single as VETO)²
F=0 DATA=0
(Read HitPattern)³ Inter­University Accelerator Centre Aruna Asaf Ali Marg New Delhi­67
Example 2# Suppose the user wants to collect data with the following constraints
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A Tri crate system.
400ns timing window
Doubles mode with singles vetoed
GEM can be initialised and read with the series of following commands.
Init commands
C=0
C=0
C=0
C=0
C=0
C=0
C=1
C=1
C=1
C=2
C=2
C=2
C=0
C=1
C=2
C=0
C=1
C=2
C=0
C=1
C=2
C=1
C=2
C=0
C=0
N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 N=22 A=1 A=2 A=3 A=4 A=5 A=6 A=1 A=3 A=6 A=1 A=3 A=6 A=1 A=1 A=1 A=0 A=0 A=0 A=1 A=0 A=0 A=0 A=0 A=7 A=8 Read commands
C=0
C=1
C=2
N=22 A=3 N=22 A=3
N=22 A=3
F=16
F=16
F=16 F=16 F=16 F=16 F=16
F=16 F=16 F=16
F=16 F=16 F=24 F=24 F=24 F=9
F=9
F=9
F=26 F=24 F=24 F=10 F=10 F=16 F=16 DATA=37 DATA=37
DATA=3000 DATA=33 DATA=197 DATA=1600
DATA=37
DATA=3000 DATA=1600
DATA=37
DATA=3000 DATA=1600
DATA=0
DATA=0
DATA=0
DATA=0
DATA=0
DATA=0
DATA=0
DATA=0
DATA=0
DATA=0
DATA=0
DATA=1
DATA=1
(Actual value = ((DATA*10) + 30)ns)
(Actual value = ((DATA*10) + 30)ns)
(Actual value = ((DATA*10) + 30)ns)
(Actual value = ((DATA*10) + 30)ns)
(Actual value = ((DATA*10) + 30)ns)
(Actual value = ((DATA*10) + 30)ns)
(Actual value = ((DATA*10) + 30)ns)
(Actual value = ((DATA*10) + 30)ns)
(Actual value = ((DATA*10) + 30)ns)
(Actual value = ((DATA*10) + 30)ns)
(Actual value = ((DATA*10) + 30)ns)
(Actual value = ((DATA*10) + 30)ns)
(Disables Global Clock Out (CEout) Feature)
(Disables Global Clock Out (CEout) Feature)
(Disables Global Clock Out (CEout) Feature)
(Resets 48 bit Time reference counter)
(Resets 48 bit Time reference counter)
(Resets 48 bit Time reference counter)
(Enables Global Clock Out (CEout) Feature)
(Disbles LAM)
(Disbles LAM)
(Clear LAM signal)
(Clear LAM signal)
(sets the multiplicity in Doubles)¹
(sets Single as VETO)²
F=0 F=0 F=0 DATA=0
DATA=0
DATA=0
(Read HitPattern)³
(Read HitPattern)
(Read HitPattern)
NOTE : 1. C=0 N=22 A=7 F=16 DATA=2
(sets the multiplicity in Tripples)
2. C=0 N=22 A=8 F=16 DATA=2
(sets Double as VETO)
3. This should be first signal to be read in CAM file if the system is running in “Hit Pattern based read” mode. (Hardware Zero Suppression would be based on this read out)
Inter­University Accelerator Centre Aruna Asaf Ali Marg New Delhi­67
TIMING Diagram: Details of propagation delay from Local Trigger requests to Global Trigger out is given in following diagram.
➢
➢
d1 => UTP cable delay.
d2 => TG in LEMO cable delay.
Fig­5
Inter­University Accelerator Centre Aruna Asaf Ali Marg New Delhi­67
Inter­University Accelerator Centre Aruna Asaf Ali Marg New Delhi­67