Memec P160 Analog Module User Guide

Memec P160
Analog Module
User Guide
Version 1.2
July 2003
PN# DS-MANUAL-ANALOG1
Table of Contents
1
ABOUT THIS KIT ................................................................................................................... 1
2
THE P160 ANALOG MODULE .............................................................................................. 1
2.1
D/A CONVERTERS ............................................................................................................ 3
2.1.1
2.1.2
2.1.3
2.1.4
2.2
DAC Signal Flow ...................................................................................................... 5
Full Scale Adjust Jumpers JP1 and JP2 ............................................................... 7
DAC External Reference ......................................................................................... 7
DAC Clocking ........................................................................................................... 7
A/D CONVERTERS ............................................................................................................ 8
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
3
A/D Signal Flow........................................................................................................ 9
A/D Data Format..................................................................................................... 12
A/D Clocking........................................................................................................... 12
A/D Full Scale Select ............................................................................................. 12
A/D Internal Reference .......................................................................................... 13
A/D Over-Range Indicator ..................................................................................... 13
2.3
EXTERNAL CLOCK INPUTS ............................................................................................... 13
2.4
P160 CONNECTORS ....................................................................................................... 14
REVISIONS........................................................................................................................... 17
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Figures
FIGURE 1 – P160 ANALOG MODULE ................................................................................................... 2
FIGURE 2 – P160 ANALOG MODULE BLOCK DIAGRAM ......................................................................... 3
FIGURE 3 – DAC #1 DIFFERENCE AMPLIFIER CONFIGURATION ............................................................ 5
FIGURE 4 – DAC #1 FILTER AND GAIN OUTPUT STAGE ....................................................................... 6
FIGURE 5 – DAC LOW PASS FILTER GAIN .......................................................................................... 6
FIGURE 6 – DAC LOW PASS FILTER 3-DB FREQUENCY ....................................................................... 6
FIGURE 7 – ANALOG INPUT STAGE ..................................................................................................... 9
FIGURE 8 – ANALOG FILTER STAGE .................................................................................................. 10
FIGURE 9 – ADC LOW PASS FILTER GAIN ........................................................................................ 10
FIGURE 10 – ADC LOW PASS FILTER 3-DB FREQUENCY ................................................................... 11
FIGURE 11 – ADC DIFFERENTIAL AMPLIFER ..................................................................................... 12
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Tables
TABLE 1 – DAC #1 P160 INTERFACE................................................................................................. 4
TABLE 2 – DAC #2 P160 INTERFACE................................................................................................. 4
TABLE 3 – DAC INPUT DATA .............................................................................................................. 5
TABLE 4 – DAC GAIN ADJUST VALUES ............................................................................................... 6
TABLE 5 – DAC LOW PASS FILTER ADJUST VALUES ........................................................................... 7
TABLE 6 – DAC REF SELECT JUMPER (JP4) ..................................................................................... 7
TABLE 7 – ADC #1 P160 INTERFACE................................................................................................. 8
TABLE 8 – ADC #2 P160 INTERFACE ................................................................................................. 8
TABLE 9 – ADC GAIN ADJUST VALUES ............................................................................................. 10
TABLE 10 – ADC LOW PASS FILTER ADJUST VALUES ....................................................................... 11
TABLE 11 – ADC OUTPUT VALUES................................................................................................... 12
TABLE 12 – ADCX.FSSEL CONTROL ............................................................................................... 13
TABLE 13 – ADCX.REFSEL CONTROL ............................................................................................ 13
TABLE 14 – JP5 EXTERNAL CLOCK SETTINGS .................................................................................. 13
TABLE 15 – JP6 EXTERNAL CLOCK SETTINGS .................................................................................. 13
TABLE 16 – P160 CONNECTOR – JX1.............................................................................................. 15
TABLE 17 – P160 CONNECTOR – JX2.............................................................................................. 16
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1
About this Kit
The Memec Design P160 Analog Module provides an advanced analog interface to existing P160
compatible FPGA platforms. The module enables designers to easily implement dual channel
analog input and output functions, targeting communications, video and general-purpose mixedsignal applications. With two 12-bit analog-to-digital (A/D) converters capable of sample speeds
up to 53Msps and two digital-to-analog (D/A) converters capable of 165Msps conversions, the
module offers flexibility and ease of use to FPGA-based DSP applications and prototyping. The
P160 Analog Module is ideally suited as an add-on for the Memec Design MB1000 Virtex-II
Development Kit and the 2VP4/7 Virtex-II Pro Development Kit. The module will also work with
the Spartan-II 200PCI and Spartan-IIE 300 platforms from Memec Design.
The Memec Design P160 Analog Module kit includes the following:
-
-
2
MBEXP3 P160 Analog Module
o 2 12-bit 53-Msps A/D converters
o AC coupled, single-ended, 1 to 1.5 Vp-p analog input
o Low pass input filter with fc = 19.4 MHz
o 2 12-bit 165 Msps D/A converters
o Single-ended, 2 Vp-p analog output
o AC coupled output optional
o Low pass output filter with fc = 28.4 MHz
Documentation CD
The P160 Analog Module
The P160 Analog Module is comprised of four independent analog channels, two supporting
analog inputs and two supporting analog outputs. The analog input channels are identical in
design and include signal conditioning analog front ends. The Texas Instruments ADS807 12-bit,
53Msps A/D converters are used to convert incoming analog signals into 12-bit data for the FPGA
located on the baseboard. Analog outputs can be generated using the two DAC902 12-bit,
165Msps D/A converters from Texas Instruments. Gain and filtering is provided on the D/A
outputs.
Control of the A/Ds and D/As is handled by the FPGA through the P160 digital interface. Sample
clocks, data, reference voltage settings, and power down control are examples of some of the
control signals available. Two external clock inputs are provided on the P160 Analog Module,
allowing clock inputs to be routed down to the FPGA and then back up to the D/As or A/Ds.
The analog front-ends to both the D/A channels and A/D channels are designed to accommodate
a wide variety of applications. Customization of the front-end gain and frequency response
characteristics is possible through the change of certain resistor and capacitor values. If electing
to make such changes, care must be taken to ensure circuit stability. Read the device data
sheets thoroughly to understand the recommended design parameters.
Figure 1 shows the P160 Analog Module.
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1
Ext Clock
ADC #2
Input
ADC #1
Input
DAC #1
Output
DAC
Ref
DAC #2
Output
Ext Clock
DAC #2
ADC #2
Latch
Latch
P160
Connector
P160
Connector
DAC #1
ADC #1
Latch
Latch
Figure 1 – P160 Analog Module
All the analog inputs and outputs are available along the topside of the module through the SMB
type connectors. The P160 connections along the left and right sides of the board connect the
digital signals between the FPGA based board and the register and control pins on the Analog
Module. A high-level block diagram of the P160 Analog Module is shown in Figure 2, followed by
a brief description of each board function.
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2
f 3db =28.4MHz
REG
DAC
#1
Analog
Output
G =2
G =1
J3
EXT
REF
P160
REG
DAC
#2
f 3db =28.4MHz
Analog
Output
G =2
G =1
J9
f 3db =19.4MHz
G =1
G =2
ADC
#1
REG
G =2
ADC
#2
REG
J1
f 3db =19.4MHz
G =1
P160
J7
CLK IN1
CLK IN2
Figure 2 – P160 Analog Module Block Diagram
2.1
D/A Converters
Two digital-to-analog converters provide single-ended analog outputs from the P160 Analog
Module. The Texas Instruments DAC902 delivers 12-bit resolution at 165Msps with differential
outputs for improved dynamic performance. The FPGA interfaces to the D/As through 12-bit
registers, which add a clock cycle delay between data out from the FPGA and the D/A analog
outputs. Two independent data channels, one channel for each DAC, are driven from the FPGA
to the P160 connector and into the register.
Table 1 shows the P160 interface signals for DAC #1 and Table 2 shows the interface signals for
DAC #2.
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Table 1 – DAC #1 P160 Interface
Signal
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
CLK
CLK2
REFSELECT
PD
JX2 P160
Connector
A39
A38
A37
A36
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A40
A23
A25
A24
Description
DAC input data bit 11 (MSB)
DAC input data bit 10
DAC input data bit 9
DAC input data bit 8
DAC input data bit 7
DAC input data bit 6
DAC input data bit 5
DAC input data bit 4
DAC input data bit 3
DAC input data bit 2
DAC input data bit 1
DAC input data bit 0 (LSB)
(Unused)
(Unused)
DAC Clock (rising edge active)
Register Clock
Reference Select (Low = Internal, High = External)
Power Down (Low = Normal, High = Power Down)
Table 2 – DAC #2 P160 Interface
Signal
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
CLK
CLK2
REFSELECT
PD
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JX2 P160
Connector
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A21
A3
A5
A4
Description
DAC input data bit 11 (MSB)
DAC input data bit 10
DAC input data bit 9
DAC input data bit 8
DAC input data bit 7
DAC input data bit 6
DAC input data bit 5
DAC input data bit 4
DAC input data bit 3
DAC input data bit 2
DAC input data bit 1
DAC input data bit 0 (LSB)
(Unused)
(Unused)
DAC Clock (rising edge active)
Register Clock
Reference Select (Low = Internal, High = External)
Power Down (Low = Normal, High = Power Down)
4
2.1.1 DAC Signal Flow
The DAC input data is defined such that DB1 is the MSB data and DB12 is the LSB data. Two
additional data bits are included in the FPGA interface for possible expansion to 14-bit offerings in
the DAC900 family. Data values and corresponding output values are shown below.
Table 3 – DAC Input Data
DAC Output
Input Code
(J3/J9)
DB1 <-> DB12
1111 1111 1111
1000 0000 0000
0000 0000 0000
3.5V
2.5V
1.5V
The DAC output seen at J3 and J9 is normally DC coupled for a 2 V peak-to-peak (Vp-p) signal
centered at 2.5 V. Current to voltage conversion, gain, and filtering is provided at the output of
the DAC chip as shown in the following figures. The diagrams presented reflect the component
designators for the DAC#1 channel.
5V
C95
0Ω
R45
510 Ω
R46
1K Ω
5
IOUT
DAC
U4
C37
15 pf
6
IOUT
R36
25 Ω
R48
25 Ω
C94
0Ω
R38
510 Ω
U5
7
R52
1KΩ
R39
510 Ω
Figure 3 – DAC #1 Difference Amplifier Configuration
The DAC has two complementary current outputs with a nominal current range of 0 mA to 20 mA.
As shown, the DAC generates a differential output signal of .5 Vp-p at the load resistors, R36 and
R48. The difference amplifier stage level shifts the .5 Vp-p DAC outputs to a 2.5 V bias and
provides a unipolar, single-ended output with a 1 Vp-p swing.
The capacitor locations C94 and C95 can be populated with .1 uf devices for improved AC
performance. The default setting has C94 and C95 set with 0 ohm jumpers, providing enhanced
DC performance.
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5
C35
56 pf
R34
100Ω
R31
100Ω
* For AC coupling
C36 = .1 uf
3
2
U5
J3
1
R42
50 Ω
C38
56 pf
R124
430Ω
C36
0Ω
R41
430 Ω
R49
430 Ω
C42
.1 uf
Figure 4 – DAC #1 Filter and Gain Output Stage
The final output stage incorporates an active two-pole Sallen-Key low pass filter set for a 3-db
frequency of 28.4MHz. (Additional filter design theory can be found in the Sallen-Key application
note included on the CD). The gain of the circuit is set at G = 2, resulting in a 2 Vpp output signal
centered at 2.5 V. It is possible to modify this circuit to adjust the gain and the 3-db frequency as
shown below.
R49 + R41
G = ------------------- = 2
R49
Figure 5 – DAC Low Pass Filter Gain
Table 4 – DAC Gain Adjust Values
R41
430 Ω
403 Ω
510 Ω
DAC #1
R49
430 Ω
806 Ω
340 Ω
Gain
2
1.5
2.5
DAC #2
R106
430 Ω
806 Ω
340 Ω
R98
430 Ω
403 Ω
510 Ω
Gain
2
1.5
2.5
1
fc = ----------------------------- = 28.4 MHz
2π (R31R34C35C38)
½
Figure 6 – DAC Low Pass Filter 3-db Frequency
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Table 5 – DAC Low Pass Filter Adjust Values
DAC #1
R31
100 Ω
28.9 Ω
33.7 Ω
R34
100 Ω
120 Ω
150 Ω
R88
100 Ω
28.9 Ω
33.7 Ω
R91
100 Ω
120 Ω
150 Ω
C35
56 pf
100 pf
100 pf
fc
C38
56 pf
56 pf
56 pf
28.4 MHz
36 MHz
30 MHz
C74
56 pf
56 pf
56 pf
28.4 MHz
36 MHz
30 MHz
DAC #2
C71
56 pf
100 pf
100 pf
fc
By default, the analog outputs are DC coupled through 0 ohm jumpers in locations C36 on DAC
#1 channel and C72 on DAC #2 channel. Replacing these jumpers with .1 uf capacitors will
result in an AC coupled output.
2.1.2 Full Scale Adjust Jumpers JP1 and JP2
The Full Scale Adjust jumpers (JP1 and JP2) are normally closed when using the internal 1.24 V
bandgap reference. Connecting an external reference voltage to the D/A via the REF Input
connector and setting jumper JP4 to select one of the DACs, may require jumper JP1 or JP2 to
be removed. See the “Internal Reference Operation” section of the DAC902 Data Sheet for
further details on configuring the full scale adjust.
2.1.3 DAC External Reference
The DAC902 has an on-chip reference circuit that is normally enabled through low inputs on the
DAC1.REFSELECT and DAC2.REFSELECT. The internal reference can be disabled by driving
one of these inputs high and applying an external reference voltage at J5. Jumper JP4 must also
be set with a jumper to connect the external reference to the desired DAC REFIN pin. The table
below explains the jumper settings.
Table 6 – DAC REF Select Jumper (JP4)
JP4
Description
OPEN
1-2
2-3
Internal REF active
External REF connected to DAC #1
External REF connected to DAC #2
2.1.4 DAC Clocking
Each DAC channel requires 2 clock signals to latch digital data into the DAC.
DAC1.CLK/DAC2.CLK and DAC1.CLK2/DAC2.CLK2 come from the FPGA and are rising-edge
triggered. The *.CLK2 signals latch the digital DAC data from the FPGA into the P160 register.
The *.CLK signals latch the output data from the register into the DAC. On the falling edge of the
*.CLK signal, the DAC output changes to the newly latched value.
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2.2
A/D Converters
Two analog-to-digital converters are included on the P160 Analog Module. These Texas
Instruments ADS807 converters provide 12-bit resolution at up to 53 Msps. The digital data out
of the A/Ds is latched into external buffers and then passed to the FPGA through the P160
interface. The tables below show the P160 interface between the P160 registers and the FPGA.
Table 7 – ADC #1 P160 Interface
Signal
JX1 P160
Connector
Description
DB1
B28
ADC output data bit 0 (MSB)
DB2
DB3
DB4
DB5
DB6
DB7
B29
B30
B31
B32
B33
B34
ADC output data bit 1
ADC output data bit 2
ADC output data bit 3
ADC output data bit 4
ADC output data bit 5
ADC output data bit 6
DB8
DB9
DB10
DB11
DB12
FSSEL
REFSEL
OEn
CLK
B35
B36
B37
B38
B39
B27
B25
B24
B40
ADC output data bit 7
ADC output data bit 8
ADC output data bit 9
ADC output data bit 10
ADC output data bit 11 (LSB)
Full Scale Select (Low = 2Vpp, High = 3Vpp)
Reference Select (Low = Internal, High = External)
Output Enable (Low = Enabled, High = Tri-Stated)
Convert Clock (rising edge active)
Table 8 – ADC #2 P160 Interface
Signal
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
FSSEL
REFSEL
OEn
CLK
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JX1 P160
Connector
B10
B11
B12
B13
B14
A25
B16
B17
A27
B19
B20
B21
B9
B23
A11
B22
Description
ADC output data bit 0 (MSB)
ADC output data bit 1
ADC output data bit 2
ADC output data bit 3
ADC output data bit 4
ADC output data bit 5
ADC output data bit 6
ADC output data bit 7
ADC output data bit 8
ADC output data bit 9
ADC output data bit 10
ADC output data bit 11 (LSB)
Full Scale Select (Low = 2Vpp, High = 3Vpp)
Reference Select (Low = Internal, High = External)
Output Enable (Low = Enabled, High = Tri-Stated)
Convert Clock (rising edge active)
8
2.2.1
A/D Signal Flow
Figure 7 shows the first stage of the analog input channel.
5V
* For DC coupling
C18 = 0 Ω
J1
C18*
.1 uf
R15
1.1K Ω
R6
50Ω
Gain = 1
3
1
U1
2
R8
50 Ω
R21
1.1K Ω
R10
402Ω
R4*
0Ω
* For gain of 2
R4 = 402 Ω
C20
.1 uf
Figure 7 – Analog Input Stage
An analog signal with amplitude 1 Vp-p or 1.5 Vp-p is applied to J1 for ADC #1 or to J7 for ADC
#2. The input has a 50 ohm termination through R8 and R65. The input signal is AC coupled,
biased to 2.5 volts for unipolar operation, and buffered through the op amp. Low-level analog
inputs can be amplified by adjusting the gain setting of this front-end op amp circuit. As shown,
the gain is defined as:
R10 + R4
G = ------------------- = 1
R10
Changing R4 (ADC #1) and R61 (ADC #2) to 402 ohms would result in a gain = 2. This would
limit the analog input to a .5 Vp-p range. The range of the input signal is dependant on the Full
Scale Select control signal to the A/D. Setting this signal to a logic high, enables 3 Vp-p inputs to
the A/D, which corresponds to a 1.5 Vp-p input to the board. Setting the Full Scale Select to low,
selects a 2 Vp-p range into the A/D and a 1 Vp-p input range to the board.
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C11
56 pf
5
R1
100Ω
R2
100Ω
6
G ain = 2
F c = 19.4 MHz
U1
C82
.1 uf
7
C19
.1 uf
R3
402Ω
R12
402 Ω
C21
.1 uf
Figure 8 – Analog Filter Stage
The second op-amp stage incorporates an active two-pole Sallen-Key low pass filter set for a 3db frequency of 19.4MHz. The gain of the circuit is set at G = 2, resulting in a 2 Vpp output signal
centered at 2.5 V. It is possible to modify this circuit to adjust the gain and the 3-db frequency as
shown below.
R12 + R3
G = ------------------- = 2
R12
Figure 9 – ADC Low Pass Filter Gain
Table 9 – ADC Gain Adjust Values
R3
402 Ω
402 Ω
510 Ω
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ADC #1
R12
402 Ω
804 Ω
340 Ω
Gain
2
1.5
2.5
R60
402 Ω
402 Ω
510 Ω
ADC #2
R69
402 Ω
804 Ω
340 Ω
Gain
2
1.5
2.5
10
1
fc = ----------------------------- = 19.4 MHz
½
2π (R1R2C11C19)
Figure 10 – ADC Low Pass Filter 3-db Frequency
Table 10 – ADC Low Pass Filter Adjust Values
ADC #1
R1
100 Ω
120 Ω
120 Ω
R2
100 Ω
100 Ω
100 Ω
C11
56 pf
56 pf
120 pf
R58
100 Ω
28.9 Ω
33.7 Ω
R59
100 Ω
120 Ω
150 Ω
C47
56 pf
100 pf
100 pf
C19
120 pf
56 pf
120 pf
fc
19.4 MHz
26 MHz
12.1 MHz
ADC #2
C55
56 pf
56 pf
56 pf
fc
28.4 MHz
36 MHz
30 MHz
The Texas Instruments THS4150 Differential Amplifier is used to convert the intermediate singleended analog input signal into a differential signal for final input into the A/D. Figure 11 shows
the circuit used.
July 24, 2003
11
5V
Depopulated
R118
402Ω
R5
402Ω
R7
402Ω
R18
50Ω
ADC
U3
U2
5V
R13
50Ω
R119
402Ω
R20
402 Ω
R116
402Ω
Figure 11 – ADC Differential Amplifer
2.2.2 A/D Data Format
The 12-bit digital data output from the ADS807 is a positive straight offset binary code as shown
in the table below.
Table 11 – ADC Output Values
ADC Input Offset Binary Output
+.5V
0V
-.5V
1111 1111 1111
1000 0000 0000
0000 0000 0000
2.2.3 A/D Clocking
The ADS807 samples the input signal on the rising edge of the CLK input. Output data values
are valid at the A/D outputs 6 clock cycles later, after the rising edge of the clock. It is important
that this clock have minimal jitter, close to a 50% duty cycle and fast rise and fall times of 2ns or
less.
2.2.4 A/D Full Scale Select
The ADS807 can be configured for a differential full-scale input range of either 2 Vp-p or 3 Vp-p.
The ADC1.FSSEL and ADC2.FSSEL control signals from the FPGA control the setting of this
input range.
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12
Table 12 – ADCx.FSSEL Control
FSSEL
LOW
HIGH
Description
2 Vp-p input range
3 Vp-p input range
2.2.5 A/D Internal Reference
The ADS807 has an internal reference source that can be enabled or disable through the FPGA
control signal ADC1.REFSEL and ADC2.REFSEL.
Table 13 – ADCx.REFSEL Control
REFSEL
LOW
HIGH
Description
Internal reference selected
External reference selected
2.2.6 A/D Over-Range Indicator
If the analog input voltage exceeds the full-scale range of the A/D, the ADC1.OTR and
ADC2.OTR signal will go high. OTR is updated along with the output data that corresponds to
the sampled analog input voltage. Therefore, the OTR data is subject to the same 6-clock cycle
pipeline delay as the digital data.
2.3
External Clock Inputs
The P160 Analog Module includes two external clock input connectors, J2 and J4. These clock
inputs are 50 ohm terminated and can be used to drive the clock inputs to the baseboard FPGA.
Two jumpers, JP5 and JP6 are used to jumper the corresponding clock inputs to one of two
FPGA pins. To achieve optimum performance, the clock input signals should connect to global
clock input pins on the FPGA. Jumpers JP5 and JP6 allow for selection of global clock input pins
to either the Virtex-II MB1000 baseboard or the Virtex-II Pro P4/P7 baseboard. Table 14 and 15
shows the jumper settings.
Table 14 – JP5 External Clock Settings
JP5 Pins
J2 External Clock Input
Description
2-3 closed J2 Clock input set for MB1000 platform
1-2 closed J2 Clock input set for Virtex-II Pro platform
P160 Pin FPGA Pin
JX2-A20
AB12
JX1-A39
E12
Table 15 – JP6 External Clock Settings
JP6 Pins
J4 External Clock Input
Description
2-3 closed J2 Clock input set for MB1000 platform
1-2 closed J2 Clock input set for Virtex-II Pro platform
July 24, 2003
P160 Pin FPGA Pin
JX2-B14
JX1-B15
Y12
F12
13
When connecting to the Spartan-II 200 PCI or Spartan-IIE platforms, regular I/O pins must be
used for these clock inputs since global clock inputs are not available. The jumper settings for
either of these baseboards are arbitrary.
2.4
P160 Connectors
A P160 format of the Analog Module allows the board to be interchanged with any of the P160
compatible baseboards from Memec Design. However, due to the external global clock input
routing, the Memec Design Virtex-II MB1000 and Virtex-II Pro P4/P7 platforms are the ideal
choices.
The P160 interface used on the Analog Module is 3.3 V compatible, so the 3.3 V bank setting
should be chosen on the baseboard when connecting to the Analog Module. The following tables
show the pin assignments to the P160 Analog Module connectors (JX1 and JX2).
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14
Table 16 – P160 Connector – JX1
BOARD NAME ! 2S200PCI
S2E
S2ELC
MB1000
REVISION !
REV2
REV1
REV1
REV1
JX1 PIN
SIGNAL NAME
FPGA PIN NUMBER
A9
NC
E16
D16
C7
K22
A11
ADC2.OEn
E15
C16
D7
J21
A13
NC
E14
D15
C6
G22
A15
NC
F12
C15
D6
F21
A17
NC
C10
D14
C5
D22
A19
NC
D10
B16
D5
C21
A21
NC
B8
E14
C4
L20
A23
NC
A7
B15
F5
K19
A25
ADC2.DB6
B7
AA20
G5
H20
A27
ADC2.DB9
B6
C13
H5
G19
A29
NC
A5
E13
J6
F20
A31
NC
B5
C12
J5
F19
A33
NC
A4
V17
K6
D11-GCLK
A35
NC
B4
Y18
K5
C11-GCLK
A37
NC
A3
W18
L6
C8
A39
CLKIN1.2VP
B3
B12
L5
D8
B8
ADC2.OTR
B19
D17
B7
L22
B9
ADC2.FSSEL
A19
C17
A6
L21
B10
ADC2.DB1
B18
C18
B6
K21
B11
ADC2.DB2
A18
D18
A5
J22
B12
ADC2.DB3
B17
B19
B5
H22
B13
ADC2.DB4
A17
A19
A4
H21
B14
ADC2.DB5
A16
B18
B4
G21
B15
CLKIN2.2VP
B15
A18
A3
F22
B16
ADC2.DB7
A15
B17
B3
E22
B17
ADC2.DB8
B14
A17
D3
E21
B18
NC
A14
AB20
E3
D21
B19
ADC2.DB10
B13
A16
F4
C22
B20
ADC2.DB11
A13
AB21
F3
L18
B21
ADC2.DB12
B12
A15
G4
L19
B22
ADC2.CLK
C18
B14
G3
K18
B23
ADC2.REFSEL
D17
A14
H4
K20
B24
ADC1.OEn
C17
B13
H3
J20
B25
ADC1.REFSEL
D16
A13
J4
J19
B26
ADC1.OTR
C16
C14
J3
H19
B27
ADC1.FSSEL
D15
D13
K4
G20
B28
ADC1.DB1
C15
E12
K3
E19
B29
ADC1.DB2
D14
D12
L4
E20
B30
ADC1.DB3
C14
A12
L3
L17
B31
ADC1.DB4
D13
E17
C2
K17
B32
ADC1.DB5
C13
E16
C1
J17
B33
ADC1.DB6
E13
E15
D2
J18
B34
ADC1.DB7
C12
AA18
D1
H18
B35
ADC1.DB8
D12
F14
E2
G18
B36
ADC1.DB9
E12
F13
E1
F18
B37
ADC1.DB10
C9
F12
F2
E18
B38
ADC1.DB11
D9
Y19
F1
E11
B39
ADC1.DB12
C8
AB19
G2
A10
B40
ADC1.CLK
D8
AA19
G1
B10
* FPGA pins are dedicated to 2.5 V signal levels, but not used on this module
P160
CONNECTOR
July 24, 2003
2VPx
REV2
F18
H20
E11-GCLK*
F11-GCLK*
F10*
D9*
B11*
E10*
G19
F20
F19
E20
C10*
D10*
E19
E12-GCLK
G18
E17
E16
E15
E14
F14
F13
F12-GCLK
H22
H21
G22
G21
F22
F21
E22
E21
D22
D21
C22
C21
D18
D17
D16
C16
D15
C15
D14
D13
C13
E13
B12
G20
H19
15
Table 17 – P160 Connector – JX2
P160
CONNECTOR
JX2 PIN
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
B2
B4
B6
B8
B10
B12
B14
B16
B18
B20
July 24, 2003
BOARD NAME !
REVISION !
SIGNAL NAME
NC
NC
DAC2.CLK2
DAC2.PD
DAC2.REFSELECT
DAC2.DB14
DAC2.DB13
DAC2.DB12
DAC2.DB11
DAC2.DB10
DAC2.DB9
DAC2.DB8
DAC2.DB7
DAC2.DB6
DAC2.DB5
DAC2.DB4
DAC2.DB3
DAC2.DB2
DAC2.DB1
CLKIN1.2V
DAC2.CLK1
NC
DAC1.CLK2
DAC1.PD
DAC1.REFSELECT
DAC1.DB14
DAC1.DB13
DAC1.DB12
DAC1.DB11
DAC1.DB10
DAC1.DB9
DAC1.DB8
DAC1.DB7
DAC1.DB6
DAC1.DB5
DAC1.DB4
DAC1.DB3
DAC1.DB2
DAC1.DB1
DAC1.CLK
NC
NC
NC
NC
NC
NC
CLKIN2.2V
NC
NC
NC
2S200PCI
S2E
REV2
REV1
V14
Y14
W13
Y18
Y13
Y17
V13
Y16
Y12
Y15
V12
AB20
V11
AA19
W11
AB18
V10
AB17
Y10
AA15
W10
AA14
Y9
AA13
W9
AA12
Y8
AB10
W8
AB9
Y7
AB8
W7
AA7
Y6
AA6
W6
AA5
W5
AA4
W18
W17
W16
W15
W14
AA20
AA18
AA17
AB16
AB15
S2ELC
MB1000
REV1
REV1
FPGA PIN NUMBER
AB18
A7
AB18
AA16
B8
AA16
AA17
A8
AA17
AB16
B9
AB16
AB17
A9
AB17
AA15
B10
AA15
W17
A10
W17
AB15
B11
AB15
Y17
D8
Y17
AA14
C8
AA14
W16
D9
W16
AB14
C9
AB14
Y16
D10
Y16
AA13
C10
AA13
V16
D11
V16
AB13
E11
AB13
W15
F11
W15
AB11
E12
AA12-GCLK
V14
F12
V14
AA11
E13
AB12-GCLK
U14
F13
U14
AB9
E14
AB9
U13
F14
U13
AA9
E15
AA9
U12
E16
U12
AB8
E17
AB8
U11
C12
U11
AA8
D12
AA8
U10
C13
U10
AB7
D13
AB7
U9
C14
U9
AA7
D14
AA7
V9
C15
V9
AB6
D15
AB6
V8
C16
V8
AA6
D16
AA6
V7
C17
V7
AB5
D17
AB5
V6
C18
V6
AA5
D18
AA5
Y15
E8
Y15
W14
E9
W14
Y14
E10
Y14
W13
F10
W13
Y13
A12
Y13
V13
B12
V13
Y12
A13
Y12-GCLK
W12
B13
W12-GCLK
V12
A14
V12
V10
B14
V10
2VPx
REV2
J21
J22
K21
K22
L21
M21
N22
P22
P21
R22
R21
T22
T21
U22
U21
V22
V21
W22
W21
Y22
Y21
AA22
R20
R19
T20
T19
U20
U19
V20
V19
M17
N17
P17
P18
R18
T18
U18
AB21
N21
H18
J18
J17
K17
L17
J19
J20
K19
K20
K18
L20
16
P160
CONNECTOR
JX2 PIN
B22
B24
B26
B28
B30
B32
B34
B36
B38
B40
3
V1.0
V1.1
V1.2
BOARD NAME !
2S200PCI
S2E
REVISION !
SIGNAL NAME
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
REV2
REV1
AB14
AB13
AB11
AA10
AA9
AA8
AB6
AB5
AB4
AB3
Y10
W10
Y9
W9
Y8
W8
Y7
W7
Y6
W6
S2ELC
REV1
FPGA PIN NUMBER
A15
B15
A16
B16
A17
B17
A18
B18
A19
B19
MB1000
2VPx
REV1
REV2
Y10
W10
Y9
W9
Y8
W8
Y7
W7
Y6
W6
L19
L18
M18
M19
M20
N18
N20
N19
P20
P19
Revisions
Initial release for Rev 1 board
Added Spartan-IIELC board
Added design files for Virtex-IIPro
July 24, 2003
October 31, 2002
June 23, 2003
July 24, 2003
17