July 2011 MOS Model, level 3100 t t t TOC Index t 6 MOS Model, level 3100 Quit file © NXP 1992-2011 169 MOS Model, level 3100 July 2011 6.1 Introduction The Junction-Field-Effect Transistor (JFET) and the depletion mode Metal-Oxide Semi(MOSFET) are semiconductor devices whose operation is achieved by depleting an already existing channel via a voltage controlled p-n junction (JFET) or a gate controlled surface depletion (MOSFET). These devices are often used as a load in high voltage MOS devices. This long channel JFET/MOSFET model is special developed to describe the drift region of LDMOS, EPMOS and VDMOS devices. When the n-channel MOS transistor equations are used for p-channel MOS transistors, the sign of the terminal potentials, terminal currents and terminal charges must be changed. 6.1.1 Survey of modelled effects • Accumulation at the surface (MOSFET) • Depletion from the surface • Depletion from the bulk • Pinch off mode • Velocity saturation in the channel • Gate charge model • Substrate charge model • Self-heating • Different temperature scaling for RON and VSAT • Include temperature scaling for RSAT Not included in the model Short channel effects • Subthreshold currents • Inversion at the surface at high negative gate voltages. TOC Index t © NXP 1992-2011 t t t 170 • Quit file July 2011 Noise model t t t TOC Index t • MOS Model, level 3100 Quit file © NXP 1992-2011 171 MOS Model, level 3100 July 2011 6.2 Symbols, parameters and constants 6.2.1 Parameter list The parameters are listed below . Parameter Units Description LEVEL - Model level, must be set to 3100 PARAMCHK - Level of clip warning info *) RON Ω Ohmic resistance at zero bias RSAT Ω Space charge resistance at zero bias VSAT V Critical drain-source voltage for hot carriers PSAT − Velocity saturation coefficient VP V Pinch off voltage at zero gate and substrate voltages VP ≤ 0: no depletion and/or accumulation in the channel TOX m Gate oxide thickness TOX > 0: MOSFET device TOX ≤ 0: No accumulation and/or depletion at the surface DCH m-3 Doping level channel DSUB m-3 Doping level substrate DSUB ≤ 0 : No depletion from the substrate VSUB V Substrate diffusion voltage VGAP V Bandgap voltage channel CGATE F Gate capacitance at zero bias CSUB F Substrate capacitance at zero bias TAUSC s Space charge transit time of the channel ACH − Temperature coefficient restivity of the channel ACHMOD − Parameter to switch to extended temperature scaling ACHRON − Temperature coefficient of ohmic resistance at zero bias ACHVSAT − Temperature coefficient of critical drain-source voltage for hot carriers ACHRSAT − Temperature coefficient of space charge resistance at zero bias TOC Index t © NXP 1992-2011 t t t 172 Quit file July 2011 MOS Model, level 3100 Parameter Units Description TREF °C Reference temperature DTA °C Temperature offset to the ambient temperature *) See Appendix B for the definition of PARAMCHK. The parameters for the model including self-heating are listed in the table below. Parameter Units Description RTH oC/W Thermal resistance CTH J/oC Thermal capacitance ATH − Temperature coefficient of the thermal resistance. The MULT and PRINTSCALED parameter arelisted in the table below. Parameter Units Description MULT − Multiplication factor PRINTSCALED − Flag to add scaled parameters to the OP output Parameter MULT This parameter may be used to put several devices in parallel. The following parameters are multiplied by MULT : CGATE CSUB CTH Divided by MULT are: RSAT RTH t t t TOC Index t RON Quit file © NXP 1992-2011 173 MOS Model, level 3100 July 2011 Default and clipping values The default values and clipping values as usedfor the MOS level 3100 model are listed below. Parameter name Units Default Clip low Clip high LEVEL - 3100 - - 0 - - PARAMCHK Ω 1.00 1e-2 - RSAT Ω 1.00 1e-2 - VSAT V 10.00 1.00 ×10-6 - PSAT − 1.00 0.1 - VP V -1.00 -1.0 - TOX m -1.00 -1.0 0.0001 DCH m-3 1.00 ×1021 1.00 ×1011 1.00 ×1029 DSUB m-3 1.00 ×1021 -1.0 1.00 ×1029 VSUB V 0.60 0.05 - VGAP V 1.20 0.1 - CGATE F 0.00 0.0 - CSUB F 0.00 0.0 - TAUSC s 0.00 0.0 - ACH − 0.00 - - ACHMOD − 0.00 0 1 ACHRON − 0.00 - - ACHVSAT − 0.00 - - ACHRSAT − 0.00 - - TREF °C 25 -273.0 - DTA °C 0.00 - - TOC Index t © NXP 1992-2011 t t t 174 RON Quit file July 2011 MOS Model, level 3100 The default values and clipping values of the additional parameters for the model including self-heating (see section 6.4) is listed in the table below. Parameter Name Units Default Clip low Clip high RTH oC/W 300.0 0.000 - CTH J/oC 3.0¥10-9 0.000 - ATH - 0.0 - - The MULT and PRINTSCALED parameter aree listed in the table below. Parameter Name Units Default Clip low Clip high MULT - 1.000 0.000 - PRINTSCALED - 0 - - t t t t TOC Index Quit file © NXP 1992-2011 175 MOS Model, level 3100 July 2011 6.3 Model equations A full description of the long channel JFET/MOSFET model is given below. Gate Qgs Q gd Ids Source Drain Qds Qbs Qbd Substrate Figure 15: Equivalent Circuit of an JFET/MOSFET 6.3.1 Model constants q = 1.6021918 ⋅ 10 – 10 ε ox = 3.453 ⋅ 10 © NXP 1992-2011 C⁄V⋅m – 11 (6.1) C⁄V⋅m TOC Index (6.2) t t t 176 C t ε si = 1.036 ⋅ 10 – 19 Quit file July 2011 MOS Model, level 3100 --k- = 0.86171 × 10 –4 V ⁄ K q δ v = 10 –8 V 0 = 10 ε = 10 (6.3) (6.4) –3 (6.5) –2 (6.6) The default reference temperature TREF for parameter determination is 25 °C. 6.3.2 Temperature effects The actual simulation temperature is denoted by TEMP (in oC). The temperature at which the parameters are determined is TREF (in oC). • Conversions to Kelvins 3 Note Note the addition of the voltage VdT of the thermal node in order to include self-heating, see section 6.7. T K = TEMP + DTA + 273.15 + V dT (6.7) T amb = TEMP + DTA + 273.15 (6.8) T RK = TREF + 273.15 (6.9) TK T N = --------T RK (6.10) t t t t TOC Index Quit file © NXP 1992-2011 177 MOS Model, level 3100 • July 2011 Thermal Voltage k V T = --- ⋅ T K q • On resistance and saturation voltage RON T = RON ⋅ T ACHRON VSAT T = VSAT ⋅ T ACHVSAT RSAT T = RSAT ⋅ T ACHRSAT • (6.12) (6.13) (6.14) Substrate depletion capacitance. k VSUB T = – 3 ⋅ --- ⋅ T K ⋅ ln ( T N ) + VSUB ⋅ T N + ( 1 – T N ) ⋅ VGAP q (6.15) VSUB CSUB T = CSUB ⋅ -----------------VSUB T (6.16) Thermal resistance RTH T T amb = RTH ⋅ ------------ T RK (6.17) TOC Index t t t © NXP 1992-2011 ATH t • 178 (6.11) Quit file July 2011 MOS Model, level 3100 6.3.3 Model preprocessing • Parameter dependent constants DC part If TOX ≤ 0 CGATE = 0 If DSUB ≤ 0 DSUB = 0 If TOX < 0 & DSUB < 0 VP = 0 For both DSUB and TOX less than or equal to zero the pinch off voltage VP = 0. When VP ≤ 0 only equations 6.29, 6.47, 6.49, 6.50, 6.62, 6.63, 6.104 and 6.105 are used. In this case the charges Qb and Qg are equal zero. DSUB > 0:k b = 2 ⋅ ε si ⋅ q ⋅ DSUB ⋅ DCH -----------------------------------------------------------DSUB + DCH (6.18) DSUB ≤ 0:k b = 0 (6.19) k b ⋅ VP Q bp = ----------------------------------------------------------------VP + VSUB T + VSUB T (6.20) ε si ⋅ q ⋅ DCH TOX 2 V ox = -------------------------------- ⋅ ------------ ε ox 2 (6.21) TOX > 0:k ox = 2 ⋅ ε si ⋅ q ⋅ DCH (6.22) TOX ≤ 0:k ox = 0 (6.23) k ox ⋅ VP Q sp = ---------------------------------------------VP + V ox + V ox (6.24) t t t t TOC Index Quit file © NXP 1992-2011 179 MOS Model, level 3100 Q i = Q bp + Q sp (6.25) Q m = k b ⋅ VP + VSUB T + k ox ⋅ VP + V ox (6.26) Qi T s = -------------------q ⋅ DCH (6.27) ε ox TOX > 0:C ox = -----------TOX (6.28) TOX ≤ 0:C ox = 0 (6.29) kb C b = ----------------------------2 ⋅ VSUB T (6.30) VSAT T J sat = -------------------------T s ⋅ RON T (6.31) RSAT VR sat = VSAT T ⋅ ---------------RON T (6.32) –2 2 ⋅ Qi TOC Index t t t © NXP 1992-2011 (6.33) t δ q = 10 180 July 2011 Quit file July 2011 MOS Model, level 3100 6.3.4 Model evaluation Drain and source voltage Vd ≥ Vs sign = 1 V d1 = V d V s1 = V s Vd < Vs sign = – 1 V d1 = V s V s1 = V d Substrate - source voltage < VSUB T 2 DSUB > 0: V bm = VSUB T + V s1 – V b – ε ⁄ VSUB T (6.34) V b1 = VSUB T + V s1 – 0.5 ⋅ ( V bm + 2 V bm 2 +4⋅ε ) DSUB ≤ 0 :V b1 = V b Gate voltage V g > V b1 – V g sw DSUB > 0 & TOX > 0 : V g sw = VSUB T – V ox + ( Q m ⁄ k ox ) 2 (6.35) 2 V gm = V g – V b1 + V g sw – ε ⋅ V g sw t t t t TOC Index Quit file (6.36) © NXP 1992-2011 181 MOS Model, level 3100 July 2011 2 2 2 V g 1 = V b1 – V g sw + 0.5 ⋅ V gm + V gm + 4 ⋅ ε ⋅ V g sw (6.37) DSUB ≤ 0 or TOX ≤ 0 : V g1 = V g • Pinch-off voltage DSUB ≤ 0:V p = VP + V g 1 (6.38) TOX ≤ 0:V p = VP + V b1 (6.39) TOX > 0 & DSUB > 0 : V b sw = V g 1 – 2 ⋅ ( Q i ⁄ k b ) ⋅ VSUB T – ( Q i ⁄ k b ) 2 (6.40) V b1 > V b sw : k b ⋅ Q m DSUB + DCH - ⋅ -----------------------------------b p = ---------------2 DCH k ox (6.41) Qm 2 DSUB + DCH c p = ------- + ( V g 1 – V b1 + VSUB T – V ox ) ⋅ ----------------------------------- k ox DCH (6.42) 2 Vp cp = V b1 – VSUB T + ----------------------------------------------------------------------2 2 2 ⋅ bp + cp + 2 ⋅ bp ⋅ bp + cp V b1 ≤ V bSW : TOC Index t © NXP 1992-2011 t t t 182 Quit file (6.43) July 2011 • MOS Model, level 3100 kb 2 b ac = V g 1 + ( Q i + k b ⋅ VSUB T ) ⁄ C ox + ---------------- 2 ⋅ C ox (6.44) kb 2 kb V p = b ac + ---------------- – -------- ⋅ b ac + VSUB T – V b1 2 ⋅ C ox C ox (6.45) Source and drain voltage including pinch-off and velocity saturation 2 VP > 0:V sp = 1 ⁄ 2 ⋅ V s1 + V p – ( V s1 – V p ) + δ v (6.46) VP ≤ 0:V sp = V s1 (6.47) VP > 0:V c 2 ⋅ VSAT T ⋅ ( V p – V sp ) = --------------------------------------------------------------------------------------------------------------2 2 VSAT T + V p – V sp + VSAT T + ( V p – V sp ) (6.48) VP ≤ 0:V c = VSAT T (6.49) ( V d 1 – V s1 ) ⋅ V c V dp = V sp + --------------------------------------------------------------------------PSAT PSAT PSAT ( V – V ) + Vc d1 s1 Integration boundary voltage V sp < V g 1 : V ad V dp < V g 1 V ad = V dp V dp ≥ V g 1 V ad = V g 1 V sp ≥ V g 1 : V ad = V sp t t t TOC Index t • (6.50) Quit file © NXP 1992-2011 183 MOS Model, level 3100 • July 2011 Transformation of voltages V sp – V b1 + VSUB T V sp – V b S spb S spb = -----------------------1 ,Y spb = -------------------------------VSUB T 1 + 1 + S spb (6.51) V dp – V b1 + VSUB T V dp – V b S dpb S dpb = -----------------------1 , Y dpb = -------------------------------VSUB T 1 + 1 + S dpb (6.52) V ad – V b1 + VSUB T S adb V ad – V b1 S adb = ------------------------ , Y adb = -------------------------------VSUB T 1 + 1 + S adb (6.53) V sp – V g 1 + V ox V sp – V g S spg = -----------------------1 , V ox S spg V sp ≥ V g 1 : Y spg = -------------------------------1 + 1 + S spg (6.54) V dp – V g 1 + V ox S dpg V dp – V g 1 = ------------------------ , V ox S dpg V dp ≥ V g 1 :Y dpg = --------------------------------1 + 1 + S dpg (6.55) TOC Index t © NXP 1992-2011 t t t 184 Quit file July 2011 MOS Model, level 3100 V ad – V g 1 + V ox S adg V ad – V g 1 = ------------------------ , V ox S adg V ad ≥ V g 1 : Y adg = --------------------------------1 + 1 + S adg (6.56) • Current reduction due to substrate effect 2 I bd • • 2 2 3 3 – 4 ⋅ C b ⋅ VSUB T Y dpb – Y spb Y dpb – Y spb = ---------------------------------------- ⋅ --------------------------- + ---------------------------- Q i ⋅ RON T 2 3 (6.57) Current increase due to accumulation 2 2 2 C ox ⋅ V ox S spg – S adg = -------------------------- ⋅ --------------------------- Q i ⋅ RON T 2 V sp < V g 1 I sa V sp ≥ V g 1 I sa = 0 (6.58) (6.59) Current reduction due to depletion at the surface V dp ≥ V g 1 : I sd 2 2 2 3 3 – 4 ⋅ C ox ⋅ V ox Y dpg – Y adg Y dpg – Y adg = --------------------------------- ⋅ ---------------------------- + ----------------------------- Q i ⋅ RON T 2 3 (6.60) V dp < V g 1 : I sd = 0 Total ohmic current VP > 0 : V dp – V sp I ohm = ----------------------- + I bd + I sa + I sd RON T t t t TOC Index t • Quit file (6.61) © NXP 1992-2011 185 MOS Model, level 3100 VP ≤ 0 : • July 2011 V dp – V sp I ohm = ----------------------RON T (6.62) Total current including velocity saturation V d 1 – V dp I ds = sign ⋅ I ohm ⋅ 1 + ----------------------- VR sat (6.63) 6.3.5 Substrate charge model 4 ( V p – V sp ) V dp – V sp -----------------------------------F c = --------------------------------------------------------------⋅ 4 4 V +V – V 0 dp sp ( V p – V sp ) + ( VP ⁄ 100 ) 2 2 2 3 (6.64) 3 4 ⋅ VSUB T Y dpb – Y spb Y dpb – Y spb Vb 1 = -------------------------------- ⋅ --------------------------- + ---------------------------- RON T ⋅ I ohm 2 3 3 3 3 4 (6.65) 4 – 8 ⋅ C b ⋅ VSUB T Y dpb – Y spb Y dpb – Y spb Vb 2 = ------------------------------------------ ⋅ --------------------------- + ---------------------------- Q i ⋅ RON T ⋅ I ohm 3 4 3 3 3 4 4 – 8 ⋅ C b ⋅ VSUB T Y dpb – Y spb Y dpb – Y spb Vb 2 = ------------------------------------------ ⋅ --------------------------- + ---------------------------- Q i ⋅ RON T ⋅ I ohm 3 4 TOC Index t © NXP 1992-2011 t t t 186 (6.66) Quit file (6.67) July 2011 MOS Model, level 3100 For TOX ≤ 0:V b 3 = V b 4 = 0 (6.68) V sp < V g 1 3 V b3 4 ⋅ C ox ⋅ VSUB T = ------------------------------------------ ⋅ Q i ⋅ RON T ⋅ I ohm V g 1 – V b1 Y 2adb – Y 2spb Y 3adb – Y 3spb ----------------------- ⋅ ---------------------------- + ---------------------------- – VSUB T 2 3 3 3 4 4 5 5 Y adb – Y spb Y adb – Y spb Y adb – Y spb 2 ⋅ ---------------------------- + 3 ⋅ ---------------------------- + ---------------------------- 3 4 5 (6.69) V sp ≥ V g 1 :V b3 = 0 V dp ≥ V g 1 :z 0 = ( V g 1 – V b1 – V ox + VSUB T ) ⁄ 2 t t t t TOC Index Quit file (6.70) © NXP 1992-2011 187 MOS Model, level 3100 July 2011 – k ox ⋅ k b ------------------------------------------------------ ⋅ Q i ⋅ RON T ⋅ C b ⋅ I ohm exact Vb 4 ( V ox – VSUB T ) ⋅ [ ( Y dpb – Y dpg ) – ( Y adb – Y adg ) ] + VSUB T ⋅ Y dpb ⋅ [ Y dpb ⋅ ( 1 + Y dpb ) + Y dpg ⋅ ( 3 + 3 ⋅ Y dpb + Y 2dpb ) ] 2 1 --- ⋅ VSUB T ⋅ V ox ⋅ – VSUB T ⋅ Y adb ⋅ [ Y adb ⋅ ( 1 + Y adb ) + Y adg ⋅ ( 3 + 3 ⋅ Y adb + Y adb ) ] 4 2 +V ⋅Y ⋅ [ Y ⋅ ( 1 + Y ) + Y ⋅ ( 3 + 3 ⋅ Y + Y ) ] ox dpg dpg dpg dpb dpg dpg 2 = – V ox ⋅ Y adg ⋅ [ Y adg ⋅ ( 1 + Y adg ) + Y adb ⋅ ( 3 + 3 ⋅ Y adg + Y adg ) ] VSUB T ⋅ ( 1 + Y dpb ) + V ox ⋅ ( 1 + Y dpg ) 2 – z 0 ⋅ ln -------------------------------------------------------------------------------------------------------VSUB T ⋅ ( 1 + Y adb ) + V ox ⋅ ( 1 + Y adg ) –2⋅ 3⁄2 VSUB T 2 2 3 3 Y dpb – Y adb Y dpb – Y adb ⋅ V ox ⋅ ----------------------------+ ----------------------------- 2 3 2 2 3 3 Y dpg – Y adg Y dpg – Y adg 3⁄2 – 2 ⋅ V ox ⋅ VSUB T ⋅ ----------------------------- + ------------------------------ 2 3 (6.71) TOC Index t © NXP 1992-2011 t t t 188 Quit file July 2011 MOS Model, level 3100 – k ox ⋅ k b ------------------------------------------------------ ⋅ Q i ⋅ RON T ⋅ C b ⋅ I ohm 2 2 3 3 V dp – V ad V dp – V ad 1 -------------------------------------------- ⋅ ( V dp – V ad ) ⋅ [ V b ⋅ V g ] – ------------------------- ⋅ [ V g + V b ] + ------------------------ + 1 1 1 1 2 3 4 ⋅ VSUB T ⋅ V ox appro Vb 4 { ( V dp – V ad ) ⋅ [ V b 1 ⋅ V g 1 ⋅ ( V g 1 ⋅ VSUB T + V b1 ⋅ V ox ) ] – = V 2 – V 2 2 2 dp ad ------------------------ ⋅ [ V g ⋅ VSUB T + V b ⋅ V ox + 2 ⋅ V b ⋅ V g ⋅ ( VSUB T + V ox ) ] + 1 1 1 1 2 1 3 3 -------------------------------------------------------⋅ 3 ⁄ 2 V dp – V ad ------------------------- ⋅ [ V ⋅ ( 2 ⋅ VSUB + V ) + V ⋅ ( VSUB + 2 ⋅ V ) ] – 16 ⋅ ( VSUB T ⋅ V ox ) g1 T ox b1 T ox 3 V 4 – V 4 dp ad ------------------------ ⋅ [ VSUB T + V ox ] 4 (6.72) 2 Y sw 2 2 2 VSUB T ⋅ ( Y dpb + Y adb ) + V ox ⋅ ( Y dpg + Y adg ) = --------------------------------------------------------------------------------------------------------------2 V 0 ⋅ ( VSUB T + V ox ) (6.73) 2 ( 1 + 2 ⋅ V o ) ⋅ Y sw Sw = ----------------------------------------- – Vo 2 1 + Y sw (6.74) exact Sw ≥ 1 V b4 = Vb 4 Sw ≤ 0 V b4 = Vb 4 Sw > 0 & Sw < 1 Vb 4 = Sw ⋅ Vb 4 V dp ≤ V g 1 Vb 4 = 0 (6.75) appr (6.76) exact (6.77) (6.78) t t t t TOC Index appr + ( 1 – Sw ) ⋅ Vb 4 Quit file © NXP 1992-2011 189 MOS Model, level 3100 July 2011 Q b x = – C SUB T ⋅ ( Vb 1 + Vb 2 + Vb 3 + Vb 4 ) (6.79) Q b y = – C SUB T ⋅ VSUB T ⋅ ( Y dpb + Y spb ) (6.80) Cb fix = 0.01 ⋅ CSUB + MULT ⋅ 10 – 17 (6.81) Qb = 0.99 ⋅ { F c ⋅ Q b x + ( 1 – F c ) ⋅ Q b y } + Cb fix ⋅ { Vb 1 – ( V d + V s ) ⁄ 2 } (6.82) TOC Index t © NXP 1992-2011 t t t 190 Quit file July 2011 MOS Model, level 3100 6.3.6 Gate charge model 2 2 2 – V ox S spg – S adg = -------------------------------- ⋅ --------------------------- RON T ⋅ I ohm 2 V sp < V g 1 : V g1 V sp ≥ V g 1 : V g1 = 0 (6.83) (6.84) 2 2 2 3 3 4 ⋅ V ox Y dpg – Y adg Y dpg – Y adg = -------------------------------- ⋅ ---------------------------- + ----------------------------- RON T ⋅ I ohm 2 3 V dp ≥ V g 1 : V g2 V dp < V g 1 : V g2 = 0 (6.86) DSUB ≤ 0 : V g3 = V g4 = 0 (6.87) DSUB > 0 : Cb V g 3 = -------- ⋅ V b3 C ox (6.88) Cb V g 4 = -------- ⋅ V b4 C ox (6.89) 3 3 (6.85) 3 C ox ⋅ V ox S spg – S adg = ------------------------------------------ ⋅ --------------------------- Q i ⋅ RON T ⋅ I ohm 3 V sp < V g 1 : V g5 V sp ≥ V g 1 : V g5 = 0 (6.90) (6.91) 3 3 3 4 4 – 8 ⋅ C ox ⋅ V ox Y dpg – Y adg Y dpg – Y adg = ------------------------------------------ ⋅ ---------------------------- + -----------------------------(6.92) Q i ⋅ RON T ⋅ I ohm 3 4 V dp ≥ V g 1 : V g6 V dp < V g 1 : V g6 = 0 (6.93) Q g x = – CGATE ⋅ ( V g 1 + V g 2 + V g 3 + V g 4 + V g 5 + V g 6 ) (6.94) : t t t t TOC Index Quit file © NXP 1992-2011 191 MOS Model, level 3100 July 2011 V sp + V dp V sp + V dp V g 1 ≥ ------------------------ : Q gy = CGATE ⋅ V g 1 – ------------------------ 2 2 2 ⋅ CGATE ⋅ [ V g 1 – ( V sp + V dp ) ⁄ 2 ] V sp + V dp V g 1 < ------------------------ : Q g y = --------------------------------------------------------------------------------------- 2 V g 1 – ( V sp + V dp ) ⁄ 2 1 + 1 – -------------------------------------------------V ox Cg fix = 0.01 ⋅ CGATE + MULT ⋅ 10 – 17 (6.95) (6.96) (6.97) Q g = 0.99 ⋅ { F c ⋅ Q g x + ( 1 – F c ) ⋅ Q g y } + Cg fix ⋅ { V g 1 – ( V d + V s ) ⁄ 2 } (6.98) TOC Index t © NXP 1992-2011 t t t 192 Quit file July 2011 MOS Model, level 3100 6.3.7 Drain and source charge model VP > 0 : V g 1 ≥ V sp :Q s = – C ox ⋅ V ox ⋅ S spg (6.99) V g 1 < V sp : Q s = – 2 ⋅ C ox ⋅ V ox ⋅ Y spg (6.100) Q spx = Q i + Q s – 2 ⋅ C b ⋅ VSUB T ⋅ Y spb (6.101) 2 T sp VP ≤ 0 : Q spx + Q spx + δ q = ------------------------------------------2 ⋅ q ⋅ DCH (6.102) I hc = J sat ⋅ T sp (6.103) I hc = VSAT T ⁄ RON T (6.104) 1 ⁄ ( 2 ⋅ PSAT ) Q ds = sign ⋅ TAUSC ⋅ I hc I ds 2 ⋅ PSAT -------- 1 + I - hc –1 (6.105) Q d = – 0.5 ⋅ ( Q g + Q b + Q ds ) (6.106) Q s = – 0.5 ⋅ ( Q g + Q b – Q ds ) (6.107) Numerical Adaptation To implement MOS Model, level 3100 in a circuit simulator, care must be taken of the numerical stability of the simulation program. The functions as well as their derivatives should be continuous at any bias condition that may occur during the iteration cycle. t t t t TOC Index Quit file © NXP 1992-2011 193 MOS Model, level 3100 July 2011 6.4 Self-heating Self-heating is part of the model. It is defined in the usual way by adding a self-heating network (see Figure 16) containing a current source describing the dissipated power and both a thermal resistance RTH and a thermal capacitance CTH. dT RTHT CTH Pdiss Material ATH Si Ge GaAs AlAs InAs InP GaP SiO2 1.3 1.25 1.25 1.37 1.1 1.4 1.4 0.7 Figure 16: On the left, the self-heating network, where the node voltage VdT is used in the temperature scaling relations. Note that for increased flexibility the node dT is available to the user. On the right are parameter values that can be used for Ath. The resistance and capacitance are both connected between ground and the temperature node dT. The value of the voltage VdT at the temperature node gives the increase in local temperature, which is included in the calculation of the temperature scaling relation (6.4), see section 6.3.2 on page 177. For the value of ATH we recommend using values from literature that describe the temperature scaling of the thermal conductivity. For the most important materials, the values are given in Figure 16, which is largely based on Ref. [1 ], see also [ 2]. For example, if the value of VdT is 0.5V, the increase in temperature is 0.5 degrees Celsius. The total dissipated power is a sum of the dissipated power of each branch of the equivalent circuit and is given by: P diss = I DS ⋅ V DS The total dissipation applies for the geometrical model (mnt1, mpt2, mos3100t3). TOC Index t © NXP 1992-2011 t t t 194 Quit file July 2011 MOS Model, level 3100 Below a Pstar example is given to illustrate how self-heating works. q Example Title: example self-heating 3100; circuit; mnt_1(Vd, Vg, Vs, 0, dt) level=3100, Rth=1e6,Cth=1e-9; R_1 ( Vdd, Vd) 100; R_2 ( Vgg, Vg) 1k; R_3 ( Vs, 0) 100; e_SRC_2 (Vgg ,net101) 5; e_SRC_1 ( Vdd, 0) 1; e_SRC_3 ( net101, 0) 0; end; dc; print: vn(dt), op(pdiss.mnt_1); end; run; result: DC Analysis. VN(DT) Pdiss.MNT_1 = = 24.764E+00 24.764E-06 The voltage on node dT is 24.764e+0 V, which means that the local temperature is increased by 24.764e+0 oC. 1.Pstar model name. 2.Pstar model name. 3.Spectre/ADS model name. t t t t TOC Index Quit file © NXP 1992-2011 195 MOS Model, level 3100 July 2011 6.5 DC Operating point output The DC operating point output facility gives information on the state of a device at its operation point. Besides terminal currents and voltages, the magnitudes of linearized internal elements are given. In some cases meaningful quantities can be derived which are then also given (e.g. u). The objective of the DCOP-facility is twofold: • • Calculate small-signal equivalent circuit element values. Open a window on the internal bias conditions of the device and its basic capabilities (e.g. u). Below the printed items are described. Cxy indicates the derivate of the charge Q at terminal x to the voltage at terminal y, when all other terminals remain constant. Quantity Equation Description Level 3100 Model level Ids Ids Drain Source current Vds Drain Source voltage Vgs Gate Source voltage Vbs Bulk Source voltage Vp Vp Channel pinch-off voltage gm dIds/dVg Transconductance gmb dIds/dVb Bulk transconductance gds dIds/dVd Output conductance Qg Cgd -dQg/dVd Gate charge dependence on drain voltage Cgg dQg/dVg Gate charge dependence on gate voltage Cgs -dQg/dVs Gate charge dependence on source voltage Cgb -dQg/dVb Gate charge dependence on bulk voltage TOC Index t t t © NXP 1992-2011 Bulk charge t Qb 196 Gate charge Quit file July 2011 MOS Model, level 3100 Cbd -dQb/dVd Bulk charge dependence on drain voltage Cbg -dQb/dVg Bulk charge dependence on gate voltage Cbs -dQb/dVs Bulk charge dependence on source voltage Cbb dQb/dVb Bulk charge dependence on bulk voltage Qd Drain charge Cdd +dQd/dVd Drain charge dependence on drain voltage Cdg -dQd/dVg Drain charge dependence on gate voltage Cds -dQd/dVs Drain charge dependence on source voltage Cdb -dQd/dVb Drain charge dependence on bulk voltage Qs Source charge Csd -dQs/dVd Source charge dependence on drain voltage Csg -dQs/dVg Source charge dependence on gate voltage Css +dQs/dVs Source charge dependence on source voltage Csb -dQs/dVb Source charge dependence on bulk voltage u gm/gds Transistor gain Rout 1/gds Small signal output resistance Vearly Ids/gds Equivalent Early voltage Iohm Iohm Drain source current excluding velocity saturation Ihc Ihc Critical current for velocity saturation. The additional operating point output for the model including self-heating (see section 6.4) is listed in the table below. Quantity Equation Description TK TK Actual temperature including self-heating Pdiss Pdiss Power dissipation t t t t TOC Index Quit file © NXP 1992-2011 197 MOS Model, level 3100 July 2011 When the parameter PRINTSCALED is set to 1, the device parameter set after geometrical and temperature scaling is added to the OP output: Quantity Description RONT Ohmic resistance at zero bias RSATT Space charge resistance at zero bias VSATT Critical drain-source voltage for hot carriers PSAT Velocity saturation coefficient VP Pinch off voltage at zero gate and substrate voltages TOX Gate oxide thickness DCH Doping level channel DSUB Doping level substrate VSUBT Substrate diffusion voltage CGATE Gate capacitance at zero bias CSUBT Substrate capacitance at zero bias TAUSC Space charge transit time of the channel Remarks: • When Vds<0, gm and gmb are calculated with drain and source terminals interchanged (see section on Channel Type Declarations). The terminal voltages and IDS keep their sign. • The signs of Vp follow the conventions of the model parameter set. The parameter set is always assumed to correspond to an n-channel device. • MULT is a scaling parameter that multiplies all currents and charges by the value of MULT. This is equivalent to putting MULT (a number) MOS transistors in parallel. And as a consequence MULT effects the operating point output. © NXP 1992-2011 TOC Index t t t 198 A non-existent conductance, Gmin, is connected between the nodes DS. This conductance Gmin does not influence the DC-operating point. t • Quit file July 2011 MOS Model, level 3100 6.6 Simulator specific items 6.6.1 Pstar syntax n channel p channel n channel self-heating p channel self-heating : : : : mn_n (d,g,s,b) mp_n (d,g,s,b) mnt_n (d,g,s,b, dt) mpt_n (d,g,s,b, dt) level=3100, <parameters> level=3100, <parameters> level=3100, <parameters> level=3100, <parameters> n : occurrence indicator <parameters> : list of model parameters d,g,s, b and dt are drain, gate, source, bulk and self-heating terminals respectively. 6.6.2 Spectre syntax n channel : p channel : n channel self-heating: p channel self-heating: model modelname mos3100 type=n <modpar> componentname d g s b modelname <inpar> model modelname mos3100 type=p <modpar> componentname d g s b modelname <inpar> model modelname mos3100t type=n <modpar> componentname d g s b dt modelname <inpar> model modelname mos3100t type=p <modpar> componentname d g s b dt modelname <inpar> modelname : name of model, user-defined componentname : occurrence indicator <modpar> : list of model parameters <inpar> : list of instance parameters d,g,s, b and dt are drain, gate, source, bulk and self-heating terminals respectively. 3 Note Warning! In Spectre, use only the parameter statements type=n or type=p. Using any other string and/or numbers will result in unpredictable and possibly erroneous results. t t t t TOC Index Quit file © NXP 1992-2011 199 MOS Model, level 3100 July 2011 6.6.3 ADS syntax n channel : p channel : model modelname mos3100 gender=1 <modpar> modelname:componentname d g s b <instpar> model modelname mos3100 gender=0 <modpar> modelname:componentname d g s b <instpar> model modelname mos3100t gender=1 <modpar> modelname:componentname d g s b dt <instpar> model modelname mos3100t gender=0 <modpar> modelname:componentname d g s b dt <instpar> n channel self-heating: p channel self-heating: modelname : name of model, user-defined componentname : occurrence indicator <modpar> : list of model parameters <instpar> : list of instance parameters d,g,s, b and dt are drain, gate, source, bulk and self-heating terminals respectively. 6.6.4 The ON/OFF condition for Pstar The solution for a circuit involves a process of successive calculations. The calculations are started from a set of ‘initial guesses’ for the electrical quantities of the nonlinear elements. A simplified DCAPPROX mechanism for devices using ON/OFF keywords is mentioned in [3]. By default the devices start in the default state. Nu n-channel ON OFF VDS 2.0 2.0 2.0 VGS -2.0 -2.0 VSB 0.0 0.0 © NXP 1992-2011 Default ON OFF VDS -2.0 -2.0 -2.0 -4.0 VGS 2.0 2.0 4.0 2.0 VSB 0.0 0.0 -2.0 TOC Index t Default t t t 200 p-channel Quit file July 2011 MOS Model, level 3100 6.6.5 The ON/OFF condition for Spectre Nu n-channel OFF Triode Saturation Subthreshold Reverse Forward Breakdown VDS 0.0 0.75 1.25 0.0 0 0 0 VGS 0.0 2.0 1.25 0.0 0 0 0 VSB 0.0 0.0 0.0 0.0 0 0 0 N p-channel OFF Triode Saturation Subthreshold Reverse Forward Breakdown VDS 0.0 -0.75 -1.25 0.0 0 0 0 VGS 0.0 -2.0 -1.25 0.0 0 0 0 VSB 0.0 0.0 0.0 0.0 0 0 0 6.6.6 The ON/OFF condition for ADS n-channel p-channel Default Default VDS 0 VDS 0 VGS 0 VGS 0 VSB 0 VSB 0 t t t t TOC Index Quit file © NXP 1992-2011 201 MOS Model, level 3100 July 2011 6.7 References [1] V. Palankovski R. Schultheis and S. Selberherr, Modelling of power heterojunction bipolar transistor on gallium arsenide,IEEE Trans. Elec. Dev., vol 48, pp. 1264-1269, 2001. Note: the paper uses α = 1.65 for Si, but α = 1.3 goves a better fit: also, k300 for GaAs is closer to 40 than to the published value of 46 (Palankovski, personal communication). [2] Sze, S.M., Physics of semiconductor devices, 2nd edition, John Wiley & Sons, Inc., New York, 1981 [3] Pstar User Manual. TOC Index t © NXP 1992-2011 t t t 202 Quit file December 2009 Hyp functions t t t TOC Index t A Hyp functions Quit file 119 Hyp functions December 2009 hyp1 ε 0 Figure 7: X 1 2 2 hyp 1 ( x ;ε ) = --- ⋅ ( x + x + 4 ⋅ ε ) 2 x0 ε hyp2 TOC Index t t t 120 hyp 2 ( x ; x 0 ;ε ) = x – hyp 1 ( x – x 0 ;ε ) t Figure 8: x x0 0 Quit file December 2009 Hyp functions xo+hyp1(-xo;ε) ε hyp3 x0 0 Figure 9: x hyp 3 ( x ; x 0 ;ε ) = hyp 2 ( x ; x 0 ;ε ) – hyp 2 ( 0 ; x 0 ;ε ) for ε = ε ( x 0 ) hyp4 ε -hyp1(-xo;ε) xo x 0 hyp 4 ( x ; x 0 ;ε ) = hyp 1 ( x – x 0 ;ε ) – hyp 1 ( – x 0 ;ε ) t t t TOC Index t Figure 10: Quit file 121 Hyp functions December 2009 x0 ε hyp5 xo 0 x 2 ε Figure 11: hyp 5 ( x ; x 0 ;ε ) = x 0 – hyp 1 x 0 – x – ----- ,ε x0 for ε = ε ( x 0 ) The hypm-function: x⋅ y hypm [ x, y;m ] = ---------------------------------------------------2⋅m 2 ⋅ m 1 ⁄ (2 ⋅ m) (x +y ) (1.289) setlength{unitlength}{0.40900pt} begin{picture}(1500,900)(0,0) enrm hinlines drawline[-50](264,158)(1436,158) hinlines drawline[-50](264,158)(264,787) hicklines path(264,158)(264,178) hicklines path(264,787)(264,767) put(264,113){makebox(0,0){0}} hicklines path(264,158)(1436,158)(1436,787)(264,787)(264,158) put(45,472){makebox(0,0)[l]{shortstack{hyp t TOC Index t t t 122 Quit file December 2009 Spectre Specific Information t t t TOC Index t B Spectre Specific Information Quit file 123 Spectre Specific Information December 2009 Imax, Imelt, Jmelt parameters Introduction Imax, Imelt and Jmelt are Spectre-specific parameters used to help convergence and to prevent numerical problems. We refer in this text only to the use of Imax model parameter in Spectre with SiMKit devices since the other two parameters, Imelt and Jmelt, are not part of the SiMKit code. For information on Imelt and Jmelt refer to Cadence documentation. Imax model parameter Imax is a model parameter present in the following SiMKit models: – juncap and juncap2 – psp and pspnqs (since they contain juncap models) In Mextram 504 (bjt504) and Modella (bjt500) SiMKit models, Imax is an internal parameter and its value is set through the adapter via the Spectre-specific parameter Imax. The default value of the Imax model parameter is 1000A. Imax should be set to a value which is large enough so it does not affect the extraction procedure. In models that contain junctions, the junction current can be expressed as: V I = I s exp ------------------ – 1 N ⋅ φ TD (1.290) The exponential formula is used until the junction current reaches a maximum (explosion) current Imax. V exp l I max = I s exp ----------------– 1 N ⋅ φ TD- (1.291) The corresponding voltage for which this happens is called Vexpl (explosion voltage). The voltage explosion expression can be derived from (1): I max V exp l = N ⋅ φ TD log ---------- + 1 Is TOC Index t t t 124 V > V exp l the following linear expression is used for the junction current: t For (1.292) Quit file December 2009 Spectre Specific Information Is V exp l I = I max + ( V – V exp l ) ------------------ exp ------------------ N ⋅ φ TD N ⋅ φ TD (1.293) Region parameter Region is an Spectre-specific model parameter used as a convergence aid and gives an estimated DC operating region. The possible values of region depend on the model: – For Bipolar models: – subth: Cut-off or sub-threshold mode – fwd: Forward – rev: Reverse – sat: Saturation. – off1 – – For MOS models: – subth: Cut-off or sub-threshold mode; – triode: Triode or linear region; – sat: Saturation 1 – off For PSP and PSPNQS all regions are allowed, as the PSP(NQS) models both have a MOS part and a juncap (diode). Not all regions are valid for each part, but when e.g. region=forward is set, the initial guesses for the MOS will be set to zero. The same holds for setting a region that is not valid for the JUNCAP. – For diode models: – fwd: Forward – rev: Reverse – brk: Breakdown – off1 Model parameters for device reference temperature in Spectre This text describes the use of the tnom, tref and tr model parameters in Spectre with SiMKit devices to set the device reference temperature. 1.Off is not an electrical region, it just states that the user does not know in what state the device is operating t t t t TOC Index Quit file 125 Spectre Specific Information December 2009 A Simkit device in Spectre has three model parameter aliases for the model reference temperature, tnom, tref and tr. These three parameters can only be used in a model definition, not as instance parameters. There is no difference in setting tnom, tref or tr. All three parameters have exactly the same effect. The following three lines are therefore completely equivalent: model nmos11020 mos11020 type=n tnom=30 model nmos11020 mos11020 type=n tref=30 model nmos11020 mos11020 type=n tr=30 All three lines set the reference temperature for the mos11020 device to 30 C. Specifying combinations of tnom, tref and tr in the model definition has no use, only the value of the last parameter in the model definition will be used. E.g.: model nmos11020 mos11020 type=n tnom=30 tref=34 will result in the reference temperature for the mos11020 device being set to 34 C, tnom=30 will be overridden by tref=34 which comes after it. When there is no reference temperature set in the model definition (so no tnom, tref or tr is set), the reference temperature of the model will be set to the value of tnom in the options statement in the Spectre input file. So setting: options1 options tnom=23 gmin=1e-15 reltol=1e-12 \ vabstol=1e-12 iabstol=1e-16 model nmos11020 mos11020 type=n will set the reference temperature of the mos11020 device to 23 C. When no tnom is specified in the options statement and no reference temperature is set in the model definition, the default reference temperature is set to 27 C. So the lines: options1 options gmin=1e-15 reltol=1e-12 vabstol=1e-12 \ iabstol=1e-16 model nmos11020 mos11020 type=n will set the reference temperature of the mos11020 device to 27 C. t TOC Index t t t 126 Quit file December 2009 Spectre Specific Information The default reference temperature set in the SiMKit device itself is in the Spectre simulator never used. It will always be overwritten by either the default "options tnom", an explicitly set option tnom or by a tnom, tref or tr parameter in the model definition. t t t t TOC Index Quit file 127 Spectre Specific Information t TOC Index t t t 128 December 2009 Quit file June 2010 OvervoltageSpecification OvervoltageSpecification t t t TOC Index t C Quit file 129 OvervoltageSpecification June 2010 Overvoltage warnings in SiMKit Introduction Overvoltage flagging is signalling that a (terminal) voltage is outside a specified safe range. A warning will be given when the conditions for giving a warning are fulfilled. Simple checks for overvoltage have been added to the following models: mos903, mos1100, mos1101, mos1102, mos2002, mos2003, mos3100, mos4000, psp102, psp103. The checks are done on terminal voltages of the models. There are many ways to define overvoltage. For a general overvoltage flagging solution Verilog-A should be used. Extra parameters for overvoltage flagging A set of extra parameters has been added to the mos models mos903, mos1100, mos1101, mos1102, mos2002, mos2003, mos3100, mos4000, psp102, psp103. Table 6: Name Unit Default Description VBOX V 0.0 Oxide breakdown voltage. Checking will be done if VBOX > 0 VBDS V 0.0 Drain-source breakdown voltage Checking will be done if VBDS > 0 TMIN s 0.0 Ovcheck tmin value TOC Index t t t 130 t For mos models the safe region is: V gs < VBOX and V gd < VBOX and V ds < VBDS Quit file June 2010 OvervoltageSpecification enter msg VBOX leave msg Ovcheck: two terminal dummy model A (dummy) two-terminal model ovcheck has been implemented that can be used to check if the voltage between the two terminals is within or without a so called safe region. The model parameters are: Name Unit Default Description VLOW V 0.0 Lower bound of safe region VHIGH V 0.0 Upper bound of safe region Checking will be done when VHIGH > VLOW TMIN s 0.0 Ovcheck tmin value For the ovcheck model the safe region is: VLOW ≤ V t1 – V t2 ≤ VHIGH , where t1 is the first and t2 is the second terminal. Functionality t t t TOC Index t In Spectre and Pstar At the end of a DC analysis or in a transient analysis after each time step a check wil be done if the device is inside or outside the safe region. A warning is given whenever the device enters or leaves the safe region. Quit file 131 OvervoltageSpecification June 2010 TOC Index t t t 132 t In Spectre only To prevent too many warnings in a Spectre transient analysis the model parameter TMIN has been introduced. If the time between leaving and entering the safe region is less than the TMIN value no warning is given. Because of the TMIN parameter a warning cannot be issued when leaving the safe region. A warning is given when the device enters the safe region again. This warning includes the time and the voltage when the safe region was exited.At the end of the transient warnings are given for devices that are still out of the safe range. In Pstar TMIN may be specified as a model parameter, but it will be ignored. Quit file July 2011 Parameter PARAMCHK Parameter PARAMCHK t t t TOC Index t D Quit file 133 Parameter PARAMCHK July 2011 Parameter PARAMCHK Introduction All models have the parameter PARAMCHK. It is not related to the model behavior, but has been introduced control the clip warning messages. Various situations may call for various levels of warnings. This is made possible by setting this parameter. PARAMCHK model parameter This model parameter has been added to control the amount of clip warnings. PARAMCHK < PARAMCHK ≥ 0 Clip warnings for instance parameters (default) PARAMCHK ≥ 1 PARAMCHK ≥ 2 Clip warnings for electrical parameters at initialisation PARAMCHK ≥ 3 Clip warnings for electrical parameters during evaluation. This highest level is of interest only for selfheating jobs, where electrical parameters may change dependent on temperature. Clip warnings for model parameters t TOC Index t t t 134 0 No clip warnings Quit file April 2008 Bibliography t t t TOC Index t E Bibliography Quit file 135 Bibliography April 2008 [1] Sze, S.M., Physics of semiconductor devices, 2nd edition, John Wiley & Sons, Inc., New York, 1981 [2] Muller, R.S. and Kamins, T.I., Device electronics for integrated circuits, 2nd edition, John Wiley & Sons, Inc., New York, 1986 [3] Ong D.G., Modern MOS Technology: Processes, Devices and Design, McGrawHill Book Company, 1984 [4] Tsividis Y.P., Operation and modelling of the MOS Transistor, McGraw-Hill Book Company, 1987 [5] Paolo Antognetti, Giuseppe Massobrio, Semiconductor Device Modeling with SPICE, McGraw-Hill, 1988. [6] Dileep A. Divekar, FET Modeling for Circuit Simulation, Kluwer Academic Publishers, 1988 [7] Laurence W. Nagel, Spice2: A computer program to simulate semiconductor circuits, University of California, Berkeley, 1975 [8] PSpice manual, MicroSim Corporation, January 1989 [9] Pstar User Manual. [10] J.J.A. Hegge, Model Specification of MOS level 1 Spice model (Metal Oxide Semiconductor Transistor), version 2, January 1991. [11] Andrei Vladimirescu, Sally Liu, The simulation of MOS integrated circuits using SPICE2, Univ. of Cal. Berkeley, 1980 [12] N. Vossenstijn, G.J. Mulder, Model specification of a Junction Field Effect Transistor, CFT-CAD-E, 1990 [13] Y. Tsividis, G. Masetti, Problems in precision of the MOS transistor for analog applications, IEE trans. CAD, 1983 [14] K.A. Sakallah, Yao-Tsung Yen, S. Greenberg, The Meyer model revisited: explaining and correcting the charge nonconservation problem, Proceedings IEEE ICCAD, 1987 [15] P.B.L. Meijer, Meijer model for Meyer model [16] SPICE version 2G6 source code, Dep. Elec. Eng. and Comput. Sci., Univ. of California Berkeley, March 15, 1983. t TOC Index t t t 136 Quit file April 2008 Bibliography [17] Klaassen, F.M., Compact models for circuit simulation, Springer, Vienna, chapter 7: Models for the enhancement - type MOSFET (1989) [18] Klaassen, F.M., Compact models for circuit simulation, Springer, Vienna, chapter 6: MOSFET - physics (1989) [19] Wright, G.T., Physical and CAD models for the VLSI mosfet, IEEE Trans. on Electron Devices, vol ED-34, page 823 (1987) [20] Oh, S.Y., Ward D.E. and Dutton R.W., Transient analysis of MOS transistors/, IEEE Journal Solid-State Circuits, Vol. SC-15, page 636 (1980) [21] Sevat, M.F., On the channel charge division in MOSFET modeling, Digest technical papers ICCAD-87, Santa Clara CA, page 208 (1987) [22] Ir. C. Kortekaas, Description and users guide of the MOS interconnect capacitance extractor; MICE 2.0/, Nat. Lab Technical note 1988 [23] Ir. C. Kortekaas, Junction capacitance- and current description for simulator models/, Nat. Lab. Technical Note 1988 [24] H. Elzinga, Extending INTCAP/LOCAL with lateral capacitances between non-overlapping PS-INS, IN-PS and INS-IN layers, RNR-46/92-IX-044, 17-09-1992 [25] Bittel und Sturm, Rauschen, Springer, page 241, (1971) [26] Ir. A. v. Steenwijk, Private communication, (1994) [27] R.M.D.A. Velghe and D.B.M. Klaassen, First official parameter set for MOS Model 9.02 for the C150DM2 process, Nat. Lab. Report 6689 [28] A.J. Scholten and D.B.M. Klaassen, Geometrical scaling of θ1 in MOS Model 9, Nat. Lab. Report 6992 [29] A.J. Scholten and D.B.M. Klaassen, Anomalous geometry dependence of source/drain resistance in narrow-width MOSFETs, Proc. IEEE 1998 Int. Conference on Microelectronic Test Structures Vol. II, March 1998 [30] Kwok K. Hung et al., IEEE Trans El. Dev. Vol. 37, No. 3, March 1990 [31] Kwok K. Hung et al., IEEE Trans El. Dev. Vol. 37, No. 5, May 1990 [32] A.J. Scholten and D.B.M. Klaassen, New 1/f noise model in MOS Model 9, level 903, Nat.Lab Unclassified Report, NL-UR 816/98 [33] R. van Langevelde, MOS Model 11, Level 1100 NL-UR 2001/813, 2001. t t t t TOC Index Quit file 137 Bibliography April 2008 internet: http://www.semiconductors.philips.com/Philips_Models. [34] R. van Langevelde, A.J. Scholten and D.B.M. Klaassen, MOS Model 11, Level 1101 NL-UR 2002/802, 2002. internet: http://www.semiconductors.philips.com/Philips_Models. [35] R. van Langevelde, A Compact MOSFET Model for Distortion Analysis in Analog Circuit Design, PhD Thesis, TU Eindhoven, Eindhoven 1998. Available on request. Write to: Ronald.van.Langevelde@philips.com [36] R. van Langevelde and F.M. Klaassen, An Explicit Surface-Potential Based MOSFET Model for Circuit Simulation, Solid-State Electron., Vol. 44, pp. 409-418, 2000. [37] R.M.D.A. Velghe, D.B.M. Klaassen, F.M. Klaassen, MOS Model 9, NL-UR 003/94, 1994. internet: http://www.semiconductors.philips.com/ Philips Models. [38] R. van Langevelde and F.M. Klaassen, Influence of Mobility Degradation on Distortion Analysis in MOSFETs, in Proceedings ESSDERC 1996, Bologna, Italy, pp. 667-670, 1996. [39] R. van Langevelde and F.M. Klaassen, Effect of Gate-Field Dependent Mobility Degradation on Distortion Analysis in MOSFET s, IEEE Trans. Electron Devices, Vol. ED-44, No. 11, pp. 2044-2052, 1997. [40] R. van Langevelde and F.M. Klaassen, Accurate Drain Conductance Modeling for Distortion Analysis in MOSFETs, IEDM 1997 Tech. Digest, pp. 313-316, 1997. [41] A.R. Boothroyd, S.W. Tarasewicz and C. Slaby, MISNAN A Physically Based Continuous MOSFET Model for CAD Applications, IEEE Trans. Computer-Aided Design, Vol. CAD-10, No. 12, pp. 1512-1529, 1991. [42] K. Joardar, K.K. Gullapulli, C.C. McAndrew, M.E. Burnham and A. Wild, An Improved MOSFET Model for Circuit Simulation, IEEE Trans. Electron Devices, Vol. ED-45, No. 1, pp. 134-148, 1998. [43] Z.A. Weinberg, On Tunneling in Metal-Oxide-Silicon Structures, J. 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Cheng, A Physics-Based MOSFET Noise Model for Circuit Simulators, IEEE Trans. Electron Devices, Vol. ED-37, No. 5, pp. 1323-1333, 1990. [50] A.J. Scholten and D.B.M. Klaassen, New 1/f Noise Model in MOS Model 9, Level 903, NL-UR 816/98, 1998. [51] H.C. de Graaff and F.M. Klaassen, Compact transistor modelling for circuit design. Vienna/New York: Springer-Verlag, 1990. [52] R. van Langevelde et al., New Compact Model for Induced Gate Current Noise, IEDM 2003 Tech. Digest, pp. 867-870, 2003. [53] A.J. Scholten et al., Accurate Thermal Noise Model for Deep-Submicron CMOS, IEDM 1999 Tech. Digest, pp. 155-158, 1999. [54] M. Minondo, G. Gouget and A. Juge, New Length Scaling of Current Gain Factor and Characterization Method for Pocket Implanted MOSFET s, Proc. ICMTS 2001, pp. 263-267, 2001. [55] T.S. Hsieh, Y.W. Chang, W.J. Tsai and T.C. Lu, A New Leff Extraction Approach for Devices with Pocket Implants, Proc. ICMTS 2001, pp. 15-18, 2001. [56] A.J. Scholten, R. Duffy, R. van Langevelde and D.B.M. Klaassen, Compact Modelling of Pocket-Implanted MOSFETs, in Proceedings ESSDERC 2001, pp. 311-314, 2001. [57] R. van Langevelde et al., Gate Current: Modeling, ∆L Extraction and Impact on RF Performance, IEDM 2001 Tech. Digest, pp. 289-292, 2001. [58] R. van Langevelde, A.J. Scholten and D.B.M. Klaassen, MOS Model 11, level t t t t TOC Index Quit file 139 Bibliography April 2008 1101, Nat.Lab Unclassified Report, NL-UR 2002/802 [59] http://www.semiconductors.philips/Philips_Models [60] N. D' Halleweyn, Modelling and Characterisation of Silicon-On-Insulator Lateral Double Diffused MOSFETs for Analogue Circuit Simulation, Ph.D. Thesis, University of Southampton, August 2001 [61] R. van Langevelde and F.M. Klaassen, An Explicit Surface-Potential Based MOSFET Model for Circuit Simulation, Solid-State Electronics, Vol 44, 2000, pp. 409-418 [62] R. van Langevelde, A.J. Scholten and D.B.M. Klaassen, MOS Model 11, level 1101, Philips Research Unclassified Report, NL-UR 2002/802, December 2002 see http://www.semiconductors.philips.com/Philips_Models [63] A.C.T. Aarts and R. van Langevelde, A Robust and Physically Based Compact SOI-LDMOS Model, Proc. of the 32nd European Solid-State Device Research Conference (ESSDERC), University of Bologna, September 2002, pp. 455-458 [64] D.E. Ward and R.W. Dutton, A Charge-Oriented Model for MOS Transistor Capacitances, IEEE Journal of Solid-State Electronics, Vol 13, No. 5, October 1978, pp. 703-708 [65] A.C.T. Aarts M.J. Swanenberg and W.J. Kloosterman, Modelling of High-Voltage SOI-LDMOS Transistors including Self-Heating, Proc. SISPAD, Springer, 2001, pp. 246-249 [66] V. Palankovski R. Schultheis and S. Selberherr, Modelling of power heterojunction bipolar transistor on gallium arsenide,IEEE Trans. Elec. Dev., vol 48, pp. 1264-1269, 2001. Note: the paper uses α = 1.65 for Si, but α = 1.3 goves a better fit: also, k300 for GaAs is closer to 40 than to the published value of 46 (Palankovski, personal communication). [67] JUNCAP: http://www.semiconducors.philips.com/Philips_Models/ [68] G.A.M. Hurkx, D.B.M. Klassen and M.P.G. Knuvers, A new recombination model for device simulation including tunneling, IEEE Trans. El. Dev., Vol.39, No.2, pp.331-338, February 1992. [69] W. Jin, C.H. Chan, S.K.H. Fung, and P.K. Ko, Shot-noise-induced excess lowfrequency noise in floating-body partially depleted SOI MOSFET’s, IEEE Trans. El. Dev., Vol. 46, No. 6, pp. 1180– 1185, June 1999. t TOC Index t t t 140 Quit file April 2008 Bibliography [70] MOSModel 9: http://www.nxp.com/models/ t t t t TOC Index Quit file 141 Bibliography t TOC Index t t t 142 April 2008 Quit file

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