Congatec 041601, 041602, 041603, 041610, 041620, 041621 User Manual

COM Express™ conga-TR4

COM Express Type 6 Basic module based on 4th Generation AMD Embedded V- and R-Series SoC

User’s Guide

Revision 1.7

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Revision History

Revision Date (yyyy.mm.dd) Author Changes

0.1

1.0

1.1

1.2

2018.01.15

2018.10.15

2019.03.19

2019.04.02

BEU

BEU

BEU

BEU

• Preliminary release

• Updated “Electrostatic Sensitive Device” information on page 3

• Corrected single/dual channel MT/s rates for two variants in table 2

• Updated section 2.2 “Supported Operating Systems”

• Added values for four variants in section 2.5 "Power Consumption"

•

• Added values in section 2.6 "Supply Voltage Battery Power"

• Updated images in section 4 "Cooling Solutions"

• Added note about requiring a re-driver on carrier for USB 3.1 Gen 2 in section 5.1.2 "USB" and 7.4 "USB Host Controller"

• Added Intel ® Ethernet Controller i211 as assembly option in table 4 "Feature Summary" and section 5.1.4 "Ethernet"

Corrected section 7.4 "USB Host Controller"

• Added section 9 "System Resources"

•

• Corrected image in section 2.4 "Supply Voltage Standard Power"

Updated section 10.4 "Supported Flash Devices"

•

• Corrected supported memory in table 2, 3, and added information about supported memory in table 4

Added information about the new industrial variant in table 3 and 7

1.3

2019.07.30

BEU

1.4

1.5

1.6

1.7

2020.01.07

2020.03.04

2020.06.02

2020.11.19

BEU

BEU

BEU

BEU

•

• Updated note in section 4 "Cooling Solutions"

Changed number of supported USB 3.1 Gen 2 interfaces to two throughout the document

• Added note regarding USB 3.1 Gen 2 in section 7.4 "USB Host Controller"

•

• Updated title page

• Updated CPU clock speed of variant 041603 in table 2

• Added variants 041620 and 041621 to table 3 and 7

• Updated section 4 "Cooling Solutions"

Updated references for power supply implementation guidelines in section 5.1.12 "Power Control"

• Added reference to BIOS Setup Description application note in section 10 "BIOS Setup Description"

•

• Updated section 10.3 "Updating the BIOS"

• Updated supported flash device in section 10.4 "Supported Flash Devices"

Added note to several button signals in table 24

• Updated section 11 "Industry Specifications"

• Added power consumption values and updated existing ones in table 7

• Corrected product name in section 4 "Cooling Solutions"

•

• Added note to section 5.1.8 "LVDS"

Added PWR_OK implementation recommendation to section 5.1.12 "Power Control"

• Removed section 11 "Industry Specifications"

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Preface

This user’s guide provides information about the components, features and interfaces available on the conga-TR4. It is one of three documents that should be referred to when designing a COM Express™ application. The other reference documents that should be used include the following:

COM Express™ Design Guide

COM Express™ Specification

The links to these documents can be found on the congatec AG website at www.congatec.com

Disclaimer

The information contained within this user’s guide, including but not limited to any product specification, is subject to change without notice.

congatec AG provides no warranty with regard to this user’s guide or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. congatec AG assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user’s guide. In no event shall congatec AG be liable for any incidental, consequential, special, or exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this user’s guide or any other information contained herein or the use thereof.

Intended Audience

This user’s guide is intended for technically qualified personnel. It is not intended for general audiences.

Electrostatic Sensitive Device

All congatec AG products are electrostatic sensitive devices. They are enclosed in static shielding bags, and shipped enclosed in secondary packaging (protective packaging). The secondary packaging does not provide electrostatic protection.

Do not remove the device from the static shielding bag or handle it, except at an electrostatic-free workstation. Also, do not ship or store electronic devices near strong electrostatic, electromagnetic, magnetic, or radioactive fields unless the device is contained within its original packaging. Be aware that failure to comply with these guidelines will void the congatec AG Limited Warranty.

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Lead-Free Designs (RoHS)

All congatec AG designs are created from lead-free components and are completely RoHS compliant.

Symbols

The following symbols are used in this user’s guide:

Warning

Warnings indicate conditions that, if not observed, can cause personal injury.

Caution

Cautions warn the user about how to prevent damage to hardware or loss of data.

Note

Notes call attention to important information that should be observed.

Copyright Notice

Copyright © 2018, congatec AG. All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted without written permission from congatec AG.

congatec AG has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied “as-is”.

Trademarks

Product names, logos, brands, and other trademarks featured or referred to within this user’s guide, or the congatec website, are the property of their respective trademark holders. These trademark holders are not affiliated with congatec AG, our products, or our website.

4/65

Warranty

congatec AG makes no representation, warranty or guaranty, express or implied regarding the products except its standard form of limited warranty (“Limited Warranty”) per the terms and conditions of the congatec entity, which the product is delivered from. These terms and conditions can be downloaded from www.congatec.com. congatec AG may in its sole discretion modify its Limited Warranty at any time and from time to time.

The products may include software. Use of the software is subject to the terms and conditions set out in the respective owner’s license agreements, which are available at www.congatec.com and/or upon request.

Beginning on the date of shipment to its direct customer and continuing for the published warranty period, congatec AG represents that the products are new and warrants that each product failing to function properly under normal use, due to a defect in materials or workmanship or due to non conformance to the agreed upon specifications, will be repaired or exchanged, at congatec’s option and expense.

Customer will obtain a Return Material Authorization (“RMA”) number from congatec AG prior to returning the non conforming product freight prepaid. congatec AG will pay for transporting the repaired or exchanged product to the customer.

Repaired, replaced or exchanged product will be warranted for the repair warranty period in effect as of the date the repaired, exchanged or replaced product is shipped by congatec, or the remainder of the original warranty, whichever is longer. This Limited Warranty extends to congatec’s direct customer only and is not assignable or transferable.

Except as set forth in writing in the Limited Warranty, congatec makes no performance representations, warranties, or guarantees, either express or implied, oral or written, with respect to the products, including without limitation any implied warranty (a) of merchantability, (b) of fitness for a particular purpose, or (c) arising from course of performance, course of dealing, or usage of trade.

congatec AG shall in no event be liable to the end user for collateral or consequential damages of any kind. congatec shall not otherwise be liable for loss, damage or expense directly or indirectly arising from the use of the product or from any other cause. The sole and exclusive remedy against congatec, whether a claim sound in contract, warranty, tort or any other legal theory, shall be repair or replacement of the product only.

Certification

congatec AG is certified to DIN EN ISO 9001 standard.

ISO 9001

CER

TIFICATIO

N

TM

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Technical Support

congatec AG technicians and engineers are committed to providing the best possible technical support for our customers so that our products can be easily used and implemented. We request that you first visit our website at www.congatec.com for the latest documentation, utilities and drivers, which have been made available to assist you. If you still require assistance after visiting our website then contact our technical support department by email at [email protected]

Terminology

Term

PEG

PCH

SM

N.C

N/A

TBD

GB

GHz kB

MB

Mbit kHz

MHz

TDP

PCIe

SATA

Description

Gigabyte

Gigahertz

Kilobyte

Megabyte

Megabit

Kilohertz

Megahertz

Thermal Design Power

PCI Express

Serial ATA

PCI Express Graphics

Platform Controller Hub

System Management

Not connected

Not available

To be determined

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Contents

1 Introduction ............................................................................. 10

2 Specifications ........................................................................... 13

2.1

2.2

2.3

2.4

2.4.1

2.4.2

2.5

2.6

2.7

3

Feature List .............................................................................. 13

Supported Operating Systems ................................................ 14

Mechanical Dimensions ........................................................... 14

Supply Voltage Standard Power .............................................. 15

Electrical Characteristics .......................................................... 15

Rise Time ................................................................................. 16

Power Consumption ................................................................ 16

Supply Voltage Battery Power ................................................. 17

Environmental Specifications ................................................... 18

Block Diagram .......................................................................... 19

4

4.1

4.2

4.3

5

Cooling Solutions ..................................................................... 20

CSA Dimensions ...................................................................... 21

CSP Dimensions ....................................................................... 22

Heatspreader Dimensions ........................................................ 23

Connector Rows ....................................................................... 24

5.1

5.1.1

Primary Connector Rows A and B ............................................ 24

Serial ATA™ (SATA) .................................................................. 24

5.1.2 USB .......................................................................................... 24

5.1.3 High Definition Audio (HDA) ................................................... 24

5.1.4 Ethernet ................................................................................... 25

5.1.5

5.1.6

LPC Bus .................................................................................... 25

I²C Bus ..................................................................................... 25

5.1.7 PCI Express™ (PCIe) ................................................................ 26

5.1.8 LVDS ......................................................................................... 26

5.1.9 Optional eDP ........................................................................... 27

5.1.10 GPIO ........................................................................................ 27

5.1.11 UART ........................................................................................ 27

5.1.12

5.1.13

5.2

Power Control .......................................................................... 28

Power Management ................................................................. 30

Secondary Connector Rows C and D ....................................... 31

7

7.1

7.2

7.3

7.4

8

8.1

8.2

9

5.2.1

5.2.2

6

PCI Express™ Graphics (PEG) .................................................. 31

Digital Display Interface (DDI) .................................................. 31

Additional Features .................................................................. 32

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.3

6.4

6.5

6.6

6.1

6.1.1

6.1.2

6.1.3 congatec Board Controller (cBC) ............................................. 32

Board Information .................................................................... 32

Fan Control .............................................................................. 32

Power Loss Control .................................................................. 32

6.1.4 Watchdog ................................................................................ 33

6.2 OEM BIOS Customization ........................................................ 33

OEM Default Settings .............................................................. 33

OEM Boot Logo ....................................................................... 33

OEM POST Logo ..................................................................... 34

OEM BIOS Code/Data ............................................................. 34

OEM DXE Driver ...................................................................... 34 congatec Battery Management Interface ................................ 34

API Support (CGOS) ................................................................ 35

Security Features ...................................................................... 35

Suspend to Ram ....................................................................... 35

conga Tech Notes .................................................................... 36

AMD Processor Features ......................................................... 36

Thermal Management ............................................................. 37

ACPI Suspend Modes and Resume Events .............................. 37

USB Host Controller ................................................................. 39

Signal Descriptions and Pinout Tables ..................................... 40

A-B Connector Signal Descriptions ......................................... 41

C-D Connector Signal Descriptions ......................................... 51

System Resources .................................................................... 61

9.1

9.1.1

9.2

9.3

9.4

I/O Address Assignment .......................................................... 61

LPC Bus .................................................................................... 61

PCI Configuration Space Map ................................................. 62

I²C Bus ..................................................................................... 63

SM Bus ..................................................................................... 63

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10

10.1

10.2

BIOS Setup Description ........................................................... 64

Navigating the BIOS Setup Menu ........................................... 64

BIOS Versions........................................................................... 64

10.3

10.4

Updating the BIOS ................................................................... 65

Supported Flash Devices ......................................................... 65

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List of Tables

Table 1 COM Express™ 3.0 Pinout Types ............................................ 10

Table 2 conga-TR4 Commercial Options ............................................. 11

Table 3 conga-TR4 Industrial Options .................................................. 12

Table 4 Feature Summary ..................................................................... 13

Table 5 Electrical Characteristics .......................................................... 15

Table 6 Measurement Description ........................................................ 16

Table 7 Power Consumption Values ..................................................... 17

Table 8 CMOS Battery Power Consumption ........................................ 17

Table 9 Cooling Solution Variants ......................................................... 20

Table 10 Wake Events ............................................................................. 38

Table 11 Signal Tables Terminology Descriptions .................................. 40

Table 12 Connector A-B Pinout .............................................................. 41

Table 13 High Definition Audio Link Signal Descriptions ....................... 42

Table 14 LPC Signal Descriptions ........................................................... 43

Table 15 Serial ATA Signal Descriptions ................................................. 43

Table 16 USB 2.0 Signal Descriptions ..................................................... 43

Table 17 PCI Express Signal Descriptions (general purpose) ................. 45

Table 18 Gigabit Ethernet Signal Descriptions....................................... 46

Table 19 LVDS Signal Descriptions ......................................................... 47

Table 20 UART Interface Signal Descriptions ......................................... 47

Table 21 SPI BIOS Flash Interface Signal Descriptions ........................... 48

Table 22 General Purpose I/O Signal Descriptions ................................ 48

Table 23 Miscellaneous Signal Descriptions ........................................... 48

Table 24 Power and System Management Signal Descriptions ............. 49

Table 25 Power and GND Signal Descriptions ....................................... 50

Table 26 Connector C-D Pinout ............................................................. 51

Table 27 SuperSpeed USB Signal Descriptions ...................................... 53

Table 28 PCI Express Signal Descriptions (general purpose) ................. 53

Table 29 PCI Express Signal Descriptions (x16 Graphics) ....................... 54

Table 30 DDI Signal Description ............................................................. 56

Table 31 HDMI/DVI Signal Descriptions ................................................. 57

Table 32 DisplayPort (DP) Signal Descriptions ....................................... 59

Table 33 Module Type Definition Signal Description ............................. 60

Table 34 Power and GND Signal Descriptions ....................................... 60

Table 35 PCI Configuration Space Map ................................................. 62

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1 Introduction

COM Express™ Concept

COM Express™ is an open industry standard defined specifically for COMs (computer on modules). Its creation makes it possible to smoothly transition from legacy interfaces to the newest technologies available today. COM Express™ modules are available in following form factors:

• Mini

• Compact

• Basic

• Extended

84mm x 55mm

95mm x 95mm

125mm x 95mm

155mm x 110mm

Table 1 COM Express™ 3.0 Pinout Types

Types Connector Rows PCIe Lanes PCI

Type 1 A-B Up to 6

Type 2

Type 3

Type 4

Type 5

A-B C-D

A-B C-D

A-B C-D

A-B C-D

Type 6

Type 7

A-B C-D

A-B C-D

Type 10 A-B

Up to 22

Up to 22

Up to 32

Up to 32

Up to 24

Up to 32

Up to 4

32 bit

32 bit

-

-

-

-

1

-

1

-

IDE SATA Ports LAN ports

4 1

4

2

2

4

4

4

4

USB 2.0 / USB 3.0 Display Interfaces

8 / 0

1

3

1

3

8 / 0

8 / 0

8 / 0

8 / 0

1 8 / 4*

5 (1x 1 G, 4x 10 G) 4 / 4*

1 8 / 2*

VGA, LVDS

VGA, LVDS, PEG

VGA,LVDS, PEG

VGA,LVDS, PEG

VGA,LVDS, PEG

-

VGA,LVDS/eDP, PEG, 3x DDI

LVDS/eDP, 1xDDI

* The SuperSpeed USB ports (USB 3.0) are not in addition to the USB 2.0 ports. Up to 4 of the USB 2.0 ports can support SuperSpeed USB.

The conga-TR4 modules use the Type 6 pinout definition and comply with COM Express 3.0 specification. They are equipped with two high performance connectors that ensure stable data throughput and support high bandwidth networking.

The COM (computer on module) integrates all the core components of a common PC and is mounted onto an application specific carrier board. COM modules are legacy-free (no Super I/O, PS/2 keyboard and mouse) and provide most of the functional requirements for any application.

These functions include, but are not limited to, a rich complement of contemporary high bandwidth serial interfaces such as PCI

Express, Serial ATA, USB 3.0/2.0, and 10 Gigabit Ethernet.

Carrier board designers can use as little or as many of the I/O interfaces as deemed necessary. The carrier board can therefore provide all the interface connectors required to attach the system to the application specific peripherals. This versatility allows the designer to create a dense and optimized package, which results in a more reliable product while simplifying system integration. Most importantly, COM Express™ modules are scalable, which means once an application has been created there is the ability to diversify the product range through the use of different performance class or form factor size modules. Simply unplug one module and replace it with another; no redesign is necessary.

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conga-TR4 Options Information

The conga-TR4 is available in five variants. This user’s guide describes these variants. The table below shows the different configurations available.

Check the Part No. that applies to your product. This will tell you what options described in this user’s guide are available on your particular module.

Table 2 conga-TR4 Commercial Options

Part-No.

SoC

CPU Clock Speed

L2 Shared Cache

Memory (DDR4)

Graphics Engine

GPU Clock Speed

PCIe

USB

DDI

LVDS

SoC TDP

041600

V1807B

041601

V1756B

041602

V1605B

3.35 GHz (3.8 GHz Turbo) 3.25 GHz (3.6 GHz Turbo) 2.0 GHz (3.6 GHz Turbo)

2 MB 2 MB 2 MB

2400 MT/s dual channel, single/dual rank


3200 MT/s dual channel, single rank only


3200 MT/s dual channel, single rank only

AMD Radeon™ Vega 11 AMD Radeon™ Vega 8

1300 MHz

(11 Compute Units)

1x PCIe Gen 3 (x8/x4)

4x PCIe Gen 3 (x4/x2/x1)

4x PCIe Gen 2 (x1)

1300 MHz

(8 Compute Units)



4x PCIe Gen 2 (x1)

Up to:

2x USB 3.1 Gen 2

2x USB 3.1 Gen 1

4x USB 2.0

2x Dedicated DDI

1x DDI multiplexed with

USB port

1x LVDS (default) or

1x eDP (optional)

35-54W

Up to:

2x USB 3.1 Gen 2

2x USB 3.1 Gen 1

4x USB 2.0

2x Dedicated DDI


USB port


1x eDP (optional)

35-54W

AMD Radeon™ Vega 8

1100 MHz

(8 Compute Units)



4x PCIe Gen 2 (x1)

Up to:

2x USB 3.1 Gen 2

2x USB 3.1 Gen 1

4x USB 2.0

2x Dedicated DDI


USB port


1x eDP (optional)

12-25W

041603

V1202B

2.3 GHz (3.2 GHz Turbo)

1 MB



1000 MHz

(3 Compute Units)



4x PCIe Gen 2 (x1)

Up to:

2x USB 3.1 Gen 2

2x USB 3.1 Gen 1

4x USB 2.0

2x Dedicated DDI


USB port


1x eDP (optional)

12-25W

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Table 3 conga-TR4 Industrial Options

Part-No.

SoC

CPU Clock Speed

L2 Shared Cache

Memory (DDR4)

041610

V1404I

041620

R1606G

041621

R1505G

2.0 GHz (3.6 GHz Turbo) 2.6 GHz (3.5 GHz Turbo) 2.4 GHz (3.3 GHz Turbo)

2 MB 1 MB 1 MB




Graphics Engine

PCIe


GPU Clock Speed 1300 MHz

(8 Compute Units)



4x PCIe Gen 2 (x1)

USB Up to:

2x USB 3.1 Gen 2

2x USB 3.1 Gen 1

4x USB 2.0

DDI

LVDS/eDP

SoC TDP

2x Dedicated DDI


USB port


1x eDP (optional)

12-25W

AMD Radeon™ Vega 3 AMD Radeon™ Vega 3

1200 MHz

(3 Compute Units)

1000 MHz

(3 Compute Units)

1x PCIe Gen 3 (x4)

3x PCIe Gen 3 (x1)

4x PCIe Gen 2 (x1)

Up to:

2x USB 3.1 Gen 2

1x USB 3.1 Gen 1

4x USB 2.0

1x PCIe Gen 3 (x4)

3x PCIe Gen 3 (x1)

4x PCIe Gen 2 (x1)

Up to:

2x USB 3.1 Gen 2

1x USB 3.1 Gen 1

4x USB 2.0

2x Dedicated DDI 2x Dedicated DDI


1x eDP (optional)

12-25W


1x eDP (optional)

12-25W

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2 Specifications

2.1 Feature List

Table 4 Feature Summary

Form Factor

SoC

Memory

Chipset

Audio

Ethernet

Graphics Options

Based on COM Express™ standard pinout Type 6 (Basic size 95 x 125 mm)

4th Generation AMD Embedded V- and R-Series (FP5) SoC. NOTE: R-Series is not available yet.

Two memory sockets (located on the top and bottom side of the conga-TR4). Supports:

-

SO-DIMM ECC and non-ECC DDR4 memory modules

Data rates up to 3200 MT/s with single rank memory

Maximum 32 GB capacity (16 GB on each socket)

Integrated in the SoC

High Definition Audio (HDA) interface with support for up to three codecs.

1x Gigabit Ethernet PHY or via the onboard Intel ® Ethernet i210 Controller (i211 available as assembly option).

AMD Radeon™ Vega Graphics Core (GFX9). Supports:

-

DirectX ® 12, EGL 1.4, OpenCL ® 2.1, OpenGL ® ES (1.1, 2.x and 3.x), OpenGL ® Next, OpenGL ® 4.6

Video Core Next (VCN): H.265/HEVC HW encode and decode, 10b HEVC and VP9 decode, MS compliant JPEG encode and decode

Up to four independent displays (three in R-Series)

1x PCIe Gen 3 (x8/x4) (Only x4 in R-Series)

1x LVDS (default) or 1x eDP (optional)

2x Dedicated DDI (DP/HDMI/DVI)

1x DDI (DP/HDMI/DVI) (N/A in R-Series) multiplexed with USB 3.1 Gen 2

Peripheral Interfaces USB up to:

2x USB 3.1 Gen 2

2x USB 3.1 Gen 1 (Only 1x in R-Series)

4x USB 2.0

2x SATA ® 6 Gb/s ports

4x PCIe Gen 3 (x4/x2/x1) (Only 3x PCIe Gen3 (x1) in R-Series)

4x PCIe Gen 2 (x1)

2x UART

NOTE: HDMI/DVI requires an external level shifter on carrier board.

Fan control

GPIOs

Buses:

-

SPI

LPC

SM

I²C

BIOS

Security

AMI Aptio ® UEFI 5.x firmware; 8 MByte serial SPI with congatec Embedded BIOS features

Infineon LPC TPM 2.0 on module. Integrated TPM 2.0 in SoC.

Power Management ACPI 5.0 compliant with battery support. Also supports Suspend to RAM (S3).

cBC Multi-stage watchdog, manufacturing and board information, board statistics, I2C bus, Power loss control.

Note

Some of the features mentioned in the table above are optional. See Table 2 and Table 3 for available features on each module variant.

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2.2

2.3

Supported Operating Systems

The conga-TR4 supports the following operating systems.

• Microsoft ® Windows ® 10 (64-bit)

• Microsoft ® Windows ® 10 IoT Enterprise (64-bit)

• Linux (32/64-bit)

Note

To improve the graphic performance of conga-TR4 after installing Microsoft ® Windows ® Operating System, congatec AG recommends the installation of AMD catalyst driver.

Mechanical Dimensions

• 95.0 mm x 125.0 mm (3.74” x 4.92”)

• Height approximately 18 or 21 mm (including heatspreader) depending on the carrier board connector that is used. If the 5mm (height) carrier board connector is used then approximate overall height is 18 mm. If the 8 mm (height) carrier board connector is used then approximate overall height is 21 mm.

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2.4 Supply Voltage Standard Power

• 12V DC ± 5%

The dynamic range shall not exceed the static range.

12.60V

12.10V

12V

11.90V

11.40V

Absolute Maximum

Dynamic Range

Nominal Static Range

Absolute Minimum

2.4.1 Electrical Characteristics

Power supply pins on the module’s connectors limit the amount of input power. The following table provides an overview of the limitations for pinout Type 6 (dual connector, 440 pins).

Table 5 Electrical Characteristics

Power Rail Module Pin

Current Capability

(Amps)

VCC_12V 12

VCC_5V-SBY 2

VCC_RTC 0.5

Nominal

Input (Volts)

12

5

3

Input

Range

(Volts)

Derated

Input (Volts)

11.4-12.6 11.4

4.75-5.25 4.75

2.0-3.3

Max. Input Ripple

(10Hz to 20MHz)

(mV)

+/- 100

+/- 50

+/- 20

Max. Module Input

Power (w. derated input)

(Watts)

137

9

Assumed

Conversion

Efficiency

85%

Max. Load

Power

(Watts)

116

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2.4.2 Rise Time

The input voltages shall rise from 10% of nominal to 90% of nominal at a minimum slope of 250V/s. The smooth turn-on requires that during the 10% to 90% portion of the rise time, the slope of the turn-on waveform must be positive.

2.5 Power Consumption

The power consumption values were measured with the following setup:

• conga-TR4 module

• modified congatec carrier board

• conga-TR4 cooling solution

• Microsoft Windows ® 10 (64-bit)

Note

The SoC was stressed to its maximum workload with the AMD APU Validation Toolkit (AVT).

Table 6 Measurement Description

The power consumption values were recorded during the following system states:

System State Description

S0: Minimum value Lowest frequency mode (LFM) with minimum core voltage during desktop idle.

S0: Maximum value Highest frequency mode (HFM/Turbo Boost).

S0: Peak value

S3

S5

Highest current spike during the measurement of “S0: Maximum value”. This state shows the peak value during runtime.

COM is powered by VCC_5V_SBY.

COM is powered by VCC_5V_SBY.

Note

1. The fan and SATA drives were powered externally.

Comment

The CPU was stressed to its maximum frequency.

Consider this value when designing the system’s power supply to ensure that sufficient power is supplied during worst case scenarios.

2. All other peripherals except the LCD monitor were disconnected before measurement.

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2.6

The tables below provide additional information about the power consumption data for each of the conga-TR4 variants offered. The values are recorded at various operating modes.

Table 7 Power Consumption Values

Part

No.

041600

041601

041602

041603

041610

041620

041621

Memory Size H.W

Rev.

BIOS

Rev.

OS

(64-bit)

CPU

Variant Cores Clock Speed

(Turbo) in GHz

TR44R010 Windows 10 V1807B 4 3.35 (3.75) 2x2 GB DDR4-2400 B.1

2x2 GB DDR4-2400 B.1

2x2 GB DDR4-2400 B.1

TR44R010 Windows 10 V1756B


2x2 GB DDR4-2400 B.1


2x4 GB DDR4-2400 C.0


2

4

4

4

3.25 (3.6)

2.0 (3.6)

2.5 (3.4)

2.0 (3.6)

2x4 GB DDR4-2400 C.0

TR44R205 Windows 10 R1606G

2x4 GB DDR4-2400 C.0

TR44R205 Windows 10 R1505G

2

2

2.6 (3.5)

2.4 (3.3)

S0:

Current (Amp.) S0 @12V and S3/S5 @5V

Min

S0:

Max

S0:

Peak

S3 S5

0.35

4.25

6.43

0.16

0.08

0.34

0.37

0.35

0.42

0.38

0.37

4.08

2.17

2.18

2.29

2.22

2.09

7.02

3.29

2.58

3.47

2.57

2.19

0.16

0.16

0.16

0.17

0.16

0.16

0.08

0.08

0.08

0.08

0.08

0.08

Note

With fast input voltage rise time, the inrush current may exceed the measured peak current.

Supply Voltage Battery Power

Table 8 CMOS Battery Power Consumption

RTC @

-10 o C

20 o C

70 o C

Voltage Current

3V DC 2.25 µA

3V DC 2.41 µA

3V DC 3.08 µA

Note

Do not use the CMOS battery power consumption values listed above to calculate CMOS battery lifetime.

Measure the CMOS battery power consumption in your customer specific application in worst case conditions (for example, during high temperature and high battery voltage).

Consider also the self-discharge of the battery when calculating the lifetime of the CMOS battery. For more information, refer to application note AN9_RTC_Battery_Lifetime.pdf on congatec AG website at www.congatec.com/support/application-notes.

We recommend to always have a CMOS battery present when operating the conga-TR4.

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2.7 Environmental Specifications

Temperature (commercial variants) Operation: 0° to 60°C

Temperature (industrial variants) Operation: -40° to 85°C

Humidity Operation: 10% to 90%

Caution

Storage: -40° to +85°C

Storage: -40° to +85°C

Storage: 5% to 95%

The above operating temperatures must be strictly adhered to at all times. When using a congatec heatspreader, the maximum operating temperature refers to any measurable spot on the heatspreader’s surface.

Humidity specifications are for non-condensing conditions.

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3 Block Diagram

COM Express AB

Connector

220 pos eDP (optional)

VGA

LVDS (default) or eDP (optional)

HDA I/F

USB Port 0-4

USB Port 5-7

3x USB 2.0

eDP-LVDS

NXP PTN3460

SATA Port 0

SATA Port 2

SATA Port 1

SATA Port 3

SPI bus

SATA Gen3

SATA Gen3

SATA Gen3

SATA Gen3

LS

USB Hub

Microchip USB2514b

MUX opt.

LPC

GPIOs

FAN Control

SM Bus

I2C Bus

Serial Port 1-0 opt.

SW congatec

Board

Controller

DP0

USB 2.0

Port 0-4

USB 2.0

Port 5

SATA 0

SPI

ROM

SATA 1

SPI

TPM

2.0

SM Bus

I2C Bus

UART 0-1

PCIe Port 0-1

PCIe Port 2

PCIe Port 3

PCIe Port 4

PCIe Port 5

Ethernet opt.

opt.

GBE Intel i210

PCIe Port 0-1

PCIe Port 2

PCIe Port 5

(in R-Series)

PCIe Port 3

(N/A in R-Series)

(in R-Series)

PCIe x1

PCIe x1

PCIe x1

Dual Channel

DDR4 SODIMM up to 16GB

Dual Channel

DDR4 SODIMM up to 16GB

Embedded V-Series SOC

Integrated

Compute Unit

2MB Shared L2

Core #1

Core #3

AES SSE4.2

Core #2

Core #4

AVX

Memory high performance ECC low power

OpenGL 4.6

Graphics Unit

OpenCL 2.1

DirectX 12

Interfaces

DisplayPort HDMI/DVI

MPEG-4

H.265

Multimedia Features

WMV-9 VC-1 MPEG-2

H.264

MVC MJPEG

PCIe

SATA

Integrated I/O Interfaces

LPC Bus GPIOs

USB 2.0

USB 3.0

RSA

Platform Security

SHA AES TRNG

COM Express CD

Connector

220 pos

DP1

DP3

DDI 1

DDI 2

MUX

DP2

(N/A in R-Series)

DDI 3

(N/A in R-Series)

USB3.1 Gen 1 Port 3 USB-SS Port 2

USB 3.1 Gen 2 Port 1



(N/A in R-Series)

PEG x4

PEG x4

(N/A in R-Series)

PCIe

Port 4

USB-SS Port 0

USB-SS Port 1

USB-SS Port 3

(N/A in R-Series)

PEG Lane 0-3

PEG Lane 4-7

(N/A in R-Series)

PEG Lane 8-15

PCIe x1

PCIe Port 6

PCIe switch opt.

PCIe x1

(N/A in

R-Series)

PCIe Port 7

(N/A in R-Series)

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4 Cooling Solutions

congatec AG offers the cooling solutions listed in Table 9 for conga-TR4. The dimensions of the cooling solutions are shown in the sub-sections.

All measurements are in millimeters.

Table 9 Cooling Solution Variants

1

2

3

Cooling Solution Part No Description

HSP 041651 Heatspreader with 2.7 mm bore-hole standoffs.

041652 Heatspreader with M2.5 mm threaded standoffs.

CSP

CSA

041653

041654

048555

048556

Passive cooling with 2.7 mm bore-hole standoffs.

Passive cooling with M2.5 mm threaded standoffs.

Active cooling with 2.7 mm bore-hole standoffs.

Active cooling with M2.5 mm threaded standoffs.

Note

1. We recommend a maximum torque of 0.4 Nm for carrier board mounting screws and 0.5 Nm for module mounting screws.

2. The gap pad material used on congatec heatspreaders may contain silicon oil that can seep out over time depending on the environmental conditions it is subjected to. For more information about this subject, contact your local congatec sales representative and request the gap pad material manufacturer’s specification.

Caution

1. The congatec heatspreaders/cooling solutions are tested only within the commercial temperature range of 0° to 60°C. Therefore, if your application that features a congatec heatspreader/cooling solution operates outside this temperature range, ensure the correct operating temperature of the module is maintained at all times. This may require additional cooling components for your final application’s thermal solution.

2. For adequate heat dissipation, use the mounting holes on the cooling solution to attach it to the module. Apply thread-locking fluid on the screws if the cooling solution is used in a high shock and/or vibration environment. To prevent the standoff from stripping or crossthreading, use non-threaded carrier board standoffs to mount threaded cooling solutions.

3. For applications that require vertically-mounted cooling solution, use only coolers that secure the thermal stacks with fixing post. Without the fixing post feature, the thermal stacks may move.

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4.1 CSA Dimensions

Threaded standoff for threaded version or non-threaded standoff for borehole version

125

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4.2 CSP Dimensions


125

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4.3 Heatspreader Dimensions


117

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5 Connector Rows

The conga-TR4 is connected to the carrier board via two 220-pin connectors (COM Express Type 6 pinout). These connectors are broken down into four rows (rows A-B and C-D).

5.1 Primary Connector Rows A and B

The following subsystems can be found on the primary connector rows A and B.

5.1.1 Serial ATA™ (SATA)

The conga-TR4 offers two 6Gb/s SATA ports. A switch on the module routes them to the four ports of the COM Express connector. You can set the two active ports via BIOS setup.

5.1.2 USB

The conga-TR4 offers signals for eight USB 2.0 ports. The signals for USB 2.0 ports 0-4 are routed from the SoC. The signals for USB 2.0 ports

5-7 are routed from a USB hub on the module.

The USB 2.0 signals can be combined with USB SuperSpeed signals to create up to two USB 3.1 Gen 2 ports and two USB 3.1 Gen 1 ports (1x

in R-Series). For more information, see section 7.4 "USB Host Controller".

5.1.3 High Definition Audio (HDA)

The conga-TR4 offers signals for HDA and supports up to three external codecs. This interface supports multiple codec configurations on a single board as long as all codecs operate on the same voltage.

Note

COM Express modules only support up to three data inputs (HDA_SDIN[0:2]) as described in COM Express Specification 3.0. AC’97 audio codecs are not supported.

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5.1.4 Ethernet

The conga-TR4 offers signals for one Gigabit Ethernet (GbE) port via GbE PHY or the integrated Intel ® i210 controller (i211 available as assembly option). The ethernet interface consists of four pairs of low voltage differential pair signals designated from GBE0_MDI0± to GBE0_MDI3± plus control signals for link activity indicators. These signals can be used to connect to a 10/100/1000 BaseT RJ45 connector with integrated or external isolation magnetics on the carrier board.

Note

The GBE0_LINK# output is only active during a 100Mbit or 1Gbit connection. It is not active during a 10Mbit connection. This is a limitation of Ethernet controller since it only has 3 LED outputs - ACT#, LINK100# and LINK1000#.

The GBE0_LINK# signal is a logic AND of the GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TR4.

Network Booting (PXE) is not possible with D-Link Switch Model No. DGS-1008D.

5.1.5 LPC Bus

conga-TR4 offers the Low Pin Count (LPC) bus via the integrated controller hub. The LPC bus corresponds approximately to a serialized ISA bus yet with a significantly reduced number of signals. Due to the software compatibility to the ISA bus, I/O extensions such as additional serial ports can be easily implemented on an application specific baseboard using this bus. Many devices are available for this cost-efficient, lowspeed interface designed to support low bandwidth and legacy devices. The LPC host bus controller supports one master DMA devices. See

section 9 "System Resources" for more information about the LPC Bus.

5.1.6 I²C Bus

The I²C bus is implemented through the congatec board controller and is accessed through the congatec CGOS driver and API. The controller provides a fast mode multi-master I²C bus that has maximum I²C bandwidth.

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5.1.7 PCI Express™ (PCIe)

The conga-TR4 offers up to four PCIe Gen 3 ports (three in R-Series) and four PCIe Gen 2 ports as shown in the routing diagrams below:

AMD SoC V-Series FP5

Gen 3

Port 0

Gen 3

Port 1

Gen 3

Port 2

Gen 3

Port 3

PCIe

Gen 3

Port 4 x1 x1

Option conga-TR4

PCIe Switch x1 x1 x1 x1

COM Express Connector

x1 x1

Gen 3

Port 0

Gen 3

Port 1

Gen 3

Port 2

Gen 3

Port 3

Gen 2

Port 4

Gen 2

Port 5

Gen 2

Port 6

Gen 2

Port 7

GbE x1

PCIe Gen 3 x4/x2/x1

AMD SoC R-Series FP5

Gen 3

Port 0

Gen 3

Port 1

Gen 3

Port 5

PCIe

Gen 3

Port 4 x1

Gen 3

Port 0 x1

Option conga-TR4

PCIe Switch x1 x1 x1 x1


x1

Gen 3

Port 1

Gen 3

Port 2

Gen 2

Port 3

Gen 2

Port 4

Gen 2

Port 5

Gen 2

Port 6

GbE x1

5.1.8 LVDS

The conga-TR4 offers signals for LVDS by default. Optionally, the conga-TR4 can offer signals for eDP instead. The eDP to LVDS bridge (NXP

PTN3460) on the module processes the incoming DisplayPort (DP) stream, converts the DP protocol to LVDS protocol and transmits the processed stream in LVDS format.

The LVDS interface supports:

• Single or dual channel LVDS (color depths of 18 bpp or 24 bpp)

• VESA and JEIDA color mappings

• Resolution up to 1920x1200 @60 Hz in in dual LVDS bus mode (color depth 24 bpp)

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Note conga-TR4 supports just one display output in BIOS setup menu and during boot-up phase. The priority of the displays is LVDS, DD1, DDI3,

DDI2. This means that there is no graphic output in BIOS setup menu on DDI1, DDI2 and DDI3 when the LVDS display interface is enabled.

5.1.9 Optional eDP

The conga-TR4 offers signals for LVDS by default. Optionally, the conga-TR4 can offer signals for eDP instead.

The eDP interface supports:

• VESA eDP Standard version 1.4

• Resolution up to 3840x2160 @60 Hz

5.1.10 GPIO

The conga-TR4 offers general purpose inputs and outputs for custom system designs and can be controlled by the congatec Board Controller

(cBC).

5.1.11 UART

The conga-TR4 offers signals for two UART interfaces routed from the SoC by default. Optionally, the signals can be routed from the congatec

Board Controller (cBC) instead.

Two TTL compatible two wire ports are available on Type 6 COM Express modules. These pins are designated SER0_TX, SER0_RX, SER1_TX and SER1_RX. Data out of the module is on the _TX pins. Hardware handshaking and hardware flow control are not supported. The module asynchronous serial ports are intended for general purpose use and for use with debugging software that makes use of the “console redirect” features available in many operating systems.

The UART controllers integrated in the cBC support up to 1MBit/s and can operate in low-speed, full-speed and high-speed modes. The UART interfaces are routed to the AB connector and require the congatec driver to function.

Note

The UART interfaces currently do not support legacy COM port emulation.

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5.1.12 Power Control

PWR_OK

Power OK from main power supply or carrier board voltage regulator circuitry. A high value indicates that the power is good and the module can start its onboard power sequencing. The PWR_OK is a 3.3V signal according to the COM Express Specification. The use of this input is optional.

Carrier board hardware must drive this signal low until all power rails and clocks are stable. Releasing PWR_OK too early or not driving it low at all can cause numerous boot up problems. It is a good design practice to delay the PWR_OK signal a little (typically 100ms) after all carrier board power rails are up, to ensure a stable system. Although the PWR_OK input is not mandatory for the onboard power-up sequencing, it is strongly recommended that the carrier board hardware drives the signal low until it is safe to let the module boot-up.

A sample screenshot is shown below:

Note

1. The module is kept in reset as long as PWR_OK is driven by carrier board hardware.

2. PWR_OK must be kept low before rising to 12V.

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The conga-TR4 PWR_OK input circuitry is implemented as shown below:

+V12.0_S0

R1%47kS02

PWR_OK

R1%20k0S02

R1%1k00S02

TBC847

R1%10kS02

R1%4k75S02

To Module Power Logic

The voltage divider ensures that the input complies with 3.3V CMOS characteristic and also makes it possible to use the module on carrier board designs that do not drive the PWR_OK signal. Although the PWR_OK input is not mandatory for the onboard power-up sequencing, it is strongly recommended that the carrier board hardware drives the signal low until it is safe to let the module boot-up.

When considering the above shown voltage divider circuitry and the transistor stage, the voltage measured at the PWR_OK input pin may be only around 0.8V when the 12V is applied to the module. Actively driving PWR_OK high is compliant to the COM Express specification but this can cause back driving. Therefore, congatec recommends driving the PWR_OK low to keep the module in reset and tri-state PWR_OK when the carrier board hardware is ready to boot.

The three typical usage scenarios for a carrier board design are:

• Connect PWR_OK to the “power good” signal of an ATX type power supply.

• Connect PWR_OK to the last voltage regulator in the chain on the carrier board.

• Simply pull PWR_OK with a 1k resistor to the carrier board 3.3V power rail.

With this solution, it must be ensured that by the time the 3.3V is up, all carrier board hardware is fully powered and all clocks are stable.

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The conga-TR4 supports the controlling of ATX-style power supplies. If you do not use an ATX power supply, do not connect the conga-TR4 pins SUS_S3/PS_ON, 5V_SB, and PWRBTN#.

SUS_S3#/PS_ON#

The SUS_S3#/PS_ON# (pin A15 on the A-B connector) signal is an active-low output that can be used to turn on the main outputs of an ATXstyle power supply. In order to accomplish this the signal must be inverted with an inverter/transistor that is supplied by standby voltage and is located on the carrier board.

PWRBTN#

When using ATX-style power supplies PWRBTN# (pin B12 on the A-B connector) is used to connect to a momentary-contact, active-low debounced push-button input while the other terminal on the push-button must be connected to ground. This signal is internally pulled up to 3V_SB using a 10k resistor. When PWRBTN# is asserted it indicates that an operator wants to turn the power on or off. The response to this signal from the system may vary as a result of modifications made in BIOS settings or by system software.

Power Supply Implementation Guidelines

12 volt input power is the sole operational power source for the conga-TR4. The remaining necessary voltages are internally generated on the module using onboard voltage regulators. A carrier board designer should be aware of the following important information when designing a power supply for a conga-TR4 application:

• It has also been noticed that on some occasions, problems occur when using a 12V power supply that produces non monotonic voltage when powered up. The problem is that some internal circuits on the module (e.g. clock-generator chips) will generate their own reset signals when the supply voltage exceeds a certain voltage threshold. A voltage dip after passing this threshold may lead to these circuits becoming confused resulting in a malfunction. It must be mentioned that this problem is quite rare but has been observed in some mobile power supply applications. The best way to ensure that this problem is not encountered is to observe the power supply rise waveform through the use of an oscilloscope to determine if the rise is indeed monotonic and does not have any dips. This should be done during the power supply qualification phase therefore ensuring that the above mentioned problem doesn’t arise in the application. For more information, see the “Power Supply Design Guide for Desktop Platform Form Factors” document at www.intel.com.

5.1.13 Power Management

ACPI 5.0 compliant with battery support. Also supports Suspend to RAM (S3).

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5.2 Secondary Connector Rows C and D

The following subsystems can be found on the secondary connector rows C and D.

5.2.1 PCI Express™ Graphics (PEG)

The conga-TR4 offers signals for a PEG x8 interface (x4 in R-Series). The default configuration of the PEG interface is one x8 link. The interface can be configured as a two x4 link in the BIOS setup menu.

5.2.2 Digital Display Interface (DDI)

The conga-TR4 offers signals for up to three DDI (two in R-Series):

• DDI1 is a native port

•

DDI2 is multiplexed with a USB 3.1 Gen 2 port. See section section 7.4 "USB Host Controller" for more information.

•

DDI3 (N/A in R-Series) is multiplexed with a USB 3.1 Gen 2 port. See section section 7.4 "USB Host Controller" for more information.

Each interface can be configured as DP++, HDMI or DVI.

Any display combination is supported.

DP supports:

• VESA DisplayPort Standard version 1.4

• Resolution up to 3840x2160 @ 120 Hz (HBR3, 8.1 GT/s; requires re-timer)

HDMI/DVI supports:

• HDMI Standard version 2.0b

• Resolution up to 4096x2160 @ 60 Hz (6 Gb/s; requires re-timer)

• Single-link DVI with resolution up to 1920x1200 @ 60 Hz

Note

To support HDMI/DVI, an external level shifter (e.g PTN3360D) should be implemented on the user’s carrier board.

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6 Additional Features

6.1 congatec Board Controller (cBC)

The conga-TR4 is equipped with a Texas Instruments Tiva™ TM4E1231H6ZRB microcontroller. This onboard microcontroller plays an important role for most of the congatec embedded/industrial PC features. It fully isolates some of the embedded features, such as system monitoring or the I²C bus from the x86 core architecture, which results in higher embedded feature performance and more reliability, even when the x86 processor is in a low power mode. It also ensures that the congatec embedded feature set is fully compatible amongst all congatec modules.

6.1.1 Board Information

The cBC provides a rich data-set of manufacturing and board information such as serial number, EAN number, hardware and firmware revisions, and so on. It also keeps track of dynamically changing data like runtime meter and boot counter.

6.1.2 Fan Control

The conga-TR4 has additional signals and functions to further improve system management. One of these signals is an output signal called

FAN_PWMOUT that allows system fan control using a PWM (Pulse Width Modulation) output. Additionally, there is an input signal called

FAN_TACHOIN that provides the ability to monitor the system’s fan RPMs (revolutions per minute). This signal must receive two pulses per revolution in order to produce an accurate reading. For this reason, a two pulse per revolution fan or similar hardware solution is recommended.

Note

A four wire fan must be used to generate the correct speed readout.

The congatec COM Express Type 6 and Type 10 modules use a Push-Pull output for the fan_pwm signal instead of the open drain output specified in the COM Express specification. Although this does not comply with the COM Express specification 2.0, the benefits are obvious.

The Push-Pull output optimizes the power consumed by the fan_pwm signal without functional change.

6.1.3 Power Loss Control

The cBC has full control of the power-up of the module and can be used to specify the behavior of the system after an AC power loss condition.

Supported modes are “Always On”, “Remain Off” and “Last State”.

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6.1.4 Watchdog

The conga-TR4 is equipped with a multi stage watchdog solution that is triggered by software. The COM Express™ Specification does not provide support for external hardware triggering of the Watchdog, which means the conga-TR4 does not support external hardware triggering.

For more information about the Watchdog feature, see the BIOS setup description in section 10 of this document and application note

AN3_Watchdog.pdf on the congatec AG website at www.congatec.com.

Note

The conga-TR4 module does not support the watchdog NMI mode.

6.2 OEM BIOS Customization

The conga-TR4 is equipped with congatec Embedded BIOS, which is based on American Megatrends Inc. Aptio UEFI firmware. The congatec

Embedded BIOS allows system designers to modify the BIOS. For more information about customizing the congatec Embedded BIOS, refer to the congatec System Utility user’s guide CGUTLm1x.pdf on the congatec website at www.congatec.com or contact technical support.

The customization features supported are described in the following sections.

6.2.1 OEM Default Settings

This feature allows system designers to create and store their own BIOS default configuration. Customized BIOS development by congatec for

OEM default settings is no longer necessary because customers can easily perform this configuration by themselves using the congatec system utility CGUTIL. See congatec application note AN8_Create_OEM_Default_Map.pdf on the congatec website for details on how to add OEM default settings to the congatec Embedded BIOS.

6.2.2 OEM Boot Logo

This feature allows system designers to replace the standard text output displayed during POST with their own BIOS boot logo. Customized

BIOS development by congatec for OEM Boot Logo is no longer necessary because customers can easily perform this configuration by themselves using the congatec system utility CGUTIL. See congatec application note AN8_Create_And_Add_Bootlogo.pdf on the congatec website for details on how to add OEM boot logo to the congatec Embedded BIOS.

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6.2.3 OEM POST Logo

This feature allows system designers to replace the congatec POST logo displayed in the upper left corner of the screen during BIOS POST with their own BIOS POST logo. Use the congatec system utility CGUTIL 1.5.4 or later to replace/add the OEM POST logo.

6.2.4 OEM BIOS Code/Data

With the congatec embedded BIOS it is possible for system designers to add their own code to the BIOS POST process. The congatec

Embedded BIOS first calls the OEM code before handing over control to the OS loader.

Except for custom specific code, this feature can also be used to support Win XP SLP installation, Window 7 SLIC table (OA2.0), Windows 8 OEM activation (OA3.0), verb tables for HDA codecs, PCI/PCIe opROMs, bootloaders, rare graphic modes and Super I/O controller initialization.

Note

The OEM BIOS code of the new UEFI based firmware is only called when the CSM (Compatibility Support Module) is enabled in the BIOS setup menu. Contact congatec technical support for more information on how to add OEM code.

6.2.5 OEM DXE Driver

This feature allows designers to add their own UEFI DXE driver to the congatec embedded BIOS. Contact congatec technical support for more information on how to add an OEM DXE driver.

6.3 congatec Battery Management Interface

In order to facilitate the development of battery powered mobile systems based on embedded modules, congatec AG has defined an interface for the exchange of data between a CPU module (using an ACPI operating system) and a Smart Battery system. A system developed according to the congatec Battery Management Interface Specification can provide the battery management functions supported by an ACPI capable operating system (e.g. charge state of the battery, information about the battery, alarms/events for certain battery states, ...) without the need for any additional modifications to the system BIOS.

In addtion to the ACPI-Compliant Control Method Battery mentioned above, the latest versions of the conga-TR4 BIOS and board controller firmware also support LTC1760 battery manager from Linear Technology and a battery only solution (no charger). All three battery solutions are supported on the I2C bus and the SMBus. This gives the system designer more flexibility when choosing the appropriate battery sub-system.

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6.4

6.5

6.6

For more information about this subject, visit the congatec website and view the following documents:

• congatec Battery Management Interface Specification

• Battery System Design Guide

• conga-SBM 3 User’s Guide

API Support (CGOS)

In order to benefit from the above mentioned non-industry standard feature set, congatec provides an API that allows application software developers to easily integrate all these features into their code. The CGOS API (congatec Operating System Application Programming

Interface) is the congatec proprietary API that is available for all commonly used Operating Systems such as Win32, Win64, Win CE, Linux.

The architecture of the CGOS API driver provides the ability to write application software that runs unmodified on all congatec CPU modules.

All the hardware related code is contained within the congatec embedded BIOS on the module. See section 1.1 of the CGOS API software developers guide, which is available on the congatec website.

Security Features

The conga-TR4 offers a discrete TPM 2.0 (Infineon SLB9665). This TPM includes coprocessors to calculate efficient hash and RSA algorithms with key lengths up to 2048 bits as well as a real random number generator. Security sensitive applications like gaming and e-commerce will benefit also with improved authentication, integrity and confidence levels. The conga-TR4 also offers AMD Secure Processor™.

Suspend to Ram

The Suspend to RAM feature is available on the conga-TR4.

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7 conga Tech Notes

The conga-TR4 has some technological features that require additional explanation. The following section will give the reader a better understanding of some of these features. This information will also help to gain a better understanding of the information found in the System

Resources section of this user’s guide as well as some of the setup nodes found in the BIOS Setup Program description section.

7.1 AMD Processor Features

Zen microarchitecture:

• Fetch Four x86 instructions

• TLBs (Translation Lookaside Buffers) in Branch Prediction pipe

• Micro-op Cache 2K instructions

• 4 Integer Execution units

• 2 Floating Point units x 128 Fmacs

• 2 Load/Store units

• 64K, 4-way L1 Instruction cache

• 32K, 8-way L1 Data cache

• 512K L2 cache

For more information about AMD Technology, visit http://www.amd.com.

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7.2

7.3

Thermal Management

ACPI is responsible for allowing the operating system to play an important part in the system’s thermal management. This results in the operating system having the ability to take control of the operating environment by implementing cooling decisions according to the demands put on the CPU by the application.

The conga-TR4 ACPI thermal solution offers three different cooling policies:

• Passive Cooling

When the temperature in the thermal zone must be reduced, the operating system can decrease the power consumption of the processor by throttling the processor clock. One of the advantages of this cooling policy is that passive cooling devices (in this case the processor) do not produce any noise. Use the “passive cooling trip point” setup node in the BIOS setup program to determine the temperature threshold that the operating system will use to start or stop the passive cooling procedure.

• Active Cooling

During this cooling policy the operating system is turning the fan on/off. Although active cooling devices consume power and produce noise, they also have the ability to cool the thermal zone without having to reduce the overall system performance. Use the “active cooling trip point” setup node in the BIOS setup program to determine the temperature threshold that the operating system will use to start the active cooling device. It is stopped again when the temperature goes below the threshold (5°C hysteresis).

• Critical Trip Point

If the temperature in the thermal zone reaches a critical point then the operating system will perform a system shut down in an orderly fashion in order to ensure that there is no damage done to the system as result of high temperatures. Use the “critical trip point” setup node in the

BIOS setup program to determine the temperature threshold that the operating system will use to shut down the system

Note

The end user must determine the cooling preferences for the system by using the setup nodes in the BIOS setup program to establish the appropriate trip points. If passive cooling is activated and the processor temperature is above the trip point the processor clock is throttled.

See section 12 of the ACPI Specification 2.0 C for more information about passive cooling.

ACPI Suspend Modes and Resume Events

conga-TR4 supports S3 (STR= Suspend to RAM).

S4 (Suspend to Disk) is not supported by the BIOS (S4_BIOS) but it is supported by most operating systems (S4_OS= Hibernate).

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This table lists the “Wake Events” that resume the system from S3 unless otherwise stated in the “Conditions/Remarks” column:

Table 10 Wake Events

Wake Event

Power Button

Onboard LAN Event

Conditions/Remarks

Wakes unconditionally from S3-S5.

Device driver must be configured for Wake On LAN support.

SMBALERT#

PCI Express WAKE#

WAKE#

PME#



Wakes uncondionally from S3.

Activate the wake up capabilities of a PCI device using Windows Device Manager configuration options for this device OR set Resume On

PME# to Enabled in the Power setup menu.

USB Mouse/Keyboard Event When Standby mode is set to S3, USB hardware must be powered by standby power source.

Set USB Device Wakeup from S3/S4 to ENABLED in the ACPI setup menu (if setup node is available in BIOS setup program).

In Device Manager look for the keyboard/mouse devices. Go to the Power Management tab and check ‘Allow this device to bring the computer out of standby’.

RTC Alarm Activate and configure Resume On RTC Alarm in the Power setup menu. Only available in S5.

Watchdog Power Button Event Wakes unconditionally from S3-S5.

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7.4 USB Host Controller

The conga-TR4 offers signals for eight USB 2.0 ports. The signals for USB 2.0 ports 0-4 are routed from the SoC. The signals for USB 2.0 ports

5-7 are routed from a USB hub on the module. The USB 2.0 signals can be combined with USB SuperSpeed signals to create up to two

USB 3.1 Gen 2 ports and two USB 3.1 Gen 1 ports (Only one Gen 1 port in R-Series). One USB port is shared with the DDI3 port (N/A in R-Series).

AMD SoC FP5

USB 2.0

Port 0

SS-0

Gen 2

USB 2.0

Port 1

USB Controller 0

SS-1

Gen 2

USB 2.0

Port 2

SS-2

Gen 2

USB 2.0

Port 3

SS-3

Gen 1

USB Controller 1

SS-0

Gen 1* 1

USB 2.0

Port 0

USB 2.0

Port 1

USB 2.0

Port 4

DDI2

MUX

DP3 DP2* 1

MUX

MUX USB Hub

USB 2.0

Port 0

SS-1

Gen 2


USB 2.0

Port 1

SS-2

Gen 2

USB 2.0

Port 2

SS-3

Gen 1

DDI3* 1 SS-4

Gen 1* 1

USB 2.0

Port 3

USB 2.0

Port 5

USB 2.0

Port 6

USB 2.0

Port 7

USB 3.1 Gen 2

Port 0* 2

USB 3.1 Gen 2

Port 1* 2

USB 3.1 Gen 1

Port 2

USB 3.1 Gen 1

Port 3* 1

Note

*1 Not available in the R-Series.

*2 The USB ports are configured in the BIOS setup menu to operate in Gen 1 mode. Before changing the setting to Gen 2, ensure the carrier board is designed for Gen 2 operation. For USB 3.1 Gen 2 design considerations, contact congatec technical support.

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8 Signal Descriptions and Pinout Tables

The following section describes the signals found on COM Express™ Type 6 connectors used for congatec AG modules. The pinout of the modules complies with COM Express Type 6 Rev. 2.1.

Table 2 describes the terminology used in this section for the Signal Description tables. The PU/PD column indicates if a COM Express™ module pull-up or pull-down resistor has been used, if the field entry area in this column for the signal is empty, then no pull-up or pull-down resistor has been implemented by congatec.

The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When

“#” is not present, the signal is asserted when at a high voltage level.

Table 11 Signal Tables Terminology Descriptions

I

Term

O

P

DDC

PCIE

PEG

SATA

REF

PDS

OC

OD

PU

PD

I/O 3.3V

I/O 5V

I/O 3.3VSB

I 3.3V

I 5V

O 3.3V

O 5V

Description

Input Pin

Output Pin

Open Collector

Open Drain

Implemented pull-up resistor

Implemented pull-down resistor

Bi-directional signal 3.3V tolerant

Bi-directional signal 5V tolerant

Bi-directional signal 3.3V tolerant active in standby state

Input 3.3V tolerant

Input 5V tolerant

Output 3.3V signal level

Output 5V signal level

Power Input

Display Data Channel

In compliance with PCI Express Base Specification

PCI Express Graphics

In compliance with Serial ATA specification, Revision 3.0.

Reference voltage output. May be sourced from a module power plane.

Pull-down strap. A module output pin that is either tied to GND or is not connected.

Used to signal module capabilities (pinout type) to the Carrier Board.

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8.1 A-B Connector Signal Descriptions

Table 12 Connector A-B Pinout

Pin Row A

A1 GND (FIXED)

A2 GBE0_MDI3-

A3 GBE0_MDI3+

A4 GBE0_LINK100#

A5 GBE0_LINK1000#

A6 GBE0_MDI2-

A7 GBE0_MDI2+

A8 GBE0_LINK#

A9 GBE0_MDI1-

A10 GBE0_MDI1+

A11 GND (FIXED)

A12 GBE0_MDI0-

A13 GBE0_MDI0+

A14 GBE0_CTREF (*)

A15 SUS_S3#

A16 SATA0_TX+

A17 SATA0_TX-

A18 SUS_S4#

A19 SATA0_RX+

A20 SATA0_RX-

A21 GND (FIXED)

A22 SATA2_TX+

A23 SATA2_TX-

A24 SUS_S5#

A25 SATA2_RX+

A26 SATA2_RX-

A27 BATLOW#

A28 (S)ATA_ACT#

A29 HDA_SYNC

A30 HDA_RST#

A31 GND (FIXED)

A32 HDA_BITCLK

A33 HDA_SDOUT

A34 BIOS_DIS0#

A35 THRMTRIP#

A36 USB6-

Pin Row B

B1 GND (FIXED)

B2 GBE0_ACT#

B3 LPC_FRAME#

B4 LPC_AD0

B5 LPC_AD1

B6 LPC_AD2

B7 LPC_AD3

B8 LPC_DRQ0#

B9 LPC_DRQ1 (*)

B10 LPC_CLK

B11 GND (FIXED)

B12 PWRBTN#

B13 SMB_CK

B14 SMB_DAT

B15 SMB_ALERT#

B16 SATA1_TX+

B17 SATA1_TX-

B18 SUS_STAT#

B19 SATA1_RX+

B20 SATA1_RX-

B21 GND (FIXED)

B22 SATA3_TX+

B23 SATA3_TX-

B24 PWR_OK

B25 SATA3_RX+

B26 SATA3_RX-

B27 WDT

B28 HDA_SDIN2

B29 HDA_SDIN1

B30 HDA_SDIN0

B31 GND (FIXED)

B32 SPKR

B33 I2C_CK

B34 I2C_DAT

B35 THRM#

B36 USB7-

Pin Row A

A56 PCIE_TX4-

A57 GND

Pin Row B

B56 PCIE_RX4-

B57 GPO2

A58 PCIE_TX3+

A59 PCIE_TX3-

A60 GND (FIXED)

A61 PCIE_TX2+

A62 PCIE_TX2-

A63 GPI1

A64 PCIE_TX1+

A65 PCIE_TX1-

A66 GND

B58 PCIE_RX3+

B59 PCIE_RX3-

B60 GND (FIXED)

B61 PCIE_RX2+

B62 PCIE_RX2-

B63 GPO3

B64 PCIE_RX1+

B65 PCIE_RX1-

B66 WAKE0#

A67 GPI2

A68 PCIE_TX0+

A69 PCIE_TX0-

A70 GND (FIXED)

A71 eDP_TX2+ / LVDS_A0+

A72 eDP_TX2- / LVDS_A0-





A77 eDP / LVDS_VDD_EN

B67 WAKE1#

B68 PCIE_RX0+

B69 PCIE_RX0-

B70 GND (FIXED)

B71 LVDS_B0+

B72 LVDS_B0-

B73 LVDS_B1+

B74 LVDS_B1-

B75 LVDS_B2+

B76 LVDS_B2-

B77 LVDS_B3+

A78 LVDS_A3+

A79 LVDS_A3-

B78 LVDS_B3-

B79 eDP / LVDS_BKLT_EN

A80 GND (FIXED) B80 GND (FIXED)

A81 eDP_TX3+ / LVDS_A_CK+ B81 LVDS_B_CK+

A82 eDP_TX3- / LVDS_A_CKB82 LVDS_B_CK-

A83 eDP_ AUX+ / LVDS_I2C_CK B83 eDP / LVDS_BKLT_CTRL

A84 eDP_AUX- / LVDS_I2C_DAT B84 VCC_5V_SBY

A85 GPI3 B85 VCC_5V_SBY

A86 RSVD

A87 eDP_HPD

A88 PCIE0_CK_REF+

B86 VCC_5V_SBY

B87 VCC_5V_SBY

B88 BIOS_DIS1#

A89 PCIE0_CK_REF-

A90 GND (FIXED)

A91 SPI_POWER

B89 VGA_RED (*)

B90 GND (FIXED)

B91 VGA_GRN (*)

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Pin Row A

A37 USB6+

A38 USB_6_7_OC#

A39 USB4-

A40 USB4+

A41 GND (FIXED)

A42 USB2-

A43 USB2+

A44 USB_2_3_OC#

A45 USB0-

A46 USB0+

A47 VCC_RTC

A48 RSVD

A49 GBE0_SDP

A50 LPC_SERIRQ

A51 GND (FIXED)

A52 PCIE_TX5+

A53 PCIE_TX5-

A54 GPI0

A55 PCIE_TX4+

Note

Pin Row B

B37 USB7+

Pin Row A

A92 SPI_MISO

B38 USB_4_5_OC#

B39 USB5-

B40 USB5+

B41 GND (FIXED)

B42 USB3-

B43 USB3+

B44 USB_0_1_OC#

A93 GPO0

A94 SPI_CLK

A95 SPI_MOSI

A96 TPM_PP

A97 TYPE10#

A98 SER0_TX

A99 SER0_RX

B45 USB1-

B46 USB1+

A100 GND (FIXED)

A101 SER1_TX

B47 ESPI EN#(*) A102 SER1_RX

B48 USB0_HOST_PRSNT(*) A103 LID#

B49 SYS_RESET#

B50 CB_RESET#

B51 GND (FIXED)

B52 PCIE_RX5+

B53 PCIE_RX5-

B54 GPO1

B55 PCIE_RX4+

A104 VCC_12V

A105 VCC_12V

A106 VCC_12V

A107 VCC_12V

A108 VCC_12V

A109 VCC_12V

A110 GND (FIXED)

The signals marked with an asterisk symbol (*) are not supported on the conga-TR4.

Pin Row B

B92 VGA_BLU (*)

B93 VGA_HSYNC (*)

B94 VGA_VSYNC (*)

B95 VGA_I2C_CK (*)

B96 VGA_I2C_DAT (*)

B97 SPI_CS#

B98 RSVD

B99 RSVD

B100 GND (FIXED)

B101 FAN_PWMOUT

B102 FAN_TACHIN

B103 SLEEP#

B104 VCC_12V

B105 VCC_12V

B106 VCC_12V

B107 VCC_12V

B108 VCC_12V

B109 VCC_12V

B110 GND (FIXED)

Table 13 High Definition Audio Link Signal Descriptions

Signal

HDA_RST#

HDA_SYNC

HDA_BITCLK

HDA_SDOUT

HDA_SDIN[2:0]

Pin #

A30

Description

Reset output to CODEC, active low.

I/O

O 3.3VSB

PU/PD Comment

AC’97 codecs are not supported.

A29

A32

Sample-synchronization signal to the CODEC(s).

O 3.3VSB

Serial data clock generated by the external CODEC(s).

O 3.3VSB

A33 Serial TDM data output to the CODEC.

B28-B30 Serial TDM data inputs from up to 3 CODECs.

O 3.3VSB




I 3.3VSB

PD 47k AC’97 codecs are not supported.

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Table 14 LPC Signal Descriptions

Signal

LPC_AD[0:3]

LPC_FRAME#

LPC_CLK

LPC_DRQ0#

LPC_DRQ1#

LPC_SERIRQ

SUS_STAT#

ESPI_EN#

BIOS_DIS0

BIOS_DIS1

Pin # Description

B4-B7 LPC Mode: LPC multiplexed address, command and data bus

B3

B10

B8

B8

A50

B18

B47

A34

B88

LPC Mode: LPC Frame indicates the start of a LPC cycle.

LPC Mode: LPC clock output, 33MHz

LPC Mode: LPC serial DMA request

LPC Mode: LPC serial DMA request

LPC Mode: LPC serial interrupt

LPC Mode: SUS_STAT# indicates imminent suspend operation. It is used to notify LPC devices that a low power state will be entered soon. LPC devices may need to preserve memory or isolate outputs during the low power state.

This signal is used by the Carrier to indicate the operating mode of the LPC/eSPI bus.

If left unconnected on the carrier, LPC mode (default) is selected. If pulled to GND on the carrier, eSPI mode is selected. This signal is pulled to a logic high on the module through a resistor. The Carrier should only float this line or pull it low.

Selection strap to determine the BIOS boot device. The Carrier should only float these or pull them low. Refer to table 4.13 of the COM Express Module Base

Specification for strapping options of BIOS disable signals.

I

I

I/O

I/O 3.3V

O 3.3V

O 3.3V

I 3.3V

I 3.3V

I/O OD 3.3V

O 3.3V

I 3.3V

PU/PD Comment

PU 10K 3.3V

PU 10K 3.3V

Not supported

Table 15 Serial ATA Signal Descriptions

Signal

SATA0_RX+

SATA0_RX-

Pin # Description

A19

A20

Serial ATA channel 0, Receive Input differential pair.

I/O

I SATA

SATA0_TX+

SATA0_TX-

SATA1_RX+

SATA1_RX-

SATA1_TX+

SATA1_TX-

SATA2_RX+

SATA2_RX-

SATA2_TX+

SATA2_TX-

SATA3_RX+

SATA3_RX-

A16

A17

B19

B20

B16

B17

A25

A26

A22

A23

B25

B26

Serial ATA channel 0, Transmit Output differential pair.






O SATA

I SATA

O SATA

I SATA

O SATA

I SATA

SATA3_TX+

SATA3_TX-

B22

B23


O SATA

(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low.

O 3.3V

Table 16 USB 2.0 Signal Descriptions

PU/PD Comment

Supports Serial ATA specification, Revision 3.0.

Only two SATA ports can be set to active via BIOS setup.















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Signal

USB0+

USB0-

USB1+

USB1-

USB2+

USB2-

USB3+

USB3-

USB4+

USB4-

USB5+

USB5-

Pin # Description

A46 USB Port 0, data + or D+

A45 USB Port 0, data - or D-

B46 USB Port 1, data + or D+

B45 USB Port 1, data - or D-









USB6+

USB6-

USB7+




USB7B36 USB Port 7, data - or D-

USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

PU/PD Comment

USB 2.0 compliant. Backwards compatible to USB 1.1

I 3.3VSB PU 10k

3.3VSB










USB 2.0 compliant. Backwards compatible to USB 1.1.

Routed from a USB hub on the module.











Do not pull this line high on the carrier board.

I 3.3VSB PU 10k

3.3VSB


I 3.3VSB PU 10k

3.3VSB


I 3.3VSB PU 10k

3.3VSB


44/65

Signal

PCIE_RX0+

PCIE_RX0-

PCIE_TX0+

PCIE_TX0-

PCIE_RX1+

PCIE_RX1-

PCIE_TX1+

PCIE_TX1-

PCIE_RX2+

PCIE_RX2-

PCIE_TX2+

PCIE_TX2-

PCIE_RX3+

PCIE_RX3-

PCIE_TX3+

PCIE_TX3-

PCIE_RX4+

PCIE_RX4-

PCIE_TX4+

PCIE_TX4-

PCIE_RX5+

PCIE_RX5-

PCIE_TX5+

PCIE_TX5-

PCIE_CLK_REF+

PCIE_CLK_REF-

Table 17 PCI Express Signal Descriptions (general purpose)

Pin # Description

B68

B69

PCI Express channel 0, Receive Input differential pair.

I/O

I PCIE

PCI Express channel 0, Transmit Output differential pair. O PCIE

B52

B53

A52

A53

A88

A89

A58

A59

B55

B56

A55

A56

B61

B62

A61

A62

B58

B59

A68

A69

B64

B65

A64

A65






PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.

I PCIE


I PCIE


I PCIE


I PCIE


I PCIE


O PCIE

PU/PD Comment

Supports PCI Express Base Specification, Revision 3.0












A PCI Express Gen2/3 compliant clock buffer chip must be used on the carrier board if more than one PCI Express device is designed in.

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Table 18 Gigabit Ethernet Signal Descriptions

Gigabit Ethernet Pin # Description

GBE0_MDI0+

GBE0_MDI0-

GBE0_MDI1+

GBE0_MDI1-

GBE0_MDI2+

GBE0_MDI2-

GBE0_MDI3+

GBE0_MDI3-

A13

A12

A10

A9

A7

A6

A3

A2

Gigabit Ethernet Controller 0: Media Dependent Interface Differential

Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:

MDI[0]+/-

MDI[1]+/-

MDI[2]+/-

1000

B1_DA+/-

B1_DB+/-

B1_DC+/-

100

TX+/-

RX+/-

10

TX+/-

RX+/-

GBE0_ACT#

GBE0_LINK#

GBE0_LINK100#

GBE0_LINK1000#

GBE0_CTREF

I/O

I/O

Analog

B2

A8

A4

MDI[3]+/B1_DD+/-

Gigabit Ethernet Controller 0 activity indicator, active low.

Gigabit Ethernet Controller 0 link indicator, active low.

O 3.3VSB

O 3.3VSB

Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low. O 3.3VSB

A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low. O 3.3VSB

A14 Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap. The reference voltage is determined by the requirements of the module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the module. In the case in which the reference is shorted to ground, the current shall be limited to 250mA or less.

PU/PD Comment

Twisted pair signals for external transformer.

Not connected

Note

The GBE0_LINK# output is only active during a 100Mbit or 1Gbit connection. It is not active during a 10Mbit connection. This is a limitation of Ethernet controller since it only has 3 LED outputs, ACT#, LINK100# and LINK1000#. The GBE0_LINK# signal is a logic AND of the

GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TR4 module.

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Table 19 LVDS Signal Descriptions

Signal

LVDS_A0+

LVDS_A0-

LVDS_A1+

LVDS_A1-

LVDS_A2+

LVDS_A2-

LVDS_A3+

LVDS_A3-

LVDS_A_CK+

LVDS_A_CK-

LVDS_B0+

LVDS_B0-

LVDS_B1+

LVDS_B1-

LVDS_B2+

LVDS_B2-

LVDS_B3+

LVDS_B3-

LVDS_B_CK+

LVDS_B_CK-

LVDS_VDD_EN

LVDS_BKLT_EN

LVDS_BKLT_CTRL

LVDS_I2C_CK

LVDS_I2C_DAT

A81

A82

B71

B72

B73

B74

B75

B76

B77

B78

B81

B82

A77

B79

B83

A83

A84

Pin # Description

A71

A72

A73

A74

A75

A76

A78

A79

LVDS Channel A differential pairs

LVDS Channel A differential clock

LVDS Channel B differential pairs

LVDS Channel B differential clock

I/O

O LVDS

O LVDS

O LVDS

O LVDS

PU/PD

LVDS panel power enable

LVDS panel backlight enable

O 3.3V

O 3.3V

PD 10K

PD 10K

LVDS panel backlight brightness control O 3.3V

DDC lines used for flat panel detection and control.

OD 3.3V

PU 2.2K 3.3V

DDC lines used for flat panel detection and control.

I/OD 3.3V PU 2.2K 3.3V

Comment

Table 20 UART Interface Signal Descriptions

Signal

SER0_TX

SER1_TX

SER0_RX

SER1_RX

Pin #

A98

A101

A99

A102

Description

General purpose serial port transmitter

General purpose serial port transmitter

General purpose serial port receiver

General purpose serial port receiver

I/O

O 3.3V

O 3.3V

I 3.3V

I 3.3V

PU/PD

PU 47K 3.3V

PU 47K 3.3V

Comment

Signal is driven to logic 1 only. External PD is required.


47/65

Table 21 SPI BIOS Flash Interface Signal Descriptions

Signal

SPI_CS#

SPI_MISO

Pin # Description

B97 Chip select for Carrier Board SPI BIOS Flash.

A92 Data in to module from carrier board SPI BIOS flash.

SPI_MOSI

SPI_CLK

A95

A94

SPI_POWER A91

BIOS_DIS0# A34

BIOS_DIS1# B88

Data out from module to carrier board SPI BIOS flash.

Clock from module to carrier board SPI BIOS flash.

Power source for carrier board SPI BIOS flash. SPI_POWER shall be used to power SPI BIOS flash on the carrier only.

Selection strap to determine the BIOS boot device.

Selection strap to determine the BIOS boot device.

I/O

O 3.3VSB

I 3.3VSB

O 3.3VSB

O 3.3VSB

P 3.3VSB

PU/PD Comment

I 3.3VSB

PU 10K 3.3VSB

Carrier shall pull to GND or left as no-connect.

I 3.3VSB

PU 10K 3.3VSB

Carrier shall pull to GND or left as no-connect

Table 22 General Purpose I/O Signal Descriptions

Signal Pin # Description

GPO0 A93 General purpose output pins.

GPO1 B54 General purpose output pins.

GPO2

GPO3

GPI0

GPI1

GPI2

GPI3

B57

B63

A54

A63

A67

A85

I/O

O 3.3V

O 3.3V

General purpose output pins.

General purpose output pins.

O 3.3V

O 3.3V

General purpose input pins. Pulled high internally on the module. I 3.3V




PU/PD

PU 10K 3.3V

PU 10K 3.3V

PU 10K 3.3V

PU 10K 3.3V

Comment

Table 23 Miscellaneous Signal Descriptions

Signal

I2C_CK

I2C_DAT

Pin # Description

B33 General purpose I²C port clock output/input

B34 General purpose I²C port data I/O line

I/O PU/PD

I/OD 3.3V PU 2.2K 3.3VSB

I/OD 3.3V PU 2.2K 3.3VSB

SPKR

WDT

FAN_PWMOUT B101 Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan’s RPM.

FAN_TACHIN B102 Fan tachometer input.

TPM_PP

B32

B27

A96

Output for audio enunciator, the “speaker” in PC-AT systems O 3.3V

Output indicating that a watchdog time-out event has occurred. O 3.3V

Physical Presence pin of Trusted Platform Module (TPM). Active high. TPM chip has an internal pull-down. This signal is used to indicate Physical Presence to the TPM.

O OD

3.3V

I OD

I 3.3V

PU 47K 3.3V

PU 47K 3.3V

PD 10K

Comment


Requires a fan with two-pulse output.

A TPM 2.0 chip is assembled on the module by default.

48/65

Note

The congatec COM Express Type 6 and Type 10 modules use a Push-Pull output for the fan_pwm signal instead of the open drain output specified in the COM Express specification. Although this does not comply with the COM Express specification 3.0, the benefits are obvious.

The Push-Pull output optimizes the power consumed by the fan_pwm signal without functional change.

Table 24 Power and System Management Signal Descriptions

Signal

PWRBTN#

SYS_RESET#

CB_RESET#

PWR_OK

SUS_STAT#

SUS_S3#

SUS_S4#

SUS_S5#

WAKE0#

WAKE1#

BATLOW#

Pin # Description

B12 Power button to bring system out of S5 (soft off), active on rising edge.

Note: For proper detection, assert a pulse width of at least 16 ms.

B49

B50

B24

B18

A15

A18

A24

B66

B67

A27

THRM# B35

THERMTRIP# A35

SMB_CK B13

SMB_DAT# B14

Reset button input. Active low input. Edge triggered.

System will not be held in hardware reset while this input is kept low.


Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.

Power OK from main power supply. A high value indicates that the power is good.

Indicates imminent suspend operation; used to notify LPC devices.

Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of

SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.

Indicates system is in Suspend to Disk state. Active low output.

Indicates system is in Soft Off state.

PCI Express wake up signal.

General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity.

Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low, or may be used to signal some other external powermanagement event.

Input from off-module temp sensor indicating an over-temp situation.

Active low output indicating that the CPU has entered thermal shutdown.

System Management Bus bidirectional clock line.

System Management Bus bidirectional data line.

I/O

I 3.3VSB

I 3.3VSB

O 3.3V

I 3.3V

O 3.3VSB

O 3.3VSB

O 3.3VSB

O 3.3VSB

I 3.3VSB

I 3.3VSB

I 3.3VSB

PU/PD

PU 10K 3.3VSB

PU 10K 3.3VSB

PU 10K 3.3V

PU 10K 3.3VSB

PU 10K 3.3VSB

PU 10K 3.3VSB

I 3.3V

O 3.3V

PU 10k 3.3V

I/O 3.3VSB PU 2.2K 3.3VSB

I/O OD

3.3VSB

I 3.3VSB

PU 10k 3.3V

PU 2.2K 3.3VSB

PU 10K 3.3VSB

SMB_ALERT#

LID#

B15 System Management Bus Alert – active low input can be used to generate an SMI#

(System Management Interrupt) or to wake the system.

A103 Lid button. Used by the ACPI operating system for a LID switch.


SLEEP# B103 Sleep button. Used by the ACPI operating system to bring the system to sleep state or to wake it up again.


I 3.3V

I 3.3V

PU 47K 3.3VSB

PU 47K 3.3VSB

Comment

Not supported

49/65

Table 25 Power and GND Signal Descriptions

Signal

VCC_12V

VCC_5V_SBY

VCC_RTC

GND

Pin #

A104-A109

B104-B109

B84-B87

A47

A1, A11, A21, A31, A41,

A51, A57, A60, A66, A70,

A80, A90, A100, A110,

B1, B11, B21, B31, B41,

B51, B60, B70, B80, B90,

B100, B110

Description

Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used.

Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions.

May be left unconnected if these functions are not used in the system design.

Real-time clock circuit-power input. Nominally +3.0V.

Ground - DC power and signal and AC signal return path.

All available GND connector pins shall be used and tied to Carrier Board GND plane.

I/O

P

P

P

P

PU/PD Comment

50/65

8.2 C-D Connector Signal Descriptions

Table 26 Connector C-D Pinout

Pin Row C

C1 GND (FIXED)

C2 GND

C3

C4

C5

C6

USB_SSRX0-

USB_SSRX0+

GND

USB_SSRX1-

C7

C8

USB_SSRX1+

GND

C9 USB_SSRX2-

C10 USB_SSRX2+

C11 GND (FIXED)

C12 USB_SSRX3-

C13 USB_SSRX3+

C14 GND

C15 DDI1_PAIR6+(*)

C16 DDI1_PAIR6- (*)

C17 RSVD

C18 RSVD

C19 PCIE_RX6+

C20 PCIE_RX6-

C21 GND (FIXED)

C22 PCIE_RX7+

C23 PCIE_RX7-

C24 DDI1_HPD

C25 DDI1_PAIR4+ (*)

C26 DDI1_PAIR4- (*)

C27 RSVD

C28 RSVD

C29 DDI1_PAIR5+ (*)

C30 DDI1_PAIR5- (*)

C31 GND (FIXED)

C32 DDI2_CTRLCLK_AUX+

C33 DDI2_CTRLDATA_AUX-

C34 DDI2_DDC_AUX_SEL

C35 RSVD

C36 DDI3_CTRLCLK_AUX+

Pin Row D

D1 GND (FIXED)

D2 GND

Pin Row C

C56 PEG_RX1-

C57 TYPE1#

Pin Row D

D56 PEG_TX1-

D57 TYPE2#

D3 USB_SSTX0-

D4 USB_SSTX0+

D5 GND

D6 USB_SSTX1-

D7 USB_SSTX1+

D8 GND

D9 USB_SSTX2-

D10 USB_SSTX2+

D11 GND (FIXED)

C58 PEG_RX2+

C59 PEG_RX2-

C60 GND (FIXED)

C61 PEG_RX3+

C62 PEG_RX3-

C63 RSVD

C64 RSVD

C65 PEG_RX4+

C66 PEG_RX4-

D58 PEG_TX2+

D59 PEG_TX2-

D60 GND (FIXED)

D61 PEG_TX3+

D62 PEG_TX3-

D63 DDPC_CTRLCLK (*)

D64 DDPC_CTRLDATA (*)

D65 PEG_TX4+

D66 PEG_TX4-

D12 USB_SSTX3-

D13 USB_SSTX3+

C67 RAPID SHUTDOWN(*) D67 GND

C68 PEG_RX5+ D68 PEG_TX5+

D14 GND C69 PEG_RX5-

D15 DDI1_CTRLCLK_AUX+ C70 GND (FIXED)

D69

D70

PEG_TX5-

GND (FIXED)

D16 DDI1_CTRLDATA_AUX- C71 PEG_RX6+

D17 RSVD C72 PEG_RX6-

D18 RSVD

D19 PCIE_TX6+

C73

C74

GND

PEG_RX7+

D20 PCIE_TX6-

D21 GND (FIXED)

D22 PCIE_TX7+

C75 PEG_RX7-

C76 GND

C77 RSVD

D71

D72

D73

D74

D75

D76

D77

PEG_TX6+

PEG_TX6-

GND

PEG_TX7+

PEG_TX7-

GND

RSVD

D23 PCIE_TX7-

D24 RSVD

D25 RSVD

D26 DDI1_PAIR0+

D27 DDI1_PAIR0-

D28 RSVD

D29 DDI1_PAIR1+

D30 DDI1_PAIR1-

D31 GND (FIXED)

D32 DDI1_PAIR2+

D33 DDI1_PAIR2-

D34 DDI1_DDC_AUX_SEL

D35 RSVD

D36 DDI1_PAIR3+

C78

C79

C80

C81

C82

C83

C84

C85

C86

C87

C88

C89

C90

C91

PEG_RX8+ (*)

PEG_RX8- (*)

GND (FIXED)

PEG_RX9+ (*)

PEG_RX9- (*)

RSVD

GND

PEG_RX10+ (*)

PEG_RX10- (*)

GND

PEG_RX11+ (*)

PEG_RX11- (*)

GND (FIXED)

PEG_RX12+ (*)

D78

D79

D80

D81

D82

D83

D84

D85

D86

D87

D88

D89

D90

D91

PEG_TX8+ (*)

PEG_TX8- (*)

GND (FIXED)

PEG_TX9+ (*)

PEG_TX9- (*)

RSVD

GND

PEG_TX10+ (*)

PEG_TX10- (*)

GND

PEG_TX11+ (*)

PEG_TX11- (*)

GND (FIXED)

PEG_TX12+ (*)

51/65

Pin Row C

C37 DDI3_CTRLDATA_AUX-

C38 DDI3_DDC_AUX_SEL

C39 DDI3_PAIR0+

C40 DDI3_PAIR0-

C41 GND (FIXED)

C42 DDI3_PAIR1+

C43 DDI3_PAIR1-

C44 DDI3_HPD

C45 RSVD

C46 DDI3_PAIR2+

C47 DDI3_PAIR2-

C48 RSVD

C49 DDI3_PAIR3+

C50 DDI3_PAIR3-

C51 GND (FIXED)

C52 PEG_RX0+

C53 PEG_RX0-

C54 TYPE0#

C55 PEG_RX1+

Note

Pin Row D

D37 DDI1_PAIR3-

D38 RSVD

D39 DDI2_PAIR0+

D40 DDI2_PAIR0-

D41 GND (FIXED)

D42 DDI2_PAIR1+

D43 DDI2_PAIR1-

D44 DDI2_HPD

D45 RSVD

D46 DDI2_PAIR2+

D47 DDI2_PAIR2-

D48 RSVD

D49 DDI2_PAIR3+

D50 DDI2_PAIR3-

D51 GND (FIXED)

D52 PEG_TX0+

D53 PEG_TX0-

D54 PEG_LANE_RV# (*)

D55 PEG_TX1+

Pin Row C

C92 PEG_RX12- (*)

C93 GND

C94 PEG_RX13+ (*)

C95 PEG_RX13- (*)

C96 GND

C97 RVSD

C98 PEG_RX14+ (*)

C99 PEG_RX14- (*)

C100 GND (FIXED)

C101 PEG_RX15+ (*)

C102 PEG_RX15- (*)

C103 GND

C104 VCC_12V

C105 VCC_12V

C106 VCC_12V

C107 VCC_12V

C108 VCC_12V

C109 VCC_12V

C110 GND (FIXED)

The signals marked with an asterisk symbol (*) are not supported on the conga-TR4.

Pin Row D

D92 PEG_TX12- (*)

D93 GND

D94 PEG_TX13+ (*)

D95 PEG_TX13- (*)

D96 GND

D97 RSVD

D98 PEG_TX14+ (*)

D99 PEG_TX14- (*)

D100 GND (FIXED)

D101 PEG_TX15+ (*)

D102 PEG_TX15- (*)

D103 GND

D104 VCC_12V

D105 VCC_12V

D106 VCC_12V

D107 VCC_12V

D108 VCC_12V

D109 VCC_12V

D110 GND (FIXED)

52/65

Table 27 SuperSpeed USB Signal Descriptions

Signal

USB_SSRX0+

USB_SSRX0-

USB_SSTX0+

USB_SSTX0-

USB_SSRX1+

USB_SSRX1-

USB_SSTX1+

USB_SSTX1-

USB_SSRX2+

USB_SSRX2-

USB_SSTX2+

USB_SSTX2-

USB_SSRX3+

USB_SSRX3-

USB_SSTX3+

USB_SSTX3-

Pin # Description

C4 Additional receive signal differential pairs for the Superspeed USB data path I

I/O

C3 I

D4

D3

C7

C6

Additional transmit signal differential pairs for the Superspeed USB data path O

O

Additional receive signal differential pairs for the Superspeed USB data path I

I

D7

D6

Additional transmit signal differential pairs for the Superspeed USB data path O

O


C9 I

D10 Additional transmit signal differential pairs for the Superspeed USB data path O

D9 O


C12 I

D13 Additional transmit signal differential pairs for the Superspeed USB data path O

D12 O

PU/PD Comment

Table 28 PCI Express Signal Descriptions (general purpose)

Signal

PCIE_RX6+

PCIE_RX6-

PCIE_TX6+

PCIE_TX6-

PCIE_RX7+

PCIE_RX7-

PCIE_TX7+

PCIE_TX7-

Pin # Description

C19

C20


PCI Express channel 6, Transmit Output differential pair.

D19

D20

C22

C23


D22

D23

PCI Express channel 7, Transmit Output differential pair.

I/O

I PCIE

O PCIE

I PCIE

O PCIE

PU/PD Comment



Not supported in R-Series.


Not supported in R-Series.


53/65

Signal

PEG_RX0+

PEG_RX0-

PEG_RX1+

PEG_RX1-

PEG_RX2+

PEG_RX2-

PEG_RX3+

PEG_RX3-

PEG_RX4+

PEG_RX4-

PEG_RX5+

PEG_RX5-

PEG_RX6+

PEG_RX6-

PEG_RX7+

PEG_RX7-

PEG_RX8+

PEG_RX8-

PEG_RX9+

PEG_RX9-

PEG_RX10+

PEG_RX10-

PEG_RX11+

PEG_RX11-

PEG_RX12+

PEG_RX12-

PEG_RX13+

PEG_RX13-

PEG_RX14+

PEG_RX14-

PEG_RX15+

PEG_RX15 -

Table 29 PCI Express Signal Descriptions (x16 Graphics)

Pin # Description

C89

C91

C92

C94

C95

C81

C82

C85

C86

C88

C98

C99

C101

C102

C72

C74

C75

C78

C79

C65

C66

C68

C69

C71

C52

C53

C55

C56

C58

C59

C61

C62

PCI Express Graphics Receive Input differential pairs.

I/O PU/PD

I PCIE

Comment

PEG_RX[8:15]± lanes are not supported.

54/65

Signal

PEG_TX8-

PEG_TX9+

PEG_TX9-

PEG_TX10+

PEG_TX10-

PEG_TX11+

PEG_TX11-

PEG_TX12+

PEG_TX12-

PEG_TX13+

PEG_TX13-

PEG_TX14+

PEG_TX14-

PEG_TX15+

PEG_TX15-

PEG_TX0+

PEG_TX0-

PEG_TX1+

PEG_TX1-

PEG_TX2+

PEG_TX2-

PEG_TX3+

PEG_TX3-

PEG_TX4+

PEG_TX4-

PEG_TX5+

PEG_TX5-

PEG_TX6+

PEG_TX6-

PEG_TX7+

PEG_TX7-

PEG_TX8+

Pin # Description

D88

D89

D91

D92

D94

D79

D81

D82

D85

D86

D95

D98

D99

D101

D102

D71

D72

D74

D75

D78

D62

D65

D66

D68

D69

D52

D53

D55

D56

D58

D59

D61

PCI Express Graphics Transmit Output differential pairs.

PEG_LANE_RV# D54 PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse lane order.

Note

The conga-TR4 supports PEG only up to x8 (x4 in R-Series).

I/O PU/PD

O PCIE

I

Comment

PEG_TX[8:15]± lanes are not supported.

Not supported.

55/65

Table 30 DDI Signal Description

Signal

DDI1_PAIR0+

DDI1_PAIR0-

Pin # Description

D26

D27

Multiplexed with DP1_LANE0+ and TMDS1_DATA2+.

Multiplexed with DP1_LANE0- and TMDS1_DATA2-.

DDI1_PAIR1+

DDI1_PAIR1-

DDI1_PAIR2+

DDI1_PAIR2-

DDI1_PAIR3+

DDI1_PAIR3-

D29

D30

D32

D33

D36

D37





Multiplexed with DP1_LANE3+ and TMDS1_CLK+.

Multiplexed with DP1_LANE3- and TMDS1_CLK-.

DDI1_HPD C24 Multiplexed with DP1_HPD and HDMI1_HPD.

DDI1_CTRLCLK_AUX+ D15 Multiplexed with DP1_AUX+ and HMDI1_CTRLCLK.

DP AUX+ function if DDI1_DDC_AUX_SEL is no connect.

HDMI/DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high.

DDI1_CTRLDATA_AUXD16 Multiplexed with DP1_AUX- and HDMI1_CTRLDATA.

DP AUX- function if DDI1_DDC_AUX_SEL is no connect.

HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high.

DDI1_DDC_AUX_SEL D34 Selects the function of DDI1_CTRLCLK_AUX+ and DDI1_CTRLDATA_AUX-.

This pin shall have a IM pull-down to logic ground on the module. If this input is floating, the AUX pair is used for the DP AUX+/- signals. If pulled-high, the

AUX pair contains the CTRLCLK and CTRLDATA signals.

DDI2_PAIR0+

DDI2_PAIR0-

DDI2_PAIR1+

DDI2_PAIR1-

DDI2_PAIR2+

DDI2_PAIR2-

DDI2_PAIR3+

DDI2_PAIR3-

D39

D40

D42

D43

D46

D47

D49

D50









DDI2_HPD D44 Multiplexed with DP2_HPD and HDMI2_HPD.

DDI2_CTRLCLK_AUX+ C32 Multiplexed with DP2_AUX+ and HDMI2_CTRLCLK.


HDMI/DVI I2C CTRLCLK if DDI2_DDC_AUX_SEL is pulled high

DDI2_CTRLDATA_AUXC33 Multiplexed with DP2_AUX- and HDMI2_CTRLDATA.



DDI2_DDC_AUX_SEL C34 Selects the function of DDI2_CTRLCLK_AUX+ and DDI2_CTRLDATA_AUX-.


AUX pair contains the CTRLCLK and CTRLDATA signals

DDI3_PAIR0+

DDI3_PAIR0-

C39

C40



I/O

O PCIE

O PCIE

O PCIE

O PCIE

I 3.3V

I/O PCIE

OD 3.3V

I/O PCIE

I/OD 3.3V

I 3.3V

O PCIE

O PCIE

O PCIE

O PCIE

I 3.3V

I/O PCIE

OD 3.3V

I/O PCIE

I/OD 3.3V

I 3.3V

O PCIE

PU/PD Comment

PD 100K

PD 100K

PU 100K

3.3V

PD 1M

PD 100K

PD 100K

PU 100K

3.3V

PD 1M

56/65

Signal

DDI3_PAIR1+

DDI3_PAIR1-

Pin # Description

C42

C43



DDI3_PAIR2+

DDI3_PAIR2-

DDI3_PAIR3+

DDI3_PAIR3-

DDI3_HPD

C46

C47

C49

C50





C44 Multiplexed with DP3_HPD and HDMI3_HPD.

DDI3_CTRLCLK_AUX+ C36 Multiplexed with DP3_AUX+ and HDMI3_CTRLCLK.


HDMI/DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high

DDI3_CTRLDATA_AUXC37 Multiplexed with DP3_AUX- and HDMI3_CTRLDATA.



DDI3_DDC_AUX_SEL C38 Selects the function of DDI3_CTRLCLK_AUX+ and DDI3_CTRLDATA_AUX-.


AUX pair contains the CTRLCLK and CTRLDATA signals

I/O

O PCIE

O PCIE

O PCIE

I 3.3V

I/O PCIE

OD 3.3V

I/O PCIE

I/OD 3.3V

I 3.3V

Note

PU/PD Comment

PD 100K

PD 100k

PU 100k

PD 1M

The DDI interfaces support dual-mode DisplayPort. To support HDMI/DVI, an external level shifter (PTN3360D) should be implemented on the user’s carrier board.

Table 31 HDMI/DVI Signal Descriptions

Signal

TMDS1_CLK +

TMDS1_CLK -

TMDS1_DATA0+

TMDS1_DATA0-

TMDS1_DATA1+

TMDS1_DATA1-

TMDS1_DATA2+

TMDS1_DATA2-

HDMI1_HPD

HDMI1_CTRLCLK

Pin # Description

D36

D37

HDMI/DVI TMDS Clock output differential pair.

Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-.

D32

D33

D29

D30

D26

D27

C24

D15

HDMI1_CTRLDATA D16

I/O

O PCIE

PU/PD Comment

HDMI/DVI TMDS differential pair.






O PCIE

O PCIE

O PCIE

HDMI/DVI Hot-plug detect. Multiplexed with DDI1_HPD. I PCIE PD 100K

HDMI/DVI I 2 C Control Clock. Multiplexed with DDI1_CTRLCLK_AUX+ OD 3.3V

PD 100K 2.2k to 3.3V Pull-up must be implemented on the carrier board.

HDMI/DVI I 2 C Control Data

Multiplexed with DDI1_CTRLDATA_AUX-

I/OD 3.3V PU 100K

3.3V

2.2k to 3.3V Pull-up must be implemented on the carrier board.

57/65

Signal

TMDS2_CLK +

TMDS2_CLK -

TMDS2_DATA0+

TMDS2_DATA0-

TMDS2_DATA1+

TMDS2_DATA1-

TMDS2_DATA2+

TMDS2_DATA2-

HDMI2_HPD

HDMI2_CTRLCLK

TMDS3_CLK +

TMDS3_CLK -

TMDS3_DATA0+

TMDS3_DATA0-

TMDS3_DATA1+

TMDS3_DATA1-

TMDS3_DATA2+

TMDS3_DATA2-

HDMI3_HPD

HDMI3_CTRLCLK

Pin # Description

D49

D50

HDMI/DVI TMDS Clock output differential pair..


C49

C50

C46

C47

C42

C43

C39

C40

C44

C36

D46

D47

D42

D43

D39

D40

D44

C32

HDM12_CTRLDATA C33

HDMI3_CTRLDATA C37

I/O

O PCIE

PU/PD Comment






Multiplexed with DDI2_PAIR0+ and DDI2_PAIR0-..

HDMI/DVI Hot-plug detect. Multiplexed with DDI2_HPD

HDMI/DVI I 2 C Control Clock

Multiplexed with DDI2_CTRLCLK_AUX+

HDMI/DVI I 2 C Control Data

Multiplexed with DDI2_CTRLDATA_AUX-

HDMI/DVI TMDS Clock output differential pair..





Multiplexed with DDI3_PAIR1+ and DDI3_PAIR1-..



O PCIE

O PCIE

O PCIE

I PCIE

O PCIE

O PCIE

O PCIE

PD 100K

OD 3.3V

PD 100K 2.2k to 3.3V Pull-up must be implemented on the carrier board.

I/OD 3.3V PU 100K

3.3V

O PCIE

2.2k to 3.3V Pull-up must be implemented on the carrier board.

HDMI/DVI Hot-plug detect. Multiplexed with DDI3_HPD.

I PCIE PD 100K

HDMI/DVI I 2 C Control Clock. Multiplexed with DDI3_CTRLCLK_AUX+ OD 3.3V

PD 100K 2.2k to 3.3V Pull-up should be implemented on the carrier board.

HDMI/DVI I 2 C Control Data. Multiplexed with DDI3_CTRLDATA_AUXI/OD 3.3V PU 100K

3.3V

2.2k to 3.3V Pull-up should be implemented on the carrier board.

Note

To support the HDMI interface, an external level translator/shifter (e.g. PTN3360D) should be implemented on the user’s baseboard.

58/65

Signal

DP1_LANE3+

DP1_LANE3-

DP1_LANE2+

DP1_LANE2-

DP1_LANE1+

DP1_LANE1-

DP1_LANE0+

DP1_LANE0-

DP1_HPD

DP1_AUX+

DP1_AUX-

DP2_LANE3+

DP2_LANE3-

DP2_LANE2+

DP2_LANE2-

DP2_LANE1+

DP2_LANE1-

DP2_LANE0+

DP2_LANE0-

DP2_HPD

DP2_AUX+

DP2_AUX-

DP3_LANE3+

DP3_LANE3-

DP3_LANE2+

DP3_LANE2-

DP3_LANE1+

DP3_LANE1-

DP3_LANE0+

DP3_LANE0-

DP3_HPD

DP3_AUX+

DP3_AUX-

Table 32 DisplayPort (DP) Signal Descriptions

Pin # Description

D36

D37

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-.

D32

D33

D29

D30

D26

D27




C24 Detection of Hot Plug / Unplug and notification of the link layer.

Multiplexed with DDI1_HPD.

D15 Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access.

D16 Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access.

D49

D50

D46

D47

Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3-


D42

D43

D39

D40



D44 Detection of Hot Plug / Unplug and notification of the link layer.


C32 Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access.


C49

C50


C46

C47

C42

C43

C39

C40




C44 Detection of Hot Plug / Unplug and notification of the link layer.




I/O

O PCIE

PU/PD Comment

O PCIE

O PCIE

O PCIE

I 3.3V

PD 100K

I/O PCIE PD 100K

I/O PCIE PU 100K

3.3V

O PCIE

O PCIE

O PCIE

O PCIE

I 3.3V

PD 100K

I/O PCIE PD 100K

I/O PCIE PU 100K

3.3V

O PCIE

O PCIE

O PCIE

O PCIE

I 3.3V

PD 100K

I/O PCIE PD 100k

I/O PCIE PU 100k

3.3V

59/65

Table 33 Module Type Definition Signal Description

Signal Pin # Description

TYPE0#

TYPE1#

TYPE2#

C54

C57

D57

The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are no-connects (NC). For Pinout Type 1, these pins do not matter (X).

TYPE2# TYPE1# TYPE0#

X

NC

NC

NC

NC

GND

GND

X

X

NC

NC

GND

GND

NC

NC

X

X

NC

GND

NC

GND

NC

GND

X

Pinout Type 1 (deprecated)





Pinout Type 6

Pinout Type 7

Pinout Type 10

I/O Comment

PDS TYPE[0:2]# signals are available on all modules following the Type 2-6

Pinout standard.

The conga-TR4 is based on the COM Express Type

6 pinout therefore the pins

0 and 1 are not connected and pin 2 is connected to

GND.

TYPE10# A97

The carrier board should implement combinatorial logic that monitors the module TYPE pins and keeps power off

(e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected.

The carrier board logic may also implement a fault indicator such as an LED.

Dual use pin. Indicates to the carrier board that a Type 10 module is installed. Indicates to the carrier that a Rev.

1.0/2.0 module is installed.

TYPE10#

PDS Not connected to indicate

“Pinout R2.0”.

NC

PD

12V

Pinout R2.0

Pinout Type 10 pull down to ground with 4.7k resistor

Pinout R1.0

This pin is reclaimed from VCC_12V pool. In R1.0 modules this pin will connect to other VCC_12V pins. In R2.0 this pin is defined as a no-connect for Types 1-6. A carrier can detect a R1.0 module by the presence of 12V on this pin. R2.0 module Types 1-6 will no-connect this pin. R3.0 module types 6 and 7 will no-connect this pin. Type 10 modules shall pull this pin to ground through a 4.7K resistor.resistor.

Table 34 Power and GND Signal Descriptions

Signal Pin #

VCC_12V C104-C109

D104-D109

GND C1, C2, C5, C8, C11, C14, C21, C31,

C41, C51, C60, C70,C73, C76, C80, C84,

C87, C90, C93, C96, C100, C103, C110,

D1, D2, D5, D8, D11, D14, D21, D31,

D41, D51, D60, D67, D70, D73, D76,

D80, D84, D87, D90, D93, D96, D100,

D103, D110

Description

Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used.

Ground - DC power and signal and AC signal return path.

All available GND connector pins shall be used and tied to carrier board GND plane.

I/O PU/PD Comment

P

P

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9 System Resources

9.1 I/O Address Assignment

The I/O address assignment of the conga-TR4 module is functionally identical with a standard PC/AT.

The BIOS assigns PCI and PCI Express I/O resources from FFF0h downwards. Non PnP/PCI/PCI Express compliant devices must not consume

I/O resources in that area.

9.1.1 LPC Bus

On the conga-TR4, the PCIExpress Bus acts as the subtractive decoding agent. All I/O cycles that are not positively decoded are forwarded to the PCIExpress Bus—not the LPC Bus. Only specified I/O ranges are forwarded to the LPC Bus.

On the conga-TR4, the following I/O address ranges are sent to the LPC Bus:

SupperIO Index 2Eh-2Fh

SerialPort0 3F8h-3FFh

SerialPort1 2F8h-2FFh

SerialPort2 3F0h-3F7h

SerialPort3 3E0h-3E7h

SerialPort4 2F0h-2F7h

SerialPort5 2E0h-2E7h

SerialPort6 3E8h-3EFh

SerialPort7 2E8h-2EFh

KbcPort 60h, 64h

BoardController E00h-FFFh

Some of these ranges are not available if a Super I/O is used on the carrier board or if they are occupied by the COMExpress on-module UARTs

(they can be enabled in BIOS setup). The I/O range E38h-EBFh is always used by on-module LPC devices. Otherwise, the ranges listed above are available for customer use.

If you require additional LPC Bus resources other than those mentioned above, or more information about this subject, contact congatec technical support for assistance.

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9.2 PCI Configuration Space Map

Table 35 PCI Configuration Space Map

Bus Number (hex) Device Number (hex) Function Number (hex) Device ID Description and Device ID

00h 00h 00h 0x15D0 Root Complex

00h 00h 02h 0x15D1 IOMMU

00h

00h (see Note 2)

00h (see Note 4)

00h (see Note 1)

00h (see Note 1)

00h (see Note 1)

00h (see Note 1)

00h (see Note 1)

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

01h (see Note 3)

02h (see Note 3)

03h (see Note 3)

04h (see Note 3)

05h

06h

06h

06h

06h

06h

07h (see Note 3)

08h (see Note 3)

09h (see Note 3)

18h

00h

00h

00h

00h

00h

01h

02h

03h

04h

05h

08h

08h

14h

14h

18h

18h

18h

18h

18h

18h

18h

00h

00h

00h

01h

01h

01h

01h

01h

01h

01h

01h

08h

07h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

01h

02h

00h

03h

00h

01h

02h

03h

04h

05h

06h

00h

00h

00h

00h

01h

02h

03h

04h

05h

06h

07h

00h

0x15DB

0x15DC

0x790B

0x790E

0x15E8

0x15E9

0x15EA

0x15EB

0x15EC

0x15ED

0x15EE

0x15EF

0x1452

0x15D3

0x15D3

0x15D3

0x15D3

0x15D3

0x15D3

0x15D3

0x1452

0x2608

0x2608

0x2608

0x2608

0x2608

0x2608

PCIe Dummy Host Bridge

PCIe PEG Bridge 0

PCIe PEG Bridge 1

PCIe GPP Bridge 0

PCIe GPP Bridge 1

PCIe GPP Bridge 2

PCIe GPP Bridge 3

PCIe GPP Bridge 4

PCIe Dummy Host Bridge

Internal PCIe GPP Bridge 0 to Bus A

Internal PCIe GPP Bridge 0 to Bus B

SMBus Controller

LPC Bridge

Data Fabric

Data Fabric

Data Fabric

Data Fabric

Data Fabric

Data Fabric

Data Fabric

Data Fabric

PCI Express Port 0

PCI Express Port 1

PCI Express Port 2

PCI Express Port 3

PCI Express Switch

PCI Express Switch port 0





PCI Express Port 4

PCI Express Port 5

PCI Express Port 6

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9.3

9.4

0Ah

0Bh (see Note 3)

Bus A

Bus A

Bus A

Bus A

Bus A

Bus A

Bus A

Bus A

Bus B

Note

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

01h

02h

03h

04h

05h

06h

07h

00h

Internal

Internal

Internal

Internal

Internal

Internal

Internal

Internal

Internal

Intel PCIe Ethernet Network on Module

PCI Express Port 7

Internal GPU

Display HD Audio Controller

Cryptographic Coprocessor

USB 3.1

USB 3.1

Audio Processor

Audio Processor – HD Audio Controller

SCSI PCIe

SATA AHCI Mode

1. The PCI Express Ports may only be visible if the PCI Express Port is set to “Enabled” in BIOS setup and a device is attached to the corresponding PCI Express port on the carrier board.

2. The PCI Express Graphics Ports may only be visible if the PCI Express Graphics Port is set to “Enabled” in BIOS setup and a device is attached to the corresponding PCI Express port on the carrier board.

3. The above table represents a case when a single function PCI Express device is connected to all possible slots on the carrier board. The given bus numbers will change based on actual hardware configuration.

4. The PCI Express Port may only be visible if PEG port is set to 2 x4 and a device is attached to the corresponding PCI Express port on the carrier board.

I²C Bus

There are no on-board resources connected to the I²C bus. Address 16h is reserved for congatec Battery Management solutions.

SM Bus

System Management (SM) bus signals are connected to the AMD Chipset and the SM bus is not intended to be used by off-board non-system management devices. For more information about this subject please contact congatec technical support.

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10 BIOS Setup Description

The BIOS setup description of the conga-TR4 can be viewed without having access to the module. However, access to the restricted area of the congatec website is required in order to download the necessary tool (CgMlfViewer) and Menu Layout File (MLF).

The MLF contains the BIOS setup description of a particular BIOS revision. The MLF can be viewed with the CgMlfViewer tool. This tool offers a search function to quickly check for supported BIOS features. It also shows where each feature can be found in the BIOS setup menu.

For more information, read the application note "AN42 - BIOS Setup Description" available at www.congatec.com.

Note

If you do not have access to the restricted area of the congatec website, contact your local congatec sales representative.

10.1 Navigating the BIOS Setup Menu

The BIOS setup menu shows the features and options supported in the congatec BIOS. To access and navigate the BIOS setup menu, press the <DEL> or <F2> key during POST.

The right frame displays the key legend. Above the key legend is an area reserved for text messages. These text messages explain the options and the possible impacts when changing the selected option in the left frame.

10.2 BIOS Versions

The BIOS displays the BIOS project name and the revision code during POST, and on the main setup screen. The initial production BIOS for conga-TR4 is identified as TR44R1xx, where:

• R is the identifier for a BIOS ROM file,

• 1 is the so called feature number and

• xx is the major and minor revision number.

The conga-TR4 binary size is 8 MB.

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10.3 Updating the BIOS

BIOS updates are recommended to correct platform issues or enhance the feature set of the module. The congaTR4 features a congatec/AMI

AptioEFI firmware on an onboard flash ROM chip. You can update the firmware with the congatec System Utility. The utility has five versions—

UEFI shell, DOS based command line 1 , Win32 command line, Win32 GUI, and Linux version.

For more information about “Updating the BIOS” refer to the user’s guide for the congatec System Utility “CGUTLm1x.pdf” on the congatec website at www.congatec.com.

Note

1. Deprecated

Caution

The DOS command line tool is not officially supported by congatec and therefore not recommended for critical tasks such as firmware updates. We recommend to use only the UEFI shell for critical updates.

10.4 Supported Flash Devices

The conga-TR4 supports the following flash devices:

• Winbond W25Q64JVSSIQ (8MB)

The flash device listed above can be used on the carrier board to support external BIOS. For more information about external BIOS support, refer to the Application Note AN7_External_BIOS_Update.pdf on the congatec website at http://www.congatec.com.

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