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CompactPCI
®
CPV5350 Single Board
Computer and Transition Module
BIOS and Programmer’s
Reference Guide
CPV5350A/PG2
August 27, 2001 Edition
© Copyright 2001 Motorola, Inc.
All Rights Reserved.
Printed in the United States of America.
Parts of this manual are reproduced and adapted from the copyrighted Phoenix
Technologies Ltd., PhoenixBIOS 4.0 User’s Manual, used by permission.
Motorola
®
and the Motorola symbol are registered trademarks of Motorola, Inc.
Phoenix
®
is a registered trademark and PhoenixBIOS, PhoenixPHLASH and MultiBoot are common law trademarks of Phoenix Technologies Ltd.
CompactPCI
® is a registered trademark of PCI Industrial Computer Manufacturers Group.
Intel
®
and the Intel logo are registered trademarks of Intel Corporation.
Pentium
® is a registered trademark of Intel Corporation.
Windows
®
and Windows NT
® are registered trademarks of Microsoft in the US and other countries.
OS/2
® is a registered trademark of International Business Machines Corporation.
All other names, products, or services mentioned in this document may be trademarks or registered trademarks of their respective holders.
Safety Summary
The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment.
The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
Ground the Instrument.
To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the equipment is supplied with a three-conductor AC power cable, the power cable must be plugged into an approved three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable meet International
Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.
Do Not Operate in an Explosive Atmosphere.
Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes.
Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage.
Keep Away From Live Circuits Inside the Equipment.
Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment. Service personnel should not replace components with power cable connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such personnel should always disconnect power and discharge circuits before touching components.
Use Caution When Exposing or Handling a CRT.
Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent
CRT implosion, do not handle the CRT and avoid rough handling or jarring of the equipment. Handling of a CRT should be done only by qualified service personnel using approved safety mask and gloves.
Do Not Substitute Parts or Modify Equipment.
Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local
Motorola representative for service and repair to ensure that all safety features are maintained.
Observe Warnings in Manual.
Warnings, such as the example below, precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed. You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment.
Warning
To prevent serious injury or death from dangerous voltages, use extreme caution when handling, testing, and adjusting this equipment and its components.
Flammability
All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers.
EMI Caution
!
Caution
This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.
Lithium Battery Caution
This product contains a lithium battery to power the clock and calendar circuitry.
!
Caution
Danger of explosion if battery is replaced incorrectly. Replace battery only with the same or equivalent type recommended by the equipment manufacturer. Dispose of used batteries according to the manufacturer’s instructions.
!
Attention
Il y a danger d’explosion s’il y a remplacement incorrect de la batterie.
Remplacer uniquement avec une batterie du même type ou d’un type
équivalent recommandé par le constructeur. Mettre au rebut les batteries usagées conformément aux instructions du fabricant.
!
Vorsicht
Explosionsgefahr bei unsachgemäßem Austausch der Batterie. Ersatz nur durch denselben oder einen vom Hersteller empfohlenen Typ. Entsorgung gebrauchter Batterien nach Angaben des Herstellers.
Notice
While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to the Motorola Computer Group website. The text itself may not be published commercially in print or electronic form, edited, translated, or otherwise altered without the permission of Motorola, Inc.
It is possible that this publication may contain reference to or information about Motorola products (machines and programs), programming, or services that are not available in your country. Such references or information must not be construed to mean that Motorola intends to announce such Motorola products, programming, or services in your country.
Limited and Restricted Rights Legend
If the documentation contained herein is supplied, directly or indirectly, to the U.S.
Government, the following notice shall apply unless otherwise agreed to in writing by
Motorola, Inc.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.
1995) and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252.227-7014 (Jun. 1995).
Motorola, Inc.
Computer Group
2900 South Diablo Way
Tempe, Arizona 85282
Table of Contents
CHAPTER 1 PhoenixBIOS Overview
The General Help Window..........................................................................2-5
Resetting Extended System Configuration Data ..............................................2-12
Floppy Configuration Submenu Options...................................................2-13
IDE Configuration Submenu Options .......................................................2-15
Primary/Secondary Master/Slave Submenus.............................................2-16
Primary/Secondary Master/Slave Submenu Options ................................2-18
I/O Device Configuration Submenu Options ............................................2-20
PCI Configuration Submenu Options........................................................2-25
HA Configuration Submenu Options ........................................................2-27
PCI/PNP IRQ Configuration Submenu ............................................................2-29
PCI/PNP IRQ Configuration Submenu Options .......................................2-30
vii
The Remote Console Feature .................................................................... 2-31
Remote Console Submenu Options .......................................................... 2-32
Embedded Flash Submenu Options .......................................................... 2-35
User and Supervisor Passwords ................................................................ 2-40
Using the Boot Device Priority Submenu ................................................. 2-45
CHAPTER 3 Phoenix BIOS Messages
CHAPTER 5 Programming Information
viii
Executing Embedded Flash ........................................................................A-5
Updating from Floppy Disk........................................................................A-5
Updating with Remote Console..................................................................A-6
APPENDIX B Remote Console Escape Keys
ix
APPENDIX D Related Documentation
x
List of Figures
Figure 5-1. Field Programmable Gate Array Watchdog Block Diagram ..................5-3
Figure 5-2. Block diagram for the Field Programmable Gate Array .......................5-12
xi
xii
List of Tables
Table 2-7. Floppy Configuration Submenu Selections ............................................2-13
Table 2-8. IDE Configuration Submenu Selections.................................................2-15
Table 2-9. Primary/Secondary Master/Slave
Table 2-10. I/O Device Configuration Submenu Options........................................2-20
Table 2-12. HA Configuration Submenu Options ...................................................2-28
Table 2-13. PCI/PNP IRQ Configuration Submenu Options...................................2-30
Table 2-19. Key Functions for the Boot Device Priority Submenu .........................2-46
Table 5-9. Index and Data Register Address and Function......................................5-15
xiii
xiv
Table 5-13. Bit Descriptions for the WDCFG Register........................................... 5-19
Table 5-14. Bit Values for Selecting Watchdog Timeout Time ............................... 5-19
Table 5-15. Bit Values Defining Watchdog Timeout and Disabling ....................... 5-20
Table 5-24. Bit Descriptions for the LNACTRL Register....................................... 5-30
Table 5-26. Bit Descriptions for the NVRAM Register .......................................... 5-32
Table 5-27. Bit Selections for the 32K NVRAM Memory Bank ............................ 5-32
Table 5-28. Bit Descriptions for the USBCTRL Register ....................................... 5-33
Table 5-29. Bit Descriptions for the FLBCTRL Register ....................................... 5-34
Table D-1. Motorola Computer Group Documents ................................................. D-1
About This Manual
This CompactPCI CPV5350 Single Board Computer and Transition
Module BIOS and Programmer’s Reference Guide is based on the
CPV5350 BIOS v3.0RM02. It gives you instructions for configuring the
PhoenixBIOS installed on these standard models of the CPV5350 and
CPV5350B Single Board Computer:
Model
Numbers
Description
CPV5350-266 CompactPCI Single Board Computer with 266 MHz processor and 64 or 128MB SDRAM
CPV5350-333 CompactPCI Single Board Computer with 333 MHz processor and 64 or 128MB SDRAM
CPV5350-500 CompactPCI Single Board Computer with 500 MHz
Pentium III processor
It also gives you instructions for using PhoenixBIOS utilities. Use this guide with the CPV5350 CompactPCI Single Board Computer and
Transition Module Installation Guide (part number CPV5350A/IHx).
Summary of Changes
This section summarizes major changes made to this manual.
Date:
August 22, 2001
Change:
Added section titled
Revised Chapter 2,
screens
Revised Chapter 3,
Revised Chapter 4,
Added Appendix A,
Revised Appendix D,
xv
Overview of Contents
This manual is divided into these chapters and appendices:
Chapter 1,
, describes the ROM BIOS and ROM
BIOS functions, the power-on self tests (POST), BIOS services, system hardware requirements, fixed disk drives, function keys and multiboot.
Chapter 2,
, describes the menus and features of the
PhoenixBIOS setup utility. This utility lets you modify BIOS settings and control the special features of your computer.
Chapter 3,
, lists the messages the BIOS can
display.
Chapter 4,
, describes a series of programs run by the
PhoenixBIOS.
Chapter 5,
, gives you information about the
Peripheral Component Interconnect (PCI) bus, watchdog timer, I/O address map, video controller, EIDE and floppy drive interfaces and the
Field Programmable Gate Array (FPGA) registers.
, tells you how to update the BIOS without
installing a new ROM BIOS chip using the Phoenix Phlash Utility or
Embedded Flash.
character sequences to emulate function or navigation keys, or key combinations.
, explains how to configure the BIOS for network boot and gives you information about the Ethernet boot ROM for the on-board Ethernet devices.
, lists other Motorola Computer
Group publications that provide additional sources of information related to the product.
xvi
Comments and Suggestions
Motorola welcomes and appreciates your comments on our documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to:
Motorola Computer Group
Reader Comments DW164
2900 S. Diablo Way
Tempe, Arizona 85282
You can also submit comments to the following e-mail address: [email protected]
In all your correspondence, please list your name, position, and company.
Be sure to include the title and part number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.
Conventions Used in This Manual
We use the following typographical conventions in this document:
bold
is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files.
italic
is used for names of variables to which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms.
courier is used for system output (for example, screen displays, reports), examples, and system prompts.
<Enter>, <Return> or <CR> xvii
xviii
<CR> represents the carriage return or Enter key.
CTRL
represents the Control key. Execute control characters by pressing the
Ctrl key and the letter simultaneously, for example, Ctrl-d.
1
PhoenixBIOS Overview
1
This chapter gives you a brief introduction and overview of the
PhoenixBIOS software. It covers:
❏ a description of the ROM BIOS including ROM BIOS functions
❏ the power-on self tests (POST)
❏
BIOS services
❏ system hardware requirements
❏ fixed disk drives
❏ function keys
❏ multiboot
What is a ROM BIOS?
A ROM BIOS (Basic Input/Output System) is a set of programs permanently stored in a ROM (Read-Only Memory) chip located on the computer motherboard. These programs manage the hardware devices installed on your computer. When you turn on your computer, the ROM
BIOS initializes and tests these devices. During run-time, the ROM BIOS provides the operating system and application programs with access to these devices. You can also use the BIOS Setup program to change your computer’s hardware or behavior.
Software works best when it operates in layers. The ROM BIOS is the bottom software layer in the computer. It functions as the interface between the hardware layer in the computer. It functions as the interface between the hardware and the other layers of software, isolating them from the details of how the hardware works. This arrangement lets you change hardware devices without having to install a new operating system.
1-1
1
PhoenixBIOS Overview
This diagram shows how the ROM BIOS interfaces with the hardware and other layers of software.
Application Programs
Operating System and
Device Drivers
ROM BIOS
System Hardware
ROM BIOS Functions
The PhoenixBIOS software performs these functions. Refer to Table 1-1
Table 1-1. PhoenixBIOS functions
Function
Configures Devices
Initializes Hardware at Boot
Executes Run-Time Routines
Description
Using the Setup program, you can enable, configure, and optimize the hardware devices in your system (clock, memory, disk drives).
At power-on or reset, the BIOS performs Power-
On-Self Test (POST) routines to test system resources and run the operating system.
The BIOS gives you access to basic hardware routines called from DOS and Windows applications.
1-2 Computer Group Literature Center Web Site
Power-On Self Test
Power-On Self Test
The ROM BIOS initializes and configures the computer hardware when you turn on your computer (system boot). It runs a series of complex programs called the Power-On Self Test (POST), which performs a number of tasks, including:
❏
Test Random Access Memory (RAM)
❏
Conduct an inventory of the hardware devices installed in the computer
❏
Configure hard and floppy disks, keyboard, monitor, and serial and parallel ports
❏
Configure other devices installed in the computer such as CD-ROM drives and sound cards
❏
Initialize computer hardware required for computer features such as plug and play and power management
❏
Run Setup if requested
❏
Load and run the Operating System (OS) such as DOS, OS/2,
UNIX, or Windows NT
BIOS Services
The second task of the ROM BIOS is to give the operating system, device drivers, and application programs access to the system hardware. It performs this task with a set of program routines, called BIOS Services, which are loaded into high memory at boot time.
The number of BIOS Services is always changing. The BIOS Services of
PhoenixBIOS provide precise control of hardware devices such as disk drives, which require careful management and exhaustive checking for errors. They also help manage new computer features such as power management, plug and play, and MultiBoot.
1
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1
PhoenixBIOS Overview
System Hardware Requirements
PhoenixBIOS requires these hardware components on the motherboard:
❏
CPU (486 or later)
❏
AT-compatible and MC146818 RTC-compatible chipset
❏
AT or PS/2-compatible Keyboard controller
❏
At least 1 MB of system RAM
❏
The power-on self test (POST) of the BIOS initializes additional
ROM BIOS extensions (Option ROMs) if they are accessible in the proper format. These special requirements apply to such adapter
ROMs. The:
– code must reside in the address space between C0000H and
F0000H.
– code must reside on a 2K boundary.
– first two bytes of the code must be 55H and AAH.
– third byte must contain the number of 512-byte blocks.
– fourth byte must contain a jump to the start of the initialization code.
– code must checksum to zero (byte sum).
Note
The address space from C0000h to C8000h is reserved for external video adapters (for example; EGA, VGA). Part of the address space from D0000h to E0000h is typically used by expanded memory (EMS).
Fixed Disk Drives
PhoenixBIOS supports up to four fixed-disk drives. You can modify the user-defined drive type for each fixed disk listed in Setup by using the menus of the Setup program. This feature avoids the need for customized software for non-standard drives.
1-4 Computer Group Literature Center Web Site
PhoenixBIOS POST Function Keys
PhoenixBIOS POST Function Keys
PhoenixBIOS uses these keys during POST (
):
Table 1-2. PhoenixBIOS keys
Press:
<F2>
<Esc>
<Space>
To:
Enter the Setup program during POST
Launch the Boot First menu
Abort the extended memory test
Phoenix MultiBoot
Phoenix MultiBoot expands your boot options by letting you choose your boot device. You can specify your boot device in Setup, or you can choose a different device each time you boot by selecting a boot device from the
Boot First menu.
When you press <Esc> during POST, the BIOS displays a menu similar to this instead of launching the operating system:
1
This “Boot First” menu displays the boot sequence specified in the Setup
Utility’s Boot menu and lets you:
❏
Override the existing boot sequence (for this boot only) by selecting another boot device. If the specified device does not load the operating system, the BIOS reverts to the previous boot sequence
❏
Enter Setup http://www.motorola.com/computer/literature 1-5
1
PhoenixBIOS Overview
❏
Press <Esc> to continue with the existing boot sequence
To specify a different boot device or enter Setup:
1. use the up and down arrow keys to select an option
2. press <Enter>
3. press <Esc> to cancel and continue with the existing boot sequence
The Boot First menu is configured in the Boot menu of the Setup Utility.
For information refer to
1-6 Computer Group Literature Center Web Site
2
BIOS Setup
2
Using the Phoenix Setup Program
This chapter describes the PhoenixBIOS Setup program (BIOS Setup
Utility). With this utility, you can modify BIOS settings and control the special features of your computer. The Setup program uses various menus for making changes and turning features on or off.
Note
The menus shown in this chapter are those in effect when the manual was printed. The actual menus displayed on your screen may be different and depend in part on the features, hardware, and version of the BIOS installed on your computer.
Starting Setup
The PhoenixBIOS setup utility starts when you turn on or reboot the computer. It checks and configures the system through a power-on self test
(POST). During POST, the following message appears at the bottom of the screen:
Press <F2> to enter SETUP
To start the PhoenixBIOS setup utility, press <F2>.
The BIOS Setup Utility starts and displays the Main Menu.
Note
If POST finishes before you respond and you still want to enter
Setup, restart the computer and try again.
2-1
2
BIOS Setup
The Setup Interface
The Setup program uses a menu-driven interface. Each Setup screen has a menu bar, a legend bar, and a field-specific help window as shown in
Figure 2-1 . An options window is also available for each field with
predefined values.
2-2
Figure 2-1. The basic setup screen
See
Table 2-1 for a description of the fields on this menu.
Computer Group Literature Center Web Site
Using the Phoenix Setup Program
The Menu Bar
The Menu Bar at the top of the window lists these selections. Refer to
.
Table 2-1. PhoenixBIOS Main Menu Bar
Use this menu bar selection:
Main
Memory
Advanced
Security
Status
Boot
Exit
To:
set time and view basic system configuration view and configure system memory and cache set up drives and configure I/O and chipset features set passwords and access options view temperature and power supply status specify boot options exit the Setup Utility with or without saving changes
Use the left/right arrow keys to make a selection.
See the section below, “exiting setup”, for information about exiting the main menu.
The Legend Bar
Use the keys listed in the legend bar on the bottom to make your selections or exit the current menu.
Table 2-2 describes the legend keys and their
alternates.
Table 2-2. Legend Bar
Use this key:
<F1> or <Alt-H>
<Esc>
← or
→ arrow keys
↑
or
↓
arrow keys
<Tab> or <Shift-Tab>
To:
get general help exit this menu select a different menu move the cursor up and down cycle the cursor up and down
2
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2
BIOS Setup
Table 2-2. Legend Bar (Continued)
Use this key:
<Home> or <End>
To:
move the cursor to the top or bottom of the window
<PgUp> or <PgDn>
<F5> or <-> select the previous value for the field
<F6> or <+> or <Space> select the next value for the field
<F9>
move the cursor to the next or previous page load the default configuration values for all menus
<F10>
<Enter>
save and exit execute a command or select > a submenu
To select an item, use the arrow keys to move the cursor to the field you want. Then use the plus and minus value keys to select a value for that field. The Save Value commands in the Exit Menu save the values currently displayed in all the menus.
To display a submenu, use the arrow keys to move the cursor to the submenu you want. Then press <Enter>. A pointer marks all submenus.
The Field Help Window
The help window on the right side of each menu displays the help text for the currently selected field. It updates as you move the cursor to each field.
2-4 Computer Group Literature Center Web Site
Using the Phoenix Setup Program
The General Help Window
Pressing <F1> or <Alt-H> on any menu brings up the General Help window that describes the legend keys and their alternates:
General Help
Setup changes system behavior by modifying the BIOS
configuration parameters. Selecting incorrect values
may cause system boot failure; load Setup Default values
to recover.
<Up/Down> arrows select fields in current menu.
<PgUp/PgDn> moves to previous/next page on scrollable menus.
<Home/End> moves to top/bottom item of current menu.
Within a field, <F5> or <-> selects next lower value and
<F6>, <+>, or <Space> selects next higher value.
<Left/Right> arrows select menus on menu bar.
<Enter> displays more options for items marked with a P.
<Enter> also displays an option list on some fields.
<F9> loads factory-installed Setup Default values.
<F10> restores previous values from CMOS.
<ESC> or <Alt-X> exits Setup; in sub-menus, pressing these
keys returns to the previous menu.
<F1> or <Alt-H> displays General Help (this screen).
_
[Continue]
2
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2
BIOS Setup
The scroll bar on the right of any window indicates that there is more than
one page of information in the window. Refer to Table 2-3
.
Table 2-3. Scroll bar selections
Use:
<PgUp> and <PgDn>
<Home> and <End>
<Enter>
<Esc>
To:
display all the pages display the first and last page display each page and then exit the window to exit the current window
Main Menu Selections
This screen appears when you select the Main Menu.
2-6 Computer Group Literature Center Web Site
Memory Menu
Feature
BIOS Version
Board Serial No.
CPU Type
CPU Speed
Host Bus
Frequency
Cache Ram
Total Memory
System Time
System Date
You can make the following selections on the Main Menu itself. Refer to
. Use the submenus for other selections.
Table 2-4. Main Menu Selections
Default
N/A
N/A
N/A
N/A
N/A
N/A
N/A
00:00:00
01/01/2000
Options
information only information only information only information only information only information only information only
HH:MM:SS
MM/DD/YY
Description
Displays the BIOS version on the
CPU board
Displays the serial number of the
CPU board
Displays the type of processor detected during bootup
Displays the processor speed detected during bootup
Displays the front side bus frequency, either 66MHz or
100MHz
Displays the amount of level 2 cache detected during bootup
Displays the total memory detected during bootup
Sets the system time
Sets the system date
2
Memory Menu
The Memory Menu lets you view and customize memory and cache settings.
http://www.motorola.com/computer/literature 2-7
2
BIOS Setup
This screen appears when you select the Memory Menu:
Feature
Cache RAM
Total Memory
Memory Bank 0
L2 Cache
Table 2-5 describes the selections available in the Memory Menu.
Table 2-5. Memory Menu Selections
Default
N/A
N/A
N/A
Enabled
Options
information only information only information only
Description
Displays the amount of L2 cache detected during bootup
Displays the total memory detected during bootup
Displays the amount of memory detected in this DIMM socket
Enable or disable the L2 cache
L2 Cache ECC
Support (hidden if
L2 Cache is
Disabled)
Enabled
Enabled
Disabled
Enabled
Disabled
Enable or disable L2 cache ECC support. Disabling support increases CPU performance slightly at the expense of error correction
2-8 Computer Group Literature Center Web Site
Memory Menu
Feature
ECC Memory
Config
Table 2-5. Memory Menu Selections (Continued)
Default
Disabled
SERR Signal
Condition (hidden if ECC Memory
Config is
Disabled)
Multiple Bit
Options
Disabled
EC
ECC
ECC Scrub
None
Single Bit
Multiple Bit
Both
Description
Disables memory error checking
Enables memory error checking only
Enables memory error checking and correction
Enables memory error checking and correction with hardware scrubbing
Disables assertion of SERR# on memory error
Enables SERR# assertion on single-bit memory errors
Enables SERR# assertion on multi-bit memory errors
Enables SERR# assertion on both single and multi-bit memory errors
2
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2
BIOS Setup
The Advanced Menu
The Advanced menu lets you set up drives and configure I/O and advanced chipset features. Select “Advanced” from the menu bar on the Main Menu to display this menu:
2-10
!
Caution
Setting items on the Advanced Menu and its submenus to incorrect values may cause your system to malfunction. Make sure you alter only settings you thoroughly understand.
Computer Group Literature Center Web Site
The Advanced Menu
Reset
Configuration
Data
Legacy USB
Support
describes the selections available on the Advanced Menu.
Table 2-6. Advanced Menu Selections
Feature Default
Plug and Play OS No
No
Enabled
Options
No
Yes
No
Yes
Disabled
Enabled
Description
Yes lets the plug-and-play (PnP) operating system configure PnP devices not required for boot. No makes the BIOS configure them.
Yes clears the Extended System
Configuration Data (ESCD) area.
Enabling legacy USB lets you use a USB keyboard as a PS/2 keyboard with a non-USB aware operating system. It also enables
USB boot support from a USB floppy.
2
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2
BIOS Setup
Resetting Extended System Configuration Data
The Extended System Configuration Data (ESCD) area stores information about the devices in your system. In most cases, when you add or remove devices, the BIOS automatically updates the ESCD based on the configuration detected during POST. However, if you want to clear the
ESCD, you can use the Reset Configuration Data feature in the Advanced menu.
Setting the Reset Configuration Data feature to "Yes" clears the ESCD after you exit Setup. At the next boot, the ESCD updates and Reset
Configuration Data automatically returns to “No”.
Floppy Configuration Submenu
The Floppy Configuration submenu lets you set up any floppy drives in your system. When you enter the Floppy Configuration submenu, this screen appears:
2-12 Computer Group Literature Center Web Site
The Advanced Menu
Floppy Configuration Submenu Options
describes the selections available in the Floppy Configuration submenu.
Table 2-7. Floppy Configuration Submenu Selections
Feature Default
Floppy Controller Enabled
Options
Disabled
Enabled
Auto
OS Controlled
Description
Disables the on-board floppy disk controller
Enables the floppy disk controller and allows the user to specify the base address
BIOS selects the floppy disk controller configuration
Allows a plug-n-play operating system to configure the floppy disk controller
Specifies the base I/O address for the enabled floppy disk controller
Base I/O Address
(displayed if
Floppy Controller is Enabled
Diskette A
Primary
Diskette B
Floppy Check
Primary
Secondary
1.44 MB, 3 1/2 inch
Disabled
Disabled
Disabled
360 KB, 5 1/4 inch
1.2 MB, 5 1/4 inch
720 KB, 3 1/2 inch
1.44 MB, 3 1/2 inch
2.88 MB, 3 1/2 inch
Disabled
360 KB, 5 1/4 inch
1.2 MB, 5 1/4 inch
720 KB, 3 1/2 inch
1.44 MB, 3 1/2 inch
Enabled
Disabled
Specifies the type of floppy disk drive installed in your system
Specifies the type of floppy disk drive installed in your system
Enabled verifies the floppy drive type on boot.
Disabled speeds boot
2
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2
BIOS Setup
IDE Configuration Submenu
The IDE Configuration submenu lets you set up any IDE drives in your system. When you enter the IDE Configuration submenu, this screen appears:
2-14 Computer Group Literature Center Web Site
The Advanced Menu
IDE Configuration Submenu Options
describes the selections available in the IDE Configuration submenu.
Table 2-8. IDE Configuration Submenu Selections
Feature
Local Bus IDE
Adapter
Large Disk Access
Mode
DOS
SMART Device
Monitoring
Default
Both
Disabled
Options
Disabled
Primary
Secondary
Both
DOS
Other
Disabled
Enabled
Description
Selects which channels of the onboard IDE controller are enabled
Select DOS for most operating systems, including DOS,
Windows, and Novell NetWare.
For other operating systems, select Other. If installing a new
OS and the drive fails, change this setting and try again.
Different operating systems require different representations of drive geometries
Enable or Disable Self-
Monitoring Analysis-Reporting
Technology (SMART) which monitors and warns of an imminent failure on a hard-disk drive
2
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BIOS Setup
Masters and Slaves
The Master and Slave settings on the IDE Configuration submenu control these types of drive devices:
❏ hard disk
❏ removable disk
❏
CD-ROM
PhoenixBIOS supports up to two IDE disk controllers, called primary and secondary controllers. Each controller supports one master drive and one optional slave drive. There is one IDE connector for each controller on your system, usually labeled “Primary IDE” and “Secondary IDE”.
When you enter the IDE Configuration submenu, it displays the results of
Autotyping. Autotyping is information each drive provides about its own size and other characteristics and their arrangement as masters or slaves on your machine.
Note
Do not change these settings unless your installed drive does not autotype properly (for example; an older hard disk drive that does not support autotyping).
If you need to change your drive settings, use one of the Master or Slave submenus.
Primary/Secondary Master/Slave Submenus
The Primary/Secondary Master/Slave submenus let you configure your system for the drives installed.
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The Advanced Menu
When you enter one of the Primary/Secondary Master/Slave submenus, a screen appears:
2
When type is set to Auto, the detected device is noted in the screen heading and its characteristics display. Use the plus or minus keys or the space bar to specify a different Type.
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BIOS Setup
Primary/Secondary Master/Slave Submenu Options
Table 2-9 describes the selections available in the Primary/Secondary
Master/Slave submenus.
Table 2-9. Primary/Secondary Master/Slave
Submenu Options
Feature
Type
Default
Auto
Options
Auto
None
CD-ROM
IDE Removable
ATAPI Removable
User
0 to 65535
Description
Autotypes installed drives and displays the drive characteristics
Manually specifies that no drive is installed
Specifies a CD-ROM drive
Specifies an IDE removable storage device (a Flash disk, for example)
Specifies an ATAPI removable storage device (for example; a
Zip drive)
Lets you manually configure the system for the installed drive
Specifies the number of drive cylinders
Cylinders
(selectable when
Type=User)
Heads (selectable when Type=User)
Sectors (selectable when Type=User)
Maximum
Capacity
N/A
N/A
N/A
N/A
Multi- Sector
Transfers
(selectable when
Type=User)
N/A
1 to 16
0 to 63 information only
Disabled 2, 4, 8, or
16 sectors
Specifies the number of drive heads
Specifies the number of sectors per track
Displays the calculated drive capacity based on the maximum number of addressable sectors
Specifies the number of sectors per block for multiple-sector transfers
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The Advanced Menu
Feature
LBA Mode
Control (selectable when Type=User)
Default
N/A
32 Bit I/O
SMART
Monitoring
Transfer Mode
(selectable when
Type=User)
Table 2-9. Primary/Secondary Master/Slave
Submenu Options (Continued)
Disabled
N/A
N/A
Ultra DMA Mode
(selectable when
Type=User)
N/A
Options
Enabled
Disabled
Enabled
Disabled information only
Standard
Fast PIO 1, 2, 3, or 4
FPIO 3 / DMA 1
FPIO 4 / DMA 2
Disabled
Mode 0, 1, 2, 3, or 4
Description
Enabling LBA causes logical block addressing to be used in place of cylinders, heads, and sectors
Enables or disables 32-bit data transfers between the CPU and the IDE controller
Displays whether or not SMART monitoring is enabled for the drive
Specifies the method for moving data to and from the drive
(autotype for the optimum transfer mode)
Specifies the Ultra DMA mode used for moving data to and from the drive (Modes 3 and 4 are not supported on the CPV5350)
I/O Device Configuration Submenu
Most devices in the computer require the exclusive use of system resources for operation. These system resources can include Input and Output (I/O) port addresses and interrupt lines.
The I/O Device Configuration submenu lets you specify addresses, interrupts, and operating mode settings for your system’s I/O devices.
2
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2
BIOS Setup
When you enter the I/O Device Configuration submenu, this screen appears:
I/O Device Configuration Submenu Options
Table 2-10 describes the selections available in the I/O Device
Configuration submenu.
Table 2-10. I/O Device Configuration Submenu Options
Feature
PS/2 Mouse
Default
Auto Detect
Options
Disabled
Enabled
Auto Detect
OS Controlled
Description
Disables the mouse port and frees up IRQ 12
Enables the mouse port even if no mouse is present
Enables mouse port only if mouse is present
Allows plug and play operating system to configure the port after
POST
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The Advanced Menu
Table 2-10. I/O Device Configuration Submenu Options (Continued)
Feature
Serial Port A
1
Default
Enabled
Options
Disabled
Enabled
Auto
Description
Disables the port
Enables the port and lets you specify the base address and interrupt
Enables mouse port only if mouse is present
Base I/O Address
(Serial Port A; displays only when Port A is
Enabled and not in use by Remote
Console)
Interrupt
(Serial Port A; displays only when Port A is
Enabled and not in use by Remote
Console)
Serial Port B
1
3F8
IRQ4
OS Controlled
3F8
2F8
3E8
2E8
IRQ3
IRQ4
Lets a plug and play operating system to configure the port after
POST
Specifies the base I/O address for the port
Specifies the interrupt assigned to the port
2
Enabled Disabled
Enabled
Auto
Disables the port
Enables the port and lets you specify the base address and interrupt
Enables mouse port only if mouse is present
OS Controlled Lets a plug-n-play operating system configure the port after
POST
1
If the Remote Console is using Serial Ports A or B, the port settings are configured using the
Remote Console submenu.
2
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2
BIOS Setup
Table 2-10. I/O Device Configuration Submenu Options (Continued)
Feature
Base I/O Address
(Serial Port B; displays only when Port B is
Enabled and not in use by Remote
Console)
Interrupt (Serial
Port B; displays only when Port B is Enabled and not in use by Remote
Console)
Parallel Port
Default
2F8
IRQ3
Enabled
Options
3F8
2F8
3E8
2E8
IRQ3
IRQ4
Disabled
Enabled
Description
Specifies the base I/O address for the port
Specifies the interrupt assigned to the port
2
Mode (Parallel
Port; hidden if
Parallel Port is
Disabled
Auto
OS Controlled
Bi-directional Output only
Bi-directional
EPP
ECP
Disables the port
Enables the port and lets you specify base address, interrupt, and DMA channel
BIOS selects configuration
Lets a plug and play operating system configure the port after
POST
Specifies the transmission mode for the parallel port
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The Advanced Menu
Table 2-10. I/O Device Configuration Submenu Options (Continued)
Feature
Base I/O Address
(Parallel Port; displays only when Parallel Port is Enabled
Default
378
Options
378
278
3BC
Description
Specifies the base I/O address for the parallel port
Interrupt (Parallel
Port; displays only when Parallel Port is Enabled)
IRQ7 IRQ5
IRQ7
Specifies the interrupt assigned to the port
2
DMA Channel
(Displays only when Parallel Port is Enabled and
Mode=ECP)
DMA3 DMA1
DMA3
Specifies the DMA channel assigned to the parallel port
2
If you choose the same I/O address or interrupt for more than one device, the menu displays an asterisk (*) by the conflicting settings. It also displays this message at the bottom of the menu.
You may have to page down to see this message:
* Indicates a DMA, Interrupt, I/O, or memory resource conflict with another device.
Resolve the conflict by selecting other settings for the devices.
2
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BIOS Setup
PCI Configuration Submenu
The PCI Configuration submenu lets you setup PCI devices in your system. When you enter the PCI Configuration submenu, you see this screen:
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The Advanced Menu
PCI Configuration Submenu Options
Table 2-11 describes the selections available in the PCI Configuration
submenu.
Table 2-11. PCI Configuration Submenu Options
Feature
Default Primary
Video Adapter
On-Card Ethernet 1 Enabled
Ethernet 1
Connection
Ethernet 1 Option
ROM
On-Card Ethernet 2 Enabled
Ethernet 2
Connection
Default
AGP
Front
Disabled
Front
Options
AGP
PCI
Enabled
Disabled
Front
Rear
Enabled
Disabled
Enabled
Disabled
Front
Rear
Description
Specifies the default display device when multiple video adapters are installed
Enables the Ethernet controller and lets the BIOS or operating system configure and use it
Disables the device and makes it inaccessible by the BIOS or operating system
1
Front connects the Ethernet signals to the front panel of the
CPU board
Rear connects the Ethernet signals to the connector on the rear transition module (if used)
Enable or disable the execution of the expansion ROM for the on-board Ethernet controller
2
Enables the Ethernet controller and lets the BIOS or operating system configure and use it
Disables the device so it is not accessible by the BIOS or operating system
1
Front connects the Ethernet signals to the front panel of the
CPU board
Rear connects the Ethernet signals to the connector on the rear transition module (if used)
2
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2
BIOS Setup
Table 2-11. PCI Configuration Submenu Options (Continued)
Feature
Ethernet 2 Option
ROM
Default
Disabled
Options
Enabled
Disabled
Description
Enable or disable the execution of the expansion ROM for the on-board Ethernet controller
2
USB Connection Front Front Front connects the USB signals to the front panel of the CPU board
Rear Rear connects the USB signals to the connector on the rear transition module (if used)
1
You cannot use any Ethernet controller features when it is disabled
2
If the on-board Ethernet controller option ROM is disabled, you can still use the Ethernet functions, but you cannot boot through the Ethernet connection or configure Ethernet boot options. Refer to Appendix C, Network Boot.
HA Configuration Submenu
The HA Configuration submenu lets you configure high availability chassis options.
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The Advanced Menu
When you enter the HA Configuration submenu, this screen appears:
2
HA Configuration Submenu Options
Table 2-12 describes the selections available in the HA Configuration
submenu.
Note
HA Configuration occurs only after the initial power-up. You must cycle power to this CPU before changes take effect. If a
Domain is already controlled by the other CPU, this processor does not override and re-configure the Domain.
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BIOS Setup
2
Feature
HA Config
Table 2-12. HA Configuration Submenu Options
Default
Enabled
Domain A
(displays only when HA Config is
Enabled)
Enabled
Domain B (displays only when HA
Config is Enabled)
Enabled
Options
Disabled
Enabled
Split
Disabled
Enabled
Disabled
Enabled
Description
Disables BIOS configuration of high availability chassis
Enables user selected Domain A and Domain B configuration of high availability chassis
Automatically detect, enable, and power slots for this CPU Domain
BIOS does not configure Domain
A
Enables Domain A and powers slots
BIOS does not configure Domain
B
Enables Domain B and powers slots
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The Advanced Menu
PCI/PNP IRQ Configuration Submenu
The PCI/PNP IRQ Configuration submenu lets you configure IRQ resources.
When you enter the PCI/PNP IRQ Configuration submenu, this screen appears:
2
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2
BIOS Setup
PCI/PNP IRQ Configuration Submenu Options
Table 2-13 describes the selections available in the PCI/PNP IRQ
Configuration submenu.
Table 2-13. PCI/PNP IRQ Configuration Submenu Options
Feature Default
IRQ 9 and IRQ 11 Reserved
Options
Available
Reserved
PCI IRQ Lines 1-4 Auto Select Disabled
Auto Select
3, 4, 5, 7, 9, 10, 11,
12, 14, 15
Description
Specifies whether an IRQ is available for PCI or PnP devices or reserved for use by a legacy
ISA device
Disables the PCI Interrupt line
(A, B, C, or D)
BIOS selects IRQ
Specifies an IRQ to assign to the
PCI line
Note
If you choose an interrupt already in use, the menu displays an asterisk (*) at the conflicting settings. It also displays this message at the bottom of the menu. You may have to page down to see this message.
* Indicates a DMA, Interrupt, I/O, or memory resource conflict with another device.
Resolve the conflict by selecting other settings for the devices.
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The Advanced Menu
Remote Console Submenu
The Remote Console submenu lets you configure the BIOS to enable access from a remote terminal.
When you enter the Remote Console submenu, this screen appears:
2
The Remote Console Feature
You can use the CPV5350 in deeply embedded or remote applications that do not require a video display or keyboard. In these applications, the BIOS can still give serial port access to POST messages and commands, and to the BIOS Setup Utility using the Remote Console feature.
Remote Console is a character-based terminal application. It supports:
❏ either VT100 or PC ANSI terminals or terminal emulation
❏ only a direct serial connection to Serial Port A or B using appropriate DTE-to-DTE cabling, such as a null modem cable. Port settings in Setup, such as baud rate, flow control, and terminal emulation, must match the port settings of the remote terminal.
Remote Console does not support graphics or graphical user interfaces.
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2
BIOS Setup
!
Caution
Remote Console is enabled by default. If the Remote Console is disabled, you lose remote access during POST and cannot configure the BIOS remotely.
Because terminals and terminal emulation software vary in their ability to transmit special function keyboard information such as function keys or navigation keys, Remote Console defines a range of escaped character sequences to emulate such keys or key combinations. Refer to Appendix
B,
Remote Console Submenu Options
Table 2-14 describes the selections available in the Remote Console
submenu.
Table 2-14. Remote Console Submenu Options
Feature
COM Port
Default
COM A
Serial Port A
(displays when
COM Port is set to
COM A
Enabled
Serial Port B
(displays when
COM Port is set to
COM B
Base I/O Address
(Serial A/B; displays only when
Port is Enabled
2
3F8
Options
Disabled
COM A
COM B
Disabled
Enabled
Auto
OS Controlled
3F8
2F8
3E8
2E8
Description
Disables Remote Console
Lets user configure Serial Port A for remote access
Lets user configure Serial Port B for remote access
Disables the port
Enables the port and lets you specify base address and interrupt
BIOS selects configuration
Lets a plug-n-play operating system configure the port after
POST
1
Specifies the base I/O address for the port
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The Advanced Menu
Table 2-14. Remote Console Submenu Options (Continued)
Feature
Interrupt (Serial
A/B displays only when port enables
2
Baud Rate
Default
IRQ 4
Options
IRQ 3
IRQ 4
Description
Specifies the interrupt assigned the port
Console Type
Flow Control
Screen Lines
19.2K
VT100
CTS/RTS
24
1200, 2400, 4800,
9600, 19.2K, 38.4K,
57.6K, 115.2K
PC ANSI
VT100
None
XON/XOFF
CTS/RTS
24
25
Specifies the serial transfer rate
Specifies the type of terminal or terminal emulation
3
Specifies hardware, software, or no flow control
3
Specifies the number of lines of text supported by your terminal
3
Active After POST Off Off Terminates remote console after
POST
On Lets you monitor text-based applications (for example; DOS) after POST
1
not recommended with Remote Console
2
port settings specified in the Remote Console submenu override settings specified in the I/O
Configuration submenu
3
Baud Rate, Console Type, and Flow Control settings must match your terminal or terminal emulator
Screen Lines
Personal computer monitors usually support 25 lines and 80 columns of characters in text mode. However, some terminals and terminal emulation software support only 24 lines of characters.
You can configure the Remote Console to scan 24 or 25 lines. If your terminal supports 24 lines, set Screen Lines to 24 to correctly display BIOS
Setup Utility menus. With Screen Lines set to 24, you may have difficulty interacting with character-based applications (for example; DOS, which uses a 25 line display buffer).
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2
BIOS Setup
Active After POST
Use the Remote Console feature for modifying the BIOS configuration in deeply embedded or remote applications. You can also configure the
Remote Console to remain active after POST to provide a remote interface for character-based operating systems such as DOS. However, we do not recommend using Remote Console with operating systems that provide their own terminal interface because it may conflict with these operating systems.
By default, Remote Console terminates after POST. To enable Remote
Console to remain active after POST, select Active After POST in the
Remote Console submenu and choose On. Depending on your application, you may also need to adjust Screen Lines.
Embedded Flash Submenu
The Embedded Flash submenu lets you reprogram the flash EPROM with a new BIOS image without booting an operating system.
When you enter the Embedded Flash submenu, this screen appears:
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The Advanced Menu
Embedded Flash Submenu Options
!
Caution
Feature
Status
Task
Device
Use extreme caution with this submenu. Reprogramming the flash
EPROM with an invalid BIOS may make the system inoperable. For more information about updating the BIOS, refer to Appendix A,
.
Table 2-15 describes the selections available in the Embedded Flash
submenu.
Table 2-15. Embedded Flash Submenu Options
Default
N/A
Save BIOS Save BIOS
Diskette
Drive
Options
information only
Program BIOS
Diskette Drive
Remote Console
(XMODEM)
Description
Displays status and error messages about the embedded flash task being performed
Saves a copy of the current BIOS image to the device and file you specify
Programs the Flash EPROM with the BIOS image you specify
Specifies that the image is contained on a floppy disk inserted in the primary floppy drive. You must also type the file name and path in the File field.
1
Specifies that the image transmits over the remote console connection
2
2
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BIOS Setup
Feature
File
Table 2-15. Embedded Flash Submenu Options (Continued)
Clear CMOS
(Displays when
Task=Program
BIOS)
Default
BIOS,
ROM
Yes
Options
text field
Yes
No
Description
Type the name of the file containing the image to load.
Include the path if the file is not at the root of the device file system (for example;
/flash/bios.rom
1
)
Yes instructs the BIOS to clear the CMOS after the Flash memory is reprogrammed
!
Caution
If the CMOS table is modified in the new BIOS image, not clearing CMOS may make the system inoperable.
!
Caution
If you update the BIOS remotely, clearing CMOS may disable remote access after a new BIOS image is installed.
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The Advanced Menu
Table 2-15. Embedded Flash Submenu Options (Continued)
Feature
Execute
Default
Enter
Options
Enter
Description
Pressing <Enter> either:
❏ saves the BIOS image to the location specified or;
❏ loads a BIOS image into memory,
❏ reprograms the Flash with the new image, and
❏ causes the system to reboot when programming is complete
If Remote Console is specified as the device, press <Enter>, then initiate a receive or send from your remote terminal.
1
Embedded Flash supports only FAT file systems (FAT12, FAT16, and FAT32) and only writes to or reads from the active (bootable) partition of a drive. Other file systems are not supported.
2
Refer to the Remote Console Submenu for information on configuring the BIOS to give remote access
2
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2
BIOS Setup
Security Menu
The Security Menu lets you set User and Supervisor passwords, write protect the boot sector, and specify access options.
When you select the Security Menu, this screen appears:
Security Menu Options
Table 2-16 describes the options available in the Security menu.
Table 2-16. Security Menu Options
Feature
Supervisor
Password
User Password
Default
Clear
Clear
Clear All
Passwords
Enter
Set User Password N/A
Options
information only information only
Enter
Up to eight alphanumeric characters
Description
Displays Supervisor password status, either Clear or Set
Displays User password status, either Clear or Set
Pressing <Enter> clears the User and Supervisor passwords
Press <Enter> to change the User password (Supervisor password must be set)
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Security Menu
Feature
Set Supervisor
Password
Table 2-16. Security Menu Options (Continued)
Default
N/A
Password on Boot Disabled
Options
Up to eight alphanumeric characters
Disabled
Enabled
Description
Press <Enter> to change the
Supervisor password
Fixed Disk Boot
Sector
Diskette Access
Normal Normal
Write Protect
Supervisor User Supervisor
Enabled requires a password on boot (Supervisor password must be set. If Supervisor password is set and this feature is disabled, the BIOS assumes Supervisor is booting)
Write protects the boot sector on the hard disk for virus protection
(Requires a password to format or FDISK the hard disk.)
Supervisor requires the
Supervisor password to boot from or access the floppy disk
2
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2
BIOS Setup
User and Supervisor Passwords
The User and Supervisor passwords are related. You cannot have a User password without first creating a Supervisor password. Passwords are not case sensitive.
When Setup detects that a Supervisor password is set, it prompts you to supply a password before entering Setup. The Supervisor password gives full access to Setup menus. The User password gives restricted view-only access. User, for example, cannot modify any Security features except the
User password.
Pressing <Enter> at either Set Supervisor Password or Set User Password displays a dialog window like this:
Type the password and press <Enter>. Repeat. When changing a password you are prompted to enter the old password.
To clear a user or supervisor password, leave the Enter New Password field blank. To clear all passwords, select Clear All Passwords in the
Security menu and press <Enter>.
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Status Menu
Status Menu
The Status Menu lets you view the current temperature, fan, and power supply status. When you select the Status Menu, this screen appears:
2
Note
You cannot change items on the status menu. They display as information only.
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2
BIOS Setup
Status Menu Options
Feature
CPU Temperature
Card Temperature
Off-Card Fan 1
Off-Card Fan 2
+5V supply
+3.3V supply
+12V supply
-12V supply
Table 2-17 describes the information displayed in the Status menu.
Table 2-17. Status Menu Options
Default
N/A
N/A
N/A
N/A
Options
information only information only information only information only
Description
CPU die temperature
Board ambient temperature at the
LM78 sensor
Displays the speeds of any offcard fans that interface to the
CPU card’s tachometer inputs
Displays the voltages delivered to the CPU card from the system power supply
Boot Menu
The Boot menu lets you configure various boot options. When you select the Boot menu, this screen appears:
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Boot Menu
Boot Menu Options
Feature
Quick Boot
Summary Screen
SETUP Prompt
NumLock
Boot Retry
Table 2-18 describes the options available in the Boot menu.
Table 2-18. Boot Menu Options
Default
Enabled
Disabled
Enabled
Auto
Disabled
Options
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
On
Off
Auto
Disabled
Enabled
Description
Enabled lets the system skip certain tests (for example; memory tests) to decrease the time needed to boot the system
Enables or disables display of system configuration on boot
Enables and disables display of
“Press <F2> for Setup” message during boot up.
Note
Disabled does not prevent entry into Setup
Turns NumLock on at boot
Turns NumLock off at boot
Turns NumLock on if a numeric keypad is detected at boot
If Operating System not found:
“Disabled” waits for a keypress before re-attempting to boot from devices in the boot order
“Enabled” does not wait for keypress and allows the BIOS to continuously re-attempt to boot from devices in the boot list until an OS is found
2
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BIOS Setup
Boot Device Priority Submenu
The Boot Device Priority submenu lets you specify the order of the devices from which the BIOS attempts to boot the operating system. During
Power-On Self Test (POST), if the BIOS is unsuccessful at booting from one device, it trys the next device in the list.
The items on this menu may represent the first of a class of items if you have more than one device of this class installed on your system. For example; if you have more than one fixed-disk drive, [Hard Drive] represents the first of such drives.
When you enter the Boot Device Priority submenu, this screen appears:
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Boot Menu
Using the Boot Device Priority Submenu
The Boot Device Priority submenu specifies:
1. the order that the POST installs devices, and the order that the operating system assigns device letters, (for example; C:, D:, E:)
2. the boot order used in the Boot First menu (Refer to
Note
The order of devices installed by POST may not correspond exactly with letters assigned by the operating system. Many devices such as Legacy Option ROMs support more than one device, which can be assigned more than one letter.
A plus (+) or minus (-) symbol represents a collection of devices that you can expand or collapse. A bang (!) symbol indicates that a device or collection is currently disabled.
To specify a different order, use the up and down arrow keys to select a device. Then use the plus and minus keys to move the item up or down in the list.
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2
BIOS Setup
Table 2-19 describes the functions of the special keys used to configure
devices in this menu.
Table 2-19. Key Functions for the Boot Device Priority Submenu
Use this key: To:
↑↓ arrow keys select a different device or collection of devices
<+> plus move the selected device or collection up in the list
<-> minus
<Enter>
move the selected device or collection down in the list expand or collapse the selected collection of devices
<Ctrl+Enter>
expand all collections of devices
<!>
enable or disable the selected device or collection
<n>
switch the selected device between Hard Drive and
Removable Devices (Applies only to devices such as
LS-120 or Flash drives that can be configured as removable or fixed media)
Network Boot
The BIOS supports network boot through a network interface card or the on-board Ethernet controllers using the Intel Boot Agent option ROM.
When the Ethernet boot ROM enables, it appears as a separate device in the Boot Device Priority submenu, such as “On-Card Ethernet 1” or “On-
Card Ethernet 2”. For more information refer to Appendix C,
Exit Menu
The Exit menu lets you exit the Setup Utility, save or discard changes, and load Setup defaults.
Note
<Esc> does not exit this menu. You must select one of the menu options or press <F10> to exit the Setup Utility.
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When you select the Exit menu, this screen appears:
Exit Menu
2
Exit Menu Options
Table 2-20 describes the options available in the Exit menu.
Table 2-20. Exit Menu Options
Use this feature: To:
Exit Saving Changes save changes to CMOS and exit the Setup
Utility (same as pressing <F10>)
Exit Discarding
Changes exits the Setup Utility without saving changes
Load Setup Defaults load the default settings for all menus
(same as pressing <F9>)
Discard Changes load the previous configuration from
CMOS
Save Changes save the current changes to CMOS but does not exit the Setup Utility
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BIOS Setup
❏
Select “Yes” and press <Enter> to complete the action
❏
Select “No” or press <Esc> to return to the Exit menu
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3
Phoenix BIOS Messages
3
PhoenixBIOS Messages
Refer to
for a list of messages that the BIOS can display. The table also includes explanations of the messages and remedies for reported problems. Most of these occur during the Power-On Self Test (POST).
Some display information about a hardware device (for example; the amount of memory installed). Others may indicate a problem with a device, such as the way it is configured.
If your system fails after you make changes in the Setup menus:
1. reset the computer
2. enter Setup
3. install Setup defaults or correct the error
Table 3-1. PhoenixBIOS Messages
This message: Means:
0200 Failure Fixed Disk Fixed disk is not working or not configured properly
0210 Stuck key
0211 Keyboard error
Stuck key on keyboard
Keyboard not working
0212 Keyboard
Controller Failed
0213 Keyboard locked -
Unlock key switch
Keyboard controller failed test
Keyboard lock on the system is enabled
Action:
Determine if fixed disk is attached properly.
Run Setup and verify that fixed-disk is correctly identified.
Refer to
Verify that nothing is resting on the keyboard
Verify that keyboard is properly attached
May require replacing keyboard controller
Unlock the system to proceed
3-1
3
Phoenix BIOS Messages
Table 3-1. PhoenixBIOS Messages (Continued)
This message:
0220 Monitor type does not match CMOS - Run
SETUP
0230 System RAM
Failed at offset: nnnn
0231 Shadow RAM
Failed at offset: nnnn
0232 Extended RAM
Failed at offset: nnnn
0250 System battery is dead - Replace and run
SETUP
0251 System CMOS checksum bad - Default configuration used
Means:
Monitor type not correctly identified in
Setup
System RAM failed at offset nnnn of the
64k block at which the error was detected
Shadow RAM failed at offset nnnn of the
64k block at which the error was detected.
Extended memory not working or not configured properly at offset nnnn
The CMOS clock battery indicator shows a dead battery. Replace the battery and run
Setup to reconfigure the system.
System CMOS is corrupted or modified incorrectly, perhaps by an application program that changes data stored in
CMOS.
0260 System timer error The timer test failed. Requires repair of
0270 Real time clock error
0271 Check date and time settings system board.
Real-time clock fails BIOS test.
Time or date settings may be incorrect.
Action:
Run setup and specify the correct monitor type
May require memory replacement
May require memory replacement
May require memory replacement
Replace the battery and run Setup to reconfigure the system
When the BIOS detects an invalid checksum, it installs Default Setup
Values. If you do not want these values, enter
Setup and enter your own values. If the error persists, check the system battery
Requires repair of system board.
May require setting legal date (1991-2099).
May require board repair.
May require setting legal date (1991-2099)
3-2 Computer Group Literature Center Web Site
PhoenixBIOS Messages
Table 3-1. PhoenixBIOS Messages (Continued)
This message:
0280 Previous boot incomplete - Default configuration used
02B0 Diskette drive A error
02B1 Diskette drive B error
02B2 Incorrect Drive A type - run SETUP
02B3 Incorrect Drive B type - run SETUP
02D0 System cache error - Cache disabled
8100: Memory
Decreased in Size
Allocation Error for: device
CD ROM Drive
Entering SETUP
Means:
Previous POST did not complete successfully. POST loads default values and offers to run Setup. If the failure was caused by incorrect values and they are not corrected, the next boot will likely fail.
On systems with control of wait states, improper Setup settings can also terminate
POST and cause this error on the next boot.
Drive A or B is present but fails the BIOS
POST diskette tests.
Action:
Run Setup and verify that the wait-state configuration is correct.
This error clears the next time the system boots.
Type of floppy drive A not correctly identified in Setup
Type of floppy drive B not correctly identified in Setup
RAM cache failed and BIOS disabled the cache.
Amount of memory has decreased since the previous boot.
Device resource conflict error
CD ROM Drive identified
Starting Setup program
Verify that the drive is defined with the proper diskette type in Setup and that the diskette drive is attached correctly.
Run Setup and correct the drive settings
Run setup and correct the drive settings
Disabled cache slows system performance.
Replace cache if the error persists.
Status message, no action required
Run setup and modify device settings to correct the conflict
Status message, no action required
Status message, no action required
3
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3
Phoenix BIOS Messages
Table 3-1. PhoenixBIOS Messages (Continued)
This message:
Failing Bits: nnnn
Fixed Disk n
Invalid System
Configuration Data
I/O device IRQ conflict I/O device IRQ conflict error
Memory Type Mixing
Detected
Multiple-bit ECC Error
Occurred
PS/2 Mouse Boot
Summary Screen:
nnnn kB Extended
RAM Passed
nnnn Cache SRAM
Passed
nnnn kB Shadow RAM
Passed
nnnn kB System RAM
Passed
nnnn mB Extended
RAM Passed
Means:
The hex number nnnn is a map of the bits at the RAM address which failed the memory test. Each 1 (one) in the map indicates a failed bit.
Fixed disk n (0-3) identified
Problem with NVRAM data
Incompatible DRAM devices installed in the system
A multi-bit error occurred during a transfer to main memory
PS/2 Mouse installed
Where nnnn is the amount of RAM in kilobytes successfully tested
Where nnnn is the amount of system cache in kilobytes successfully tested
Where nnnn is the amount of shadow
RAM in kilobytes successfully tested
Where nnnn is the amount of system
RAM in kilobytes successfully tested
Where nnnn is the amount of RAM in megabytes successfully tested
Action:
See errors 0230, 0231, or 0232 above for offset address of the failure in
System, Extended, or
Shadow memory.
Status message, no action required
Run setup and clear the
ESCD area
Run setup and modify device settings to correct the conflict
Use same type and speed DIMMs
May require DIMM replacement
Status message, no action required
Status message, no action required
Status message, no action required
Status message, no action required
Status message, no action required
Status message, no action required
3-4 Computer Group Literature Center Web Site
PhoenixBIOS Messages
Table 3-1. PhoenixBIOS Messages (Continued)
This message:
Operating system not found
Parity Check 1 nnnn
Parity Check 2 nnnn
Means:
Operating system cannot be located on any of the enabled boot devices
Parity error found in the system bus.
Parity error found in the I/O bus.
Press <F1> to resume,
<F2> to Setup, <F3> for previous
Displayed after any non-recoverable error message.
Action:
Enter Setup and verify that all fixed and removable devices are properly identified.
Verify that the boot device appears in the boot sequence and is not disabled
BIOS attempts to locate the address and display it on the screen. If it cannot locate the address, it displays
????. Parity is a method for checking errors in binary data. A parity error indicates that some data is corrupted.
BIOS attempts to locate the address and display it on the screen. If it cannot locate the address, it displays
????.
Press <F1> to start the boot process or <F2> to enter Setup and change the settings. Press <F3> to display the previous screen (usually an initialization error of an
Option ROM). Write down and follow the information shown on the screen.
3
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3
Phoenix BIOS Messages
Table 3-1. PhoenixBIOS Messages (Continued)
This message:
Press <F2> to enter
Setup
PS/2 Mouse:
Resource Conflict
Single-bit ECC Error
Occurred
Means:
Optional message displayed during POST.
If you want to enter
Setup, press <F2>, otherwise POST proceeds normally.
PS/2 mouse identified.
Action:
Status message, no action required
Device resource conflict error
A single-bit error was detected during a transfer to main memory
System BIOS shadowed System BIOS copied to shadow RAM.
Run Setup and modify device settings to correct the conflict
May require DIMM replacement
Status message, no action required
Status message, no action required
UMB upper limit segment address: nnnn
Displays the address nnnn of the upper limit of UMB (Upper Memory Blocks) indicating released segments of the BIOS which can be reclaimed by a virtual memory manager
Video BIOS shadowed Video BIOS successfully copied to shadow RAM
Status message, no action required
3-6 Computer Group Literature Center Web Site
4
Power-On Self Tests
4
This chapter helps you troubleshoot your system. It describes error reporting methods and beep codes.
The PhoenixBIOS runs a series of programs called the Power-
On Self Tests (POST), which performs several tasks, including:
❏
Test a Random Access Memory (RAM)
❏
Conduct an inventory of the hardware devices installed in the computer
❏
Configure hard and floppy disks, keyboard, monitor, and serial and parallel ports
❏
Configure other devices installed in the computer such as CD-ROM drives and sound cards
❏
Initialize computer hardware required for computer features such as
Plug and Play (PnP) and power management
❏
Run Setup if requested
❏
Load and run the operating system such as DOS, OS/2, UNIX or
Windows NT
Recoverable Power-On Self Test Errors
When a recoverable error occurs during Power On Self-Test (POST),
PhoenixBIOS displays an error message describing the problem.
PhoenixBIOS also issues a beep code (one long tone followed by two short tones) during POST if the video configuration fails (no card installed or faulty) or if an external ROM module does not properly checksum to zero.
An external ROM module (for example; VGA) can also issue audible errors, usually consisting of one long tone followed by a series of short tones.
4-1
4
Power-On Self Tests
POST Terminal Errors
There are several POST routines that issue a POST Terminal Error and shut down the system if they fail. Before shutting down the system, the terminal-error handler:
1. issues a beep code signifying the test point error
2. writes the error to port 80h
3. attempts to initialize the video
4. writes the error in the upper left corner of the screen (using both mono and color adapters).
The routine derives the beep code from the test point error:
1. The 8-bit error code is broken down to four 2-bit groups (Discard the most significant group if it is 00).
2. Each group is made one-based (1 through 4) by adding 1.
3. Short beeps generate for the number in each group.
Example:
Testpoint 01Ah = 00 01 10 10 = 1-2-3-3 beeps
Test Points and Beep Codes
At the beginning of each POST routine, the BIOS outputs the test point error code to I/O address 80h. Use this code during troubleshooting to establish at what point the system failed and what routine was performed.
Some motherboards have a seven-segment LED display that displays the current value of port 80h. For production boards which do not contain the
LED display, you can purchase a card that performs the same function.
If the BIOS detects a terminal error condition, it:
1. issues a terminal error beep code
2. halts POST and attempts to display the error code on the upper left corner of the screen and on the port 80h LED display. It attempts
4-2 Computer Group Literature Center Web Site
Test Points and Beep Codes repeatedly to write the error to the screen. This may cause "hash" on some CGA displays.
If the system hangs before the BIOS can process the error, the value displayed at the port 80h is the last test performed. In this case, the screen does not display the error code.
Refer to
for a list of the checkpoint codes written at the start of each test and the beep codes issued for terminal errors.
Code Beep
01h
0Bh
0Ch
0Eh
0Fh
10h
11h
12h
02h
03h
04h
06h
08h
09h
0Ah
13h
14h
16h 1-2-2-3
17h
18h
Table 4-1. Checkpoint Codes and Beep Codes
POST Routine Description
Intelligent Platform Management Interface (IPMI) initialization
(optional)
Verify Real Mode
Disable Non-Maskable Interrupt (NMI)
Get CPU type
Initialize system hardware
Initialize chipset with initial POST values
Set IN POST flag
Initialize CPU registers
Enable CPU cache
Initialize caches to initial POST values
Initialize I/O component
Initialize the local bus IDE
Initialize Power Management
Load alternate registers with initial POST values
Restore CPU control word during warm boot
Initialize PCI Bus Mastering devices
Initialize keyboard controller
BIOS ROM checksum
Initialize cache before memory Autosize
8254 timer initialization http://www.motorola.com/computer/literature 4-3
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4
Power-On Self Tests
Table 4-1. Checkpoint Codes and Beep Codes (Continued)
Code Beep
1Ah
1Ch
20h 1-3-1-1
22h 1-3-1-3
24h
26h
28h
29h
2Ah
2Ch 1-3-4-1
2Bh
2Eh
1-3-4-3
2Fh
30h
1-4-1-1
32h
33h
36h
38h
3Ah
3Ch
3Dh
42h
45h
46h 2-1-2-3
47h
POST Routine Description
8237 DMA controller initialization
Reset Programmable Interrupt Controller
Test DRAM refresh
Test 8742 Keyboard Controller
Set ES segment register to 4 GB
Enable A20 line
Autosize DRAM
Initialize POST Memory Manager
Clear 512 kB base RAM
RAM failure on address line xxxx
1
Initialize CMOS with data stored in non-volatile memory other than
CMOS (optional)
RAM failure on data bits xxxx of low byte of memory bus
1
Enable cache before system BIOS shadow
RAM failure on data bits xxxx of high byte of memory bus
1
Test CPU bus-clock frequency
Initialize Phoenix Dispatch Manager
Warm start shut down
Shadow system BIOS ROM
Autosize cache
Advanced configuration of chipset registers
Load alternate registers with CMOS values
Initialize interrupt vectors
POST device initialization
Check ROM copyright notice
Initialize I20 support
4-4 Computer Group Literature Center Web Site
Test Points and Beep Codes
Table 4-1. Checkpoint Codes and Beep Codes (Continued)
69h
6Ah
6Bh
6Ch
6Eh
70h
62h
64h
66h
67h
68h
Code Beep
48h
49h
4Ah
4Bh
4Ch
4Eh
50h
5Ah
5Bh
5Ch
60h
51h
52h
54h
58h 2-2-3-1
59h
POST Routine Description
Check video configuration against CMOS
Initialize PCI bus and devices
Initialize all video adapters in s
QuietBoot start (optional)
Shadow video BIOS ROM
Display BIOS copyright notice
Display CPU type and speed
Initialize EISA board
Test keyboard
Set key click if enabled
Test for unexpected interrupts
Initialize POST display service
Display prompt "Press F2 to enter SETUP"
Disable CPU cache
Test RAM between 512 and 640 kB
Test extended memory
Test extended memory address lines
Jump to UserPatch1
Configure advanced cache registers
Initialize Multi Processor APIC
Enable external and CPU caches
Setup System Management Mode (SMM) area
Display external L2 cache size
Load custom defaults (optional)
Display shadow-area message
Display possible high address for UMB recovery
Display error messages
4
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Power-On Self Tests
Table 4-1. Checkpoint Codes and Beep Codes (Continued)
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
Code Beep
72h
76h
7Ch
7Eh
80h
81h
82h
8Ch
8Fh
90h
91h
92h
93h
95h
96h
97h
98h 1-2
POST Routine Description
Check for configuration errors
Check for keyboard errors
Set up hardware interrupt vectors
Initialize coprocessor if present
Disable onboard Super I/O ports and IRQs
Late POST device initialization
Detect and install external RS232 ports
Configure non-MCD IDE controllers
Detect and install external parallel ports
Initialize PC-compatible PnP ISA devices
Re-initialize onboard I/O ports.
Configure Motherboard Configurable Devices (optional)
Initialize BIOS Data Area
Enable Non-Maskable Interrupts (NMIs)
Initialize Extended BIOS Data Area
Test and initialize PS/2 mouse
Initialize floppy controller
Determine number of ATA drives (optional)
Initialize hard-disk controllers
Initialize local-bus hard-disk controllers
Jump to UserPatch2
Build MPTABLE for multi-processor boards
Install CD ROM for boot
Clear huge ES segment register
Fixup Multi Processor table
Search for option ROMs. One long, two short beeps on checksum failure
4-6 Computer Group Literature Center Web Site
Test Points and Beep Codes
B4h 1
B5h
B6h
B9
BAh
BBh
BCh
BDh
BEh
BFh
Table 4-1. Checkpoint Codes and Beep Codes (Continued)
A2h
A4h
A8h
AAh
ACh
AEh
B0h
B2h
B3h
Code Beep
99h
9Ah
9Ch
9Dh
9Eh
9Fh
A0h
POST Routine Description
Check for SMART Drive (optional)
Shadow option ROMs
Set up Power Management
Initialize security engine (optional)
Enable hardware interrupts
Determine number of ATA drives
Set time of day
Check key lock
Initialize typematic rate
Erase F2 prompt
Scan for F2 key stroke
Enter SETUP
Clear Boot flag
Check for errors
POST done - prepare to boot operating system
Store CMOS data in non-volatile memory other than CMOS
(optional)
One short beep before boot
Terminate QuietBoot (optional
Check password (optional
Prepare Boot
Initialize DMI parameters
Initialize PnP Option ROMs
Clear parity checkers
Display MultiBoot menu
Clear screen (optional)
Check virus and backup reminders
4
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Power-On Self Tests
Table 4-1. Checkpoint Codes and Beep Codes (Continued)
86h
87h
88h
89h
8Ah
80h
81h
82h
83h
84h
85h
C7h
C8h
C9h
CAh
CBh
Code Beep
C0h
C1h
C2h
C3h
C4h
C5h
C6h
CCh
CDh
D2h
POST Routine Description
Try to boot with INT 19
Initialize POST Error Manager (PEM)
Initialize error logging
Initialize error display function
Initialize system error handler
Dual CMOS (optional)
Initialize note dock (optional)
Initialize note dock late
Force check (optional)
Extended checksum (optional)
Initialize serial keyboard device (optional)
Install ROM/RAM disk (optional)
Initialize serial video device (optional)
Enable PCMCIA cards (optional)
Unknown interrupt
Codes 80h through 97h used for boot block in Flash ROM
Initialize the chipset
Initialize the bridge
Initialize the CPU
Initialize the system timer
Initialize system I/O
Check force recovery boot
Checksum BIOS ROM
Go to BIOS
Set Huge Segment
Initialize Multi Processor
Initialize OEM special code
4-8 Computer Group Literature Center Web Site
Test Points and Beep Codes
Table 4-1. Checkpoint Codes and Beep Codes (Continued)
Code Beep POST Routine Description
8Bh
Initialize PIC and DMA
8Ch
Initialize Memory type
8Dh
Initialize Memory size
8Eh
Shadow Boot Block
8Fh
Initialize system management mode (optional)
90h
System memory test
91h
Initialize interrupt vectors
92h
Initialize Run Time Clock
93h
Initialize video
94h
Output one beep
95h
Initialize boot device
96h
Clear Huge Segment
97h
Boot to OS
1
If the BIOS detects error 2C, 2E or 30 (base 512K RAM error), it displays an additional word-bitmap (xxxx) indicating the address line or bits that failed. For example; "2C
0002" means address line 1 (bit one set) failed. "2E 1020" means data bits 12 and 5 (bits
12 and 5 set) failed in the lower 16 bits. The BIOS also sends the bitmap to the port-80
LED display. This sequence repeats continuously: check point code display, high-order byte and low-order byte.
4
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Power-On Self Tests
4-10 Computer Group Literature Center Web Site
5
Programming Information
5
This chapter gives you information about the:
❏
Peripheral Component Interconnect (PCI) bus
❏ watchdog timer
❏
I/O address map
❏ video controller
❏
EIDE and floppy drive interfaces
❏
Field Programmable Gate Array (FPGA) registers
Peripheral Component Interconnect (PCI)
Local Bus
The PCI local bus is a high-performance, 32-bit bus with multiplexed address and data lines. Use it as an interconnect mechanism between highly-integrated peripheral controller components, peripheral add-in boards and processor/memory systems.
The CPV5350 supports a 32-bit PCI interface on the physical CompactPCI connector. On-board devices connect directly to the primary bus. Offboard access is supported through the DEC 21154 PCI-PCI bridge. The
PCI interface has a read or write bandwidth of at least 120MB per second.
5-1
5
Programming Information
Watchdog Timer
The Field Programmable Gate Array (FPGA) includes a two-level watchdog timer. The watchdog timer has four modes of operation:
1. disabled
2. set a flag in a register in ISA I/O memory map
3. item 2 + assert a selectable interrupt (ISA, NMI, SMI, SMALERT)
4. item 2 + assert NMI followed by a system Reset
The timer interfaces through the Watchdog Configuration (WDCFG)
Register and Watchdog Strobe (WDSTB) port. You can program the watchdog timer via registers in the ISA I/O memory map. The watchdog timer is protected from accidental enabling. The timer supports a range of count down timeouts from 17.8 ms to 4.86 minutes.
5-2 Computer Group Literature Center Web Site
Watchdog Timer
Watchdog Timer Operation
You can enable/disable the watchdog timer and set the level 1 watchdog timeout for a delay of 17.8 ms to 291 seconds. You can also remotely monitor the system by generating a level 1 timeout. You cannot program the level 2 timer. It has a fixed period of 8.2 ms.
diagram of the watchdog timer.
5
56.18Hz
Oscillator
Write to
Strobe Port
WD[1:0]<>00
0
1
SEL2-0
0
1
0
1
0
WD[1:0]=11
0
1
Level 1
Timer
CLK
CLR
Period
TO
CLK
CLR
EN
Level 2
Timer
TO
1
0
D
CLK
CLR
Q
WD1
1
0
ALARM_EN
WDNMI
WDIRQ
0
1
WDALARM
Reset
CLR_STATUS
Figure 5-1. Field Programmable Gate Array Watchdog Block Diagram
Enabling the timer
To enable the timer, you must initialize the WDCFG register with the timer period (SEL[2:0]) and mode (WD[1:0]). After initialization the level 1 timer begins to count down. If the level 1 timer reaches the period specified in the SEL bits in the WDCFG register, it times out and generates a system http://www.motorola.com/computer/literature 5-3
5
Programming Information event specified by the WD[1:0] bits. At timeout the system can generate an alarm signal (controlled by the ALARM_EN bit). It also enables the level
2 watchdog timer to begin counting down if WD[1:0] is set to 11.
If the level 2 timer enables it times out 8.4 milliseconds after the level 1 timer. At timeout of the level 2 timer a power-on type system reset generates. All FPGA registers reset to their power-on states with the exception of the watchdog timeout latch. The timeout latch can determine whether a watchdog timeout caused the system to reboot. You can view the value of the watchdog timeout latch by reading bit 2 of the watchdog strobe
(WDSTB) port.
You can strobe the watchdog by writing to the WDSTB. When the watchdog strobes, both timers reset to their initial count; and the watchdog resets to its initial state of counting down the level 1 timer. Strobing affects the watchdog timeout latch and must be cleared separately.
I/O Address Map
PCI system memory and I/O are configured or enumerated dynamically each time the system boots or by an operating system (Plug and Play), but there are legacy I/O locations that remain constant.
Table 5-1 shows I/O addressing. Functions listed with (opt) are not
normally occupied by on-board resources. BIOS Setup or special utilities may be used to enable or relocate these features from their default values.
Table 5-1. I/O Addresses
Address
0000-000F
0020-0021
0040-0043
0060-0064
0070-0071
0050-0057
1
0058-005F
1
DMA Controller 1
Interrupt controller 1
Counter timer
Function
Keyboard, NMI, speaker
Real time clock/NMI mask
LM78 System monitor (opt)
WatchDog timer, ENUM (opt)
5-4 Computer Group Literature Center Web Site
I/O Address Map
Table 5-1. I/O Addresses (Continued)
Address
0080-009F
00A0-00BF
00C0-00DF
00F0
0170-0177
2
01F0-01F7
2
0278-027F
3
02E8-02EF
3
02F8-02FF
2
0376-0377
2
0378-037F
2
03BC-03C3
3
03E8-03EF
3
DMA page register, POST checkpoint
Interrupt controller 2
DMA controller 2
Reset coprocessor
Secondary IDE channel (opt)
Primary IDE channel
Function
Parallel port 2 (opt)
Serial port 4 (opt)
Serial port 2 (default)
Secondary IDE port (opt)
Parallel port 1 (default)
Parallel port 3 (opt)
Serial port 3 (opt)
Floppy channel 03F0-03F5
03F6-03F7
03F8-03FF
040A-043F
0480-048F
2
Primary IDE and floppy
Serial port 1 (default)
DMA scatter/gather
DMA high pages
04D0-04D1
04D6
0678-067A
3
0778-077A
3
07BC-07BE
3
Edge/level interrupts
DMA2 extended mode
Parallel port 2 (opt)
Parallel port 1 (opt)
Parallel port 3 (opt)
0CF8-0Cff PCI configuration
1
The Watchdog timer and LM78 are normally disabled but you can relocate and enable them via PCI configuration.
2
These ports are available if the listed function is not enabled in the
BIOS.
3
This is an alternate range that you can select in the BIOS setup.
5
http://www.motorola.com/computer/literature 5-5
5
Programming Information
Memory Address Mapping
PCI system memory and I/O configure or enumerate dynamically each time the system boots or by an operating system (Plug and Play), but there are legacy memory locations that remain constant.
Refer to
for memory address information.
Table 5-2. Memory Address
Address Range
000000H-09FFFFH
0A0000H-0BFFFFH
0C0000H-0C7FFFH
0C8000H-0DFFFH
0E0000H-0EFFFFH
0F0000H-0FFFFFH
Function
640 KB conventional RAM
VGA DRAM (typically on the
PCI backplane)
VGA ROM (typically on the PCI backplane)
Expansion ROM
System BIOS extensions
Phoenix system BIOS
Video Controller
The i740 chip gives on-card video including hardware 3D rendering, hardware 3D texturing and Advanced Graphics Port (AGP) interface. AGP gives a synchronous interface at 66MHz. The AGP reaches a theoretical transfer rate of 500MB/second and supplies a direct connection to the oncard video controller.
You can enable or disable this device through the BIOS setup utility. You can access video connections on the CPV5350 front panel and the
CPV5350 Transition Module rear panel via a standard 15-pin high density
D-sub video connector.
5-6 Computer Group Literature Center Web Site
EIDE Interface
EIDE Interface
You can connect to both primary and secondary Enhanced Integrated
Device Electronics (EIDE) interfaces through the rear I/O Transition
Module. The primary EIDE channel is available for the connection of onboard devices through an on-board height density connector. The IDE interface supports AT Attachment Packet Interface (ATAPI) modes 0 to 4.
Each IDE interface supports two IDE devices (master and slave). The IDE interface supports disk drives up to 8.2Gbytes and CD-ROM drives.
Note
If you use the on-board IDE hard drive, it connects to the primary
IDE port. If this is the case, you can connect only one drive to the primary rear I/O EIDE port, and you must jumper the drive different (master or slave) than the on-board drive
shows all possible on-board drive options.
Table 5-3. On-board Drive Options
Drive option 1
Floppy
IDE hard drive
IDE flash drive
Floppy
Floppy
IDE flash drive
Drive option 2
Not installed
Not installed
Not installed
IDE hard drive
IDE flash drive
IDE hard drive
Floppy Interface
The floppy interface supports up to two floppy drives:
❏
5.25 inch - 360Kb, 1.2MB
❏
3.5 inch - 720KB, 1.44MB
5
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5
Programming Information
The floppy interface connector consists of a 34(2x17) pin shrouded header available on the rear I/O transition module, or a flex cable connector for on-board drive mounting.
Note
You cannot use both the rear I/O connected floppy and the onboard floppy connection at the same time.
Parallel Port
The parallel port has Enhanced Capabilities Port (ECP) and Enhanced
Parallel Port (EPP) modes of operation.
The parallel interface connector is a 25-pin D-connector header available on the rear I/O transition module, or a 25-pin micro-D connector on the front panel.
Serial Ports
The CPV5350 has two serial ports. The ports support 16550 operation. The serial interface connector is a 9-pin D style connector available on the rear
I/O transition module and on the front panel. The serial ports are ESD protected to 15KV.
USB
The CPV5350 has two Universal Serial Bus (USB) ports with transfer capability from 1.2Mbits/second to 12Mbits/second.
Both ports have two USB connectors on the front panel and the rear I/O transition module. You can route USB signals to the front or rear I/O connectors and enable or disable USB in the BIOS setup.
❏
Jumper installed - rear connection
❏
Jumper removed - front connection
5-8 Computer Group Literature Center Web Site
Keyboard/Mouse Interface
Keyboard/Mouse Interface
The keyboard and mouse is supported by a single PS/2 connector on the front panel and separate PS/2 style connectors on the rear I/O transition module. The front I/O keyboard/mouse connector uses a standard splitter cable to connect to a mouse and keyboard.
DMA Channels
Their are eight Direct Memory Access (DMA) channels. Refer to Table 5-
Table 5-4. DMA Channels
Channel
DMA 0
DMA 1
DMA 2
DMA 3
DMA 4
DMA 5
DMA 6
DMA 7
Function
ISA memory refresh
Reserved
Floppy disk controller
Reserved
Cascade for DMA 1
Reserved
Reserved
Reserved
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Programming Information
Interrupts
Their are 18 interrupt channels. Refer to
.
Table 5-5. Interrupt Channels
9
10
11
12
7
8
5
6
Channel
NMI
SMI
0
3
4
1
2
13
14
15
Function
Reports parity / System errors
System management
System timer
Keyboard
Cascade for IRQ 8-15
COM 2/serial port 2
COM 1/serial port 1
Parallel port 2
Floppy controller
Parallel port 1
Real time clock
Software redirect to IRQ2
Reserved
Reserved / special features
Reserved / PS/2 mouse
Coprocessor
Hard disk controller
Reserved
5-10 Computer Group Literature Center Web Site
Field Programmable Gate Array Registers
Field Programmable Gate Array Registers
The Field Programmable Gate Array (FPGA) has four major functional blocks:
❏ a two level watchdog timer
❏ system monitoring
❏ a serial EEPROM interface
❏ peripheral components configuration
The FPGA is I/O mapped and resides on the single board computer’s ISA
shows the FPGA block diagram.
5
DEG
FAL
ENUM
ISA Bus
Host
CPU
Interface
WDSTB
INDEX
DATA
REGISTER
FILE
EEPROM
Interface
Watchdog
Timer
System
Monitoring
Reset
NMI
SMI
SCI
IRQ5
IRQ7
IRQ9
IRQ11
Figure 5-2. Block diagram for the Field Programmable Gate Array
http://www.motorola.com/computer/literature 5-11
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Programming Information
You can configure and control FPGA features by reading from and writing to the internal configuration registers. You can access the registers by:
1. writing the register number to the FPGA index port
2. reading or writing data to the FPGA data port
The index port clears to zero after writes to the data port to protect from inadvertent corruption of the register file. The FPGA also has an I/O mapped watchdog strobe port (WDSTB). Writes to this port reset the watchdog timer count.
shows the I/O addresses for each FPGA port.
Table 5-6. FPGA Mapping for I/O Ports
Address
0x005B
0x005D
0x005F
Port/Register Name
WDSTB
INDEX
DATA
Internally, the FPGA is divided into a series of register sets. The register sets logically group registers together which perform similar functions.
The default register set contains registers that control most FPGA features.
Occasionally you may need to select a different set. To switch between register sets, you must program the DEVNUM register for the register set that you want to access.
shows the device numbers and the descriptions for the register sets within the FPGA.
Table 5-7. FPGA Register Sets
Device
Number
0x00
0x10
Register Set/Device Description
Legacy Features
On-Card Ethernet Controller A
5-12 Computer Group Literature Center Web Site
Field Programmable Gate Array Registers
Table 5-7. FPGA Register Sets (Continued)
Device
Number
0x11
0x12
0x13
0x14
Register Set/Device Description
On-Card Ethernet Controller B
Non-volatile RAM
On-Card USB Controller
Flash BIOS
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Programming Information
Table 5-8 shows the registers defined for each register set.
Table 5-8. FPGA Registers
0x00
0x00
0x00
0x00
0x10
0x11
0x12
0x13
0x14
Device
Number
0x00
0x00
0x00
0x00
0x00
0x00
0x07
0x08
0x09
0x0B
0x01
0x01
0x01
0x01
0x01
Register
Number
0x00
0x02
0x03
0x04
0x05
0x06
Register
Name
STAT
ECTRL
WTR
ISR
SCIEN
NMIEN
IRQEN
ALEN
LEN
POS
LNACTRL
LNBCTRL
NVRAM
USBCTRL
FLBCTRL
5-14 Computer Group Literature Center Web Site
Field Programmable Gate Array Registers
Register Descriptions
This section describes how to access the various FPGA register sets.
“RES” means that bit is “reserved”. The bit description tables below show bits 0 through 7 on the top line and bit functions on the second line.
You can access the FPGA registers by an index register at offset 05h from the base address of the FPGA (0x5Dh). The data register is located at offset
07h (0x5Fh). Refer to
. To access an FPGA register, write to the index register first and then read/write from the data register. The BIOS sets the default FPGA Base address to 58h.
Table 5-9. Index and Data Register Address and Function
Port
Index
Data
Offset
Address
05h
07h
Function
select the device register read/write data to the selected register
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Programming Information
5
There is also a device select register at Index 0Fh. Use this register to
address multiple devices using the same index set. Refer to Table 5-10 for
a map of the FPGA register set.
Table 5-10. Map of the FPGA Register Set
DEVICE 00h
SYSTEM
00 Status
DEVICE 10h
LAN A Ctrl
01 LAN A
02 EEPROM
03 Watchdog
04 INT Sel
05 SCI Mask
06 NMI Mask
07 IRQ Mask
08 Alm Mask
09 FLT Latch
0B Power On
0F DEV SEL 0F DEV SEL
DEVICE 11h
LAN B Ctrl
01 LAN B
0F DEV SEL
DEVICE 12h
NVRAM Ctrl
01 NRAM
0F DEV SEL
DEVICE 13h
USB Ctrl
01 USB
0F DEV SEL
DEVICE 14h
FLASH WP
01 FLASH
0F DEV SEL
5-16 Computer Group Literature Center Web Site
Field Programmable Gate Array Registers
STAT
The Status Register (STAT) is a read only register. Reads of the unused bits produce indeterminate values. Writes have no effect. Refer to
Table 5-11. Bit Descriptions for the STAT Register
5 4 3 2 1 7 (most significant bit)
RES
6
FAL DEG ENUM LM78
ALARM A
LM78
ALARM B
SMB
ALERT
0 (least significant bit)
MMC2
TEMP
ALARM
MMC2 TEMP ALARM (Bit 0)
This signal connects to the MMC2’s thermal sensor alarm output (ATF).
The input is latched when active. You can clear this bit (0) with a write to the LTCLR register. A read of this bit returns the latched status of the input.
SMB ALERT (Bit 1)
This bit reflects the level of the SMBus Alert signal.
LM78 ALARM A (Bit 3) and LM78 ALARM B (Bit 2)
The LM78 output functions feed these signals. The input is latched when active. You can clear these bits (3 and 2) with a write to the LTCLR register. A read of this bit returns the latched status of the input.
ENUM (Bit 4)
ENUM comes from the CompactPCI (CPCI) bus and signals the insertion of a new device. The input is latched when active. You can clear this bit
(4) with a write to the LTCLR register. A read of this bit returns the latched status of the input.
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Programming Information
DEG (Bit 5)
DEG comes from the CompactPCI bus and signals a power supply deregulation condition. A read of this bit returns the current state of the input.
FAL (Bit 6)
This signal comes from the CompactPCI bus and signals a power failure condition. A read of this bit returns the current state of the input.
ECTRL
The Serial EEPROM Control Register (ECTRL) lets you access the external serial configuration EEPROM. Refer to
7 (most significant bit)
RES
Table 5-12. Bit Descriptions for the ECTRL Register
6 5 4 3 2 1
RES RES EEPRG EERST EEEN EECLK
0 (least significant bit)
EEDTA
EEDTA (Bit 0)
Writes to this bit are sent to the external serial EEPROM’s data line. If you write a 1 to this bit, reads from the bit reflect the state of the data output from the external serial EEPROM.
EECLK (Bit 1)
This bit is used to send clock data into and out of the external serial
EEPROM.
EEEN (Bit 2)
Set to 1 to enable access to the serial EEPROM.
EERST (Bit 3)
Set to 1 to reset the external serial configuration EEPROM.
5-18 Computer Group Literature Center Web Site
Field Programmable Gate Array Registers
EEPRG (Bit 4)
Set to 1 to enable programming of the serial EEPROM.
WDCFG
Refer to
Table 5-13 for bit descriptions for the WDCFG.
Table 5-13. Bit Descriptions for the WDCFG Register
7 (most significant bit)
CLR_STATUS
6 5 4 3 2 1 0 (least significant bit)
ALARM_SET RES WD1 WD0 SEL2 SEL1 SEL0
SEL0 (Bit 0), SEL1 (Bit 1) and SEL2 (Bit 2)
Use SEL0, SEL1, and SEL2 to select the watchdog timeout time. Writing to these bits does not clear or reset the watchdog timer. Refer to
Table 5-14. Bit Values for Selecting Watchdog Timeout Time
Period SEL2 SEL1 SEL0
17.8ms
0 0 0
71.1ms
0
284ms 0
0
1
1
0
1.14ms
0
4.55s
1
18.22s
1
72.8s
1
291s 1
1
0
0
1
1
1
0
1
0
1
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Programming Information
5-20
WD0 (Bit 3) and WD1 (Bit 4)
Use these bits to define the event that occurs on a watchdog timeout and to disable the watchdog timer. Reading these bits returns the last value written. Refer to
Table 5-15. Bit Values Defining Watchdog Timeout and Disabling
Description
Disabled (resets watchdog)
FPGA IRQX
Undefined
Undefined followed by reset (17ms delay before single board computer reset)
0
1
1
0
WD1
1
0
1
0
WD0
ALARM_SET (Bit 6)
Use this bit to control whether a watchdog timeout event generates an
FPGA Alarm.
❏
Write a logic 1 to cause the alarm signal to become active on a watchdog timeout event.
❏
Write a logic 0 to latch a watchdog timer event. Strobe the watchdog timer before enabling the latch to ensure that a watchdog timeout has not occurred before the latch is enabled.
Reading this bit returns the last written value.
CLR_STATUS (Bit 7)
Use this bit to reset the watchdog timer output latch.
❏
❏
Write a logic 1 to hold the watchdog timer output latch in a reset state.
Write a logic 0 to latch a watchdog timer event.
Reading this bit returns the last written value.
Computer Group Literature Center Web Site
Field Programmable Gate Array Registers
INTEN
Use the Interrupt Select Register (INTEN). Refer to Table 5-16 .
Table 5-16. Bit Descriptions for the INTUM Register
4 7 (most significant bit)
RES
6 5
RES RES RES
3 2 1 0 (least significant bit)
IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0
IRQSEL0 (Bit 0), IRQSEL1 (Bit 1) and IRQSEL2 (Bit 2)
These bits determine which IRQ is driven when an IRQ event triggers.
Refer to
Table 5-17. IRQ Line Bit Values
None
None
None
IRQ9
IRQ10
IRQ11
Interrupt
Line
None
None
None
None
None
IRQ5
IRQSEL3
0
0
0
0
0
0
0
0
1
1
1
1
IRQSEL2
0
0
0
0
1
1
1
1
0
0
0
0
IRQSEL1
0
0
1
1
0
0
1
1
0
0
1
1
IRQSEL0
0
1
0
1
0
1
0
1
0
1
0
1
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Programming Information
Table 5-17. IRQ Line Bit Values (Continued)
Interrupt
Line
None
None
None
None
IRQSEL3
1
1
1
1
IRQSEL2
1
1
1
1
IRQSEL1
0
0
1
1
IRQSEL0
0
1
0
1
5-22 Computer Group Literature Center Web Site
Field Programmable Gate Array Registers
SCIEN
The SCI Enable Register (SCIEN) defines the type of events that can generate an SCI. Refer to
Table 5-18. Bit Descriptions for the SCIEN Register
5 4 3 2 1 7 (most significant bit)
ENABLE
6
RES RES ENUM ALARM_A ALARM_B TEMP
0 (least significant bit)
SMB
SMB (Bit 0)
❏
Set to a logic 1 to allow generation of an SCI when SMB ALERT is active. SMB ALERT is active when logic 0.
❏
Write a logic 0 to this bit to disable an SCI for this event.
TEMP (Bit 1)
❏
Set to a logic 1 to allow generation of an SCI when TEMP is active.
TEMP is the ATF signal from the MMC2 and is active when logic 0.
❏
Write a logic 0 to this bit to disable an SCI for this event.
ALARM_A (Bit 3) and ALARM_B (Bit 2)
❏
Set to a logic 1 to allow the generation of an SCI when the
ALARM_A or ALARM_B go active. Alarm is active when logic 0.
❏
Write a logic 0 to these bits to disable an SCI for this event.
ENUM (Bit 4)
❏
Set to a logic 1 to allow generation of an SCI when the ENUM event occurs.
❏
Write a logic 0 to this bit to disable an SCI for this event.
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Programming Information
ENABLE
❏
Set to a logic 1 to allow generation of an SCI by one of the events above.
❏
Write a logic 0 to prevent the events from generating an SCI.
NMIEN
The NMI Enable Register (NMIEN) defines the events that can generate an NMI. Refer to
Table 5-19. Bit Descriptions for the NMIEN Register
7 (most significant bit)
ENABLE
6
RES
5 4 3 2 1 0 (least significant bit)
RES ENUM ALARM_A ALARM_B TEMP SMB
SMB (Bit 0)
❏
Set to a logic 1 to allow the generation of an NMI when the SMB
Alert is active. SMB Alert is active when logic 0.
❏
Write a logic 0 to this bit to disable an NMI for this event.
TEMP (Bit 1)
❏
Set to a logic 1 to allow the generation of an NMI when TEMP is active. TEMP is active when logic 0.
❏
Write a logic 0 to this bit to disable an NMI for this event.
ALARM_A (Bit 3) and ALARM_B (Bit 2)
❏
Set to a logic 1 to allow the generation of an NMI when the
ALARM_A or ALARM_B go active. ALARM is active when logic
0.
❏
Write a logic 0 to this bit to disable an NMI for this event.
5-24 Computer Group Literature Center Web Site
Field Programmable Gate Array Registers
ENUM (Bit 4)
❏
Set to a logic 1 to allow the generation of an NMI when the ENUM event occurs.
❏
Write a logic 0 to this bit to disable an NMI for this event.
ENABLE (Bit 7)
❏
Set to a logic 1 to allow the listed events to generate an NMI.
❏
Write a logic 0 to prevent the events from generating an NMI.
IRQEN
The IRQ Enable Register (IRQEN) defines the events that can generate an
IRQ. The IRQ generated is set by IRQ Select Register (IRQNUM) index
.
Table 5-20. Bit Descriptions for the IRQEN Register
7 (most significant bit)
ENABLE
6
RES
5 4 3 2 1 0 (least significant bit)
RES ENUM ALARM_A ALARM_B TEMP SMB
SMB (Bit 0)
❏
Set to a logic 1 to allow the generation of an IRQ when the SMB
Alert is active. SMB Alert is active when logic 0.
❏
Write a logic 0 to this bit to disable an IRQ for this event.
TEMP (Bit 1)
❏
Set to a logic 1 to allow the generation of an IRQ when TEMP is active. TEMP is active when logic 0.
❏
Write a logic 0 to this bit to disable an IRQ for this event.
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Programming Information
ALARM_A (Bit 3) and ALARM_B (Bit 2)
❏
Set to a logic 1 to allow the generation of an IRQ when the
ALARM_A or ALARM_B go active. Alarm is active when logic 0.
❏
Write a logic 0 to this bit to disable an IRQ for this event.
ENUM (Bit 4)
❏
Set to a logic 1 to allow the generation of an IRQ when the ENUM event occurs.
❏
Write a logic 0 to this bit to disable an IRQ for this event.
ENABLE (Bit 7)
❏
Set to a logic 1 to allow the listed events to generate an IRQ.
❏
Write a logic 0 to prevent the events from generating an IRQ.
ALEN
The Alarm Enable Register (ALEN) defines the events that generate an
Alarm output. Refer to Table 5-21
.
7 (most significant bit)
ENABLE
6
RES
Table 5-21. Bit Descriptions for the ALEN Register
5 4 3 2 1 0 (least significant bit)
RES ENUM ALARM_A ALARM_B TEMP SMB
SMB ALERT (Bit 0)
❏
Set to a logic 1 to allow the generation of an Alarm when the SMB
Alert is active. SMB Alert is active when logic 0.
❏
Write a logic 0 to this bit to disable an Alarm for this event.
5-26 Computer Group Literature Center Web Site
Field Programmable Gate Array Registers
TEMP (Bit 1)
❏
Set to a logic 1 to allow the generation of an Alarm when TEMP is active. TEMP is the ATF signal from the MMC2.
❏
Write a logic 0 to this bit to disable an Alarm for this event.
ALARM_A (Bit 3) and ALARM_B (Bit 2)
❏
Set to a logic 1 to allow the generation of an Alarm when the
ALARM_A or ALARM_B go active.
❏
Write a logic 0 to this bit to disable an Alarm for this event.
ENUM (Bit 4)
❏
Set to a logic 1 to allow the generation of an Alarm when the ENUM event occurs.
❏
Write a logic 0 to this bit to disable an Alarm for this event.
ENABLE (Bit 7)
❏
Set to a logic 1 to allow the listed events to generate an Alarm.
❏
Write a logic 0 to prevent the events from generating an Alarm.
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Programming Information
LEN
The Latch Enable Register (LEN) resets latches in the Field Programmable
Gate Array (FPGA) for the SMB Alert, TEMP ALARM_A and
ALARM_B alarms. Refer to
Table 5-22 . This register is write only. Write
a logic 1 to clear the latch. Writing a logic has no effect on the latch.
Table 5-22. Bit Descriptions for the LEN Register
7 (most significant bit)
6 5 4 3 2 1 0
UNUSED UNUSED UNUSED ENUM ALARM_A ALARM_B TEMP SMB
Alert
SMB Alert (Bit 0) - SMB Alert Signal
TEMP (Bit 1) - CPU Temperature Signal
ALARM_B (Bit 2) - LM78 Alarm B Signal
ALARM_A (Bit 3) - LM78 Alarm A Signal
ENUM (Bit 4) - Bus Enumeration Signal
5-28 Computer Group Literature Center Web Site
Field Programmable Gate Array Registers
POS
The Power-On Status Register (POS) checks for power-on condition. You can also read back written bits. Refer to
Table 5-23. Bit Descriptions for the POS Register
7 (most significan t bit)
6 5 4 3 2 1 0
UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED PWRON
PWRON (Bit 0)
The BIOS uses this bit to determine if it is booting from a power-up. After
BIOS POST this bit reads as a 1.
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5
Programming Information
LNACTRL
The LAN A Control Register (LNACTRL) controls the on-card LAN A controller. Bits written can also read back. Refer to
Table 5-24. Bit Descriptions for the LNACTRL Register
3 2 1 7 (most significant bit)
LAN A
ENABLE
6 5 4
LAN A
REAR
RES RES RES RES RES
0 (least significant bit)
RES
LAN A REAR (Bit 6)
The BIOS uses this bit to route LAN A signals to either the front or the rear connectors.
❏
Write a logic 0 to this bit to route LAN A signals to the front connector.
❏
Write a logic 1 to this bit to route LAN A signals to the rear connector.
The BIOS sets this bit according to CMOS setup.
LAN A ENABLE (Bit 7)
The BIOS uses this bit to enable LAN A.
❏
Write a logic 1 to this bit to enable LAN A for the operating system and application code.
❏
Write a logic 0 to this bit to disable it.
The BIOS sets this bit according to CMOS setup.
5-30 Computer Group Literature Center Web Site
Field Programmable Gate Array Registers
LNBCTRL
The LAN B Control Register (LNBCTRL) controls the on-card LAN B controller. Bits written can also read back. Refer to
Table 5-25. Bit Descriptions for the LAN B Register
2 1 7 (most significant bit)
LAN B
ENABLE
6
LAN B
REAR
5 4 3
RES RES RES RES RES
0 (least significant bit)
RES
LAN B REAR (Bit 6)
The BIOS uses this bit to route LAN B signals to either the front or the rear connectors.
❏
Write a logic 0 to this bit to route LAN B signals to the front connector.
❏
Write a logic 1 to this bit to route LAN B signals to the rear connector.
The BIOS sets this bit according to CMOS setup.
LAN B ENABLE (Bit 7)
The BIOS uses this bit to enable LAN B.
❏
Write a logic 1 to this bit to enable LAN B for the operating system and application code.
❏
Write a logic 0 to this bit to disable it.
The BIOS sets this bit according to CMOS setup.
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Programming Information
NVRAM
The Non-Volatile Random Access Memory (NVRAM) Register controls
Ethernet LAN B. Bits written can also read back. Refer to
Table 5-26. Bit Descriptions for the NVRAM Register
1 0 7 (most significant bit)
NVRAM
ENABLE
6 5 4 3
UNUSED UNUSED BATTLO BANK
SEL 3
2
BANK
SEL 2
BANK
SEL 1
BANK
SEL 0
BANK SEL0 (Bit 0), BANK SEL1 (Bit 1), BANK SEL2 (Bit 2)
These bits select the 32K NVRAM memory bank. Refer to Table 5-27
.
Table 5-27. Bit Selections for the 32K NVRAM Memory Bank
32K BANK Offset SEL 3
Bank 0 00000h 0
Bank 1
Bank 2
04000h
08000h
0
0
Bank 3
Bank 4*
Bank 5*
Bank 6*
0C000h
10000h
14000h
18000h
0
0
0
0
Bank 7*
Bank 8*
Bank 9*
Bank 10*
Bank 11*
Bank 12*
Bank 13*
Bank 14*
Bank 15*
1C000h
20000h
24000h
28000h
2C000h
30000h
34000h
38000h
3C000h
0
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
0
1
1
0
1
0
0
SEL 2
0
0
1
1
0
1
0
1
1
0
0
1
1
0
0
1
SEL 1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
SEL 0
0
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Field Programmable Gate Array Registers
BATTLO (Bit 4)
This bit reflects the battery low signal from the NVRAM’s power controller. This bit is read only.
NVRAM ENABLE (Bit 7)
This bit enables the NVRAM. A "1" enables NVRAM and a "0" disables it. When enabled the selected 32K bank is accessible in ISA space at address D000:0h.
USBCTRL
The USB Control Register (USBCTRL) controls the on-card USB routing.
Bits written can also read back. Refer to
Table 5-28. Bit Descriptions for the USBCTRL Register
2 1 7 (most significant bit)
RES
6
USB
REAR
5 4 3
RES RES RES RES RES
0 (least significant bit)
RES
USB REAR (Bit 6)
The BIOS uses this bit to route the on-card USB signals to either the front or the rear connectors.
❏
Write a logic 0 to this bit to route USB signals to the front connector.
❏
Write a logic 1 to this bit to route USB signals to the rear connector.
The BIOS sets this bit according to CMOS setup.
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Programming Information
FLBCTRL
The Flash BIOS Control (FLBCTRL) Register controls the write protect line on the BIOS flash memory part. Bits written can also read back. Refer to
Table 5-29. Bit Descriptions for the FLBCTRL Register
4 3 2 1 7 (most significant bit)
WP-
6 5
RES RES RES RES RES RES
0 (least significant bit)
RES
WP- (Bit 7)
This bit enables the Flash BIOS boot block for updating.
❏
Write a logic 0 to this bit to protect the BIOS boot block.
❏
Write a logic 1 to this bit to open it for writing.
5-34 Computer Group Literature Center Web Site
A
Updating the BIOS
A
The BIOS is software upgradeable. You can update the BIOS without installing a new ROM BIOS chip using the:
❏
Phoenix Phlash Utility, a DOS application recommended for most
BIOS updates
❏
Embedded Flash, an integrated update function used to update the
BIOS in some real-time or deeply embedded applications
Update Files
You can get BIOS updates on floppy disks or download them from the
Motorola Computer Group website. Contact your local sales representative for information about getting updates and update notices.
A BIOS update typically includes these files. Refer to
Table A-1. Typical BIOS Update
Filename
README.TXT
RELNOTES.TXT
REFLASH.BAT
PHLASH.EXE
PLATFORM.BIN
BIOS.ROM
Function
Platform specific BIOS update procedures
Release notes and supported hardware
Batch file for running the Phlash program with the necessary platform specific command line options
Phlash application that programs the Flash memory
Provides configuration information and platform dependent functions for the Phlash utility
BIOS image to program into Flash memory
A-1
A
Updating the BIOS
Phoenix Phlash Utility
Use the Phoenix Phlash utility for these tasks:
❏ updating the current BIOS with a new version
❏ saving the current BIOS to a file
❏ restoring a BIOS from a saved image
Installing Phoenix Phlash
You can run Phoenix Phlash directly from floppy disk or, for better performance, you can install the files on your hard disk.
To install Phoenix Phlash on your hard disk:
1. Insert the distribution diskette into drive A:.
2. Copy the contents of the diskette into a local directory such as
C:\PHLASH
3. Store the distribution diskette in a safe place
Executing Phoenix Phlash
For specific instructions about how to flash your BIOS from the command line, refer to the README.TXT file on the distribution diskette. In most cases, you can execute the REFLASH.BAT file.
A-2
Note
Keep a record of any changes you make to the BIOS defaults so that you can restore them if necessary after the BIOS updates.
The Phlash utility also lets you create a copy of your current BIOS image.
To create a copy, enter phlash/RO on the command line. Phlash reads the current contents of the BIOS Flash memory and creates a file named
BIOS.BAK.
To execute Phlash in command line mode:
1. Move to the Phoenix Phlash directory
Computer Group Literature Center Web Site
Phoenix Phlash Utility
2. Enter phlash [options] [filename] on the command line where: a. [options] is the command line options string specified in the
README.TXT file on the BIOS update disk, and b. [filename] is the name of the BIOS image. If no filename is specified, BIOS.ROM is assumed.
Phoenix Phlash automatically updates or replaces the current BIOS with the new BIOS image.
Note
Phlash may fail and display this message if your system uses memory managers:
Cannot flash when memory managers are present
If you see this message after you execute Phlash, you must disable the memory manager on your system. Refer to
3. To make changes to the BIOS configuration after reboot.
Press <F2> during POST to enter the Setup Utility.
Disabling Memory Managers
To avoid failure when flashing, you must disable the memory mangers that load from CONFIG.SYS and AUTOEXEC.BAT. Use one of these procedures for disabling the memory managers:
❏
Press the <F5> key if you are using DOS 5.0 or above, or
❏
Create a boot diskette
DOS 5.0 (or later version)
If you do not use at least DOS 5.0, or if you run Windows 95, Windows
98, Windows NT, or Windows 2000, you must create a boot diskette to
bypass any memory managers. Refer to
For DOS 5.0 and later, use this procedure to disable any memory managers on your system:
A
http://www.motorola.com/computer/literature A-3
A
Updating the BIOS
1. Restart your system
2. Press <F5> when this message displays:
Starting MS-DOS
When you press <F5>, DOS bypasses the CONFIG.SYS and
AUTOEXEC.BAT files, and does not load memory managers.
You can now execute Phlash.
Creating a Boot Diskette
To bypass memory managers in DOS versions earlier than 5.0 or when running Windows 95, Windows 98, Windows NT, or Windows 2000, you can use a boot diskette. To create a boot diskette:
1. Insert a diskette into your A: drive.
2. Enter format a: /s from the command line.
Note
This command does not create a bootable system disk when performed under Windows NT or Windows 2000. If you run
Windows NT or Windows 2000 and you do not configure an alternate startup operating system, you may need to create a boot disk on another system that uses a DOS based operating system.
3. Reboot your system using the boot disk in the A: drive.
Your system should now boot without loading the memory managers, and you can execute Phlash.
Embedded Flash
In most cases, you should use the Phoenix Phlash utility to update the
BIOS. However, some releases of the BIOS Setup Utility also include an integrated update function, Embedded Flash, that lets you reprogram the
Flash memory without booting from an operating system. You can also use
Embedded Flash with the Remote Console feature to update the BIOS in deeply embedded or remote applications.
A-4 Computer Group Literature Center Web Site
Phoenix Phlash Utility
You can access the Embedded Flash function from the Advanced menu of the BIOS Setup Utility. Refer to
Executing Embedded Flash
Embedded Flash lets you update the BIOS from:
❏ a floppy disk installed in your system’s primary floppy-disk drive
❏ a serial connection using Remote Console
Updating from Floppy Disk
To update the BIOS from disk:
Note
Keep a record of any changes you make to the BIOS defaults so that you can restore them if necessary after the BIOS updates.
1. Power-on or restart the computer, then access the BIOS Setup
Utility by pressing <F2> during POST.
2. Select Embedded Flash from the Advanced menu and press
<Enter> to open the Embedded Flash submenu.
Refer to
for more information.
3. Select Program BIOS as the Task.
4. Select Diskette Drive as the Device.
Insert a floppy disk containing the new BIOS image into drive A:.
Note
If you do not insert a disk and try to load a BIOS image, the system may hang. You must also type the file name and path in the file field.
Embedded Flash currently supports only FAT file systems
(FAT12, FAT16, and FAT32) and only writes to or reads from the active (bootable) partition of a drive.
A
http://www.motorola.com/computer/literature A-5
A
Updating the BIOS
5. Type the file name and path in the File field (for example;
\flash\BIOS.ROM.
6. Select Yes from the Clear CMOS field.
If the CMOS table is modified in the new BIOS image, the system may become inoperable if you do not clear CMOS when you update the BIOS.
7. Select Execute and press <Enter>.
The Flash memory is reprogrammed with the new BIOS image.
Reprogramming may take several minutes.
When reprogramming completes, the system automatically reboots.
8. Press <F2> during POST to enter the Setup Utility and make needed changes if any to the BIOS configuration.
Updating with Remote Console
Use this procedure to update the BIOS from a serial connection using the
Remote Console. For information on configuring the BIOS to give you
.
Note
Read these instructions completely before you proceed.
Keep a record of any changes you make to the BIOS defaults so you can restore them if necessary after the BIOS updates.
1. Make sure your system is properly configured for remote access and
that your remote terminal connection is active. Refer to
2. Power-on or restart the computer, and access the BIOS Setup Utility by pressing <F2> during POST.
3. Select Embedded Flash from the Advanced menu and press
<Enter> to open the Embedded Flash submenu. Refer to
.
4. Select Program BIOS as the Task.
5. Select Remote Console (XMODEM) as the Device.
A-6 Computer Group Literature Center Web Site
Phoenix Phlash Utility
6. Select Yes from the Clear CMOS field.
If the CMOS table is modified in the new BIOS image, the system may become inoperable if you do not clear CMOS when you update the BIOS.
If the BIOS default for Remote Console is Disabled, clearing
CMOS may disable remote access after a new BIOS image is installed.
7. Select Execute and press <Enter>.
Embedded Flash waits for you to transmit a new image.
8. Send the new BIOS image from your remote terminal using the
XMODEM transfer protocol. This may take several minutes.
Once the image file is received, the Flash memory is reprogrammed with the new BIOS image. Reprogramming may take several minutes.
Do not power-off or reset the system.
When reprogramming is complete, the system automatically reboots.
9. Press <F2> during POST to enter the Setup Utility and make any changes to the BIOS configuration.
A
http://www.motorola.com/computer/literature A-7
A
Updating the BIOS
A-8 Computer Group Literature Center Web Site
B
Remote Console Escape Keys
B
Because terminals and terminal emulation software vary in their ability to transmit special function keyboard information such as function keys or navigation keys, Remote Console defines a range of escaped character sequences to emulate such keys or key combinations. This appendix lists the sequences that are defined. For more information about Remote
Console, see
Defined Sequences
Table B-1 lists the sequences defined in Remote Console. When Remote
Console detects one of these escape sequences, it translates it to the corresponding key, then passes the information to the software. For example; pressing Esc followed by O followed by P at the remote terminal is equivalent to pressing the F1 key.
Note that characters are case-sensitive. Esc, O, P is not the same as Esc,
O, p. Also note that letters and numbers are not mixed. The O in Esc, O,
P is the capital letter O. The 0 in Esc, [, 2, 0, ~ is the number zero. Some keys have more than one escape sequence.
Table B-1. Remote Console Escape Sequences
Key
Esc
Shift Tab
Up Arrow
Down Arrow
Left Arrow
Right Arrow
Home
End
Escape
Sequence
Esc Esc
Esc [ Z
Esc [ A
Esc [ B
Esc [ D
Esc [ C
Esc [ H
Esc [ K
B-1
B
Remote Console Escape Keys
Table B-1. Remote Console Escape Sequences (Continued)
Key
F8
F8
F9
F10
F10
F11
F12 control F1 control F2 control F3
F6
F6
F7
F7
F4
F4
F5
F5
F1
F2
F3
F3
Page Down
Page Up
Insert
Print Screen
Shift Print
Screen
Escape
Sequence
Esc [ U
Esc [ V
Esc [ @
Esc [ i
Esc 2 i
Esc O P
Esc O Q
Esc O R
Esc O w
Esc O S
Esc O x
Esc O t
Esc [ M
Esc O u
Esc [ 1 7 ~
Esc O q
Esc [ 1 8 ~
Esc O r
Esc [ 1 9 ~
Esc [ 2 0 ~
Esc O p
Esc [ 2 1 ~
Esc [ 2 3 ~
Esc [ 2 4 ~
Esc [ 6 4 ~
Esc [ 6 5 ~
Esc [ 6 6 ~
B-2 Computer Group Literature Center Web Site
Defined Sequences
Table B-1. Remote Console Escape Sequences (Continued)
Key
control F4 control F5 control F6 control F7 control F8 control F9 control F10 control F11 control F12
Escape
Sequence
Esc [ 6 7 ~
Esc [ 6 8 ~
Esc [ 6 9 ~
Esc [ 7 0 ~
Esc [ 7 1 ~
Esc [ 7 2 ~
Esc [ 7 3 ~
Esc [ 7 4 ~
Esc [ 7 5 ~
B
http://www.motorola.com/computer/literature B-3
B
Remote Console Escape Keys
B-4 Computer Group Literature Center Web Site
C
Network Boot
C
You can configure the CPV5350 to boot from a network resource using an
Ethernet port. This appendix explains how to configure the BIOS for network boot and gives you information about the Ethernet boot ROM for the on-board Ethernet devices.
Enabling Network Boot
You must properly configure both the BIOS and the Ethernet option ROM before you can boot from a network resource using an Ethernet port.
To configure the system for network boot:
❏ make sure you enable in the BIOS the on-board Ethernet controller and option ROM. See
❏ specify the desired network boot configuration using the Boot
Agent Setup program for that controller. See
❏
make the Intel Boot Agent the first boot device. See
.
C-1
C
Network Boot
Intel Boot Agent
The on-board Ethernet option ROMs are loaded with Intel Boot Agent.
The Intel Boot Agent configures and controls the network boot features of the Ethernet controller. To enable the Boot Agent, make sure to enable (in
the BIOS) the on-board Ethernet controller and option ROM. See the
This message displays when the enabled Boot Agent initializes during
POST.
C-2
Note
If the message does not display, you can still enter the Boot Agent
Setup menu by pressing <Ctrl-S>. In the Setup menu, you can enable display of the startup message and specify how long it should display before boot. See
.
Computer Group Literature Center Web Site
Intel Boot Agent
If you configure the BIOS and Boot Agent for network boot, the Boot
Agent attempts to boot from a network server and displays information similar to this, depending on the boot configuration:
C
The number (nnn) indicates the number of seconds before the Boot Agent continues by using the default choice in the boot menu. The choices in the boot menu depend on the network server.
http://www.motorola.com/computer/literature C-3
C
Network Boot
Boot Agent Setup
The Boot Agent Setup Menu lets you configure an on-board Ethernet controller for network boot.
To run the Boot Agent Setup Menu, enable the on-board Ethernet controller and option ROM in the BIOS and press <Ctrl-S> during system boot. See the
on page 2-24 . A screen similar
to this appears:
C-4
Note
The Boot Agent Setup Menu does not display correctly using
Remote Console.
Computer Group Literature Center Web Site
Intel Boot Agent
Boot Agent Setup Options
Table C-1 describes the menu fields available in the Boot Agent Setup
program.
Table C-1. Boot Agent Setup Menu Fields
Feature
Network Boot
Protocol
Boot Order
Default
PXE
Options
PXE
RPL
Use BIOS
Setup Boot
Order
Use BIOS Setup
Boot Order
Description
Preboot eXecution Environment protocol (for use with WfMcompatible network management programs)
Remote Program Load protocol
(for legacy-style remote booting)
Uses the boot priority specified in the BIOS Setup Boot Device
Priority submenu (see
). Because the BIOS on the
CPV5350 supports the BIOS
Boot Support (BBS) specification and allows selection of the boot order in the Setup program, this is the only option available.
C
http://www.motorola.com/computer/literature C-5
C
Network Boot
Table C-1. Boot Agent Setup Menu Fields (Continued)
Feature Default
Show Setup Prompt Enabled
Setup Menu Wait
Time
2 seconds
Legacy OS Wakeup
Support
Disabled
Options
Enabled
Disabled
2, 3, 5, 0 seconds
Disabled
Enabled
Description
Enables display of the Ctrl-S prompt during POST
Disables display of the Ctrl-S prompt during POST (you can still press Ctrl-S to enter Boot
Agent Setup)
Specifies the number of seconds the Boot Agent waits for you to press Ctrl-S during the boot process
Allow/disallow non-Windows
OS to use adapter remote wakeup capability. Select Disabled for
ACPI (Advanced Configuration and Power Interface) compliant operating systems. Select
Enabled for non-Windows operating systems if your system supports remote wakeup.
Cancelling Network Boot
When you select an on-board Ethernet as a network boot device, you can abort the network boot by pressing <Esc> or <Ctrl-C>. The PXE then resets the Ethernet device, removes itself from RAM, and returns control to the BIOS.
C-6 Computer Group Literature Center Web Site
D
Related Documentation
D
Motorola Computer Group Documents
The publications listed in
Table D-1 give you more information about the
CPV5350 Single Board Computer and Transition Module. To purchase manuals you can contact:
❏ your local Motorola sales office
❏ the Motorola Computer Group’s World Wide Web literature site, http://www.motorola.com/computer/literature
Table D-1. Motorola Computer Group Documents
Document Title
CPV5350 CompactPCI Single Board Computer and
Transition Module Installation Guide
CompactPCI CPV5350 Windows NT
®
4.0 Operating
System Installation Guide
Motorola Publication Number
CPV5350A/IHx
CPV5350WNTA/RNx
To get the most up-to-date product information in PDF format, visit http://www.motorola.com/computer/literature .
URLs
These URLs (uniform resource locators) may give you helpful sources of more information about this product, related services, and development tools. We verify these URLs but they can change without notice.
❏
Motorola Computer Group, http://www.motorola.com/computer
❏
Motorola Computer Group OEM Services, http://www.motorola.com/computer/support
D-1
D
Related Documentation
❏
PCI Industrial Computer Manufacturer’s Group (PICMG) Hot
Swap Specification, http://www.picmg.org
❏
Peripheral Component Interconnect (PCI) Local Bus Specification,
Revision 2.1 PCI Special Interest Group, http://www.pcisig.com
❏
PCI to PCI Bridge Architecture Specification, Revision 1.0 PCI
Special Interest Group, http://www.pcisig.com
❏
CompactPCI Specification, Revision 2.1 PCI Industrial Computer
Manufacturers Group, http://www.picmg.com
❏
CompactPCI Hot Swap Specification, Revision 1.0 PCI Industrial
Computer Manufacturers Group, http://www.picmg.com
❏
BIOS Boot Specification Version 1.01, Phoenix Technologies, Inc., http://www.phoenix.com/PlatSS/products/specs.html
❏
"El Torito" Bootable CD-ROM Specification, Version 1.0, Phoenix
Technologies, Inc., http://www.phoenix.com/PlatSS/products/specs.html
❏
Wired for Managment (WfM), Preboot Execution Environment
(PXE), Intel Corporation, http://developer.intel.com/ial/wfm/
❏
System Managment BIOS Reference Specification, Revision 2.3.1
Distributed Managment Task Force, Inc., http://www.dmtf.org/spec/bios/DSP0119.pdf
❏
PhoenixBIOS 4.0 Release 6 User’s Manual, Phoenix Technologies, http://www.phoenix.com/pcuser/PDF-Files/userman.pdf
These URLs give you access to the manufacturers’ data sheets for information about the major chips used on the CPV5350.
❏
Intel Processor, Pentium II (MMC-2), Intel Corporation, http://developer.intel.com/design/mobile/datashts/243668.htm
❏
Intel 440BX AGPset: 82443BX Host Bridge/Controller, Intel
Corporation, http://developer.intel.com/design/chipsets/440bx/
❏
Intel 82371 EB PCI-to-ISA/IDE Xcelerator (PIIX4E) Specification
Update, Intel Corporation, http://developer.intel.com/design/chipsets/specupdt/290635.htm
D-2 Computer Group Literature Center Web Site
Motorola Computer Group Documents
❏
Intel 82559 Fast Ethernet Multifunction PCI/Cardbus Controller,
Intel Corporation, http://developer.intel.com/design/network/datashts/738259.htm
❏
Chips and Technologies 69000 AGP Video, Asiliant Technologies, http://www.asiliant.com/69000.htm
❏
Intel i740 AGP Video, Intel Corporation, http://support.intel.com/support/graphics/intel740/
❏
SMC FDC37C67x Super I/O, Standard Microsystems Corporation, http://www.smsc.com/main/catalog/fdc37c67x.html
❏
Intel 21154 PCI-to-PCI Bridge, Intel Corporation, http://developer.intel.com/design/bridge/quicklist/dsc-21154.htm
❏
LM78 Microprocessor System Hardware Monitor, National
Semiconductor Corporation, http://www.national.com/pf/LM/LM78.html
❏
MAX1617 Remote/Local Temperature Sensor with SMBus Serial
Interface, Maxim Corporation, http://dbserv.maximic.com/quick_view2.cfm?pdf_num=1855
D
http://www.motorola.com/computer/literature D-3
D
Related Documentation
D-4 Computer Group Literature Center Web Site
Index
A
advanced menu
ALEN
B
beep code 4-2
BIOS
setup
test points
updating from floppy disk
updating the
updating with remote console
boot agent setup options
boot agent setup
boot diskette
C
check points, POST
checkpoint codes
D
DEVNUM
DMA channels
E
ECTRL
error 4-2 port 80h codes
escape
sequences
F
field help window
Field Programmable Gate Array watchdog timer
Field Programmable Gate Array Registers
fixed disk drives
FLBCTRL
floppy configuration submenu
floppy interface
FPGA
G
general help window
H
hard disk features
hardware requirements
I
I/O Address Map
Intel boot agent
INTUM
IN-1
I
N
D
E
X
IRQEN
K
keyboard/mouse interface
L
legend bar
LNACTRL
LNBCTRL
local bus
M
main menu bar
main menu bar
main menu selections
Memory Managers disabling
memory menu
menu bar
messages
PhoenixBIOS
models xv
N
NMIEN
O
overview
PhoenixBIOS
P
parallel port
PCI
Peripheral Component Interconnect
Phlash
IN-2
Index
PHLASH.EXE
PhoenixBIOS
messages
port 80h codes
POST
test points
POST terminal errors
power-on self test
power-on self tests
programming information
R
README.TXT
REFLASH.BAT
register descriptions
registers
FPGA
requirements
ROM BIOS
S
SCIEN
serial ports
Computer Group Literature Center Web Site
setup program
setup screen
starting setup
STAT
system hardware requirements 1-4
T
terminal error 4-2 test points
test, RAM 4-1 timer
troubleshooting
U
URLs (uniform resource locators)
USBCTRL
V
video controller 5-6
W
wait states
watchdog timer
watchdog timer operation
WDCFG
http://www.motorola.com/computer/literature IN-3
I
N
D
E
X
Index
I
N
D
E
X
IN-4 Computer Group Literature Center Web Site
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Table of contents
- 7 Table of Contents
- 11 List of Figures
- 13 List of Tables
- 15 About This Manual
- 15 Summary of Changes
- 16 Overview of Contents
- 17 Comments and Suggestions
- 17 Conventions Used in This Manual
- 19 PhoenixBIOS Overview
- 19 What is a ROM BIOS?
- 20 ROM BIOS Functions
- 21 Power-On Self Test
- 23 PhoenixBIOS POST Function Keys
- 23 Phoenix MultiBoot
- 25 BIOS Setup
- 25 Using the Phoenix Setup Program
- 25 Starting Setup
- 26 The Setup Interface
- 27 The Menu Bar
- 27 The Legend Bar
- 28 The Field Help Window
- 29 The General Help Window
- 30 Main Menu Selections
- 31 Memory Menu
- 34 The Advanced Menu
- 36 Resetting Extended System Configuration Data
- 36 Floppy Configuration Submenu
- 37 Floppy Configuration Submenu Options
- 38 IDE Configuration Submenu
- 39 IDE Configuration Submenu Options
- 40 Masters and Slaves
- 40 Primary/Secondary Master/Slave Submenus
- 42 Primary/Secondary Master/Slave Submenu Options
- 43 I/O Device Configuration Submenu
- 44 I/O Device Configuration Submenu Options
- 48 PCI Configuration Submenu
- 49 PCI Configuration Submenu Options
- 50 HA Configuration Submenu
- 51 HA Configuration Submenu Options
- 53 PCI/PNP IRQ Configuration Submenu
- 54 PCI/PNP IRQ Configuration Submenu Options
- 55 Remote Console Submenu
- 55 The Remote Console Feature
- 56 Remote Console Submenu Options
- 57 Screen Lines
- 58 Active After POST
- 58 Embedded Flash Submenu
- 59 Embedded Flash Submenu Options
- 62 Security Menu
- 62 Security Menu Options
- 64 User and Supervisor Passwords
- 65 Status Menu
- 66 Status Menu Options
- 66 Boot Menu
- 67 Boot Menu Options
- 68 Boot Device Priority Submenu
- 69 Using the Boot Device Priority Submenu
- 70 Network Boot
- 70 Exit Menu
- 71 Exit Menu Options
- 73 Phoenix BIOS Messages
- 73 PhoenixBIOS Messages
- 79 Power-On Self Tests
- 79 Recoverable Power-On Self Test Errors
- 80 POST Terminal Errors
- 80 Test Points and Beep Codes
- 89 Programming Information
- 89 Peripheral Component Interconnect (PCI) Local Bus
- 90 Watchdog Timer
- 91 Watchdog Timer Operation
- 91 Enabling the timer
- 92 I/O Address Map
- 94 Memory Address Mapping
- 94 Video Controller
- 95 EIDE Interface
- 95 Floppy Interface
- 96 Parallel Port
- 96 Serial Ports
- 96 USB
- 97 Keyboard/Mouse Interface
- 97 DMA Channels
- 98 Interrupts
- 99 Field Programmable Gate Array Registers
- 103 Register Descriptions
- 105 STAT
- 106 ECTRL
- 107 WDCFG
- 109 INTEN
- 111 SCIEN
- 112 NMIEN
- 113 IRQEN
- 114 ALEN
- 116 LEN
- 117 POS
- 118 LNACTRL
- 119 LNBCTRL
- 120 NVRAM
- 121 USBCTRL
- 122 FLBCTRL
- 123 Updating the BIOS
- 123 Update Files
- 124 Phoenix Phlash Utility
- 124 Installing Phoenix Phlash
- 124 Executing Phoenix Phlash
- 125 Disabling Memory Managers
- 125 DOS 5.0 (or later version)
- 126 Creating a Boot Diskette
- 126 Embedded Flash
- 127 Executing Embedded Flash
- 127 Updating from Floppy Disk
- 128 Updating with Remote Console
- 131 Remote Console Escape Keys
- 131 Defined Sequences
- 135 Network Boot
- 135 Enabling Network Boot
- 136 Intel Boot Agent
- 138 Boot Agent Setup
- 139 Boot Agent Setup Options
- 140 Cancelling Network Boot
- 141 Related Documentation
- 141 Motorola Computer Group Documents
- 145 Index