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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
DS92LV3241/DS92LV3242
Demonstration Kit
User Manual
P/N LV32EVK01
Rev 1.0
National Semiconductor Corporation
Date: 9/28/2009
Page 1 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Table of Contents
......................................................................................... 7
............................................................................ 9
.................................................................................. 11
............................................................................. 12
National Semiconductor Corporation
Date: 9/28/2009
Page 2 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Introduction:
National Semiconductor’s SERDES evaluation kit contains one (1) DS92LV3241
Serializer (Tx) board, one (1) DS92LV3242 Deserializer (Rx) board, and one (1) standard (~2) meter CAT 6 style cable assembly.
Note: The demo boards are not intended for EMI testing. These demo boards were designed for easy accessibility to device pins with tap points for monitoring or applying signals, and additional pads for termination.
The DS92LV3241/3242 chipset supports a variety of display and imaging applications.
Typical applications include: navigation displays, automated teller machines (ATMs),
POS, video cameras, global positioning systems (GPS), portable equipment/instruments, factory automation, printers, etc.
The DS92LV3241 and DS92LV3242 can also be used as a 32-bit general purpose
LVDS Serializer and Deserializer chipset designed to transmit data at clocks speeds ranging from 20 to 50 MHz in dual mode or 40MHz to 85 MHz in quad mode.
The DS92LV3241 serializer board accepts LVCMOS input signals at either 3.3V or
1.8V.
Note: IOV
DD
must be set to 3.3V for 3.3V input levels or 1.8V for 1.8V input levels.
The LVDS Serializer converts the LVCMOS parallel lines into either two (2) serialized
LVDS data pairs with an embedded LVDS clock on each channel or four (4) serialized
LVDS data pairs with an embedded LVDS clock on each channel.
The DS92LV3242 deserializer board accepts the LVDS serialized data streams with an embedded clock on each LVDS stream and converts the data back into parallel
LVCMOS signals and clock. Note that NO reference clock is needed to prevent harmonic lock as with other devices currently on the market.
Suggested equipment to evaluate the chipset include: an LVCMOS signal source, such as a video generator, word generator, or pulse generator and oscilloscope.
The user needs to provide the proper LVCMOS clock and data inputs to the serializer and also provide a proper interface from the deserializer output to an LCD panel or test equipment. The serializer and deserializer boards can also be used to evaluate device parameters.
National Semiconductor Corporation
Date: 9/28/2009
Page 3 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Refer to the proper datasheet information on Chipsets (Tx/Rx) provided on each board for more detailed information.
Contents of the Evaluation Kit:
1) One serializer board with the DS92LV3241
2) One deserializer board with the DS92LV3242
3) One 2-meter standard CAT 6 cable assembly
4) Evaluation Kit Documentation (this manual)
5) DS92LV3241/3242 Datasheet
National Semiconductor Corporation
Date: 9/28/2009
Page 4 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
How to set up the Evaluation Kit:
The PCB routing for the serializer input pins (TxIN) have been laid out to accept incoming LVCMOS signals from a 50-pin IDC connector. The serial interface between the DS92LV3241 and the DS92LV3242 uses a standard RJ-45 connector and CAT-5/6 cable assembly (small CAT-6 cable provided). The PCB routing for the Rx output pins
(RxOUT) are accessed through a 50-pin IDC connector. Please follow these steps to set up the evaluation kit for bench testing and performance measurements:
1) A two (2) meter CAT 6 connector
/ cable assembly has been included in the kit.
Connect one side of cable to the serializer board and the other side to the deserializer board. This completes the LVDS interface connection.
2) Jumpers and switches have been configured at the factory; they should not require any changes for immediate operation of the chipset. See text on Configuration
Settings for more details. From the transmitting test equipment, connect a flat cable or fly wires (not supplied) to the Serializer board and connect another flat cable or fly wires (not supplied) from the Deserializer board to the receiving test equipment.
Caution: The LVCMOS input levels should be within the specified range for optimal performance, not to exceed the absolute maximum rating of -0.3V to (V
DD
+0.3V).
Note: For 50 ohm signal sources, add 50 ohm parallel termination resistors R1-R32 on the DS92LV3241 Serializer board and provide appropriate 3.3V LVCMOS input signal levels into TxIN[32:0] and TxCLKIN.
Note: The Rx board may require the use of LVCMOS buffers to drive 50 ohm inputs
found in some test equipment.
3) Power for the Tx and Rx boards must be supplied externally through Power Jack
(V
DD
). Grounds for both boards are connected through Power Jack (V
SS
) (see section below).
Power Connection:
The serializer and deserializer boards must be powered by supplying power externally through J7 (V
DD
) and J8 (V
SS
) on the serializer Board and J6 (VDD) and J7 (VSS) on the deserializer board. Note +4V is the absolute MAXIMUM voltage (not operating voltage) that should ever be applied to the serializer (DS92LV3241) or deserializer
(DS92LV3242) VDD terminal. Damage to the device(s) can result if the voltage maximum is exceeded.
National Semiconductor Corporation
Date: 9/28/2009
Page 5 of 34
J1
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Serializer (Tx) Board Description:
The 50-pin IDC connector J1 accepts 32 bits of LVCMOS RGB/generic data (TxIN0-
TxIN32) along with the clock input (TCLK).
The SERDES serializer board is powered externally from the J7 (V
DD
) and J8 (V
SS
) connectors shown below. For the serializer to be operational, the Power Down
(PWDNB) switch on S1 must be set HIGH. The board is factory configured (with series
0.1
μF capacitors on the LVDS outputs. Rising or falling edge input clock is also selected on S1-TRFB: HIGH (rising) or LOW (falling). JP2 is configured from the factory to be tied to V
DD
(3.3V), which sets the LVCMOS I/O pins to operate at 3.3V logic levels.
The RJ-45 connector P1 (on the bottom side of the board) provides the interface connection to the LVDS signals to the deserializer board. f
J7, J8
Note:
V
DD
and VSS MUST be applied externally here.
(IOV
DD
default setting -
IOV
DD
is connected to V
DD
)
c
LVDS OUTPUTS d
LVCMOS INPUTS e
FUNCTION CONTROLS f
POWER SUPPLY g
50
Ω INPUT
TERMINATION
(For 50
Ω
signal sources, populated with 50ohm resistors to provide proper termination.)
S1 d e g g g g
ASSY DS92LV3241 TX DEMO REV
National Semiconductor Corporation c
P1 (BOTTOM SIDE)
(RJ-45)
Date: 9/28/2009
Page 6 of 34 e
VR1, JP4
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Configuration Settings for the Serializer Board
S1: Serializer Input Features Selection
Reference Description Input = L Input = H
PWDNB PoWerDowN Bar Powers Normal
Down operation
(Default)
BISTEN BIST ENable BIST BIST mode disabled
(Default)
enabled
TRFB Latch input data on Rising or
Falling edge of
TCLK
Falling
Edge
(Default)
MODE
DB/Q
RES_0
V SEL
Dual or Quad mode
REServed
LVDS output V
OD
SELect
Dual mode
(Default)
MUST be tied low for normal operation
(Default)
≈440 mV
(Default)
JP2: Serializer Input Features Selection
P-P
Rising
Edge
Quad mode
Not allowed
≈850 mV
P-P
Reference Description Default External
Connected to VDD (J7) option.
For 1.8V input swing IOVDD is connected to
VDDI. VDDI must be applied on JP1 pin 1.
S1
JP2
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
JP4,VR1: Pre-Emphasis Feature Selection
Reference Description OPEN
JP4 Pre-Emphasis – helps to increase the eye pattern opening in the LVDS streams by providing current boost
(floating)
Disabled – no jumper
(Default)
(Path to GND)
Enabled –
With jumper
JP4 &
VR1
Clockwise Counter-
Clockwise
Pre-Emphasis adjustment
(via screw)
JP1 MUST have a jumper to use VR1 potentiometer.
VR1 = 0
Ω to 20 kΩ,
JP1 + VR1 + 12 k
Ω
(
R34) =
~12 k
Ω (maximum preemphasis) to
~32 k
Ω (minimum preemphasis*).
I
PRE
= [1.2/(R
PRE
)] x 40,
R
PRE (minimum)
> 12 k
Ω
*Note: maximum is based on resistor value. In this case ~32K
Ω
value is based on the ~12k
Ω
fixed resistor plus ~20K
Ω
maximum potentiometer value. User can use hundreds of k Ohms to reduce the preemphasis value.
increases
R
PRE
value which decreases preemphasis decreases
R
PRE
value which increases preemphasis
Pre-emphasis user note:
Pre-emphasis must be adjusted correctly based on application frequency, cable quality, cable length, and connector quality. Maximum pre-emphasis should only be used under worse case conditions; for example at the upper frequency specification of the part and/or low grade cables at maximum cable lengths. Typically all that is needed is minimum pre-emphasis. Users should start with no pre-emphasis first and gradually apply pre-emphasis until there is clock lock and no data errors. The best way to monitor the pre-emphasis effect is to hook up a differential probe across the AC-coupling capacitors for the (+) and (-) inputs of the LVDS channels on the DS92LV3242 Rx demo board (NOT across the AC-coupling capacitors for the LVDS channels on the
DS92LV3241 Tx demo board).
National Semiconductor Corporation
Date: 9/28/2009
Page 8 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Serializer LVCMOS and LVDS Pinout by IDC Connector
The following two (2) tables illustrate how the serializer inputs are mapped to the IDC connector J1, the LVDS outputs on the RJ-45 connector P1 pinout.
Note: Labels are also printed on the demo boards for both the LVCMOS input and
LVDS outputs.
62
64
66
46
48
50
52
54
56
58
60
26
28
30
32
34
36
38
40
42
44
TTL INPUT
J1 Pin No. Symbol
12
14
16
18
20
2
4
6
8
10
22
24
TxIN10
TxIN11
TxIN0
TxIN1
TxIN2
TxIN3
TxIN4
TxIN5
TxIN6
TxIN7
TxIN8
TxIN9
TxIN12
TxIN13
TxIN14
TxIN15
TxIN16
TxIN17
TxIN18
TxIN19
TxIN20
TxIN21
TxIN22
TxIN23
TxIN24
TxIN25
TxIN26
TxIN27
TxIN28
TxIN29
TxIN30
TxIN31
TxCLKIN
LVDS OUTPUT
P1 Pin No. Symbol
4
5
6
7
8
1
2
3
OUT 0 +
OUT 0 -
OUT 1 +
OUT 2 +
OUT 2 -
OUT 1 -
OUT 3 +
OUT 3 -
All Odd Pins GND
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Deserializer (Rx) Board:
The RJ-45 connector P1 provides the interface connection for LVDS signals to the deserializer board.
The deserializer board is powered externally from the J6 (VDD) and J7 (VSS) connectors shown below. For the deserializer to be operational, the Power Down
(PWDNB) and Receiver Enable (REN) switches on S1 must be set HIGH. Rising or falling edge output clock is also selected by S1(R FB): HIGH (rising) or LOW (falling).
The 50 pin IDC Connector J1 provides access to the 32 LVCMOS data and clock outputs. f
J6, J7
Note:
V
DD
and Gnd MUST be applied externally here e
S1 c
P1 (TOP SIDE) g g g d
JP3 d
J1 c LVDS INPUTS d LVCMOS OUTPUTS e FUNCTION CONTROLS f POWER SUPPLY g OPTIONAL PARALLEL
LVCMOS LOADING PADS
ASSY DS92LV3242 RX DEMO REV
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Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Configuration Settings for the Deserializer Board
S1: Deserializer Input Features Selection
Reference
RSVD
Description
ReSerVeD
Input = L
MUST be tied low for normal operation
(Default)
Input = H
Not allowed
RRFB Rising Edge
RxCLKOUT
PWDNB Normal
(Disabled) Operational
(Default)
REN
Latch input data on Rising or Falling edge of
Receiver Output Data
ENabled
Falling Edge
(Default)
Disabled Enabled
(Default)
Output Monitor Pins for the Deserializer Board
JP3: Output Lock Monitor
Reference Description Output = L Output = H
Note:
DO NOT PUT A SHORTING
JUMPER IN JP3.
(LED1 will illuminate)
S1
JP3
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Deserializer LVDS and LVCMOS Pinout by Connector
The following two tables illustrate how the LVDS inputs are mapped to the RJ-45 connector J1 and the Rx outputs are mapped to the IDC connector J1.
Note: Labels are also printed on the demo boards for both the LVDS inputs and
LVCMOS outputs.
LVDS INPUT
P1 Pin No. Symbol
4
5
6
7
8
1
2
3
IN 0 +
IN 0 -
IN 1 +
IN 2 +
IN 2 -
IN 1 -
IN 3 +
IN 3 -
39
41
43
45
47
49
51
23
25
27
29
31
33
35
37
LVCMOS OUTPUT
J1 Pin No.
Symbol
9
11
13
15
17
5
7
1
3
19
21
RxOUT0
RxOUT1
RxOUT2
RxOUT3
RxOUT4
RxOUT5
RxOUT6
RxOUT7
RxOUT8
RxOUT9
RxOUT10
RxOUT11
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT16
RxOUT17
RxOUT18
RxOUT19
RxOUT20
RxOUT21
RxOUT22
RxOUT23
RxOUT24
RxOUT25
61
63
65
53
55
57
59
RxOUT26
RxOUT27
RxOUT28
RxOUT29
RxOUT30
RxOUT31
RxCLKOUT
All Even Pins GND
LVCMOS OUTPUT
JP3 pin no. Symbol
1
2
LOCK (PLL)
GND
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Typical Connection and Test Equipment
The following is a list of typical test equipment that may be used to generate signals for the TX inputs:
1) Digital Video Source – for generation of specific display timing such as Digital Video
Processor or Graphics Controller with digital RGB (LVCMOS) output.
2) Astro Systems VG-835 - This video generator may be used for video signal sources for 6-bit Digital TTL/RGB.
3) Any other signal / video generator that generates the correct input levels as specified in the datasheet.
4) Logic Analyzer or Oscilloscope
The following is a list of typically test equipment that may be used to monitor the output signals from the RX:
1) LCD Display Panel which supports digital RGB (LVCMOS) inputs.
2) National Semiconductor DS92LV3241 Serializer (Tx)
3) Optional – Logic Analyzer or Oscilloscope
4) Any SCOPE with a bandwidth of at least 170 MHz for TTL and/or 1 GHz for looking at the LVDS signals.
LVDS signals may be easily measured with high impedance, low capacitance, high bandwidth differential probes such as the TEK P6330 differential probes.
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Typical Applications:
Figure 1. Typical SERDES Application
The chipset supports up to 30-bit color depth TFT LCD Panels. The picture below shows a typical test set up using a Graphics Controller and LCD Panel.
Transmitter
Board
Receiver
Board
LCD Panel
Digital RGB (TTL) from Graphic
Contoller
LVDS Interface
Cable
Digital RGB
(TTL) to Panel
Contents of Demo Kit
Graphics Controller /
Video Processor Board
Figure 2. Typical SERDES Setup of LCD Panel Application
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Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
The picture below shows a typical test set up using a generator and scope.
Figure 3. Typical SERDES Test Setup for Evaluation
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Troubleshooting
If the demo boards are not performing properly, use the following as a guide for quick solutions to potential problems. If the problem persists, please contact the local Sales
Representative for assistance.
QUICK CHECKS:
1. Check that Power and Ground are connected to both Tx AND Rx boards.
2. Check the supply voltage (typical 3.3V) and also current draw with both Tx and Rx boards. The Serializer board should draw about 150-200 mA with clock and all data bits switching at 85 MHz in Quad Mode, (R
PRE
=12 k
Ω). The Deserializer board should draw about 240-265mA with clock and all data bits switching at 85 MHz in
Quad Mode (8pF RxOUT loading).
3. Verify input clock and input data signals meet requirements for V
IL min, V
IL max,
V
IH min, V
IH max, t
STC
, t
HTC
), also verify that data is strobed on the selected rising/falling (RFB pin) edge of the clock.
4. Check that the Jumpers and Switches are set correctly.
5. Check that the cable is properly connected.
TROUBLESHOOTING CHART
Problem…
There is only the output clock.
There is no output data.
Solution…
Make sure the data is applied to the correct input pin.
Make sure data is valid at the input.
No output data and clock.
Power, ground, input data and input clock are connected correctly, but no outputs.
The devices are pulling more than 1A of current.
Make sure Power is on. Input data and clock are active and connected correctly.
Make sure that the cable is secured to both demo boards.
Check the Power Down pins of both Serializer and
Deserializer boards to make sure that the devices are enabled (/PWDB=V
DD
) for operation. Also check
DEN on the Serializer board and REN on the
Deserializer board is set HIGH.
Check for shorts in the cables connecting the TX and
RX boards.
After powering up the demo boards, the power supply reads less than 3V when it is set to 3.3V.
Use a larger power supply that will provide enough current for the demo boards, a 500mA minimum power supply is recommended.
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Appendix
BOM (Bill of Materials) Serializer PCB:
DS92LV3241 Tx Demo Board - Board Stackup Revised: Monday, September 21, 2009
DS92LV3241 Tx Demo Board Revision: 1
Bill Of Materials September 21, 2009
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
BOM (Bill of Materials) Deserializer PCB:
DS92LV3242 Rx Demo Board - Board Stackup Revised: Monday, September 21, 2009
DS92LV3242 Rx Demo Board Revision: 1
Bill Of Materials September 21, 2009
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Serializer (Tx) PCB Schematic:
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Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
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Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Deserializer (Rx) PCB Schematic:
National Semiconductor Corporation
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Serializer (Tx) PCB Layout:
ASSY DS92LV3241 TX DEMO REV
TOP VIEW
PWB DS92LV3241 TX DEMO REV 1
BOTTOMSIDE VIEW
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
PRIMARY COMPONENT SIDE – LAYER 1 GROUND PLANE (VSS) – LAYER 2 POWER PLANE (VDD) – LAYER 3
SECONDARY COMP SIDE – LAYER 4 PRIMARY COMP SIDE – SOLDER MASK (LAYER 1) SECONDARY COMP SIDE – SOLDER MASK (LAYER 4)
PRIMARY COMP SIDE – SOLDER PASTE (LAYER 1) SECONDARY COMP SIDE – SOLDER PASTE (LAYER 4)
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
ASSY DS92LV3241 TX DEMO REV
PRIMARY COMP SIDE – SILKSCREEN (LAYER 1) SILKSCREEN COMP SIDE – SILKSCREEN (LAYER 4)
National Semiconductor Corporation
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Serializer (Tx) PCB Stackup:
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Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Deserializer (Rx) PCB Layout:
ASSY DS92LV3242 RX DEMO REV
TOP VIEW
PWB DS92LV3242 RX DEMO REV 1
BOTTOMSIDE VIEW
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
PRIMARY COMPONENT SIDE – LAYER 1 GROUND PLANE (VSS) – LAYER 2 POWER PLANE (VDD) – LAYER 3
SECONDARY COMP SIDE – LAYER 4 PRIMARY COMP SIDE – SOLDER MASK (LAYER 1) SECONDARY COMP SIDE – SOLDER MASK (LAYER 4)
PRIMARY COMP SIDE – SOLDER PASTE (LAYER 1) SECONDARY COMP SIDE – SOLDER PASTE (LAYER 4)
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
ASSY DS92LV3242 RX DEMO REV
PRIMARY COMP SIDE – SILKSCREEN (LAYER 1) SILKSCREEN COMP SIDE – SILKSCREEN (LAYER 4)
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Deserializer (Rx) PCB Stackup:
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Frequently Answers and Questions
What devices are included in the Texas Instruments LV32EVK01 Evaluation Kit?
What is the purpose of the LV32EVK01 Evaluation Kit?
How do I power the serializer and deserializer boards?
How do I connect the serializer and deserializer boards?
What is the default setting for the LVCMOS I/O pins on the serializer board?
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