AN4878, QorIQ LS1021A Design Checklist

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AN4878, QorIQ LS1021A Design Checklist | Manualzz

Freescale Semiconductor

Application Note

Document Number: AN4878

Rev. 1, 11/2015

QorIQ LS1021A Design Checklist

Also supports the LS1020A and LS1022A

1 About this document

This document provides recommendations for new designs based on the LS102xA family, which is a cost-effective, power-efficient, and highly integrated system-on-chip (SoC) design that extends the reach of the Freescale Value

Performance line, the Layerscape LS1 series, of QorIQ communications processors.

This document can also be used to debug newly-designed systems by highlighting those aspects of a design that merit special attention during initial system start-up.

NOTE

This document applies to the LS1020A,

LS1021A, and LS1022A. For a list of functionality differences, see the appendices in LS1021A QorIQ Integrated Multicore

Communications Processor Reference

Manual

.

Contents

1 About this document........................... ...................... 1

2 Before you begin............................... ........................1

3 Simplifying the first phase of design.........................2

4 Power design recommendations.......... ..................... 6

5 Interface recommendations......................................21

6 Thermal recommendations............... .......................75

7 Revision history.......................... ............................ 78

2 Before you begin

Ensure you are familiar with the following Freescale collateral before proceeding:

LS1020A QorIQ Advanced Multicore Processor

(LS1020A)

© 2014-2015 Freescale Semiconductor, Inc.

Simplifying the first phase of design

LS1021A QorIQ Advanced Multicore Processor (LS1021A)

LS1022A QorIQ Advanced Multicore Processor (LS1022A)

LS1021A QorIQ Advanced Multicore Processor Reference Manual (LS1021ARM)

2

3 Simplifying the first phase of design

Before designing a system with the chip, it is recommended that the designer be familiar with the available documentation, software, models, and tools.

This figure shows the major functional units within the LS1021A chip.

QorIQ LS1021A Processor Block Diagram

System Control

2x WDOG

Internal Boot ROM

Security Fuses

Security Monitor

Power Management eDMA qDMA

FPU

ARM

®

Cortex

®

-A7

Core

NEON

32 KB

D Cache

32 KB

I Cache

FPU

ARM

®

Cortex

®

-A7

Core

NEON

32 KB

D Cache

512 KB Coherent L2 Cache

32 KB

I Cache

Cache Coherent Interconnect (CCI-400)

System Interfaces

GIC-400

IFC Flash

QuadSPI Flash

1x SD/MMC

2x DUART, 6x LPUART

3x I

2

C, 2x SPI, 4x GPIO

Audio Subsystem:

4x SAI, ASRC, SPDIF

4x CAN, 8x FlexTimer/PWM

USB 3.0 w/ PHY

USB 2.0

2D-ACE LCD Controller

TMU

μQE

(HDLC,

TDM,

PB)

SMMU

Security

(XoR,

CRC)

SMMU SMMU

DDR3L/4

Memory

Controller

SMMU

4-Lane 6 GHz SerDes

128 KB

SRAM

Core Complex Basic Peripherals and Interconnect

Accelerators and Memory Control

Networking Elements

Figure 1. LS1021A block diagram

This figure shows the major functional units within the LS1020A chip.

QorIQ LS1021A Design Checklist, Rev. 1, 11/2015

Freescale Semiconductor, Inc.

Simplifying the first phase of design

QorIQ LS1020A Processor Block Diagram

System Control

2x WDOG

Internal Boot ROM

Security Fuses

Security Monitor

Power Management eDMA qDMA

System Interfaces

GIC-400

IFC Flash

QuadSPI Flash

1x SD/MMC

2x DUART, 6x LPUART

3x I

2

C, 2x SPI, 4x GPIO

Audio Subsystem:

4x SAI, ASRC, SPDIF

8x FlexTimer/PWM

USB 2.0

USB 3.0 w/ PHY

TMU

FPU

ARM

Cortex ®

®

Core

-A7

NEON FPU

ARM ®

Cortex ®

Core

-A7

NEON

32 KB

D Cache

32 KB

I Cache

32 KB

D Cache

32 KB

I Cache

512 KB Coherent L2 Cache

SMMU

μQE

(HDLC,

TDM,

PB)

Security

(XoR,

CRC)

Cache Coherent Interconnect (CCI-400)

SMMU

SMMU

DDR3L/4

Memory

Controller

SMMU

4-Lane 6 GHz SerDes

128 KB

SRAM

Core Complex Basic Peripherals and Interconnect

Accelerators and Memory Control Networking Elements

Figure 2. LS1020A block diagram

This figure shows the major functional units within the LS1022A chip.

Freescale Semiconductor, Inc.

QorIQ LS1021A Design Checklist, Rev. 1, 11/2015

3

Simplifying the first phase of design

QorIQ LS1022A Processor Block Diagram

System Control

2x WDOG

Internal Boot ROM

Security Fuses

Security Monitor

Power Management eDMA qDMA

System Interfaces

GIC-400

IFC Flash

QuadSPI Flash

1x SD/MMC

2x DUART, 6x LPUART

3x I

2

C, 2x SPI, 4x GPIO

Audio Subsystem:

4x SAI, ASRC, SPDIF

USB 2.0

4x CAN, 8x FlexTimer/PWM

TMU

FPU

ARM

®

Cortex

®

-A7

Core

NEON

32 KB

D Cache

32 KB

I Cache

FPU

ARM

®

Cortex

®

-A7

Core

NEON

32 KB

D Cache

32 KB

I Cache

512 KB Coherent L2 Cache

SMMU

Security

(XoR,

CRC)

Cache Coherent Interconnect (CCI-400)

SMMU SMMU

Core Complex Basic Peripherals and Interconnect

Accelerators and Memory Control Networking Elements

DDR3L

Memory

Controller

SMMU

128 KB

SRAM

PCIe 2.0

1-Lane 5 GHz

SerDes

Figure 3. LS1022A block diagram

4

3.1 Recommended resources

This table lists helpful tools, training resources, and documentation, some of which may be available only under a nondisclosure agreement (NDA). Contact your local field applications engineer or sales representative to obtain a copy.

Table 1. Helpful tools and references

ID Location

LS1021ACE

Name

Related collateral

QorIQ LS1021A Chip Errata

NOTE: This document describes the latest fixes and workarounds for the chip. It is strongly recommended that this document be thoroughly researched prior to starting a design with the chip.

Table continues on the next page...

Contact your Freescale representative

QorIQ LS1021A Design Checklist, Rev. 1, 11/2015

Freescale Semiconductor, Inc.

Simplifying the first phase of design

Table 1. Helpful tools and references (continued)

LS1020A

LS1021A

LS1022A

LS1020A

LS1022AFS

LS1021AFS

LS1021ARM

QEIWRM

AN3940

AN4311

AN4871

TWR

IBIS

BSDL

1

Flotherm

ID

LS1021A-IOT

QorIQ LS1020A Data Sheet

Name Location

Contact your Freescale representative

QorIQ LS1021A Data Sheet

QorIQ LS1022A Data Sheet

QorIQ LS1020A Data Sheet

QorIQ LS1022A Fact Sheet

QorIQ LS1021A Fact Sheet

QorIQ LS1021A Reference Manual

Contact your Freescale representative

Contact your Freescale representative

Contact your Freescale representative

Contact your Freescale representative

Contact your Freescale representative

Contact your Freescale representative

Contact your Freescale representative freescale.com

QUICC Engine Block Reference Manual with Protocol

Interworking

Hardware and Layout Design Considerations for DDR3 SDRAM

Memory Interfaces

SerDes Reference Clock Interfacing and HSSI Measurements

Recommendations

Assembly Handling and Thermal Solutions for Lidless Flip Chip

Ball Grid Array Packages

Hardware tools

QorIQ LS1021A-IOT Gateway reference design freescale.com

freescale.com

Tower-based, low-cost evaluation platform, including schematics, and bill of materials

Models

Contact your Freescale representative

Contact your Freescale representative

To ensure first path success, Freescale strongly recommends using the IBIS models for board-level simulations, especially for

SerDes and DDR characteristics.

Use the BSDL files in board verification.

Contact your Freescale representative

Use the Flotherm model for thermal simulation. Especially without forced cooling or constant airflow, a thermal simulation should not be skipped.

Available training

Contact your Freescale representative

Contact your Freescale representative

Our third-party partners are part of an extensive alliance network.

More information can be found at freescale.com/alliances.

Training materials from past Smart Network Developer's Forums and Freescale Technology Forums (FTF) are also available at our website. These training modules are a valuable resource for understanding the chip.

freescale.com/alliances freescale.com/alliances

1. Design requirements in the device data sheet supersede requirements mentioned in the design checklist, and design requirements mentioned in the design checklist supersede the design/implementation of the Freescale reference design

(RDB) system.

Freescale Semiconductor, Inc.

QorIQ LS1021A Design Checklist, Rev. 1, 11/2015

5

Power design recommendations

3.2 Product revisions

This table lists the ARM core main ID register and system version register (SVR) values for the various chip silicon derivatives.

Table 2. Chip product revisions

Part

LS1020AE

LS1020A

LS1021AE

LS1021A

LS1022AE

LS1022A

ARM® Cortex®-A7

MPCore processor revision

r0p5 r0p5 r0p5 r0p5 r0p5 r0p5

ARM core main

ID register

410FC075h

410FC075h

410FC075h

410FC075h

410FC075h

410FC075h

System version register value

(Rev 2.0 silicon)

8708_1020h

8700_1020h

8708_1120h

8700_1120h

8708_1220h

8700_1220h

Note

With security

Without security

With security

Without security

With security

Without security

4 Power design recommendations

6

4.1 Power pin recommendations

NOTE

LS102xA has several power supplies and ground signals. When implementing deep sleep mode, separate the switchable supplies and the Always ON supplies. For deep sleep, the power rail must be turned off and disconnected from the pins.

Table 3. Power and ground pin termination checklist

Signal Name

AV

DD

_CGA1

AV

DD

_D1

AV

DD

_PLAT

AVDD_SD1_PLL1

AV

DD

_SD1_PLL2

Power domain in deep sleep

Used

Switchable Power supply for cluster group A

PLL 1 supply (1.8 V through a filter)

Switchable Power supply for DDR PLL (1.8 V through a filter)

Always

ON

Power supply for Platform PLL

(1.8 V through a filter)

Switchable Power supply for SerDes1 PLL 1

(SerDes, filtered from X1V

DD

(SerDes, filtered from X1V

DD

)

Switchable Power supply for SerDes1 PLL 2

)

Not Used

Must remain powered.

Must remain powered.

Must remain powered.

Must remain powered (no need to filter from X1V

DD

).

Must remain powered (no need to filter from X1V

DD

).

Table continues on the next page...

QorIQ LS1021A Design Checklist, Rev. 1, 11/2015

Completed

Freescale Semiconductor, Inc.

BV

DD

D1V

DD

1

DV

DD

1

EV

DD

FA_VL

G1V

DD

L1V

DD

2

LV

DD

2

O1V

DD

OV

DD

PROG_MTR

S1V

DD

Power design recommendations

Table 3. Power and ground pin termination checklist (continued)

Signal Name Completed

SENSEV

DD

SENSEV

DDC

TA_BB_V

DD

TA_PROG_SFP

TH_V

DD

Power domain in deep sleep

Used

Switchable Power supply for the QSPI, SPI1,

IFC, FTM5, FTM6, FTM7, I

2

C,

GPIO3, and DIU (3.3 V/1.8 V)

Always

ON

Power supply for the DUART, I

2

C, and GPIO (3.3 V/1.8 V)

Switchable Power supply for the DUART, I

2

C,

DMA, QE, TDM, 2D-ACE,

LPUART, GPIO, eSDHC, SAI

(I

2

S), SPDIF, FTM, SPI, and IRQ

(3.3 V/1.8 V)

Switchable Power supply for eSDHC(3.3 V/1.8

V)

— This pin must be pulled to ground

(GND).

Switchable Power supply for the DDR3L/4

(1.35 V/1.2 V)

Always

ON

Power supply for the Ethernet 1

I/O, Ethernet management interface 1 (EMI1), and GPIO (3.3

V/2.5 V/1.8 V)

Switchable Power supply for the Ethernet 2

I/O, 1588, GPIO (3.3 V/ 2.5 V/1.8

V) GPIO only support at 3.3 V

Must remain powered.

Must remain powered.

Must remain powered.

Must remain powered.

Not Used

Must remain powered.

Must remain powered.

Must remain powered.

Always

ON

Power supply for system control and power management, GPIO1,

GPIO2, debug, and IRQ (1.8 V)

Switchable Power supply for clocking, debug,

DDRCLK supply, JTAG, RTC, and

IRQ (1.8 V)

Must remain powered.

Must remain powered.

— Only supply 1.8 V during secure boot programming. For normal operation, this pin must be tied to GND.

Switchable Core power supply for the SerDes logic and receivers (1.0 V)

Must remain powered.

Switchable V

Always

ON

V

DD

sense pin

DDC

sense pin

Do not connect. These pins should be left floating.

Do not connect. These pins should be left floating.

Low power security monitor supply. This signal should be connected to 1.0 V always on supply.

This signal should be connected to

1.0 V switchable supply.

Should only be supplied 1.8 V during secure boot programming. For normal operation, this pin needs to be tied to GND.

Switchable Must remain powered (1.8 V).

Table continues on the next page...

Freescale Semiconductor, Inc.

QorIQ LS1021A Design Checklist, Rev. 1, 11/2015

7

Power design recommendations

Table 3. Power and ground pin termination checklist (continued)

Signal Name Power domain in deep sleep

Used Not Used

USB1_SDV

USB1_SPV

USB1_SXV

USB_HV

V

V

DD

DDC

X1V

DD

S1GND

X1GND

GND

DD

DD

DD

DD

AGND_SD1_PLL1

AGND_SD1_PLL2

SENSEGND

SENSEGNDC

Optionally switchable or always

ON

USB PHY transceiver supply voltage (1.0 V)

Optionally switchable or always

ON

Optionally switchable or always

ON

USB PHY analog supply voltage

(1.0 V)

USB PHY transceiver supply voltage (1.0 V)

Optionally switchable or always

ON

USB PHY transceiver supply voltage (3.3 V)

Switchable Core and platform supply voltage

Always

ON

Core and platform supply voltage

Switchable Pad power supply for SerDes transmitters (1.35 V)

SerDes core logic GND

SerDes transmitter GND

Ground

Serdes1 PLL 1 GND

SerDes 1 PLL 2 GND

GND sense pin

Must remain powered.

Must remain powered.

Must remain powered.

Must remain powered.

Must remain powered.

Tie to GND.

Tie to GND.

Tie to GND.

Tie to GND.

Tie to GND.

Do not connect. These pins should be left floating.

GND sense pin for VDDC domain Do not connect. These pins should be left floating.

Notes:

1. D1V

DD

and DV

DD

must always be the same voltage.

2. L1V

DD

and LV

DD

must always be the same voltage.

Completed

8

4.2 Power system-level recommendations

Table 4. Power design system-level checklist

Item

General

Table continues on the next page...

Completed

QorIQ LS1021A Design Checklist, Rev. 1, 11/2015

Freescale Semiconductor, Inc.

Power design recommendations

Table 4. Power design system-level checklist (continued)

Completed Item

Ensure that the ramp rate for all voltage supplies (including OV

X1V

DD

, LV

DD

, L1V

DD

, EV

DD

, BV

DD

DD

, O1V

DD

, DV

DD

, D1V

DD

, G1V

DD

, S1V

DD

,

, all core and platform VDD supplies, Dn_MVREF, and all AVDD supplies) is less than 25 V/mS. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (for example, exponential), the maximum rate of change from 200 to 500 mV is the most critical, because this range might falsely trigger the ESD circuitry. Required ramp rate for TA_PROG_SFP should be less than 25 V/mS.

Ensure that V

DD

V

DD

value.

nominal voltage supply is set for 1.0 V with voltage tolerance of +/- 30 mV from the nominal

Ensure that all other power supplies have a voltage tolerance no greater than 5% from the nominal value.

1

Ensure the power supply is selected based on MAXIMUM power dissipation.

1

Ensure the thermal design is based on THERMAL power dissipation.

1

Ensure the power-up sequence is within 75 ms.

1

Use large power planes to the extent possible.

Ensure the PLL filter circuit is applied to AV

DD

_PLAT, AV

DD

_CGA1, AV

DD

_D1, and AV

DD

_SD1_PLLn.

If SerDes is enabled, ensure the PLL filter circuit is applied to the respective SDAV

DD

. Otherwise, a filter is not required. Even if an entire SerDes module is not used, the power is still needed to the AV

However, instead of using a filter, it needs to be connected to the XV

DD

DD

pins.

rail through a 0 Ω resistor.

Ensure the PLL filter circuits are placed as close to the respective AV

DD

pin as possible.

Ensure the decoupling capacitors of 0.1 μF are placed at each V

DDC

, V

DD

, and B/G/L/X/S/OV

DD

pin.

Power supply decoupling

Provide sufficiently-sized power planes for the respective power rail. Use separate planes if possible; split

(shared) planes if necessary. If split planes are used, ensure that signals on adjacent layers do not cross splits. Avoid splitting ground planes at all costs.

Place at least one decoupling capacitor at each V

DD

X1V

DD

, LV

DD

, L1V

DD

, EV

DD

, and BV

DD

, V

DDC

, OV

DD

, O1V

DD

, DV

DD

pin of this chip.

, D1V

DD

, G1V

DD

, S1V

DD

,

It is recommended that the decoupling capacitors receive their power from separate V

DD

DV

DD

, D1V

DD

, G1V

DD

, S1V

DD

, X1V

DD

, LV

DD

, L1V

DD short traces to minimize inductance.

, EV

DD

, BV

DD

, OV

DD

, O1V

DD

,

, and GND planes in the PCB, utilizing

Capacitors may be placed directly under the chip using a standard escape pattern, and others may surround the part.

Ensure the board has at least one 0.1 μF (surface-mount technology) SMT ceramic chip capacitor as close as possible to each supply ball of the chip (V

L1V

DD

, EV

DD

, BV

DD

).

DD

, OV

DD

, O1V

DD

, DV

DD

, D1V

DD

, G1V

DD

, S1V

DD

, X1V

DD

, LV

DD

,

Ensure these capacitors have a value of at least 0.1 μF. Recommend 0201.

Only use ceramic SMT capacitors to minimize lead inductance, preferably 0402 or 0603.

Distribute several bulk storage capacitors around the PCB, feeding the V

DD

DV

DD

, EV

DD

, LV

DD

, and G1V

DD

and other planes (for example,

), to enable quick recharging of the smaller chip capacitors.

Ensure the bulk capacitors have a low equivalent series-resistance (ESR) rating to ensure the quick response time necessary.

Ensure the bulk capacitors are connected to the power and ground planes through two vias to minimize inductance.

Ensure you work directly with your power regulator vendor for best values and types of bulk capacitors. The capacitors need to be selected to work well with the power supply to be able to handle the chip's power requirements.

2

Most regulators perform best with a mix of ceramic and very low ESR Tantalum type capacitors.

Table continues on the next page...

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9

Power design recommendations

Table 4. Power design system-level checklist (continued)

Item

As a guideline for customers and their power regulator vendors, Freescale recommends that these bulk capacitors be chosen to maintain the positive transient power surges to less than +50 mV (negative transient undershoot should comply with specification -30 mV) for current steps of up to 2 A with a slew rate of 1.5 A/μs.

Additional power supply decoupling

Use only SMT capacitors to minimize inductance.

Connections from all capacitors to power and ground must be done with multiple vias to further reduce inductance.

Ensure the board has at least one 0.1 μF SMT ceramic chip-capacitor as close as possible to each supply ball of the chip (SnV

DD

and XnV

DD

).

Where the board has blind vias, ensure these capacitors are placed directly below the chip supply and ground connections.

Where the board does not have blind vias, ensure these capacitors are placed in a ring around the chip as close as possible to the supply and ground connections.

For all SerDes supplies: Ensure there is a 1 µF ceramic chip capacitor on each side of the chip.

For all SerDes supplies: Ensure there is a 10 µF, low equivalent series resistance (ESR) SMT Tantalum chip capacitor and a 100 µF, low ESR SMT Tantalum chip capacitor between the device and any SerDes voltage regulator.

PLL power supply filtering

3

Provide independent filter circuits per PLL power supply, as illustrated in this figure.

R

1.8 V source AV

DD

_PLAT, AV

DD

_CGA1, AV

DD

_D1

C1 C2

Completed

Low-ESL surface-mount capacitors

GND

Figure 4. PLL power supply filter circuit

• R = 5 Ω ± 5%

• C1 = 10 μF ± 10%, 0603, X5R, with ESL ≤ 0.5 nH

• C2 = 1.0 μF ± 10%, 0402, X5R, with ESL ≤ 0.5 nH

• Low-ESL surface-mount capacitors

NOTE: A higher capacitance value for C2 may be used to improve the filter as long as the other C2 parameters do not change (0402 body, X5R, ESL ≤ 0.5 nH).

NOTE: Voltage for AV

DD

is defined at the input of the PLL supply filter and not the pin of AV

DD

.

Ensure filter circuits use surface mount capacitors with minimum effective series inductance (ESL).

Place each circuit as close as possible to the specific AV from nearby circuits.

DD

pin being supplied to minimize noise coupled

NOTE: If done properly, it is possible to route directly from the capacitors to the AV

DD

pin, which is on the periphery of the 525 FC-PBGA footprint, without the added inductance of vias.

NOTE: It is recommended that an area fill or power plane split be provided to provide a low-impedance profile, which helps keep nearby crosstalk noise from inducing unwanted noise.

Ensure each of the PLLs is provided with power through independent power supply pins (AVDD_CGA1,

AV

DD

_PLAT, AV

DD

_D1, AV

DD

_SD1_PLL1, and AV

DD

_SD1_PLL2, respectively).

Table continues on the next page...

10

QorIQ LS1021A Design Checklist, Rev. 1, 11/2015

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Power design recommendations

Table 4. Power design system-level checklist (continued)

Item

For maximum effectiveness, ensure the filter circuit is placed as close as possible to the AV ball to ensure it filters out as much noise as possible.

DD

_SDn_PLLn

Ensure the ground connection is near the AV

DD

_SDn_PLLn ball. The 0.003 μF capacitor is closest to the ball, followed by a 4.7 μF capacitor and 47 μF capacitor, and finally the 0.33 Ω resistor to the board supply plane.

To ensure stability of the internal clock, ensure the power supplied to the PLL is filtered using a circuit similar to the one shown in this figure.

• AV

DD

_SDn_PLLn should be a filtered version of XnV

DD

• Signals on the SerDes interface are fed from the XnV

DD

.

power plane.

• It is recommended that an area fill or power plane split be provided for both AV

DD

and AGND to provide a low-impedance profile, which helps keep nearby crosstalk noise from inducing unwanted noise.

• Voltage for AV

DD

_SDn_PLLn is defined at the PLL supply filter and not the pin of AV

DD

_SDn_PLLn.

• A 47 μF 0805 XR5 or XR7, 4.7 μF 0603, and 0.003 μF 0402 capacitor are recommended. The size and material type are important. A 0.33 Ω ± 1% resistor is recommended.

Caution: These filters are a necessary extension of the PLL circuitry and are compliant with the device specifications. Any deviation from the recommended filters is done at the user's risk.

Completed

0.33 Ω

X1V

DD

AV

DD

_SD1_PLLn

47 µF 4.7 µF 0.003 µF

AGND_SD1_PLLn

Figure 5. SerDes PLL power supply filter circuit

Ensure the capacitors are connected from AV

DD

_SDn_PLLn to the ground plane.

Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide, and direct.

Ensure AV

DD

_SDn_PLLn is a filtered version of X1V

DD

.

Ensure that signals on the SerDes interface are fed from the XV

DD

power plane.

S1V

DD

may be supplied by a linear regulator or sourced by a filtered V

DD

. Systems may design-in both options to allow flexibility to address system noise dependencies. However, for initial system bring-up, the linear regulator option is highly recommended. An example solution for SnV

DD

filtering, where SnV

DD

is sourced from a linear regulator, is shown in the following figure. The component values in this example filter are system dependent and are still under characterization, so component values may need adjustment based on the system or environment noise.

Where:

• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH

• C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH

• F1 and F2 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata BLM18PG121SH1)

• Bulk and decoupling capacitors are added, as needed, per power supply design.

Table continues on the next page...

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11

Power design recommendations

Table 4. Power design system-level checklist (continued)

Item

F1

S1V

DD

Bulk and decoupling capacitors

C1 C2 C3

Linear regulator output

F2

GND

Figure 6. SV

DD

power supply filter circuit

NOTE: See section "Power-on ramp rate" in the applicable chip data sheet for maximum S1V

DD

power-up ramp rate.

NOTE: There must be enough output capacitance or a soft-start feature to ensure the ramp-rate requirement is met.

NOTE: The Ferrite beads should be placed in parallel to reduce voltage droop.

NOTE: Besides a linear regulator, a low-noise, dedicated switching regulator can also be used. The goal is

10 mVp-p, 50 kHz to 500 MHz.

XnV

DD

may be supplied by a linear regulator or sourced by a filtered GnV

DD

. Systems may design-in both options to allow flexibility to address system noise dependencies. However, for initial system bring-up, the linear regulator option is highly recommended. An example solution for XnV

DD

filtering, where XnV

DD

is sourced from a linear regulator, is shown in the following figure. The component values in this example filter are system dependent and are still under characterization, so component values may need adjustment based on the system or environment noise.

Where:

• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH

• C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH

• F1 and F2 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata BLM18PG121SH1)

• Bulk and decoupling capacitors are added, as needed, per power supply design.

Completed

X1V

DD

Bulk and decoupling capacitors

F1

Linear regulator output

C1 C2 C3

F2

GND

Figure 7. XnV

DD

power supply filter circuit

NOTE: See section "Power-on ramp rate" in the applicable chip data sheet for maximum XnV

DD

power-up ramp rate.

NOTE: There must be enough output capacitance or a soft-start feature to assure the ramp-rate requirement is met.

NOTE: The Ferrite beads should be placed in parallel to reduce voltage droop.

NOTE: Besides a linear regulator, a low-noise-dedicated switching regulator can be used. 10 mVp-p, 50 kHz to 500 MHz is the noise goal.

USB_HV

DD

must be sourced by a filtered 3.3 V voltage source using a star connection. An example solution for USB_HV

DD

filtering, where USB_HV

DD

is sourced from a 3.3 V voltage source, is illustrated in the following figure. The component values in this example filter are system dependent and are still under characterization, so component values may need adjustment based on the system or environment noise.

Where:

• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH

• C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH

Table continues on the next page...

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Power design recommendations

Table 4. Power design system-level checklist (continued)

Item

• F1 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata BLM18PG121SH1)

• Bulk and decoupling capacitors are added, as needed, per power supply design.

Completed

F1

USB_HV

DD

Bulk and decoupling capacitors

C1 C2 C3

3.3-V source

GND

Figure 8. USB_HV

DD power supply filter circuit

USB1_SDV

DD

must be sourced by a filtered V

DD

USB1_SDV

DD

filtering, where USB1_SDV

DD

using a star connection. An example solution for

is sourced from V

DD

, is illustrated in the following figure. The component values in this example filter are system dependent and are still under characterization, so component values may need adjustment based on the system or environment noise.

Where:

• C1 = 2.2 μF ± 20%, X5R, with low ESL (for example, Panasonic ECJ0EB0J225M)

• F1 = 120 Ω at 100 MHz 2A 25% Ferrite (for example, Murata BLM18PG121SH1)

• Bulk and decoupling capacitors are added, as needed, per power supply design

USB_SnV

DD

Figure 9. USB_SnV

DD

power supply filter circuit

Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide, and direct.

Notes:

1. See the applicable chip data sheet for more details.

2. Suggested bulk capacitors are 100-300 μF (AVX TPS Tantalum or Sanyo OSCON).

3. The PLL power supply filter circuit filters noise in the PLLs' resonant frequency range from 500 kHz to 10 MHz.

4.3 Power-on reset recommendations

Various chip functions are initialized by sampling certain signals during the assertion of PORESET_B. These power-on reset

(POR) inputs are pulled either high or low during this period. While these pins are generally output pins during normal operation, they are treated as inputs while PORESET_B is asserted. When PORESET_B de-asserts, the configuration pins are sampled and latched into registers, and the pins then take on their normal output circuit characteristics.

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Power design recommendations

Table 5. Power-on reset system-level checklist

Item

Ensure PORESET_B is asserted for a minimum of 1 ms.

Ensure HRESET_B is asserted for a minimum of 32 SYSCLK cycles.

In cases where a configuration pin has no default, use a 4.7 kΩ pull-up or pull-down resistor for appropriate configuration of the pin.

Optional: An alternative to using pull-up and pull-down resistors to configure the POR pins is to use a PLD or similar device that drives the configuration signals to the chip when HRESET_B is asserted. The PLD must begin to drive these signals at least four SYSCLK cycles prior to the de-assertion of PORESET_B (PLL configuration inputs must meet a 100 µs set-up time to HRESET_B), hold their values for at least two

SYSCLK cycles after the de-assertion of PORESET_B, and then release the pins to high impedance afterward for normal device operation.

NOTE: See the applicable chip data sheet for details about reset initialization timing specifications.

Configuration settings

Ensure the settings in the applicable configuration section are selected properly.

NOTE: See the applicable chip reference manual for a more detailed description of each configuration option.

Power sequencing

Apply the power rails in a specific sequence to ensure proper device operation. The required power-up sequence is as follows:

Table 6. Power-up sequence

1.

Step

2.

3.

Notes:

BV

DD

, AV

DD

EV

DD

, TH_V

_CGA1, AV

DD

DD

, USB_HV

_PLAT, AV

DD

DD

_D1, O1V

DD

, OV

DD

, D1V

DD

, DV

DD

, L1V

. Drive PROG_SFP = GND.

DD

, LV

DD

,

V

DDC

, V

DD

, S1V

DD

, TA_BB_V

DD

G1V

DD

, AV

DD

Procedure

, USB1_SPV

DD

, USB1_SDV

DD

, USB1_SXV

_SD1_PLL1, AV

DD

_SD1_PLL2, X1V

DD

DD

1

Notes

2, 3

4, 5

1. PORESET_B should be driven, asserted, and held during this step.

2. When deep sleep mode is used, V

DDC

should ramp up before V

DD together with V

DDC

provided that the relative timing between V

DDC

. Alternatively, V

DD

and V

DD

may ramp up

ramp up conforms to Figure 10 .

3. When deep sleep is not used, it is recommended to source V

DD

and V

DDC

from the same power supply.

4. When using DDR4: AV

DD

_SD1_PLL1, AV

DD

_SD1_PLL2, and X1V

DD

may ramp up with step 1 supplies.

5. When using DDR3L: All supplies in step 3 above may be sourced from the same supply.

Completed

The required sequence for exiting deep sleep mode is as follows:

Table 7. Sequence for exiting deep sleep mode

Step

1.

2.

3.

Notes:

Procedure

USB_HV

DD

, BV

DD

, AV

DD

_CGA1, AV

DD

_D1, DV

DD

, LV

DD

, EV

DD

V

DD

, S1V

DD

, TA_BB_V

DD

, USB1_SPV

DD

, USB1_SDV

DD

, USB1_SXV

DD

G1V

DD

, AV

DD

_SD1_PLL1, AV

DD

_SD1_PLL2, X1V

DD

1. PORESET_B should be driven, asserted, and held during this step.

Table continues on the next page...

14

Notes

1

2, 3

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Power design recommendations

Table 5. Power-on reset system-level checklist (continued)

Item

Table 7. Sequence for exiting deep sleep mode

Completed

Step Procedure Notes

2. When using DDR4: AV

DD

_SD1_PLL1, AV

DD

_SD1_PLL2, and X1V

DD

may ramp up with step 1 supplies.

3. When using DDR3L: All supplies in step 3 above may be sourced from the same supply.

Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of their value.

All supplies must be at their stable values within 75 ms.

Negate PORESET_B input when the required assertion/hold time has been met per Table 3

.

The supplies mentioned as OFF in the "Power Domain in Deep Sleep" column of the "Recommended operating conditions" table of the chip data sheet are switched ON during exit from deep sleep power management mode. These supplies should also follow the same power up sequence as mentioned above.

NOTE:

• While V

DD

is ramping, current may be supplied from V

DD

through the LS1021A to G1V

DD

.

• EVT2_B may be unstable when PORESET_B is asserted. The signal should not be used to enable switchable power supplies during this period.

• Ramp rate requirements should be met per the "Power-on ramp rate" section of the chip data sheet.

NOTE: Only 300,000 POR cycles are permitted per lifetime of a device. Note that this value is based on design estimates and is preliminary.

This figure shows the V

DDC

and V

DD

ramp-up diagram.

Table continues on the next page...

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Power design recommendations

Table 5. Power-on reset system-level checklist (continued)

Item

90%

Completed

VDD

10%

90%

10%

VDDC

T1 <= 1 us T2 <= 1 us

Figure 10. V

DDC

and V

DD

ramp-up diagram

Elaborating V

DDC

should ramp up along with or before V

DD

1. Use Case 1: V

DDC

and V

DD

power supply:

are generated using a single power regulator with FET control.

VDDC

VDD

Regulator

DC/DC Converter

EVT_B2 (Power-en)

Figure 11. Single power regulator with FET control

FET is controlled by EVT2_B, that is, POWER_EN.

Table continues on the next page...

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Power design recommendations

Table 5. Power-on reset system-level checklist (continued)

Item

Because of the different impedance between the two power distribution networks, it is possible that

V

DD

V

DD

ramps up before V

DDC

. Care should be taken to ensure that relative timing between V

DDC

conforms as per the "V

DDC

and V

DD

ramp-up diagram" in the chip data sheet. This can be

and achieved using additional delay elements in the V

DD

PDN.

2. Use Case 2: V

DDC

and V

DD

are generated using separate power regulators.

Completed

VIN

EVT2_B (Power-en)

SHUT DN

VIN

Regulator 2

Regulator 1

VDDC

VDD

Figure 12. Dual regulator

V

DDC

should ramp before V

DD

. One way to achieve this is to tie PGOOD of regulator 1 to regulator 2.

NOTE: See the chip's data sheet for power sequencing requirements.

For secure boot fuse programming, use the following steps:

1. After negation of PORESET_B, drive TA_PROG_SFP = 1.8 V after a required minimum delay per

Table 5.

2. After fuse programming is complete, it is required to return TA_PROG_SFP = GND before the system is power cycled (PORESET_B assertion) or powered down (V

DD

ramp down) per the required timing specified in Table 5. See Security fuse processor for additional details.

Warning: No activity other than that required for secure boot fuse programming is permitted while

TA_PROG_SFP is driven to any voltage above GND, including the reading of the fuse block.

The reading of the fuse block may only occur while TA_PROG_SFP = GND.

This figure shows the TA_PROG_SFP timing diagram.

Fuse programming

TA_PROG_SFP

10% TA_PROG_SFP

10% TA_PROG_SFP

90% V

DD t

TA_PROG_SFP_VDD V

DD

PORESET_B

90% OV

DD t

TA

_

PROG_SFP_PROG

90% OV

DD t

TA_PROG_SFP_RST t

TA

_

PROG_SFP_DELAY

NOTE: TA_PROG_SFP must be stable at 1.8 V prior to initiating fuse programming.

Figure 13. TA_PROG_SFP timing diagram

NOTE: See the applicable chip data sheet for power sequencing requirements.

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Power design recommendations

4.3.1 Configuration signals sampled at reset

The signals that serve alternate functions as configuration input signals during system reset are summarized in this table.

Reset configuration signals are sampled at the negation of PORESET_B. However, there is a setup and hold time for these signals relative to the rising edge of PORESET_B, as described in the chip's data sheet.

The reset configuration signals are multiplexed with other functional signals. The values on these signals during reset are interpreted to be logic one or zero, regardless of whether the functional signal name is defined as active-low. The reset configuration signals have internal pull-up resistors so that if the signals are not driven, the default value is high ("1"), as shown in the table. Some signals must be driven high or low during the reset period. For details about all the signals that require external pull-up resistors, see the applicable device data sheet.

Table 8. LS1021A reset configuration signals

Configuration Type

Reset configuration word (RCW) source inputs cfg_rcw_src[0:8]

Functional Pins

IFC_AD[8:15]

IFC_CLE

Comments

They must be set to one of the valid options. The 512-bit RCW word has all the necessary configuration information for the chip. If there is no valid RCW in the external memory, it can be programmed using CodeWarrior or another programmer. JTAG configuration files available with CodeWarrior Installation

(CWInstallDir\PA\PA_Support

\Initialization_Files\jtag_chains) can be used to override the reset configuration word (RCW) for LS1021A. The JTAG configuration files can be used in the following situations:

1, 2

• target boards that do not have RCW already programmed

• new board bring up

• recovering boards with blank or damaged flash

Default is "1" IFC external transceiver enable polarity select (cfg_ifc_te)

DRAM type select (cfg_dram_type)

IFC_TE

"Single Oscillator Source" clock select

(cfg_eng_use0)

IFC_A[21]

General-purpose input (cfg_gpinput[0:7]) IFC_AD[0:7] cfg_eng_use1 cfg_eng_use2

Note:

IFC_WE0_B

IFC_OE_B

IFC_WP0_B

Default is DDR3L. This reset configuration pin selects the proper I/O voltage: DDR3L

= 1.35 V or DDR4 = 1.2 V. Ensure the selection value matches the DDR type used on the board.

Default "1111 1111", values can be application defined.

0 = DIFF_SYSCLK/DIFF_SYSCLK_B

(differential)

1 = SYSCLK (single ended)

Default is "1." Reserved.

Default is "1." Reserved.

1. The hardcoded RCW can be used as an alternative method for initial board bring-up when there is no RCW in the external memory. For more information, see

Table 9 .

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Power design recommendations

This table shows the hardcoded RCW values.

Table 9. Hardcoded RCW values cfg_rcw_src[0:

8]

SYSCLK (MHz) 100

DDRCLK (MHz) 100

64

133

Harcoded RCW

9'b0_1001_1010 9'b0_1001_1011 9'b0_1001_1100 9'b0_1001_1101 9'b0_1001_1110 9'b0_1001_1111

100

100

PLL configuration

64

64

100

100

133

125

SYS_PLL_RAT 3:1

RCW[2:6]

5'd3

MEM_PLL_RAT 10:1

RCW[10:15]

CGA_PLL1_RA

T

RCW[26:31]

6'd10

6:1

6'd6

4:1

5'd4

8:1

6'd8

10:1

6'd10

3:1

5'd3

13:1

6'd13

8:1

6'd8

4:1

5'd4

20:1

6'd20

12:1

6'd12

3:1

5'd3

13:1

6'd13

10:1

6'd10

2:1

5'd2

10:1

6'd10

7:1

6'd7

4.4 Power management recommendations

The LS1021A QorIQ processor implements sophisticated power-saving modes for managing energy consumption in both dynamic and static power modes. These include the traditional nap, doze, sleep, and packet loss-less deep-sleep modes.

Designers may leverage these modes to efficiently match work accomplished with the correct level of energy consumed. See the QorIQ LS1021A Reference Manual for details.

4.4.1 Power management pin termination recommendations

Table 10. Power management pin termination checklist

Signal Name

ASLEEP O

I/O type Used Not Used

Pin must NOT be pulled down during power-on reset. This pin may be pulled up, driven high, or, if there are any externally connected devices, left in tristate. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state during reset.

Functionally, this pin is an output or an input, but, structurally, it is an

I/O because it either samples configuration input during reset, is a muxed pin, or has other manufacturing test functions. This pin is, therefore, described as an I/O for boundary scan.

Completed

4.4.2 Deep-sleep system-level recommendations

In deep-sleep mode, power to a large portion of the chip is turned off to save power. Dynamically turning portions of the die on or off must be coordinated between the SoC and the system. Both should know when it is safe to apply or remove power and indicate when the process is completed.

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Power design recommendations

The wake up sources of the SoC are eTSEC1, USB (optional), IRQ[0:9], general purpose timer, and GPIOs. All signals of the above interfaces should remain powered up during deep sleep mode. Other signals that should remain powered during deep sleep are: PORESET_B, HRESET_B, RESET_REQ_B, SYSCLK, DIFF_SYSCLK/DIFF_SYSCLK_B, ASLEEP,

EVT_B[0:4], CLK_OUT, IRQ_OUT, and some test signals.

The LS1021A Reference Design Board User Guide can be used as a reference design while designing a system with deepsleep mode.

Table 11. Deep-sleep system level checklist

Item

For external power supply requirements, see the QorIQ LS1021A Data Sheet.

For power sequencing in deep sleep mode, see the QorIQ LS1021A Data Sheet.

See the deep-sleep entry indicative sequence and the deep-sleep exit indicative sequence in the QorIQ

LS1021A Reference Manual.

When the I/O supplies are switched off, the corresponding I/Os should not be driven by any peripheral. It is recommended to switch off the peripheral devices connected to switched-off interfaces to avoid any damage to the device.

If the peripheral device is not switched off, please ensure that the output pins of the peripheral device are driven into high impedance state or appropriately isolated.

All the pull up resistors should be connected to their respective power supplies. See the QorIQ LS1021A

Data Sheet.

When V

DDC

and V

DD

are supplied by the same power source, ensure switching events do not trigger transient voltages, nor trip voltage monitors.

VeTSEC clocking in deep sleep:

• VeTSEC is clocked with 2* 125 MHz GTX_CLK125 from PHY in RGMII mode.

• VeTSEC is clocked with system clock in MII mode.

Completed

EC1_GTX_CLK125/MII_CRS

EC2_GTX_CLK125

SCFG _EMIIOCR

[GTXCLXSEL]

PLATFORM CLOCK

Clock double

+

Duty cycle reshaper

System clock

250MHz

125MHz

Duty cycle corrected clock

VeTSEC core clock during deep sleep

SCFG_FMCLKDPSLPCR

[CLKCTRL]

VeTSEC

MAC 1

MAC 2

125MHz

RGMII1 TX CLK

RGMII2 TX CLK

Figure 14. Clocking in deep sleep mode

DDR controller in deep sleep:

• G1V

DD

to DDR controller is switched OFF.

• GV

DD

to SDRAM memory remains ON.

• Separate power planes are required for DDR controller and SDRAM memory.

• SDRAM is powered ON and in self refresh.

• MCKE should be driven low by a board-level pulldown (controller cannot guarantee a low output with

G1V

DD

powered down).

• Deep-sleep wake up requires that RESET to the DDR memory be masked.

Notes:

1. RGMII is supported at 1.8 V to help lower deep-sleep power consumption.

2. Deep sleep on MII interface may not be loss-less.

3. DDR3L RDIMM is not supported in deep sleep.

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Interface recommendations

5 Interface recommendations

5.1 DDR controller recommendations

The memory interface controls main memory accesses.

5.1.1 DDR SDRAM memory interface 1 pin termination recommendations

Table 12. DDR SDRAM memory interface 1 pin termination checklist

Signal Name

DDR3L signal

D1_MAPAR_ERR_B

DDR4 signal

ALERT_B I

I/O type

D1_MAPAR_OUT

D1_MA[0:15]

D1_MBA[0:2]

D1_MCAS_B

D1_MCKE[0:1]

D1_MCK[0:1]

PAR O

O

O

O

O

O

Used Not Used

This pin is an open drain output from registered

DIMMs. Ensure that a 2-10 kΩ pull up to G1V

DD this pin.

is present on

This pin should be pulled up.

May be left unconnected.

If the controller supports the optional D1_MAPAR_OUT and D1_MAPAR_ERR_B signals, ensure that they are hooked up as follows:

• D1_MAPAR_OUT (from the controller) =>

PAR_IN (at the RDIMM)

• ERR_OUT (from the

RDIMM) =>

D1_MAPAR_ERR_B (at the controller)

Must be properly terminated to VTT.

Must be properly terminated to VTT.

Must be properly terminated to VTT.

May be left unconnected.

May be left unconnected.

May be left unconnected.

This output is actively driven during reset rather than being tri-stated during reset.

Must be properly terminated to VTT.

Ensure proper termination.

Table continues on the next page...

May be left unconnected.

May be left unconnected.

Complete d

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Interface recommendations

Table 12. DDR SDRAM memory interface 1 pin termination checklist (continued)

Signal Name

DDR3L signal DDR4 signal

I/O type Used Not Used Complete d

D1_MCK[0:1]_B

D1_MCS[0:3]_B

D1_MDIC[0:1]

D1_MDM[0:3,8]

D1_MDQS[0:3,8]

D1_MDQS[0:3,8]_B

D1_MDQ[0:31]

D1_MECC[0:3]

D1_MODT[0:1]

O

O

I/O

O

I/O

I/O

I/O

I/O

O

Ensure proper termination.

Must be properly terminated to VTT.

MDIC[0] must be grounded through a 162 Ω precision 1% resistor and MDIC[1] must be connected to GV

DD

through a

162 Ω precision 1% resistor.

For either full or half driver strength calibration of DDR

I/Os, use the same MDIC resistor value of 162 Ω.

Memory controller register setting can be used to determine whether automatic calibration is done to full or half drive strength. These pins are used for automatic calibration of the DDR3L/

DDR4 I/Os.

Ensure the MODT signals are connected correctly. LS1021A does not support two dualranked DIMMs topology.

NOTE: All unused MCK pins should be disabled via the

DCFG_CCSR_DDRCLKDR register.

Ensure proper termination.

NOTE: All unused MCK pins should be disabled via the

DCFG_CCSR_DDRCLKDR register.

May be left unconnected.

May be left unconnected.

May be left unconnected.

May be left unconnected.

May be left unconnected.

May be left unconnected.

May be left unconnected.

May be left unconnected.

For quad-ranked DIMMS, it is recommended to obtain a data sheet from the memory supplier to confirm required signals. But, in general, each controller needs MCS(0:3),

MODT(0:1), and MCKE(0:1) connected to the one quadranked DIMM. These pins are

Table continues on the next page...

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Interface recommendations

Table 12. DDR SDRAM memory interface 1 pin termination checklist (continued)

Signal Name

DDR3L signal DDR4 signal

I/O type Used Not Used Complete d

D1_MRAS_B

D1_MWE_B

D1_MVREF

O

O

I/O actively driven during reset instead of being released to high impedance.

Must be properly terminated to VTT.

Must be properly terminated to VTT.

May be left unconnected.

May be left unconnected.

DDR reference voltage: 0.49 x

GV

DD

to 0.51 x G1V

DD

.

D1_MVREF can be generated using a divider from GV

DD

as

MVREF. Another option is to use supplies that generate

GV

DD

, VTT, and D1_MVREF voltage. These methods help reduce differences between

GV

DD

and MVREF.

D1_MVREF generated from a separate regulator is not recommended, because

D1_MVREF does not track

GV

DD

as closely.

5.1.2 DDR system-level recommendations

Table 13. DDR system-level checklist

Item

General

DDR3L /DDR4 mode selection is through por-config signal cfg_dram_type. Ensure that the pin is configured correctly as per the DDR mode. Setting DDR4 mode while applying GV

DD

= 1.35 V can damage the I/Os.

Data Bus inversion (DBI) signals are muxed on Data Mask (D1_MDM) signals and are optional function for

DDR4. Only one function can be used at a time.

PORESET_B assertion should also reset SDRAM memory.

For deep-sleep-related recommendations, see

Deep-sleep system-level recommendations .

Completed

NOTE

Stacked memory for DDR4 is not supported.

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Interface recommendations

5.2 Integrated flash controller (IFC) pin termination recommendations

NOTE

1. For LS1021A device configuration, IFC_A16 must be pulled down and IFC_A17 must be pulled up during power-on reset.

2. For LS1022A device configuration, IFC_A16 must be pulled up and IFC_A17 must be pulled down during power-on reset.

3. For LS1020A device configuration, IFC_A16 and IFC_A17 must be pulled up during power-on reset.

Signal Name

IFC_AD[0:15]

IFC_AVD

IFC_A16

IFC_A17

IFC_A[18:19]

IFC_A[20:21]

IFC_A[22:27]

IFC_BCTL

IFC_CLE

Table 14. Integrated flash controller pin termination checklist

O

O

I/O type

I/O

O

O

O

O

O

O

Used Not Used

This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. The internal pull-up resistor value for applicable IFC pins is ~33 kΩ. This pull-up is designed such that it can be overpowered by an external 4.7 kΩ resistor. However, if the signal is intended to be high after reset, and if there is any device on the net that might pull down the value of the net at reset, a pull-up or active driver is needed.

Pin must

NOT be pulled down during power-on reset. This pin may be pulled up, driven high, or, if there are any externally connected devices, left in tristate. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state during reset.

Must be pulled down during power-on reset. For details, see the notes at the top of this table.

Pin must NOT be pulled down during power-on reset. This pin may be pulled up, driven high, or, if there are any externally connected devices, left in tristate. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state during reset. For details, see the notes at the top of this table.

Pin must

NOT be pulled down during power-on reset. This pin may be pulled up, driven high, or, if there are any externally connected devices, left in tristate. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state during reset.

This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. The internal pull-up resistor value for applicable IFC pins is ~33 kΩ. This pull-up is designed such that it can be overpowered by an external 4.7 kΩ resistor. However, if the signal is intended to be high after reset, and if there is any device on the net that might pull down the value of the net at reset, a pull-up or active driver is needed.

Functionally, this pin is an I/O because it either samples configuration input during reset, is a muxed pin, or has other manufacturing test functions. This pin is, therefore, described as an I/O for boundary scan.

Connect as needed.

May be left unconnected.

This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. The internal pull-up resistor value for applicable IFC pins is ~33 kΩ. This pull-up is designed such that it can be overpowered by an

Table continues on the next page...

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Signal Name

IFC_CLK[0:1]

IFC_CS[0:6]_B

IFC_NDDDR_CLK

IFC_NDDQS

IFC_OE_B

IFC_TE

Interface recommendations

Table 14. Integrated flash controller pin termination checklist (continued)

IFC_PAR[0:1]

IFC_PERR_B

IFC_RB[0:1]_B

IFC_RB[2:3]_B

IFC_WE[0]_B

IFC_WP[0]_B

IFC_WP[1:3]_B

I

O

O

O

I/O

O

I

I

I/O

O

O

O

O

I/O type Used Not Used

external 4.7 kΩ resistor. However, if the signal is intended to be high after reset, and if there is any device on the net that might pull down the value of the net at reset, a pull-up or active driver is needed.

May be left unconnected.

This output is actively driven during reset rather than being tristated during reset.

Recommend that a weak pull-up resistor (2-10 kΩ) be placed on this pin to the respective power supply.

May be left unconnected.

This output is actively driven during reset rather than being tristated during reset.

Connect as needed.

May be left unconnected.

May be left unconnected.

This pin has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. This pin should have an optional pull down resistor on board.

Connect as needed.

May be left unconnected.

Pull high through a 2-10 kΩ resistor to BV

DD

.

Recommend that a weak pull-up resistor (2-10 kΩ) be placed on this pin to the respective power supply.

Functionally, this pin is an output or an input, but, structurally, it is an

I/O because it either samples configuration input during reset, is a muxed pin, or has other manufacturing test functions. This pin is, therefore, described as an I/O for boundary scan.

This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. The internal pull-up resistor value for applicable IFC pins is ~33 kΩ. This pull-up is designed such that it can be overpowered by an external 4.7 kΩ resistor. However, if the signal is intended to be high after reset, and if there is any device on the net that might pull down the value of the net at reset, a pull-up or active driver is needed.

This pin has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. This pin should have an optional pull down resistor on board. This is required to support

DIFF_SYSCLK/DIFF_SYSCLK_B.

Pin must NOT be pulled down during power-on reset. This pin may be pulled up, driven high, or, if there are any externally connected devices, left in tristate. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state during reset.

Connect as needed.

This pin can be left unconnected.

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Interface recommendations

5.3 DUART pin termination recommendations

Table 15. DUART pin termination checklist

Signal Name

UART[1:2]_CTS_B

UART[1:2]_RTS_B

UART[1:4]_SIN

UART[1:4]_SOUT

I

I

O

O

I/O type Used

The functionality of these pins is determined by the UART_BASE and UART_EXT fields in the reset configuration word

(RCW[UART_BASE],

RCW[UART_EXT]).

The functionality of these pins is determined by the UART_BASE and UART_EXT fields in the reset configuration word

(RCW[UART_BASE],

RCW[UART_EXT]).

The functionality of these pins is determined by the UART_BASE and UART_EXT fields in the reset configuration word

(RCW[UART_BASE],

RCW[UART_EXT]).

The functionality of these pins is determined by the UART_BASE and UART_EXT fields in the reset configuration word

(RCW[UART_BASE],

RCW[UART_EXT]).

Not Used

Pull high through a 2-10 kΩ resistor to DV

DD

/D1V

DD

, or else program as a GPIO and output.

Program as GPIOs and outputs.

Program as GPIOs and outputs.

Program as GPIOs and outputs.

Completed

5.4 LPUART pin termination recommendations

Signal Name

LPUART[1:3]_CTS_B I

Table 16. LPUART pin termination checklist

I/O type Used

The functionality of

LPUART1_CTS_B is determined by the UART_BASE and

UART_EXT fields in the reset configuration word

(RCW[UART_BASE],

RCW[UART_EXT]).

The functionality of

LPUART[2:3]_CTS_B is determined by the SDHC_BASE and SDHC_EXT fields in the reset configuration word

(RCW[SDHC_BASE],

RCW[SDHC_EXT]).

Table continues on the next page...

Not Used

Program as GPIOs and outputs.

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Signal Name

LPUART[1:3]_RTS_B

LPUART[1:6]_SIN

LPUART[1:6]_SOUT

Interface recommendations

Table 16. LPUART pin termination checklist (continued)

I

O

I/O type

O

Used

The functionality of

LPUART1_RTS_B is determined by the UART_BASE and

UART_EXT fields in the reset configuration word

(RCW[UART_BASE],

RCW[UART_EXT]).

The functionality of

LPUART[2:3]_RTS_B is determined by the SDHC_BASE and SDHC_EXT fields in the reset configuration word

(RCW[SDHC_BASE],

RCW[SDHC_EXT]).

The functionality of

LPUART[1:2]_SIN and

LPUART[4]_SIN is determined by the UART_BASE and UART_EXT fields in the reset configuration word (RCW[UART_BASE],

RCW[UART_EXT]).

The functionality of

LPUART[5:6]_SIN and

LPUART[3]_SIN is determined by the SDHC_BASE and SDHC_EXT fields in the reset configuration word (RCW[SDHC_BASE],

RCW[SDHC_EXT]).

The functionality of

LPUART[1:2]_SOUT and

LPUART[4]_SOUT is determined by the UART_BASE and

UART_EXT fields in the reset configuration word

(RCW[UART_BASE],

RCW[UART_EXT]).

The functionality of

LPUART[5:6]_SOUT and

LPUART[3]_SOUT is determined by the SDHC_BASE and

SDHC_EXT fields in the reset configuration word

(RCW[SDHC_BASE],

RCW[SDHC_EXT]).

Not Used

Program as GPIOs and outputs.

Program as GPIOs and outputs.

Program as GPIOs and outputs.

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Interface recommendations

5.5 I

2

C pin termination recommendations

Table 17. I

2

C pin termination checklist

Signal Name

IIC1_SCL

IIC1_SDA

IIC2_SCL

IIC2_SDA

IIC3_SCL

I/O type

I/O

I/O

I/O

I/O

I/O

Used

The functionality of this signal is determined by the IIC_EXT and

IIC_BASE field in the reset configuration word

(RCW[IIC_EXT]) and

(RCW[IIC_BASE]).

Not Used

Pull high through a 2-10 kΩ resistor to D1V

DD

.

This pin is an open-drain signal.

Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective power supply.

The functionality of this signal is determined by the IIC_EXT and

IIC_BASE field in the reset configuration word

(RCW[IIC_EXT]) and

(RCW[IIC_BASE]).

Pull high through a 2-10 kΩ resistor to D1V

DD

.

This pin is an open-drain signal.

Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective power supply.

The functionality of this signal is determined by the IIC_EXT and

IIC_BASE field in the reset configuration word

(RCW[IIC_EXT]) and

(RCW[IIC_BASE]).

Pull high through a 2-10 kΩ resistor to DV

DD

.

This pin is an open-drain signal.

Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective power supply.

The functionality of this signal is determined by the IIC_EXT and

IIC_BASE field in the reset configuration word

(RCW[IIC_EXT]) and

(RCW[IIC_BASE]).

Pull high through a 2-10 kΩ resistor to DV

DD

.

This pin is an open-drain signal.

Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective power supply.

The functionality of this signal is determined by the IIC_EXT and

IIC_BASE field in the reset configuration word

(RCW[IIC_EXT]) and

(RCW[IIC_BASE]).

Pull high through a 2-10 kΩ resistor to BV

DD

.

Table continues on the next page...

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Signal Name

IIC3_SDA

Interface recommendations

Table 17. I

2

C pin termination checklist (continued)

I/O type Completed

I/O

Used

This pin is an open-drain signal.

Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective power supply.

The functionality of this signal is determined by the

IFC_GRP_E1_EXT and

IFC_GRP_E1_BASE field in the reset configuration word

(RCW[IFC_GRP_E1_EXT]) and

(RCW[IFC_GRP_E1_BASE])

Not Used

Pull high through a 2-10 kΩ resistor to BV

DD

.

This pin is an open-drain signal.

Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective power supply.

5.6 eSDHC pin termination recommendations

Table 18. eSDHC pin termination checklist

Signal Name

SDHC_CLK

SDHC_CMD

SDHC_DAT[1:7]

SDHC_CLK_SYNC_IN I

I/O type

I/O

I/O

I/O

Used

The functionality is determined by the IIC_BASE and IIC_EXT fields in the reset configuration word

(RCW[IIC_BASE] and

RCW[IIC_EXT]).

The functionality is determined by the IIC_BASE and IIC_EXT fields in the reset configuration word

(RCW[IIC_BASE] and

RCW[IIC_EXT]).

SDHC_DAT[0:3] should be pulled high through a 10-100 kΩ resistor to EV

DD

.

SDHC_DAT[4:7] should be pulled high through a 10-100 kΩ resistor to DV

DD

.

The functionality is determined by the SDHC_EXT and SDHC_BASE fields in the reset configuration word (RCW[SDHC_EXT] and

(RCW[SDHC_BASE]).

The functionality is determined by the IRQ_BASE and IRQ_EXT fields in the reset configuration word (RCW[IRQ_BASE] and

RCW[IRQ_EXT]).

Not Used

Program as GPIO and output.

Program as a GPIO and output.

Unused pins should be pulled high through a 10-100 kΩ resistor to

EV

DD

/DV

DD

or programmed as

GPIOs and as outputs.

Can be programmed for other functions or pulled down using a weak resistor.

Table continues on the next page...

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Interface recommendations

Table 18. eSDHC pin termination checklist (continued)

Signal Name

SDHC_VS O

I/O type Used

The functionality is determined by the IRQ_BASE and IRQ_EXT fields in the reset configuration word (RCW[IRQ_BASE] and

RCW[IRQ_EXT]).

Not Used

Can be left floating or programmed for other functions.

SDHC_CLK_SYNC_OUT O

SDHC_CD_B

SDHC_WP I

I

NOTE: External voltage select, to change voltage of external regulator.

The functionality is determined by the SDHC field in the reset configuration word (RCW[SDHC]).

The functionality is determined by the IIC_BASE and IIC_EXT field in the reset configuration word

(RCW[IIC_BASE] and

RCW[IIC_EXT]).

The functionality is determined by the IIC_BASE and IIC_EXT fields in the reset configuration word

(RCW[IIC_BASE] and

RCW[IIC_EXT]).

Can be left floating or programmed for another function.

These pins should be pulled high through a 10-100 kΩ resistor to

DV

DD

or programmed as GPIOs and output.

These pins should be pulled high through a 10-100 kΩ resistor to

DV

DD

or programmed as GPIOs and output.

Notes:

1. Separate DIR signals are implemented to support card interrupt on DAT1 in single-bit mode.

2. SDHC_CLK_SYNC_OUT to SDHC_CLK_SYNC_IN connection is required in SDR50 and DDR50 modes only.

Completed

3. In SDR50 and DDR50 modes, all the input signals are sampled with respect to SDHC_CLK_SYNC_IN.

4. SDHC_CLK_SYNC_OUT and SDHC_CLK_SYNC_IN should be routed as close as possible to the card, with minimum skew with respect to SD_CLK.

5. When using 8-bit MMC/eMMC configuration, EV

DD

and DV

DD

should be set at same voltage.

5.6.1 eSDHC system-level recommendations

Table 19. eSDHC system-level checklist

SD Card Connections (FS and HS mode)

DV

DD

/EV

DD

configured for 3.3 V

Item

SD card interfacing (8 bit is not supported)

Table continues on the next page...

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Interface recommendations

Table 19. eSDHC system-level checklist (continued)

Item Completed

LS1021A

3.3 V 3.3 V

CMD, DAT[0], DAT[1:3],

CLK, CD_B, WP

SD

CARD

Figure 15. FS and HS modes

SD Card Connections (FS and HS modes with voltage translator)

EV

DD

configured for 1.8 V

LS1021A

1.8V

1.8V

Voltage

Translator

3.3V

3.3V

SD

CARD

CMD, DAT[0], DAT[1:3], CLK, CD_B, WP

Figure 16. FS and HS modes

SD card connections (SDR12, 25, 50, 104 and DDR50 modes without voltage translator)

UHS-I modes, work on 1.8 V signalling

SYNC_OUT, SYNC_IN connections are required in DDR50 mode only

NOTE: Resistor R = 10K is needed when RCW loading is required to be done from SD card.

Dual Voltage

Regulator

(3.3V/1.8V)

Voltage

Select

SDHC_VS

LS1021A

R

3.3 V/1.8V

3.3 V/1.8V

SDHC_CLK_SYNC_OUT

SD

CARD

SDHC_CLK_SYNC_IN

CMD, DAT[0], DAT[1:3], CLK, CD_B, WP

Figure 17. SDR12, 25, 50, 104 and DDR50 modes

SD card connections (SDR12, 25, 50, 104 and DDR50 Modes with voltage translator)

UHS-I modes, work on 1.8V signalling.

SYNC_IN connections are required in DDR50 modes only

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Interface recommendations

Table 19. eSDHC system-level checklist (continued)

Item

NOTE: Resistor R=10K is needed when RCW loading is required to be done from SD card.

Voltage

Regulator

(1.8V)

Voltage

Regulator

(3.3V

Voltage

Select

SDHC_VS

R

LS1021A

1.8V

SDHC_CLK_SYNC_IN

Voltage

Translator

(3.3V/1.8V)

3.3V/1.8V

SD-CARD

Boot @ 3.3V

work @ 1.8V

Completed

CMD, DAT[0], DAT[1:3], CLK, CD_B, WP

DIR

Figure 18. SDR12, 25, 50, 104 and DDR50 modes

MMC Interfacing

MMC card connections (FS, HS, HS200 modes)

8-bit MMC requires EV

DD

DAT[4:7] are on DV

DD

.

and DV

DD

configured at same voltage. This is because DAT[0:3] are on EV

DD

and

LS1021A

3.3 V/1.8V

3.3 V/1.8V

MMC

CARD

CMD, DAT[0], DAT[1:7], CLK, CD

Figure 19. FS, HS, HS200 modes for MMC

NOTE: Voltage translator requirment depends on the chosen MMC/eMMC voltage and DV configuration.

DD

/EV

DD

voltage

MMC card connection in DDR mode

8-bit operation cannot be supported due to pin multiplexing constraints.

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Table 19. eSDHC system-level checklist

Item

Interface recommendations

Completed

LS1021A

3.3 V/1.8V

3.3 V/1.8V

SDHC_CLK_SYNC_OUT

SDHC_CLK_SYNC_IN eMMC

CMD, DAT[0], DAT[1:3], CLK, CD

In DDR mode, all the input signals are sampled with respect to SYNC_IN.

Figure 20. DDR mode without voltage translator

LS1021A

1.8V

3.3V

Voltage

Translator

(3.3V/1.8V)

DIR

SDHC_CLK_SYNC_IN

CMD, DAT[0], DAT[1:3], CLK, CD

DIR

In DDR mode, all the input signals are sampled with respect to SYNC_IN

Voltage translator is not needed for 1.8V MMC

Figure 21. DDR mode with voltage translator

eMMC (3.3V)

5.7 EVT and IRQ pin termination recommendations

Table 20. EVT and IRQ pin termination checklist

Signal Name

EVT0_B

EVT1_B

I/O type

I/O

I/O

Used

This pin can be used for an offchip event when configured as an input or, for example, assert event to on-board FPGAs when configured as output.

This pin can be used for an offchip event when configured as an input or, for example, assert event

Not Used

This pin should be pulled high through 2-10 kΩ resistors to

O1V

DD

or else programmed as

O/P through

EPU_EPEVTCRn[DIR] = 1 and left floating.

This pin should be pulled high through 2-10 kΩ resistors to

O1V

DD

or else programmed as

O/P through

Table continues on the next page...

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Interface recommendations

Table 20. EVT and IRQ pin termination checklist (continued)

Signal Name

EVT2_B

EVT3_B

I/O type

I/O

I/O

Used

to on-board FPGAs when configured as output.

EVT2_B serves the alternate function of the POWER_EN pin

(output) for deep sleep.

POWER_EN is connected to the external power switch device or regulator and indicates to the external power regulator to toggle the power switch to off mode during deep-sleep entry.

EPU_EPEVTCRn[DIR] = 1 and left floating.

This pin should be pulled high through 2-10 kΩ resistors to

O1V

DD

, or else programmed as

O/P through

EPU_EPEVTCRn[DIR] = 1 and left floating.

Not Used

During PORESET_B assertion,

EVT2_B is a high impedance input so there must be an external pull up on board on EVT2_B to ensure

POWER_EN is asserted at power up. Until PORESET_B gets deasserted, EVT2_B

(POWER_EN) should not be sampled.

EVT3_B serves the alternate function of the POWER_OK pin

(input) for deep sleep. Connect

POWER_EN directly to the external power switch device.

• 0 = POWER from regulator is not stable.

• 1 = POWER from regulator is stable.

This pin should be pulled high through 2-10 kΩ resistors to

O1V

DD

, or else programmed as

O/P through

EPU_EPEVTCRn[DIR] = 1 and left floating.

EVT4_B

EVT9_B

I/O

I/O

If there is no external source of

POWER_OK, then the

POWER_OK has to be tied to logic 1 on the board.

This pin should be configured as an output. It is intended for MCKE isolation, which is off-chip/onboard.

The functionality is determined by the EVT9_B field in the reset configuration word

(RCW[EVT9_B]).

This is an output pin used to enable isolation on the board during deep sleep. This pin isolation is required for isolating output pins that are powered down in LS1021A, which are interfacing with other ICs. For example, IFC pins are used to interface flash interface, and the O/P pins of

Table continues on the next page...

This pin should be pulled high through 2-10 kΩ resistors to

O1V

DD

, or else programmed as

O/P through

EPU_EPEVTCRn[DIR] = 0 and left floating.

This pin should be pulled high through 2-10 kΩ resistors to

O1V

DD

, or else programmed as

O/P through

EPU_EPEVTCRn[DIR] = 1 and left floating.

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IRQ0

IRQ1

IRQ2

IRQ3

Signal Name

IRQ[4:5]

Interface recommendations

Table 20. EVT and IRQ pin termination checklist (continued)

I

I/O type Used

LS1021A must be isolated to safe values if they intend not to switch off the flash power supply.

Not Used Completed

I

I

I

I —

Pull high through a 2-10 kΩ resistor to O1V

DD

.

Pull high through a 2-10 kΩ resistor to OV

DD

.

Pull high through a 2-10 kΩ resistor to L1V

DD

.

Pull high through a 2-10 kΩ resistor to LV

DD

.

Pull high through a 2-10 kΩ resistor to DV

DD

.

5.8 Trust pin termination recommendations

Table 21. Trust pin termination checklist

Signal Name

TA_BB_TMP_DETECT_B

TA_BB_RTC

TA_TMP_DETECT_B I

I

I

I/O type Used

If a tamper sensor is used, it must maintain the signal at the specified voltage (1.8 V) until a tamper is detected. A 1 kΩ pull-down resistor is strongly recommended.

Not Used

Tie this pin to ground

(GND). This forces the

SecMon to enter the nonsecure state.

If trust is used without tamper sensors, tie high.

Functionally, this pin is an output or an input, but, structurally, it is an I/O because it either samples configuration input during reset, is a muxed pin, or has other manufacturing test functions. This pin is, therefore, described as an

I/O for boundary scan.

If a tamper sensor is used, it must maintain the signal at the specified voltage (OV

DD

) until a tamper is detected. A 1 kΩ pull-down resistor is strongly recommended.

If trust is used without temper sensors, tie high.

Pull low through a 2-10 kΩ resistor to GND.

Tie this pin to ground

(GND). This forces the

SecMon to enter the nonsecure state.

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Interface recommendations

5.9 System control pin termination recommendations

Table 22. System control pin termination checklist

Signal Name

HRESET_B

PORESET_B

RESET_REQ_B

I

I/O type

I/O

O

Used Not Used

This pin is an open-drain signal and should be pulled high through a

2-10 kΩ resistor to the respective power supply.

This pin is required to be asserted as per the applicable chip data sheet, in relation to minimum assertion time and during power-up/ power-down. It is an input-only pin and must be asserted to sample power on configuration pins.

Pin must

NOT be pulled down during power-on reset.

This pin should be pulled high through a 2-10 kΩ resistor to the respective power supply and must not be pulled down during poweron reset.

Completed

Notes:

1. If on-board programming of NOR and NAND boot flash, QSPI boot flash, or SD card is needed, then maintain an option (may be via a jumper) that keeps PORESET_B and RESET_REQ_B disconnected from each other. Booting from a blank NAND flash or SPI flash causes boot error, which in turn causes assertion of RESET_REQ_B. When RESET_REQ_B is connected with

PORESET_B, the device goes in a recurring reset loop and does not provide enough time for JTAG to take control of the device and perform any operation.

2. PORESET_B should be asserted zero during the JTAG boundary scan operation and is required to be controllable on-board.

3. Recommend to use PORESET_B. HRESET_B is to be used for debug purpose only.

4. HRESET_B input must not be asserted during deep sleep.

5.10 Clock recommendations

5.10.1 Clock pin termination recommendations

Table 23. Clock pin termination checklist

Signal Name I/O type Used Not Used

EC1_GTX_CLK

EC1_GTX_CLK125

EC2_GTX_CLK

EC2_GTX_CLK125

EC3_GTX_CLK

EC3_GTX_CLK125 I

O

I

O

I

O The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC3 field in the reset configuration word

(RCW[EC3]).

Program as a GPIO and as an output.

May be left unconnected.

May be configured as a GPIO.

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Complete d

Freescale Semiconductor, Inc.

Interface recommendations

Table 23. Clock pin termination checklist (continued)

Signal Name I/O type Used Not Used Complete d

SYSCLK

DIFF_SYSCLK

DIFF_SYSCLK_B

RTC

DDRCLK

I

I

I

I

I This is the single-ended primary clock input to the chip. It supports a

64.0 MHz to 133.3 MHz clock range.

Note that 64 MHz SYSCLK reference frequency is specifically for Profibus support on QUICC

Engine.

These pins are the differential primary clock input to the chip.

These pins support 100 MHz only.

When used, these pins should be connected to a 100 MHz differential clock generator.

The functionality of this signal is determined by the RTC field in the reset configuration word

(RCW[RTC]).

The reference clock for the DDR controller supports a 64 MHz to

133.3 MHz input clock range.

This pin should be pulled low through a 2-10 kΩ resistor to GND.

1

These pins should be pulled low through a 2-10 kΩ resistor to GND, or they can be left floating.

3

Pull low through a 2-10 kΩ resistor to GND, or program pin as a GPIO and output.

This pin should be pulled low through a 2-10 kΩ resistor to GND.

4

2,

Notes:

1. In the "Single Oscillator Source" reference clock mode supported by LS1021A, DIFF_SYSCLK/DIFF_SYSCLK_B

(differential) clock inputs are used as primary clock inputs and SYSCLK is unused. Power-on-configuration signal cfg_eng_use0 selects between SYSCLK (single ended) and DIFF_SYSCLK/DIFF_SYSCLK_B (differential) clock inputs.

2. In the "Single Oscillator Source" reference clock mode, DIFF_SYSCLK/DIFF_SYSCLK_B clock inputs can be selected to feed the DDR PLL. RCW bits [DDR_REFCLK_SEL] are used for this selection and DDRCLK is unused.

3. When SYSCLK is chosen as the primary clock input to the chip, these pins are unused.

4. The options for RCW bits 186-187 (DDR_REFCLK_SEL, DDR reference clock selection) are as follows:

• 00 The DDRCLK pin provides the reference clock to the DDR PLL

• 10 DIFF_SYSCLK/DIFF_SYSCLK_B provides the reference clock to the DDR PLL

5.10.2 Clocking system-level recommendations

Table 24. Clocking system-level checklist

Item

"Single Oscillator Source" Reference Clock Mode

• In this clocking mode, DIFF_SYSCLK/DIFF_SYSCLK_B (differential) clock inputs are used as the primary clock input and SYSCLK is unused. Power-on-config signal cfg_eng_use0 selects between

SYSCLK (single ended) and DIFF_SYSCLK/DIFF_SYSCLK_B (differential) clock inputs.

• DIFF_SYSCLK/DIFF_SYSCLK_B clock inputs can be selected to feed the DDR PLL and DDRCLK is unused. RCW bits RCW[DDR_REFCLK_SEL] are used for this selection.

• The RCW[DDR_REFCLK_SEL] bit is used to select the clock input (DIFF_SYSCLK or DDRCLK) to the

DDR PLL.

Table continues on the next page...

Completed

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Interface recommendations

Table 24. Clocking system-level checklist (continued)

Item

EC1_GTX_CLK125

EC2_GTX_CLK125

EC3_GTX_CLK125

SYSCLK

DIFF_SYSCLK_B/DIFF_SYSCLK

On Board

Oscillator

100 MHZ

3 Differential outputs cfg_eng_use0

Duty Cycle

Reshaper

125 MHz duty cycle corrected clock

RGMII1 TX CLK (125 MHz) eTSEC

RGMII2 TX CLK (125 MHz)

RGMII3 TX CLK (125 MHz)

SCFG_ETSECCMCR[ETSECCM]

SYS_REF_CLK

0.6 - 1 GHz

Core PLL

Platform PLL

RCW[SYS_PLL_CFG]

RCW[SYS_PLL_RAT]

RCW[SYS_PLL_SPD]

300 MHZ

Platform Clock

RCW[USB3_REFCLK_SEL]

USB PHY

DDRCLK

RCW[DDR_REFCLK_SEL]

DDR

PLL

RCW[MEM_PLL_RAT]

RCW[MEM_PLL_CFG]

RCW[MEM_PLL_SPD]

1 G-1.6 G

DDR Controller

SerDes PLL1

SerDes PLL2

RCW[SD_REFCLK_SEL]

Figure 22. Single oscillator source clocking

Multiple Reference Clock Mode

• In this clocking mode, SYSCLK (single ended) clock input is used as a primary clock input. Power-onconfig signal cfg_eng_use0 selects between SYSCLK (single ended) and DIFF_SYSCLK/

DIFF_SYSCLK_B (differential) clock inputs.

• DDRCLK clocks the DDRPLL. RCW bits RCW[DDR_REFCLK_SEL] are used for this selection.

Completed

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Table 24. Clocking system-level checklist

Item

Interface recommendations

Completed

EC1_GTX_CLK125

EC2_GTX_CLK125

EC3_GTX_CLK125

Duty Cycle

Reshaper

125 MHz duty cycle corrected clock

RGMII1 TX CLK (125 MHz) eTSEC

RGMII2 TX CLK (125 MHz)

RGMII3 TX CLK (125 MHz)

SYSCLK

DIFF_SYSCLK_B/DIFF_SYSCLK

On Board

Oscillator

100 MHZ

3 Differential outputs

On Board

Oscillator

64 -100Mz

2 Single-ended outputs cfg_eng_use0

SCFG_ETSECCMCR[ETSECCM]

SYS_REF_CLK

0.6 - 1 GHz

Core PLL

Platform PLL

RCW[SYS_PLL_CFG]

RCW[SYS_PLL_RAT]

RCW[SYS_PLL_SPD]

300 MHZ

Platform Clock

RCW[USB3_REFCLK_SEL]

USB PHY

DDRCLK

RCW[DDR_REFCLK_SEL]

DDR

PLL

RCW[MEM_PLL_RAT]

RCW[MEM_PLL_CFG]

RCW[MEM_PLL_SPD]

1 G-1.6 G

DDR Controller

SerDes PLL1

SerDes PLL2

RCW[SD_REFCLK_SEL]

Figure 23. Multiple reference clocking

5.10.2.1 DIFF_SYSCLK/DIFF_SYSCLK_B system-level recommendations

Table 25. DIFF_SYSCLK/DIFF_SYSCLK_B system-level checklist

Completed Item

DIFF_SYSCLK/DIFF_SYSCLK_B can be selected to provide primary clock to the chip.

It is a Low Voltage Differential Signaling (LVDS) type clock driver but it has AC/DC characteristics identical to the SerDes reference clock inputs, which are High-Speed Current Steering Logic (HCSL)-compatible. This eases system design as the same clock driver can be used to provide the various differential clock inputs required by the chip.

DIFF_SYSCLK

100 Ohm

LVDS

RX

DIFF_SYSCLK_B

Figure 24. LVDS receiver

Interfacing DIFF_SYSCLK/DIFF_SYSCLK_B with other differential signaling levels

Table continues on the next page...

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Interface recommendations

Table 25. DIFF_SYSCLK/DIFF_SYSCLK_B system-level checklist

(continued)

Item

Connection with HCSL clock driver

HCSL CLK Driver Chip

CLK_Out

33Ω

DIFF_SYSCLK

Freescale device

Clock

100 Ω differential PWB trace

100 Ω

LVDS CLK

Receiver

33Ω

DIFF_SYSCLK_B

CLK_Out

Total 50 Ω assume clock driver's output impedance is about 16 Ω.

Clock driver vendor dependent source termination resistor

Figure 25. Interfacing with HCSL clock driver (reference only)

Connection with LVDS clock driver

Freescale device

LVDS CLK Driver chip

CLK_Out

Clock 100 Ω differential PWB trace

DIFF_SYSCLK

100 Ω

LVDS CLK

Receiver

CLK_Out

DIFF_SYSCLK_B

Completed

Figure 26. Interfacing with LVDS clock driver (reference only)

Connection with LVPECL clock driver

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Interface recommendations

Table 25. DIFF_SYSCLK/DIFF_SYSCLK_B system-level checklist

(continued)

Item Completed

LVPECL CLK

Driver chip

CLK_Out

DIFF_SYSCLK

Freescale device

Clock

CLK_Out

R2

R1

R2

100 Ω differential PWB trace

R1

R1=140 Ω to 240 Ω

DIFF_SYSCLK_B

100 Ω

LVDS CLK

Receiver

Figure 27. Interfacing with LVPECL clock driver (reference only)

Single-ended connection with clock driver

The DIFF_SYSCLK_B should be terminated to O1V

DD

/2.

Single-ended

CLK driver chip

Clock

CLK_Out

33 Ω

Total 50 Ω. Assume clock driver's output impedance is about 16 Ω.

DIFF_SYSCLK

100 Ω differential PWB trace

100 Ω

Freescale device

LVDS CLK receiver

DIFF_SYSCLK_B

O1VDD/2

Figure 28. Single-ended connection (reference only)

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Interface recommendations

5.11 Debug pin termination recommendations

Table 26. Debug pin termination checklist

Signal Name

CKSTP_OUT_B

CLK_OUT

EVT[0:4]_B

O

I/O type

O

I/O

Used

This pin is an open-drain signal.

Not Used

Functionally, this pin is an output or an input, but, structurally, it is an

I/O because it either samples configuration input during reset, is a muxed pin, or has other manufacturing test functions. This pin is, therefore, described as an I/O for boundary scan.

Recommend that a weak pull-up resistor (2-10 kΩ) be placed on this pin to the respective power supply.

CLK_OUT is for monitoring purposes only. Connect to test point to aid in debug.

This pin may be left unconnected.

This pin has a weak (~20 kΩ) internal pull-up P-FET that is always enabled.

Pull high through a 2-10 kΩ resistor to O1V

DD

.

Completed

5.12 DFT pin termination recommendations

Table 27. DFT pin termination checklist

Signal Name

SCAN_MODE_B

TEST_SEL_B I

I

I/O type Used Not Used

These are test signals for factory use only and must be pulled up (100

Ω to 1 kΩ) to the respective power supply for normal operation.

For JTAG compliant mode, this pin should have a pull up.

Completed

5.13 Analog signals pin termination recommendations

Table 28. Analog signals pin termination checklist

Signal Name

D1_TPA

FA_ANALOG_G_V

FA_ANALOG_PIN

TD1_ANODE

TD1_CATHODE

TH_TPA

I/O type

I/O

I/O

I/O

I/O

I/O

Used

Do not connect. This pin should be left floating.

Not Used

Connect to GND.

Connect to GND.

Connect to temp sensor.

Connect to temp sensor.

This pin should be tied to ground if the diode is not used for temperature monitoring.

This pin should be tied to ground if the diode is not used for temperature monitoring.

Do not connect. This pin should be left floating.

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Interface recommendations

5.14 SerDes 1 pin termination recommendations

The LS1021A SerDes block provides four high-speed serial communication lanes, which support a variety of protocols, including:

• Support for SGMII 1.25 Gbps

• Support for PCI Express (PEX) Gen 2 1x/2x/4x 2.5 or 5 Gbaud data rate per lane

• Support for SATA I, II, and III data rates 1.5, 3.0, and 6.0 Gbaud

Table 29. SerDes 1 pin termination checklist

Signal Name

SD1_IMP_CAL_RX

SD1_IMP_CAL_TX

SD1_PLL1_TPA

SD1_PLL1_TPD

SD1_PLL2_TPA

SD1_PLL2_TPD

SD1_REF_CLK[1:2]_N

SD1_REF_CLK[1:2]_P

SD1_RX[0:3]_N

SD1_RX[0:3]_P

SD1_TX[0:3]_N

SD1_TX[0:3]_P

I

I

I

I

I

I

O

O

O

O

O

O

I/O type Used Not Used

This pin requires a 200 Ω pull-up to the respective power supply.

This pin requires a 698 Ω pull-up to the respective power supply.

If the SerDes interface is entirely unused, the unused pin must be left unconnected.

If the SerDes interface is entirely unused, the unused pin must be left unconnected.

Do not connect. These pins should be left floating. Provide a test point if possible.

Do not connect. These pins should be left floating. Provide a test point if possible.

Do not connect. These pins should be left floating. Provide a test point if possible.

Do not connect. These pins should be left floating. Provide a test point if possible.

Ensure clocks are driven from an appropriate clock source, as per the default allocation with the

RCW settings.

Ensure clocks are driven from an appropriate clock source, as per the default allocation with the

RCW settings.

If the SerDes n lanes are unused, connect to SDn GND, where n corresponds to the unused SerDes lanes.

If the SerDes n lanes are unused, connect to SDn GND, where n corresponds to the unused SerDes lanes.

Ensure the pins are correctly terminated for the interface type used.

Ensure the pins are correctly terminated for the interface type used.

Ensure the pins are correctly terminated for the interface type used.

Ensure the pins are correctly terminated for the interface type used.

If the SerDes interface is entirely or partly unused, the unused pins must be connected to SDn GND.

If the SerDes interface is entirely or partly unused, the unused pins must be connected to SDn GND.

If the SerDes interface is entirely unused, the unused pin must be left unconnected.

If the SerDes interface is entirely unused, the unused pin must be left unconnected.

Completed

Notes:

1. In the RCW configuration field SRDS_PLL_PD_S1, the respective bits for each unused PLL must be set to power it down. The

SerDes module is disabled when both of its PLLs are turned off.

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Interface recommendations

Table 29. SerDes 1 pin termination checklist

Signal Name I/O type Used Not Used Completed

2. After POR, if an entire SerDes module is unused, it must be powered down by clearing the SDEN fields of its corresponding

PLL1 and PLL2 reset control registers (SRDSxPLL1RSTCTL).

3. Unused lanes must be powered down by clearing the RRST and TRST fields and setting the RX_PD and TX_PD fields in the corresponding lane's general control register (SRDSxLNmG0).

4. A spread-spectrum reference clock is permitted for PCI Express. However, if any other high-speed interface, such as SGMII or

SATA, is used concurrently on the same SerDes bank, spread-spectrum clocking is not permitted.

5. RCW[SRDS_PRTCL_S1] selection should be strictly according to product personality.

5.15 USB1 PHY pin termination recommendations

Table 30. USB1 PHY pin termination checklist

Signal Name

USB1_D_M

USB1_D_P

USB1_ID

USB1_RESREF

USB1_RX_M

USB1_RX_P

USB1_TX_M

USB1_TX_P

USB1_VBUS I

I

I

I

I/O type

I/O

I/O

I/O

O

O

Used

USB PHY Data Minus

USB PHY Data Plus

Not Used

Do not connect. These pins should be left floating.

Do not connect. These pins should be left floating.

USB PHY ID Detect

USB PHY Impedance Calibration

NOTE: A 200 Ω with 1% 100ppm/C precision external resistor should be used to connect USB1_RESREF to ground. It cannot be shared with other USB

PHY.

USB PHY 3.0 Receive Data

(negative)

USB PHY 3.0 Receive Data

(positive)

Do not connect. These pins should be left floating.

Do not connect. These pins should be left floating.

Connect to ground (GND).

Connect to ground (GND).

USB PHY 3.0 Transmit Data

(negative)

USB PHY 3.0 Transmit Data

(positive)

USB PHY VBUS. Expecting a 5V signal.

Do not connect. These pins should be left floating.

Do not connect. These pins should be left floating.

Do not connect. These pins should be left floating.

Table continues on the next page...

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Signal Name

USB1_DRVVBUS

USB1_PWRFAULT

Interface recommendations

Table 30. USB1 PHY pin termination checklist (continued)

I

O

I/O type

NOTE:

Used

• When the USB controller is configured as

HOST, this signal is not used.

• When the USB controller is configured as

DEVICE, this signal is reqired.

VBUS power enable. Optional. For example, if an external hub is used, it can handle this signal.

The functionality of the

USB1_DRVVBUS signal is determined by the RCW[SDHC] field in the reset configuration word.

Indicates that a VBUS fault has occurred. Optional. For example, if an external hub is used, it can handle this signal.

The functionality of the

USB1_PWRFAULT signal is determined by the RCW[SDHC] field in the reset configuration word.

Not Used Completed

5.15.1 USB1 PHY connections

This section describes the hardware connections required for the USB PHY.

This figure shows the VBUS interface for the chip.

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Interface recommendations

VBUS

(USB connector)

VBUS charge pump

USB_DRVVBUS

USB_PWRFAULT

USB1_VBUS

LS102xA

Figure 29. USB1 PHY VBUS interface

5.16 Ethernet Management Interface pin termination recommendations

Table 31. Ethernet Management Interface pin termination checklist

Signal Name

EMI1_MDC

EMI1_MDIO

O

I/O type

I/O

Used

This pin should be pulled high through a 2-10 kΩ resistor to

L1V

DD

.

Not Used

May be left unconnected or can be configured as a GPIO.

This pin should be tied low through a 2-10 kΩ resistor to ground

(GND), or may be configured as a

GPIO and as an output.

Completed

5.17 Ethernet controller 1 pin termination recommendations

Table 32. Ethernet controller 1 pin termination checklist

Signal Name I/O type Completed

EC1_GTX_CLK

EC1_GTX_CLK125 I

O

Used

In RGMII mode

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

Program as a GPIO and as an output.

Not Used

Program as a GPIO and as an output.

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Interface recommendations

Table 32. Ethernet controller 1 pin termination checklist (continued)

Signal Name

EC1_RXD[0:3]

EC1_RX_CLK

EC1_RX_DV

EC1_TXD[0:3]

EC1_TX_EN

EC1_TX_CLK

EC1_RX_ER

EC1_RXD[0:3]

EC1_RX_CLK

EC1_RX_DV

EC1_TXD[0:3]

I

I

I

I

I

I

I

I

O

O

O

I/O type Used

The functionality of these signals is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

The functionality of these signals is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

This pin requires an external 1 kΩ pull-down resistor to prevent PHY from seeing a valid Transmit

Enable before it is actively driven.

In MII mode

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

The functionality of these signals is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

The functionality of these signals is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

Not Used

Can be configured as a GPIO.

Can be configured as a GPIO.

Can be configured as a GPIO.

May be left unconnected or can be configured as GPIOs.

May be left unconnected or can be configured as a GPIO.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Can be configured as a GPIO.

Can be configured as a GPIO.

Can be configured as a GPIO.

May be left unconnected or can be configured as GPIOs.

Table continues on the next page...

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Interface recommendations

Table 32. Ethernet controller 1 pin termination checklist (continued)

Signal Name

EC1_TX_EN O

I/O type Used

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC1]).

This pin requires an external 1 kΩ pull-down resistor to prevent PHY from seeing a valid Transmit

Enable before it is actively driven.

Not Used

May be left unconnected or can be configured as a GPIO.

Completed

5.18 Ethernet controller 2 pin termination recommendations

Table 33. Ethernet controller 2 pin termination checklist

Signal Name I/O type Completed

EC2_GTX_CLK

EC2_GTX_CLK125

EC2_RXD[0:3]

EC2_RX_CLK

EC2_RX_DV

EC2_TXD[0:3]

EC2_TX_EN

I

I

I

I

O

O

O

Used

In RGMII mode

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of these signals is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of these signals is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

This pin requires an external 1 kΩ pull-down resistor to prevent PHY from seeing a valid Transmit

Enable before it is actively driven.

These pins may be left unconnected or configured as

GPIOs.

Not Used

This pin may be left unconnected.

This pin may be left unconnected.

This pin can be configured as a

GPIO.

This pin can be configured as a

GPIO.

This pin can be configured as a

GPIO.

This pin may be left unconnected or configured as a GPIO.

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Interface recommendations

Table 33. Ethernet controller 2 pin termination checklist (continued)

Signal Name I/O type Completed

EC2_TX_CLK

EC2_RX_ER

EC2_RXD[0:3]

EC2_RX_CLK

EC2_RX_DV

EC2_TXD[0:3]

EC2_TX_EN

I

I

I

I

I

O

O

Used

In MII mode

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of these signals is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of these signals is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

This pin requires an external 1 kΩ pull-down resistor to prevent PHY from seeing a valid Transmit

Enable before it is actively driven.

Not Used

This pin can be programmed as a

GPIO and as an output.

This pin can be programmed as a

GPIO and as an output.

This pin can be configured as a

GPIO.

This pin can be configured as a

GPIO.

This pin can be configured as a

GPIO.

These pins may be left unconnected or configured as

GPIOs.

This pin may be left unconnected or configured as a GPIO.

5.19 Ethernet controller 3 pin termination recommendations

Table 34. Ethernet controller 3 pin termination checklist

Signal Name Not Used

EC3_GTX_CLK O

I/O type Used

In RGMII mode

The functionality of this signal is determined by the EC3 field in the reset configuration word

(RCW[EC3]).

Table continues on the next page...

This pin may be configured as a GPIO.

Completed

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Interface recommendations

Table 34. Ethernet controller 3 pin termination checklist (continued)

Signal Name

EC3_GTX_CLK125

EC3_RXD[0:3]

EC3_RX_CLK

EC3_RX_DV

EC3_TXD[0:3]

EC3_TX_EN

EC3_RX_ER

EC3_TX_CLK

EC1_TX_ER

EC2_TX_ER

I

I

I

I

I

I

O

O

O

O

I/O type Used

The functionality of this signal is determined by the EC3 field in the reset configuration word

(RCW[EC3]).

The functionality of these signals is determined by the

EC3 field in the reset configuration word

(RCW[EC3]).

The functionality of this signal is determined by the EC3 field in the reset configuration word

(RCW[EC3]).

The functionality of this signal is determined by the EC3 field in the reset configuration word

(RCW[EC3]).

The functionality of these signals is determined by the

EC3 field in the reset configuration word

(RCW[EC3]).

The functionality of this signal is determined by the EC3 field in the reset configuration word

(RCW[EC3]).

This pin requires an external 1kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven.

In RMII mode

The functionality of this signal is determined by the

RCW[EC3] field in the reset configuration word.

The functionality of this signal is determined by the

RCW[EC3] field in the reset configuration word.

MII 1/2 optional signals

The functionality of this signal is determined by the

RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the

RCW[EC2] field in the reset configuration word.

Not Used

This pin may be configured as a GPIO.

These pins may be configured as GPIOs and outputs.

This pin may be configured as a GPIO.

This pin may be configured as a GPIO.

These pins may be left unconnected or configured as GPIOs.

This pin may be left unconnected or configured as a GPIO.

This pin can be programmed as a GPIO and as an output.

This pin can be programmed as a GPIO and as an output.

This pin can be programmed as a GPIO and as an output.

This pin can be programmed as a GPIO and as an output.

Table continues on the next page...

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EC1_COL

EC2_COL

EC1_CRS

EC2_CRS

Interface recommendations

Table 34. Ethernet controller 3 pin termination checklist (continued)

Signal Name

TSEC_1588_ALARM_OUT[1:2]

TSEC_1588_CLK_IN

TSEC_1588_CLK_OUT

TSEC_1588_PULSE_OUT[1:2]

TSEC_1588_TRIG_IN[1:2] I

I

I

I

I

I

O

O

O

I/O type Used

The functionality of this signal is determined by the

RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the

RCW[EC2] field in the reset configuration word.

The functionality of this signal is determined by the

RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the

RCW[EC2] field in the reset configuration word.

IEEE 1588

The functionality of these signals is determined by the

EC3 field in the reset configuration word

(RCW[EC3]).

Connect to an external highprecision timer reference input.

The functionality of this signal is determined by the EC3 field in the reset configuration word

(RCW[EC3]).

The functionality of this signal is determined by the EC3 field in the reset configuration word

(RCW[EC3]).

The functionality of these signals is determined by the

EC3 field in the reset configuration word

(RCW[EC3]).

The functionality of these signals is determined by the

EC3 field in the reset configuration word

(RCW[EC3]).

Not Used

This pin can be programmed as a GPIO and as an output.

This pin can be programmed as a GPIO and as an output.

This pin can be programmed as a GPIO and as an output.

This pin can be programmed as a GPIO and as an output.

These pins can be programmed as GPIOs and as outputs.

This pin can be programmed as a GPIO and as an output.

This pin can be programmed as a GPIO and as an output.

These pins can be programmed as GPIOs and as outputs.

These pins can be programmed as GPIOs and as outputs.

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Interface recommendations

5.20 TDM pin termination recommendations

Table 35. TDM pin termination checklist

Signal Name I/O type Used Not Used

CLK09

CLK10

CLK11

CLK12

TDMA_RQ

TDMA_RSYNC

TDMA_RXD

TDMA_TSYNC

TDMA_TXD

TDMB_RQ

TDMB_RSYNC

TDMB_RXD

TDMB_TSYNC

TDMB_TXD

I

I

I

I

I

I

I

I

I

I

O

O

O

O

The functionality of this signal is determined by the

SCFG[QEIOCLKCR] register fields.

CLK12 is connected to CLK8 internally.

The functionality of this signal is determined by the RCW[QE_TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE_TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE_TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE_TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE_TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE_TDMB] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE_TDMB] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE_TDMB] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE_TDMB] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE_TDMB] field in the reset configuration word.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

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Interface recommendations

5.21 2D-ACE pin termination recommendations

Table 36. 2D-ACE pin termination checklist

Signal Name

2D-ACE_D[00:11]

2D-ACE_CLK_OUT

2D-ACE_DE

2D-ACE_HSYNC

2D-ACE_VSYNC

O

I/O type

O

O

O

O

Used

The functionality of

2D_ACE_D[00:04] and

2D_ACE_D[10:11] is determined by the

RCW[QE_TDMA] field in the reset configuration word.

The functionality of

2D_ACE_D[05:09] is determined by the

RCW[QE_TDMB] field in the reset configuration word.

The functionality of this signal is determined by the

RCW[QE_TDMB] field in the reset configuration word.

The functionality of this signal is determined by the

RCW[QE_TDMB] field in the reset configuration word.

The functionality of this signal is determined by the

RCW[UART_EXT] and

RCW[UART_BASE] fields in the reset configuration word.

The functionality of this signal is determined by the

RCW[UART_EXT] and

RCW[UART_BASE] fields in the reset configuration word.

Not Used

2D_ACE_D[00:04] can be configured as a GPIO or may be left unconnected.

This pin can be configured as a GPIO or may be left unconnected.

This pin can be configured as a GPIO or may be left unconnected.

This pin can be configured as a GPIO or may be left unconnected.

This pin can be configured as a GPIO or may be left unconnected.

Completed

5.22 QSPI pin termination recommendations

Table 37. QSPI pin termination checklist

Signal Name

QSPI_CK_A O

I/O type Used

The functionality of this signal is determined by the

RCW[IFC_GRP_F_EXT] and

[IFC_A_22_24] fields in the reset configuration word.

Table continues on the next page...

Not Used

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Completed

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Interface recommendations

Table 37. QSPI pin termination checklist (continued)

Signal Name

QSPI_CK_B

QSPI_CS_A[0:1]

QSPI_CS_B[0:1]

QSPI_DIO_A[0:3]

QSPI_DIO_B[0:3]

QSPI_DQS_A

QSPI_DQS_B

O

I/O type

O

O

I/O

I/O

I/O

I/O

Used

The functionality of this signal is determined by the

RCW[IFC_GRP_F_EXT] and

[IFC_A_22_24] fields in the reset configuration word.

This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. The internal pull-up resistor value for applicable IFC pins is

~33 kΩ. This pull-up is designed such that it can be overpowered by an external 4.7 kΩ resistor.

However, if the signal is intended to be high after reset, and if there is any device on the net that might pull down the value of the net at reset, a pull-up or active driver is needed.

The functionality of these signals is determined by the

RCW[IFC_GRP_F_EXT] and

[IFC_A_22_24] fields in the reset configuration word.

The functionality of these signals is determined by the

RCW[IFC_GRP_F_EXT] and

[IFC_A_22_24] fields in the reset configuration word.

The functionality of these signals is determined by the

RCW[IFC_GRP_F_EXT] and

[IFC_A_22_24] fields in the reset configuration word.

The functionality of these signals is determined by the

RCW[IFC_GRP_F_EXT] and

[IFC_A_22_24] fields in the reset configuration word.

The functionality of these signals is determined by the

RCW[IFC_GRP_F_EXT] and

[IFC_A_22_24] fields in the reset configuration word.

The functionality of these signals is determined by the

RCW[IFC_GRP_F_EXT] and

[IFC_A_22_24] fields in the reset configuration word.

Not Used Completed

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Interface recommendations

5.23 General Purpose Input/Output pin termination recommendations

NOTE

When configuring GPIO, the entire bank of GPIO must be selected in RCW for even a subset to be used as GPIO. For example, if GPIO3 is used, the following RW bits must be selected:

• RCW bit 416-418 EC1 = 001 GPIO3[2:14]

• RCW bit 419-421 EC2 = 001 GPIO3[15:27]

• RCW bit 422-424 EC3 = 001 GPIO3[28:31]

• RCW bit 425-426 MDC_MDIO = 01 GPIO3[0:1]

Table 38. General Purpose Input/Output pin termination checklist

Signal Name I/O type Used Not Used

GPIO1_13

GPIO1_14

GPIO1_[15:22]

GPIO1_[23:25]

GPIO2_[04:09]

GPIO2_[10:12]

GPIO2_[13:15]

GPIO2_24

GPIO2_[25:27]

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

The functionality of this signal is determined by the RCW[ASLEEP] field in the reset configuration word.

The functionality of this signal is determined by the RCW[RCT] field in the reset configuration word.

The functionality of these signals is determined by the RCW[RCT] field in the reset configuration word.

The functionality of these signals is determined by the RCW[IRQ_EXT] and RCW[IRQ_BASE] fields in the reset configuration word.

The functionality of these signals is determined by the

RCW[SDHC_EXT] and

RCW[SDHC_BASE] fields in the reset configuration word.

For all GPIOx pins: When programmed as outputs, no termination is required.

For all GPIOx pins: When programmed as outputs, no termination is required.

The functionality of these signals is determined by the

RCW[IFC_GRP_E1_BASE] field in the reset configuration word.

The functionality of these signals is determined by the

RCW[IFC_GRP_D_BASE] fields in the reset configuration word.

The functionality of this signal is determined by the RCW[EVT9_B] and RCW[SDHC_BASE] fields in the reset configuration word.

For all GPIOx pins: When programmed as outputs, no termination is required.

The functionality of these signals is determined by the

RCW[IFC_GRP_A_BASE] field in the reset configuration word.

Table continues on the next page...

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Interface recommendations

Table 38. General Purpose Input/Output pin termination checklist (continued)

Signal Name I/O type Used Not Used Complete d

GPIO3_[00:01]

GPIO3_[02:14]

GPIO3_[15:27]

GPIO3_[28:31]

GPIO4_[00:08]

GPIO4_[09:13]

GPIO4_[14:18]

GPIO4_[19:22]

GPIO4_[23:26]

GPIO4_[27:28]

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

The functionality of these signals is determined by the RCW[MDC/

MDIO] field in the reset configuration word.

For all GPIOx pins: When programmed as outputs, no termination is required.

The functionality of these signals is determined by the RCW[EC1] field in the reset configuration word.

The functionality of these signals is determined by the RCW[EC2] field in the reset configuration word.

The functionality of these signals is determined by the RCW[EC3] field in the reset configuration word.

The functionality of these signals is determined by the RCW[EC3] field in the reset configuration word.

The functionality of these signals is determined by the RCW[QE/TDMA] field in the reset configuration word.

The functionality of these signals is determined by the RCW[QE/TDMB] field in the reset configuration word.

The functionality of BRGO[2:3] is determined by the QE_TDMA and

QE_TDMB fields in the reset configuration word. See register

SCFG_QEIOCLKCR in the

"Supplemental Configuration Unit" chapter of QorIQ LS1021A

Reference Manual.

The functionality of these signals is determined by the RCW[SDHC] field in the reset configuration word.

The functionality of these signals is determined by the RCW[IIC_EXT] and RCW[IIC_BASE] fields in the reset configuration word.

For all GPIOx pins: When programmed as outputs, no termination is required.

For all GPIOx pins: When programmed as outputs, no termination is required.

5.24 FlexTimer recommendations

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Interface recommendations

5.24.1 FTM1 pin termination recommendations

Table 39. FTM1 pin termination checklist

Signal Name

FTM1_CH[0:7]

FTM1_EXTCLK

FTM1_FAULT

FTM1_QD_PHA

FTM1_QD_PHB I

I

I

I

I/O type

I/O

Used

The functionality of these signals is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

Not Used

Program as GPIOs and as outputs.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Completed

5.24.2 FTM2 pin termination recommendations

Table 40. FTM2 pin termination checklist

Signal Name

FTM2_CH[0:7]

FTM2_EXTCLK

FTM2_FAULT

FTM2_QD_PHA

FTM2_QD_PHB I

I

I

I

I/O type

I/O

Used

The functionality of these signals is determined by the RCW[EC2] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC2] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC2] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC2] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC2] field in the reset configuration word.

Not Used

Program as GPIOs and as outputs.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

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5.24.3 FTM3 pin termination recommendations

Table 41. FTM3 pin termination checklist

Signal Name

FTM3_CH[0:7]

FTM3_EXTCLK

FTM3_FAULT

FTM3_QD_PHA

FTM3_QD_PHB I

I

I

I

I/O type

I/O

Used

The functionality of these signals is determined by the RCW[EC3] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC3] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC3] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC3] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC3] field in the reset configuration word.

Not Used

Program as GPIOs and as outputs.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Completed

5.24.4 FTM4 pin termination recommendations

Table 42. FTM4 pin termination checklist

Signal Name

FTM4_CH[0:7]

FTM4_EXTCLK

FTM4_FAULT

FTM4_QD_PHA

FTM4_QD_PHB I

I

I

I

IO

IO type Used

The functionality of these signals is determined by the RCW[QE/

TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMA] field in the reset configuration word.

Not Used

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

If unused, this pin can be programmed as a GPIO and as an output.

If unused, this pin can be programmed as a GPIO and as an output.

Completed

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Interface recommendations

5.24.5 FTM5 pin termination recommendations

Table 43. FTM5 pin termination checklist

Signal Name

FTM5_CH[0:1]

FTM5_EXTCLK I

I/O type

I/O

Used

The functionality of these signals is determined by the

RCW[IFC_GRP_A_EXT] field in the reset configuration word.

The functionality of this signal is determined by the

RCW[IFC_GRP_A_EXT] field in the reset configuration word.

Not Used

Pull low through a 2-10 kΩ resistor to GND.

Pull low through a 2-10 kΩ resistor to GND.

Completed

5.24.6 FTM6 pin termination recommendations

Table 44. FTM6 pin termination checklist

Signal Name

FTM6_CH[0:1]

FTM6_EXTCLK I

I/O type

I/O

Used

The functionality of these signals is determined by the

RCW[IFC_GRP_D_EXT] field in the reset configuration word.

The functionality of this signal is determined by the

RCW[IFC_GRP_D_EXT] field in the reset configuration word.

Not Used

Pull low through a 2-10 kΩ resistor to GND.

Pull low through a 2-10 kΩ resistor to GND.

Completed

5.24.7 FTM7 pin termination recommendations

Table 45. FTM7 pin termination checklist

Signal Name

FTM7_CH[0:1]

FTM7_EXTCLK I

I/O type

I/O

Used

The functionality of these signals is determined by the

RCW[IFC_GRP_E1_EXT] field in the reset configuration word.

The functionality of this signal is determined by the

RCW[IFC_GRP_E1_EXT] field in the reset configuration word.

Not Used

Pull low through a 2-10 kΩ resistor to GND.

Pull low through a 2-10 kΩ resistor to GND.

Completed

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5.24.8 FTM8 pin termination recommendations

Table 46. FTM8 pin termination checklist

Signal Name

FTM8_CH[0:1]

I/O type

I/O

Used

The functionality of these signals is determined by the RCW[QE/

TDMB] field in the reset configuration word.

Not Used

Pull low through a 2-10 kΩ resistor to GND.

Completed

5.25 Synchronous Audio Interface (SAI)/Integrated Interchip

Sound (I

2

S) recommendations

5.25.1 SAI1 pin termination recommendations

Table 47. SAI1 pin termination checklist

Signal Name

EXT_AUDIO_MCLK2

SAI1_RX_BCLK

SAI1_RX_DATA

SAI1_RX_SYNC

SAI1_TX_BCLK

SAI1_TX_DATA

SAI1_TX_SYNC

I

I

I/O

I/O

I/O

O

I/O type

I/O

Used

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

Not Used

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Completed

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Interface recommendations

5.25.2 SAI2 pin termination recommendations

Table 48. SAI2 pin termination checklist

Signal Name

SAI2_RX_BCLK

SAI2_RX_DATA

SAI2_RX_SYNC

SAI2_TX_BCLK

SAI2_TX_DATA

SAI2_TX_SYNC

I

I/O type

I/O

I/O

I/O

O

I/O

Used

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

The functionality of this signal is determined by the RCW[EC1] field in the reset configuration word.

Not Used

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Completed

5.25.3 SAI3 pin termination recommendations

Table 49. SAI3 pin termination checklist

Signal Name

EXT_AUDIO_MCLK1

SAI3_RX_BCLK

SAI3_RX_DATA

SAI3_RX_SYNC

SAI3_TX_BCLK

I

I

I/O type

I/O

I/O

I/O

Used

The functionality of this signal is determined by the RCW[QE/

TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMA] field in the reset configuration word.

Program as a GPIO and as an output.

Not Used

Pull low through a 2-10 kΩ resistor to GND.

Program as a GPIO and as an output.

Pull low through a 2-10 kΩ resistor to GND.

Program as a GPIO and as an output.

Table continues on the next page...

Completed

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Table 49. SAI3 pin termination checklist (continued)

Signal Name

SAI3_TX_DATA

SAI3_TX_SYNC

O

I/O type

I/O

Used

The functionality of this signal is determined by the RCW[QE/

TDMA] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMA] field in the reset configuration word.

Not Used

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Completed

5.25.4 SAI4 pin termination recommendations

Table 50. SAI4 pin termination checklist

Signal Name

SAI4_RX_BCLK

SAI4_RX_DATA

SAI4_RX_SYNC

SAI4_TX_BCLK

SAI4_TX_DATA

SAI4_TX_SYNC

I

I/O type

I/O

I/O

I/O

O

I/O

Used

The functionality of this signal is determined by the RCW[QE/

TDMB] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMB] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMB] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMB] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMB] field in the reset configuration word.

The functionality of this signal is determined by the RCW[QE/

TDMB] field in the reset configuration word.

Not Used

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Pull low through a 2-10 kΩ resistor to GND.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Completed

5.26 FlexCAN recommendations

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Interface recommendations

5.26.1 CAN1 pin termination recommendations

Table 51. CAN1 pin termination checklist

Signal Name

CAN1_RX

CAN1_TX

I

O

I/O type Used

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

Not Used

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Completed

5.26.2 CAN2 pin termination recommendations

Table 52. CAN2 pin termination checklist

Signal Name

CAN2_RX

CAN2_TX

I

O

I/O type Used

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

Not Used

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Completed

5.26.3 CAN3 pin termination recommendations

Table 53. CAN3 pin termination checklist

Signal Name

CAN3_RX

CAN3_TX

I

O

I/O type Used

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

Not Used

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Completed

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5.26.4 CAN4 pin termination recommendations

Table 54. CAN4 pin termination checklist

Signal Name

CAN4_RX

CAN4_TX

I

O

I/O type Used

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC2 field in the reset configuration word

(RCW[EC2]).

Not Used

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Completed

5.27 USB host port 2 pin termination recommendations

Table 55. USB host port 2 pin termination checklist

Signal Name

USB2_CLK

USB2_D[0:7]

USB2_DIR

USB2_DRVVBUS

USB2_NXT

USB2_PWRFAULT

USB2_STP

I

I

I

I/O type

I/O

I

O

O

Used

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC2]).

The functionality of these signals is determined by the EC1 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC3]).

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC2]).

The functionality of this signal is determined by the EC1 field in the reset configuration word

(RCW[EC2]).

Not Used Completed

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Interface recommendations

5.28 BRGO pin termination recommendations

Table 56. BRGO pin termination checklist

Signal Name

BRGO[1:4] O

I/O type Used

The functionality of BRGO[2:3] is determined by the QE_TDMA field in the reset configuration word.

See register SCFG_QEIOCLKCR in the "Supplemental Configuration

Unit" chapter of the QorIQ

LS1021A Reference Manual for more information.

The functionality of BRGO[1] and

BRGO[4] is determined by the

QE_TDMB field in the reset configuration word. See register

SCFG_QEIOCLKCR in the

"Supplemental Configuration Unit" chapter of the QorIQ LS1021A

Reference Manual for more information.

Not Used

Program as GPIOs and as outputs.

Completed

5.29 Sony/Philips Digital Interconnect Formal (S/PDIF) pin termination recommendations

Table 57. Sony/Philips Digital Interconnect Formal (S/PDIF) pin termination checklist

Signal Name

SPDIF_EXTCLK I

I/O type Completed

SPDIF_IN

SPDIF_OUT

SPDIF_PLOCK

SPDIF_SRCLK

I

O

O

O

Used

The functionality of

SPDIF_EXTCLK is determined by the RCW[QE/TDMB] field in the reset configuration word.

The functionality of SPDIF_IN is determined by the RCW[QE/

TDMB] field in the reset configuration word.

The functionality of SPDIF_OUT is determined by the RCW[QE/

TDMB] field in the reset configuration word.

The functionality of

SPDIF_PLOCK is determined by the RCW[QE/TDMB] field in the reset configuration word.

The functionality of

SPDIF_SRCLK is determined by the RCW[QE/TDMB] field in the reset configuration word.

Not Used

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

Program as a GPIO and as an output.

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Interface recommendations

5.30 SPI interface pin termination recommendations

Table 58. SPI interface pin termination checklist

Signal Name

SPI1_PCS0

SPI1_PCS[1:5]

SPI1_SCK

SPI1_SIN

SPI1_SOUT

I

I/O type

I/O

O

I/O

O

Used

The functionality of SPI1_PCS0 is determined by the

RCW[IFC_GRP_E1_EXT] and

[IFC_GRP_E1_BASE] fields in the reset configuration word.

The functionality of these signals is determined by the

RCW[IFC_GRP_G_EXT] field in the reset configuration word.

These pins are reset configuration pins. They have a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. The internal pull-up resistor value for applicable

IFC pins is ~33 kΩ. This pull-up is designed such that it can be overpowered by an external 4.7

kΩ resistor. However, if the signals are intended to be high after reset, and if there is any device on the net that might pull down the value of the net at reset, a pull-up or active driver is needed.

Not Used

Can be programmed as GPIOs and as an output.

The pins can be programmed as

GPIOs or may be left unconnected.

The functionality of SPI1_SCK is determined by the

RCW[IFC_GRP_E1_EXT] and

[IFC_GRP_E1_BASE] fields in the reset configuration word.

The functionality of SPI1_SIN is determined by the

RCW[IFC_GRP_E1_EXT] and

[IFC_GRP_E1_BASE] fields in the reset configuration word.

The functionality of SPI1_SOUT is determined by the

RCW[IFC_GRP_G_EXT] field in the reset configuration word.

Can be programmed as GPIOs and as an output.

Can be programmed as GPIOs and as an output.

Can be programmed as GPIOs or may be left unconnected.

This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. The internal pull-up resistor value for applicable IFC pins is

~33 kΩ. This pull-up is designed such that it can be overpowered by an external 4.7 kΩ resistor.

However, if the signal is intended

Table continues on the next page...

66

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Signal Name

SPI2_PCS0

SPI2_PCS[1:5]

SPI2_SCK

SPI2_SIN

SPI2_SOUT

Interface recommendations

Table 58. SPI interface pin termination checklist (continued)

I

I/O

O

O

I/O type

I/O

Used

to be high after reset, and if there is any device on the net that might pull down the value of the net at reset, a pull-up or active driver is needed.

The functionality of SPI2_PCS0 is determined by the UART_BASE and UART_EXT fields in the reset configuration word

(RCW[UART_BASE],

RCW[UART_EXT]).

The functionality of SPI2_PCS[1:2] is determined by the UART_BASE and UART_EXT fields in the reset configuration word

(RCW[UART_BASE],

RCW[UART_EXT]).

The functionality of SPI2_PCS[3:4] is determined by the IIC_BASE and IIC_EXT fields in the reset configuration word

(RCW[IIC_BASE],

RCW[IIC_EXT]).

Not Used

Can be programmed as a GPIO and as an output.

These pins can be programmed as

GPIOs or may be left unconnected.

The functionlity of SPI2_PCS[5] is determined by the IRQ_BASE and

IRQ_EXT fields in the reset configuration word

(RCW[IRQ_BASE],

RCW[IRQ_EXT]).

The functionality of SPI2_SCK is determined by the UART_BASE and UART_EXT fields in the reset configuration word

(RCW[UART_BASE],

RCW[UART_EXT]).

The functionality of SPI2_SIN is determined by the UART_BASE and UART_EXT fields in the reset configuration word

(RCW[UART_BASE],

RCW[UART_EXT]).

The functionality of SPI2_SOUT is determined by the UART_BASE and UART_EXT fields in the reset configuration word

(RCW[UART_BASE],

RCW[UART_EXT]).

Can be programmed as a GPIO and as an output.

Can be programmed as a GPIO or as an output.

Can be programmed as a GPIO or may be left unconnected.

Completed

5.31 JTAG recommendations

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Interface recommendations

5.31.1 JTAG pin termination recommendations

Table 59. JTAG pin termination checklist

Signal Name I/O type

TCK

TDI

TDO

TMS

TRST_B I

I

I

I

O

Used Not Used

Connect to pin 4 of the ARM

®

Cortex

®

10-pin header. This pin requires a 2-10 kΩ resistor to OV

DD

.

Connect to pin 8 of the ARM

Cortex 10-pin header. This pin has a weak (~20 kΩ) internal pull-up P-

FET that is always enabled.

May be left unconnected.

May be left unconnected.

Connect to pin 6 of the ARM

Cortex 10-pin header. This output is actively driven during reset rather than being tri-stated during reset.

Connect to pin 2 of the ARM

Cortex 10-pin header. This pin has a weak (~20 kΩ) internal pull-up P-

FET that is always enabled.

May be left unconnected.

This pin has a weak (~20 kΩ) internal pull-up P-FET that is always enabled.

Tie TRST_B to PORESET_B through a 0 kΩ resistor.

Connect as shown in Figure 31

.

Completed

5.31.2 System clocking

This section describes the PLL configuration of the chip.

5.31.2.1 Clock ranges

This table provides the clocking specifications for the processor core, platform, memory, and integrated flash controller.

Table 60. Processor, platform, and memory clocking specifications

Characteristic Notes

Core cluster group PLL frequency

Platform clock frequency

Memory bus clock frequency (DDR3L)

Memory bus clock frequency (DDR4)

IFC clock frequency

250

500

667

Maximum processor core frequency

600 MHz

7

800 MHz 1000 MHz

Min

600

Max

600

300

800

800

75

Min

600

250

500

667

800

300

800

800

75

Max

Min

800

250

500

667

Max

1000

Unit

MHz

300 MHz

800 MHz

800 MHz

75 MHz

Table continues on the next page...

1

1

1, 2, 3, 6

1, 2, 3

4

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Interface recommendations

Table 60. Processor, platform, and memory clocking specifications (continued)

Characteristic Maximum processor core frequency

600 MHz

7

800 MHz 1000 MHz

Unit Notes

Min Max Min Max Min Max

1. Caution: The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting

SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum operating frequencies

2. The memory bus clock speed is half the DDR3L/DDR4 data rate.

3. The memory bus clock speed is dictated by its own PLL.

4. The integrated flash controller (IFC) clock speed on IFC_CLK[0:1] is determined by the IFC module input clock (platform clock/1) divided by the IFC ratio programmed in IFC_CCR[CLKDIV]. See the chip reference manual for more information.

5. "Single Oscillator Source" reference clock mode supports differential reference clock pair frequency of 100 MHz.

6. LS1022A only supports DDR3L at 500 MHz bus clock frequency.

7. LS1022A only supports core frequency at 600 MHz.

5.31.2.1.1 DDR clock ranges

The DDR memory controller can run only in asynchronous mode, where the memory bus is clocked with the clock provided on the DDRCLK input pin, which has its own dedicated PLL.

This table provides the clocking specifications for the memory bus.

Table 61. Memory bus clocking specifications

Characteristic

Memory bus clock frequency DDR3L

DDR4

Notes:

500

667

Min

800

800

Max

MHz

Unit Notes

1, 2, 3, 4

1. Caution: The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting

SYSCLK frequency, core frequency, and platform frequency do not exceed their respective maximum or minimum operating frequencies. For details on ratio settings, see

Platform to SYSCLK PLL ratio ,

Core cluster to SYSCLK PLL ratio , and DDR controller PLL ratios

.

2. The memory bus clock refers to the chip's memory controllers' D1_MCK[0:1] and D1_MCK[0:1]_B output clocks, running at half of the DDR data rate.

3. The memory bus clock speed is dictated by its own PLL. See DDR controller PLL ratios

.

4. Minimum frequency supported by DDR4 is 1333 MT/s.

5.31.2.2 Platform to SYSCLK PLL ratio

Table 62 lists the allowed platform clock to SYSCLK ratios.

Because the DDR operates asynchronously, the memory bus clock frequency is decoupled from the platform bus frequency.

For all valid platform frequencies supported on this chip, set the RCW configuration field SYS_PLL_CFG = 0b00.

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0_0010

0_0011

0_0100

All others

Table 62. Platform to SYSCLK PLL ratios

Binary value of SYS_PLL_RAT Platform:SYSCLK Ratio

2:1

3:1

4:1

Reserved

5.31.2.3 Core cluster to SYSCLK PLL ratio

The clock ratio between SYSCLK and each of the core cluster PLLs is determined by the binary value of the RCW configuration field CGA_PLL1_RAT. This table describes the supported ratios. For all valid core cluster frequencies supported on this chip, set the RCW configuration field CGA_PLL1_CFG = 0b00.

This table lists the supported asynchronous core cluster to SYSCLK ratios.

Table 63. Core cluster PLL to SYSCLK ratios

Binary value of CGA_PLL1_RAT

00_0101

. . .

10_1000

All others

5:1

. . .

40:1

Reserved

Core cluster:SYSCLK Ratio

00_0110

00_0111

00_1000

00_1001

00_1010

00_1011

00_1100

00_1101

00_1111

01_0000

5.31.2.4 DDR controller PLL ratios

The DDR memory controller operates asynchronous to the platform.

In asynchronous DDR mode, the DDR data rate to DDRCLK ratios supported are listed in

Table 64 . This ratio is determined

by the binary value of the RCW configuration field MEM_PLL_RAT (bits 10-15).

The RCW configuration field MEM_PLL_CFG (bits 8-9) must be set to MEM_PLL_CFG = 0b00 for all valid DDR PLL reference clock frequencies supported on this chip.

Table 64. DDR clock ratio

Binary value of MEM_PLL_RAT DDR data rate:DDRCLK ratio

6:1

7:1

8:1

9:1

10:1

11:1

12:1

13:1

15:1

16:1

Table continues on the next page...

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70 Freescale Semiconductor, Inc.

01_0001

01_0010

01_0011

01_0100

01_0101

01_0110

01_0111

01_1000

Interface recommendations

Table 64. DDR clock ratio (continued)

Binary value of MEM_PLL_RAT DDR data rate:DDRCLK ratio

17:1

18:1

19:1

20:1

21:1

22:1

23:1

24:1

5.31.2.5 SerDes PLL ratio

The clock ratio between each of the two SerDes PLLs and their respective externally supplied SD1_REF_CLKn_P/

SD1_REF_CLKn_N inputs is determined by a set of RCW configuration fields (SRDS_PRTCL_S1,

SRDS_PLL_REF_CLK_SEL_Sn, and SRDS_DIV_*_Sn), as shown in this table.

Table 65. Valid SerDes RCW encodings and reference clocks

SerDes protocol (given lane)

Valid reference clock frequency

100 MHz

125 MHz

Legal setting for

SRDS_PRTCL_S1

Valid setting as determined by

SRDS_PLL_RE

F_CLK_SEL_Sn

High-speed serial interfaces

Any PCIe 0b0: 100 MHz

0b1: 125 MHz

Valid setting as determined by

SRDS_DIV_*_Sn

2b10: 2.5 G

Notes

PCI Express 2.5 Gbps

(doesn't negotiate upwards)

PCI Express 5 Gbps

(can negotiate up to 5 Gbps)

SATA (1.5, 3, 6 Gbps)

100 MHz

125 MHz

100 MHz

125 MHz

Any PCIe

SATA

0b0: 100 MHz

0b1: 125 MHz

0b0: 100 MHz

0b1: 125 MHz

2b01: 5.0 G

Don't care

1

1

1

1

2

SGMII (1.25 Gbps) 100 MHz

125 MHz

Networking interfaces

SGMII @ 1.25 Gbps

1000Base-KX @ 1.25

Gbps

0b0: 100 MHz

0b1: 125 MHz

Don't care 1

1

Notes:

1. A spread-spectrum reference clock is permitted for PCI Express. However, if any other high-speed interface, such as

SATA, SGMII, or 1000Base-KX, is used concurrently on the same SerDes PLL, spread-spectrum clocking is not permitted.

2. SerDes lanes configured as SATA that initially operate at 1.5 Gbps, 3.0 Gbps, or 6.0 Gbps operation may later be enabled through the SATA IP itself. It is possible for software to set each SATA at a different rate.

5.31.2.6 eSDHC SDR mode clock select

The eSDHC SDR mode is asynchronous to the platform.

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Interface recommendations

This table describes the clocking options that may be applied to the eSDHC SDR mode. The clock selection is determined by the binary value of the RCW clocking configuration field HWA_CGA_M1_CLK_SEL.

Table 66. eSDHC SDR mode clock select

Binary value of HWA_CGA_M1_CLK_SEL

Reserved

Cluster group A PLL 1/1

Cluster group A PLL 1/2

Cluster group A PLL 1/3

Cluster group A PLL 1/4

Reserved

eSDHC SDR mode frequency

1

0b000

0b001

0b010

0b011

0b100

0b101

Note:

1. For asynchronous mode, max frequency, see table "Processor clocking specifications" in the chip reference manual.

5.31.2.7 Frequency options

This section discusses interface frequency options.

5.31.2.7.1 SYSCLK and core cluster frequency options

This table shows the expected frequency options for SYSCLK and core cluster frequencies.

Table 67. SYSCLK and core cluster frequency options

Core cluster:

SYSCLK Ratio

5:1

6:1

7:1

8:1

9:1

10:1

11:1

12:1

13:1

14:1

15:1

Notes:

640

704

768

832

896

960

64.00

667

733

800

867

933

1000

SYSCLK (MHz)

66.67

100.00

Core cluster Frequency (MHz)

1

125.00

600

700

800

900

1000

625

750

875

1000

667

800

933

133.33

1. Core cluster frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed).

2. When using single-source clocking only, 100 MHz input is available.

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Interface recommendations

5.31.2.7.2 SYSCLK and platform frequency options

This table shows the expected frequency options for SYSCLK and platform frequencies.

Table 68. SYSCLK and platform frequency options

Platform: SYSCLK

2:1

3:1

4:1

Notes:

Ratio

256

64.00

267

66.67

SYSCLK (MHz)

100.00

Platform Frequency (MHz)

1

250

300

125.00

267

133.33

1. Platform frequency values are shown rounded down to the nearest whole number (decimal place accuracy removed).

2. When using single-source clocking, only 100 MHz options are valid.

5.31.2.7.3 DDRCLK and DDR data rate frequency options

This table shows the expected frequency options for DDRCLK and DDR data rate frequencies.

Table 69. DDRCLK and DDR data rate frequency options

DDR data rate:

DDRCLK Ratio

64.00

66.67

DDRCLK (MHz)

100.00

DDR Data Rate (MT/s)

1

125.00

15:1

16:1

17:1

18:1

19:1

20:1

Notes:

7:1

8:1

9:1

10:1

11:1

12:1

13:1

14:1

1024

1088

1152

1216

1280

1000

1067

1133

1200

1267

1333

1000

1100

1200

1300

1400

1500

1600

1000

1125

1250

1375

1500

1066

1200

1333

1467

1600

1. DDR data rate values are shown rounded up to the nearest whole number (decimal place accuracy removed).

2. When using single-source clocking, only 100 MHz options are available.

3. The minimum data rate supported by DDR4 is 1333 MT/s.

133.33

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Interface recommendations

5.31.3 JTAG system-level recommendations

Table 70. JTAG system-level checklist

Item

ARM®Cortex® 10-pin header signal interface to JTAG port

Configure the group of system control pins as shown in

Figure 31 .

NOTE: These pins must be maintained at a valid deasserted state under normal operating conditions because most have asynchronous behavior and spurious assertion gives unpredictable results.

The JTAG port of these processors allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The ARM Cortex 10pin header connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The ARM Cortex 10-pin header interface requires the ability to independently assert PORESET_B in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the nRESET signals must be merged into these signals with logic.

Boundary-scan testing

Ensure that TRST_B is asserted during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal chip operation. The TEST_SEL_B pin must be pulled to OV

DD resistor.

through a 100 Ω to 1 kΩ

NOTE: For boundary scan, the TEST_SEL_B and PORESET_B pins must be pulled to ground (GND), and

SCAN_MODE_B and EVT2_B must be pulled up.

Follow the arrangement shown in

Figure 31 to allow the ARM Cortex 10-pin header to assert PORESET_B

independently while ensuring that the target can drive PORESET_B as well.

The ARM® Cortex® 10-pin interface has a standard header, shown in the following figure. The connector typically has pin 7 removed as a connector key. The signal placement recommended in this figure is common to all known emulators.

Completed

V

DD

GND

GND

KEY

GNDDetect

1

3

5

KEY

No pin

9

6

8

2

4

10

TMS

TCK

TDO

TDI nRESET

Figure 30. ARM Cortex 10-pin header

NOTE: The ARM Cortex 10-pin header adds many benefits such as breakpoints, watch points, register and memory examination/modification, and other standard debugger features. An inexpensive option is to leave the ARM Cortex 10-pin header unpopulated until needed.

Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure

31

. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions, as most have asynchronous behavior and spurious assertion gives unpredictable results.

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Thermal recommendations

1 kΩ

OV

DD

1

3

5

KEY

No pin

9

2

4

6

8

10

ARM Cortex 10-pin physical pinout

From target board sources

(if any)

HRESET_B

PORESET_B

10 nRESET

A

2

B

10 kΩ

OV

DD

10 kΩ

Other TRST_B source

(for example, boundary scan)

2

6

1

V

DD

TMS

TDO

10 Ω

8

TDI

4

TCK

10 kΩ

10 kΩ

HRESET_B

PORESET_B

TRST_B

TMS

TDO

TDI

TCK

9

5

3

GNDDetect

1

GND

GND

10 kΩ

Note:

1. GNDDetect is an optional board feature. Check with 3 rd

-party tool vendor.

2. This switch is included as a precaution for BSDL testing. The switch should be open (in position B) during BSDL testing to avoid accidentally asserting the TRST_B line. For normal device operation or debug testing, ensure this switch is closed (in position A).

Figure 31. JTAG interface connection

6 Thermal recommendations

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Thermal recommendations

6.1 Recommended thermal model

Information about Flotherm models of the package or thermal data not available in this document can be obtained from your local Freescale sales office.

6.2 Thermal system-level recommendations

Proper thermal control design is primarily dependent on the system-level design — the heat sink, airflow, and thermal interface material.

Table 71. Thermal system-level checklist

Completed Item

Use the recommended thermal model. Information about Flotherm models of the package or thermal data not available in this document can be obtained from your local Freescale sales office.

Use this recommended board attachment method to the heat sink:

1

The processor heat sink must be connected to GND at one point for EMC performance.

GND here specifies processor ground.

FC-PBGA package (no lid)

Heat sink

Heat sink clip

Adhesive or thermal interface material

Die

Printed circuit-board

Figure 32. Cross-secitonal view of FC PBGA with no lid

Ensure the heat sink is attached to the printed-circuit board with the spring force centered over the package.

2

Ensure the spring force does not exceed 15 pounds force (65 Newtons).

A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance.

3

Ensure the method of mounting heat sinks on the package is by means of a spring clip attachment to the printed-circuit board.

A thermal simulation is required to determine the performance in the application.

4

Notes:

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Thermal recommendations

Table 71. Thermal system-level checklist

Item Completed

1. The system board designer can choose among several types of commercially available heat sinks to determine the appropriate one to place on the device. Ultimately, the final selection of an appropriate heat sink depends on factors such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.

2. The performance of the thermal interface materials improves with increased contact pressure; the thermal interface vendor generally provides a performance characteristic to guide improved performance.

3. The system board designer can choose among several types of commercially available thermal interface materials.

4. A Flotherm model of the part is available.

6.3 Internal package conduction resistance

For the package, the intrinsic internal conduction thermal resistance paths are as follows:

• The die junction-to-case thermal resistance

• The die junction-to-board thermal resistance

This figure depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.

External resistance Radiation Convection

Heat sink

Internal resistance

Thermal interface material

Die/Package

Die junction

Package/Solder balls

Printed-circuit board

External resistance

Radiation Convection

(Note the internal versus external package resistance)

Figure 33. Package with heat sink mounted to a printed-circuit board

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Revision history

The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is conducted through the silicon and through the heat sink attach material (or thermal interface material), and finally to the heat sink. The junctionto-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms.

7 Revision history

This table summarizes changes to this document.

Table 72. Revision history

1

Revision Date

11/2015

0 10/2015

Change

In Table 60 and

Table 61

, updated the DDR3L minimum frequency from 600 MHz to 500 MHz.

In Table 69 , removed select frequencies for ratios 7:1 through 15:1.

Initial release

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How to Reach Us:

Home Page:

freescale.com

Web Support:

freescale.com/support

Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document.

Freescale reserves the right to make changes without further notice to any products herein.

Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.

“Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions .

Freescale, the Freescale logo, CodeWarrior, and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Layerscape and QUICC Engine are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. ARM, ARM Powered, Cortex, and TrustZone are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. NEON is a trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved.

© 2014-2015 Freescale Semiconductor, Inc.

Document Number AN4878

Revision 1, 11/2015

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