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TB-FMCH-DP3 Hardware User
’s Manual
TB-FMCH-DP3
Hardware User
’s Manual
Rev.1.00
Rev.1.00
1
TB-FMCH-DP3 Hardware User
’s Manual
Revision history
Revision Date Description
Rev.1.00
10/29/2015 Initial Release
Publisher
Ueda
Rev.1.00
2
TB-FMCH-DP3 Hardware User
’s Manual
Table of Contents
1.
Related Documents and Board Accessories ............................................................................... 8
2.
Overview ...................................................................................................................................... 8
3.
Feature ........................................................................................................................................ 8
4.
TB-FMCH-DP3 Function ............................................................................................................. 9
4.1.
Block Diagram ............................................................................................................................ 9
4.2.
External View of the Board ....................................................................................................... 10
4.3.
Board Specification .................................................................................................................... 11
4.4.
Power Supply ........................................................................................................................... 12
4.4.1.
IO Voltage ......................................................................................................................... 12
4.5.
Source(TX) Block ..................................................................................................................... 13
4.6.
Sink(RX) Block ......................................................................................................................... 14
4.7.
Clock circuit .............................................................................................................................. 15
4.7.1.
Operation example of PLL ................................................................................................ 16
4.8.
FMC connector for stacking ..................................................................................................... 17
4.9.
Pin Assignment of CN4 ............................................................................................................ 17
4.10.
FMC connector for expanded Board (CN3) .......................................................................... 28
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TB-FMCH-DP3 Hardware User
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List of Tables
Table 4-1 Signals of Source Circuit .................................................................................................. 13
Table 4-2 DP130 I2C Address .......................................................................................................... 13
Table 4-3 Signals of Sink Circuit ...................................................................................................... 14
Table 4-4 DP159 I2C Address .......................................................................................................... 14
Table 4-5 signals of PLL circuit......................................................................................................... 15
Table 4-6 PLL Resister settings (Step3) ........................................................................................... 16
Table 4-7 CN4 Pin assign (To carrier board) .................................................................................... 18
Table 4-8 CN3 Pin assign (For expanded Board) ............................................................................ 29
List of figures
Figure 3-1 High-pin Count Pin assignment ........................................................................................ 8
Figure 4-1 TB-FMCH-DP3 Block Diagram ......................................................................................... 9
Figure 4-2 Top view .......................................................................................................................... 10
Figure 4-3 bottom view ..................................................................................................................... 10
Figure 4-4 TB-FMCH-DP3 Dimension Diagram ................................................................................ 11
Figure 4-5 Block diagram of Power Circuit ...................................................................................... 12
Figure 4-6 Voltage level shifter ......................................................................................................... 12
Figure 4-7 Block Diagram of Source circuit...................................................................................... 13
Figure 4-8 Block Diagram of Sink circuit .......................................................................................... 14
Figure 4-9 Block Diagram of PLL Circuit .......................................................................................... 15
Figure 4-10 Signal connection of stacking two boards. ................................................................... 17
Figure 4-11 Stacked boards ............................................................................................................. 17
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TB-FMCH-DP3 Hardware User
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Introduction
Thank you for purchasing the TB-FMCH-DP3 board. Before using the product, be sure to carefully read this user manual and fully understand how to correctly use the product. First read through this manual, then always keep it handy.
SAFETY PRECAUTIONS
Be sure to observe these precautions
Observe the precautions listed below to prevent injuries to you or other personnel or damage to property.
Before using the product, read these safety precautions carefully to assure correct use.
These precautions contain serious safety instructions that must be observed.
After reading through this manual, be sure to always keep it handy.
The following conventions are used to indicate the possibility of injury/damage and classify precautions if the product is handled incorrectly.
Danger
Indicates the high possibility of serious injury or death if the product is handled incorrectly.
Warning
Indicates the possibility of serious injury or death if the product is handled incorrectly.
Caution
Indicates the possibility of injury or physical damage in connection with houses or household goods if the product is handled incorrectly.
The following graphical symbols are used to indicate and classify precautions in this manual.
(Examples)
Turn off the power switch.
Do not disassemble the product.
Do not attempt this.
!
Rev.1.00
5
!
!
!
!
!
!
!
TB-FMCH-DP3 Hardware User
’s Manual
Warning
In the event of a failure, disconnect the power supply.
If the product is used as is, a fire or electric shock may occur. Disconnect the power supply immediately and contact our sales personnel for repair.
If an unpleasant smell or smoking occurs, disconnect the power supply.
If the product is used as is, a fire or electric shock may occur. Disconnect the power supply immediately. After verifying that no smoking is observed, contact our sales personnel for repair.
Do not disassemble, repair or modify the product.
Otherwise, a fire or electric shock may occur due to a short circuit or heat generation. For inspection, modification or repair, contact our sales personnel.
Do not touch a cooling fan.
As a cooling fan rotates in high speed, do not put your hand close to it. Otherwise, it may cause injury to persons. Never touch a rotating cooling fan.
Do not place the product on unstable locations.
Otherwise, it may drop or fall, resulting in injury to persons or failure.
If the product is dropped or damaged, do not use it as is.
Otherwise, a fire or electric shock may occur.
Do not touch the product with a metallic object.
Otherwise, a fire or electric shock may occur.
Do not place the product in dusty or humid locations or where water may splash.
Otherwise, a fire or electric shock may occur.
Do not get the product wet or touch it with a wet hand.
Otherwise, the product may break down or it may cause a fire, smoking or electric shock.
Do not touch a connector on the product (gold-plated portion).
Otherwise, the surface of a connector may be contaminated with sweat or skin oil, resulting in contact failure of a connector or it may cause a malfunction, fire or electric shock due to static electricity.
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TB-FMCH-DP3 Hardware User
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Caution
!
Do not use or place the product in the following locations.
Humid and dusty locations
Airless locations such as closet or bookshelf
Locations which receive oily smoke or steam
Locations exposed to direct sunlight
Locations close to heating equipment
Closed inside of a car where the temperature becomes high
Staticky locations
Locations close to water or chemicals
Otherwise, a fire, electric shock, accident or deformation may occur due to a short circuit or heat generation.
!
Do not place heavy things on the product.
Otherwise, the product may be damaged.
■ Disclaimer
This product is an evaluation board for Displayport interface. Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those stated.
Even if the product is used properly, Tokyo Electron Device Limited assumes no responsibility for any damages caused by:
(1) Earthquake, thunder, natural disaster or fire resulting from the use beyond our responsibility, acts by a third party or other accidents, the customer
’s willful or accidental misuse or use under other abnormal conditions.
(2) Secondary impact arising from use of this product or its unusable state (business interruption or others)
(3) Use of this product against the instructions given in this manual.
(4) Malfunctions due to connection to other devices.
Tokyo Electron Device Limited assumes no responsibility or liability for:
(1) Erasure or corruption of data arising from use of this product.
(2) Any consequences or other abnormalities arising from use of this product, or
(3) Damage of this product not due to our responsibility or failure due to modification
This product has been developed by assuming its use for research, testing or evaluation. It is not authorized for use in any system or application that requires high reliability.
Repair of this product is carried out by replacing it on a chargeable basis, not repairing the faulty devices.
However, non-chargeable replacement is offered for initial failure if such notification is received within two weeks after delivery of the product.
The specification of this product is subject to change without prior notice.
The product is subject to discontinuation without prior notice.
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TB-FMCH-DP3 Hardware User
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1. Related Documents and Board Accessories
Related documents:
All documents relating to this Board can be downloaded from our website. Please refer to attached paper of the products.
Board Accessories:
- Spacer set : x1
2. Overview
The TB-FMCH-DP3 provides test environment for DisplayPort Standard Version1, Revision 2a.
It supports below features
4 Lane of 1.62Gbps, 2.7Gbps and 5.4Gbps
It uses TI SN75SP130 for Source(TX) and SN65DP159 for Sink(RX)
AUX Communication.(FAUX is not supported)
Also, it could stack up two TB-FMCH-DP3 for expand more channels.
Notice: This board is used with Xilinx
’s Displayport IP core.
Some points are not tested because IP does not use.
Question for IP core and reference design, please contact to Xilinx.
3. Feature
DisplayPort Driver IC: Texas Instruments, SN75DP130SS
DisplayPort Redriver IC: Texas Instruments, SN65DP159RGZ
PLLIC: Texas Instruments, LMK04906
DisplayPort connector: JAE, DP1RD20JQ1R400
FMC connector: Samtec, ASP-134488-01 / ASP-134486-01
Rev.1.00
Figure 3-1 High-pin Count Pin assignment
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TB-FMCH-DP3 Hardware User
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4. TB-FMCH-DP3 Function
4.1. Block Diagram
The following figure shows the block diagram of this Board.
CN4 is mounted to bottom side and it will connect to FPGA Evaluation boards.
Please see more detail of each circuit.
Rev.1.00
Figure 4-1 TB-FMCH-DP3 Block Diagram
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TB-FMCH-DP3 Hardware User
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4.2. External View of the Board
The following figures show the external views of the Board.
Figure 4-2 Top view
Rev.1.00
FMC-HPC for
Platform 基板
Figure 4-3 bottom view
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TB-FMCH-DP3 Hardware User
’s Manual
4.3. Board Specification
External Dimensions: W:78.8mm x H:69.0mm
Number of Layers: 8 Layers
Board Thickness: 1.6mm
Material: MEG-6(R-5775) or same specification.
Figure 4-4 TB-FMCH-DP3 Dimension Diagram
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TB-FMCH-DP3 Hardware User
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4.4. Power Supply
This board generates required voltage(1.1V) of DP139 from +3.3V is coming from FMC Connector.
Following is block diagram of power circuit.
VADJ +3.3V
1.1V
(RX IC Core Power)
Power
IC
3.3V
to 1.1V
+3.3V
DisplayPort
RX
IC
Input
Signal
BUF
IC
(Level
conversion)
VADJ
to 3.3
+3.3V
Input
Signal
BUF
IC
(Level
conversion)
VADJ
to 3.3
DisplayPort
TX
IC
I/O
Signal
+3.3V
Output
Signal
BUF
IC
(Level
conversion)
3.3
to VADJ
Figure 4-5 Block diagram of Power Circuit
4.4.1. IO Voltage
This board has a voltage level shifter for required signals.
FPGA IO voltage should be connected via FMC_VADJ on Carrier board.
PLL
Rev.1.00
Figure 4-6 Voltage level shifter
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TB-FMCH-DP3 Hardware User
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4.5. Source(TX) Block
Following figure shows block diagram of Source circuit. DP130 keep signal integrity before transfer signal via cable and it can change swing level and pre-emphasis by AUX communication.
SOURCE_AUX
SOURCE_LANE(x4)
SOURCE_HPD
SOURCE_EN
SOURCE_I2C(SCL/SDA)
SOURCE_RST
Other
(CAD,DDC_SCL/SDA,DDC_EN)
Figure 4-7 Block Diagram of Source circuit.
Table 4-1 Signals of Source Circuit
Signal Name I/O Description
SOURCE_AUX
SOURCE_LANE
SOURCE_HPD
SOURCE_EN
SOURCE_I2C
IO AUX signal. Bi-direction, Differential signals. Normally use this signals.
O Main link of displayport
I Hot Plug Detect Signal
O This is enabling DP130. It has pull-up register on the board.
Enable: High(1)
IO I2C signals for DP130. It is control interface without AUX communication.
Normally, it is not required to controlling.
SOURCE_RST
Other
O Reset Signal of DP130. It has pull-down register on the board.
-
Reset: High(1)
CAD_DDC，SCL/SDA，DDC_EN（
not tested
）
Accessing to DP130 via I2C interface.
It is possible to accessing DP130 via I2C interface. About I2C address please refer to below table.
Note: Basically, it is controlled by AUX communication. I2C access is not required.
Table 4-2 DP130 I2C Address
I2C Address(7bit) 010 1110 (0x2E)
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TB-FMCH-DP3 Hardware User
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4.6. Sink(RX) Block
Following figure shows block diagram of Sink circuit. DP159 keep signal integrity as swing level and jitter.
Figure 4-8 Block Diagram of Sink circuit
Table 4-3 Signals of Sink Circuit
Signal Name
SINK_AUX
SINK_LANE
SINK_HPD
SINK_I2C
I/O Description
IO AUX signal. Bi-direction, Differential signals. Normally use this signals.
I
O
Main link of displayport
Hot Plug Detect Signal
SINK_EN
IO I2C signals for DP159. It is control interface from Xilinx IP. DP159 required control from I2C because DP159 does not have AUX interface.
O This is output enable for DP159 It has pull-up register on the board.
Enable: High(1)
CLKOUT O This is CDR clock output. Frequency is depended on DP159 internal PLL setting.
It is related Xilinx Displayport IP control.
HBR2(5.4Gbps): 270MHz
HBR (2.7Gbps): 135MHz
RBR (1.62Gbps): 81MHz
Accessing to DP159 via I2C interface.
It is possible to accessing DP159 via I2C interface. About I2C address please refer to below table.
Note: It is required to access DP159 via I2C. setting is depended on AUX communication.
Xilinx Displayport IP supports DP159 and I2C control.
Table 4-4 DP159 I2C Address
I2C Address(7bit) 101 1110 (0x5E)
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TB-FMCH-DP3 Hardware User
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4.7. Clock circuit
Following block diagram shows PLL circuit.
PLL device is TI
“LMK04906” to generating reference clock of FPGA
Signal Name
Microwire
Status
CLKOUT0
Clean clock
Figure 4-9 Block Diagram of PLL Circuit
Table 4-5 signals of PLL circuit
I/O Description
IO Interface of LMK04906 internal resister.
Please refer to data sheet of LMK04906.
IO Status signals. Status meaning is depended on resister settings.
O
O
Output clock. It is possible to use reference clock of FPGA.
Not Tested
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TB-FMCH-DP3 Hardware User
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4.7.1. Operation example of PLL
This section described how to set resister of PLL for generating 135MHz, 81MHz, 162MHz and 270MHz.
1) Enable resister change: Write 0x00000031 to R31
2) Reset to PLL: write 0x00200000 to R00
3) Set following settings to each resister.
Table 4-6 PLL Resister settings (Step3)
Resister Address[5:0] Data[31:6] Note
R 00*
R 01*
R 02*
R 03
R 04
R 05
R 06
R 07
R 08
R 09
R 10
R 11
R 12
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0000009
0x000000F
0x0000012
0x000001E
0x0000009
0x000000F
0x0000012
0x000001E
0x0000009
0x000000F
0x0000012
0x000001E
0x400_0001
0x400_0000
0x400_0000
0x088_8000
0x088_8000
Same setting, even different frequency.
Same setting, even different frequency.
Same setting, even different frequency.
Same setting, even different frequency.
Same setting, even different frequency.
0x088_8000 Same setting, even different frequency.
0x2AA_AAAA Same setting, even different frequency.
0x08A_0200
0x02C_0881
0x0D8_600B
Disable reset of PLL. CLKOut0 : 270MHz
Disable reset of PLL. CLKOut0 : 162MHz
Disable reset of PLL. CLKOut0 : 135MHz
Disable reset of PLL. CLKOut0 : 81MHz
CLKOut1 : 270MHz
CLKOut1 : 162MHz
CLKOut1 : 135MHz
CLKOut1 : 81MHz
CLKOut2 : 270MHz
CLKOut2 : 162MHz
CLKOut2 : 135MHz
CLKOut2 : 81MHz
Same setting, even different frequency.
Same setting, even different frequency.
Same setting, even different frequency.
R 13
R 14
R 15
R 16
R 24
R 25
R 26
R 27
R 28
R 29
0x0D
0x0E
0x0F
0x10
0x18
0x19
0x2A
0x2B
0x2C
0x2D
0x1D8_0003
0x091_8000
0x000_0000
0x00A_A820
0x000_0006
0x008_0030
0x07D_4000
0x080_0002
0x000_8002
0x000_002D
Same setting, even different frequency.
Same setting, even different frequency.
Same setting, even different frequency.
Same setting, even different frequency.
Same setting, even different frequency.
Same setting, even different frequency.
Same setting, even different frequency.
Same setting, even different frequency.
Same setting, even different frequency.
Same setting, even different frequency.
R 30 0x2E 0x010_002D Same setting, even different frequency.
*This resister setting is depended on what frequency is required.
4) Disable resister change: write 0x00000001 to R31
For more detail, please refer to data sheet.
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TB-FMCH-DP3 Hardware User
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4.8. FMC connector for stacking
This board has two FMC connectors. One is connecting to FPGA Evaluation board and other is stacking same TB-FMCH-DP3 board.
In this section, it shows that lower FMC is
“base board” and upper FMC is “stack board”.
Following figure shows signal connection when stacking two boards.
Signal of stack board will connect CN3 of base board then signal name is changed as
“EX_***”.
“EX_***” signals connect to FPGA carrier board via CN4 of base board.
An exception, PLL control signal and clock are not connecting to FPGA carrier board via base board.
Figure 4-10 Signal connection of stacking two boards.
Figure 4-11 Stacked boards
Cation: Please confirm the notice of TB-FMCH-DP3.
4.9. Pin Assignment of CN4
Table 4-7 CN4 Pin assign (To carrier board) shows FMC pin assignment.
Signal direction is assigned as follows:
-
“I”: The signal came from carrier board to TB-FMCH-DP3.
-
“O”: The signal came from TB-FMCH-DP3 to carrier board.
Blue Character signal are connected to CN4 FMC Expansion connector.
Rev.1.00
17
19
25
26
27
28
29
30
31
32
33
20
21
22
23
24
34
15
16
17
18
35
36
37
38
#
9
10
11
12
13
5
6
7
8
1
2
3
4
14
39 DP5_C2M_N
40 GND
Rev.1.00
DP4_M2C_N
GND
GND
DP5_M2C_P
DP5_M2C_N
GND
GND
DP1_C2M_P
DP1_C2M_N
GND
GND
DP2_C2M_P
DP2_C2M_N
GND
GND
DP3_C2M_P
DP3_C2M_N
GND
GND
DP4_C2M_P
DP4_C2M_N
GND
GND
DP5_C2M_P
FMC signal
GND
DP1_M2C_P
DP1_M2C_N
GND
GND
DP2_M2C_P
DP2_M2C_N
GND
GND
DP3_M2C_P
DP3_M2C_N
GND
GND
DP4_M2C_P
TB-FMCH-DP3 Hardware User
’s Manual
Table 4-7 CN4 Pin assign (To carrier board)
O
-
I
I
-
-
I
-
-
I
I
I
-
-
-
I
O
-
-
O
I
-
-
I
I/O
-
O
O
-
-
-
O
O
-
-
O
O
-
O
I
-
A row in HPC pin assignment (CN4)
Signal in schematic
GND
SINK_ML_LANE1_P
SINK_ML_LANE1_N
GND
GND
SINK_ML_LANE2_P
SINK_ML_LANE2_N
GND
GND
SINK_ML_LANE3_P
SINK_ML_LANE3_N
GND
GND
EX_SINK_ML_LANE0_P
EX_SINK_ML_LANE0_N
GND
GND
EX_SINK_ML_LANE1_P
EX_SINK_ML_LANE1_N
GND
GND
SOURCE_ML_LANE2_P
SOURCE_ML_LANE2_N
GND
GND
SOURCE_ML_LANE1_P
SOURCE_ML_LANE1_N
GND
GND -
SOURCE_ML_LANE0_P
SOURCE_ML_LANE0_N
GND
GND
EX_SOURCE_ML_LANE0_P
EX_SOURCE_ML_LANE0_N
GND
GND
EX_SOURCE_ML_LANE1_P
EX_SOURCE_ML_LANE1_N
GND
Note
GND
SINK MainLink LANE1 (Positive)
SINK MainLink LANE1 (Negative)
GND
GND
SINK MainLink LANE2 (Positive)
SINK MainLink LANE2 (Negative)
GND
GND
SINK MainLink LANE3 (Positive)
SINK MainLink LANE3 (Negative)
GND
GND
SINK MainLink LANE0 from expanded board(Positive)
SINK MainLink LANE0 from expanded board (Negative)
GND
GND
SINK MainLink LANE1 from expanded board(Positive)
SINK MainLink LANE1 from expanded board (Negative)
GND
GND
SOURCE MainLink LANE2 (Positive)
SOURCE MainLink LANE2 (Negative)
GND
GND
SOURCE MainLink LANE1 (Positive)
SOURCE MainLink LANE1 (Negative)
GND
GND
SOURCE MainLink LANE0 (Positive)
SOURCE MainLink LANE0 (Negative)
GND
GND
SOURCE MainLink LANE0 (Positive, expanded board)
SOURCE MainLink LANE0 (Negative, expanded board)
GND
GND
SOURCE MainLink LANE1 (Positive, expanded board)
SOURCE MainLink LANE1 (Negative, expanded board)
GND
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TB-FMCH-DP3 Hardware User
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12
13
14
15
16
17
32
33
34
35
36
37
38
39
40
#
5
6
7
1
2
3
4
8
9
10
11
FMC signal
RES1
GND
GND
DP9_M2C_P
DP9_M2C_N
GND
GND
DP8_M2C_P
DP8_M2C_N
GND
GND
DP7_M2C_P
DP7_M2C_N
GND
GND
DP6_M2C_P
DP6_M2C_N
18
19
20
GND
GND
-
-
GBTCLK1_M2C_P O
25
26
27
28
29
30
31
21 GBTCLK1_M2C_N O
22
23
24
GND
GND
DP9_C2M_P
-
-
-
DP9_C2M_N
GND
GND
DP8_C2M_P
DP8_C2M_N
GND
GND
-
-
-
-
-
-
-
DP7_C2M_P
DP7_C2M_N
GND
GND
DP6_C2M_P
DP6_C2M_N
GND
GND
RES0
I
-
-
-
I/O
-
-
-
-
-
-
-
-
-
-
-
O
O
-
-
O
O
I
I
-
-
I
B row in HPC pin assignment (CN4)
Signal in schematic
-
GND
GND
-
-
GND
GND
-
-
GND
GND
EX_SINK_ML_LANE3_P
EX_SINK_ML_LANE3_N
GND
GND
EX_SINK_ML_LANE2_P
EX_SINK_ML_LANE2_N
GND
GND
CLK_OUT_P
CLK_OUT_N
GND
GND
-
-
GND
GND
-
-
GND
GND
EX_SOURCE_ML_LANE3_P
EX_SOURCE_ML_LANE3_N
GND
GND
EX_SOURCE_ML_LANE2_P
EX_SOURCE_ML_LANE2_N
GND
GND
-
Note
N.C
GND
GND
N.C
N.C
GND
GND
N.C
N.C
GND
GND
SINK MainLink LANE3 (Positive, expanded board)
SINK MainLink LANE3 (Negative, expanded board)
GND
GND
SINK MainLink LANE2 (Positive, expanded board)
SINK MainLink LANE2 (Negative, expanded board)
GND
GND
DP159 CDR Clock (Positive)
DP159 CDR Clock (Negative)
GND
GND
N.C
N.C
GND
GND
N.C
N.C
GND
GND
SOURCE MainLink LANE3 (Positive, expanded board)
SOURCE MainLink LANE3 (Negative, expanded board)
GND
GND
SOURCE MainLink LANE2 (Positive, expanded board)
SOURCE MainLink LANE2 (Negative, expanded board)
GND
GND
N.C
Rev.1.00
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TB-FMCH-DP3 Hardware User
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3
4
5
6
#
1
2
FMC signal
GND
DP0_C2M_P
DP0_C2M_N
GND
GND
DP0_M2C_P
7
12
13
14
15
16
17
18
8
9
10
11
19
20
21
22
23
24
25
26
27
35
36
37
38
39
40
28
29
30
31
32
33
34
Rev.1.00
DP0_M2C_N
GND
GND
LA06_P
LA06_N
GND
GND
LA10_P
LA10_N
GND
GND
LA14_P
LA14_N
GND
GND
LA18_P_CC
LA18_N_CC
GND
GND
LA27_P
LA27_N
GND
GND
SCL
SDA
GND
GND
GA0
12P0V
GND
12P0V
GND
3P3V
GND
I
-
-
O
O
-
-
I/O
I/O
-
-
I/O
-
-
I
I
I/O
-
-
O
I
-
-
I
I
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O
-
I
C row in HPC pin assignment (CN4)
Signal in schematic
GND GND
Note
SOURCE_ML_LANE0_P SOURCE MainLink LANE0 (Positive)
SOURCE_ML_LANE0_N
GND
GND
SINK_ML_LANE0_P
SINK_ML_LANE0_N
GND
GND
SINK_HPD
SINK_EN
GND
GND
SINK_I2C_SCL
SINK_I2C_SDA
GND
GND
SINK_AUX_P
SOURCE MainLink LANE0 (Negative)
GND
GND
SINK MainLink LANE0 (Positive)
SINK MainLink LANE0 (Negative)
GND
GND
SINK Hot Plug Detect signal
SINK DP159 Enable signal
GND
GND
SINK DP159 I2C SCL signal
SINK DP159 I2C SDA signal
GND
GND
SINK bi-direction AUX signal(Positive)
SINK_AUX_N
GND
GND
SINK_AUX_RX
SINK_AUX_TX
GND
GND
SINK_AUX_DE
SINK bi-direction AUX signal(Negative)
GND
GND
SINK single-end AUX, receiver signal
SINK single-end AUX, transfer signal
GND
EX_SINK_AUX_DE
GND
GND
2Kb_EEPPROM_SCL
GND
SINK single-end AUX, data enable signal
SINK single-end AUX, data enable signal
(expanded board)
GND
GND
I2C SCL signal for 2Kbit EEPROM
2Kb_EEPPROM_SDA I2C SDA signal for 2Kbit EEPROM
GND GND
GND
2Kb_EEPPROM_E0
GND
Address setting of 2Kbit RRPROM
+12V
GND
+12V
GND
+3.3V
GND
12P0V
GND
12P0V
GND
3P3V
GND
20
TB-FMCH-DP3 Hardware User
’s Manual
15
16
17
#
9
10
11
12
13
5
6
7
8
1
2
3
4
14
18
25
26
27
28
29
30
31
19
20
21
22
23
24
32
33
34
35
36
37
38
39
40
LA09_N
GND
GND
LA17_P_CC
LA17_N_CC
GND
LA23_P
LA23_N
GND
LA26_P
LA26_N
GND
TCK
TDI
TDO
3P3VAUX
TMS
TRST_L
GA1
3P3V
GND
3P3V
GND
3P3V
FMC signal I/O
PG_C2M
GND
-
-
GND -
GBTCLK0_M2C_P O
GBTCLK0_M2C_N O
GND -
GND
LA01_P_CC
-
I
LA01_N_CC
GND
LA05_P
LA05_N
GND
I
-
I/O
I/O
-
LA09_P
LA13_P
LA13_N
I/O
I/O
-
O
I
-
-
-
-
I/O
I/O
-
-
I/O
I/O
-
I
I
-
-
-
-
-
-
-
-
-
D row in HPC pin assignment (CN4)
Signal in schematic
-
GND
GND
GCLK0_P
GCLK0_N
GND
GND
EX_SINK_HPD
EX_SINK_EN
GND
EX_SINK_I2C_SCL
EX_SINK_I2C_SDA
GND
EX_SINK_AUX_P
EX_SINK_AUX_N
GND
EX_SINK_AUX_RX
EX_SINK_AUX_TX
GND
PLL_REFCLKIN_P
PLL_REFCLKIN_N
GND
EDID_I2C_SCL
EDID_I2C_SDA
GND
HDCP_I2C_SCL
HDCP_I2C_SDA
GND
-
-
-
+3.3V_AUX
-
-
2Kb_EEPPROM_E1
+3.3V
GND
+3.3V
GND
+3.3V
Note
N.C
GND
GND
PLL Clock output 0(Positive)
PLL Clock output 0(Negative)
GND
GND
SINK Hot Plug Detect signal(expanded board)
SINK DP159 Enable signal(expanded board)
GND
SINK DP159 I2C SCL(expanded board)
SINK DP159 I2C SDA(expanded board)
GND
SINK bi-direction AUX signal
(Positive, expanded board)
SINK bi-direction AUX signal
(Negative, expanded board)
GND
SINK single-end AUX, receiver signal
(expanded board)
SINK single-end AUX, transfer signal
(expanded board)
GND
PLL reference clock input(Positive)
PLL reference clock input(Negative)
GND
EDID ROM I2C SCL signal
EDID ROM I2C SDA signal
GND
HDCP ROM I2C SCL signal
HDCP ROM I2C SDA signal
GND
N.C
N.C
N.C
3P3VAUX
N.C
N.C
Address setting of 2Kbit RRPROM
3P3V
GND
3P3V
GND
3P3V
Rev.1.00
21
34
35
36
37
38
39
40
29
30
31
32
33
24
25
26
27
28
19
20
21
22
23
14
15
16
17
18
9
10
11
12
13
4
5
6
7
8
#
1
2
3
Rev.1.00
GND
HB13_P
HB13_N
GND
HB19_P
HB19_N
GND
HB21_P
HB21_N
GND
VADJ
GND
HA20_N
GND
HB03_P
HB03_N
GND
HB05_P
HB05_N
GND
HB09_P
HB09_N
FMC signal
GND
HA01_P_CC
HA01_N_CC
GND
GND
HA05_P
HA05_N
GND
HA09_P
HA09_N
GND
HA13_P
HA13_N
GND
HA16_P
HA16_N
GND
HA20_P
TB-FMCH-DP3 Hardware User
’s Manual
E row in HPC pin assignment (CN4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O
-
-
-
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
VADJ Power
GND
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
GND
N.C
N.C
GND
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
-
-
GND
-
-
GND
-
-
GND
FMC_VADJ
GND
-
GND
-
-
GND
-
-
GND
-
-
Signal in schematic
GND
-
-
GND
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
Note
22
#
22
23
24
25
26
27
28
15
16
17
18
19
20
21
9
10
11
12
13
14
5
6
7
8
1
2
3
4
35
36
37
38
39
40
29
30
31
32
33
34
Rev.1.00
FMC signal
GND
HA15_P
HA15_N
GND
HA19_P
HA19_N
GND
HB02_P
HB02_N
GND
HB04_P
HB04_N
GND
HB08_P
PG_M2C
GND
GND
HA00_P_CC
HA00_N_CC
GND
HA04_P
HA04_N
GND
HA08_P
HA08_N
GND
HA12_P
HA12_N
HB08_N
GND
HB12_P
HB12_N
GND
HB16_P
HB16_N
GND
HB20_P
HB20_N
GND
VADJ
TB-FMCH-DP3 Hardware User
’s Manual
F row in HPC pin assignment (CN4)
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N.C
N.C
GND
N.C
N.C
GND
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
GND
N.C
N.C
GND
N.C
N.C
PG_M2C
GND
GND
N.C
N.C
GND
N.C
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
VADJ Power
Signal in schematic
-
-
GND
-
-
GND
-
GND
-
-
GND
-
-
GND
GND
-
-
GND
-
-
-
GND
GND
-
-
GND
-
-
-
GND
-
-
GND
-
-
GND
-
-
GND
FMC_VADJ
Note
23
TB-FMCH-DP3 Hardware User
’s Manual
#
22
23
24
25
26
27
28
15
16
17
18
19
20
21
9
10
11
12
13
14
5
6
7
8
1
2
3
4
35
36
37
38
39
40
29
30
31
32
33
34
Rev.1.00
FMC signal
LA12_P
LA12_N
GND
LA16_P
LA16_N
GND
LA20_P
LA20_N
GND
LA22_P
LA22_N
GND
LA25_P
LA25_N
GND
CLK1_M2C_P
CLK1_M2C_N
GND
GND
LA00_P_CC
LA00_N_CC
GND
LA03_P
LA03_N
GND
LA08_P
LA08_N
GND
GND
LA29_P
LA29_N
GND
LA31_P
LA31_N
GND
LA33_P
LA33_N
GND
VADJ
GND
G row in HPC pin assignment (CN4)
I/O Signal in schematic Note
I
-
-
I
-
-
-
I/O
I/O
-
O
O
I
I
-
O
O
-
-
O
O
-
GND
CLK1_P
CLK1_N
GND
GND
PLL Clock output2 (Positive)
PLL Clock output2 (Negative)
GND
- GND GND
I/O SOURCE_DDC_SDA Please fixed to High(1)
I/O SOURCE_DDC_SCL Please fixed to High(1)
- GND GND
SOURCE_HPD
SOURCE_CAD
GND
SOURCE_RST
SOURCE_EN
GND
SOURCE Hot Plug Detect signal
SOURCE Cable Adapter Detect signal
GND
SOURCE DP130 reset signal(Active High)
SOURCE DP130 Enable signal(Active High)
GND
-
I/O
I/O
I
I
I
-
I/O SOURCE_I2C_SDA SOURCE DP130 I2C SDA signal
I/O SOURCE_I2C_SCL SOURCE DP130 I2C SCL signal
-
I/O
GND
SOURCE_AUX_P
GND
SOURCE bi-direction AUX signal(Positive)
I/O
-
O
SOURCE_AUX_N
GND
SOURCE bi-direction AUX signal(Negative)
GND
SOURCE_AUX_RX SOURCE single-end AUX, receiver signal
SOURCE_AUX_TX
GND
GND
STATUS_HLD
STATUS_LD
SOURCE single-end AUX, transfer signal
GND
SOURCE_DDC_EN Not used
SOURCE_AUX_DE SOURCE single-end AUX, data enable
GND
PLL Status: default is Read Back signal
PLL Status: default is Lock signal
GND
STATUS_CLK0
STATUS_CLK1
GND
-
-
GND
-
-
GND
FMC_VADJ
GND
GND
PLL Status: default is CLKin select signal
PLL Status: default is CLKin select signal
GND
N.C
N.C
GND
N.C
N.C
GND
VADJ power
GND
24
17
18
19
20
21
22
11
12
13
#
5
6
7
8
1
2
3
4
9
10
14
15
16
23
24
25
LA19_N
GND
LA21_P
26
32
33
34
35
36
37
27
28
29
30
31
38
39
40
Rev.1.00
LA21_N
GND
LA24_P
LA24_N
GND
LA28_P
LA28_N
GND
LA30_P
LA30_N
GND
LA32_P
LA32_N
GND
VADJ
FMC signal
VREF_A_M2C
PRSNT_M2C_L
GND
CLK0_M2C_P
CLK0_M2C_N
GND
LA02_P
LA02_N
GND
LA04_P
LA04_N
GND
LA07_P
LA07_N
GND
LA11_P
LA11_N
GND
LA15_P
LA15_N
GND
LA19_P
TB-FMCH-DP3 Hardware User
’s Manual
H row in HPC pin assignment (CN4)
I/O Signal in schematic note
-
-
-
-
-
-
I
-
I
I/O
I
-
I
-
-
-
O
O
O
-
I
I
-
I/O
I/O
-
I/O
I/O
-
O
I
-
I
I
-
-
GND
CLK0_P
EX_SOURCE_HPD
EX_SOURCE_CAD
GND
EX_SOURCE_RST
EX_SOURCE_EN
GND
EX_SOURCE_I2C_SDA
EX_SOURCE_I2C_SCL
GND
EX_SOURCE AUX_P
EX_SOURCE_AUX_N
GND
EX_SOURCE_AUX_RX
EX_SOURCE_AUX_TX
GND
EX_SOURCE_DDC_EN
EX_SOURCE_AUX_DE
GND
N.C
N.C
GND
PLL Clock output1 (Positive)
O
-
CLK0_N
GND
PLL Clock output1 (Negative)
GND
I/O EX_SOURCE_DDC_SDA Please fixed to High(1)
I/O EX_SOURCE_DDC_SCL Please fixed to High(1)
- GND GND
SOURCE Hot Plug detect signal
(expanded board)
SOURCE Cable Adapter Detect signal
(expanded board)
GND
SOURCE DP130 reset signal
(expanded board)
SOURCE DP130 enable signal
(expanded board)
GND
SOURCE DP130 I2C SDA
(expanded board)
SOURCE DP130 I2C SCL
(expanded board)
GND
SOURCE bi-direction AUX signal
(Positive, extended board)
SOURCE bi-direction AUX signal
(Negative, expanded board)
GND
SOURCE single-end AUX, receiver signal
(extended board)
SOURCE single-end AUX, transfer signal
(extended board)
GND
Not used
SOURCE single-end AUX, data enable
(extended board)
GND
STATUS_CLK2
STATUS_DIR
GND
LE_WR
CLK_WR
GND
DATA_WR
PLL Status: default is CLKin select signal
Direction control of Status_X
GND
Mircowire: Enable signal
Microwire: Clock signal
GND
Microwire: Data signal
-
GND
-
-
GND
FMC_VADJ
N.C
GND
N.C
N.C
GND
VADJ Power
25
TB-FMCH-DP3 Hardware User
’s Manual
36
37
38
39
40
31
32
33
34
35
26
27
28
29
30
21
22
23
24
25
16
17
18
19
20
11
12
13
14
15
6
7
8
9
10
#
1
2
3
4
5
Rev.1.00
HA22_P
HA22_N
GND
HB01_P
HB01_N
GND
HB07_P
HB07_N
GND
HB11_P
HB11_N
GND
HB15_P
HB15_N
GND
HB18_P
HB18_N
GND
VIO_B_M2C
GND
FMC signal
GND
CLK3_M2C_P
CLK3_M2C_N
GND
GND
HA03_P
HA03_N
GND
HA07_P
HA07_N
GND
HA11_P
HA11_N
GND
HA14_P
HA14_N
GND
HA18_P
HA18_N
GND
J row in HPC pin assignment (CN4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O
-
-
-
-
-
-
GND
-
-
GND
-
-
GND
-
GND
-
-
GND
-
-
GND
-
-
GND
-
Signal in schematic
GND
-
-
GND
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
GND
N.C
N.C
GND
GND
N.C
N.C
GND
N.C
N.C
note
26
TB-FMCH-DP3 Hardware User
’s Manual
34
35
36
37
38
39
40
29
30
31
32
33
24
25
26
27
28
19
20
21
22
23
14
15
16
17
18
7
8
9
10
11
12
13
#
1
2
3
4
5
6
HA21_P
HA21_N
GND
HA23_P
HA23_N
GND
HB00_P_CC
HB00_N_CC
GND
HB06_P_CC
HB06_N_CC
GND
HB10_P
HB10_N
GND
HB14_P
HB14_N
GND
HB17_P_CC
HB17_N_CC
GND
VIO_B_M2C
FMC signal
VREF_B_M2C
GND
GND
CLK2_M2C_P
CLK2_M2C_N
GND
HA02_P
HA02_N
GND
HA06_P
HA06_N
GND
HA10_P
HA10_N
GND
HA17_P_CC
HA17_N_CC
GND
K row in HPC pin assignment (CN4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O
-
-
-
O
O
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
-
-
GND
-
-
GND
-
-
GND
-
Signal in schematic
-
GND
GND
VCXO_OUT_P
VCXO_OUT_N
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
note
N.C
GND
GND
PLL VCXO Output (Positive)
PLL VCXO Output (Negative)
GND
Rev.1.00
27
TB-FMCH-DP3 Hardware User
’s Manual
4.10. FMC connector for expanded Board (CN3)
From next page, Table 4-8 CN3 Pin assign (For expanded Board) shows FMC pin assignment.
Signal direction is assigned as follows:
-
“I”: The signal came from carrier board to TB-FMCH-DP3.
-
“O”: The signal came from TB-FMCH-DP3 to carrier board.
Rev.1.00
28
TB-FMCH-DP3 Hardware User
’s Manual
7
8
9
10
11
17
18
19
20
21
12
13
14
15
16
22
#
1
2
3
4
5
6
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DP3_C2M_N
GND
GND
DP4_C2M_P
DP4_C2M_N
GND
GND
DP5_C2M_P
DP5_C2M_N
GND
Rev.1.00
FMC signal
GND
DP1_M2C_P
DP1_M2C_N
GND
GND
DP2_M2C_P
DP2_M2C_N
GND
GND
DP3_M2C_P
DP3_M2C_N
GND
GND
DP4_M2C_P
DP4_M2C_N
GND
GND
DP5_M2C_P
DP5_M2C_N
GND
GND
DP1_C2M_P
DP1_C2M_N
GND
GND
DP2_C2M_P
DP2_C2M_N
GND
GND
DP3_C2M_P
Table 4-8 CN3 Pin assign (For expanded Board)
I
-
-
I
O
-
-
O
I
-
-
-
-
-
-
-
-
-
-
O
I
-
-
I
O
-
-
O
O
-
-
-
-
-
-
-
-
-
I/O
-
I
A row in HPC pin assignment (CN3)
Signal in schematic
GND
EX_SINK_ML_LANE1_P
EX_SINK_ML_LANE1_N
GND
GND
EX_SINK_ML_LANE2_P
EX_SINK_ML_LANE2_N
GND
GND
EX_SINK_ML_LANE3_P
EX_SINK_ML_LANE3_N
GND
GND
-
-
GND
GND
-
-
GND
GND
EX_SOURCE_ML_LANE1_P
EX_SOURCE_ML_LANE1_N
GND
GND
EX_SOURCE_ML_LANE2_P
EX_SOURCE_ML_LANE2_N
GND
GND
EX_SOURCE_ML_LANE3_P
EX_SOURCE_ML_LANE3_N
GND
GND
-
-
GND
GND
-
-
GND
Note
N.C
N.C
GND
GND
N.C
N.C
GND
SINK MainLink LANE1
(Positive, extending board)
SINK MainLink LANE1
(Negative, extending board)
GND
GND
SINK MainLink LANE2
(Positive, extending board)
SINK MainLink LANE2
(Negative, extending board)
GND
GND
SINK MainLink LANE3
(Positive, extending board)
SINK MainLink LANE3
(Negative, extending board)
GND
GND
GND
GND
SOURCE MainLink LANE1
(Positive, extending board)
SOURCE MainLink LANE1
(Negative, extending board)
GND
GND
SOURCE MainLink LANE2
(Positive, extending board)
SOURCE MainLink LANE2
(Negative, extending board)
GND
GND
SOURCE MainLink LANE3
(Positive, extending board)
SOURCE MainLink LANE3
(Negative, extending board)
GND
GND
N.C
N.C
GND
GND
N.C
N.C
GND
29
TB-FMCH-DP3 Hardware User
’s Manual
#
21
22
23
24
25
26
27
15
16
17
18
19
20
8
9
10
11
12
13
14
5
6
7
1
2
3
4
35
36
37
38
39
40
28
29
30
31
32
33
34
Rev.1.00
FMC signal
RES1
GND
GND
DP9_M2C_P
DP9_M2C_N
GND
GND
DP8_M2C_P
DP8_M2C_N
GND
GND
DP7_M2C_P
DP7_M2C_N
GND
GND
DP6_M2C_P
DP6_M2C_N
GND
GND
GBTCLK1_M2C_P
GBTCLK1_M2C_N
GND
GND
DP9_C2M_P
DP9_C2M_N
GND
GND
DP8_C2M_P
DP8_C2M_N
GND
GND
DP7_C2M_P
DP7_C2M_N
GND
GND
DP6_C2M_P
DP6_C2M_N
GND
GND
RES0
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B row in HPC pin assignment (CN3)
Signal in schematic
-
GND
GND
-
-
GND
GND
GND
-
-
GND
GND
-
-
-
GND
GND
-
-
GND
-
GND
GND
-
-
GND
GND
GND
-
-
GND
GND
-
-
-
GND
GND
-
-
GND
N.C
GND
GND
N.C
N.C
GND
GND
GND
N.C
N.C
GND
GND
N.C
N.C
N.C
GND
GND
N.C
N.C
GND
N.C
GND
GND
N.C
N.C
GND
GND
GND
N.C
N.C
GND
GND
N.C
N.C
N.C
GND
GND
N.C
N.C
GND
Note
30
19
20
21
22
LA14_N
GND
GND
LA18_P_CC
23
24
25
26
LA18_N_CC
GND
GND
LA27_P
33
34
35
36
37
38
39
40
27
28
29
30
31
32
Rev.1.00
LA27_N
GND
GND
SCL
SDA
GND
GND
GA0
12P0V
GND
12P0V
GND
3P3V
GND
11
12
13
14
15
16
17
18
7
8
9
10
#
1
2
3
4
5
6
FMC signal
GND
DP0_C2M_P
DP0_C2M_N
GND
GND
DP0_M2C_P
DP0_M2C_N
GND
GND
LA06_P
LA06_N
GND
GND
LA10_P
LA10_N
GND
GND
LA14_P
TB-FMCH-DP3 Hardware User
’s Manual
-
-
-
-
-
-
-
-
-
-
-
-
-
-
O
-
-
I
I
-
-
O
O
-
-
O
O
-
-
I/O
I/O
-
-
I/O
I/O
-
-
I
I/O
-
O
C row in HPC pin assignment (CN3)
Signal in schematic
GND
EX_SOURCE_ML_LANE0_P
EX_SOURCE_ML_LANE0_N
GND
GND
EX_SINK_ML_LANE0_P
EX_SINK_ML_LANE0_N
GND
GND
EX_SINK_HPD
EX_SINK_EN
GND
GND
EX_SINK_I2C_SCL
EX_SINK_I2C_SDA
GND
GND
EX_SINK_AUX_P
EX_SINK_AUX_N
GND
GND
EX_SINK_AUX_RX
EX_SINK_AUX_TX
GND
GND
EX_SINK_AUX_DE
-
GND
GND
-
-
GND
GND
-
+12V
GND
+12V
GND
+3.3V
GND
Note
GND
SOURCE MainLink LANE0
(Positive, extending board)
SOURCE MainLink LANE0
(Negative, extending board)
GND
GND
SOURCE MainLink LANE3
(Positive, extending board)
SOURCE MainLink LANE3
(Negative, extending board)
GND
GND
SINK Hot Plug Detect signal
(extended board)
SINK SP159 enable signal
(extended board)
GND
GND
SINK DP159 I2C SCL(expanded board)
SINK DP159 I2C SDA(expanded board)
GND
GND
SINK bi-direction AUX signal
(Positive, expanded board)
SINK bi-direction AUX signal
(Negative, expanded board)
GND
GND
SINK single-end AUX, receiver signal
(expanded board)
SINK single-end AUX, transfer signal
(expanded board)
GND
GND
SINK single-end AUX, data enable signal (expanded board)
-
GND
GND
N.C
N.C
GND
GND
N.C
12P0V
GND
12P0V
GND
3P3V
GND
31
TB-FMCH-DP3 Hardware User
’s Manual
#
22
23
24
25
26
27
28
15
16
17
18
19
20
21
9
10
11
12
13
14
5
6
7
8
1
2
3
4
35
36
37
38
39
40
29
30
31
32
33
34
FMC signal
PG_C2M
GND
GND
GBTCLK0_M2C_P
GBTCLK0_M2C_N
GND
GND
LA01_P_CC
LA01_N_CC
GND
LA05_P
LA05_N
GND
LA09_P
LA09_N
GND
LA13_P
LA13_N
GND
LA17_P_CC
LA17_N_CC
GND
LA23_P
LA23_N
GND
LA26_P
LA26_N
GND
TCK
TDI
TDO
3P3VAUX
TMS
TRST_L
GA1
3P3V
GND
3P3V
GND
3P3V
D row in HPC pin assignment (CN3)
I/O Signal in schematic
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
-
-
GND
-
-
GND
-
GND
-
-
GND
-
-
-
GND
-
-
GND
-
-
GND
GND
-
-
GND
GND
-
-
-
-
+3.3V_AUX
-
-
-
+3.3V
GND
+3.3V
GND
+3.3V
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
GND
N.C
N.C
GND
N.C
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
GND
N.C
N.C
GND
GND
N.C
N.C
N.C
N.C
3P3VAUX
N.C
N.C
N.C
3P3V
GND
3P3V
GND
3P3V
Rev.1.00
Note
32
34
35
36
37
38
39
40
29
30
31
32
33
24
25
26
27
28
19
20
21
22
23
14
15
16
17
18
9
10
11
12
13
4
5
6
7
8
#
1
2
3
Rev.1.00
GND
HB13_P
HB13_N
GND
HB19_P
HB19_N
GND
HB21_P
HB21_N
GND
VADJ
GND
HA20_N
GND
HB03_P
HB03_N
GND
HB05_P
HB05_N
GND
HB09_P
HB09_N
FMC signal
GND
HA01_P_CC
HA01_N_CC
GND
GND
HA05_P
HA05_N
GND
HA09_P
HA09_N
GND
HA13_P
HA13_N
GND
HA16_P
HA16_N
GND
HA20_P
TB-FMCH-DP3 Hardware User
’s Manual
E row in HPC pin assignment (CN3)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O
-
-
-
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
VADJ Power
GND
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
GND
N.C
N.C
GND
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
-
-
GND
-
-
GND
-
-
GND
FMC_VADJ
GND
-
GND
-
-
GND
-
-
GND
-
-
Signal in schematic
GND
-
-
GND
GND
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
Note
33
#
22
23
24
25
26
27
28
15
16
17
18
19
20
21
9
10
11
12
13
14
5
6
7
8
1
2
3
4
35
36
37
38
39
40
29
30
31
32
33
34
Rev.1.00
FMC signal
GND
HA15_P
HA15_N
GND
HA19_P
HA19_N
GND
HB02_P
HB02_N
GND
HB04_P
HB04_N
GND
HB08_P
PG_M2C
GND
GND
HA00_P_CC
HA00_N_CC
GND
HA04_P
HA04_N
GND
HA08_P
HA08_N
GND
HA12_P
HA12_N
HB08_N
GND
HB12_P
HB12_N
GND
HB16_P
HB16_N
GND
HB20_P
HB20_N
GND
VADJ
TB-FMCH-DP3 Hardware User
’s Manual
F row in HPC pin assignment (CN3)
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N.C
N.C
GND
N.C
N.C
GND
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
GND
N.C
N.C
GND
N.C
N.C
PG_M2C
GND
GND
N.C
N.C
GND
N.C
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
VADJ Power
Signal in schematic
-
-
GND-
-
-
GND
-
GND
-
-
GND
-
-
GND
GND
-
-
GND
-
-
-
GND
GND
-
-
GND
-
-
-
GND
-
-
GND
-
-
GND
-
-
GND
FMC_VADJ
Note
34
10
11
12
13
14
15
16
17
18
#
5
6
7
8
1
2
3
4
9
19
20
21
22
23
24
LA20_N
GND
LA22_P
25
30
31
32
33
34
35
36
26
27
28
29
37
38
39
40
Rev.1.00
LA22_N
GND
LA25_P
LA25_N
GND
LA29_P
LA29_N
GND
LA31_P
LA31_N
GND
LA33_P
LA33_N
GND
VADJ
GND
FMC signal
GND
CLK0_M2C_P
CLK0_M2C_N
GND
GND
LA00_P_CC
LA00_N_CC
GND
LA03_P
LA03_N
GND
LA08_P
LA08_N
GND
LA12_P
LA12_N
GND
LA16_P
LA16_N
GND
LA20_P
TB-FMCH-DP3 Hardware User
’s Manual
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O
-
I/O
I/O
-
-
-
-
-
I
I
-
O
O
-
I/O
I/O
-
I/O
I/O
-
I
O
-
O
G row in HPC pin assignment (CN3)
Signal in schematic Note
GND
-
-
GND
GND
N.C
N.C
GND
GND GND
EX_SOURCE_DDC_SDA Please fixed to High(1)
EX_SOURCE_DDC_SCL Please fixed to High(1)
-
EX_SOURCE_HPD
EX_SOURCE_CAD
-
EX_SOURCE_RST
EX_SOURCE_EN
-
EX_SOURCE_I2C_SDA
EX_SOURCE_I2C_SCL
-
EX_SOURCE_AUX_P
EX_SOURCE_AUX_N
-
EX_SOURCE_AUX_RX
EX_SOURCE_AUX_TX
-
GND
SOURCE Hot Plug detect signal
(expanded board)
SOURCE Cable Adapter Detect signal
(expanded board)
GND
SOURCE DP130 reset signal
(expanded board)
SOURCE DP130 enable signal
(expanded board)
GND
SOURCE DP130 I2C SDA
(expanded board)
SOURCE DP130 I2C SCL
(expanded board)
GND
SOURCE bi-direction AUX signal
(Positive, extended board)
SOURCE bi-direction AUX signal
(Negative, expanded board)
GND
SOURCE single-end AUX, receiver signal
(extended board)
SOURCE single-end AUX, transfer signal
(extended board)
GND
EX_SOURCE_DDC_EN Not used
EX_SOURCE_AUX_DE
GND
SOURCE single-end AUX, data enable
(extended board)
GND
-
-
GND
-
-
GND
-
N.C
N.C
GND
N.C
N.C
GND
N.C
-
GND
-
-
GND
FMC_VADJ
GND
N.C
GND
N.C
N.C
GND
VADJ power
GND
35
TB-FMCH-DP3 Hardware User
’s Manual
# FMC signal
20
21
22
23
24
25
13
14
15
16
17
18
19
7
8
9
10
11
12
1
2
3
4
5
6
33
34
35
36
37
38
39
40
26
27
28
29
30
31
32
Rev.1.00
LA21_N
GND
LA24_P
LA24_N
GND
LA28_P
LA28_N
GND
LA30_P
LA30_N
GND
LA32_P
LA32_N
GND
VADJ
LA07_P
LA07_N
GND
LA11_P
LA11_N
GND
LA15_P
LA15_N
GND
LA19_P
LA19_N
GND
LA21_P
VREF_A_M2C
PRSNT_M2C_L
GND
CLK0_M2C_P
CLK0_M2C_N
GND
LA02_P
LA02_N
GND
LA04_P
LA04_N
GND
H row in HPC pin assignment (CN3)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O
N.C
GND
N.C
N.C
GND
N.C
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
VADJ power
Signal in schematic
-
GND
-
-
GND
-
-
-
GND
-
-
GND
-
-
-
GND
-
-
GND
-
-
-
-
-
GND
-
-
-
GND
GND
-
-
GND
-
-
GND
-
-
GND
FMC_VADJ
Note
36
#
22
23
24
25
26
27
28
15
16
17
18
19
20
21
9
10
11
12
13
14
5
6
7
8
1
2
3
4
35
36
37
38
39
40
29
30
31
32
33
34
Rev.1.00
FMC signal
HA14_P
HA14_N
GND
HA18_P
HA18_N
GND
HA22_P
HA22_N
GND
HB01_P
HB01_N
GND
HB07_P
HB07_N
GND
CLK3_M2C_P
CLK3_M2C_N
GND
GND
HA03_P
HA03_N
GND
HA07_P
HA07_N
GND
HA11_P
HA11_N
GND
GND
HB11_P
HB11_N
GND
HB15_P
HB15_N
GND
HB18_P
HB18_N
GND
VIO_B_M2C
GND
TB-FMCH-DP3 Hardware User
’s Manual
J row in HPC pin assignment (CN3)
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N.C
GND
N.C
N.C
GND
N.C
N.C
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
N.C
GND
N.C
N.C
GND
GND
N.C
N.C
GND
GND
N.C
N.C
GND
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
VIO_B_M2C
GND
Signal in schematic
-
GND
-
-
GND
-
-
-
-
GND
-
-
GND
-
-
-
GND
-
-
GND
GND
-
-
GND
GND
-
-
GND
GND
-
-
GND
-
GND
GND
-
-
GND
-
-
Note
37
#
22
23
24
25
26
27
28
15
16
17
18
19
20
21
9
10
11
12
13
14
5
6
7
8
1
2
3
4
35
36
37
38
39
40
29
30
31
32
33
34
FMC signal
VREF_B_M2C
GND
GND
CLK2_M2C_P
CLK2_M2C_N
GND
HA02_P
HA02_N
GND
HA06_P
HA06_N
GND
HA10_P
HA10_N
GND
HA17_P_CC
HA17_N_CC
GND
HA21_P
HA21_N
GND
HA23_P
HA23_N
GND
HB00_P_CC
HB00_N_CC
GND
HB06_P_CC
HB06_N_CC
GND
HB10_P
HB10_N
GND
HB14_P
HB14_N
GND
HB17_P_CC
HB17_N_CC
GND
VIO_B_M2C
TB-FMCH-DP3 Hardware User
’s Manual
K row in HPC pin assignment (CN3)
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N.C
N.C
GND
N.C
N.C
GND
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
GND
N.C
N.C
GND
N.C
N.C
N.C
GND
GND
N.C
N.C
GND
N.C
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
N.C
GND
N.C
Signal in schematic
-
-
GND
-
-
GND
-
GND
-
-
GND
-
-
GND
GND
-
-
GND
-
-
-
GND
GND
-
-
GND
-
-
-
GND
-
-
GND
-
-
GND
-
-
GND
-
Note
Rev.1.00
38
TB-FMCH-DP3 Hardware User
’s Manual
Rev.1.00
Inrevium Company
URL:
http://solutions.inrevium.com/ http://solutions.inrevium.com/jp
E-mail: [email protected]
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Kanagawa, Japan 221-0056
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39
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