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CS470xx

CS470xx Data Sheet

Features

 Cost-effective, High-performance 32-bit DSP

 300,000,000 MAC/S (multiply accumulates per second)

 Dual MAC cycles per clock

 72-bit accumulators are the highest precision in the industry

 32K x 32-bit SRAM with three 2K blocks assignable to either Y data or program memory

 Integrated DAC and ADC Functionality

The CS470xx family is a new generation of audio system-on-a-chip (ASOC) processors targeted at high fidelity, cost sensitive designs. Derived from the highly successful CS48500 32-bit fixed-point audio enhancement processor family, the CS470xx further simplifies system design and reduces total system cost by integrating the S/

PDIF Rx, S/PDIF Tx, analog inputs, analog outputs, and

SRCs. For example, a hardware SRC can down-sample a

192 kHz S/PDIF stream to a lower Fs to reduce memory and MIPS requirements for processing. This integration effectively reduces the chip count from 3 to 1, which allows smaller, less expensive board designs.

 8

Channels of 24-bit DAC output: 108dB DR, –98 dB

THD+N

 4

Channels of 24-bit ADC input: 105dB DR, –98 dB

THD+N

 Integrated 5:1 analog mux feeds one stereo ADC

 Configurable Serial Audio Inputs and Outputs

Target applications include:

Automotive head units and outboard amplifiers

Automotive processors and automotive integration hubs

Digital TV

 MP3 docking stations

 Integrated 192 kHz S/PDIF Rx

 Integrated 192 kHz S/PDIF Tx

 Supports 32-bit serial data @ 192 kHz

 Supports 32-bit audio sample I/O between DSP chips

 TDM I/O modes

Supports Different Sample Rates (Fs)

AVR and DVD RX

DSP controlled speakers (subwoofers, sound bars)

The CS470xx is programmed using the simple yet powerful

Cirrus proprietary DSP Composer™ GUI development and pre-production tuning tool. Processing chains can be designed using a drag-and-drop interface to place/utilize functional macro audio DSP primitives and custom audio filtering blocks. The end result is a software image that is downloaded to the DSP via serial control port.

 Three integrated hardware SRC blocks

 Output can be master or slave

 Supports dual-domain Fs on S/PDIF vs. I²S inputs

DSP Tool Set with Private Keys Protect Customer IP

The Cirrus Framework™ programming environment offers

Assembly and C language compilers and other software development tools for porting existing code to the CS470xx family platform.

 Integrated Clock Manager/PLL

 Flexibility to operate from internal PLL, external crystal, external oscillator

 Input Fs Auto Detection w/ µC Acknowledgement

The CS470xx is available in a 100-pin LQFP package with exposed pad for better thermal characteristics. Both

Commercial (0°C to +70°C) and Automotive (–40°C to

+85°C) temperature grades.

 Host Control and Boot via I²C™ or SPI™ Serial Interface

Ordering Information:

 Configurable GPIOs and External Interrupt Input

See Section 6 for ordering information.

 1.8V Core and a 3.3V I/O that is tolerant to 5V input

 Low-power Mode

“ †” features differ on CS47024, CS47028, or CS47048.

See Table 3-1 .

Copyright

Cirrus Logic, Inc. 2012

(All Rights Reserved) http://www.cirrus.com

DS787PP9

JUL '12

ADC’s & DAC’s operate in Single ended or

Differential mode

DBC

(I

2

C Slave)

PLL

Clock

Manager

Timers GPIO x4

I

2

S /

S/PDIF

I

2

S

Coyote 32-bit Core

text

in the CS47048 DSP

8ch

S

R

C

2

DAC0

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

DAC7

ADC0/1

Stereo Inputs

On Analog in

S

R

C

1

4ch

ADC2/3

SPI / I

2

C

Control

DMA x8

PIC

ROM

RAM

P

Y

X

ROM

RAM

ROM

RAM

32K x 32-bit SRAM with three 2K blocks

Assignable to Program or Y Data memory

CS47048 Block Diagram

8ch

S

R

C

3

SRC3 has 8 independent Channels for In or Out

x2

I

2

S x2

I

2

S / S/PDIF

DS787PP9 2

3

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find the one nearest you, go to www.cirrus.com.

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR

ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS

SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS.

INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES

NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR

PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS

THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS,

EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR

ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, the Cirrus Logic logo designs, Framerwork, and DSP Composer are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

SPI is a trademark of Motorola, Inc.

I²C is a trademark of Philips Semiconductor.

Dolby, Pro Logic, Dolby Headphone, Virtual Speaker and the double-D symbol are registered trademarks of Dolby Laboratories, Inc. Supply of an implementation of Dolby

Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories.

SRS CircleSurround II technology is incorporated under license from SRS Labs, Inc. The SRS Circle Surround II technology/solution rights incorporated in the Cirrus Logic

CS470xx products are owned by SRS Labs, a U.S. Corporation and licensed to Cirrus Logic, Inc. Purchaser of the Cirrus Logic CS470xx products must sign a license for use of the chip and display of the SRS Labs trademarks. Any products incorporating the Cirrus Logic CS470xx products must be sent to SRS Labs for review. SRS CircleSurround

II is protected under US and foreign patents issued and/or pending. SRS Circle Surround II, SRS and (O) symbol are trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the Cirrus Logic CS470xx products, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS technology/solution. SRS Labs requires all set makers to comply with all rules and regulations as outlined in the SRS

Trademark Usage Manual.

DS787PP9

1 Documentation Strategy

1 Documentation Strategy

The CS470xx Data Sheet describes the CS47048, CS47028, and CS47024 audio processors. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS470xx processors.

Table 1-1. CS470xx Related Documentation

Document Name Description

CS470xx Data Sheet This document

CS470xx Hardware User’s Manual Guide Includes detailed system design information such as typical connection diagrams, boot-procedures, and pin descriptions

AN333 - CS470xx Firmware User’s Manual Includes a list of firmware modules available on the CS470xx family platform and detailed firmware design information including signal processing flow diagrams and control API information

DSP Composer User’s Manual Includes detailed configuration and usage information for the GUI development tool

CDB470xx User’s Manual Includes detailed instructions on the use of the CDB470xx development board

The scope of the CS470xx Data Sheet is primarily the hardware specifications of the CS470xx family of devices. This includes hardware functionality, characteristic data, pinout, and packaging information.

The intended audience for the CS470xx Data Sheet is the system PCB designer, MCU programmer, and the quality control engineer.

2 Overview

The CS470xx DSP is designed to provide high-performance post-processing and mixing of analog and digital audio. Dual clock domains are supported when the DAI and SPDIF RX inputs are used together. Integrated sample rate converters

(SRCs) allow audio streams with different sample rates to be mixed. The low-power standby preserves battery life for applications that are always on, but not necessarily processing audio, such as automotive audio systems.

The CS470xx uses voltage-out DACs and is capable of supporting dual input clock domains through the use of the internal

SRCs. The CS470xx is available in a 100-pin LQFP package. Refer to

Table 3-1 and Table 3-2

for the input, output, and firmware configurations for the CS470xx DSP.

2.1 Licensing

Licenses are required for any third-party audio processing algorithms provided for the CS470xx. Contact your local Cirrus

Logic Sales representative for more information.

DS787PP9 4

3 Code Overlays

3 Code Overlays

The suite of software available for the CS470xx family consists of an operating system (OS) and a library of overlays. The software components for the CS470xx family include:

1. OS/Kernel—Encompasses all non-audio processing tasks, including loading data from external serial memory, processing host messages, calling audio-processing subroutines, error concealment, etc.

2. Decoder—Any module that performs a compressed audio decode on IEC61937-packed data delivered via S/PDIF

Rx or I²S input, such as Dolby Digital (AC3).

3. Matrix-processor—Any Module that performs a matrix decode on PCM data to produce more output channels than input channels (2Æn channels). Examples are Dolby ® Pro Logic ® IIx and SRS Circle Surround II ® . Generally speaking, these modules increase the number of valid channels in the audio I/O buffer.

4. Virtualizer-processor—Any module that encodes PCM data into fewer output channels than input channels (nÆ2 channels) with the effect of providing “phantom” speakers to represent the physical audio channels that were eliminated. Examples are Dolby Headphone

®

2 and Dolby

®

Virtual Speaker

®

2. Generally speaking, these modules reduce the number of valid channels in the audio I/O buffer.

5. Post-processors—Any module that processes audio I/O buffer PCM data. Examples are bass management, audio manager, tone control, EQ, delay, customer-specific effects, and any post-processing algorithms available for the

CS470xx DSP.

The bulk of standard overlays are stored in ROM within the CS470xx, but a small image is required to configure the overlays and boot the DSP. This small image can either be stored in an external serial flash/EEPROM, or downloaded via a host controller through the SPI/I²C serial port.

The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a different post-processor is selected, the OS, does not need to be reloaded—only the new post-processor.

Table 3-1 lists the different configuration options available. Refer to the CS470xx Firmware User’s Manual for the latest

listing of application codes and Cirrus Framework™ modules available. See

Table 3-2

, which provides a summary of the available channels for each type of input and output communication mode for members of the CS470xx family of DSPs.

5 DS787PP9

3 Code Overlays

Table 3-1. CS470xx Device Selection Guide

Features

CS47048-CQZ

CS47048-DQZ

CS47028-CQZ

CS47028-DQZ

CS47024-CQZ

CS47024-DQZ

Primary Applications • 4-In/8-Out Car Audio

• High-end Digital TV

• Dual Source/Dual Zone

• 2-In/8-Out Car Audio

• Sound Bar

• DVD Receiver

• 2-In/4-Out Car Audio

• Digital TV

• Portable Audio Docking Station

• Portable DVD

• DVD Mini / Receiver

• Multimedia PC Speakers

Package

DSP Core

100-pin LQFP with Exposed Pad

Cirrus Logic 32-bit Core

SRAM 32K x 32-bit SRAM with three 2K blocks x 32-bit SRAM, assignable to either Y data or program memory

Integrated DAC and ADC • 2 Channels of ADC input: with integrated 5:1 analog mux

• 2 additional channels of ADC input: without mux

• 8 channels of DAC output

• 2 channels of ADC input: with integrated 5:1 analog mux

• 8 channels of DAC output

• 2 channels of ADC input: with integrated 5:1 analog mux

• 4 channels of DAC output

Configurable Serial Audio

Inputs/Outputs

• Integrated 192 kHz S/PDIF Rx, 2 Integrated 192 kHz S/PDIF Tx

• I2S support for 32-bit Samples @ 192 kHz

• TDM Input modes (Up to 8 channels)

• TDM Output modes (Up to 8 channels)

Supports Different Fs

Sample Rates

Other Features

• Integrated hardware SRC blocks for all ADC and DAC channels

• Additional 8-channel hardware SRC block

• Dual-domain Fs on inputs (I2S and S/PDIF Rx)

• Output can be master or slave

• Integrated Clock Manager/PLL with flexibility to operate from internal PLL, external crystal, external oscillator

• Host Control and Boot via SPI/I²C Serial Interface

• DSP Tool Set w/ Private Keys Protect Customer IP

• Configurable GPIOs and External Interrupts

• Hardware Watchdog Timer

Table 3-2. CS470xx Channel Count

Product

PCM/TDM In

1

TDM Out

1

PCM

Out

ADC with 5:1

Input Mux

ADC without Mux

DAC

Out

S/PDIF In

(Stereo

Pairs)

S/PDIF

Out (Stereo Pairs)

CS47048 • Up to 5 I2S lines, 2 channels per line or

• 1 TDM line, up to 8 channels per line.

CS47028 • Up to 5 I2S lines, 2 channels per line or

• 1 TDM line, up to 8 channels per line.

CS47024 • Up to 5 I2S lines, 2 channels per line or

• 1 TDM line, up to 8 channels per line.

Up to 8 channels

Up to 8 channels

Up to 8 channels

8

8

8

2

2

2

2

0

0

8

8

4

1

1

1

2

2

2

1. Contact your Cirrus Logic representative to determine the TDM modes that are supported. The CS470xx can support up to 8 channels per line, but the DSP software provided for the IC can restrict this capability.

DS787PP9 6

4 Hardware Functional Description

4 Hardware Functional Description

The CS470xx family, which includes the CS47048, CS47028, and CS47024 DSPs, is a true system-on-a-chip that combines a powerful 32-bit DSP engine with analog/digital audio inputs and analog/digital audio outputs. It can be integrated into a complex multi-DSP processing system, or stand alone in an audio product that requires analog-in and analog-out. A top level block diagram for the CS47048, CS47028, and CS47024 products are shown in

Fig. 4-1 ,

Fig. 4-2

,

and Fig. 4-3

respectively.

ADC’s & DAC’s operate in Single ended or

Differential mode

DBC

(I

2

C Slave)

PLL

Clock

Manager

Timers GPIO x4

I

2

S /

S/PDIF

I

2

S

32-bit Core

text

in the CS47048 DSP

8ch

S

R

C

2

DAC0

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

DAC7

ADC0/1

Stereo Inputs

On Analog in

S

R

C

1

4ch

ADC2/3

SPI / I

2

Control

C

DMA x8

PIC

ROM

RAM

P

Y

X

ROM

RAM

ROM

RAM

32K x 32-bit SRAM with three 2K blocks

Assignable to Program or Y Data memory

Figure 4-1. CS47048 Top-level Block Diagram

8ch

S

R

C

3

SRC3 has 8 independent Channels for In or Out

x2

I

2

S x2

I

2

S / S/PDIF

7 DS787PP9

DS787PP9

4 Hardware Functional Description

ADC’s & DAC’s operate in Single ended or

Differential mode

DBC

(I

2

C Slave)

PLL

Clock

Manager

Timers GPIO x4

I

2

S /

S/PDIF

I

2

S

32-bit Core

text

in the CS 47028 DSP

8ch

S

R

C

2

DAC0

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

DAC7

Stereo Inputs

On Analog in

ADC2/3

S

R

C

1

4ch

SPI / I

2

Control

C

ADC’s & DAC’s operate in Single ended or

Differential mode

DMA x8

PIC

ROM

RAM

P

Y

X

ROM

RAM

ROM

RAM

32K x 32-bit SRAM with three 2K blocks

Assignable to Program or Y Data memory

Figure 4-2. CS47028 Top-level Block Diagram

DBC

(I

2

C Slave)

PLL

Clock

Manager

Timers GPIO

8ch

S

R

C

3

SRC3 has 8 independent Channels for In or Out

x2

I

2

S x2

I

2

S / S/PDIF x4

I

2

S /

S/PDIF

I

2

S

32-bit Core

text

in the CS 47024 DSP

8ch

S

R

C

2

DAC0

DAC1

DAC2

DAC3

Stereo Inputs

On Analog in

ADC2/3

S

R

C

1

4ch

SPI / I

2

Control

C

DMA x8

PIC

ROM

RAM

P

Y

X

ROM

RAM

ROM

RAM

32K x 32-bit SRAM with three 2K blocks

Assignable to Program or Y Data memory

Figure 4-3. CS47024 Top-level Block Diagram

8ch

S

R

C

3

SRC3 has 8 independent Channels for In or Out

x2

I

2

S x2

I

2

S / S/PDIF

8

4.1 Cirrus Logic 32-bit DSP Core

4.1 Cirrus Logic 32-bit DSP Core

The CS470xx comes with a Cirrus Logic 32-bit core with separate X and Y data and P code memory spaces. The DSP core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight 72-bit accumulators, four X-data and four Y-data registers, and 12 index registers.

The DSP core is coupled to a flexible 8-channel DMA engine. The DMA engine can move data between peripherals such as the serial control port (SCP), digital audio input (DAI) and digital audio output (DAO), sample rate converters (SRC), analog-to-digital converters (ADC), digital-to-analog converters (DAC), or any DSP core memory, all without the intervention of the DSP. The DMA engine off-loads data move instructions from the DSP core, leaving more MIPS available for signal processing instructions.

CS470xx functionality is controlled by application codes that are stored in on-chip ROM or downloaded to the CS470xx from a host controller or external serial flash/EEPROM.

Users can develop applications using the DSP Composer™ tool to create the processing chain and then compile the image into a series of commands that are sent to the CS470xx through the SCP. The processing application can either load modules (post-processors) from the DSPs on-chip ROM, or custom firmware can be downloaded through the SCP.

The CS470xx is suitable for a variety of audio post-processing applications where sound quality via sound enhancement and speaker/cabinet tuning is required to achieve the sound quality consumers expect. Examples of such applications include automotive head-ends, automotive amplifiers, docking stations, sound bars, subwoofers, and boom boxes.

The DSP core has its own on-chip data and program RAM and ROM and does not require external memory for post-processing applications.

The Y-RAM and P-RAM share a single block of memory that includes three 2K word blocks (32 bits/word) that are assignable to either Y-RAM or P-RAM as shown in Table 4.

Table 4-1. Memory Configurations for the C470xx

P-RAM X-RAM Y-RAM

14K words 10K words 8K words

12K words 10K words 10K words

10K words 10K words 12K words

8K words 10K words 14K words

4.2.1

DMA Controller

The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter:

X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service intervals for each DMA channel, as well as up to 6 interrupt events, are programmable.

4.3 On-chip DSP Peripherals

4.3.1

Analog to Digital Converter Port (ADC)

The ADCs in the CS470xx devices feature dynamic range performance in excess of 100 dB. See

Section 5.16

for more details on CS470xx ADC performance. The CS47024 and CS47028 devices support up to 2 simultaneous channels of analog-to-digital conversion with the input source selectable using an integrated 5:1 stereo analog mux (analog inputs

AIN_2A/B through AIN_6A/B). The CS47048 device adds a second pair of ADCs that are directly connected to input pins

AIN_1A/B providing a total of 4 simultaneous channels of analog-to-digital conversion. This feature gives the CS47048 the ability to select from a total of six stereo pairs of analog input. A single programmable bit selects single-ended or differential mode signals for all inputs. The conversions are performed with Fs=96 kHz.

9 DS787PP9

4.3 On-chip DSP Peripherals

4.3.2

Digital to Analog Converter Port (DAC)

The DACs in the CS470xx devices feature dynamic range performance in excess of 100 dB. See

Section 5.17

for more details on CS470xx DAC performance. The CS47024 device supports four simultaneous channels of digital-to-analog conversion. The CS47028 and CS47048 devices provide eight simultaneous channels of digital-to-analog conversion. The

DACs have voltage mode outputs that can be connected either as single-ended or differential signals. The conversions are performed with Fs=96 kHz.

4.3.3

Digital Audio Input Port (DAI)

The input capabilities for each version of the CS470xx are summarized in Table 3-1 and Table 3-2

.

Up to five DAI ports are available. Two of the DAI ports can be programmed to implement other functions. If the SPI mode is used, the DAI_DATA4 pin becomes the SCP_CS input. The integrated S/PDIF receiver can be used to take over the

DAI_DATA3 pin.

The DAI port PCM inputs have a single slave-only clock domain. The S/PDIF receiver, if used, is a separate clock domain.

The output of the S/PDIF Rx can then be converted through one of the internal SRC blocks to synchronize with the PCM input. The sample rate of the input clock domains can be determined automatically by the DSP, off-loading the task of monitoring the S/PDIF Rx from the host. A time-stamping feature provides the ability to also sample-rate convert the input data via software.The DAI port supports PCM format with word lengths up to 32 bits and sample rates as high as 192 kHz.

The DAI also supports a time division multiplexed (TDM) mode that packs up to 10 PCM audio channels on a single data line.

4.3.4

S/PDIF RX Input Port (DAI)

One of the PCM pins of the DAI can also be used as a DC-coupled, TTL-level S/PDIF Rx input capable of receiving and demodulating bi-phase encoded S/PDIF signals with Fs < 192 kHz.

4.3.5

Digital Audio Output Port (DAO)

DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a clock slave if an external MCLK or SCLK/

LRCLK source is available.

The DAO also supports a time division multiplexed (TDM) mode, that packs up to 8 channels of PCM audio on a single data line.

4.3.6

S/PDIF TX Output Port (DAO)

Two of the serial audio pins can be re-configured as S/PDIF TX pins that drive a bi-phase encoded S/PDIF signal (data with embedded clock on a single line).

4.3.7

Sample Rate Converters (SRC)

All CS470xx devices have at least two internal hardware SRC modules. One is directly associated with the ADCs and normally serves to convert data from the 96 kHz sampling rate of the ADCs to another Fs appropriate for mixing with other audio in the system.

The other SRC module is directly associated with the DACs and normally serves to convert data from the DSP into the 96 kHz sample rate needed by the DACs.

The CS47024, CS47028, and CS47048 devices have an additional stand-alone 8-channel SRC module. This SRC module can be used to make independent input clock domains synchronous (different Fs on PCM input and S/PDIF Rx).

DS787PP9 10

4.4 DSP I/O Description

4.3.8

Serial Control Port (I

2

C or SPI)

The on-chip serial control port is capable of operating as master or slave in either SPI or I2C modes. Master/Slave operation is chosen by mode select pins when the CS470xx comes out of reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock speed must always be < (DSP Core Frequency/2)). The CS470xx serial control port also includes a pin for flow control of the communications interface (SCP_BSY) and a pin to indicate when the DSP has a message for the host (SCP_IRQ).

4.3.9

GPIO

Many of the CS470xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high.

4.3.10

PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency, which is used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS470xx defaults to running from the external reference frequency and is switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external flash or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.

4.3.11

Hardware Watchdog Timer

The CS470xx has an integrated watchdog timer that acts as a “health” monitor for the DSP. The watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS470xx resets itself in the event of a temporary system failure. In stand-alone mode (where there is no host MCU), the DSP reboots from external flash. In slave mode (where the host MCU is present), a GPIO is used to signal the host that the watchdog has expired and the DSP should be rebooted and re-configured.

4.4 DSP I/O Description

4.4.1

Multiplexed Pins

Many of the CS470xx pins are multifunctional. For details on pin functionality, see Section 10.5, “Pin Assignments”, in the

CS470xx Hardware User’s Manual

.

4.4.2

Termination Requirements

Open-drain pins on the CS470xx must be pulled high for proper operation. See the CS470xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation.

Mode select pins on CS470xx are used to select the boot mode on the rising edge from reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS470xx Hardware User’s Manual.

4.4.3

Pads

The CS470xx Digital I/Os operate from the 3.3 V supply and are 5 V tolerant.

4.5 Application Code Security

The external program code can be encrypted by the programmer to protect any intellectual property it contains. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. Contact your local

Cirrus representative for details.

11 DS787PP9

5 Characteristics and Specifications

5 Characteristics and Specifications

Note:

All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature.

All data sheet typical parameters are measured under the following conditions: T = 25°C, VDD = 1.8 V, VDDIO =

VDDA = 3.3 V, GND = GNDIO = GNDA = 0 V.

5.1 Absolute Maximum Ratings

(GND = GNDIO = GNDA = 0V; all voltages with respect to 0V)

Parameter Symbol Min Max Unit

DC power supplies:

Core supply

Analog supply

I/O supply

|VDDA–VDDIO|

VDD

VDDA

VDDIO

Input pin current, any pin except supplies I in

Input voltage on PLL_REF_RES V filt

Input voltage on digital I/O pins V inio

Analog Input Voltage

Storage temperature

V in

T stg

–0.3

–0.3

–0.3

–0.3

–0.3

2.0

3.6

3.6

0.3

±10 mA

3.6

5.0

V

V

V

V

V

V

AGND–0.7 VA+0.7

V

–65 150 °C

WARNING:

Operation at or beyond these limits can result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

(GND = GNDIO = GNDA = 0V; all voltages with respect to 0V)

Parameter Symbol Min Typ Max Unit

DC power supplies:

Core supply

Analog supply

I/O supply

|VDDA – VDDIO|

Ambient operating temperature

Commercial—CQZ (147 MHz)

Automotive—DQZ (131 MHz)

Automotive—DQZ (113 MHz)

VDD

VDDA

VDDIO

T

A

1.71

3.13

3.13

0

–40

–40

1.8

3.3

3.3

0

1.89

3.46

3.46

— +70

+85

+105

°C

V

V

V

V

Note:

It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.

(Measurements performed under static conditions.)

Parameter Symbol

High-level input voltage

Input leakage current (all digital pins with internal pull-up resistors enabled)

V

IH

Low-level input voltage, except XTI

Low-level input voltage, XTI

Input Hysteresis

V

IL

V

ILKXTI

V hys

High-level output voltage (I

O

= –2mA), except XTO V

OH

Low-level output voltage (I

O

= 2mA), except XTO

Input leakage XTI

V

OL

I

LXTI

I

LEAK

Min Typ Max Unit

2.0

— 0.4

VDDIO*0.9 —

0.8

0.6

— VDDIO*0.1

V

5

70

μ

A

μ

A

V

V

V

V

V

DS787PP9 12

5.4 Power Supply Characteristics

5.4 Power Supply Characteristics

Note:

Measurements performed under operating conditions

Parameter

Operational Power Supply Current:

VDD: Core and I/O operating 1

VDDA: PLL operating current

VDDA: DAC operating current (all 8 channels enabled)

VDDA: ADC operating current (all 4 channels enabled)

VDDIO: With most ports operating

Min Typ Max Unit

325

16

56

34

27

Total Operational Power Dissipation: 1025

Standby Power Supply Current:

VDD: Core and I/O not clocked

VDDA: PLLs halted

VDDA: DAC disabled

VDDA: ADC disabled

VDDIO: All connected I/O pins 3-stated by other ICs in system

Total Standby Power Dissipation:

1. Dependent on application firmware and DSP clock speed.

410

26

40

24

215

1745

μA

μA

μA

μA

μA

μW mA mA mA mA mA mW

5.5 Thermal Data (100-pin LQFP with Exposed Pad)

Parameter

Thermal Resistance (Junction to Ambient)

Two-layer Board 1

Four-layer Board 2

Thermal Resistance (Junction to Top of Package)

Two-layer Board 1

Four-layer Board 2

Symbol Min Typ Max Unit

 ja

°C/Watt

34

18

 jt

°C/Watt

0.54

.28

1. To calculate the die temperature for a given power dissipation:

 j

= Ambient temperature + [ (Power Dissipation in Watts) *

 ja

]

2. To calculate the case temperature for a given power dissipation:

 c

=

 j

- [ (Power Dissipation in Watts) *

 jt

]

Note:

Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% of the top and bottom layers.

Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% of the top and bottom layers and 0.5-oz. copper covering 90% of the internal power plane and ground plane layers.

Parameter Symbol Min Max Unit

RESET minimum pulse width low 1 T rstl

All bidirectional pins high-Z after RESET low T rst2z

Configuration pins setup before RESET high T rstsu

1 —

 s

— 200 ns

50 — ns

Configuration pins hold after RESET high T rsthld

20 — ns

1. The rising edge of RESET must not occur before the power supplies are stable at the recommended operating values as described in

Section 5.2

. In

addition, for the configuration pins to be read correctly, the RESET T rstl

requirement must be met.

13 DS787PP9

VDD

1

RESET

HS[3:0]

1

Refers to all power supplies.

All supplies at recommended operating values.

T rstl

T rstsu

T rsthld

5.7 Digital Switching Characteristics–XTI

Figure 5-1. RESET Timing at Power-on

RESET

HS[3:0]

All Bidirectional

Pins

T rstsu

T rsthld

T rst2z

T rstl

Figure 5-2. RESET Timing after Power is Stable

Parameter

External Crystal operating frequency

1

XTI period

XTI high time

XTI low time

External Crystal Load Capacitance (parallel resonant)

2

External Crystal Equivalent Series Resistance

Symbol Min Max Unit

F xtal

T clki

T clkih

T clkil

C

L

ESR

12.288 24.576 MHz

41 81 ns

13.3

13.3

— ns ns

10

18

50 pF

1. Part characterized with the following crystal frequency values: 12.288 and 24.576 MHz.

2. C

L refers to the total load capacitance as specified by the crystal manufacturer. Crystals that require a C

L

outside this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s recommendation for load capacitor selection.

XTI t clkih t clkil

T clki

Figure 5-3. XTI Timing

DS787PP9 14

5.8 Digital Switching Characteristics–Internal Clock

5.8 Digital Switching Characteristics–Internal Clock

Parameter

Internal DSP_CLK frequency

1

CS47048-CQZ

CS47048-DQZ

CS47028-CQZ

CS47028-DQZ

CS47024-CQZ

CS47024-DQZ

Internal DSP_CLK period 1

CS47048-CQZ

CS47048-DQZ

CS47028-CQZ

CS47028-DQZ

CS47024-CQZ

CS47024-DQZ

Symbol

F dclk

DCLKP

Min (2layer Boards)

6.8

7.6

6.8

7.6

6.8

7.6

Min (4layer Boards)

(See Footnote 2)

F

F xtal

F xtal

F xtal

F xtal

F xtal xtal

6.8

6.8

6.8

6.8

6.8

6.8

Max (2layer Boards)

147

131

147

131

147

131

1/F xtal

1/F xtal

1/F xtal

1/F xtal

1/F xtal

1/F xtal

Max (4layer Boards)

147

147

147

147

147

147

Unit

MHz ns

1. After initial power-on reset, F dclk

= F xtal

. After initial kick-start commands, the PLL is locked to max F dclk

and remains locked until the next power-on reset.

2. See Section 5.7

. for all references to F xtal

.

Parameter Symbol Min

SCP_CLK frequency

SCP_CS falling to SCP_CLK rising

SCP_CLK low time

SCP_CLK high time

1

Setup time SCP_MOSI input

Hold time SCP_MOSI input

SCP_CLK low to SCP_MISO output valid

SCP_CLK falling to SCP_IRQ rising f spisck t spicss t spickl t spickh t spidsu t spidh t spidov t spiirqh

SCP_CS rising to SCP_IRQ falling

SCP_CLK low to SCP_CS rising t spiirql t spicsh

SCP_CS rising to SCP_MISO output high-Z t spicsdz

SCP_CLK rising to SCP_BSY falling t spicbsyl

Typical Max Unit

20

5

5

24

20

0

24

20

— 3*DCLKP+20 —

27

11

25 MHz

— ns

— ns ns ns ns ns ns ns ns ns ns

1. f spisck

indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port can be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is F xtal

/3.

15 DS787PP9

5.10 Digital Switching Characteristics–Serial Control Port–SPI Master

t spicss

SCP_CS

0 1 2 t spickl

6 7 0 5 6 7 t spicsh

SCP_CLK

1/ f spisck t spickh

SCP_MOSI A6 t spidsu

A5 t spidh

A0 R/W MSB LSB t spidov t spicsdz

SCP_MISO

MSB LSB t spiirqh

SCP_IRQ t spibsyl

SCP_BSY

Figure 5-4. Serial Control Port–SPI Slave Mode Timing

5.10 Digital Switching Characteristics–Serial Control Port–SPI Master Mode

t spiirql

Parameter Symbol Min

SCP_CLK frequency 1,2

EE_CS falling to SCP_CLK rising

SCP_CLK low time

SCP_CLK high time

Setup time SCP_MISO input

Hold time SCP_MISO input

3 f spisck t spicss t spickl t spickh t spidsu t spidh

SCP_CLK low to SCP_MOSI output valid

SCP_CLK low to EE_CS falling

SCP_CLK low to EE_CS rising t spidov t spicsl t spicsh

Bus free time between active EE_CS t spicsx

SCP_CLK falling to SCP_MOSI output high-Z t spidz

Typical

— —

— 11*DCLKP+(SCP_CLK PERIOD)/2

18 —

18

9

5

7 —

— 11*DCLKP+(SCP_CLK PERIOD)/2

3*DCLKP

Max Units

F xtal

/2 MHz

— ns

— ns ns ns

8

20 ns ns ns ns ns ns

1. f spisck

indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port can be limited by the firmware application.

2. See Section 5.7.

3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter.

DS787PP9 16

t spicss

EE_CS

SCP_CLK t spicsl

1/ f spisck

0

SCP_MISO

1

A6 t spidsu

A5 t spidh

5.11 Digital Switching Characteristics–Serial Control Port I2C Slave Mode

t spicsx

2 t spickl

6 t spickh

A0 R/W MSB t spidov

7 0

5 6

7

LSB t spicsh t spidz

SCP_MOSI

MSB LSB

Figure 5-5. Serial Control Port–SPI Master Mode Timing

5.11 Digital Switching Characteristics–Serial Control Port I

2

C Slave Mode

Parameter Symbol Min Typical

SCP_CLK frequency

SCP_CLK rise time

SCP_CLK fall time

1

SCP_CLK low time

SCP_CLK high time t iicckh

SCP_CLK rising to SCP_SDA rising or falling for START or STOP condition t iicckcmd

START condition to SCP_CLK falling t iicstscl

SCP_CLK falling to STOP condition t iicckl t iicstp

Bus free time between STOP and START conditions f iicck t iicr t iicf

Setup time SCP_SDA input valid to SCP_CLK rising

Hold time SCP_SDA input after SCP_CLK falling

SCP_CLK low to SCP_SDA out valid t iicbft t iicsu t iich t iicdov

SCP_CLK falling to SCP_IRQ rising

NAK condition to SCP_IRQ low

SCP_CLK rising to SCB_BSY low t iicirqh t iicirql t iicbsyl

Max Units

1.25

1.25

1.25

1.25

2.5

3

110

100

— 3*DCLKP+20

— 3*DCLKP+20

400

150

150

18 ns

3*DCLKP+40 ns

— ns ns

µs

µs ns ns kHz ns ns

µs

µs

µs

µs

1. f iicck

indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port can be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer.

I

2

C Slave Address = 0x82

17 DS787PP9

SCP_CLK t iicckcmd

Start Condition

0 1 t iicckl

6

5.12 Digital Switching Characteristics–Serial Control Port–I2C Master

t iicr

7 8 t iicf

0 1 6 7 8 t iicckcmd

Stop Condition t iicstp

SCP_SDA t iicstscl

A6 t iicckh

A0 t iicdov

R/W ACK MSB

1/ f iicck

LSB

ACK t iicbft t iicirqh t iicirql t iicsu t iich

SCP_IRQ t iiccbsyl

SCP_BSY

Figure 5-6. Serial Control Port–I 2 C Slave Mode Timing

5.12 Digital Switching Characteristics–Serial Control Port–I

2

C Master Mode

Parameter Symbol Min Max Units

SCP_CLK frequency

SCP_CLK rise time

SCP_CLK fall time

SCP_CLK low time

SCP_CLK high time

1

Hold time SCP_SDA input after SCP_CLK falling

SCP_CLK low to SCP_SDA out valid f iicck t iicr t iicf t iicckl t iicckh

SCP_CLK rising to SCP_SDA rising or falling for START or STOP condition t iicckcmd

START condition to SCP_CLK falling t iicstscl

SCP_CLK falling to STOP condition t iicstp

Bus free time between STOP and START conditions t iicbft

Setup time SCP_SDA input valid to SCP_CLK rising t iicsu t iich t iicdov

— 400 kHz

— 150 ns

— 150 ns

1.25 — µs

1.25 —

1.25 —

1.25 —

2.5

µs

µs

µs

µs

3 —

110 —

100 —

— 36

µs ns ns ns

1. f iicck

indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port can be limited by the firmware application.

t iicckcmd t iicckl t iicr t iicf t iicckcmd

0 1 6 7 8 0 1 6 7 8

SCP_CLK t iicstscl t iicckh

1/ f iicck t iicstp t iicbft

SCP_SDA A6 A0 t iicdov

R/W ACK MSB

LSB

ACK t iicsu t iich

Figure 5-7. Serial Control Port–I

2

C Master Mode Timing

DS787PP9 18

5.13 Digital Switching Characteristics–Digital Audio Slave Input Port

5.13 Digital Switching Characteristics–Digital Audio Slave Input Port

Parameter Symbol Min Max Unit

DAI_SCLK period

DAI_SCLK duty cycle

T daiclkp

Setup time DAI_DATAn t daidsu

Hold time DAI_DATAn t daidh

8

5

20 — ns

45 55 %

— ns ns

DAI_SCLK t daidsu t daidh

DAI_DATAn

Figure 5-8. Digital Audio Input (DAI) Port Timing Diagram

5.14 Digital Switching Characteristics–Digital Audio Output Port

Parameter Symbol Min Max Unit

DAO_MCLK period

DAO_MCLK duty cycle

DAO_SCLK period for Master or Slave mode 1

DAO_SCLK duty cycle for Master or Slave mode 1

T daomclk

T daosclk

Master Mode (Output A1 Mode)

1,2

DAO_SCLK delay from DAO_MCLK rising edge, DAO MCLK as an input t daomsck

DAO_LRCLK to DAO_SCLK inactive edge 3 . See

Fig. 5-9

.

DAO_SCLK inactive edge 3 to DAO_LRCLK. See

Fig. 5-10

DAO_DATA[3:0] delay from DAO_SCLK inactive edge 3

.

t daomlrts t daomstlr t daomdy

Slave Mode (Output A0 Mode)

4

DAO_SCLK active edge to DAO_LRCLK transition. See

DAO_LRCLK transition to DAO_SCLK active edge. See

DAO_Dx delay from DAO_SCLK inactive edge

Fig. 5-11

Fig. 5-12

.

.

t daosstlr t daoslrts t daosdv

20 — ns

45 55 %

20 — ns

40 60 %

— 19 ns

— 8 ns

— 8

— 8 ns ns

10 — ns

10 — ns

— 11 ns

1. Master mode timing specifications are characterized, not production tested.

2. Master mode is defined as the CS47048 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_

LRCLK.

3. The DAO_LRCLK transition can occur on either side of the edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the data is valid.

4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

t daomclk

DAO_MCLK t daomsck

DAO_SCLK t daomlrts

DAO_LRCLK t daomdv

DAO_DATAn

Figure 5-9. DAO_LRCLK Transition before DAO_SCLK Inactive Edge

19 DS787PP9

DS787PP9

5.14 Digital Switching Characteristics–Digital Audio Output Port

t daomclk

DAO_MCLK t daomsck

DAO_SCLK t daomstlr

DAO_LRCLK t daomdv

DAO_DATAn

Figure 5-10. DAO_LRCLK Transition after DAO_SCLK Inactive Edge

DAO_LRCLK t daoslrts

DAO_SCLK t daosclk

DAO_Dx

Figure 5-11. DAO_LRCLK Transition before DAO_SCLK Inactive Edge

t daosclk

DAO_LRCLK

DAO_SCLK t daosstlr t daosdv

DAO_Dx

Figure 5-12. DAO_LRCLK Transition after DAO_SCLK Inactive Edge

20

5.15 Digital Switching Characteristics–S/PDIF RX Port

5.15 Digital Switching Characteristics–S/PDIF RX Port

(Inputs: Logic 0 = V

IL

, Logic 1 = V

IH

, C

L

= 20 pF)

Parameter

PLL Clock Recovery Sample Rate Range

Symbol Min Typ Max Units

— 30 — 200 kHz

5.16 ADC Characteristics

5.16.1

Analog Input Characteristics (Commercial)

Test Conditions (unless otherwise specified): T

A driven through the passive input filter (R i

Bandwidth is 10–20kHz.

= 0–+70°C; VDD = 1.8V±5%, VDDA (VA) = 3.3V±5%, 1kHz sine wave

= 10 k

) in

Fig. 5-13

or

Fig. 5-14 ; DSP running test application; Measurement

Differential Single-ended

Fs = 96 kHz

A-weighted

Unweighted

Parameter

Dynamic Range 1,6,7

40 kHz bandwidth unweighted

Min

99

96

Total Harmonic Distortion + Noise 6,7

–1 dB

–20 dB

–60 dB

40 kHz bandwidth –1 dB

AIN_1A/B Interchannel Isolation

10

AID_[2.6]A/B MUX Interchannel Isolation —

Typ

105

102

99

–98

–82

–42

–90

95

95

Max Min

–92

96

93

Typ

102

99

96

–95

–79

–39

–90

95

95

Max

–89

Unit

dB dB dB dB dB dB dB dB dB

DC Accuracy

Interchannel Gain Mismatch

Gain Drift

— 0.1

— — 0.1

— dB

±120

— —

±

120 — ppm/°C

Analog Input

Full-scale Input Voltage 2,3

Differential Input Impedance 4

Single-ended Input Impedance

5

Common Mode Rejection Ratio (CMRR) 8 —

Parasitic Load Capacitance (C

L

) 9 —

3.3 3.7

VA 3.9 1.65 1.85

VA 1.95

V

PP

— 400 — — — —

— — — — 200 —

60

— —

20 —

20 dB pF

1. dB units referred to the typical full-scale voltage.

2. These full-scale values were measured with R i

=10k for both the single-ended and differential mode input circuits.

3. The full-scale voltage can be changed by scaling R i

.

Differential Full-Scale (Vpp) = 3.7*VDDA*(Ri+200)/(10k+200)

Single-Ended Full-Scale (Vpp) = 1.85*VDDA*(Ri+200)/(10k+200)

4. Measured between AIN_xx+ and AN_xx–.

5. Measured between AIN_xx+ and AGND.

6. Decreasing full-scale voltage by reducing R i

causes the noise floor to increase.

7. Common mode input current should be kept to less than ±160uA to avoid performance degradation: |(I ip

+I for R i

=10 k

in the differential case.

in

)/2| < 160uA. This corresponds to ±1.6V

8. This number was measured using perfectly matched external resistors (R i

). Mismatch in the external resistors typically reduces CMRR by 20 log

(|

R i

|/R i

+ 0.001).

9. C

L

represents the parasitic load capacitance between R i

on the input circuit and the input pin of the CS47048 package.

10. This measurement is not applicable to the CS47028 and CS47024 devices.

21 DS787PP9

5.16 ADC Characteristics

5.16.2

Analog Input Characteristics (Automotive)

Test Conditions (unless otherwise specified): TA = –40–85°C; VDD = 1.8V±5%, VDDA (VA) = 3.3V±5%; kHz sine wave driven through the passive input filter (R i

Bandwidth is 10 Hz–20 kHz.

= 10 k

) in

Fig. 5-13

or

Fig. 5-14 ; DSP running test application; Measurement

Differential Single-ended

Parameter

Fs = 96 kHz

Dynamic Range

1,6,7

A-weighted

Unweighted

40 kHz bandwidth unweighted

Min

97

94

Total Harmonic Distortion + Noise

6,7

–1 dB

–20 dB

–60 dB

40 kHz bandwidth –1 dB

AIN_1A/B Interchannel Isolation 10 —

AID_[2.6]A/B MUX Interchannel Isolation —

Typ

105

102

99

–98

–82

–42

–90

95

95

Max Min

–90

94

91

Typ

102

99

96

–95

–79

–39

–90

95

95

Max

–87

Unit

dB dB dB dB dB dB dB dB dB

DC Accuracy

Interchannel Gain Mismatch

Gain Drift

— 0.1

— —

— ±120 — —

0.1

— dB

±

120 — ppm/°C

Analog Input

Full-scale Input Voltage 2,3

Differential Input Impedance

4

Single-ended Input Impedance 5

3.3 3.7

VA 3.9 1.65 1.85

VA 1.95

V

PP

— 400 — — — —

Common Mode Rejection Ratio (CMRR) 8 —

60

— —

— —

200

 dB

Parasitic Load Capacitance (C

L

) 9 — — 20 — — 20 pF

1. dB units referred to the typical full-scale voltage.

2. These full-scale values were measured with R i

=10k for both the single-ended and differential mode input circuits.

3. The full-scale voltage can be changed by scaling R i

.

Differential Full-Scale (Vpp) = 3.7*VDDA*(Ri+200)/(10k+200)

Single-Ended Full-Scale (Vpp) = 1.85*VDDA*(Ri+200)/(10k+200)

4. Measured between AIN_xx+ and AN_xx–.

5. Measured between AIN_xx+ and AGND.

6. Decreasing full-scale voltage by reducing R i

causes the noise floor to increase.

7. Common mode input current should be kept to less than ±160uA to avoid performance degradation: |(I ip

+I for R i

=10 k

in the differential case.

in

)/2| < 160uA. This corresponds to ±1.6V

8. This number was measured using perfectly matched external resistors (R i

). Mismatch in the external resistors typically reduces CMRR by 20 log

(|

R i

|/R i

+ 0.001).

9. C

L

represents the parasitic load capacitance between R i

on the input circuit and the input pin of the CS47048 package.

10. This measurement is not applicable to the CS47028 and CS47024 devices.

AIN

100K

10µF

+

R i

C

L

AIN_xA+ or

AIN_xB+

Figure 5-13. ADC Single-ended Input Test Circuit

DS787PP9 22

5.17 DAC Characteristics

AIN-

AIN+

10µF

+

100K

R i

10µF

+

100K

R i

C

L

AIN_xAor

AIN_xB-

C

L

AIN_xA+ or

AIN_xB+

Figure 5-14. ADC Differential Input Test Circuit

5.16.3

ADC Digital Filter Characteristics

Parameter 1,2

Min Typ Max Unit

Fs = 96 kHz

Passband (Frequency Response) to –0.1 dB corner

Passband Ripple

Stopband

Stopband Attenuation

Total Group Delay

0

0.5688

0.4896 Fs

0.08

— dB

Fs

70

— —

12/Fs — dB s

High-pass Filter Characteristics

Frequency Response:

–3.0 dB

–0.13 dB

Phase Deviation @ 20 Hz

Passband Ripple

Filter Settling Time

1

20

10

0

— 10

5

/Fs 0

Hz

Hz

Deg dB s

1. Filter response is guaranteed by design.

2. Response is clock-dependent and scales with Fs.

5.17 DAC Characteristics

5.17.1

Analog Output Characteristics (Commercial)

Test Conditions (unless otherwise specified): TA = 0–+70°C; VDD = 1.8V±5%, VDDA(VA) = 3.3V±5%; 1 kHz sine wave

driven through a filter shown in Fig. 5-15

or

Fig. 5-16 ; DSP running test application; Measurement Bandwidth is 20 Hz–20

kHz.

Parameter

Fs = 96 kHz

Dynamic Range

A-weighted

Unweighted

Total Harmonic Distortion + Noise

0 dB

–20 dB

–60 dB

Interchannel Isolation (1 kHz)

Differential Single-ended

Min Typ Max Min Typ Max Unit

102

99

108

105

–98

–88

–48

95

99

96

–90

— —

105

102

–95

–85

–45

95

–87

— dB dB dB dB dB dB

23 DS787PP9

5.17 DAC Characteristics

Parameter

Differential Single-ended

Min Typ Max Min Typ Max Unit

Analog Input

Full-scale Output

Interchannel Gain Mismatch

Gain Drift

Output Impedance

AC-load Resistance (R

L

) 2

Load Capacitance (C

L

) 2

1.20 1.40

VA 1.60 0.60 0.70

VA 0.80

V

PP

— 0.1

— — 0.1

— dB

DC Current Draw from an AOUT Pin 1 —

3

±

120 — —

±

120 — ppm/°C

100 — — 100 —

— 10 — — 10

A

— — 3 — — k

— 100 — — 100 pF

5.17.2

Analog Output Characteristics (Automotive)

Test Conditions (unless otherwise specified): T

A

= –40 to +85

C; VDD = 1.8V±5%, VDDA(VA) = 3.3V±5%; 1 kHz sine wave driven through a filter shown in

Fig. 5-15 or

Fig. 5-16 ; DSP running test application; Measurement Bandwidth is

20 Hz–20 kHz.

Differential Single-ended

Parameter Min Typ Max Min Typ Max Unit

Fs = 96 kHz

Dynamic Range

A-weighted

Unweighted

Total Harmonic Distortion + Noise

0 dB

–20 dB

–60 dB

Interchannel Isolation (1 kHz)

100

97

108

105

–98

–88

–48

95

97

94

–90

— —

105

102

–95

–85

–45

95

–87

— dB dB dB dB dB dB

Analog Input

Full-scale Output

Interchannel Gain Mismatch

Gain Drift

Output Impedance

DC Current Draw from an AOUT Pin

1

AC-load Resistance (R

L

) 2

Load Capacitance (C

L

) 2

1.20 1.40

VA 1.60 0.60 0.70

VA 0.80

V

PP

— 0.1

— — 0.1

— dB

3

±

120 — —

±

120 — ppm/°C

100 — — 100 —

10 —

— 3

10

A k

— — 100 — — 100 pF

1. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic

DC-blocking capacitors.

2. Guaranteed by design. R

L

and C

L

reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp’s stability and signal integrity. In this circuit topology, C

L represents any capacitive loading that appears before the 560

 series resistor (typically parasitic), and effectively moves the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the internal op-amp to become unstable.

AOUT_x+

3.3 µF

+

560

AOUT

C

L

R

L

10 k

2200 pF

Figure 5-15. DAC Single-ended Output Test Circuit

DS787PP9 24

AOUT_x-

AOUT_x+

1800 pF

4.87 k

470 pF

4.87 k

1.96 k

C

L

C

L

2.43 k

953

4700 pF

+

22 µF

1200 pF

-

+

560

22 µF

10 k

5.17 DAC Characteristics

AOUT

125

P output: R

L

= 1.96k + ( [2

F*4700pF]

-1

|| (1.96k + [2

F*22µF

-

]

-1

) || (953 + [2

F*1200pF ]

-1

))

N output: R

L

= 4.87k + ( [2

F*1800pF]

-1

|| ((2.43k + [2

F*470pF]

-1

) || 4.87k ))

Figure 5-16. DAC Differential Output Test Circuit

100

75

50

25

Safe Operating

Region

2.5

3

5 10 15

Resistive Load -- R (k

)

Figure 5-17. Maximum Loading

5.17.3

Combined DAC Interpolation and On-chip Analog Filter Response

20

Parameter Min Typ Max Unit

Passband (Frequency Response) to 0.22 dB corner to –3 dB corner

0

0

0.4125

0.4979

Fs

Fs

Frequency Response 10 Hz–20 kHz –0.02

— +0.02

dB

StopBand 0.5465

— — Fs

StopBand Attenuation

Group Delay

100 — —

— 10/Fs — dB s

25 DS787PP9

6 Ordering Information

The CS470xx DSP part numbers are described as follows:

Example:

CS47048I-XYZR where

I–ROM ID Letter

X–Product Grade

Y–Package Type

Z–Lead (Pb) Free

R–Tape and Reel Packaging

Table 6-1. Ordering Information

Part No.

Grade Temp. Range Package

CS47048C-CQZ Commercial

CS47048C-DQZ Automotive

0–+70°C

–40–+85°C

CS47048C-EQZ Extended Automotive –40–+105°C

CS47028C-CQZ Commercial 0–+70°C

CS47028C-DQZ Automotive –40–+85°C

CS47028C-EQZ Extended Automotive –40–+105°C

CS47024C-CQZ Commercial

CS47024C-DQZ Automotive

0–+70°C

–40–+85°C

CS47024C-EQZ Extended Automotive –40–+105°C

100-pin LQFP

Note:

Contact the factory for availability of the –D (automotive grade) package.

7 Environmental, Manufacturing, and Handling Information

Table 7-1. Environmental, Manufacturing, and Handling Information

Model Number Peak Reflow Temp. MSL

1

Rating Max Floor Life

CS47048C-CQZ 260° C

CS47048C-DQZ

CS47048C-EQZ

CS47028C-CQZ 260° C

CS47028C-DQZ

CS47028C-EQZ

CS47024C-CQZ 260° C

CS47024C-DQZ

CS47024C-EQZ

3

3

3

7 days

7 days

7 days

1. Moisture Sensitivity Level as specified by IPC/JEDEC J-STD-020.

6 Ordering Information

26 DS787PP9

8 Device Pinout Diagrams

8 Device Pinout Diagrams

DBCK

DBDA

GPIO15, DAI_LRCLK

GPIO17, DAI_SCLK

VDDIO1

GNDIO1

GPIO16, DAI_DATA0, TM0

GPIO0, DAI_DATA1, TM1

GPIO1, DAI_DATA2, TM2

GPIO2, DAI_DATA3, TM3, SPDIF RX

VDD1

GND1

GPIO7, DAO_LRCLK

GPIO14, DAO_SCLK

GNDIO2

VDDIO2

GPIO18, DAO_MCLK, HS4

GPIO6, DAO_DATA0, HS0

GPIO3, DAO_DATA1, HS1

GPIO4, DAO_DATA2, HS2, S/PDIF TXb

GPIO5, DAO_DATA3, HS3, S/PDIF TXa

VDD2

GND2

GPIO9, SCP_MOSI

GPIO10, SCP_MISO, SCP_SDA

1

5

10

15

20

25

CS47048

100-Pin LQFP

(Thermal Pad Package )

75

VDD_DAC

GND_DAC

VDD_ADC_MON

REXT

VQ

70

BIASREF_DAC

GNDA3

AIN_1A+

AIN_1A-

65

AIN_1B+

AIN_1B-

VDDA3

BIASREF_ADC

VDDA2

GNDA2

60

AIN_2A+

AIN_2A-

55

AIN_3A+

AIN_3A-

AIN_4A+

AIN_4A-

AIN_5A+

AIN_5A-

AIN_6A+

51

AIN_6A-

Figure 8-1. CS47048 Pinout Diagram

27 DS787PP9

28

DBCK

DBDA

GPIO15, DAI_LRCLK

GPIO17, DAI_SCLK

VDDIO1

GNDIO1

GPIO16, DAI_DATA0, TM0

GPIO0, DAI_DATA1, TM1

GPIO1, DAI_DATA2, TM2

GPIO2, DAI_DATA3, TM3, SPDIF RX

VDD1

GND1

GPIO7, DAO_LRCLK

GPIO14, DAO_SCLK

GNDIO2

VDDIO2

GPIO18, DAO_MCLK, HS4

GPIO6, DAO_DATA0, HS0

GPIO3, DAO_DATA1, HS1

GPIO4, DAO_DATA2, HS2, S/PDIF TXb

GPIO5, DAO_DATA3, HS3, S/PDIF TXa

VDD2

GND2

GPIO9, SCP_MOSI

GPIO10, SCP_MISO, SCP_SDA

1

5

10

15

20

25

8.2 CS47028, 100-pin LQFP Pinout Diagram

CS47028

100-Pin LQFP

(Thermal Pad Package )

75

VDD_DAC

70

GND_DAC

VDD_ADC_MON

REXT

VQ

BIASREF_DAC

GNDA3

65

60

NC

NC

NC

NC

VDDA3

BIASREF_ADC

VDDA2

GNDA2

AIN_2A+

AIN_2A-

55

AIN_3A+

AIN_3A-

AIN_4A+

AIN_4A-

51

AIN_5A+

AIN_5A-

AIN_6A+

AIN_6A-

Figure 8-2. CS47028 Pinout Diagram

DS787PP9

29

DBCK

DBDA

GPIO15, DAI_LRCLK

GPIO17, DAI_SCLK

VDDIO1

GNDIO1

GPIO16, DAI_DATA0, TM0

GPIO0, DAI_DATA1, TM1

GPIO1, DAI_DATA2, TM2

GPIO2, DAI_DATA3, TM3, SPDIF RX

VDD1

GND1

GPIO7, DAO_LRCLK

GPIO14, DAO_SCLK

GNDIO2

VDDIO2

GPIO18, DAO_MCLK, HS4

GPIO6, DAO_DATA0, HS0

GPIO3, DAO_DATA1, HS1

GPIO4, DAO_DATA2, HS2, S/PDIF TXb

GPIO5, DAO_DATA3, HS3, S/PDIF TXa

VDD2

GND2

GPIO9, SCP_MOSI

GPIO10, SCP_MISO, SCP_SDA

1

5

10

15

20

25

8.3 CS47024, 100-pin LQFP Pinout Diagram

CS47024

100-Pin LQFP

(Thermal Pad Package )

75

VDD_DAC

70

GND_DAC

VDD_ADC_MON

REXT

VQ

BIASREF_DAC

GNDA3

65

60

NC

NC

NC

NC

VDDA3

BIASREF_ADC

VDDA2

GNDA2

AIN_2A+

AIN_2A-

55

AIN_3A+

AIN_3A-

AIN_4A+

AIN_4A-

51

AIN_5A+

AIN_5A-

AIN_6A+

AIN_6A-

Figure 8-3. CS47024 Pinout Diagram

DS787PP9

9 100-pin LQFP with Exposed Pad Package Drawing

Fig. 9-1 shows the 100-pin LQFP package with exposed pad for the CS47048, CS47028, and CS47024.

Figure 9-1. 100-pin LQFP Package Drawing

10 Parameter Definitions

10 Parameter Definitions

10.1 Dynamic Range

The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth.

Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ

CP-307. Expressed in decibels.

10.2 Total Harmonic Distortion + Noise

The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth

(typically 10 Hz–20 kHz), including distortion components. Expressed in decibels. Measured at –1 and –20 dBFS as suggested in AES17-1991 Annex A.

10.3 Frequency Response

A measure of the amplitude response variation from 10 Hz–20 kHz relative to the amplitude response at 1 kHz. Units in decibels.

10.4 Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.

10.5 Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

10.6 Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

10.7 Gain Drift

The change in gain value with temperature. Units in ppm/°C.

31 DS787PP9

11 Revision History

11 Revision History

Revision

PP1

PP2

PP3

PP4

PP5

PP6

PP7

PP8

PP9

Date Changes

August, 2009 Updated Characterization data in

Section 5.4

,

Section 5.7

,

Section 5.9

,

Section 5.11

,

Section 5.12

,

Section 5.16.1

,

Section 5.16.2

, Section 5.16.3

, Section 5.17.1

, and Section 5.17.2

. Modified Footnote 3 in

both

Section 5.16.1

and Section 5.16.2

. Added Footnote 5 to

Section 5.14

. Updated

Section 2.1

. Modified

Section 4.3.6

and

Section 4.3.8

. Modified references to TDM in various sections of the data sheet.

January, 2010

June, 2010

Updated TDM Feature description on page 1. Modified note at the bottom of the feature list on page 1.

Updated table in

Section 5.8

, specifying performance data for 2- and 4-layer boards. Updated

Table 3-1

and

Table 3-2 Updated block diagrams in

Fig. 4-1 ,

Fig. 4-2 , and Fig. 4-3

.

Table 3-1 : Straddled all three columns in the “Supports Different Fs Sample Rates” row to indicate that

CS47024 devices have the same features as the CS47048 and CS47028.

Added “The CS47024 has the 8-channel SRC block” to Section 4.3.7

.

Added text in the following places to indicate that the CS47024 implements the S/PDIF Rx functionality:

• Removed dagger from the S/PDIF Rx bullet on p. 1.

• Updated bullet in “Configurable Serial Audio Inputs/Outputs” row in Table 2 Integrated 192 kHz S/PDIF

Rx, 2 Integrated 192 kHz S/PDIF Tx.

• Changed entry in “S/PDIF In (Stereo Pairs)” column in Table 3-2 .

• Updated I2S block in

Table 3-2

.

• Removed text “On the CS47048 and CS47028...” from

Section 4.3.4

.

• Removed “(Not available on CS47024)” from the heading to

Section 5.15

.

• Described additional support for TDM 8-channel output mode on CS47024.

• Removed dagger from the TDM I/O bullet on p. 1.

• Straddled “Configurable Serial Audio Inputs/Outputs” row in Table 3-1 .

• Changed cell in “TDM Out” column in

Table 3-2

.

• Removed text “On the CS47048 and CS47028...” from

Section 4.3.5

.

February, 2011 Added “Decoder” information to

Section 3 . Changed the name of the core to “Cirrus Logic 32-bit core”.

February, 2011 Added “SPDIF RX” to

Fig. 5-17 .

June, 2011

In Section 4.3.1

and Section 4.3.7

, removed mention of 192 kHz sampling frequency. Updated temperature

operating conditions in Section 5.2

. Updated pin 33 to XTAL_OUT, TEST in Fig. 8-1

, Fig. 8-2 , and

Fig. 8-3 .

April, 2012

Corrected peak reflow temperature in Table 7-1 .

June, 2012

July, 2012

Added number of bits to Integrated DAC and ADC Functionality on the cover page.

Updated frequencies in

Section 5.2

. Added extended automotive grade information to Section 6

and

Section 7

.

DS787PP9 32

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