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Zynq-7000

All Programmable SoC

ZC702 Base

Targeted Reference Design

(Vivado Design Suite 2013.2)

User Guide

UG925 (v5.0) October 14, 2013

Notice of Disclaimer

The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES

AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,

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(including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm

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© Copyright 2012–2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight,

Cortex, and PrimeCell are trademarks of ARM in the EU and other countries. PCI Express is a trademark of PCI-SIG and used under license.

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Zynq-7000 AP SoC ZC702 Base TRD

UG925 (v5.0) October 14, 2013 www.xilinx.com

2

Revision History

The following table shows the revision history for this document.

Date

06/21/2012

10/08/2012

Version

1.0

2.0

Revision

Initial Xilinx release.

Updated for ISE® Design Suite 14.2.

Replaced AXI VTC with VTC throughout. Changed Sobel engine to Sobel filter.

Chapter 1, Introduction : Added R, RW, COR, SoC, and SC to

Table 1-1 . Expanded

descriptions of the TRD. Updated the block diagram in

Figure 1-1

.

Chapter 2, Functional Description : In

Figure 2-1

, replaced the continuous line with a dotted line for Monitor and between VIDEO_MUX0 and Clk_detect and revised AXI Interconnect inputs. Added slice registers to

Table 2-1 . In Table 2-2

, changed SOBEL_ENGINE to FILTER_VDMA and FILTER_ENGINE. Added

FILTER_0_interrupt row in

Table 2-3 , and SOBEL_VDMA changed to

FILTER_VDMA. In

Table 2-4 , GPIO bit number 7 became N/A. In

PL Clocks, page 19

, (FCLKCLK[3:0]) became (FCLK_CLK). In

PL Reset, page 19

,

(FCLKRESETN[3:0]) became FCLK_RESET[3:0]_N and FCLKRESETN[0] changed to

FCLK_RESET0_N. In

Clocking, page 19 , PS FCLKCLK[0] changed to PS FCLK_CLK0.

In

Table 2-5 , clock signal sources and uses were updated. In

Table 2-9 , added

xFilter, changed frequency and connection of s_axi_CONTROL_BUS_ACLK and deleted s_axi_SOBEL_CONTROL_ACLK. Changed frequency of

INTERCONNECT_ACLK bus. Changed SOBEL_ENGINE to FILTER_ENGINE and

SOBEL_VDMA to FILTER_VDMA. Added information to the end of the table for

DVI2AXI_0, CRESAMPLE_0, and YUV2RGB_0 components. In

Processor System

Reset Module, page 22

, input to the proc_sys_reset core is generated by PS

Proc_sys_reset_1_N. In Clock Detect, page 23 , FMC changed to FMC-IMAGEON.

The v_cresample, v_ycrcb2rgb, vsrc_sel, sobel_filter_top, and dvi2axi sections were added. Starting in

fmc imageon hdmi in, page 25 , YCbCr was changed to

YCrCb. In

Figure 2-4 , added xFilter to the Device Drivers. In the Boot Loader

section, removed "HDMI in" chip. In xFilter, page 30 , updated the introductory text for clarity and reformatted the IOTCL arguments. Modified the description of Figure 2-6

for clarity. Modified the descriptions of Figure 2-8 and Figure 2-9

for clarity and added description of cases 4, 5, and 6. Modified

Software Sobel

Filter Processing, page 45

for clarity. Added xFilter sections to

Xilinx Linux Kernel, page 34

. Figure 2-4, GUI for TRD Application was replaced and notes about the

GUI were added. AXI was added to the Plot Graph descriptions. DDR3 was removed from

Figure 2-8 and Figure 2-9 . The

Software Sobel Filter Processing, page 45

description and API changed.

Appendix A, Register Description

: New sections were added from

Sobel Filter

Registers, page 46

to the end of the appendix. Removed redundant instances of

TPG.

Appendix C, Directory Structure : Figure C-1

, Directory Structure, was updated.

Appendix F, Additional Resources : PG012, LogiCORE IP Chroma Resampler

Product Guide and PG014, LogiCORE IP YCrCb to RGB Color-Space Converter

Product Guide were added to references.

Appendix G, Regulatory and Compliance Information was added.

Appendix H, Warranty

was added.

Zynq-7000 AP SoC ZC702 Base TRD

UG925 (v5.0) October 14, 2013 www.xilinx.com

3

Date

11/12/2012

11/19/2012

01/31/2013

Version

2.1

2.1.1

3.0

Revision

Updated for ISE® Design Suite 14.3.

Chapter 1, Introduction

: Document and web site references changed throughout the book. In

Base TRD Key Features, page 11

, 1 GB DDR3 running at 533 MHz was removed.

Chapter 2, Functional Description :

Figure 2-1

line colors changed.

Table 2-1 cell

values changed.

Table 2-2

Peripheral names changed. Under

Clocking, page 19

,

RGB2YUV block was removed. In

Table 2-6

, the processor is ps7_0, and

PERF_MON_HP0, PERF_MON_HP2, VTC_0, and DVI2AXI_0 sections changed. The

dvi2axi Converter heading changed to dvi2axi on page 25. Figure 2-6 was replaced and a GUI explanation added. Figure 2-7 was added to show minimized

GUI mode. In section

Graphical User Interface, page 41 , the File Browser and

Command Line Shell paragraphs were removed. The directory structure changed in

Figure C-1 .

Appendix F, Additional Resources : Appendix was reorganized. A link was added

for the Master Answer Record for the ZC702 board.

Appendix G, Regulatory and Compliance Information : A Declaration of

Conformity link was added.

Made typographical edits.

Updated for ISE® Design Suite 14.4.

Chapter 2, Functional Description :

Figure 2-1

was changed in the Performance

Monitor and TPG_0 areas.

Table 2-1 changed Used 19,052 to 19,805, 42 to 43,

23,881 to 24,094, and % of Used 35 to 37.

Table 2-2

, deleted PERF_MON_HP2 row and renamed next row to PERF_MON_HP2_HP0_HP2.

APU, page 17

, end of

Cortex-A9 Core section added “For this TRD, both ARM cores run at 667 MHz.”

Table 2-6 , PERF_MON_HP0 changed to PERF_MON_HP0_HP2. In that same

section added new row SLOT_1_AXI_ACLK 150 0 Yes clk_150mhz and removed

PERF_MON_HP2 section. In TPG_0 section, changed clk to aclk, 148 to 150, video_clk_int to clk_150mhz, S_AXI_ACLK to s_axi_aclk, and DVI2AXI_0 section to

VID_IN_AXI4S. Reset Module changed to

Processor System Reset Module, page 22

. AXI VDMA Video Direct Memory Access, page 21 changed to

AXI Video

Direct Memory Access

. Heading VTC on page 22 changed to

Video Timing

Controller . In the same section, VTC IP in last paragraph changed to “Video

Timing Controller IP.” Added final sentence in that section “For detailed information on ...”. The TPG section changed to

Test Pattern Generator, page 24 .

Section

logiCVC-ML, page 25

was added. In

AXI Performance Monitor, page 25

added the final sentence, “For more information...” In

Chroma Resampler, page 26

edited the last sentence and added “and licensing information ...”

AXI

Performance Monitor, page 25

changed Instance: PERF_MON_HP0_HP2 and dropped ‘s’ at Instance. The last sentence in the same section changed from “Two

AXI Performance Monitors are instantiated” to “Two slots of AXI Performance

Monitors are used.”

Video Multiplexer, page 26

added the final sentence “For detailed information ...” The dvi2axi section on page 25 was removed.

Figure 2-4

changed “Xilinx DMA” block to “Xilinx AXI VDMA.”

Table 2-9 changed “core DMA”

to “Xilinx AXI VDMA.”

XVDMA Driver, page 35 changed “Xilinx DMA” to “Xilinx

AXI VDMA.” XFILTER_STOP, page 31 bullet switched “On demand mode” with

“Continuous mode” in both sentences.

Application, page 40

added a new sentence at end “The Linux kernel is in SMP mode and both ...” Figure 2-6 and

Figure 2-7 were replaced. In

Control and Decision Making, page 43 the bullet

“Sobel Filter (using the xFilter driver)” was added. In

User Space Device Control, page 44

deleted “Sobel filter” bullet.

Zynq-7000 AP SoC ZC702 Base TRD

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4

Date

01/31/2013,

continued

06/07/2013

10/14/2013

Version

3.0

4.0

5.0

Revision

Appendix A, Register Description

: Removed the AXI TPG Registers section.

Modified

Table A-1 and added a row for Bit Position 7.

Appendix C, Directory Structure : The directory structure in Figure C-1 changed.

Appendix F, Additional Resources : Added references for PG043 and PG103.

Updated ISE Design Suite version 14.3 to version 14.5 throughout document.

Added chroma resampler and YCrCb to RGB color space converter IP, and clarified third bullet under

The Base Targeted AP SoC Reference Design, page 8 .

Changed “Two AXI Performance Monitors” to “AXI Performance Monitor” under

Base TRD Key Features, page 11 . Updated

Figure 2-1, page 15 ,

Clocking, page 19

, Table 2-6, page 20

,

Programmable Logic, page 19

, to delete Clk_detect references. Updated values in

Table 2-1, page 16 .

Table 2-4, page 18

with

VID_IN_AXI4s information. Added

Video Color Space Formats, page 27 . and I2C

Sub-system, page 27

. Added Linux Boot, page 31 to replace earlier Boot loader contents. Updated

Table 2-7, page 27 to add UIO, Imageon, ADV7511, and

ADV7611 information. Added

ADV7511 V4L2 Driver, page 36 and

Xylon Frame

Buffer Driver, page 37 . Updated

Figure 2-6, page 39 and Figure 2-7, page 40 .

Updated

User Space Device Control, page 44 with sobel_lib information, and

deleted reference to udriver.h file. Added

Appendix B, Extended Display

Identification Data . Updated

Figure C-1, page 56 . Deleted “Set Up Linux System

Software Development tools” from

Appendix E

.

Updated ISE Design Suite version 14.5 to Vivado Design Suite version 2013.2 throughout document. Changes quantiy of Axi Performance Monitors from two to one under

Base TRD Key Features, page 11 . Updated

Table 2-1, page 16 .

Deleted AXI TPG from

Clocking, page 19

. Updated the names of the instances in

Processor System Reset Module, page 22

,

AXI Interconnect, page 22 ,

AXI Video

Direct Memory Access, page 23

,

Video Timing Controller, page 24 , Test Pattern

Generator, page 24 ,

logiCVC-ML, page 25

,

AXI Performance Monitor, page 25

,

fmc imageon hdmi in, page 25 ,

Chroma Resampler, page 26

,

YCrCb to RGB

Color-Space Converter, page 26

,

Video Multiplexer, page 26

,

Sobel Filter, page 26

, and

Video In to AXI4-Stream, page 27 . Added

Sobel Edge Detection, page 30

. Updated

Software Architecture, page 31

. Updated

Appendix C,

Directory Structure to reflect new updated directory structure. Added

Appendix D, PetaLinux Software Development Kit

.

Zynq-7000 AP SoC ZC702 Base TRD

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5

Table of Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Chapter 1: Introduction

The Base Targeted AP SoC Reference Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Base TRD Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 2: Functional Description

Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Appendix A: Register Description

Sobel Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Appendix B: Extended Display Identification Data

Storing and Programming EDID data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Appendix C: Directory Structure

Included Files and Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Appendix D: PetaLinux Software Development Kit

PetaLinux Development Tools (Host) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Appendix E: Install the Zynq-7000 AP SoC Design and Development Environment

Install the Xilinx Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Set Up git Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Appendix F: Additional Resources

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Additional References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Zynq-7000 AP SoC ZC702 Base TRD

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Appendix G: Regulatory and Compliance Information

Declaration of Conformity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Appendix H: Warranty

Zynq-7000 AP SoC ZC702 Base TRD

UG925 (v5.0) October 14, 2013 www.xilinx.com

7

Zynq-7000 AP SoC ZC702 Base TRD

UG925 (v5.0) October 14, 2013

Chapter 1

Introduction

This user guide describes the Base Targeted Reference Design (TRD) based on Zynq-7000

All Programmable SoC (AP SoC) architecture. The TRD is included with the ZC702 evaluation kit. To learn more about the ZC702 evaluation kit and how to evaluate different demonstrations based on Zynq-7000 AP SoC architecture, see the Zynq-7000

All Programmable SoC: ZC702 Evaluation Kit and Video and Imaging Kit Getting Started

Guide (UG926)

[Ref 1] .

This document explains the functional architecture of the hardware and software components of the TRD. Also provided are register descriptions for IP/logic implemented in programmable logic (PL), Base TRD package directory structure, and pointers to enable the user to further develop embedded platforms based on Zynq-7000 AP SoC architecture.

To build hardware and software for the Base TRD, refer to the Xilinx Zynq-7000 Base

Targeted Reference Design webpage wiki.xilinx.com/zc702-base-trd .

The Base Targeted AP SoC Reference Design

The Base TRD showcases various features and capabilities of the Zynq-7000 AP SoC Z-7020 device for the embedded domain in a single package using a Xilinx standard Zynq platform

Linux-based video pipeline design.

The Base TRD consists of two processing elements: the Zynq-7000 AP SoC processing system (PS) and a video accelerator based on PL. The AP SoC allows the user to implement a specific functionality either as a software program running on the Zynq-7000 AP SoC PS or as a hardware design inside the PL. The Base TRD demonstrates an optimization of how the user can seamlessly switch between a software or a hardware implementation, contributing to ease of use. The TRD also demonstrates the value of offloading computation-intensive tasks onto PL, thereby freeing the CPU resources available for user-specific applications.

Software developers can leverage the Base TRD and start programming immediately using the widely known Eclipse-based integrated development environment (IDE), GNU compiler tool chain, Linux operating system (OS), and libraries. Embedded hardware designers now have immediate access to the industry standard ARM® Cortex™-A9 core processor system and video IPs running on PL out of the box. In addition, the TRD also provides customers with access to the various PL-based video components such as video direct memory access www.xilinx.com

8

The Base Targeted AP SoC Reference Design

(VDMA), video timing controller (VTC), video test pattern generator (TPG), Sobel filter and the Xylon logiCVC-ML display controller ( www.logicbricks.com/Products/logiCVC-ML.aspx

).

These IPs are part of the video pipeline implemented in the PL.

The Base TRD consists of a PS based on the embedded ARM Cortex-A9 core processor, a video processing pipeline implemented in PL, and a Linux-based software application that includes a Qt-based graphical user interface (GUI) ( doc.qt.nokia.com

) to provide user control and monitoring. The Linux-based software platform and software application run on the ARM Cortex-A9 cores. The software application works in tandem with hardware and provides the user the choice of offloading computation-intensive processing to the

PL-based hardware subsystem.

Zynq-7000 AP SoC ZC702 Base TRD

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The Base Targeted AP SoC Reference Design

The Zynq-7000 AP SoC Base TRD reference design (

Figure 1-1 ) consists of these

components:

• A dual ARM Cortex-A9 core processor-based embedded Linux OS, board support package (BSP), and U-Boot boot loader

• PL-based hardware IPs that enable acceleration of computation-intensive video processing tasks

• Linux application to configure and control the video IPs in the PL and the PS

X-Ref Target - Figure 1-1

Linux User Space

Command Line Application Qt-Based Multithreaded Application

Linux Kernel

Kernel Libraries and Utilities Device Drivers

Processing

System

DDR Memory Controller

Programmable

Logic

AMBA Switches

APU

Display Controller

Video Processing

(Sobel Filter)

Video

Output

AMBA Switches

Video Test Pattern

Generator

(Optional)

Video Input with

Zynq-7000

Video and

Imaging Kit

S_AXI3_HP 64 bit

M_AXI3_GP 32 bit

UG925_c1_01_061913

Figure 1-1:

Zynq-7000 AP SoC Base TRD System Block Diagram

The TRD deliverables include source code for RTL design and software packages such as the

Linux OS, device drivers, the application, and the GUI.

Note:

The camera supplied with the video kit is not supported with the TRD.

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Base TRD Key Features

Base TRD Key Features

Components in the Base TRD are further described in this section.

The Base TRD processing system (PS) includes:

• A dual ARM Cortex-A9 core

• ARM AMBA® AXI interconnect

• Multi-protocol, 32-bit DDR DRAM controller

• Standard peripheral interfaces including USB, Ethernet, UART, I2C, SD MMC, and GPIO

Base TRD programmable logic includes:

• AXI interconnects, 64-bit wide at 150 MHz

• One AXI interconnect, 32-bit wide at 75 MHz

• AXI VDMA(s)

• A full HD video input and output interface

• A Sobel accelerator

• AXI Performance Monitor

Base TRD software includes:

• Xilinx Zynq-7000 standard Linux kernel (based on Open Source Linux 3.x)

• Linux device drivers for TRD-specific IPs

• Qt-based Linux application demonstrating the video processing pipeline

List of Acronyms

Table 1-1 lists acronyms used in this document.

Table 1-1:

Acronyms

Acronym

AFI

APU

BSP

COR

DTB

DTS

AXI FIFO interface

Application processor unit

Board support package

Clear on read

Device tree binary

Device tree source

Definition

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11

Table 1-1:

Acronyms (Cont’d)

Acronym

SDK

SoC

TDP

TPG

TRD

PL

PS

R

RTL

RW

SC

SD

SD MMC

IDE

IOP

IP

JTAG

KFLOPS

NVM

OCM

OS

EDK

AP SoC

FMC

FPS

FSBL

GIC

GUI

HD

Definition

Embedded Development Kit

All Programmable SoC

FPGA mezzanine card

Frames per second

First-stage boot loader

General interrupt controller

Graphical user interface

High definition

Integrated development environment

Input/output peripherals

Intellectual property

Joint Test Action Group

Kilo floating-point operations per second

Nonvolatile memory

On-chip memory

Operating system

Programmable logic (inside the Zynq-7000 AP SoC)

Processing system

Read only

Register transfer level

Read/write

Self clear

Secure Digital

Secure Digital Multimedia Card

Software Development Kit

System on Chip

Targeted Design Platform

(Video) Test Pattern Generator

Targeted Reference Design

VDMA

VTC

Video direct memory access

Video timing controller

Base TRD Key Features

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Base TRD Key Features

Table 1-1:

Acronyms (Cont’d)

Acronym Definition

XPS

ZC702

Xilinx Platform Studio

Platform development board based on the Zynq AP SoC Z-7020 device

Zynq Z-7020 An implementation of the Zynq-7000 AP SoC with a fixed feature set and

PL capabilities

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Chapter 2

Functional Description

This chapter describes the Zynq-7000 AP SoC ZC702 Base Targeted Reference Design

(TRD) hardware design, software system, and video demonstration application components.

It also describes how data flows through the various connected IPs and includes information about the flow of application control.

To build hardware and software for the Base TRD, refer to the Xilinx Zynq-7000 Base

Targeted Reference Design wiki page wiki.xilinx.com/zc702-base-trd .

Hardware Architecture

The block diagram for the Base TRD is shown in

Figure 2-1

. This design has two parts:

• Processing system (PS)

• Video IPs and custom logic implemented in programmable logic (PL)

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Hardware Architecture

X-Ref Target - Figure 2-1

Bank0

MIO

(15:0)

I/O

MUX

(MIO)

I/O Peripherals

SPI 0

SPI 1

I2C 0

I2C 1

CAN 0

CAN 1

UART 0

UART 1

GPIO

SD 0

SD 1

USB 0

USB 1

Enet 0

Enet 1

Bank1

MIO

(53:16)

FLASH Memory

Interfaces

SRAM/NOR

NAND

Quad SPI

Input Clock and Freq

Clock

Generation

0 1 2 3

Extended

MIO (EMIO) PS to PL

Clock Ports

Reset

Central

Interconnect

Processing System (PS)

SWDT

TTC

System

Level

Control

Regs

DMAS

Channel

Application Processor Unit (APU)

NEON/FPU Engine

MMU

32 KB I

Cache

Cortex-A9

MPCore

CPU

32 KB D

Cache

GIC

NEON/FPU Engine

MMU

32 KB I

Cache

Cortex-A9

MPCore

CPU

32 KB D

Cache

Snoop Control Unit

CoreSight

Components

OCM

Interconnect

512 KB L2 Cache and Controller

255 KB OCM

BootROM

32b GP

AXI

Master

Ports

32b GP

AXI

Slave

Ports

DAP

DMA Sync

0 1 2 3

DEVC

12 13 14 15

8 9 10 11

4 5 6 7

0 1 2 3

Programmable

Logic to Memory

Interconnect

IRQ

High Performance

AXI 32b/64b

Slave Ports

Memory Interfaces

DDR2/3, LPDDR2

Controller

Perf

Mon

PS I2C-1

(EMIO)

S

AXI Interconnect

M M M M M M

M

M M

Master

AXI Interconnect

Slave Slave

Master

AXI Interconnect

Slave Slave

Local Pcore

EDK IP

Third Party IP

CORE Generator EDK IP

AXI Interface

Video Interface

AXI Streaming

Interface

Video Sync Signals

Monitor

Video

In

1080p

HDMI_IN

VTC_0

VID_IN_AXI4S

VIDEO_MUX_0

TPG_0

S2MM

TPG VDMA

LOGICVC_0

YUV2RGB_0

CRESAMPLE_0

Video

Out

1080p

MM2S S2MM

Sobel VDMA

Sobel Filter

64b

AXI ACP

Slave

Port

UG925_c2_01_042313

Figure 2-1:

Zynq-7000 AP SoC Base TRD Hardware Block Diagram

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Hardware Architecture

This system is implemented in a Zynq-7000 AP SoC device (XC7Z020-CLG484-1) using

Vivado® Design Suite, version 2013.2 tools.

The PL hardware utilization for the implemented design is shown in

Table 2-1

.

Table 2-1:

PL Hardware Utilization for Device XC7Z020-CLG484-1

(1)

FPGA Components

LUTs

I/Os

Slice registers

Total Available

53,200

200

106,400

Used

20,992

43

28,212

% Used

39

21

26

FPGA Logic Memory

RAMB36/FIFO

RAMB18

140

280

45

14

32

5

Notes:

1. The figures provided here are only indicative of nature and can vary between different tool chain versions.

The PL-implemented video IP and custom logic address map is shown in

Table 2-2 .

Table 2-2:

FPGA Logic Address Map for the Zynq-7000 AP SoC ZC702 Base TRD

Instance

VTC_0

TPG_0

TPG_VDMA

FILTER_VDMA

LOGICVC_0

PERF_MON_HP0_HP2

CRESAMPLE_0

YUV2RGB_0

FILTER_ENGINE

Peripheral

axi_vtc axi_tpg axi_vdma axi_vdma

LogiCVC axi_perf_mon v_cresample v_ycrcb2rgb sobel_filter_top

Base Address

0x40070000

0x40080000

0x40090000

0x400B0000

0x40030000

0x400F0000

0x40040000

0x40050000

0x400D0000

High Address

0x4007FFFF

0x4008FFFF

0x4009FFFF

0x400BFFFF

0x4003FFFF

0x400FFFFF

0x4004FFFF

0x4005FFFF

0x400DFFFF

System Configuration

Processing System

This design makes full use of these four major components in the PS:

• Application processor unit (APU)

• Interconnect

• Input/output peripherals (IOP)

• Memory interfaces

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Hardware Architecture

This section describes some of the features of the PS used in this design. For detailed information about the complete feature set including a functional description, see the

Zynq-7000 All Programmable SoC Technical Reference Manual (UG585)

[Ref 2]

.

APU

The APU includes the dual ARM Cortex-A9 core processor, snoop control unit (SCU), L2 cache controller, on-chip memory (OCM), 8-channel DMA, system watchdog timer (SWDT), and triple-timer controller (TTC) blocks.

Cortex-A9 Core - The ARM Cortex-A9 core processor implements the ARMv7 architecture and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java byte codes in the Jazelle state. The media processing engine implements ARM NEON coprocessor technology, a single instruction multiple data (SIMD) architecture that adds instructions targeted at audio, video, 3D graphics, image, and speech processing. For this

TRD, both ARM cores run at 667 MHz.

General Interrupt Controller - The GIC collects interrupts from various sources and distributes these interrupts to each of the ARM cores. The interrupt distributor holds the list of pending interrupts for each ARM Cortex-A9 core processor and then selects the highest priority interrupt before issuing it to the Cortex-A9 processor interface. Interrupts of equal priority are resolved by selecting the lowest ID. A total of 64 shared peripheral interrupts (PL interrupts + PS I/O peripheral interrupts) are supported, starting from ID 32.

Table 2-3

lists interrupt IDs for interrupts coming from PL.

Table 2-3:

Interrupt IDs for PL-Generated Interrupts

Interrupt line

CVC_DISPLAY_interrupt

TPG_VDMA_s2mm_introut

FIILTER_VDMA_s2mm_introut

FIILTER_VDMA_mm2s_introut

FILTER_0_interrupt

ADV7511 HPD interrupt

ID

88

87

86

91

90

89

Type

Level

Level

Level

Level

Level

Level

Instance

CVC_DISPLAY

TPG_VDMA

FIILTER_VDMA

FIILTER_VDMA

FILTER_ENGINE

HDMI_O_INT

Interconnect

The interconnect unit connects all PS and PL master and slave devices. There are a total of six Advanced eXtensible Interface (AXI) slave ports dedicated for AXI masters residing in the

PL, and four of these ports contain deep FIFOs to improve data throughput. Two AXI master ports provide access to AXI slaves in the PL. In this design, masters in PL are connected through two AXI slave ports with deep FIFOs. One AXI master port is used to access registers in AXI slave IPs in PL.

An advanced peripheral bus (APB) master port is provided for accessing software programmable registers of all PS modules. The top level switch is AXI3-compliant, the soft

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Hardware Architecture

IPs provided by Xilinx are AXI4-compliant, and the soft AXI interconnect IP provides protocol bridging as needed.

S_AXI_HP - The high performance slave AXI interfaces (S_AXI_HP) connect the PL to AFI blocks in the PS. The PL has four AXI masters out of which two are connected to the

S_AXI_HP0 port and two are connected to the S_AXI_HP2 port. The HP port enables a high throughput data path between AXI masters in the programmable logic and the processing system's DDR3 memory. The main aim of the AXI FIFO interface (AFI) units is to smooth out this variable latency, allowing the ability to stream data continuously from DDR to the PL masters and from the PL masters to DDR. The PL-side interface of AFI runs on the clock coming from the PL. In this design, a 150 MHz clock is connected from the PL side. The

DDR-side clock is running on 2/3 of the DDR_CLK (533 MHz). The high performance AXI interface module provides several "hooks" to assist in bandwidth management of masters connected to different PL ports. Controlling issuance capability available from the PL port is one of the hooks exercised in this design to obtain a fair share of bandwidth between two masters, SOBEL VDMA, and the display controller.

M_AXI_GP - This AXI master port interfaces with AXI slave IPs in PL through an AXI Lite interconnect. The CPU manages initializing and controlling the video pipeline through this port.

IOP - The IOP unit includes communication peripherals. GPIO, Ethernet, USB, I2C, and SD controllers from the PS are used extensively in this design.

GPIO - The 64-bit general purpose input/outputs (GPIOs) are connected to the PL through the extendable multiplexed I/O (EMIO) interface. Sixty-four bits are divided into two banks, each of 32 bits. Because each GPIO bit can be dynamically configured as input or output,

GPIO bits are used in this design for a variety of functions.

Table 2-4 lists the GPIO bit and

purpose in design.

Table 2-4:

GPIO Bits Functional Description

GPIO Bit

Number

Net Name Purpose

0

1

3 ps7_0_GPIO_O[0] Resets video receiving block VID_IN_AXI4s ps7_0_GPIO_O[1] Resets Sobel filter block ps7_0_GPIO_O[3] Selects a line for the video multiplexer—either the external video source or the internally generated test pattern

6 ps7_0_GPIO_O[6] FMC-IMAGEON I2C multiplexer reset

2, 4, 5, 7 N/A N/A

Memory Interfaces

The memory interfaces unit includes the DDR memory controller and nonvolatile memory

(NVM) controllers. The DDR memory controller includes a 4-port arbiter. One AXI port is dedicated for ARM CPU access and two ports are dedicated for high performance AXI interface master devices in the programmable logic. The remaining port is shared by all

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Hardware Architecture

other AXI masters. In this design, DDR3 is configured to run at 533 MHz, and the AXI interface is running at 355 MHz.

PL Clocks

The PS provides four fully programmable clocks (FCLK_CLK) to the PL. These clocks are routed directly to PL clock buffers to serve as a frequency source for the PL. The clock generator module in PL gets a 100 MHz clock from FCLK_CLK0.

PL Reset

The PS provides four FCLK_RESET[3:0]_N fully programmable reset signals to the PL. These signals are asynchronous to PS clocks. The PL logic reset block in this design receives input from FCLK_RESET0_N and generates necessary reset signals for the design implemented in

PL.

Programmable Logic

Clocking

The FPGA logic design has three clock domains: AXI MM (memory-mapped) interconnect,

AXI register interface, and video clock. These domains run at 150 MHz, 75 MHz, and

148.5 MHz, respectively.

The clock generator module receives a 100 MHz input clock from the PS FCLK_CLK0 and generates 75 MHz and 150 MHz. The AXI Lite interconnect works on 75 MHz. Apart from the AXI Lite interconnect, the register interface of AXI VDMA, AXI TPG, logiCVC-ML, VTC, and perf_monitor are driven by the 75 MHz clock.

Two instances of the AXI_MM interconnect connected to the HP port of the PS run on

150 MHz. The S2MM (stream to memory map) and MM2S (memory map to stream) channels of VDMAs are running at 150 MHz. The 150 MHz clock drives the logiCVC-ML memory read interface and also the AXI slave interface of the Sobel filter.

The video clock comes from the onboard clock synthesizer or the FMC-IMAGEON card.

BUFGMUX dynamically selects which video clock source drives logic running on the video clock domain. The VTC, VID_IN_AXI4S, and logiCVC-ML blocks run on the video clock.

Table 2-5 lists system clocks.

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Hardware Architecture

Table 2-5:

System Clocks

Clock Signal

FPGA_CLK clk_75mhz clk_150mhz

Source

PS - FCLK_CLK0

Internal mixed-mode clock manager (MMCM)

Internal MMCM

VIDEO_CLK_P, VIDEO_CLK_N External differential video clock coming from clock synthesizer on board fmc_imageon_in_0_clk_pin External video clock coming from Imageon FMC

Frequency Use

100 MHz

75 MHz

150 MHz

Input clock to clock generator

Clock for AXI Lite interconnect, generated by clock generator

Clock for AXI MM interconnect, generated by clock generator

148.5 MHz Clock for display controller and video receiving blocks

148.5 MHz Clock for video receiving modules

Based on user clock configuration inputs, the clock generator determines the correct configuration of the PLLs.

Table 2-6 shows clock requirements of master and slave peripherals connected in system

and their connection.

Table 2-6:

PL Clock Configuration

Component clock_generator_0

• CLKIN

• CLKOUT0

• CLKOUT1

Frequency (MHz) Phase Buffered

100

75

150

Yes

Yes

Yes

Connection

FPGA_CLK clk_75mhz clk_150mhz

VIDEO_MUX_0

• video_clk_1

• video_clk_2

• video_clk

Processor

ps7_0

• FCLK_CLK0

• M_AXI_GP0_ACLK

• S_AXI_HP0_ACLK

• S_AXI_HP2_ACLK

148.5

148.5

148.5

100

75

150

150

0

0

0

0

0

0

0

Yes

Yes

Yes

Yes

Yes

Yes

Yes

VIDEO_CLK fmc_imageon_hdmi_in_0_clk_pin video_clk_int

FPGA_CLK clk_75mhz clk_150mhz clk_150mhz

Buses

axi4_0

• INTERCONNECT_ACLK

150 0 Yes clk_150mhz

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Hardware Architecture

Table 2-6:

PL Clock Configuration (Cont’d)

Component

axi4_1

• INTERCONNECT_ACLK axi4_lite

• INTERCONNECT_ACLK

Frequency (MHz) Phase Buffered

150

75

0

0

Yes

Yes

Connection

clk_150mhz clk_75mhz

Peripherals

proc_sys_reset_1

• Slowest_sync_clk

75 0 Yes clk_75mhz

LOGICVC_0

• S_AXI_ACLK

• mclk

• vclk

FILTER_ENGINE

• SYS_CLK

• s_axi_CONTROL_BUS_ACLK

SOBEL_SWRST_FF

• Clk

75

150

148.5

150

150

75

0

0

0

0

0

0

Yes

Yes

Yes

Yes

Yes

Yes clk_75mhz clk_150mhz

VIDEO_CLK clk_150mhz clk_150mhz clk_75mhz

FILTER_VDMA

• m_axi_mm2s_aclk

• m_axi_s2mm_aclk

• m_axis_mm2s_aclk

• s_axi_lite_aclk

• s_axis_s2mm_aclk

TPG_SWRST_FF

• Clk

TPG_VDMA

• m_axi_s2mm_aclk

• s_axi_lite_aclk

• s_axis_s2mm_aclk

PERF_MON_HP0_HP2

• SLOT_0_AXI_ACLK

• SLOT_1_AXI_ACLK

• S_AXI_ACLK

• CORE_ACLK

VTC_0

150

150

150

75

150

75

150

75

150

150

150

75

150

0

0

0

0

0

0

0

0

0

0

0

0

0

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes clk_150mhz clk_150mhz clk_150mhz clk_75mhz clk_150mhz clk_75mhz clk_150mhz clk_75mhz clk_150mhz clk_150mhz clk_150mhz clk_75mhz clk_150mhz

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Hardware Architecture

Table 2-6:

PL Clock Configuration (Cont’d)

Component

• clk

• S_AXI_ACLK

Frequency (MHz) Phase Buffered

148.5

75

0

0

Yes

Yes

Connection

video_clk_int clk_75mhz

TPG_0

• aclk

• s_axi_aclk

HDMI_IN

• clk

150

75

148.5

0

0

0

Yes

Yes

Yes clk_150mhz clk_75mhz fmc_imageon_hdmi_in_0_clk_pin

VID_IN_AXI4S

• vid_in_clk

• aclk

CRESAMPLE_0

• aclk

• s_axi_aclk

YUV2RGB_0

• aclk

• s_axi_aclk

148.5

150

150

75

150

75

0

0

0

0

0

0

Yes

Yes

Yes

Yes

Yes

Yes video_clk_int clk_150mhz clk_150mhz clk_75mhz clk_150mhz clk_75mhz

Processor System Reset Module

Instance: system_top_i/proc_sys_reset_1

The proc_sys_reset module implements a reset scheme. Input to the proc_sys_reset core is generated by PS Proc_sys_reset_1_N. The polarity of input reset to this block is indicated by parameter C_EXT_RESET_HIGH. In this design, C_EXT_RESET_HIGH is set to 0 as reset generated by PS is active-Low. This block generates various types of resets, such as reset for interconnect, peripheral reset, and so on. All the blocks in the PL are driven by interconnect reset, which is active-Low in polarity.

For detailed information about the complete feature set and a functional description of the proc_sys_reset IP, see the LogiCORE IP Processor System Reset Module Product Specification

(PG164) [Ref 3]

.

AXI Interconnect

Instances: system_top_i/axi4_hp0, system_top_i/axi4_hp2, system_top_i/axi4_gp0

FPGA logic design has two interconnects for AXI memory-mapped masters and one interconnect for the AXI register interface.

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Hardware Architecture

AXI memory-mapped interconnects are connected to masters like AXI_VDMA and logiCVC-ML. Slaves connected to these interconnects includes HP0 and HP2 ports of

Zynq-7000 AP SoC PS. This interconnect operates at 150

MHz

and the data width is 64-bit wide. The read/write acceptance and issuance are set to 8. The acceptance and issuance helps improve system performance. The PS HP port can accept a maximum burst length of

16. This imposes a limitation on getting minimum acceptable bandwidth for every master in a multi-master system. The optimum setting of issuance and acceptance reduces throttle on the bus and compensates for long latencies.

The AXI register interface is clocked at 75

MHz

. The Zynq-7000 AP SoC PS GP0 port acts as master on this interconnect and connected slaves have register maps. AXI TPG and VTC are examples of slaves connected to this interconnect. The operations of the video pipeline are controlled by registers inside every IP. Depending upon data flow required in the video pipeline, the processor writes these registers through the AXI Lite interconnect. The AXI Lite interconnect accepts write or read transfers from the CPU, performs address decoding, selects a particular slave, and establishes a communication channel between the CPU and the slave device.

For detailed information about the complete feature set and a functional description of the

AXI Interconnect IP, see the LogiCORE IP AXI Interconnect Product Guide (PG059)

[Ref 4] .

AXI Video Direct Memory Access

Instances: system_top_i/Video_Capture/TPG_VDMA, system_top_i/Video_Processing/FILTER_VDMA

AXI VDMA has an AXI streaming interface on one side and an AXI memory-mapped interface on the other side. The VDMA has two channels: MM2S (memory-mapped to streaming) and S2MM (streaming to memory-mapped). The MM2S channel reads the number of data beats programmed through the C_MM2S_MAX_BURST_LENGTH parameter and presents it to the slave device connected through the streaming interface. The data width of the streaming interface can be different than the memory-mapped interface and controlled through C_M_AXIS_MM2S_TDATA_WIDTH. The data width of the S2MM memory-mapped interface is controlled by the C_M_AXI_MM2S_DATA_WIDTH parameter.

The S2MM channel receives data from the master device connected through the streaming interface. The C_S_AXIS_S2MM_TDATA_WIDTH parameter decides the width of the streaming interface. Data received on the streaming interface is then written into the system memory through the memory-mapped interface. The C_M_AXI_S2MM_DATA_WIDTH parameter decides the data width of the memory-mapped interface and

C_S2MM_MAX_BURST_LENGTH governs the burst length of the write transaction.

In this design, the streaming interface data width is set to 32-bit wide and the memory-mapped interface is configured as 64-bit wide. The AXI VDMA is used in simple register direct mode, which removes the area cost of the scatter/gather feature.

Initialization, status, and management registers in the AXI VDMA core are accessed through an AXI4-Lite slave interface. To get the best possible throughput for AXI VDMA instances,

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Hardware Architecture

the maximum burst length is set to 16. In addition, the master interfaces have a read and write issuance of 8 and a read and write FIFO depth of 512 to maximize throughput. The line buffers inside the AXI VDMA for the read and write sides are set to 4K deep and the store and forward feature of the AXI VDMA are enabled on both channels to improve system performance and reduce the risk of system throttling.

For detailed information on the complete feature set and a functional description of AXI

VDMA IP, see the LogiCORE IP AXI Video Direct Memory Access Product Guide (PG020)

[Ref 5] .

Video Timing Controller

Instance: system_top_i/Video_Capture/VTC_0

The VTC is a general purpose video timing generator and detector. The input side of this core automatically detects horizontal and vertical synchronization pulses, polarity, blanking timing, and active video pixels. This information can be used by application software to take various decisions and for configuration of the video pipeline. In the current design, application software measures resolution of external video and then decides whether to switch to the external video source or not. The same feature can be expanded in the future to configure the video pipeline based on input resolution.

The output side of the core generates the horizontal and vertical blanking and synchronization pulses. The width and interval of these pulses are configured through the

AXI Lite interface. The AXI TPG block generates a video test pattern based on video timing pulses generated by VTC. In this design, VTC is used to generate video timing signals to match Full HD (1080p60) video format.

The video timing generator/detector block and AXI Lite interface of this core work on a single clock domain (i.e., the video clock).

For detailed information on the complete feature set, a functional description, and licensing information for Video Timing Controller IP, see the LogiCORE IP Video Timing Controller

Product Guide (PG016)

[Ref 6] .

Test Pattern Generator

Instance: system_top_i/Video_Capture/TPG_0

The Test Pattern Generator contains an AXI register interface to access slave control registers from a processor. This IP can generate patterns like color bars, horizontal and vertical burst patterns, and zone plates. The generation of pattern is controlled through the pattern control register. It also enables the overlay of a box on a selected pattern. The motion control register controls the speed at which the box moves over a selected pattern.

In this design, a zone plate pattern is used with a moving box. The size of the zone plate is controlled through zplate hdelta and zplate vdelta registers. The box size register controls the size of the box, and the color of the box is selected by the box color register. The width

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Hardware Architecture

and height of the pattern is equal to 1920 x 1080, selected through the line length and frame height register.

For detailed information on the complete feature set and a functional description of Test

Pattern Generator, see the LogiCORE IP Test Pattern Generator Product Guide (PG103)

[Ref 7]

.

logiCVC-ML

Instance: system_top_i/Video_Display/LOGICVC_0

The logiCVC-ML is a multi-layer video display controller from Xylon

( www.logicbricks.com/Products/logiCVC-ML.aspx

). The logiCVC-ML controller refreshes the display image by reading the video memory and converting the read data into a data stream acceptable for the display interface. It generates control signals for the display, and supports multiple layers with video processing functions such as alpha blending, transparency, and move around.

For detailed information about the complete feature set, a functional description, and license information for logiCVC-ML IP, refer to the Xylon data sheet

( www.logicbricks.com/Products/logiCVC-ML.aspx

).

AXI Performance Monitor

Instance: system_top_i/PERF_MON_HP0_HP2

The AXI Performance Monitor can monitor and analyze system behavior on the AXI interface. This core is used in the Base TRD to measure read and write throughput on AXI slave ports of the PS (HP0 and HP2), which are used to access DDR memory from PL. The core consists of the AXI4-Lite interface to configure and control the core.

This core is configured to measure the read and write throughput by counting the number of transactions per second. When the configured time interval expires, measured throughput in bytes is loaded into a register and read by the software application.

Two slots of AXI Performance Monitors are used to measure read and write throughput of

HP0 and HP2 simultaneously.

For detailed information on the complete feature set and a functional description of AXI

Performance Monitor, see the LogiCORE IP AXI Performance Monitor Product Guide (PG037)

[Ref 8] .

fmc imageon hdmi in

Instance: system_top_i/HDMI_IN

This IP core receives video from FMC-IMAGEON, in YCrCb 4:2:2 format, with embedded vblank and hblank signals, and extracts blanking information.

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Hardware Architecture

Chroma Resampler

Instance: system_top_i/Video_Capture/CRESAMPLE_0

This IP is a chroma resampler, which is configured to convert the video from YCrCb 4:2:2 to

YCrCb 4:4:4. This IP has an AXI4 slave interface to configure, control, and read status from the application software.

For detailed information on the complete feature set, a functional description, and license information for Chroma Resampler, see the LogiCORE IP Chroma Resampler Product Guide

(PG012) [Ref 9]

.

YCrCb to RGB Color-Space Converter

Instance: system_top_i/Video_Capture/YUV2RGB_0

This IP is a color space converter, which converts the video from YCrCb to RGB format as the rest of video IPs in the pipeline work on RGB video. This IP has an AXI4 slave interface to configure, control, and read status from the application software.

For detailed information on the complete feature set, a functional description, and license information for YCrCb to RGB Color-Space Converter IP, see the LogiCORE IP YCrCb to RGB

Color-Space Converter Product Guide (PG014)

[Ref 10] .

Video Multiplexer

Instance: system_top_i/Video_Capture/VIDEO_MUX_0

This IP multiplexes the sync signals from time base generator (VTC_0) and fmc_imageon_hdmi_in and feeds the Video In to AXI4-Stream (VID_IN_AXI4S). The selection is done by PS GPIO (ps7_0_GPIO_O[3]).

For detailed information on the complete feature set and a functional description of Video in to AXI4-Stream IP, see the LogiCORE IP Video In to AXI4-Stream v1.0 (PG043)

[Ref 12]

.

Sobel Filter

Instance: system_top_i/Video_Processing/FILTER_ENGINE

This IP has the AXI4-Lite interface through which the IP is configured and controlled.

The number of rows and columns are configured using AXI interface, and the filtering process starts when the Start register is written through the Sobel interface.

The Sobel filter detects the edge in the video frame and the processed frame is sent out on

AXI stream interface.

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Hardware Architecture

This IP generates an interrupt after processing every frame, then the software initiates the process for the next frame by writing to the control register.

Video In to AXI4-Stream

Instance: system_top_i/Video_Capture/VID_IN_AXI4S

This IP interfaces a video source to the AXI4-Stream interface. It also handles video data clock boundary crossing between the video clock domain and AXI4-Stream clock domain.

For detailed information on the complete feature set and a functional description of Video in to AXI4-Stream IP, see the LogiCORE IP Video In to AXI4-Stream v1.0 (PG043)

[Ref 12] .

Video Color Space Formats

Table 2-7 shows the video color space formats available in the video pipeline.

Table 2-7:

Video Color Space formats

Video IP

HDMI_IN (ADV7611)

VID_IN_AXI4S

TPG_0 (Test Pattern Generator)

CRESAMPLE_0

YUV2RGB_0

TPG_VDMA (S2MM)

FILTER_VDMA (S2MM & MM2S)

Sobel Filter

LogiCVC

HDMI_OUT (ADV7511)

Input Video Format

YCbCr 4:2:2

YCbCr 4:2:2

YCbCr 4:4:4

ARGB 32 bpp

ARGB 32 bpp

YCbCr 4:2:2

Output Video Format

YCbCr 4:2:2

YCbCr 4:4:4

ARGB 32 bpp

ARGB 32 bpp

YCbCr 4:2:2

RGB

Because both VDMAs operate on ARGB 32 bpp, the DDR memory always has the ARGB

32 bpp video format.

I2C Sub-system

I2C is a two-wire bus for attaching low-speed peripherals. It uses two bi-directional open-drain lines, SDA (serial data) and SCL (serial clock), pulled up with resistors. In standard mode, a 7-bit address space and a 100 kHz bus speed are used. In this reference design, the two PS I2C controllers are used as bus masters to configure a number of I2C slaves or clients. The bus hierarchy is shown in

Figure 2-2

.

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X-Ref Target - Figure 2-2

ZC702

PS 12C0

MIO

PCA9548

(0x74)

0 1 2 3 4 5 6 7

FMC-IMAGEON

Hardware Architecture

PS 12C1

EMIO

PCA9546

(0x70)

0 1 2 3

SI570

(0x5D)

ADV7511

(0x39)

CAT24C02

(0x50)

ADV7611

(0x4C)

PCA9534

(0x20)

UG925_c2_11_05091

Figure 2-2:

I2C Sub-system

The PS I2C0 controller is connected via hard-wired MIO signals (SCL on MIO[50] and SDA on

MIO[51]) to an 8-channel I2C multiplexer (PCA9548) at address 0x74 on the ZC702 board.

The following I2C clients are connected to the I2C multiplexer and used in this design: A programmable clock synthesizer (SI570) is connected to channel 0 at address 0x5D; an

HDMI encoder/transmitter (ADV7511) is connected to channel 1 at address 0x39; and, optionally, a 2 Kb EEPROM (CAT24C02) is connected to channel 6 at address 0x50 on a daughter card plugged into the FMC2 slot.

The PS I2C1 controller is connected through the PL via EMIO signals to a 4-channel I2C multiplexer (PCA9546) at address 0x70 on the FMC-IMAGEON daughter card (if present).

The following I2C clients are connected to the I2C multiplexer and (optionally) used in this design: An HDMI decoder/receiver (ADV7611) is connected to channel 2 at address 0x4C; an 8-bit I/O expander (PCA9534) is connected to channel 3 at address 0x20.

Both I2C multiplexers can be reset individually by toggling their active-low reset line connected to the PS GPIO controller. The 8-channel I2C multiplexer is connected to

GPIO[13] via MIO; the 4-channel I2C multiplexer is connected to GPIO[60] via EMIO (routed through the PL).

The SI570 clock synthesizer is used to generate an accurate video clock that is used to drive the display output. The logiCVC display controller configures the SI570 to generate a specific video clock frequency based on the selected video resolution (e.g., for 1920x1080 at 60 frames per second [1080p60]), the video clock needs to be set to 148.5 MHz. The generated clock is a differential clock connected the PL. The same clock is used not only to drive the display output, but it also connects to the VTC's timing generator which in turn provides video timing signals to the TPG.

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Hardware Architecture

The ADV7511 HDMI transmitter is driven by the logiCVC display controller. Its video input interface consists of a video clock, a 16-bit video data bus, a data enable, and horizontal and vertical sync signals. The HDMI transmitter serializes the incoming video stream and sends it to the display via HDMI. The video input format is YCbCr 4:2:2; built-in color space converter and chroma resampler are used to drive RGB 4:4:4 on the output side interfacing the display. The SPDIF pin for audio is unused and therefore not connected in this design.

The interrupt pin is connected to the GIC and the signal is routed through the PL. The main purpose is to detect if a display is connected to the HDMI port or not; this feature is called hot plug detect (HPD). Furthermore, the ADV7511 is used to query the Extended Display

Identification Data (EDID), a standard published by the Video Electronics Standards

Association (VESA). The main purpose of the EDID is to provide information on the video resolutions supported by a video sink, in this case a display monitor. This information is communicated back to the display controller which then uses the information to generate the proper timing signals to drive the HDMI transmitter which in turn drives the display.

The FMC standard defines an I2C bus interface to optionally support the Intelligent

Platform Management Interface (IPMI). The Field Replaceable Unit (FRU) for IPMI is a data structure stored inside the CAT24C02 2 Kb EEPROM of the FMC-IMAGEON daughter card. It holds the inventory information, such as vendor ID and manufacturer, part number, version number etc. The reference design tries to access the FRU information to detect the presence of and to identify the FMC-IMAGEON daughter card.

The ADV7611 HDMI receiver on the FMC-IMAGEON daughter card is used to connect an external video source like an HD camera or video player via HDMI. The interface to the PL consists of a video clock and a 16-bit video data bus. The video format interfacing the PL is

YCbCr 4:2:2 with embedded sync signals (i.e. there are no separate signals for data enable, horizontal and vertical sync to reduce pin count). The SPDIF pin for audio is unused in this design and hence not connected. The active-low reset and HPD control pins are inputs, connected to the I/O expander.

The PCA9534 I/O expander is used to drive the reset line and HPD control pin of the

ADV7611 HDMI receiver. The HPD signal is only asserted after the EDID has been programmed into the internal EEPROM of the ADV7611. On the video input side, the EDID is used to advertise the video resolutions supported by the HDMI receiver to the video source (e.g. an HD media player). The video source will receive the HPD event and then determine the video output resolution based on the EDID information read from the

ADV7611 HDMI receiver. Some video sources do not attempt to read the EDID and therefore allow driving a potentially unsupported video resolution.

Note that more complex ICs like the ADV7511 or the ADV7611 can also have internal I2C bus structures to communicate with sub-components (e.g., the ADV7611 is comprised of 7

I2C sub-devices with the EDID EEPROM being one of them).

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Hardware Architecture

Sobel Edge Detection

Sobel edge detection is a classical algorithm in the field of image and video processing for the extraction of object edges. Edge detection using Sobel operators works on the premise of computing an estimate of the first derivative of an image to extract edge information. By computing the x and y direction derivatives of a specific pixel against a neighborhood of surrounding pixels, it is possible to extract the boundary between two distinct elements in an image. Due to the computational load of calculating derivatives using squaring and square root operators, fixed coefficient masks have been adopted as a suitable approximation in computing the derivative at a specific point. In the case of Sobel, the masks used are shown in

Table 2-8

Table 2-8:

Sobel Operator Masks

-1

0

1

-2

0

2

-1

0

1

-1

-2

-1

0

0

0

1

2

1

The visual effect of applying a Sobel operation on a frame of video or an image is shown in

Figure 2-3

.

X-Ref Target - Figure 2-3

Sobel

HW Core

X890_01_092412

Figure 2-3:

Sobel Edge Detection

There are different ways of implementing the C code for Sobel edge detection depending on the target execution platform and performance requirements. The sobel implementation is in /hardware/vivado_hls/src/sobel.cpp.

The C code shows that applying the masks of

Figure 2-3 to an image creates a

two-dimensional traversal in memory along a 3 x 3 window. Because this window accesses different rows in the image, the benefits of memory locality to reduce memory bandwidth requirements are limited.

To achieve the target performance of 60 frames per second at 1080p, the inner for-loops computing x_weight and y_weight must be fully unrolled.

Complete unrolling of the inner for-loop structure in the context of the HLS tool has the effect of exposing the entire datapath for the computation of the gradient at a pixel to the compiler. It also exposes all the memory accesses required to complete the computation as fast as possible. In this case, achieving maximum performance requires nine read operations to the memory storing the input image to construct the 3 x 3 window on which

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Software Architecture

the gradient is computed. This creates a memory bandwidth bottleneck, which must be addressed at the algorithmic level.

As described in Implementing Memory Structures for Video Processing in the Vivado HLS Tool

(XAPP793)

[Ref 11]

, the algorithm targeted at the HLS tool must have a notion of proper memory architecture for achieving performance. In the context of Sobel edge detection, proper memory architecture requires only a single access to the global memory storing the input image and local buffer storage to create the 3 x 3 computation window. Line buffers and other memory structures must be part of the C code given to the HLS tool in order to generate the correct design. Implementing Memory Structures for Video Processing in the

Vivado HLS Tool provides the details on how to create line buffers and memory structures for image and video processing. The code in the TRD has been modified to express tiered memory architecture to meet the performance requirements of the design.

Software Architecture

This section explains the software architecture for the Zynq-7000 AP SoC ZC702 Base TRD.

Figure 2-4

illustrates a top-level view of the software architecture.

A multi-threaded Linux application is responsible for running the TRD demonstration. This application uses the Qt-based GUI, which is displayed through Display Monitor, to obtain user inputs. Depending on the inputs, it calls device drivers to configure the hardware and to enable a particular data path.

The Zynq Base TRD uses PetaLinux framework for building/customizing software artifacts.

See

Appendix D, PetaLinux Software Development Kit for more details on PetaLinux SDK.

Three major software components are involved in the Base TRD:

• Xilinx Boot Loader

• Xilinx Linux kernel

• Application

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Software Architecture

X-Ref Target - Figure 2-4

Linux User Space

User Space

Libraries

Zynq-7000 AP SoC

TRD Application

C Libraries

System Calls and Driver Interfaces

Linux Kernel

OS Services

Device Drivers

UIO

Frame

Buffer

USB

GPIO

IIC xvdma

Xilinx

AXI VDMA

HW Access

Hardware

Processor

Subsystem

Clock

Synthesizer

Sobel Filter

VTC

Sobel VDMA

TPG

TPG VDMA

Chroma

Resampler

LogiCVC-ML yuv2rgb

Converter

UG925_c2_02_042313

Figure 2-4:

Software Architecture: Top Level View

Boot Loader

Responsible for the power-on boot-up process, the non-changeable boot code resides in the boot ROM. At power-on, the boot ROM reads the boot mode register to determine the boot mode. The boot mode is user-configurable.

User-Configurable Boot Modes

The user can select one of these boot sources to configure the boot mode:

• SD Card

• Nand flash

• NOR flash

• Quad-SPI flash

• JTAG: No boot source, this mode is used for non-secure debugging

Note:

NAND/NOR flashes are not available on the ZC702 board.

This TRD uses SD card boot mode for booting. For details on pin and jumper configuration for SD boot, see the Zynq-7000 All Programmable SoC: ZC702 Evaluation Kit and Video and

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Software Architecture

Imaging Kit Getting Started Guide (UG926)

[Ref 1]

.

In all modes except JTAG, the boot ROM reads the boot configuration header from the selected boot media, which is based on the boot mode register. In SD Card mode the boot header is located in the BOOT.bin file, located on the first partition of the SD card. For other boot modes, see the Zynq-7000 All Programmable SoC Technical Reference Manual

(UG585)

[Ref 2] .

BOOT.bin File Elements

The BOOT.bin file contains these elements:

Boot header - It contains information about the other contents of BOOT.bin along with their offsets and sizes, as well as whether this is a secure or non-secure boot.

First Stage Boot Loader (FSBL) - FSBL is responsible for initializing the minimum required hardware to program the PL bit stream, and load and execute U-Boot. For details, see

Boot

Loader, page 33

.

Bitstream - PL hardware bit stream that gets programmed in FSBL by CPU instructions.

U-Boot - Second stage boot loader responsible to complete initializing the hardware, and load and execute the Linux kernel. For details, see

Boot Loader, page 33 .

Boot Loader

A two-stage boot loader is used for the Zynq-7000 AP SoC Linux boot-up.

FSBL - Initializes the required hardware in the PS along with PL programming and loads the second-stage boot loader, U-Boot. The FSBL source code is generated through the Xilinx

SDK tool, depending on the hardware design specification.

U-Boot - Loads the kernel image in the DDR memory. U-Boot is an open source universal boot loader used across various embedded platforms. U-Boot uses the boot mode register to determine the location of the kernel image, device tree, and file system to be loaded. The source code, customized for Zynq-7000 AP SoC Linux, is available on the Xilinx Open Source

ARM git Repository: https://github.com/xilinx/ .

Refer to the Zynq-7000 Base Targeted Reference Design wiki page at wiki.xilinx.com/zc702-base-trd.

to build the FSBL and U-Boot, boot image BOOT.bin.

Xilinx Linux Kernel

The Xilinx Linux kernel is based on the mainline open source kernel git tree, adding support for a variety of Xilinx IP core drivers and reference boards. The source code is available on the Xilinx Open Source ARM git Repository: https://github.com/xilinx .

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Software Architecture

The Xilinx Linux kernel is extended (patched) to support functionality specific to the Base

TRD. Patching and building the Linux kernel is explained in the Zynq-7000 Base Targeted

Reference Design wiki page at wiki.xilinx.com/zc702-base-trd.

Table 2-9 lists kernel drivers used for the Base TRD.

Table 2-9:

Linux Kernel Drivers Used by the Base TRD

Linux Driver Function

Frame buffer

Frame buffer

PS - GPIO

Drives the display controller (logiCVC-ML) to display the application UI and control data path

Frame buffer console display

Provides Reset signals to VDMA IPs

XVDMA Controls VDMA IP for various data flows

Xilinx AXI VDMA Provides core AXI VDMA functionality and the actual hardware interface

UIO Generic UIO kernel drivers

Application

Called By

Linux console

Application

Application

XVDMA driver

ADV7511 V4L2 compliant HDMI transmitter driver

UIO userspace drivers for various video IPs

Display Controller (logiCVC-ML)

Frame Buffer Driver

Linux provides a standard frame buffer, which is hardware-independent, and the application can use this buffer without knowing the underlying display controller. The Xylon frame buffer driver for CVC IP is registered with the standard frame buffer driver to provide support for the logiCVC-ML display controller.

The Xylon frame buffer driver is compiled with the kernel and probes for the hardware and resolution specification by scanning the dtb file at boot. If there is no entry for logiCVC-ML

IP in the dtb file, then the driver does not load itself.

The application uses the standard Linux frame buffer driver, which has a character driver interface.

For this Base TRD, /dev/fb0 is the node that is populated. To find the exact device node, iteratively match the id field of structure fb_fix_screeninfo acquired by the

FBIOGET_FSCREENINFO IOCTL call for each device node populated. If the id field is Xylon

FB, the frame buffer driver is for Xylon logiCVC-ML.

Note:

An IOCTL (input/output control) is a general purpose Linux system call used for implementing the interface between a user application and a device driver.

More details on the frame buffer driver is available in kernel documentation at <Linux

Kernel source>/Documentation/fb/framebuffer.txt

.

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Software Architecture

PS-GPIO Driver

The GPIO SYSFS interface is used for GPIO configuration. The GPIO SYSFS interface allows the user to control I/O pins using files under the /sys directory.

When the system boots, all GPIO pins are owned by the kernel. The pins do not show up in the SYSFS system until they are exported. To export them, write the pin number (say 54) to the file /sys/class/gpio/export.

This results in the pseudo files for pin 54 showing up under /sys/class/gpio/gpio54 as:

/sys/class/gpio/gpio54/direction

/sys/class/gpio/gpio54/value

The user can set the direction by writing in or out to the direction file. For the out direction, writing 0 or 1 on the corresponding value file resets or sets the pin, respectively.

Similarly, the user can read the value file for the in direction.

XVDMA Driver

XVDMA is a character driver used for configuring and controlling video DMA transactions for both TPG and Sobel hardware. XVDMA internally calls the Xilinx AXI VDMA driver to complete the task and interrupt handling.

The device node that uses the XVDMA driver is /dev/xvdma. The following IOCTLs are defined for the XVDMA driver and contain the corresponding IOCTL arguments to be used:

• XVDMA_GET_NUM_DEVICES

°

This call obtains the number of VDMA probed and available for use.

Argument: Address of unsigned int [unsigned int *].

°

- This gets filled up with the number of VDMA when the call returns.

• XVDMA_GET_DEV_INFO

°

This call gives device information like channel number, for the given VDMA ID.

Argument: Address of structure xvdma_dev [struct xvdma_dev *].

°

- Before calling, the device_id field of this structure should be filled with VDMA

ID. On return the rest of the structure is filled by the driver.

• XVDMA_DEVICE_CONTROL

°

°

This call sets the VDMA channel configuration.

Argument: Address of structure xvdma_chan_cfg [struct xvdma_chan_cfg *].

- Before calling, this structure should be filled with required channel configurations.

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Software Architecture

- To reset VDMA, only fill chan = <channel id> and config.reset = 1 fields of structure.

• XVDMA_PREP_BUF

°

This call sets the buffer configurations.

Argument: Address of structure xvdma_buf_info [struct xvdma_buf_info *].

°

- Before calling, this structure should be filled with required buffer configurations.

• XVDMA_START_TRANSFER

°

This call triggers the VDMA transfer.

Argument: Address of structure xvdma_transfer [struct xvdma_transfer *].

°

- Before calling, this structure should be filled. The structure specifies the channel

ID and whether the call is synchronous or asynchronous.

• XVDMA_STOP_TRANSFER

°

°

This call stops the VDMA.

Argument: Address of the unsigned int variable [unsigned int *].

- Before calling, this int variable should be filled with the channel ID.

Structures used for the above IOCTL are defined in the driver_include.h file, which is part of the application source code provided with the Base TRD. The file contains comments explaining each field of the structure.

Xilinx AXI VDMA

This driver is not used by the application. It is internally called by XVDMA to perform operations on video DMA hardware.

ADV7511 V4L2 Driver

The ADV7511 V4L2 driver is Linux V4L2 framework-compliant; it controls the ADV 7511

HDMI transmitter and registers itself as an I2C device driver. The Xylon frame buffer driver makes use of the APIs exported by the driver to stream HDMI content.

Source path - The driver resides at /drivers/media/i2c/adv7511.c in Linux kernel sources

Control operations supported - Only s_cntrl is supported to set a new control value.

V4L2 I2C sub-devices and operations support -

Table 2-10

shows driver operations support for sub-devices.

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Software Architecture

Table 2-10:

ADV7511 V4L2 Driver I2C Sub-device and Operations Support

Sub-device

Core

Video

Audio

Supported Operations

log_status g_chip_ident s_power interrupt_service_routine ioctl s_stream s_dv_timings g_dv_timings enum_mbus_fmt g_mbus_fmt try_mbus_fmt s_mbus_fmt enum_dv_timings dv_timings_cap s_stream s_clock_freq s_i2s_clock_freq s_routing

Xylon Frame Buffer Driver

The Xylon frame buffer driver provides user space applications interfaces to logiCVC-ML IP core (compatible = "xylon, logicvc-2.05.c", "xylon, logicvc-3.00.a"), adhering to the frame buffer (FB) concept. The FB concept is central to video on Linux.

The Xylon FB driver offers these features:

• Resolutions starting from 64x1 to 2048x2048.

• Up to 5 layers supported.

• Last layer configurable as background color.

• Configurable layer size and position.

• Support for Alpha blending and Color keyed transparency.

• Pixel, Layer or Color lookup table alpha blending mode.

• Programmable layer memory base address and stride.

• Double/triple buffering enables flicker-free reproduction.

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Software Architecture

• Display power-on sequencing control signals.

• Driver Interfaces with ADV7511 HDMI transmitter V4L2 driver to get EDID parameters and initialize logiCVC accordingly to display a preferred resolution.

• Pixel clock frequency supported with:

°

Zynq-PS

°

SI570 hardware (ZC702 board)

° logiCLK IP core (ZED and other boards)

Supported FB operations - Table 2-11 shows the supported operations for the Xylon FB driver.

Table 2-11:

Xylon Frame Buffer Driver Supported Operations

Sr No.

1

2

Operations

fb_open fb_release

5

6

3

4 fb_check_var fb_set_par fb_setcolreg fb_setcmap

7

8 fb_blank fb_pan_display

9 fb_fillrect

10 fb_copyarea

11 fb_imageblit

Description

Open device file

Close device file

Sanity check on video parameters

Configure video controller registers

Create pseudo color palette map

Set color registers in batch

Blank/Un-blank display

Pan display

Draw a rectangle

Copy data from one area to another

Draw image on display

Xylon FB driver custom IOCTLs - Table 2-12 shows the custom ioctl system calls (IOCTL) for the Xylon FB driver.

Table 2-12:

Custom IOCTL Calls for the Xylon FB Driver

Sr. No.

5

6

3

4

1

2

7

8

System Call

XYLONFB_GET_LAYER_IDX

XYLONFB_GET_LAYER_ALPHA

XYLONFB_SET_LAYER_ALPHA

XYLONFB_LAYER_COLOR_TRANSP

XYLONFB_GET_LAYER_COLOR_TRANSP

XYLONFB_SET_LAYER_COLOR_TRANSP

XYLONFB_GET_LAYER_SIZE_POS

XYLONFB_SET_LAYER_SIZE_POS

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Software Architecture

Table 2-12:

Custom IOCTL Calls for the Xylon FB Driver (Cont’d)

Sr. No.

12

13

14

15

9

10

11

16

System Call

XYLONFB_GET_LAYER_BUFFER

XYLONFB_SET_LAYER_BUFFER

XYLONFB_GET_LAYER_BUFFER_OFFSET

XYLONFB_GET_BACKGROUND_COLOR

XYLONFB_SET_BACKGROUND_COLOR

XYLONFB_LAYER_EXT_BUFF_SWITCH

XYLONFB_READ_HW_REG

XYLONFB_WRITE_HW_REG

Xylon FB driver-specific SW parameters - Table 2-13 shows software parameters specific to the Xylon FB driver.

Table 2-13:

Xylon FB Driver-specific Software Parameters

Parameter Description

pixel-data-invert pixel-clock-active-high logiCVC sends inverted pixel data towards display logiCVC transmits pixel data on rising pixel clock edge pixel-component-format ARGB or RGBA pixel-component-layer Number of logiCVC layer which uses RGBA format active-layer videomode

Ordinal number of logiCVC layer which is used for system console

Display resolution for which logiCVC will be initialized in HRESxVRES text format

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Software Architecture

Application

Figure 2-5

describes various components of the application.

X-Ref Target - Figure 2-5

User Space

Application

Graphical User Interface

Pthread

Libraries Control and

Decision

Making

User Space

Device Control

Software Sobel

Filter Processing

Accessing

Memory-Mapped

Hardware

Kernel

Driver

Calls

Kernel

Driver

Calls

Qt

Libraries

Kernel Space Drivers

HW

Access

Hardware

UG925_c2_03_061312

Figure 2-5:

Application Functional Blocks

The application is divided into the following functional blocks:

• GUI

• Control and decision making

• User space device control

• Software Sobel filter processing

The first three components run in one thread of the application, while the software Sobel filter runs in a second separate thread. The Linux kernel is in SMP mode and both the cores are utilized for running different threads. At run time, the kernel assigns one of the cores for software Sobel filter processing and other core for running the rest of the application and the operating system.

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Software Architecture

Graphical User Interface

The GUI for this Base TRD is designed using the Qt framework (see

Figure 2-6

).

X-Ref Target - Figure 2-6

Figure 2-6:

GUI for TRD Application

UG925_c2_05_011813

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Software Architecture

In

Figure 2-7

, the grey screen at the bottom is the GUI. The GUI can be minimized or maximized with the MIN/MAX button on the right side. The complete screen is the Video

(or display) area, where the pattern or video is displayed. There is a Transparency slider that makes the GUI semi-transparent. The bottom portion of the GUI consists of the ZYNQ banner, a pictorial view of Operation Mode and two graphs, which are only available in the

MAX GUI mode. All other controls are available in both the MAX and MIN GUI mode.

X-Ref Target - Figure 2-7

UG925_c2_04_051313

Figure 2-7:

Minimized GUI Mode

Figure 2-8

shows the minimized (MIN) GUI mode.

The main functionality of the GUI includes:

• Getting user inputs

• Plotting graphs

• Displaying the video area

Get User Inputs

The Qt framework provides for having the mouse as input device (it internally uses Linux

USB-HID class drivers). The input from the user includes video Enable/Disable, Input

Source Select, Sobel Control Settings, and Mode Select for the video pipeline.

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Software Architecture

Plot Graph

Two graphs are plotted using the Qt framework. The first graph demonstrates CPU utilization for each ARM core, and the second demonstrates AXI memory bandwidth utilization on HP0 and HP2 ports.

In the CPU utilization graph, the horizontal axis is for time and the vertical axis is for the percentage of CPU utilization.

In the memory bandwidth graph, the horizontal axis is for time and the vertical axis is for the Gb/s of read and write transactions on AXI.

Along with the graphs, the utilization and bandwidth numbers are also displayed above the graphs. These numbers are available in both MIN and MAX GUI mode.

Display Video Area

This is the full screen area, where the output of the video pipeline is displayed.

Control and Decision Making

This block receives input from the GUI and maintains the state transition for the complete application. It communicates with all other blocks of the application and with the kernel drivers to change the state of hardware.

The following hardware is configured through this control block using the kernel drivers mentioned in

Xilinx Linux Kernel :

• VDMA (using the XVDMA driver)

• VDMA reset and multiplexer switching for external video (using the GPIO driver)

• logiCVC-ML control (using the frame buffer driver)

Data Flow Use Cases

The video source can be either the video TPG (internal) or an external video source (HDMI

IN). The six combinations of data flow use cases are listed in this section. Use cases 1, 2, and

3 use the TPG and use cases 4, 5, and 6 use external video as video source.

The Sobel filter can either be a software or hardware implementation or it is bypassed entirely (turned off). Use cases 1 and 4 have the filter turned off, use cases 2 and 5 refer to the software implementation, and use cases 3 and 6 refer to the hardware implementation.

Figure 2-8

combines TPG/external video in one functional block.

Figure 2-9

combines software and hardware implementation in one functional block, therefore, use cases 4, 5, and 6 refer to both

Figure 2-8

and

Figure 2-9

.

There are six combinations of the data flow:

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Software Architecture

1. The TPG creates and writes the pattern in reserved video memory in DDR. The display controller displays video memory (TPG pattern) as shown in

Figure 2-8

.

X-Ref Target - Figure 2-8

Internal Video

Pattern (TPG)

Video Memory

Intermediate

Memory

Display

Controller

Software/

Hardware

Sobel Filter

Output to Monitor

UG925_c2_06_110412

Figure 2-8:

Video Display Pipeline Data Flow

2.

Figure 2-9

shows the software Sobel filter configuration. The TPG creates and writes the pattern in intermediate DDR memory. The software Sobel filter reads the intermediate

DDR memory, detects the edges, and writes the filtered image in the reserved video memory in DDR. The display controller displays video memory (filtered TPG pattern) as shown in

Figure 2-9

.

X-Ref Target - Figure 2-9

Internal Video

TPG/External

Video

(HDMI IN)

Video Memory

Display

Controller

Output to Monitor

UG925_c2_07_110412

Figure 2-9:

Video Processing and Display Pipeline Data Flow

3.

Figure 2-9 shows the hardware Sobel filter configuration. The TPG creates and writes

the pattern in intermediate DDR memory. The hardware Sobel filter reads the intermediate DDR memory (using VDMA), detects the edge, and writes the filtered image in the reserved video memory in DDR (using VDMA). The display controller displays video memory (filtered TPG pattern).

Similarly, there are three more cases (4, 5, and 6) where instead of an internally generated pattern, external video is used. See

Figure 2-8

and

Figure 2-9 with external video (HDMI IN)

used instead of TPG for the video source. Cases 4, 5, and 6 are the same as cases 1, 2, and

3 with the only difference being the input source. In cases 1, 2, and 3, the input comes from

TPG, whereas in cases 4, 5, and 6, the input comes from external video.

User Space Device Control

In many cases it is not necessary to write a custom kernel driver simply to access some memory-mapped registers in a custom IP core. The Userspace IO (UIO) framework permits simple user space interrupt handling. Such IPs can be configured and controlled from the user space by using UIO Framework drivers.The UIO framework was designed to allow a light weight, low overhead access to hardware devices directly from user space.

These IPs are configured and controlled from the user space:

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Software Architecture

• TPG

• Video Timing Controller

• Croma Resampler

• YUV to RGB Converter

• AXI performance Monitor

The APIs to configure these IPs are explained in the sobel_lib (common library for sobel

QT and cmd application), which is part of the application source code provided with the

Base TRD.

Software Sobel Filter Processing

This section describes the implementation of the software Sobel filter algorithm for edge detection. The algorithm runs in a separate thread and is turned On and Off by the controlling block. The application is compiled with the highest compiler optimization level

(O3), so that the algorithm gives best performance. This algorithm takes the buffer address of the original frame as input and writes the filter image on the buffer address provided as output.

The following API is used for software Sobel filter processing: void img_process(ZNQ_S32 *rgb_in_strm32, ZNQ_S32 *rgb_out_strm32, int height, int width, int stride);

An object’s edge detection filter algorithm for imaging/video looks for gradient magnitude changes in the image background and processing is performed in both the horizontal and vertical directions. The algorithm takes the RGB raw formatted image and detects the image object’s edges based on the pixel luminance values.

Input : ZNQ_S32 *rgb_data_in

The implemented Sobel filter algorithm expects each pixel is a 32-bit ARGB integer with each color as 8-bit depth. A pointer to the ARGB pixel array is provided on a per frame basis.

Output : ZNQ_S32 *rgb_data_out

The implemented algorithm computes each output pixel's value of the frame using the

Sobel filter edge detection algorithm. This function returns a 32-bit edge-detected ARGB array of the frame with each color as 8-bit depth.

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Appendix A

Register Description

This appendix describes the details about configuration and control registers most commonly accessed by the Linux driver and application. The registers implemented in hardware are memory-mapped to the PS address range directly.

Sobel Filter Registers

The Sobel filter registers are used to configure and control various internal features within the Sobel filter logic.

Base address

Version

0x400D0000

N/A

Control and Status Register

The relative address of the Control and Status register is 0x00.

Table A-1

describes this register's structure.

Relative address

0x00

Table A-1:

Control and Status Register

Bit Position Mode

31:8-6:4

7

-

RW

3 R

2 R

1

0

COR

RW/SC

Default Value

-

0x0

0x1

0x1

0x0

0x0

Description

Reserved.

Auto Restart

IP is ready to accept new data.

IP is idle.

Frame process is done.

Start processing the frame.

Global Interrupt Enable Register

The relative address of the Global Interrupt Enable register is 0x04. Table A-2 describes this

register's structure.

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Sobel Filter Registers

Relative address

0x04

Table A-2:

Global Interrupt Enable Register

Bit Position

31:1

0

Mode

-

RW

Default Value

-

0x0

Description

Reserved.

Global interrupt enable.

Interrupt Enable Register

The relative address of the Interrupt Enable register is 0x08.

Table A-3

describes this register's structure.

Relative address

0x08

Table A-3:

Interrupt Enable Register

Bit Position

31:1

0

Mode

-

RW

Default Value

-

0x0

Description

Reserved.

Frame processing done interrupt enable.

Interrupt Status Register

The relative address of the Interrupt Status register is 0x0C.

Table A-4 describes this

register's structure.

Relative address

0x0C

Table A-4:

Interrupt Status Register

Bit Position

31:2

1

0

Mode

-

RW

RW

Default Value

-

0x0

0x0

Description

Reserved.

IP ready interrupt status.

Frame processing done interrupt status.

Number of Rows Register

The relative address of the Number of Rows register is 0x14.

Table A-5 describes this

register's structure.

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Sobel Filter Registers

Relative address

0x14

Table A-5:

Number of Rows Register

Bit Position

31:0

Mode

RW

Default Value

-

Description

Number of rows in a frame.

Number of Columns Register

The relative address of the Number of Columns register is 0x1C.

Table A-6 describes this

register's structure.

Relative address

0x1C

Table A-6:

Number of Columns Register

Bit Position

31:0

Mode

RW

Default Value

-

Description

Number of columns in a frame.

XR0C0 Coefficient Register

The relative address of the XR0C0 Coefficient Register is 0x24. Table A-7 describes this register's structure.

Relative address

0x24

Table A-7:

XR0C0 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

XR0C0 coefficient for Sobel filtering.

XR0C1 Coefficient Register

The relative address of the XR0C1 Coefficient Register is 0x2C. Table A-8 describes this register's structure.

Relative address

0x2C

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Sobel Filter Registers

Table A-8:

XR0C1 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

XR0C1 coefficient for Sobel filtering.

XR0C2 Coefficient Register

The relative address of the XR0C2 Coefficient Register is 0x34.

Table A-9 describes this

register's structure.

Relative address

0x34

Table A-9:

XR0C2 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

XR0C2 coefficient for Sobel filtering.

XR1C0 Coefficient Register

The relative address of the XR1C0 Coefficient Register is 0x3C.

Table A-10 describes this

register's structure.

Relative address

0x3C

Table A-10:

XR1C0 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

XR1C0 coefficient for Sobel filtering.

XR1C1 Coefficient Register

The relative address of the XR1C1 Coefficient Register is 0x44.

Table A-11 describes this

register's structure.

Relative address

0x44

Table A-11:

XR1C1 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

XR1C1 coefficient for Sobel filtering.

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Sobel Filter Registers

XR1C2 Coefficient Register

The relative address of the XR1C2 Coefficient Register is 0x4C.

Table A-12 describes this

register's structure.

Relative address

0x4C

Table A-12:

XR1C2 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

XR1C2 coefficient for Sobel filtering.

XR2C0 Coefficient Register

The relative address of the XR2C0 Coefficient Register is 0x54.

Table A-13 describes this

register's structure.

Relative address

0x54

Table A-13:

XR2C0 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

XR2CO coefficient for Sobel filtering.

XR2C1 Coefficient Register

The relative address of the XR2C1 Coefficient Register is 0x5C.

Table A-14 describes this

register's structure.

Relative address

0x5C

XR2C2

Table A-14:

XR2C1 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

XR2C1 coefficient for Sobel filtering.

XR2C2 Coefficient Register

The relative address of the XR2C2 Coefficient Register is 0x64.

Table A-15 describes this

register's structure.

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Sobel Filter Registers

Relative address

0x64

Table A-15:

XR2C2 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

XR2C2 coefficient for Sobel filtering.

YR0C0 Coefficient Register

The relative address of the YR0C0 Coefficient Register is 0x6C.

Table A-16

describes this register's structure.

Relative address

0x6C

Table A-16:

YR0C0 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

YR0C0 coefficient for Sobel filtering.

YR0C1 Coefficient Register

The relative address of the YR0C1 Coefficient Register is 0x74.

Table A-17

describes this register's structure.

Relative address

0x74

Table A-17:

YR0C1 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

YR0C1 coefficient for Sobel filtering.

YR0C2 Coefficient Register

The relative address of the YR0C2 Coefficient Register is 0x7C.

Table A-18

describes this register's structure.

Relative address

0x7C

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Sobel Filter Registers

Table A-18:

YR0C2 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

YR0C2 coefficient for Sobel filtering.

YR1C0 Coefficient Register

The relative address of the YR1C0 Coefficient Register is 0x84.

Table A-19

describes this register's structure.

Relative address

0x84

Table A-19:

YR1C0 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

YR1C0 coefficient for Sobel filtering.

YR1C1 Coefficient Register

The relative address of the YR1C1 Coefficient Register is 0x8C.

Table A-20

describes this register's structure.

Relative address

0x8C

Table A-20:

YR1C1 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

YR1C1 coefficient for Sobel filtering.

YR1C2 Coefficient Register

The relative address of the YR1C2 Coefficient Register is 0x94.

Table A-21

describes this register's structure.

Relative address

0x94

Table A-21:

YR1C2 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

YR1C2 coefficient for Sobel filtering.

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Sobel Filter Registers

YR2C0 Coefficient Register

The relative address of the YR2C0 Coefficient Register is 0x9C.

Table A-22

describes this register's structure.

Relative address

0x9C

Table A-22:

YR2C0 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

YR2C0 coefficient for Sobel filtering.

YR2C1 Coefficient Register

The relative address of the YR2C1 Coefficient Register is 0xA4C.

Table A-23 describes this

register's structure.

Relative address

0xA4

Table A-23:

YR2C1 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

YR2C1 coefficient for Sobel filtering.

YR2C2 Coefficient Register

The relative address of the YR2C2 Coefficient Register is 0xAC.

Table A-24

describes this register's structure.

Relative address

0xAC

Table A-24:

YR2C2 Coefficient Register

Bit Position

31:0

Mode

RW

Default Value

0x0

Description

YR2C2 coefficient for Sobel filtering.

High Threshold Register

The relative address of the High Threshold register is 0xB4. Table A-25 describes this register's structure.

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Sobel Filter Registers

Relative address

0xB4

Table A-25:

High Threshold Register

Bit Position

31:8

7:0

Mode

-

RW

Default Value

-

0x0

Description

Reserved.

High Threshold for Sobel filtering.

Low Threshold Register

The relative address of the Low Threshold register is 0xBC.

Table A-26 describes this

register's structure.

Relative address

0xBC

Table A-26:

Low Threshold Register

Bit Position

31:8

7:0

Mode

-

RW

Default Value

-

0x0

Description

Reserved.

Low Threshold for Sobel filtering.

Invert Output Register

The relative address of the Invert Output register is 0xC4.

Table A-27 describes this

register's structure.

Relative address

0xC4

Table A-27:

Invert Output Register

Bit Position

31:1

0

Mode

RW

Default Value

0x0

Description

Reserved.

Inverts output of Sobel filter.

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Appendix B

Extended Display Identification Data

The Extended Display Identification Data (EDID) protocol is a standardized means for a display to communicate its operational characteristics, such as native resolution, to a source device. This allows the source to generate the necessary video characteristics to match the needs of the display. Because the source generates the necessary video characteristics, this removes dependency on the user to configure the source and display device, thus reducing the potential for incorrect settings and adjustments.

Storing and Programming EDID data

The EDID data bytes (stored as a part of the FSBL) are binary and are programmed by FSBL logic into EDID RAM (ADV7611) during system initialization, for transmission to the video source device. This EDID data is read by the video source, and video is output accordingly by the source.

Contents of EDID data can be modified by the ADVANTIV EDID editor: http://ez.analog.com/docs/DOC-2143

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Appendix C

Directory Structure

This appendix describes the directory structure and organization of the files and folders delivered with the package.

X-Ref Target - Figure C-1

Included Files and Systems

Figure C-1

gives a top-level view of the directories and files included in the Zynq-7000 All

Programmable SoC (AP SoC) ZC702 Base TRD package.

Table C-1 summarizes how the

directories provided relate to this user guide. This user guide uses the directories in the extracted Base TRD zipped package and assumes that the directories and files are placed or copied onto the user's local computer.

zc702-zvik-base-trd-rdf0286 doc lgpl-2.1.txt

README.txt

ready_to_test

BOOT.bin

image.ub

hardware vivado vivado_hls software petalinux patch workspace

UG927_aC_01_092413

Figure C-1:

Directory Structure

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Included Files and Systems

Table C-1:

Explanation of Directories in the Zynq-7000 AP SoC ZC702 Base TRD File System

Directory Purpose

doc hardware

This directory contains the documents provided with the Zynq-7000 AP SoC ZC702

Base TRD, including this user guide.

ready_to_test

This directory contains a pre-built hardware design and software executables which provide a quick way to run the video demonstration. The application binary images are compatible to boot from the SD MMC and run the Linux application.

This directory includes the Zynq-7000 AP SoC ZC702 Base TRD hardware design and

VHLS project to build Sobel Filter IP.

sw

This directory includes the Base TRD applications source code, hardware platform exported from the Vivado Design Suite tool, and PetaLinux configuration files. The included ISE-SDK project can be used to build the application. It also includes the

Zynq Base TRD patches to the Xilinx Linux kernel.

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Appendix D

PetaLinux Software Development Kit

The PetaLinux Software Development Kit (SDK) is a complete embedded Linux distribution and development environment that works with the Xilinx hardware design flow for Xilinx

FPGAs and Zynq™-7000 All Programmable SoCs. Tailored to accelerate design productivity, the solution contains everything necessary to build, develop, test, and deploy Embedded

Linux systems.

PetaLinux consists of three key elements: pre-configured binary bootable images, fully customizable Linux for the Xilinx device, and PetaLinux SDK which includes tools and utilities that automate otherwise complex tasks across configuration, build, and deployment tasks.

This appendix describes the directory structure and organization of the files and folders delivered with the package.

PetaLinux Development Tools (Host)

PetaLinux eases the development of Linux-based products, from system boot to execution, with the following tools:

• Command-line and Eclipse IDE UIs

• Application, Device Driver, and Library generators and development templates

• Bootable system Image builder

• Debug and Trace tools

• GCC tools

• Integrated QEMU Full System Simulator

• Automated tools

PetaLinux capabilities can be integrated into Xilinx SDK to expand Xilinx SDKs from an application development platform to a full system development and deployment solution, and build tools, Root file-system configuration and build, QEMU full system simulator, deploy tools and target boot management.

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PetaLinux Development Tools (Host)

Petalinux SDK provides a framework for building user application, user libraries, Linux, uboot, romfs, etc.

Note:

The Zynq Base TRD uses latest Xilinx Open Source Linux (OSL) kernel, not the default petalinux Linux kernel that comes as a part of PetaLinux SDK. See the following documents for more information.

PetaLinux SDK User Guide: Installation Guide (UG976)

[Ref 13]

PetaLinux SDK User Guide: Getting Started Guide (UG977)

[Ref 14]

PetaLinux SDK User Guide: Board Bringup Guide (UG980)

[Ref 15]

PetaLinux SDK User Guide: Application Development Guide (UG981)

[Ref 16]

These and other Petalinux SDK documents can be found at: www.xilinx.com/support/index.html/content/xilinx/en/supportNav/design_tools/petaLinux

-sdk.html

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Appendix E

Install the Zynq-7000 AP SoC Design and

Development Environment

Install the Xilinx Vivado Design Suite

The user needs to install the Embedded Edition and System Edition of the Xilinx Vivado

Design Suite. See Vivado Design Suite User Guide: Release Notes, Installation (UG973)

[Ref 17]

to install and license the Vivado Design Suite.

Set Up git Tools

Git is a free software tool for managing distributed version control and the development of software project files. A git clone is a full-fledged repository with complete history and full revision tracking capabilities. Git gives the developer a local copy of the entire development project files and their existing (published) history on a git server within a repository organized as a set of directories. A user must clone a file or folder before using the same items from the project repository.

The user needs to have a git client installed on the Linux development PC. Refer to the

Using Git web site ( wiki.xilinx.com/using-git ) for working with Xilinx git and see section 4.2 of Zynq-7000 All Programmable SoC Software Developers Guide (UG821)

[Ref 18]

for working with Xilinx git Linux repositories.

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Appendix F

Additional Resources

Xilinx Resources

For support resources such as Answers, Documentation, Downloads, and Forums, see the

Xilinx Support website at: www.xilinx.com/support .

For continual updates, add the Answer Record to your myAlerts: www.xilinx.com/support/myalerts .

For a glossary of technical terms used in Xilinx documentation, see: www.xilinx.com/company/terms.htm

.

Solution Centers

See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips.

References

The most up to date information related to the ZC702 board and its documentation is available on the following websites.

The Xilinx Zynq-7000 SoC ZC702 Evaluation Kit Product Page: www.xilinx.com/zc702

The Zynq-7000 SoC ZC702 Evaluation Kit Master Answer Record: www.xilinx.com/support/answers/47864.htm

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References

The following Xilinx documents provide supplemental material useful with this guide:

1. Zynq-7000 All Programmable SoC: ZC702 Evaluation Kit and Video and Imaging Kit

Getting Started Guide ( UG926 ) (Vivado Design Suite 2013.2)

2. Zynq-7000 All Programmable SoC Technical Reference Manual ( UG585 )

3. LogiCORE IP Processor System Reset Module Product Specification ( PG164 )

4. LogiCORE IP AXI Interconnect ( PG059 )

5. LogiCORE IP AXI Video Direct Memory Access Product Guide ( PG020 )

6. LogiCORE IP Video Timing Controller Product Guide ( PG016 )

7. LogiCORE IP Test Pattern Generator Product Guide (PG103 )

8. LogiCORE IP AXI Performance Monitor Product Guide ( PG037 )

9. LogiCORE IP Chroma Resampler Product Guide ( PG012 )

10. LogiCORE IP YCrCb to RGB Color-Space Converter Product Guide ( PG014 )

11. Implementing Memory Structures for Video Processing in the Vivado HLS Tool ( XAPP793 )

12. LogiCORE IP Video In to AXI4-Stream v1.0 ( PG043 )

13. PetaLinux SDK User Guide: Installation Guide ( UG976 )

14. PetaLinux SDK User Guide: Getting Started Guide ( UG977 )

15. PetaLinux SDK User Guide: Board Bringup Guide ( UG980 )

16. PetaLinux SDK User Guide: Application Development Guide ( UG981 )

17. Vivado Design Suite User Guide: Release Notes, Installation ( UG973 )

18. Zynq-7000 All Programmable SoC Software Developers Guide ( UG821 )

19. Xilinx Design Tools: Installation and Licensing Guide ( UG798 )

20. Zynq-7000 All Programmable SoC: Concepts, Tools, and Techniques Guide ( UG873 )

21. Quick Front-to-Back Overview Tutorial: PlanAhead Design Tool ( UG673 )

22. Zynq-7000 All Programmable SoC Overview ( DS190 )

23. Vivado Design Suite Migration Methodology Guide ( UG911 )

More information on Zynq-7000 family boards, FMC extension cards, and other kits based on Zynq-7000 architecture is available at the following websites.

Xilinx Zynq-7000 All Programmable SoC Boards and Kits www.xilinx.com/products/boards_kits/zynq-7000.htm

Xilinx Zynq-7000 Base Targeted Reference Design wiki page: wiki.xilinx.com/zc702-base-trd

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Additional References

These Xilinx documents and websites provide supplemental material useful with this guide:

Xilinx Open Source ARM git Repository: github.com/xilinx.com/

Xilinx ARM GNU Tools: wiki.xilinx.com/zynq-tools

Using Git: wiki.xilinx.com/using-git git: the fast version control system home page: git-scm.com/

Xilinx Zynq-7000 All Programmable SoC website www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm

Zynq-7000 All Programmable SoC product table www.xilinx.com/publications/prod_mktg/zynq7000/Zynq-7000-combined-product-tabl e.pdf

Zynq Linux: Downloading the Kernel Tree: xilinx.wikidot.com/zynq-linux#toc7

Zynq Linux: Configuring and Building the Linux Kernel: xilinx.wikidot.com/zynq-linux#toc8

Xilinx Open Source Linux: wiki.xilinx.com/open-source-linux

Xilinx Device Tree Generator: xilinx.wikidot.com/device-tree-generator

Xilinx PlanAhead Design and Analysis Tool website www.xilinx.com/tools/planahead.htm

Additional References

The following external websites provide supplemental material useful with this guide:

Xylon IP Cores - logiCVC-ML Compact Multilayer Video Controller description www.logicbricks.com/Products/logiCVC-ML.aspx

Qt Online Reference Documentation. Qt is a toolkit for creating GUIs.

doc.qt.nokia.com/

Device Tree general information devicetree.org/Main_Page

AMBA AXI4-Stream Protocol Specification infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0051a/index.html

PCI-SIG Documentation www.pcisig.com/specifications

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Additional References

logiCVC-ML Compact Multilayer Video Controller Data Sheet www.logicbricks.com/Documentation/Datasheets/IP/logiCVC-ML_hds.pdf

Silicon Labs CP210x USB to UART Bridge VCP Drivers www.silabs.com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.aspx

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Appendix G

Regulatory and Compliance Information

This product is designed and tested to conform to the European Union directives and standards described in this section.

Declaration of Conformity

To view the Declaration of Conformity online, please visit: http://www.xilinx.com/support/documentation/boards_and_kits/ce-declarations-of-con formity-xtp251.zip

Directives

2006/95/EC, Low Voltage Directive (LVD)

2004/108/EC, Electromagnetic Compatibility (EMC) Directive

Standards

EN standards are maintained by the European Committee for Electrotechnical

Standardization (CENELEC). IEC standards are maintained by the International

Electrotechnical Commission (IEC).

Electromagnetic Compatibility

EN 55022:2010, Information Technology Equipment Radio Disturbance Characteristics –

Limits and Methods of Measurement

EN 55024:2010, Information Technology Equipment Immunity Characteristics – Limits and

Methods of Measurement

This is a Class A product. In a domestic environment, this product can cause radio interference, in which case the user might be required to take adequate measures.

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Markings

Safety

IEC 60950-1:2005, Information technology equipment – Safety, Part 1: General requirements

EN 60950-1:2006, Information technology equipment – Safety, Part 1: General requirements

Markings

This product complies with Directive 2002/96/EC on waste electrical and electronic equipment (WEEE). The affixed product label indicates that the user must not discard this electrical or electronic product in domestic household waste.

This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment.

This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive.

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Appendix H

Warranty

THIS LIMITED WARRANTY applies solely to standard hardware development boards and standard hardware programming cables manufactured by or on behalf of Xilinx

(“Development Systems”). Subject to the limitations herein, Xilinx warrants that

Development Systems, when delivered by Xilinx or its authorized distributor, for ninety (90) days following the delivery date, will be free from defects in material and workmanship and will substantially conform to Xilinx publicly available specifications for such products in effect at the time of delivery. This limited warranty excludes: (i) engineering samples or beta versions of Development Systems (which are provided “AS IS” without warranty); (ii) design defects or errors known as “errata”; (iii) Development Systems procured through unauthorized third parties; and (iv) Development Systems that have been subject to misuse, mishandling, accident, alteration, neglect, unauthorized repair or installation. Furthermore, this limited warranty shall not apply to the use of covered products in an application or environment that is not within Xilinx specifications or in the event of any act, error, neglect or default of Customer. For any breach by Xilinx of this limited warranty, the exclusive remedy of Customer and the sole liability of Xilinx shall be, at the option of Xilinx, to replace or repair the affected products, or to refund to Customer the price of the affected products.

The availability of replacement products is subject to product discontinuation policies at

Xilinx. Customer may not return product without first obtaining a customer return material authorization (RMA) number from Xilinx.

THE WARRANTIES SET FORTH HEREIN ARE EXCLUSIVE. XILINX DISCLAIMS ALL OTHER

WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT

LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT, AND ANY WARRANTY THAT MAY ARISE FROM

COURSE OF DEALING, COURSE OF PERFORMANCE, OR USAGE OF TRADE. (2008.10)

Do not throw Xilinx products marked with the “crossed out wheeled bin” in the trash.

Directive 2002/96/EC on waste electrical and electronic equipment (WEEE) requires the separate collection of WEEE. Your cooperation is essential in ensuring the proper management of WEEE and the protection of the environment and human health from potential effects arising from the presence of hazardous substances in WEEE. Return the marked products to Xilinx for proper disposal. Further information and instructions for free-of-charge return available at: http:\\www.xilinx.com\ehs\weee.htm

.

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