Datasheet | Cool-Icam Stylus 1500 Technical data

Freescale Semiconductor

Technical Data

Power Management Integrated

Circuit (PMIC) for i.MX35/51

The MC13892 is a Power Management Integrated Circuit (PMIC) designed specifically for use with the Freescale i.MX35 and i.MX51 families. It is also compatible with the i.MX27, i.MX31, and i.MX37 application processors targeting netbooks, ebooks, smart mobile devices, smart phones, personal media players, and portable navigation devices. This device is powered by SMARTMOS technology.

Features

• Battery charger system for wall charging and USB charging

• 10-bit ADC for monitoring battery and other inputs, plus a coulomb counter support module

• Four adjustable output buck regulators for direct supply of the processor core and memory

• 12 adjustable output LDOs with internal and external pass devices

• Boost regulator for supplying RGB LEDs

• Serial backlight drivers for displays and keypad, plus RGB LED drivers

• Power control logic with processor interface and event detection

• Real time clock and crystal oscillator circuitry, with coin cell backup and support for external secure real time clock on a companion system processor IC

• Touch screen interface

• SPI/I

2

C bus interface for control and register access

Document Number: MC13892

Rev. 19.0, 4/2014

13892

POWER MANAGEMENT

VK SUFFIX

98ASA10820D

139-PIN 7X7MM BGA

VL SUFFIX

98ASA10849D

186-PIN 12X12MM BGA

ORDERING INFORMATION

See Device Variation Table on Page 2.

Stereo

Loudspeakers

Line

In/Out

Audio

IC

Stereo headphones

Li Ion

Battery

Coin Cell

Battery

MC13892

Power Mgmt &

AP

Aud& Pwr Mgmt

UI

Backlight

RGB

Color

Indicators

Touch

Screen

Figure 1. MC13892 Typical Operating Circuit

© Freescale Semiconductor, Inc., 2010 - 2014. All rights reserved.

DEVICE VARIATIONS

DEVICE VARIATIONS

Table 1. MC13892 Device Variations

Part Number

(1)

Notes Package

Temperature

Range (T

A

)

Pin Map Description

MC13892CJVK

MC13892AJVK

MC13892DJVK

MC13892BJVK

MC13892VK

MC13892JVK

MC13892CJVL

MC13892AJVL

MC13892DJVL

MC13892BJVL

MC13892VL

MC13892JVL

(2)

(3)

(2) (4)

(3)

(3)

(3)

(2)

(3)

(2) (4)

(3)

(3)

(3)

139-PIN

7x7 mm BGA

186-PIN

12x12 mm BGA

-40 to +85 °C

Figure 3

Figure 4

Global Reset Function Default ON

Global Reset Function Default OFF

No Global Reset Function

Global Reset Function Default ON

Global Reset Function Default OFF

No Global Reset Function

Notes

1.

For Tape and Reel product, add an “R2” suffix to the part number.

2.

Recommended for all new designs

3.

Not recommended for new designs

4.

Backward compatible replacement part for MC13892VK, MC13892JVK, MC13892VL, MC13892JVL, MC13892BJVK, and

MC13892BJVL

MC13892

2

Analog Integrated Circuit Device Data



Freescale Semiconductor

INTERNAL BLOCK DIAGRAM

INTERNAL BLOCK DIAGRAM

GNDADC

ADIN5

ADIN6

ADIN7

TSX1

TSX2

TSY1

TSY2

TSREF

ADTRIG

BATTISNSCC

CFP

CFM

Battery Interface &

Protection

Charger Interface and Control:

4 bit DAC, Clamp, Protection,

Trickle Generation

LICELL, UID, Die Temp, GPO4

Voltage /

Current

Sensing &

Translation

Touch

Screen

Interface

BATT

MUX

Coulomb

Counter

10 Bit GP

ADC

Trigger

Handling

CCOUT

To SPI

A/D Result

A/D

Control

SPIVCC

CS

CLK

MOSI

MISO

GNDSPI

VCORE

VCOREDIG

REFCORE

GNDCORE

UID

UVBUS

VBUSEN

VINUSB

VUSB

OTG

5V

VUSB

Regulator

LICELL

BP

Li Cell

Charger

SPI

Interface

+

Muxed

I2C

Optional

Interface

Reference

Generation

Backlight

LED Drive

Die Temp &

Thermal Warning

Detection

To Interrupt

Section

Tri-Color

LED Drive

SW1

1050 mA

Buck

SW2

800 mA

Buck

SW3

800 mA

Buck

SW4

800 mA

Buck

DVS

CONTROL

VBUS/ID

Detectors

LCELL

Switch

Package Pin Legend

MC13892

IC

Output Pin

Input Pin

Bi-directional Pin

SWBST

300 mA

Boost

Shift Register

SPI

Registers

Shift Register

32 KHz

Internal

Osc

32 KHz

Crystal

Osc

To Enables & Control

MC13892

SPI

Control

Logic

Trim-In-Package

PUMS

Startup

Sequencer

Decode

Trim?

To

Trimmed

Circuits

Control

Logic

SPI Result

Registers

Interrupt

Inputs

Enables &

Control

Core Control Logic, Timers, & Interrupts

PLL

Monitor

Timer

RTC +

Calibration

32 KHz

Buffers

Switchers

Best of

Supply

VSRTC

SPI Control

VVIDEO

VUSB2

VAUDIO

VIOHI

VPLL

VDIG

VCAM

VSD

VGEN1

VGEN2

VGEN3

GPO

Control

PWR Gate

Drive & Chg

Pump

PWGTDRV1

PWGTDRV2

O/P

Drive

O/P

Drive

O/P

Drive

O/P

Drive

SW1IN

SW1OUT

GNDSW1

SW1FB

SW2IN

SW2OUT

GNDSW2

SW2FB

SW3IN

SW3OUT

GNDSW3

SW3FB

SW4IN

SW4OUT

GNDSW4

SW4FB

DVS1

DVS2

O/P

Drive

SWBSTIN

SWBSTOUT

SWBSTFB

GNDSWBST

GNDREG1

GNDREG2

GNDREG3

Pass

FET

Pass

FET

Pass

FET

Pass

FET

Pass

FET

Pass

FET

Pass

FET

VCAM

VSDDRV

VSD

VGEN1DRV

VGEN1

VGEN2DRV

VGEN2

VINGEN3DRV

VGEN3

VVIDEODRV

VVIDEO

VINUSB2

VUSB2

VINAUDIO

VAUDIO

VINIOHI

VIOHI

VINPLL

VPLL

VINDIG

VDIG

VINCAMDRV

Figure 2. MC13892 Simplified Internal Block Diagram





MC13892

3

PIN CONNECTIONS

PIN CONNECTIONS

1 2 3 4 5 6 7 8 9 10 11 12 13

A VUSB2 VUSB2 VINUSB2 SWBSTIN GNDSWBST GNDBL NC MODE VCORE BATT CHRGRAW CHRGCTRL2 CHRGCTRL2

B VUSB2 GPO1 DVS2 SWBSTOUT LEDB LEDKP LEDR GNDCORE VCOREDIG BP CHRGCTRL1 BATTISNSCC CHRGCTRL2

C VINPLL VSDDRV

D VUSB VSD SWBSTFB LEDMD DVS1 REFCORE CHRGSE1B LICELL BATTFET

CHRGISNS BATTISNS

BPSNS PWRON1

E

F

G

UVBUS VPLL

GNDSW3 VBUSEN

SW3OUT VINUSB

LEDG GNDLED UID PUMS2 GNDCHRG CHRGLED PWRON2 ADTRIG INT GNDSW1

SW3FB LEDAD GNDSUB GNDSUB GNDSUB GPO3 GPO2 RESETBMCU RESETB SW1OUT

SW4FB GNDREG2 GNDSUB GNDSUB GNDSUB PUMS1 WDI GPO4 SW1IN

H

J

SW3IN

SW4IN

MISO

MOSI

GNDSPI GNDREG3

CLK32KMCU STANDBY

GNDSUB GNDSUB GNDSUB

GNDADC GNDREG1 PWRON3

GNDCTRL

TSX1

SW1FB

SW2FB

STANDBYSEC SW2IN

TSX2 SW2OUT

VVIDEODRV GNDSW2 K SW4OUT SPIVCC

L GNDSW4 CS

PWGTDRV1 CLK32K VCAM CFP CFM ADIN5 ADIN6

TSY2 VVIDEO

M VGEN3 CLK VGEN2 VSRTC GNDRTC VINCAMDRV PWGTDRV2 VDIG VINDIG VGEN1DRV ADIN7 TSY1 TSREF

N VGEN3 VGEN3 VINGEN3DRV VGEN2DRV XTAL2 XTAL1 VINAUDIO VAUDIO VIOHI VINIOHI VGEN1 TSREF TSREF

Regulators

Switchers

Backlights

Control Logic

Charger

RTC

Grounds

USB

ADC

SPI/I2C

No Connect

Figure 3. MC13892VK Pin Connections

MC13892

4





PIN CONNECTIONS

1 2 3 4 5 6 7

VUSB2 VINUSB2 SWBSTOUT SWBSTIN GNDSUB NC A

B VSDDRV GPO1 GNDSUB GNDSUB LEDR UID

8 9

MODE VCORE

10 11

DVS1 REFCORE GNDCORE CHRGSE1B BP

12 13

BATT CHRGRAW CHRGCTRL2 CHRGISNS

14

GNDCHRG BATTISNSCC BATTISNS

C

D

VSD DVS2 SWBSTFB LEDB LEDG LEDKP LEDAD PUMS2 VCOREDIG LICELL BATTFET BPSNS GPO3 PUMS1

VUSB VPLL GNDSUB GNDSUB GNDSWBST GNDLED LEDMD GNDBL CHRGCTRL1 CHRGLED PWRON1 PWRON3 ADTRIG GPO4

UVBUS GNDREG2 VINPLL GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB PWRON2 GPO2 INT RESETBMCU E

F SW3OUT VBUSEN VINUSB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDCTRL WDI RESETB SW1OUT

G GNDSW3 GNDSW3 SW3FB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB SW1FB GNDSW1 GNDSW1

H SW3IN SW3IN GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB SW1IN SW1IN

J

K

SW4IN SW4IN SW4FB

GNDSW4 GNDSW4 SPIVCC GNDSUB

GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB

GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB

SW2FB SW2IN SW2IN

VVIDEODRV GNDSW2 GNDSW2

L SW4OUT CS GNDSPI GNDSUB GNDSUB GNDSUB VCAM VINAUDIO VDIG GNDSUB TSY2 STANDBYSEC VVIDEO SW2OUT

M

N

P

CLK VINGEN3DRV CLK32KMCU CLK32K VSRTC STANDBY VINCAMDRV CFP CFM VGEN1DRV VGEN1 TSX1 TSX2 TSY1

VGEN3 MOSI VGEN2 GNDREG3 XTAL2 XTAL1 VAUDIO PWGTDRV2 VIOHI VINIOHI GNDADC ADIN5 ADIN7 TSREF

MISO PWGTDRV1 VGEN2DRV GNDSUB GNDRTC GNDSUB GNDSUB GNDSUB GNDSUB VINDIG GNDREG1 ADIN6

Figure 4. MC13892VL Pin Connections

RTC

Grounds

USB

ADC

SPI/I2C

No Connect

Regulators

Switchers

Backlights

Control Logic

Charger





MC13892

5

PIN CONNECTIONS

Table 2. MC13892 Pin Definitions

A functional description of each pin can be found in the Functional Description

.

Pin Number on the

13982VK

7x7 mm

Pin Number on the 13982VL

12x12 mm

Pin Name

Rating

(V)

Pin Function Formal Name

A1, A2, B1

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12, A13, B13

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

C1

C2

C12

C13

D5

D8

A7

A8

A2

A3

A5

A9

A10

A11

A12

B2

C2

A4

C4

C6

B5

B9

C9

B11

D9

B13

E3

B1

A13

B14

VUSB2

VINUSB2

SWBSTIN

GNDSWBST

GNDBL

NC

MODE

VCORE

BATT

CHRGRAW

CHRGCTRL2

GPO1

DVS2

SWBSTOUT

LEDB

LEDKP

LEDR

GNDCORE

VCOREDIG

BP

CHRGCTRL1

BATTISNSCC

VINPLL

VSDDRV

CHRGISNS

BATTISNS

–

–

–

9.0

3.6

5.5

5.5

3.6

5.5

20

5.5

3.6

3.6

7.5

7.5

5.5

20

4.8

5.5

5.5

4.8

4.8

28

7.5

–

1.5

Output

Power

Power

Ground

Ground

–

Input

Output

Input

I/O

Output

Output

Input

Power

Input

Input

Input

Ground

Output

Power

Output

Input

Power

Output

Input

Input

Definition

USB 2 Supply

Output regulator for USB PHY

USB 2 Supply Input

Input regulator VUSB2

Switcher Boost Power

Input

Switcher BST input

Switcher Boost Ground Ground for switcher BST

Backlight LED Ground Ground for serial LED drive

No Connect

Do not connect

Mode Configuration

USB LBP mode, normal mode, test mode selection,& anti-fuse bias

Core Supply

Regulated supply output for the IC analog core circuitry

Battery Connection

1. Battery positive pin

2. Battery current sensing point 2

3. Battery supply voltage sense

Charger Input

1. Charger input

2. Output to battery supplied accesories

Charger Control 2

General Purpose

Output 1

Driver output for charger path FETs M2

General purpose output 1

Dynamic Voltage

Scaling Control 2

Switcher 2 DVS input pin

Switcher Boost Output Switcher BST BP supply

LED Driver

General purpose LED current sink driver

Blue

LED Driver

Keypad lighting LED current sink driver

LED Driver

General purpose LED current sink driver Red

Core Ground

Ground for the IC core circuitry

Digital Core Supply

Regulated supply output for the IC digital core circuitry

Battery Plus

1. Application supply point

2. Input supply to the IC core circuitry

3. Application supply voltage sense

Charger Control 1

Driver output for charger path FETs M1

Battery Current Sense Accumulated current counter current sensing point

PLL Supply Input

VSD Driver

Input regulator processor PLL

Drive output regulated SD card

Charger Current Sense Charge current sensing point 1

Battery Current Sense Battery current sensing point 1

MC13892

6





PIN CONNECTIONS

Table 2. MC13892 Pin Definitions (continued)

A functional description of each pin can be found in the Functional Description .


13982VK

7x7 mm


12x12 mm

Pin Name

Rating

(V)


D1

D2

D4

D5

D6

D7

D8

D9

D10

D12

D13

E1

E2

E4

E12

E13

F1

F2

E8

E9

E10

E11

F4

F5

E5

E6

E7

F6

D1

C1

C3

D7

B7

C11

C12

D11

E1

D2

C5

D6

B6

C8

B8

B10

C10

B12

D10

E11

D13

E13

G13, G14

G1, G2

F2

G3

C7

A6, B3, B4, D3,

D4, E4, E5, E6

VUSB

VSD

SWBSTFB

LEDMD

DVS1

REFCORE

CHRGSE1B

LICELL

BATTFET

BPSNS

PWRON1

UVBUS

VPLL

LEDG

GNDLED

UID

PUMS2

GNDCHRG

CHRGLED

PWRON2

ADTRIG

INT

GNDSW1

GNDSW3

VBUSEN

SW3FB

LEDAD

GNDSUB1

28

3.6

3.6

3.6

3.6

4.8

4.8

3.6

20

3.6

7.5

3.6

–

–

3.6

–

20

3.6

3.6

3.6

28

3.6

3.6

3.6

–

5.5

3.6

–

Output

Output

Input

Input

Input

Output

Input

I/O

Output

Input

Input

I/O

Output

Input

Ground

Input

Input

Ground

Output

Input

Input

Output

Ground

Ground

Input

Input

Input

Ground

Definition

USB Supply

SD Card Supply

USB transceiver regulator output

Output regulator SD card

Switcher Boost

Feedback

LED Driver

Switcher BST feedback

Main display backlight LED current sink driver

Dynamic Voltage

Scaling Control 1

Switcher 1DVS input pin

Core Reference

Main bandgap reference

Charger Select

Charger forced SE1 detection input

Coin Cell Connection

1. Coin cell supply input

2. Coin cell charger output

Battery FET

Connection

Driver output for battery path FET M3

Battery Plus Sense

1. BP sense point

2. Charge current sensing point 2

Power On 1

USB Bus

Power on/off button connection 1

1. USB transceiver cable interface

2. VBUS & OTG supply output

Voltage Supply for PLL Output regulator processor PLL

PWM Driver for Green

LED

General purpose LED current sink driver

Green

LED Ground

Ground for LED drivers

USB ID

Charger Ground

USB OTG transceiver cable ID

Power Up Mode Select

2

Power up mode supply setting 2

Ground for charger interface

Charger LED

Trickle LED driver output 1

Power On 2


ADC Trigger

ADC trigger input

Interrupt Signal

Interrupt to processor

Switcher 1 Ground

Ground for switcher 1

Switcher 3 Ground


VBUS Enable

External VBUS enable pin for OTG supply

Switcher 3 Feedback

Switcher 3 feedback

Auxiliary Display LED Auxiliary display backlight LED sinking current driver

Ground 1

Non critical signal ground and thermal heat sink





MC13892

7

PIN CONNECTIONS




13982VK

7x7 mm


12x12 mm

Pin Name

Rating

(V)


F7 GNDSUB2 – Ground Ground 2

F8

F9

E7, E8, E9, E10,

F4, F5, F6

F7, F8, F9, F10,

G4, G5, G6, G7,

G8

C13

GNDSUB3

GPO3

–

–

Ground

Output

Ground 3

F10

G4

G5

G6

F11

F12

F13

G1

G2

G7

G8

G9

E12

E14

F13

F14

F1

F3

J3

E2

G9, G10, G11,

H3, H5, H6, H7,

H8

H9, H10, H12,

J5, J6, J7

J8, J9, J10, K4,

K5, K6, K7

C14

GPO2

RESETBMCU

RESETB

SW1OUT

SW3OUT

VINUSB

SW4FB

GNDREG2

GNDSUB4

GNDSUB5

GNDSUB6

PUMS1

3.6

3.6

–

–

3.6

3.6

5.5

5.5

7.5

–

–

3.6

Output

Output

Output

Output

Output

Input

Input

Ground

Ground

Ground

Ground

Input

Definition



General Purpose

Output 3


General Purpose

Output 2


MCU Reset

Reset output for processor

Peripheral Reset

Reset output for peripherals

Switcher 1 Output

Switcher 1 output

Switcher 3 Output

Switcher 3 output

VUSB Supply Input

Input option for UVUSB; tie to SWBST at top level

Switcher 4 Feedback

Switcher 4 feedback

Regulator 2 Ground

Ground for regulators 2

Ground 4


G10

G12

G13

H1

H2

H4

H5

H6

H7

H8

H9

F12

D14

H13, H14

H1, H2

P2

L3

N4

K8, K10, L4, L5,

L6, L10

P5, P7, P8, P9,

P10

–

F11

WDI

GPO4

SW1IN

SW3IN

MISO

GNDSPI

GNDREG3

GNDSUB7

GNDSUB8

GNDSUB9

GNDCTRL

3.6

3.6

5.5

5.5

3.6

–

–

–

–

–

–

Input

Output

Input

Power

I/O

Ground

Ground

Ground

Ground

Ground

Ground

Ground 5

Ground 6



Power Up Mode Select

1

Power up mode supply setting 1

Watchdog Input

Watchdog input

General Purpose

Output 4


Switcher 1 Input

Input voltage for switcher 1

Switcher 3 Input

Switcher 3 input

Master In Slave Out

Primary SPI read output

SPI Ground

Ground for SPI interface

Regulator 3 Ground


Ground 7


Ground 8

Ground 9



Logic Control Ground Ground for control logic

MC13892

8





PIN CONNECTIONS




13982VK

7x7 mm


12x12 mm

Pin Name

Rating

(V)


H10

H12

J5

J6

J7

J8

J9

H13

J1

J2

J4

J10

J12

K9

K10

K12

K13

L1

L2

L12

K5

K6

K7

K8

J13

K1

K2

K4

L13

M1, N1, N2

M2

M3

G12

L12

J13, J14

J1, J2

N2

M3

M6

N11

P12

D12

M12

J12

M13

N12

P13

K12

K13, K14

K1, K2

L2

L11

M4

L7

M8

M9

L14

L1

K3

P3

L13

N1

M1

N3

SW1FB

STANDBYSEC

SW2IN

SW4IN

MOSI

CLK32KMCU

STANDBY

GNDADC

GNDREG1

PWRON3

TSX1

SW2FB

TSX2

SW2OUT

SW4OUT

SPIVCC

PWGTDRV1

CLK32K

VCAM

CFP

CFM

ADIN5

ADIN6

VVIDEODRV

GNDSW2

GNDSW4

CS

TSY2

VVIDEO

VGEN3

CLK

VGEN2

3.6

3.6

Input

Input

Output

Ground

Ground

Input

Input

Output

Output

Input

Output

Output

Output

Passive

Passive

–

3.6

3.6

4.8

4.8

5.5

–

3.6

3.6

4.8

4.8

5.5

5.5

3.6

4.8

3.6

–

–

3.6

3.6

5.5

5.5

3.6

3.6

3.6

3.6

3.6

3.6

3.6

3.6

Input

Input

Input

Power

Input

Output

Input

Ground

Ground

Input

Input

Input

Input

Output

Output

Input

Output

Definition

Switcher 1 Feedback

Switcher 1 feedback

Secondary Standby

Signal

Standby input signal from peripherals

Switcher 2 Input

Input voltage for Switcher 2

Switcher 4 Input

Switcher 4 input

Master Out Slave In

Primary SPI write input

32 kHz Clock for MCU 32 kHz clock output for processor

Standby Signal

Standby input signal from processor

ADC Ground

Ground for A to D circuitry

Regulator 1 Ground


Power On 3


Touch Screen

Interface X1

Switcher 2 Output

Touch screen interface X1

Switcher 2 Feedback

Switcher 2 feedback

Touch Screen

Interface X2

Touch screen interface X2

Switcher 2 output

Switcher 4 Output

Switcher 4 output

Supply Voltage for SPI Supply for SPI bus and audio bus

Power Gate Driver 1

Power gate driver 1

32 kHz Clock

32 kHz clock output for peripherals

Camera Supply

Output regulator camera

Current Filter Positive Accumulated current filter cap plus pin

Current Filter Negative Accumulated current filter cap minus pin

ADC Channel 5 Input ADC generic input channel 5

ADC Channel 6 Input ADC generic input channel 6

VVIDEO Driver

Drive output regulator VVIDEO

Switcher 2 Ground


Switcher 4 Ground


Chip Select

Primary SPI select input

Touch Screen

Interface Y2

Touch screen interface Y2

Video Supply

Output regulator TV DAC

General Purpose

Regulator 3

Output GEN3 regulator

Clock

Primary SPI clock input

General Purpose

Regulator 2

Output GEN2 regulator





MC13892

9

PIN CONNECTIONS




13982VK

7x7 mm


12x12 mm

Pin Name

Rating

(V)


M4

M5

M6

M7

M8

M9

M10

M11

M12

M13, N12,

N13

N3

N8

N9

N10

N4

N5

N6

N7

N11

M5

P6

M7

N14

M2

P4

N5

N6

L8

N7

N9

N10

N8

L9

P11

M10

N13

M14

M11

VSRTC

GNDRTC

VINCAMDRV

PWGTDRV2

VDIG

VINDIG

VGEN1DRV

ADIN7

TSY1

TSREF

VINGEN3DRV

VGEN2DRV

XTAL2

XTAL1

VINAUDIO

VAUDIO

VIOHI

VINIOHI

VGEN1

Definition

3.6

–

5.5

3.6

3.6

5.5

5.5

2.5

2.5

5.5

3.6

Output

Ground

I/O

Output

Input

Input

Power

Output

Output

Input

Output

SRTC Supply

Output regulator for SRTC module on processor

Real Time Clock

Ground

Ground for the RTC block

Camera Regulator

Supply Input and Driver

Output

1. Input regulator camera using internal

PMOS FET.

2. Drive output regulator for camera voltage using external PNP device.

4.8

3.6

5.5

5.5

Output

Output

Input

Output

Power Gate Driver 2

Power gate driver 2

Digital Supply

Output regulator digital

VDIG Supply Input

Input regulator digital

VGEN1 Driver

Drive output GEN1 regulator

4.8

3.6

3.6

Input

Input

Output

ADC Channel 7 Input ADC generic input channel 7, group 1

Touch Screen

Interface Y1

Touch screen interface Y1

Touch Screen

Reference

Touch screen reference

5.5

Power/Output VGEN3 Supply Input and Driver Output

1. Input VGEN3 regulator

2. Drive VGEN3 output regulator

VGEN2 Driver

Drive output GEN2 regulator

Crystal Connection 2

32.768 kHz oscillator crystal connection 2

Crystal Connection 1

32.768 kHz oscillator crystal connection 1

Audio Supply Input

Input regulator VAUDIO

Audio Supply

Output regulator for audio

High Voltage IO Supply Output regulator high voltage IO, efuse

High Voltage IO Supply

Input

Input regulator high voltage IO

General Purpose

Regulator 1

Input GEN1 regulator

MC13892

10





ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 3. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.

Ratings Symbol Value Unit

ELECTRICAL RATINGS

Charger and USB Input Voltage

MODE pin Voltage

(5)

Main/Aux/Keypad Current Sink Voltage

Battery Voltage

Coin Cell Voltage

ESD Voltage

(6)

Human Body Model - HBM with Mode pin excluded

(9)

Charge Device Model - CDM

V

CHRGR

V

MODE

V

LEDMD,

V

LEDAD,

V

LEDKP

V

V

V

BATT

LICELL

ESD

-0.3 to 20

-0.3 to 9.0

-0.3 to 28

-0.3 to 4.8

-0.3 to 3.6

±1500

±250

V

V

V

V

V

V

THERMAL RATINGS

Ambient Operating Temperature Range

Operating Junction Temperature Range

Storage Temperature Range

T

A

T

J

T

STG

-40 to +85

-40 to +125

-65 to +150

°C

°C

°C

THERMAL RESISTANCE

Peak Package Reflow Temperature During Reflow

(7)

,

(8)

T

PPRT

Note 8

°C

Notes

5.

USB Input Voltage applies to UVBUS pin only

6.

ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500



) and the Charge Device

Model (CDM), Robotic (CZAP = 4.0 pF).

7.

Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.

8.

Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

9.

Mode Pin is not ESD protected.

Table 4. Dissipation Ratings

Rating Parameter

Junction to Ambient Natural Convection

Junction to Ambient Natural Convection

Junction to Ambient (@200 ft/min)

Junction to Ambient (@200 ft/min)

Junction to Board

Junction to Case

Junction to Package Top

Condition

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

Natural Convection

Symbol

R



JA

R



JMA

R



JMA

R



JMA

R



JB

R



JC



JT

VK Package

104

54

88

49

32

29

7.0

VL Package

28

22

5.0

65

42

55

38

Unit

°C/W

°C/W

°C/W

°C/W

°C/W

°C/W

°C/W





MC13892

11


STATIC ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics

Characteristics noted under conditions 40



C



T

A the approximate parameter means at T

A =



85



C, GND = 0 V unless otherwise noted. Typical values noted reflect

25 °C under nominal conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

CURRENT CONSUMPTION

RTC Mode

All blocks disabled, no main battery attached, coin cell is attached to

LICELL

(10)

RTC

OFF Mode (All blocks disabled, main battery attached)

(10)

MC13892 core and RTC module

I

RTC

I

OFF

–

–

Power Cut Mode (All blocks disabled, no main battery attached, coin cell

is attached and valid)

(10)

MC13892 core and RTC module

I

PCUT

–

ON Standby mode - Low-power mode

4 buck regulators in low-power mode, 3 regulators

(11)

I

STBY

–

ON Mode - Typical use case

4 buck regulators in PWMPS mode, 5 Regulators

(12)

I

ON

–

I/O CHARACTERISTICS

(13)

PWRON1, PWRON2, PWRON3, Pull-up

(14)

Input Low, 47 kOhm

Input High, 1.0 MOhm

CHRGSE1B, Pull-up

(15)

Input Low

Input High

STANDBY, STANDBYSEC, WDI, ADTRIG, Weak Pull-down

(16)

,

(17)

Input Low

Input High

0.0

1.0

0.0

1.0

0.0

1.0

CLK32K, CMOS

Output Low, -100

Output High, 100





A

A

0.0

SPIVCC -0.2

CLK32KMCU, CMOS

Output Low, -100



A

Output High, 100



A

RESETB, RESETBMCU, Open Drain

(18)

Output Low, -2.0 mA

Output High, Open Drain

0.0

VSRTC- 0.2

0.0

0.0

Notes

10.

Valid at 25 °C only.

11.

VPLL, VIOHI, VGEN2

12.

VPLL, VIOHI, VGEN2, VAUDIO, VVIDEO

13.

SPIVCC is typically connected to the output of buck regulator: SW4 and set to 1.800 V

14.

Input has internal pull-up to VCOREDIG equivalent to 200 kOhm

15.

Input has internal pull-up to VCORE equivalent to 100 kOhm

16.

SPIVCC needs to remain enabled for proper detection of WDI High to avoid involuntary shutdown

17.

A weak pull-down represents a nominal internal pull down of 100 nA, unless otherwise noted

18.

RESETB & RESETBMCU have open drain outputs, external pull-ups are required

3.00

10

3.0

230

459

–

–

–

–

–

–

–

–

–

–

–

–

6.00

30

6.0

295

1500

0.3

VCOREDIG

0.3

VCORE

0.3

3.6

0.2

SPIVCC

0.2

VSRTC

0.4

3.6

µA

µA

µA

µA

µA

V

V

V

V

V

V

MC13892

12







Table 5. Static Electrical Characteristics (continued)




C



T


A =



85





Unit Characteristic Symbol Min Typ Max

I/O CHARACTERISTICS (CONTINUED)

(19)

VSRTC, Voltage Output

DVS1, DVS2, Weak Pull-down

(20)

Input Low

Input High

1.1

0.0

0.7* SPIVCC

–

–

–

1.3

0.3* SPIVCC

3.1

GPO1, CMOS

Output Low, -400

Output High, 400

To VCORE





A

A

0.0

VCORE- 0.2

200

–

–

–

0.2

VCORE

500

GPO2, GPO3, GPO4, CMOS

Output Low, -100

Output High, 100





A

A

0.0

VIOHI - 0.2

0.0

–

–

–

0.2

VIOHI

VCORE+0.3

GPO4, Analog Input

CS, CLK, MOSI, VBUSEN, Weak Pull-down on CS and VBUSEN

(20)

Input Low

Input High

CS, MOSI (at Booting for SPI / I

2

C decoding), Weak Pull-down on CS

(21)

Input Low

Input High

MISO, INT, CMOS

(22)

Output Low, -100



A

Output High, 100



A

PUMS1, PUMS2

(22)

PUMSxS = 00

PUMSxS = 01, Load < 10 pF

PUMSxS = 10

PUMSxS = 11

0.0

0.7* SPIVCC

0.0

0.7 * VCORE

0.0

SPIVCC -0.2

–

–

–

–

–

–

0.3* SPIVCC

SPIVCC+0.3

0.3 * VCORE

VCORE

0.2

SPIVCC

0.0

Open

1.3

2.5

–

–

–

–

0.3

Open

2.0

3.1

MODE

(23)

Input Low

Input Med

Input High

0.0

1.1

VCORE

–

–

–

Notes

19.

SPIVCC is typically connected to the output of buck regulator: SW4 and set to 1.800 V

20.

A weak pull-down represents a nominal internal pull down of 100 nA unless otherwise noted

21.

The weak pull-down on CS is disabled if a VIH is detected at startup to avoid extra consumption in I

2

C mode

22.

The output drive strength is programmable

23.

Input state is latched in first phase of cold start, refer to

Power Control System

for description of PUMS configuration

24.

Input state is not latched

0.4

1.7

9.0

V

V

V

V

V

Ohm

V

V

V

V

V





MC13892

13







C



T


A =



85






32 KHZ CRYSTAL OSCILLATOR

Operating Voltage

Oscillator and RTC Block from BP

Coincell Disconnect Threshold

At LICELL

Output Low CLK32K, CLK32KMCU

Output sink 100 µA

Output High

CLK32K Output source 100 µA

CLK32KMCU Output source 100 µA

VSRTC GENERAL

Operating Input Voltage Range V

INMIN

Valid Coin Cell range

to V

INMAX

Or valid BP

Operating Current Load Range IL

MIN

to IL

MAX

Bypass Capacitor Value

VSRTC ACTIVE MODE – DC

Output Voltage V

V

INMIN

< V

IN

OUT

< V

INMAX

, IL

MIN

< IL < IL

MAX

CLK AND MISO

Input Low CS, MOSI, CLK

Input High CS, MOSI, CLK

Output Low MISO, INT

Output sink 100 µA

Output High MISO, INT

Output source 100 µA

SPIVCC Operating Range

V

XTAL

V

LCD

V

CLKLO

V

CLKHI

V

CLKMCUHI

V

LICELL

BP

I

SRTC

C

SRTC

V

SRTC

V

INCSLO

V

INMOSILO

V

INCLKLO

V

INCSHI

V

INMOSIHI

V

INCLKHI

V

OMISOLO

V

OINTLO

V

OMISOHI

V

OINTHI

SPIV

CC

1.2

1.8

0.0

SPIV

CC

V

SRTC

-0.2

-0.2

1.8

UVDET

0.0

–

1.15

0.0

0.7*SPIV

CC

0.0

SPIV

CC

-0.2

1.75

–

–

–

–

–

–

–

–

1.0

1.20

–

–

–

–

–

4.65

2.0

0.2

SPIV

CC

V

SRTC

3.6

4.65

50

–

1.25

0.3*SPIV

CC

SPIV

CC

+0.3

0.2

SPIV

CC

3.1

V

V

V

V

V

µA

µF

V

V

V

V

V

V

MC13892

14











C



T


A =



85






BUCK REGULATORS

Operating Input Voltage

PWM operation, 0 < IL < I

MAX



PFM operation, 0 < IL < I

MAX



Extended PWM or PFM operation

(25)

Output Voltage Range

Switcher 1

Switchers 2, 3, and 4

Output Accuracy

PWM mode including ripple, load regulation, and transients

(26)

PFM Mode, including ripple, load regulation, and transients

Maximum Continuous Load Current, I

MAX

, V

INMIN

<BP<4.65 V

SW1 in PWM mode (SWILIMB = 0, no max current limit)



SW1 in PWM Mode (SWILIMB = 1, no max current limit)

(27)



SW2, SW3, SW4 in PWM mode (SWILIMB = 0, no max current limit)



SW2, SW3, SW4 in PWM mode (SWILIMB = 1, no max current limit)

(27)



SW1, SW2, SW3, SW4 in PFM mode

Maximum Peak Load Current, I

PEAK

, BP



4.2 V,


(27)




(27)

V

SWIN

V

SW1

V

SWLOPP

V

SWLIPPI

I

SW1

I

SW2,3,4

I

SW2,3,4

I

SW1, 2, 3, 4

I

SW1

I

SW4

3.0

2.8

UVDET

0.6

0.6

Nom-50

Nom-50

800

1050

800

800

–

1250

1000

–

–

Nom

Nom

–

–

–

–

50

–

–

–

–

–

4.65

4.65

4.65

1.375

1.850

Nom+50

Nom+50

–

–

–

–

–

–

–

V

V mV mA mA

Notes

25.

In the extended operating range the performance may be degraded

26.

Transient loading for load steps of ILmax/2

27.

In this mode, current limit protection is disabled for SW1 - SW4 by setting SWILIMB = 1. Therefore, the load on SW1-4 should not exceed the conditions specified in the table above. Application needs to provide current limit protection circuitry either in battery or as preregulated supply to BP.





MC13892

15







C



T


A =



85






BUCK REGULATORS (CONTINUED)

Automatic Mode Change Threshold, Switchover between PFM and PWM modes

Efficiency

PFM, 0.9 V, 1.0 mA

PFM, 01.8 V, 1.0 mA

PWM Pulse Skipping, 1.25 V, 50 mA

PWM Pulse Skipping, 1.8 V, 50 mA

PWM, 1.25 V, 500 mA

PWM, 1.8 V, 500 mA

External Components, Used as a condition for all other parameters

Inductor for SW2, SW3, SW4

(28)

Inductor for SW1

(28)

Inductor Resistance

Bypass Capacitor for SW2, SW3, SW4

(29)

Bypass Capacitor for SW1

(30)

Bypass Capacitor ESR

Input Capacitor

(31)

AMC

L

C

L

R

C

ESR

TH

SW234

SW1

WSW

OSW234

OSW1

SW

–

–

–

–

–

–

–

-20%

-30%

–

-35%

-35%

5.0

1.0

50

75

85

78

82

78

82

2.2

1.5

–

10

2x22

–

4.7

–

–

–

–

–

–

–

+20%

+30%

0.16

+35%

+35%

50

– mA



SWBST

Average Output Voltage

(32)

3.0 V < V

IN

< 4.65 (1), 0 < IL < IL

MAX

(33)

Output Ripple

3.0 V < V

IN

< 4.65, 0 < IL < IL

Schottky diode

MAX

, Excluding reverse recovery of

V

V

BST

BSTPP

Nom-5%

–

5.0

–

Nom+5%

120

V mVpp

Average Load Regulation

V

IN

= 3.6 V, 0 < IL < IL

MAX

Average Line Regulation

3.0 V < V

IN

< 4.65 V, IL = IL

MAX

V

V

BSTLOR

BSTLIR

–

–

–

–

0.5

50 mV/mA mV

Notes

28.

Preferred device TDK VLS252012 series at 2.5x2.0 mm footprint and 1.2 mm max height

29.

Preferably 0603 style 6.3 V rated X5R/X7R type at 35% total make tolerance, temperature spread and DC bias derating such as TDK

C1608X5R0J106M

30.


C2012X5R0J226M

31.


C1608X5R0J475

32.

Output voltage when configured to supply VBUS in OTG mode can be as high as 5.75 V

33.

Vin is the low side of the inductor that is connected to BP.

µH

µH



µF

µF m



µF

MC13892

16











C



T


A =



85






SWBST (CONTINUED)

Maximum Continuous Load Current IL

MAX

3.0 V < V

IN

< 4.65, V

OUT =

5.0 V

Start-up Overshoot

IL = 0 mA

Efficiency, IL = IL

MAX

External Components - Used as a condition for all other parameters

Inductor

(34)

Inductor Resistance

Inductor saturation current at 30% loss in inductance value

Bypass Capacitor

(35)

Bypass Capacitor ESR at resonance

Input Capacitor

Diode current capability

Diode current capability

NMOS Off Leakage, SWBSTIN = 4.5 V, SWBSTEN = 0

V

I

BST

BSTOS

SWBST

L

BST

R_W

IL

SAT

CO

ESR

I

I

C

EFF

BST

BST

BST

BSTD

BSTDPK

BSTDPK

300

–

–

-20%

–

1.0

-60%

1.0

1.0

850

1500

–

–

80

2.2

–

–

10

–

4.7

–

–

–

500

–

+20%

0.2

–

+35%

10

–

–

– mA mV

%

I

BSTIK

– 1.0

5.0

µA

VVIDEO


INMIN

to V

INMAX


MIN

(Not exceeding PNP max power)

to IL

MAX



Minimum Bypass Capacitor Value

Used as a condition for all other parameters


10 kHz -1.0 MHz

V

I

INVIDEO

VIDEO

CO

VIDEO

ESR

VIDEO

V

NOM

+0.25

0.0

1.1

–

–

2.2

4.65

350

–

V mA

µF m



20 – 100

VVIDEO ACTIVE MODE DC

Output Voltage V

V

INMIN

< V

IN

OUT

< V

INMAX

, IL

MIN

< IL < IL

MAX

Load Regulation

1.0 mA < IL < IL

MAX

, For any V

INMIN

< V

IN

< V

INMAX

V



V

VIDEO

VIDEOLOPP

V

NOM

–

- 3% V

NOM

–

V

NOM

+ 3%

0.20

V mV/mA

Line Regulation

V

INMIN

< V

IN

< V

INMAX

, For any IL

MIN

< IL < IL

MAX

Short-circuit Protection Threshold

V

INMIN

< V

IN

< V

INMAX

, Short-circuit V

OUT

to GND

V

VIDEOLIPP

I

VIDEOSHT

– 5.0

8.0

mV mA

IL

MAX

+20% – –

Notes

34.

Preferred device TDK VLS252012 series at 2.5x2.0 mm footprint and 1.2 mm max height

35.

Applications of SWBST should take into account impact of tolerance and voltage derating on the bypass capacitor at the output level.

µH



A

µF m



µF mAdc mApk





MC13892

17







C



T


A =



85






VVIDEO LOW-POWER MODE DC - VVIDEOMODE = 1

Output Voltage V

V

INMIN

< V

IN

OUT

< V

INMAX

, IL

MINLP

< IL < IL

MAXLP

Current Load Range ILminlp to IL

MAXLP

VAUDIO


INMIN

to V

INMAX


MIN

to IL

MAX



10 kHz -1.0 MHz

VAUDIO ACTIVE MODE DC

Output Voltage V

OUT

(V

INMIN

< V

IN

< V

INMAX

, IL

MIN

< IL < IL

MAX

)

Load Regulation (1.0 mA < IL < IL

MAX

, For any V

INMIN

< V

IN

< V

INMAX

)

Line Regulation

V

INMIN

< V

IN

< V

INMAX

, For any IL

MIN

< IL < IL

MAX


V

INMIN

< V

IN

< V

INMAX

, Short-circuit V

OUT

to GND

VPLL AND VDIG


INMIN

VDIG, VPLL all settings, BP biased

to V

INMAX

VPLL, VDIG [1:0] = 00,01

VPLL, VDIG [1:0] = 10, 11, External Switcher


MIN

to IL

MAX




10 kHz -1.0 MHz

VPLL AND VDIG ACTIVE MODE DC

Output Voltage V

V

INMIN

< V

IN

OUT

< V

INMAX

, IL

MIN

< IL < IL

MAX

Load Regulation

1.0 mA < IL < IL

MAX for any V

INMIN

< V

IN

< V

INMAX

Line Regulation

V

INMIN

< V

IN

< V

INMAX for any IL

MIN

< IL < IL

MAX

VIOHI


INMIN

V

NOM

= 2.775 V

to V

INMAX


MIN

to IL

MAX



10 kHz -1.0 MHz



V

VIDEOLO

I

VIDEOLO

V

AUDIO

I

AUDIO

C

OAUDIO

ESR

AUDIO

V

AUDIO

V

AUDIOLOR

V

AUDIOLIR

I

AUDIOSHT

V

INPLL,

V

INDIG

I

PLL,

I

DIG

C

OPLL,

C

ODIG

ESR

PLL

,

ESR

DIG

V

PLL

, V

DIG

V

PLLLOR

,

V

DIGLOR

V

PLLLIR

,

V

DIGLIR

V

INIOHI

I

IOHI

C

OIOHI

ESR

IOHI

V

NOM

-3%

0.0

V

NOM

+0.25

0.0

0.65

0.0

V

NOM

- 3%

–

–

IL

MAX

+20%

UVDET

1.75

2.15

0.0

0.65

0.0

V

NOM

- 0.05

–

–

V

NOM

+0.25

0.0

0.65

0.0

V

NOM

–

–

V

NOM

–

5.0

–

–

SW4 = 1.8

2.2

–

2.2

–

V

NOM

–

5.0

–

–

2.2

–

–

2.2

–

V

NOM

+3%

3.0

4.65

150

–

0.1

V

NOM

+ 3%

0.25

8.0

–

4.65

4.65

4.65

50

–

0.1

V

NOM

+ 0.05

0.35

8.0

4.65

100

–

100

V mA

V mA

µF



V mV/mA mV mA

V mA

µF



V mV/mA mV

V mA

µF m



MC13892

18











C



T


A =



85






VIOHI ACTIVE MODE DC

Output Voltage V

V

INMIN

< V

IN

OUT

- (V

NOM

= 2.775)

< V

INMAX

, IL

MIN

< IL < IL

MAX

Load Regulation

1.0 mA < IL < IL

MAX

, for any V

INMIN

< V

IN

< V

INMAX

Line Regulation

V

INMIN

< V

IN

< V

INMAX

, for any IL

MIN

< IL < IL

MAX

VCAM


INMIN

to V

INMAX


MIN

Internal pass FET

to IL

MAX

External PNP


Internal pass device

External PNP (not exceeding PNP max power)


10 kHz -1.0 MHz

VCAM ACTIVE MODE DC

Output Voltage V

V

INMIN

< V

IN

OUT

(V

< V

INMAX

NOM

, IL

= 2.775)

MIN

< IL < IL

MAX

Load Regulation

1.0 mA < IL < IL

MAX

, for any V

INMIN

< V

IN

< V

INMAX

Line Regulation

V

INMIN

< V

IN

< V

INMAX

, for any IL

MIN

< IL < IL

MAX


V

INMIN

< V

IN

< V

INMAX

, Short-circuit V

OUT

to GND

VCAM LOW-POWER MODE DC

Output Voltage V

V

INMIN

< V

IN

OUT

< V

INMAX

, IL

MINLP

< IL < IL

MAXLP

Current Load Range IL

MINLP

to IL

MAXLP

VSD


INMIN

VSD[2:0] = 010 to 111

to V

INMAX

VSD[2:0] = 010 to 111, Extended Operation

VSD[2:0] = 000, 001 [000] BP Supplied

VSD[2:0] = 000 External Switcher Supplied


MIN

Not exceeding PNP max power

to IL

MAX



10 kHz -1.0 MHz

V

IOH

V

IOHLOR

V

IOHLIR

V

INCAM

I

CAM

C

OCAM

ESR

CAM

V

CAM

V

CAMLOR

V

CAMLIR

I

CAMSHT

V

CAMLO

I

CAMLO

V

INSD

I

SD

C

OSD

ESR

SD

V

NOM

-3%

–

–

V

NOM

+0.25

0.0

0.0

0.65

1.1

20

V

NOM

- 3%

–

–

IL

MAX

+20%

V

NOM

-3%

0.0

V

NOM

+0.25

UVDET

UVDET

2.15

0.0

1.1

20

V

NOM

–

5.0

–

–

–

2.2

2.2

–

V

NOM

–

5.0

–

V

NOM

–

–

–

–

2.20

–

2.2

–

V

NOM

+3%

0.35

8.0

4.65

65

250

–

–

100

V

NOM

+ 3%

0.25

8.0

–

V

NOM

+3%

3.0

4.65

4.65

4.65

4.65

250

–

100

V mV/mA mV

V mA

µF m



V mV/mA mV mA

V mA

V mA

µF m







MC13892

19







C



T


A =



85






VSD ACTIVE MODE DC

Output Voltage V

V

INMIN

< V

IN

OUT

< V

INMAX

, IL

MIN

< IL < IL

MAX

Load Regulation

1.0 mA < IL < IL

MAX

, for any V

INMIN

< V

IN

< V

INMAX

Line Regulation

V

INMIN

< V

IN

< V

INMAX

, for any IL

MIN

< IL < IL

MAX


V

INMIN

< V

IN

< V

INMAX

, Short-circuit V

OUT

to GND

VSD LOW-POWER MODE DC - VSDMODE = 1

Output Voltage V

V

INMIN

< V

IN

OUT

< V

INMAX

, IL

MINLP

< IL < IL

MAXLP


MINLP

to IL

MAXLP

VUSB GENERAL


INMIN

Supplied by VBUS

to V

INMAX

Supplied by SWBST


MIN

to IL

MAX

Bypass Capacitor Value Range


10 kHz -1.0 MHz

VUSB ACTIVE MODE DC

Output Voltage V

V

INMIN

< V

IN

OUT

< V

INMAX

, IL

MIN

< IL < IL

MAX

Load Regulation

0 < IL < IL

MAX

from DM/DP for any V

INMIN

< V

IN

< V

INMAX

Line Regulation

V

INMIN

< V

IN

< V

INMAX

, for any IL

MIN

< IL < IL

MAX


V

INMIN

< V

IN

< V

INMAX

, Short-circuit V

OUT

to GND

VUSB2


INMIN

Extended operation

to V

INMAX


MIN

to IL

MAX




10 kHz -1.0 MHz

V

SD

V

SDLOR

V

SDLIR

I

SDSHT

V

SDLO

I

SDLO

V

INUSB

I

USB

C

OUSB

ESR

USB

V

USB

V

USBLOR

V

USBLIR

V

USBSHT

V

INUSB2

I

USB2

C

OUSB2

ESR

USB2

V

NOM

- 3%

–

–

IL

MAX

+20%

V

NOM

-3%

0.0

4.4

–

0.0

0.65

0.0

V

NOM

- 4%

–

–

IL

MAX

+20%

V

NOM

+0.25

UVDET

0.0

0.65

0.0

V

NOM

–

5.0

–

V

NOM

–

5.0

–

–

2.2

–

3.3

–

–

–

–

–

–

2.2

–

V

NOM

+ 3%

0.25

8.0

–

V

NOM

+3%

3.0

5.25

5.75

100

–

0.1

V

NOM

+ 4%

1.0

20

–

4.65

4.65

50

–

0.1

V mV/mA mV mA

V mA

V mA

µF



V mV/mA mV mA

V mA

µF



MC13892

20











C



T


A =



85






VUSB2 ACTIVE MODE DC

Output Voltage V

V

INMIN

< V

IN

OUT

< V

INMAX

, IL

MIN

< IL < IL

MAX

Load Regulation

1.0 mA < IL < IL

MAX

, for any V

INMIN

< V

IN

< V

INMAX

Line Regulation

V

INMIN

< V

IN

< V

INMAX

, for any IL

MIN

< IL < IL

MAX

UVBUS


INMIN

VINUSB supplied by SWBST

to V

INMAX


MIN

to IL

MAX



10 kHz -1.0 MHz

UVBUS ACTIVE MODE DC

Output Voltage Vout

V

INMIN

< V

IN

< V

INMAX

, IL

MIN

< IL < IL

MAX

VGEN1


INMIN

to V

INMAX



All settings, BP biased



V

V

V

C

V

USB2LOR

I

V

INUVBUS

INUVBUS

V

USB2

USB2LIR

UVBUS

OUVBUS

UVBUS

V

INGEN1

V

NOM

–

–

-3%

4.75

0.0

(36)

(36)

4.4

V

NOM

–

5.0

5.0

–

(36)

(36)

5.0

V

NOM

+ 3%

0.35

8.0

5.25

100

6.5

(37)

(37)

5.25

V mV/mA mV

V mA

µF



V

V

UVDET <

V

NOM

+0.25

– 4.65

VGEN1=00,01, External switcher supplied


MIN

(not exceeding PNP max power)

to IL

MAX



Extended input voltage range (BP biased, performance may be out of specification for output levels VGEN1[1:0] = 10 to 11)



10 kHz -1.0 MHz

I

GEN1

C

OGEN1

ESR

GEN1

2.15

0.0

UVDET

1.1

2.2

–

–

2.2

4.65

200

4.65

+35% mA

V

µF m



20 – 100

VGEN1 ACTIVE MODE DC

Output Voltage V

OUT

VGEN1 = 00, 01, V

INMIN

< V

IN

< V

INMAX

IL

VGEN1 = 10, 11, V

INMIN

< V

IN

< V

INMAX

IL

MIN

< IL < IL

MAX

MIN

< IL < IL

MAX

Load Regulation

1.0 mA < IL < IL

MAX

, for any V

INMIN

< V

IN

< V

INMAX

V

V

GEN1

GEN1LOR

V

NOM

V

NOM

– 0.05

– 3%

–

V

V

NOM

NOM

–

V

V

NOM

NOM

+ 0.05

+ 3%

0.25

V mV/mA

Line Regulation

V

INMIN

< V

IN

< V

INMAX

, for any IL

MIN

< IL < IL

MAX


V

INMIN

< V

IN

< V

INMAX

, Short-circuit V

OUT

to GND

V

GEN1LIR

V

GEN1SHT

– 5.0

8.0

mV mA

IL

MAX

+20% – –

Notes

36.

Filtering is shared with CHRGRAW (shorted at board level). 2.2 µF is typically included at the CHRGRAW pin.

37.

6.5 µF is the maximum allowable capacitance on VBUS including all tolerances of filtering capacitance on VBUS and CHRGRAW (which are shorted at the board level).





MC13892

21







C



T


A =



85






VGEN1 LOW-POWER MODE DC - VGEN1MODE = 1

Output Voltage V

OUT -

V

VGEN1 = 00, 01

INMIN

< V

IN

< V

INMAX

, IL

MINLP

< IL < IL

MAXLP

VGEN1 = 10, 11


MINLP

to IL

MAXLP

VGEN2 GENERAL


INMIN

to V

INMAX



All settings, BP biased



VGEN2=000,001, External switcher supplied


MIN power)

to IL

MAX

(Not exceeding PNP max



10 kHz -1.0 MHz


Output Voltage V

OUT

VGEN2 = 000, 001, 010, V

INMIN

< V

IN

< V

INMAX

IL

VGEN2 = 011, 100, 101, 110, 111, V

IL

MAX

INMIN

< V

MIN

< IL < IL

MAX



IN

< V

INMAX

IL

MIN

< IL <

Load Regulation

1.0 mA < IL < IL

MAX

, For any V

INMIN

< V

IN

< V

INMAX

Line Regulation

V

INMIN

< V

IN

< V

INMAX

, For any IL

MIN

< IL < IL

MAX


V

INMIN

< V

IN

< V

INMAX

, Short-circuit V

OUT

to GND

VGEN2 LOW-POWER MODE DC - VGEN2MODE=1

Output Voltage V

OUT

- V

VGEN2 = 000 to 010

INMIN

< V

IN

< V

INMAX

, IL

MINLP

< IL < IL

MAXLP

VGEN2 = 011 to 111


MINLP

to IL

MAXLP

VGEN3 GENERAL


INMIN

VGEN3CONFIG, VGEN3 = 01, 11

to V

INMAX

VGEN3CONFIG, VGEN3 = 00, 10


MIN

Internal Pass FET

to IL

MAX

External PNP (Not exceeding PNP max power)


Internal pass device

External pass device


10 kHz -1.0 MHz

V

GEN1LO

I

GEN1LO

V

INGEN2

I

GEN2

C

OGEN2

ESR

GEN2

V

GEN2

V

GEN2LOR

V

GEN2LIR

V

GEN2SHT

VGEN2LO

I

GEN2LO

V

INGEN3

I

GEN3

C

OGEN3

ESR

GEN3

V

NOM

- 0.05

V

NOM

-3%

0.0

UVDET<

V

NOM

+0.25

2.15

0.0

1.1

20

V

NOM

V

NOM

-0.05

-3%

–

–

IL

MAX

+20%

V

NOM

V

NOM

-0.05

-3%

0.0

V

NOM

+0.2

UVDET

0.0

0.0

0.65

1.1

20

V

NOM

V

NOM

–

–

2.2

–

2.2

–

V

NOM

V

NOM

–

5.0

–

V

NOM

V

NOM

–

–

–

–

–

2.2

2.2

–

V

NOM

+ 0.05

V

NOM

+3%

3.0

4.65

4.65

350

+35%

100

V

NOM

V

NOM

+0.05

+3%

0.20

8.0

–

V

NOM

V

NOM

+0.05

+3%

3.0

4.65

4.65

50

200

–

–

100

V mA

V mA

µF m



V mV/mA mV mA

V mA

V mA

µF m



MC13892

22











C



T


A =



85







Output Voltage V

OUT

VGEN2 = 000, 001, 010, V

INMIN

< V

IN

< V

INMAX

IL

MIN

< IL < IL

MAX

Load Regulation

1.0 mA < IL < IL

MAX

, For any V

INMIN

< V

IN

< V

INMAX

Line Regulation

V

INMIN

< V

IN

< V

INMAX

, For any IL

MIN

< IL < IL

MAX


V

INMIN

< V

IN

< V

INMAX

, Short circuit V

OUT

to GND

VGEN3 LOW-POWER MODE DC

Output Voltage V

V

INMIN

< V

IN

OUT

- (Accuracy)

< V

INMAX

, IL

MINLP

< IL < IL

MAXLP


MINLP

to IL

MAXLP

CHARGE PATH REGULATOR

Input Operating Voltage - CHRGRAW

Output Voltage Spread - VCHRG[2:0]=011, 1XX

Charge current 1.0 mA to 100 mA

Charge current 100 mA and above

Current Limit Tolerance

(38)

ICHRG[3:0] = 0001

ICHRG[3:0] = 0100

ICHRG[3:0] = 0110

All other settings

Start-up Overshoot - Unloaded

Configuration

Input Capacitance - CHRGRAW

(39)



Load Capacitor - BPSNS

(39)



Cable length

THERMAL

Thermal Warning Lower Threshold

Thermal Warning Higher Threshold

Thermal Warning Hysteresis

Thermal Protection Threshold

BACKLIGHT LED DRIVERS

Absolute Accuracy - All current settings

Matching - At 400 mV, 21 mA

Leakage - LEDxDC[5:0] = 000000

SIGNALING LED DRIVERS

Absolute Accuracy - All current settings

Matching - At 400 mV, 21 mA

Leakage - LEDxDC[5:0] = 000000

V

GEN3

V

GEN3LOR

V

GEN3SHT

V

GEN3SHT

V

GEN3LO

I

GEN3LO

V

INCHRG

BP

SP



I

LIM

BP

OS-START

C

INCHRG

C

BP

L

C

T

WL

T

WH

T

WHYS

T

PT

V

NOM

-3%

–

–

IL

MAX

+20%

V

NOM

-3%

0.0

BATT

MIN

-1.5

-3.0

–

–

–

–

–

–

–

–

–

–

68

360

500

– v

–

10

–

V

NOM

–

5.0

–

V

NOM

1.0

–

–

–

–

–

–

–

–

–

80

400

560

–

–

2.2

–

–

100

120

3.0

140

V

NOM

+ 3%

0.40

9.0

–

V

NOM

+3%

3.0

5.6

1.5

1.5

92

440

620

15

2.0

–

47

3.0

15

10

1.0

15

3.0

1.0

–

–

–

–

V mV/mA mV mA

V mA

V

%

%

%

µA

%

%

µA

°C

°C

°C

°C mA mA mA

%

%

µF

µF m





MC13892

23







C



T


A =



85






ACTIVE MODE DC

Output Voltage V

OUT

- (V

NOM

< IL

MAX

= 2.775), V

INMIN

< V

IN

< V

INMAX

, IL

MIN

< IL

ADC

Converter Core Input Range

Single ended voltage readings

Differential readings

Maximum Input Voltage

(40)



Channels ADIN5, ADIN6 and ADIN7

Integral Nonlinearity

Differential Nonlinearity

Zero Scale Error (Offset) after auto calibration

4.4

0.0

-1.2

–

–

–

–

–

–

5.0

–

–

–

–

–

–

–

–

5.25

2.4

1.2

BP

3

1

1

5

1

V

V

V

Full Scale Error (Gain) after auto calibration

Drift Over-temperature - Including scaling

Source Impedance



No bypass capacitor at input



Bypass capacitor at input 10 nF

–

–

–

–

5.0

30

TOUCH SCREEN

Plate Maximum Voltage X, Y

(41)

Plate Resistance X, Y

Resistance Between Plates Settling Time - Contact

Position measurement

TOUCH SCREEN IN STAND ALONE MODE

(42)

–

100

180

3.0

–

–

–

–

VCORE

1000

1200

5.5

V





µs

Max Load Current - Active Mode

Output Voltage - 0.0<IL<20 mA

PSRR - IL=15 mA


Bypass Capacitance

–

-3%

50

0.0

0.65

–

1.20

–

–

2.2

20

+3%

–

0.1

+35% mA

V dB



µF

Notes

38.

Excludes spread and tolerance due to board and 100 mOhm sense resistor tolerances.

39.

An additional derating of 35% is allowed.

40.

ADIN5, 6 and 7 inputs must not exceed BP voltage.

41.

TS[xy][1,2] inputs must not exceed BP or VCORE

42.

All characteristics in this table are applicable only for non touch screen operation. This applies to Touch Screen in Standalone mode and below.

LSB

LSB

LSB

LSB

LSB

K



MC13892

24






DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 6. Dynamic Electrical Characteristics

Characteristics noted under conditions 3.1 V



BATT



4.65



V, -40



T

A values noted reflect the approximate parameter means at T

A =



85 °C, GND = 0 V, unless otherwise noted. Typical



32 KHZ CRYSTAL OSCILLATOR

RTC oscillator start-up time

Upon application of power

CLK32K Rise and Fall Time - CL = 50 pF

CLK32KDRV[1:0] = 00 (default)

CLK32KDRV[1:0] = 01

CLK32KDRV[1:0] = 10

CLK32KDRV[1:0] = 11

CLK32KMCU Rise and Fall Time

CL = 12 pF

CLK32K and CLK32KMCU Output Duty Cycle

Crystal on XTAL1, XTAL2 pins

CLK AND MISO

MISO Rise and Fall Time, CL = 50 pF, SPIVCC = 1.8 V

SPIDRV [1:0] = 00 (default)

SPIDRV [1:0] = 01

SPIDRV [1:0] = 10

SPIDRV [1:0] = 11

BUCK REGULATORS

Turn-on Time, Enable to 90% of end value, IL = 0

SWBST

Turn-on Time

Enable to 90% of V

OUT

, IL = 0

Transient Load Response, IL from 1.0 mA to 100 mA in 1.0 µs steps

Maximum transient Amplitude

Time to settle 80% of transient

Transient Load Response, IL from 100 mA to 1.0 mA

Maximum transient Amplitude

Time to settle 80% of transient

VVIDEO ACTIVE MODE - AC

PSRR - IL = 75% of IL

MAX

V

IN

= V

INMIN

+ 100 mV

, 20 Hz to 20 kHz

V

IN

= V

NOM

+ 1.0 V

Max Output Noise - V

IN

100 Hz – 1.0 kHz

= V

INMIN

, IL = 75% of IL

MAX

>1.0 kHz – 10 kHz

>10 kHz – 1.0 MHz

Turn-on Time

Enable to 90% of end value, V

IN

= V

INMIN

, V

INMAX

, IL = 0

VVIDEO ACTIVE MODE - AC (CONTINUED)

Turn-off Time

Disable to 10% of initial value, V

IN

= V

INMIN

, V

INMAX

, IL = 0

Transient Load Response

V

IN

= V

INMIN

, V

INMAX t

RTCST t

CLK32KET t

CLK32KMCUET t

CLK32KDC

, t

CLK32KMCUDC t

MISOET t

ONPWM t

ONBST

A

TMAX

A

TMAX

V

VIDEOPSSR

V

VIDEOON

VVIDEOt

ON

VVIDEOt

OFF

V

VIDEOTLOR

–

–

–

–

–

–

45

–

–

–

–

–

–

–

–

–

–

35

50

–

–

–

–

0.1

–

–

22

11

High Z

44

22

–

11

6.0

High Z

22

–

–

–

–

–

–

40

60

-114

-124

-129

–

–

1.0

1.0

–

55

–

–

–

–

–

–

–

–

500

2.0

300

500

300

20

–

–

–

–

–

1.0

10

2.0

Sec ns ns

% ns

µs ms mV

µs mV

µs dB dBV/



Hz ms ms

%





MC13892

25



Table 6. Dynamic Electrical Characteristics (continued)




BATT



4.65



V, -40



T


A =





Symbol Min Typ Max Unit Characteristic

Transient Line Response

IL = 75% of IL

MAX

Mode Transition Time

From low-power to active, V

IN

= V

INMIN

, V

INMAX

, IL = IL

MAXLP

Mode Transition Response

From low-power to active and from active to low-power, V

IN

= V

INMIN

,

V

INMAX

, IL = IL

MAXLP

VAUDIO


MAX

V

IN

= V

INMIN

, 20 Hz to 20 kHz

+ 100 mV, > UVDET

V

IN

= V

NOM

+ 1.0 V, > UVDET


IN

100 Hz – 1.0 kHz

= V

INMIN

, IL = 0.75*ILmax

>1.0 kHz – 10 kHz

>10 kHz – 1.0 MHz

Turn-on Time


IN

= V

INMIN

, V

INMAX

, IL = 0

Turn-off Time


IN

= V

INMIN

, V

INMAX

, IL = 0

Transient Load Response - See Transient Waveforms on page 84

,

V

IN

= V

INMIN

, V

INMAX

Transient Line Response - See Transient Waveforms on page 84

IL = 75% of IL

MAX

VPLL AND VDIG ACTIVE MODE - AC


MAX

V

IN

= UVDET

, 20 Hz to 20 kHz

V

IN

= V

NOM

+ 1.0 V, > UVDET

Output Noise - V

IN

= V

INMIN

, IL = 0.75*IL

100 Hz – 1.0 kHz

MAX

>1 kHz – 1.0 MHz

Turn-on Time


IN

= V

INMIN

, V

INMAX

, IL = 0

Turn-off Time


IN

= V

INMIN

, V

INMAX

, IL = 0


V

IN

= V

INMIN

, V

INMAX


IL = 75% of IL

MAX

V

VIDEOTLIR

VVIDEOt

MOD

V

VIDEOMTR

V

AUDIOPSSR

V

AUDIOON

VAUDIOt

ON

VAUDIOt

OFF

V

AUDIOTLOR

V

AUDIOTLIR

VPLLPSSR

VPLLON

VPLLt

ON

VPLLt

OFF

V

PLLTLOR

,

V

DIGTLOR

V

PLLTLIR

V

DIGTLIR

,

–

–

–

35

50

–

–

–

–

0.1

–

–

35

50

–

–

–

0.1

–

–

5.0

–

1.0

40

60

-114

-124

-129

–

–

1.0

5.0

40

60

20

2.5

–

–

50

5.0

8.0

100

2.0

–

–

–

1.0

10

2.0

8.0

–

–

–

–

–

–

100

10

70

8.0

mV

µs

% dB dBV/



Hz ms ms

% mV dB dB/dec

µV/



Hz

µs ms mV mV

MC13892

26











BATT



4.65



V, -40



T


A =






VIOHI ACTIVE MODE - AC


MAX

V

IN

= V

INMIN

, 20 Hz to 20 kHz

+ 100 mV, > UVDET

V

IN

= V

NOM

+ 1.0 V, > UVDET

Output Noise - V

IN

= V

INMIN

, IL = 0.75*IL

100 Hz – 1.0 kHz

MAX

>1.0 kHz – 1.0 MHz

Turn-on Time


IN

= V

INMIN

, V

INMAX

, IL = 0

Turn-off Time


IN

= V

INMIN

, V

INMAX

, IL = 0


V

IN

= V

INMIN

, V

INMAX


IL = 75% of IL

MAX

Mode Transition Time -

See Transient Waveforms on page 84


IN

= V

INMIN

, V

INMAX

, IL = IL

MAXLP



IN

= V

INMIN

,

V

INMAX

, IL = IL

MAXLP

VCAM ACTIVE MODE - AC


MAX

V

IN

= V

INMIN

+ 100 mV

, 20 Hz to 20 kHz

V

IN

= V

NOM

+ 1.0 V

Output Noise - V

IN

= V

INMIN

, IL = 0.75*IL

100 Hz – 1.0 kHz

MAX

>1.0 kHz – 1.0 MHz

Turn-on Time (Enable to 90% of end value, V

IN

= V

INMIN

, V

INMAX

, IL = 0)

Turn-off Time (Disable to 10% of initial value, V

IN

= V

INMIN

, V

INMAX

, IL = 0)


V

IN

= V

INMIN

, V

INMAX

VCAM = 01, 10, 11

VCAM = 00


IL = 75% of IL

MAX




IN

= V

INMIN

, V

INMAX

, IL = IL

MAXLP


From low-power to active and from, active to low-power,



V

IN

= V

INMIN

, V

INMAX

, IL = IL

MAXLP

V

IOHIPSSR

V

IOHION

VIOHIt

ON

VIOHIt

OFF

V

IOHITLOR

V

IOHITLIR

V

IOHIMTR

V

IOHIMTR

V

CAMPSSR

V

CAMON

VCAMt

ON

VCAMt

OFF

V

CAMLOR

V

CAMLIR

VCAMt

MOD

V

CAMMTR

35

50

–

–

–

0.1

–

–

–

–

35

50

–

–

–

0.1

–

–

–

–

–

40

60

20

1.0

–

–

1.0

5.0

–

1.0

40

60

20

1.0

–

–

1.0

50

5.0

–

1.0

–

–

–

–

1.0

10

2.0

8.0

10

2.0

–

–

–

–

1.0

10

2.0

70

8.0

100

2.0

dB dB/dec

µV/



Hz ms ms

% mV

µs

% dB dB/dec

µV/



Hz ms ms

% mV mV

µs

%





MC13892

27







BATT



4.65



V, -40



T


A =






VSD ACTIVE MODE - AC


MAX

V

IN

= V

INMIN

+ 100 mV

, 20 Hz to 20 kHz

V

IN

= V

NOM

+ 1.0 V


IN

100 Hz – 1.0 kHz

= V

INMIN

, IL = 75% of IL

MAX

>1.0 kHz – 10 kHz

>10 kHz – 1.0 MHz

Turn-on Time (Enable to 90% of end value, V

IN

= V

INMIN

, V

INMAX

, IL = 0)

Turn-off Time (Disable to 10% of initial value, V

IN

= V

INMIN

, V

INMAX

, IL = 0)


V

IN

= V

INMIN

, V

INMAX

- VSD[2:0] = 010 to 111

- VSD[2:0] = 000 to 001


IL = 75% of IL

MAX




IN

= V

INMIN

, V

INMAX

, IL = IL

MAXLP

Mode Transition Response - See Transient Waveforms on page 84


IN

= V

INMIN

,

V

INMAX

, IL = IL

MAXLP

VUSB ACTIVE MODE - AC


MAX

V

IN

= V

INMIN

+ 100 mV

, 20 Hz to 20 kHz


IN

100 Hz – 50 kHz

= V

INMIN

, IL = 75% of IL

MAX

>50 kHz – 1.0 MHz

VUSB2 ACTIVE MODE - AC


MAX

V

IN

= V

INMIN

+ 100 mV

, 20 Hz to 20 kHz

V

IN

= V

NOM

+ 1.0 V

Output Noise - V

IN

= V

INMIN

, IL = 0.75*IL

100 Hz – 1.0 kHz

MAX

>1.0 kHz – 1.0 MHz

Turn-on Time


IN

= V

INMIN

, V

INMAX

, IL = 0

Turn-off Time


IN

= V

INMIN

, V

INMAX

, IL = 0

Start-up Overshoot

V

IN

= V

INMIN

, V

INMAX

, IL = 0


V

IN

= V

INMIN

, V

INMAX


IL = 75% of IL

MAX

V

SDPSSR

V

SDON

VSDt

ON

VSDt

OFF

V

SDTLOR

V

SDTLIR

VSDt

MOD

V

SDMTR

V

USBPSSR

V

USBON

V

USB2PSSR

V

USB2ON

VUSB2t

ON

VUSBt

OFF

V

USB2OS

V

USB2TLOR

V

USB2TLIR

35

50

–

–

–

–

0.1

–

–

–

–

–

35

–

–

35

50

–

–

–

0.1

–

–

–

40

60

-115

-126

-132

–

–

1.0

–

5.0

–

1.0

40

1.0

0.2

40

60

20

0.2

–

–

1.0

1.0

5.0

–

–

–

–

–

1.0

10

2.0

70

8.0

100

2.0

–

–

–

–

–

–

–

100

10

2.0

2.0

8.0

dB dBV/



Hz ms ms

% mV mV

µs

% dB

µV/



Hz dB dB/dec

µV/



Hz

µs ms

%

% mV

MC13892

28











BATT



4.65



V, -40



T


A =






UVBUS ACTIVE MODE DC

Turn-on Time

VBUS Rise Time per USB OTG with max loading of 6.5 µF+10 µF

Turn-off Time

Disable to 0.8 V, per USB OTG specification parameter VA_SESS_VLD,



V

IN

= V

INMIN

, V

INMAX

, IL = 0

VGEN1 ACTIVE MODE - AC


MAX

V

IN

= UVDET

, 20 Hz to 20 kHz

V

IN

= V

NOM

+ 1.0 V, > UVDET


IN

100 Hz – 1.0 kHz

= V

INMIN

, IL = 0.75*IL

MAX

>1.0 kHz – 10 kHz

>10 kHz – 1.0 MHz

Turn-on Time

Enable to 90% of end value V

IN

= V

INMIN

, V

INMAX

, IL = 0

Turn-off Time

Disable to 10% of initial value V

IN

= V

INMIN

, V

INMAX

, IL = 0


V

IN

= V

INMIN

, V

INMAX

- VGEN1[1:0] = 10 to 11

- VGEN[1:0] = 00 to 01


IL = 75% of IL

MAX



From low-power to active V

IN

= V

INMIN

, V

INMAX

, IL = IL

MAXLP


From low-power to active and from active to low-power



V

IN

= V

INMIN

, V

INMAX

, IL = IL

MAXLP



MAX

V

IN

= V

INMIN

+ 100 mV

, 20 Hz to 20 kHz

V

IN

= V

NOM

+ 1.0 V


IN

100 Hz – 1.0 kHz

= V

INMIN

, IL = IL

MAX

>1.0 kHz – 10 kHz

>10 kHz – 1.0 MHz

Turn-on Time


IN

= V

INMIN

, V

INMAX

, IL = 0

Turn-off Time (Disable to 10% of initial value V

IN

= V

INMIN

, V

INMAX

, IL = 0)


V

IN

= V

INMIN

, V

INMAX

- VGEN2[2:0] = 100 to 111

- VGEN2[2:0] = 000 to 011


IL = 75% of IL

MAX

UVBUSt

UVBUSt

V

V

V

V

GEN1ON

VGEN1t

VGEN1t

V

ON

OFF

GEN1TLIR

VGEN1t

MOD

V

V

GEN1PSSR

GEN1TLOR

GEN2PSSR

V

GEN1MTR

GEN2ON

VGEN2t

VGEN2t

V

ON

OFF

ON

OFF

GEN2TLOR

GEN2TLIR

–

–

35

50

–

–

–

–

0.1

–

–

–

–

–

35

50

–

–

–

–

0.1

–

–

–

–

–

40

60

-115

-126

-132

–

–

1.0

–

5.0

–

1.0

40

60

-115

-126

-132

–

–

1.0

–

5.0

100

1.3

–

–

–

–

–

1.0

10

3.0

70

8.0

100

2.0

–

–

–

–

–

1.0

10

3.0

70

8.0

ms sec dB dBV/



Hz ms ms

% mV mV

µs

% dB dBV/



Hz ms ms

% mV mV





MC13892

29







BATT



4.65



V, -40



T


A =






VGEN2 ACTIVE MODE - AC (CONTINUED)




IN

= V

INMIN

, V

INMAX

, IL = IL

MAXLP


From low-power to active and from active to low-power



V

IN

= V

INMIN

, V

INMAX

, IL = IL

MAXLP


PSRR

IL = 75% of IL

MAX

, 20 Hz to 20 kHz, V

IN

= V

INMIN

+100 mV

V

IN

= V

NOM

+1.0 V

Output Noise - V

IN

= V

INMIN

, IL = 75% of IL

MAX

100 Hz – 1.0 kHz

>1.0 kHz – 1.0 MHz

Turn-on Time


IN

= V

INMIN

, V

INMAX

, IL = 0

Turn-off Time

Disable to 10% of initial value V

IN

= V

INMIN

, V

INMAX

, IL = 0

Transient Load Response

V

IN

= V

INMIN

, V

INMAX

- VGEN3 = 1

- VGEN3 = 0

Transient Line Response (IL = 75% of IL

MAX

)

Mode Transition Time


IN

= V

INMIN

, V

INMAX

, IL = IL

MAXLP


From low-power to active and from active to low-power,



V

IN

= V

INMIN

, V

INMAX

, IL = IL

MAXLP

UVBUS - ACTIVE MODE DC

Turn-on Time - VBUS Rise Time por USB OTG with max loading of

6.5 µF+10 µF

Turn-off Time - Disable to 0.8 V, per USB OTG specification parameter

VA_SESS_VLD V

IN

= V

INMIN

, V

INMAX

, IL=0

ADC

Conversion Time per Channel - PLLX[2:0] = 100

Turn On Delay

If Switcher PLL was active

If Switcher PLL was inactive

TOUCH SCREEN

Turn-on Time - 90% of output

VGEN2t

MOD

V

GEN2MTR

V

GEN3PSSR

V

GEN3ON

VGEN3t

ON

VGEN3t

OFF

V

GEN3TLOR

V

GEN3TLIR

VGEN3t

MOD

V

GEN3MTR

–

–

35

45

–

–

–

0.1

–

–

–

–

–

–

–

–

–

–

–

–

1.0

40

50

20

1.0

–

–

1.0

–

5.0

–

1.0

–

–

–

0.0

5.0

–

100

2.0

–

–

–

–

1.0

5.0

2.0

70

8.0

100

2.0

100

1.3

10

–

10

500

µs

% dB dB/dec

µV/



Hz ms ms

% mV mV

µs

% ms sec

µs

µs

µs

MC13892

30





FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

CHARGER

CHRGRAW

1. Charger input. The charger voltage is measured through an ADC at this pin. The UVBUS pin must be shorted to CHRGRAW in cases where the charger is being supplied from the USB cable. The minimum voltage for this pin depends on BATTMIN

threshold value (see Battery Interface and Control

).

2. Output to battery supplied accessories. The battery voltage can be applied to an accessory by enabling the charge path for the accessory via the CHRGRAW pin. To accomplish this, the charger needs to be configured in reverse supply mode.

CHRGCTRL1

Driver output for charger path FET M1.

CHRGCTRL2

Driver output for charger path FET M2.

CHRGISNS

Charge current sensing point 1. The charge current is read by monitoring the voltage drop over the charge current 100 m

 sense resistor connected between CHRGISNS and BPSNS.

BPSNS

1. BP sense point. BP voltage is sensed at this pin and compared with the voltage at CHRGRAW.

2. Charge current sensing point 2. The charge current is read by monitoring the voltage drop over the charge current 100 m

 sense resistor. This resistor is connected between CHRGISNS and BPSNS.

BP

This pin is the application supply point, the input supply to the IC core circuitry. The application supply voltage is sensed through an ADC at this pin.

BATTFET

Driver output for battery path FET M3. If no charging system is required or single path is implemented, the pin BATTFET must be floating.

BATTISNS

Battery current sensing point 1. The current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNS.

BATT

Battery positive terminal. Battery current sensing point 2. The supply voltage of the battery is sensed through an ADC on this pin. The current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNS.

BATTISNSCC

Accumulated current counter current sensing point. This is the coulomb counter current sense point. It should be connected directly to the 0.020



sense resistor via a separate route from BATTISNS. The coulomb counter monitors the current flowing in/ out of the battery by integrating the voltage drop over the BATTISNCC and the BATT pin.





MC13892

31



CFP AND CFM

Accumulated current filter cap plus and minus pins respectively. The coulomb counter will require a 10

µ

F output capacitor connected between these pins to perform a first order filtering of the signal across R1.

CHRGSE1B

An unregulated wall charger configuration can be built in which case this pin must be pulled low. When charging through USB, it can be left open since it is internally pulled up to VCORE. The recommendation is to place an external FET that can pull it low or left it open, depending on the charge method.

CHRGLED

Trickle LED driver output 1. Since normal LED control via the SPI bus is not always possible in the standalone operation, a current sink is provided at the CHRGLED pin. This LED is to be connected between this pin and CHRGRAW.

GNDCHRG

Ground for charger interface.

LEDR, LEDG AND LEDB

General purpose LED driver output Red, Green and Blue respectively. Each channel provides flexible LED intensity control.

These pins can also be used as general purpose open drain outputs for logic signaling, or as generic PWM generator outputs.

GNDLED

Ground for LED drivers

IC CORE

VCORE

Regulated supply output for the IC analog core circuitry. It is used to define the PUMS VIH level during initialization. The bandgap and the rest of the core circuitry are supplied from VCORE. Place a 2.2



F capacitor from this pin to GNDCORE.

VCOREDIG

Regulated supply output for the IC digital core circuitry. No external DC loading is allowed on VCOREDIG. VCOREDIG is kept powered as long as there is a valid supply and/or coin cell. Place a 2.2



F capacitor from this pin to GNDCORE.

REFCORE

Main bandgap reference. All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at REFCORE. No external DC loading is allowed on REFCORE. Place a 100 nF capacitor from this pin to GNDCORE.

GNDCORE

Ground for the IC core circuitry.

POWER GATING

PWGTDRV1 AND PWGTDRV2

Power Gate Drivers.

PWGTDRV1 is provided for power gating peripheral loads sharing the processor core supply domain(s) SW1, and/or SW2, and/or SW3. In addition, PWGTDRV2 provides support to power gate peripheral loads on the SW4 supply domain.

In typical applications, SW1, SW2, and SW3 will both be kept active for the processor modules in state retention, and SW4 retained for the external memory in self refresh mode. SW1, SW2, and SW3 power gating FET drive would typically be connected to PWGTDRV1 (for parallel NMOS switches). SW4 power gating FET drive would typically be connected to PWGTDRV2. When

Low-power Off mode is activated, the power gate drive circuitry will be disabled, turning off the NMOS power gate switches to isolate the maintained supply domains from any peripheral loading.

MC13892

32







SWITCHERS

SW1IN, SW2IN, SW3IN AND SW4IN

Switchers 1, 2, 3, and 4 input. Connect these pins to BP to supply Switchers 1, 2, 3, and 4.

SW1FB, SW2FB, SW3FB AND SW4FB

Switchers 1, 2, 3, and 4 feedback. Switchers 1, 2, 3, and 4 output voltage sense respectively. Connect these pins to the farther point of each of their respective SWxOUT pin, in order to sense and maintain voltage stability.

SW1OUT

Switcher 1 output. Buck regulator for processor core(s).

GNDSW1

Ground for Switcher 1.

SW2OUT

Switcher 2 output. Buck regulator for processor SOG, etc.

GNDSW2

Ground for Switcher 2.

SW3OUT

Switcher 3 output. Buck regulator for internal processor memory and peripherals.

GNDSW3

Ground for switcher 3.

SW4OUT

Switcher 4 output. Buck regulator for external memory and peripherals.

GNDSW4

Ground for switcher 4.

DVS1 AND DVS2

Switcher 1 and 2 DVS input pins. Provided for pin controlled DVS on the buck regulators targeted for processor core supplies.

The DVS pins may be reconfigured for Switcher Increment / Decrement (SID) mode control. When transitioning from one voltage to another, the output voltage slope is controlled in steps of 25 mV per time step. These pins must be set high in order for the

DVS feature to be enabled for each of switchers 1 or 2, or low to disable it.

SWBSTIN

Switcher BST input. The 2.2



H switcher BST inductor must be connected here.

SWBSTOUT

Power supply for gate driver for the internal power NMOS that charges SWBST inductor. It must be connected to BP.

SWBSTFB

Switcher BST feedback. When SWBST is configured to supply the UVBUS pin in OTG mode the feedback will be switched to sense the UVBUS pin instead of the SWBSTFB pin.

GNDSWBST

Ground for switcher BST.





MC13892

33



REGULATORS

VINIOHI

Input of VIOHI regulator. Connect this pin to BP in order to supply VIOHI regulator.

VIOHI

Output regulator for high voltage IO. Fixed 2.775 V output for high-voltage level interface.

VINPLL AND VINDIG

The input of the regulator for processor PLL and Digital regulators respectively. VINDIG and VINPLL can be connected to either BP or a 1.8 V switched mode power supply rail, such as from SW4 for the two lower set points of each regulator (the 1.2 and 1.25 V output for VPLL, and 1.05 and 1.25 V output for VDIG). In addition, when the two upper set points are used (1.50 and

1.8 V outputs for VPLL, and 1.65 and 1.8 V for VDIG), they can be connected to either BP or a 2.2 V nominal external switched mode power supply rail, to improve power dissipation.

VPLL

Output of regulator for processor PLL. Quiet analog supply (PLL, GPS).

VDIG

Output regulator Digital. Low voltage digital (DPLL, GPS).

VVIDEODRV

Drive output for VVIDEO external PNP transistor.

VVIDEO

Output regulator TV DAC. This pin must be connected to the collector of the external PNP transistor of the VVIDEO regulator.

VINAUDIO

Input regulator VAUDIO. Typically connected to BP.

VAUDIO

Output regulator for audio supply.

VINUSB2

Input regulator VUSB2. This pin must always be connected to BP even if the regulators are not used by the application.

VUSB2

Output regulator for powering USB PHY.

VINCAMDRV

1. Input regulator camera using internal PMOS FET. Typically connected to BP.

2. Drive output regulator for camera voltage using external PNP device. In this case, this pin must be connected to the base of the PNP in order to drive it.

VCAM

Output regulator for the camera module. When using an external PNP device, this pin must be connected to its collector.

VSDDRV

Drive output for the VSD external PNP transistor.

VSD

Output regulator for multi-media cards such as micro SD, RS-MMC.

MC13892

34







VGEN1DRV

Drive output for the VGEN1 external PNP transistor.

VGEN1

Output of general purpose 1 regulator.

VGEN2DRV

Drive output for the VGEN2 external PNP transistor.

VGEN2


VINGEN3DRV

1. Input for the VGEN3 regulator when no external PNP transistor used. Typically connected to BP.

2. Drive output for VGEN3 in case an external PNP transistor is used on the application. In this case, this pin must be connected the base of the PNP transistor.

VGEN3


VSRTC

Output regulator for the SRTC module on the processor. The VSRTC regulator provides the CLK32KMCU output level (1.2 V).

Additionally, it is used to bias the low-power SRTC domain of the SRTC module integrated on certain FSL processors.

GNDREG1

Ground for regulators 1.

GNDREG2


GNDREG3


GENERAL OUTPUTS

GPO1

General purpose output 1. Intended to be used for battery thermistor biasing. In this case, connect a 10 K



resistor from GPO1 to ADIN5, and one from ADIN5 to GND.

GPO2

General purpose output 2.

GPO3

General purpose output 3.

GPO4

General purpose output 4. It can be configured for a muxed connection into Channel 7 of the GP ADC.





MC13892

35



CONTROL LOGIC

LICELL

Coin cell supply input and charger output. The LICELL pin provides a connection for a coin cell backup battery or supercap.

If the main battery is deeply discharged, removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell maintained logic will switch over to the LICELL for backup power. This pin also works as a current-limited voltage source for battery charging. A small capacitor should be placed from LICELL to ground under all circumstances.

XTAL1

32.768 kHz Oscillator crystal connection 1.

XTAL2

32.768 kHz Oscillator crystal connection 2.

GNDRTC

Ground for the RTC block.

CLK32K

32 kHz Clock output for peripherals. At system start-up, the 32 kHz clock is driven to CLK32K (provided as a peripheral clock reference), which is referenced to SPIVCC. The CLK32K is restricted to state machine activation in normal on mode.

CLK32KMCU

32 kHz Clock output for processor. At system start-up, the 32 kHz clock is driven to CLK32KMCU (intended as the CKIL input to the system processor) referenced to VSRTC. The driver is enabled by the start-up sequencer and the CLK32KMCU is programmable for Low-power Off mode control by the state machine.

RESETB AND RESETBMCU

Reset output for peripherals and processor respectively. These depend on the Power Control Modes of operation (

See

Functional Device Operation on page 40 ). These are meant as reset for the processor, or peripherals in a power up condition, or

to keep one in reset while the other is up and running.

WDI

Watchdog input. This pin must be high to stay in the On mode. The WDI IO supply voltage is referenced to SPIVCC (normally connected to SW4 = 1.8 V). SPIVCC must therefore remain enabled to allow for proper WDI detection. If WDI goes low, the system will transition to the Off state or Cold Start (depending on the configuration).

STANDBY AND STANDBYSEC

Standby input signal from processor and from peripherals respectively.

To ensure that shared resources are properly powered when required, the system will only be allowed into Standby when both the application processor (which typically controls the STANDBY pin) and peripherals (which typically control the STANDBYSEC pin) allow it. This is referred to as a Standby event.

The Standby pins are programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into account the programmed input polarities associated with each pin. Since the Standby pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin level changes.

The state of the Standby pins only have influence in the On mode and are therefore ignored during start up and in the

Watchdog phase. This allows the system to power up without concern of the required Standby polarities, since software can make adjustments accordingly, as soon as it is running.

INT

Interrupt to processor. Unmasked interrupt events are signaled to the processor by driving the INT pin high.

MC13892

36







PWRON1, 2 AND 3

A turn on event can be accomplished by connecting an open drain NMOS driver to the PWRONx pin of the MC13892, so that it is in effect a parallel path for the power key.

In addition to the turn on event, the MC13892A/B/C/D versions include a global reset feature on the PWRON3 pin.



On the A/B/C/D versions, the GLBRSTENB defaults to 0. In the MC13892A/C versions global reset is active low. Since

GLBRSTENB defaults to 0, the global reset feature is enabled by default. In the MC13892B/D versions global reset is active high.

Since GLBRSTENB defaults to 0, the global reset feature is disabled by default. The global reset function can be enabled or disabled by changing the SPI bit GLBRSTENB at any time, as shown in table below:

Device

MC13892

MC13892A

MC13892B

MC13892C

MC13892D

Global Reset

Function

NO

YES

GLBRSTENB

Configuration

N/A

Active low

YES

YES

YES

Active HI

Active low

Active HI

GLBRSTENB

N/A

0 = Enabled (default)

1 = Disabled

0 = Disabled (default)

1 = Enabled

0 = Enabled (default)

1 = Disabled

0 = Disabled (default)

1 = Enabled

The global reset feature powers down the part, disables the charger, resets the SPI registers to their default value and then powers back on. To generate a global reset, the PWRON3 pin needs to be pulled low for greater than 12 seconds and then pulled back high. If the PWRON3 pin is held low for less than 12 seconds, the pin will act as a normal PWRON pin.

PUMS1 AND PUMS2

Power up mode supply setting. Default start-up of the device is selectable by hardwiring the Power Up Mode Select pins. The

Power Up Mode Select pins (PUMS1 and PUMS2) are used to configure the start-up characteristics of the regulators. Supply enabling and output level options are selected by hardworking the PUMS pins for the desired configuration.

MODE

USB LBP mode, normal mode, test mode selection & anti-fuse bias. During evaluation and testing, the IC can be configured for normal operation or test mode via the MODE pin as summarized in the following table.

MODE PIN STATE

Ground

VCOREDIG

VCORE

MODE

Normal Operation

USB Low-power Boot Allowed

Test Mode

GNDCTRL

Ground for control logic.

SPIVCC

Supply for SPI bus and audio bus

CS

CS held low at Cold Start configures the interface for SPI mode. Once activated, CS functions as the SPI Chip Select. CS tied to VCORE at Cold Start configures the interface for I

2

C mode; the pin is not used in I

2

C mode other than for configuration.

Because the SPI interface pins can be reconfigured for reuse as an I

2

C interface, a configuration protocol mandates that the

CS pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin).





MC13892

37



CLK

Primary SPI clock input. In I

2

C mode, this pin is the SCL signal (I

2

C bus clock).

MOSI

Primary SPI write input. In I

2

C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible addresses (A0 address selection).

MISO

Primary SPI read output. In I

2

C mode, this pin is the SDA signal (bi-directional serial data line).

GNDSPI

Ground for SPI interface.

USB

UID

This pin identifies if a mini-A or mini-B style plug has been connected to the application. The state of the ID detection can be read via the SPI, to poll dedicated sense bits for a floating, grounded, or factory mode condition on the UID pin.

UVBUS

1. USB transceiver cable interface.

2. OTG supply output.

When SWBST is configured to supply the UVBUS pin in OTG mode, the feedback will switch to sense the UVBUS pin instead of the SWBSTFB pin.

VUSB

This is the regulator used to provide a voltage to an external USB transceiver IC.

VINUSB

Input option for VUSB; supplied by SWBST. This pin is internally connected to the UVBUS pin for OTG mode operation (for more details about OTG mode).

Note: When VUSBIN = 1, UVBUS will be connected via internal switches to VINUSB and incur some current drain on that pin, as much as 270



A maximum, so care must be taken to disable this path and set this SPI bit (VUSBIN) to 0 to minimize current drain, even if SWBST and/or VUSB are disabled.

VBUSEN

External VBUS enable pin for the OTG supply. VBUS is defined as the power rail of the USB cable (+5.0 V).

A TO D CONVERTER

Note: The ADIN5/6/7 inputs must not exceed BP.

ADIN5

ADC generic input channel 5. ADIN5 may be used as a general purpose unscaled input, but in a typical application, ADIN5 is used to read out the battery pack thermistor. The thermistor must be biased with an external pull-up to a voltage rail greater than the ADC input range. In order to save current when the thermistor reading is not required, it can be biased from one of the general purpose IOs such as GPO1. A resistor divider network should assure the resulting voltage falls within the ADC input range, in particular when the thermistor check function is used.

ADIN6

ADC generic input channel 6. ADIN6 may be used as a general purpose unscaled input, but in a typical application, the PA thermistor is connected here.

MC13892

38







ADIN7

ADC generic input channel 7, group 1. ADIN7 may be used as a general purpose unscaled input or as a divide by 2 scaled input. In a typical application, an ambient light sensor is connected here. A second general purpose input ADIN7B is available on channel 7. This input is muxed on the GPO4 pin. In the application, a second ambient light sensor is supposed to be connected here.

TSX1 AND TSX2, TSY1 AND TSY2 -

Note: The TS[xy] [12] inputs must not exceed BP or VCORE.

Touch Screen Interfaces X1 and X2, Y1 and Y2. The touch screen X plate is connected to TSX1 and TSX2, while the Y plate is connected to Y1 and Y2. In inactive mode, these pins can also be used as general purpose ADC inputs. They are respectively mapped on ADC channels 4, 5, 6, and 7. In interrupt mode, a voltage is applied to the X-plate (TSX2) via a weak current source to VCORE, while the Y-plate is connected to ground (TSY1).

TSREF

Touch Screen Reference regulator. This regulator is powered from VCORE. In applications not supporting touch screen, the

TSREF can be used as a low current general purpose regulator, or it can be kept disabled and the bypass capacitor omitted.

ADTRIG

ADC trigger input. A rising edge on this pin will start an ADC conversion.

GNDADC

Ground for A to D circuitry.

THERMAL GROUNDS

GNDSUB1-9

General grounds and thermal heat sinks.





MC13892

39

FUNCTIONAL DEVICE OPERATION

PROGRAMMABILITY

FUNCTIONAL DEVICE OPERATION

PROGRAMMABILITY

INTERFACING OVERVIEW AND CONFIGURATION OPTIONS

The MC13892 contains a number of programmable registers for control and communication. The majority of registers are accessed through a SPI interface in a typical application. The same register set may alternatively be accessed with an I

2

C interface that is muxed on SPI pins. The following table describes the muxed pin options for the SPI and I

2

C interfaces. Further details for each interface mode follow in this chapter.

Table 7. SPI / I

2

C Bus Configuration

CS

CLK

MISO

MOSI

Pin Name SPI Mode Functionality

Configuration

(43)

SPI Clock

, Chip Select

Master In, Slave Out (data output)

Master Out, Slave In (data input)

I2C Mode Functionality

Configuration

(44)

SCL: I

2

C bus clock

SDA: Bi-directional serial data line

A0 Address Selection

(45)

Notes

43.

CS held low at Cold Start configures interface for SPI mode; once activated, CS functions as the SPI Chip Select.

44.

CS tied to VCORE at Cold Start configures interface for I

2

C mode; the pin is not used in I

2

C mode other than for configuration.

45.

In I

2

C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible addresses.

SPI INTERFACE

The MC13892 contains a SPI interface port, which allows access by a processor to the register set. Via these registers, the resources of the IC can be controlled. The registers also provide status information about how the IC is operating, as well as information on external signals.

The SPI interface pins can be reconfigured for reuse as an I

2

C interface. As a result, a configuration protocol mandates that the CS pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin. With the CS pin held low during startup (as would be the case if connected to the CS driver of an unpowered processor, due to the integrated pull-down), the bus configuration will be latched for SPI mode.

The SPI port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. The addressable register map spans 64 registers of 24 data bits each.

The general structure of the register set is given in the following table. Bit names, positions, and basic descriptions are provided in

SPI Bitmap . Expanded bit descriptions are included in the following functional chapters for application guidance. For

brevity's sake, references are occasionally made herein to the register set as the “SPI map” or “SPI bits”, but note that bit access is also possible through the I

2

C interface option, so such references are implied as generically applicable to the register set accessible by either interface.

6

7

4

5

2

3

0

1

8

9

10

11

Table 8. Register Set

Register

Interrupt Status 0

Interrupt Mask 0

Interrupt Sense 0

Interrupt Status 1

Interrupt Mask 1

Interrupt Sense 1

20

21

Power Up Mode Sense 22

Identification 23

16

17

18

19

Unused

ACC 0

ACC 1

Unused

24

25

26

27

Register

Unused

Unused

Memory A

Memory B

RTC Time

RTC Alarm

RTC Day

RTC Day Alarm

Switchers 0

Switchers 1

Switchers 2

Switchers 3

36

37

38

39

32

33

34

35

40

41

42

43

Register

Regulator Mode 0

Regulator Mode 1

Power Miscellaneous

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

ADC 0

52

53

54

55

48

49

50

51

56

57

58

59

Register

Charger 0

USB0

Charger USB1

LED Control 0

LED Control 1

LED Control 2

LED Control 3

Unused

Unused

Trim 0

Trim 1

Test 0

MC13892

40






PROGRAMMABILITY

Table 8. Register Set

12

13

14

15

Register

Unused

Power Control 0

Power Control 1

Power Control 2

28

29

30

31

Register

Switchers 4

Switchers 5

Regulator Setting 0

Regulator Setting 1

44

45

46

47

The SPI interface is comprised of the package pins listed in

Table 9 .

Register

ADC 1

ADC 2

ADC 3

ADC4

Table 9. SPI Interface Pin Description

SPI Bus

CLK

MOSI

MISO

CS

Interrupt

INT

Supply

SPIVCC

Description

Clock input line, data shifting occurs at the rising edge

Serial data input line

Serial data output line

Clock enable line, active high

Description

Interrupt to processor

Description

Processor SPI bus supply

60

61

62

63

Register

Test 1

Test 2

Test 3

Test 4

SPI INTERFACE DESCRIPTION

The control bits are organized into 64 fields. Each of these 64 fields contains 32-bits. A maximum of 24 data bits are used per field. In addition, there is one “dead” bit between the data and address fields. The remaining bits include 6 address bits to address the 64 data fields and one write enable bit to select whether the SPI transaction is a read or a write.

The register set will be to a large extent compatible with the MC13783, in order to facilitate software development.

For each SPI transfer, first a one is written to the read/write bit if this SPI transfer is to be a write. A zero is written to the read/ write bit if this is to be a read command only.

The CS line must remain high during the entire SPI transfer. To start a new SPI transfer, the CS line must go inactive and then go active again. The MISO line will be tri-stated while CS is low.

To read a field of data, the MISO pin will output the data field pointed to by the 6 address bits loaded at the beginning of the

SPI sequence.

Figure 5. SPI Transfer Protocol Single Read/Write Access





MC13892

41


PROGRAMMABILITY

Figure 6. SPI Transfer Protocol Multiple Read/Write Access

SPI ELECTRICAL & TIMING REQUIREMENTS

The following diagram and table summarize the SPI electrical and timing requirements. The SPI input and output levels are set independently via the SPIVCC pin by connecting it to the desired supply. This would typically be tied to SW4 programmed for 1.80 V. The strength of the MISO driver is programmable through the SPIDRV[1:0] bits.

Figure 7. SPI Interface Timing Diagram

MC13892

42






PROGRAMMABILITY

Table 10. SPI Interface Timing Specifications

Parameter Description

t

SELSU t

SELHLD t

SELLOW t

CLKPER t

CLKHIGH t

CLKLOW t

WRTSU t

WRTHLD t

RDSU t

RDHLD t

RDEN t

RDDIS

Time CS has to be high before the first rising edge of CLK

Time CS has to remain high after the last falling edge of CLK

Time CS has to remain low between two transfers

Clock period of CLK

Part of the clock period where CLK has to remain high

Part of the clock period where CLK has to remain low

Time MOSI has to be stable before the next rising edge of CLK

Time MOSI has to remain stable after the rising edge of CLK

Time MISO will be stable before the next rising edge of CLK

Time MISO will remain stable after the falling edge of CLK

Time MISO needs to become active after the rising edge of CS

Time MISO needs to become inactive after the falling edge of CS

Notes

46.

This table reflects a maximum SPI clock frequency of 26 MHz

Table 11. SPI Interface Logic IO Specifications

Parameter

Input Low CS, MOSI, CLK

Input High CS, MOSI, CLK

Output Low MISO, INT

Output High MISO, INT

SPIVCC Operating Range

Condition

Output sink 100



A

Output source 100



A

MISO Rise and Fall Time

CL = 50 pF, SPIVCC = 1.8 V

SPIDRV[1:0] = 00 (default)

SPIDRV[1:0] = 01

SPIDRV[1:0] = 10

SPIDRV[1:0] = 11

Min

0.0

0.7*SPIVCC

0

SPIVCC-0.2

1.75

–

–

–

–

11

6.0

High Z

22

Typ

–

–

–

–

–

Max

0.3*SPIVCC

SPIVCC+0.3

0.2

SPIVCC

3.1

–

–

–

–

t min (ns)

15

15

4.0

4.0

15

15

15

38

4.0

4.0

4.0

4.0

Units

V

V

V

V

V ns ns ns ns





MC13892

43


I2C INTERFACE

I

2

C INTERFACE

I

2

C CONFIGURATION

When configured for I

2

C mode (see

Table 7 ) the interface may be used to access the complete register map previously

described for SPI access. The MC13892 can function only as an I

2

C slave device, not as a host.

I

2

C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for bus conflict avoidance, pin programmable selection is provided through the MOSI pin to allow configuration for the address

LSB(s). This product supports 7-bit addressing only; support is not provided for 10-bit or General Call addressing.

The I

2

C mode of the interface is implemented generally following the Fast Mode definition which supports up to 400 kbits/s operation. Timing diagrams, electrical specifications, and further details can be found in the I

2

C specification.

Standard I

2

C protocol utilizes packets of 8-bits (bytes), with an acknowledge bit (ACK) required between each byte. However, the number of bytes per transfer is unrestricted. The register map of the MC13892 is organized in 24-bit registers which corresponds to the 24-bit words supported by the SPI protocol of this product. To ensure that the I

2

C operation mimics SPI transactions in behavior of a complete 24-bit word being written in one transaction, software is expected to perform write transactions to the device in 3 byte sequences, beginning with the MSB. Internally, data latching will be gated by the acknowledge at the completion of writing the third consecutive byte.

Failure to complete a 3 byte write sequence will abort the I

2

C transaction and the register will retain its previous value. This could be due to a premature STOP command from the master.

I

2

C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and 3 bytes will be sent out, unless a STOP command or NACK is received prior to completion.

The following examples show how to write and read data to the IC. The host initiates and terminates all communication. The host sends a master command packet after driving the start condition. The device will respond to the host if the master command packet contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK to transmissions from the host. If at any time a NAK is received, the host should terminate the current transaction and retry the transaction.

I

2

C DEVICE ID

The I

2

C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for bus conflict avoidance, pin programmable selection is provided to allow configuration for the address LSB(s). This product supports 7-bit addressing only. Support is not provided for 10-bit or General Call addressing.

Because the MOSI pin is not utilized for I

2

C communication, it is reassigned for pin programmable address selection by hardwiring to VCORE or GND at the board level, when configured for I

2

C mode. MOSI will act as Bit 0 of the address. The I

2

C address assigned to FSL PM ICs (shared amongst our portfolio) is as follows:

00010-A1-A0, where the A1 and A0 bits are allowed to be configured for either 1 or 0. It is anticipated for a maximum of two

FSL PM ICs on a given board, which could be sharing an I

2

C bus. The A1 address bit is internally hard wired as a “0”, leaving the LSB A0 for board level configuration. The A1 bit will be implemented such that it can be re-wired as a “1” (with a metal change or fuse trim), if conflicts are encountered before the final production material is manufactured. The designated address is defined as: 000100-A0.

I

2

C OPERATION

The I

2

C mode of the interface is implemented, generally following the Fast mode definition, which supports up to 400 kbits/s operation. The exceptions to the standard are noted to be 7-bit only addressing, and no support for General Call addressing.

Timing diagrams, electrical specifications, and further details can be found in the I

2

C specification, which is available for download at: http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf

Standard I

2

C protocol utilizes bytes of 8-bits, with an acknowledge bit (ACK) required between each byte. However, the number of bytes per transfer are unrestricted. The register map is organized in 24-bit registers, which corresponds to the 24-bit words supported by the SPI protocol of this product. To ensure that I

2

C operation mimics SPI transactions in behavior of a complete 24-bit word being written in one transaction. The software is expected to perform write transactions to the device in 3 byte sequences, beginning with the MSB. Internally, data latching will be gated by the acknowledge at the completion of writing the third consecutive byte.

Failure to complete a 3 byte write sequence will abort the I

2

C transaction, and the register will retain its previous value. This could be due to a premature STOP command from the master, for example. I

2

C read operations are also performed in byte

MC13892

44






I2C INTERFACE

increments separated by an ACK. Read operations also begin with the MSB, and 3 bytes will be sent out unless a STOP command or NACK is received prior to completion.

The following examples show how to write and read data to the IC. The host initiates and terminates all communication. The host sends a master command packet after driving the start condition. The device will respond to the host if the master command packet contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK to transmissions from the host. If at any time a NAK is received, the host should terminate the current transaction and retry the transaction.

Figure 8. I

2

C 3 Byte Write Example





Figure 9. I

2

C 3 Byte Read Example

MC13892

45


I2C INTERFACE

INTERRUPT HANDLING

CONTROL

The MC13892 has interrupt generation capability to inform the system on important events occurring. An interrupt is signaled to the processor by driving the INT pin high. This is true whether the communication interface is configured for the SPI or I

2

C.

Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each interrupt can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register. This will also cause the interrupt line to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high.

Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor the option of polling for status from the IC. The IC powers up with all interrupts masked except the USB low-power boot, so the processor must initially poll the device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the interrupt line will go high after unmasking.

The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources.

They are read only, and not latched or clearable.

Interrupts generated by external events are debounced, meaning that the event needs to be stable throughout the debounce period before an interrupt is generated.

BIT SUMMARY

Table 12 summarizes all interrupt, mask, and sense bits associated with INT control. For more detailed behavioral

descriptions, refer to the related chapters.

Table 12. Interrupt, Mask and Sense Bits

Interrupt Mask Sense Section

ADCDONEI

ADCBISDONEI

TSI

CHGDETI

USBOVI

CHGREVI

CHGSHORTI

CHGFAULTI

CHGCURRI

CCCVI

BPONI

LOBATLI

BVALIDI

ADCDONEM

ADCBISDONEM

TSM

CHGDETM

USBOVM

CHGREVM

CHGSHORTM

CHGFAULTM

CHGCURRM

CCCVM

BPONM

LOBATLM

BVALIDM

–

–

–

CHGDETS

CHGENS

USBOVS

–

–

CHGFAULTS[1:0]

CHGCURRS

CCCVS

BPONS

LOBATLS

BVALIDS

Purpose

ADC has finished requested conversions

ADCBIS has finished requested conversions

Touch screen wake-up

Charger detection sense is 1 if detected

Charger state sense is 1 if active

VBUS over-voltage

Sense is 1 if above threshold

Charger path reverse current

Charger path short circuit

Charger fault detection

00 = Cleared, no fault

01 = Charge source fault

10 = Battery fault

11 = Battery temperature

Charge current below threshold


CCCVI transition detection

BP turn on threshold detection.

Sense is 1 if above threshold.

Low battery detect

Sense is 1 if below LOBATL threshold

USB B-session valid


L2H

L2H

Dual

Dual

Dual

L2H

L2H

L2H

H2L

Dual

L2H

L2H

Dual

0

0

30ms

32 ms

100 ms

60

 s

1.0 ms

1.0 ms

10 ms

1.0 ms

100 ms

30 ms

0

L2H: 20-

24 ms

H2L: 8-

12 ms

page 100 page 100 page 100

page 89 page 89 page 89 page 89 page 89 page 89 page 89

page 54 page 54

page 111

MC13892

46






I2C INTERFACE

Table 12. Interrupt, Mask and Sense Bits

Interrupt Mask Sense Purpose Section

LOBATHI LOBATHM LOBATHS

Low battery warning

Sense is 1 if above LOBATH threshold.

Dual 30

 s

VBUSVALIDI VBUSVALIDM VBUSVALIDS Detects A-Session Valid on VBUS Dual

L2H: 20-

24 ms

H2L: 8-

12 ms

IDFLOATI

IDGNDI

IDFACTORYI

CHRGSE1BI

SCPI

BATTDETBI

1HZI

TODAI

PWRON1I

PWRON2I

PWRON3I

SYSRSTI

WDIRESETI

PCI

WARMI

MEMHLDI

CLKI

RTCRSTI

THWARNHI

THWARNLI

IDFLOATM

IDGNDM

IDFACTORYM

CHRGSE1BM

SCPS

BATTDETBM

1HZM

TODAM

PWRON1M

PWRON2M

PWRON3M

SYSRSTM

WDIRESETM

PCM

WARMM

MEMHLDM

CLKM

RTCRSTM

THWARNHM

THWARNLM

IDFLOATS

IDGNDS

IDFACTORYS

CHRSE1BS

–

BATTDETBS

–

–

PWRON1S

PWRON2S

PWRON3S

–

–

–

–

–

CLKS

–

THWARNHS

THWARNLS

ID floating detect. Sense is 1 if above threshold

USB ID ground detect. Sense is 1 if not to ground

ID voltage for Factory mode detect


Wall charger detect

Regulator short-circuit protection tripped

Short circuit protection trip detection

Battery removal detect

1.0 Hz time tick

Time of day alarm

PWRON1 event

Sense is 1 if pin is high.

PWRON2 event


PWRON3 event


System reset through PWRONx pins

WDI silent system restart

Power cut event

Warm Start event

Memory Hold event

Clock source change

Sense is 1 if source is XTAL

RTC reset or intrusion has occurred

Thermal warning higher threshold


Thermal warning lower threshold


Low-power boot interrupt

Dual

Dual

Dual

Dual

L2H

L2H

Dual

L2H

L2H

H2L

L2H

H2L

L2H

H2L

L2H

L2H

L2H

L2H

L2H

L2H

Dual

L2H

Dual

Dual

90

90

90

0

0

0

0







200 s s s

1.0 ms



30 ms

0

0 s

30 ms

(1)

30 ms

30 ms

(47)

30 ms

30 ms

30 ms

0

0

0

0

30 ms

30 ms

(47)

LPBI LPBM LPBS Dual 1.0 ms

Notes

47.

Debounce timing for the falling edge can be extended with PWRONxDBNC[1:0]; refer to Power Control System for details.

page 54

page 111 page 111 page 111 page 111

page 89

page 71

page 100

page 49 page 49

page 54 page 54 page 54 page 54 page 54 page 54 page 54 page 54 page 54 page 54 page 54

page 49 page 49

page 71 page 71

page 89

Additional sense bits are available to reflect the state of the power up mode selection pins, as summarized in Table 13 .





MC13892

47


I2C INTERFACE

Table 13. Additional Sense Bits

Sense

MODES[1:0]

PUMSxS[1:0]

CHRGSSS

00 = MODE grounded

10 = MODE to VCOREDIG

11 = MODE to VCORE

00 = PUMS grounded

01 = PUMS open

10 = PUMS to VCOREDIG

11 = PUMS to VCORE

0 = Single path

1 = Serial path

Description Section

page 40

page 54

page 89

SPECIFIC REGISTERS

IDENTIFICATION

The MC13892 parts can be identified though identification bits which are hardwired on chip.

The version of the MC13892 can be identified by the ICID[2:0] bits. This is used to distinguish future derivatives or customizations of the MC13892. The bits are set to ICID[2:0] = 111 and are located in the revision register.

The revision of the MC13892 is tracked with the revision identification bits REV[4:0]. The bits REV[4:3] track the full mask set revision, where bits REV[2:0] track the metal revisions. These bits are hardwired.

Table 14. IC Revision Bit Assignment

Bits REV[4:0]

10001

IC Revision

Pass 3.1

The bits FIN[3:0] are Freescale use only and are not to be explored by the application.

The MC13892 die is produced using different wafer fabrication plants. The plants can be identified via the FAB[1:0] bits. These bits are hardwired.

MEMORY REGISTERS

The MC13892 has a small general purpose embedded memory of two times 24-bits to store critical data. The data is maintained when the device is turned off and when in a power cut. The contents are only reset when a RTC reset occurs, see

Clock Generation and Real Time Clock

.

MC13892

48






CLOCK GENERATION AND REAL TIME CLOCK

CLOCK GENERATION AND REAL TIME CLOCK

CLOCK GENERATION

The MC13892 generates a 32.768 kHz clock as well as several 32.768 kHz derivative clocks that are used internally for control.

Support is also provided for an external Secure Real Time Clock (SRTC) which may be integrated on a companion system processor IC. For media protection in compliance with Digital Rights Management (DRM) system requirements, the

CLK32KMCU can be provided as a reference to the SRTC module where tamper protection is implemented.

CLOCKING SCHEME

The MC13892 contains an internal 32 kHz oscillator, that delivers a 32 kHz nominal frequency (20%) at its outputs when an external 32.768 kHz crystal is not present.

If a 32.768 kHz crystal is present and running, then all control functions will run off the crystal derived 32 kHz oscillator. In absence of a valid supply at the BP supply node (for instance due to a dead battery), the crystal oscillator continues running, supplied from the coin cell battery until the coin cell is depleted.

The 32 kHz clock is driven to two output pins, CLK32KMCU (intended as the CKIL input to the system processor) is referenced to VSRTC, and CLK32K (provided as a clock reference for the peripherals) is referenced to SPIVCC. The driver is enabled by the startup sequencer, and CLK32KMCU is programmable for Low-power Off mode, controlled by the state machine.

Additionally, a SPI bit CLK32KMCUEN bit is provided for direct SPI control. The CLK32KMCUEN bit defaults to a 1 and resets on RTCPORB, to ensure the buffer is activated at the first power up and configured as desired for subsequent power ups.

CLK32K is restricted to state machine activation in normal On mode.

The drive strength of the CLK32K output drivers are programmable with CLK32KDRV[1:0] (master control bits that affect the drive strength of CLK32K).

During a switchover between the two clock sources (such as when the crystal oscillator is starting up), the output clock is maintained at a stable active low or high phase of the internal 32 kHz clock to avoid any clocking glitches. If the XTAL clock source suddenly disappears during operation, the IC will revert back to the internal clock source. Given the unpredictable nature of the event and the startup times involved, the clock may be absent long enough for the application to shut down during this transition, for example, due to a sag in the switchover output voltage, or absence of a signal on the clock output pins.

A status bit, CLKS, is available to indicate to the processor which clock is currently selected: CLKS=0 when the internal RC is used, and CLKS=1 if the XTAL source is used. The CLKI interrupt bit will be set whenever a change in the clock source occurs, and an interrupt will be generated if the corresponding CLKM mask bit is cleared.

OSCILLATOR SPECIFICATIONS

The crystal oscillator has been designed for use in conjunction with the Micro Crystal CC7V-T1A-32.768 kHz-9pF-30 ppm or equivalent (such as Micro Crystal CC5V-T1A or Epson FC135).

Table 15. RTC Crystal Specifications

Nominal Frequency

Make Tolerance

Temperature Stability

Series Resistance

Maximum Drive Level

Operating Drive Level

Nominal Load Capacitance

Pin-to-pin Capacitance

Aging

32.768 kHz

+/-30 ppm

-0.038 ppm /C

2

80 kOhm

1.0



W

0.25 to 0.5



W

9.0 pF

1.4 pF

3 ppm/year

The oscillator also accepts a clock signal from an external source. This clock signal is to be applied to the XTAL1 pin, where the signal can be DC or AC coupled. A capacitive divider can be used to adapt the source signal to the XTAL1 input levels. When applying an external source, the XTAL2 pin is to be connected to VCOREDIG.

The electrical characteristics of the 32 kHz Crystal oscillator are given in the table below, taking into account the above crystal characteristics





MC13892

49



Table 16. Crystal Oscillator Main Characteristics

Parameter Condition

Operating Voltage

Coin cell Disconnect Threshold

RTC oscillator startup time

XTAL1 Input Level

XTAL1 Input Range

Output Low CLK32K,

CLK32KMCU

Oscillator and RTC Block from BP

At LICELL

Upon application of power

External clock source

External clock source

Output sink 100



A

Output High

CLK32K Rise and Fall Time

CLK32K Output source 100



A

CLK32KMCU Output source 100



A

CL=50 pF

CLK32KDRV[1:0] = 00 (default)

CLK32KDRV[1:0] = 01

CLK32KDRV[1:0] = 10

CLK32KDRV[1:0] = 11

CLD32KMCU Rise and Fall Time CL=12 pF

CLK32K and CLK32KMCU

Output Duty Cycle

Crystal on XTAL1, XTAL2 pins

Min

1.2

1.8

-

0.3

-0.5

0

SPIVCC-0.2

VSRTC-0.2

–

–

–

–

–

45

Typ

–

–

–

–

–

–

–

–

22

11

High Z

44

22

–

Max

4.65

2.0

1.0

-

1.2

0.2

SPIVCC

VSRTC

–

–

–

–

–

55

Units

V

V sec

V

PP

V

V

V

V ns ns ns ns ns

%

OSCILLATOR APPLICATION GUIDELINES

The guidelines below may prove to be helpful in providing a crystal oscillator that starts reliably and runs with minimal jitter.

PCB leakage: The RTC amplifier is a low-current circuit. Therefore, PCB leakage may significantly change the operating point of the amplifier and even the drive level to the crystal. (Changing the drive level to the crystal may change the aging rate, jitter, and even the frequency at a given load capacitance.) The traces should be kept as short as possible to minimize the leakage, and good PCB manufacturing processes should be maintained.

Layout: The traces from the MC13892 to the crystal, load capacitance, and the RTC Ground are sensitive. They must be kept as short as possible with minimal coupling to other signals. The signal ground for the RTC is to be connected to GNDRTC, and via a single connection, GNDRTC to the system ground. The CLK32K and CLK32KMCU square wave outputs must be kept away from the crystal / load capacitor leads, as the sharp edges can couple into the circuit and lead to excessive jitter. The crystal / load capacitance leads and the RTC Ground must form a minimal loop area.

Crystal Choice: Generally speaking, crystals are not interchangeable between manufacturers, or even different packages for a given manufacturer. If a different crystal is considered, it must be fully characterized with the MC13892 before it can be considered.

Tuning Capacitors: The nominal load capacitance is 9.0 pF, therefore the total capacitance at each node should be 18 pF, composed out of the load capacitance, the effective input capacitance at each pin, plus the PCB stray capacitance for each pin.

SRTC SUPPORT

The MC13892 provides support for processors which have an integrated SRTC for Digital Rights Management (DRM), by providing a VSRTC voltage to bias the SRTC module of the processor, as well as a CLK32KMCU at the VSRTC output level.

When configured for DRM mode (SPI bit DRM = 1), the CLK32MCU driver will be kept enabled through all operational states, to ensure that the SRTC module always has its reference clock. If DRM = 0, the CLK32KMCU driver will not be maintained in the

Off state. Refer to

Table 23

for the operating behavior of the CLK32KMCU output in User Off, Memory Hold, User off Wait, and internal MEMHOLD PCUT modes.

It is also necessary to provide a means for the processor to do an RTC initiated wake-up of the system, if it has been programmed for such capability. This can be accomplished by connecting an open drain NMOS driver to the PWRON pin of the

MC13892, so that it is in effect a parallel path for the power key. The MC13892 will not be able to discern the turn on event from a normal power key initiated turn on, but the processor should have the knowledge, since the RTC initiated turn on is generated locally.

MC13892

50







Figure 10. SRTC block diagram

VSRTC

The VSRTC regulator provides the CLK32KMCU output level. It is also used to bias the Low-power SRTC domain of the SRTC module integrated on certain FSL processors. The VSRTC regulator is enabled as soon as the RTCPORB is detected. The

VSRTC cannot be disabled.

Table 17. VSRTC Specifications

Parameter

General

Operating Input Voltage Range,

V

INMIN

to V

INMAX


MIN to IL

MAX

Bypass Capacitor Value

Active Mode - DC

Condition

Valid Coin Cell range or valid BP

Min

1.8

UVDET

0.0

–

Typ

–

–

–

1.0

Max

3.6

4.65

50

–

Units

V

V



A



F

Output Voltage V

OUT

V

INMIN

IL

MIN

< V

IN

< V

INMAX

< IL < IL

MAX

1.150

1.20

1.25

V

REAL TIME CLOCK

A real Time Clock (RTC) function is provided including time and day counters as well as an alarm function. The utilizes a

32 kHz clock, either the RC oscillator or the 32.768 kHz crystal oscillator as a time base, and is powered by the coin cell backup supply when BP has dropped below operational range. In configurations where the SRTC is used, the RTC can be disabled to conserve current drain by setting the RTCDIS bit to a 1 (defaults on at power up).

TIME AND DAY COUNTERS

The 32 kHz clock is divided down to a 1.0 Hz time tick which drives a 17-bit Time Of Day (TOD) counter. The TOD counter counts the seconds during a 24 hour period from 0 to 86,399, and will then roll over to 0. When the roll over occurs, it increments the 15-bit DAY counter. The DAY counter can count up to 32767 days. The 1.0 Hz time tick can be used to generate a 1HZI interrupt if unmasked.


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MC13892

51



TIME OF DAY ALARM

A Time Of Day Alarm (TODA) function can be used to turn on the application and alert the processor. If the application is already on, the processor will be interrupted. The TODA and DAYA registers are used to set the alarm time. Only a single alarm can be programmed at a time. When the TOD counter is equal to the value in TODA, and the DAY counter is equal to the value in DAYA, the TODAI interrupt will be generated.

At initial power up of the application (application of the coin cell), the state of the TODA and DAYA registers will be all 1's. The interrupt for the alarm (TODAI) is backed up by LICELL and will be valid at power up. If the mask bit for the TOD alarm (TODAM) is high, then the TODAI interrupt is masked and the application will not turn on with the time of day alarm event

(TOD[16:0] = TODA[16:0] and DAY[14:0] = DAYA[14:0]). By default, the TODAM mask bit is set to 1, thus masking the interrupt and turn on event.

TIMER RESET

As long as the supply at BP is valid, the real time clock will be supplied from VCORE. If not, it can be backed up from a coin cell via the LICELL pin. When the backup voltage drops below RTCUVDET, the RTCPORB reset signal is generated and the contents of the RTC will be reset. Additional registers backed up by coin cell will also reset with RTCPORB. To inform the processor that the contents of the RTC are no longer valid due to the reset, a timer reset interrupt function is implemented with the RTCRSTI bit.

RTC TIMER CALIBRATION

A clock calibration system is provided to adjust the 32,768 cycle counter that generates the 1.0 Hz timer for RTC timing registers to comply with digital rights management specifications of ±50 ppm. This calibration system can be disabled, if not needed to reduce the RTC current drain. The general implementation relies on the system processor to measure the 32.768 kHz crystal oscillator against a higher frequency and more accurate system clock such as a TCXO. If the RTC timer needs a correction, a 5-bit 2's complement calibration word can be sent via the SPI to compensate the RTC for inaccuracy in its reference oscillator as defined in

Table 18 .

Table 18. RTC Calibration Settings

Code in RTCCAL[4:0]

01111

00011

00001

00000

11111

11101

10001

10000

Correction in Counts per 32768

-1

-3

-15

-16

+15

+3

+1

0

Relative correction in ppm

+458

+92

+31

0

-31

-92

-458

-488

Note that the 32.768 kHz oscillator is not affected by RTCCAL settings. Calibration is only applied to the RTC time base counter. Therefore, the frequency at the clock outputs CLK32K and CLK32KMCU are not affected.

The RTC system calibration is enabled by programming the RTCCALMODE[1:0] for desired behavior by operational mode.

Table 19. RTC Calibration Enabling

RTCCALMODE

00

01

10

11

Function

RTC Calibration disabled (default)

RTC Calibration enabled in all modes except coin cell only

Reserved for future use. Do not use.

RTC Calibration enabled in all modes

A slight increase in consumption will be seen when the calibration circuitry is activated. To minimize consumption and maximize lifetime when the RTC system is maintained by the coin cell, the RTC Calibration circuitry can be automatically disabled when main battery contact is lost, or if it is so deeply discharged that RTC power draw is switched to the coin cell (configured with RTCCALMODE = 01).

Because of the low RTC consumption, RTC accuracy can be maintained through long periods of the application being shut down, even after the main battery has discharged. However, it is noted that the calibration can only be as good as the RTCCAL

MC13892

52







data that has been provided, so occasional refreshing is recommended to ensure that any drift influencing environmental factors have not skewed the clock beyond desired tolerances.

COIN CELL BATTERY BACKUP

The LICELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged, removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell maintained logic will switch over to the

LICELL for backup power. This switch over occurs for a BP below the UVDET threshold with LICELL greater than BP. A small capacitor should be placed from LICELL to ground under all circumstances.

Upon initial insertion of the coincell, it is not immediately connected to the on chip circuitry. The cell gets connected when the

IC powers on, or after enabling the coincell charger when the IC was already on. During operation, coincells can get damaged and their lifetime reduced when deeply discharged. In order to avoid such, the internal circuitry supplied from LICELL is automatically disconnected for voltages below the coincell disconnect threshold. The cell gets reconnected again under the same conditions as for initial insertion.

The coin cell charger circuit will function as a current-limited voltage source, resulting in the CC/CV taper characteristic typically used for rechargeable Lithium-Ion batteries. The coin cell charger is enabled via the COINCHEN bit. The coin cell voltage is programmable through the VCOIN[2:0] bits. The coin cell charger voltage is programmable in the ON state where the charge current is fixed at ICOINHI.

If COINCHEN=1 when the system goes into Off or User Off state, the coin cell charger will continue to charge to the predefined voltage setting but at a lower maximum current ICOINLO. This compensates for self discharge of the coin cell and ensures that if/when the main cell gets depleted, that the coin cell will be topped off for maximum RTC retention. The coin cell charging will be stopped for the BP below UVDET. The bit COINCHEN itself is only cleared when an RTCPORB occurs.

Table 20. Coin cell Charger Voltage Specifications

VCOIN[2:0]

100

101

110

111

000

001

010

011

Output Voltage

2.50

2.70

2.80

2.90

3.00

3.10

3.20

3.30

Table 21. Coin cell Charger Specifications

Parameter

Voltage Accuracy

Coin Cell Charge Current in On and Watchdog modes ICOINHI

Coin Cell Charge Current in Off and Low-power Off modes (User Off / Memory Hold) ICOINLO

Current Accuracy

LICELL Bypass Capacitor

LICELL Bypass Capacitor as coin cell replacement

LICELL Bypass Capacitor

LICELL Bypass Capacitor as coin cell replacement

Typ

100

4.7

100

4.7

100

60

10

30

Units

mV



A



A

% nF



F nF



F





MC13892

53


POWER CONTROL SYSTEM

POWER CONTROL SYSTEM

INTERFACE

The power control system on the MC13892 interfaces with the processor via different IO signals and the SPI/I2C bus. It also uses on chip signals and detector outputs.

Table 22 gives a listing of the principal elements of this interface.

Name

PWRON1

PWRON2

PWRON3

PWRONxI/M/S

PWRON1DBNC[1:0]

PWRON2DBNC[1:0]

PWRON3DBNC[1:0]

PWRON1RSTEN

PWRON2RSTEN

PWRON3RSTEN

RESTARTEN

SYSRSTI/M

WDI

WDIRESET

WDIRESETI/M

RESET

RESETMCU

PUMS1

PUMS2

STANDBY

STANDBYINV

STANDBYSEC

STANDBYSECINV

STBYDLY[1:0]

BPON

BPONI/M/S

LOBATH

LOBATHI/M/S

LOBATL

LOBATLI/M/S

BPSNS [1:0]

UVDET

LICELL

CLK32KMCU

CLK32K

CLK32KMCUEN

DRM

PCEN

PCI/M

PCT[7:0]

PCCOUNTEN

PCCOUNT[3:0]

Type of Signal

Output pin

Input pin

Input pin

Input pin

SPI bit

Input pin

SPI bit

SPI bits

Threshold

SPI bits

Threshold

SPI bits

Threshold

SPI bits

SPI bits

Threshold

Input pin

Output pin

Output pin

SPI bit

Input pin

Input pin

Input pin

SPI bits

SPI bits

SPI bits

SPI bits

SPI bit

SPI bit

SPI bit

SPI bit

SPI bits

Input pin

SPI bit

SPI bits

Output pin

SPI bit

SPI bit

SPI bits

SPI bits

SPI bit

SPI bits

Table 22. Power Control System Interface Signals

Function

Power on/off 1 button connection



PWRONx pin interrupt /mask / sense bits

Sets time for the PWRON1 pin hardware debounce



Allows for system reset through the PWRON1 pin



Allows for system restart after a PWRON initiated system reset

PWRONx System restart interrupt / mask bits

Watchdog input has to be kept high by the processor to keep the MC13892 active

Allows for system restart through the WDI pin

WDI System restart interrupt / mask bits

Reset Bar output (active low) to the application. Requires an external pull-up

Reset Bar output (active low) to the processor core. Requires an external pull-up

Switchers and regulators power up sequence and defaults selection 1

Switchers and regulators power up sequence and defaults selection 2

Signal from primary processor to put the MC13892 in a Low-power mode

Standby signal polarity setting

Signal from secondary processor to put the MC13892 in a Low-power mode

Secondary standby signal polarity setting

Sets delay before entering standby mode

Threshold validating turn on events

BP turn on threshold interrupt / mask / sense bits

Threshold for a low battery warning

Low battery warning interrupt / mask / sense bits

Threshold for a low battery detect

Low battery detect interrupt / mask / sense bits

Selects for different settings of LOBATL and LOBATH thresholds

Threshold for under-voltage detection, will shut down the device

Connection for Lithium based coin cell

Low frequency system clock output for the processor 32.768 kHz

Low frequency system clock output for application (peripherals) 32.768 kHz

Enables the CLK32KMCU clock output

Keeps VSRTC and CLK32KMCU active in all states for digital rights management, including off mode

Enables power cut support

Power cut detect interrupt / mask bits

Allowed power cut duration

Enables power cut counter

Power cut counter

MC13892

54





Table 22. Power Control System Interface Signals

Name

PCMAXCNT[3:0]

PCUTEXPB

Type of Signal

SPI bits

SPI bit

Function

Maximum number of allowed power cuts

Indicates a power cut timer counter expired


POWER CONTROL SYSTEM





MC13892

55


OPERATING MODES

OPERATING MODES

POWER CONTROL STATE MACHINE

Figure 11

shows the flow of the power control state machine. This diagram serves as the basis for the description in the remainder of this chapter.

MC13892

56

Figure 11. Power Control State Machine Flow Diagram






OPERATING MODES

POWER CONTROL MODES DESCRIPTION

Following are text descriptions of the power states of the system, which give additional details of the state machine, and

complement Figure 11

. Note that the SPI control is only possible in the Watchdog, On, and User Off Wait states, and that the interrupt line INT is kept low in all states except for Watchdog and On.

Off

If the supply at BP is above the UVDET threshold, only the IC core circuitry at VCOREDIG and the RTC module are powered, all other supplies are inactive. To exit the Off mode, a valid turn on event is required. No specific timer is running in this mode.

If the supply at BP is below the UVDET threshold no turn on events are accepted. If a valid coin cell is present, the core gets powered from LICELL. The only active circuitry is the RTC module, with BP greater than UVDET detection, and the SRTC support circuitry, if so configured.

Cold Start

Entered upon a Turn On event from Off, Warm Boot, successful PCUT, or Silent System Restart. The switchers and regulators are powered up sequentially to limit the inrush current. See the Power Up section for sequencing and default level details. The reset signals RESETB and RESETBMCU are kept low. The Reset timer starts running when entering a Cold Start. When expired, the Cold Start state is exited for the Watchdog state, and both RESETB and RESETBMCU become high (open drain output with external pull ups). The input control pins WDI, and STANDBYx are ignored.

Watchdog

The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The Watchdog timer starts running when entering the Watchdog state. When expired, the system transitions to the On state, where WDI will be checked and monitored. The input control pins WDI and STANDBYx are ignored while in the Watchdog state.

On

The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The WDI pin must be high to stay in this mode. The WDI IO supply voltage is referenced to SPIVCC (Normally connected to SW4). SPIVCC must therefore remain enabled to allow for proper WDI detection. If WDI goes low, the system will transition to the Off state or Cold Start (depending on the configuration. Refer to the section on Silent System Restart with WDI Event for details).

User Off Wait

The system is fully powered and under SPI control. The WDI pin no longer has control over the part. The Wait mode is entered by a processor request for User Off by setting the USEROFFSPI bit high. This is normally initiated by the end user via the power key. Upon receiving the corresponding interrupt, the system will determine if the product has been configured for User Off or

Memory Hold states (both of which first require passing through User Off Wait) or just transition to Off.

The Wait timer starts running when entering User Off Wait mode. This leaves the processor time to suspend or terminate its tasks. When expired, the Wait mode is exited for User Off mode or Memory Hold mode, depending on warm starts being enabled or not via the WARMEN bit. The USEROFFSPI bit is being reset at this point by RESETB going low.

Memory Hold and User Off (Low-power Off states)

As noted in the User Off Wait description, the system is directed into Low-power Off states based on a SPI command in response to an intentional turn off by the end user. The only exit then will be a turn on event. To an end user, the Memory Hold and User Off states look like the product has been shut down completely. However, a faster startup is facilitated by maintaining external memory in self-refresh mode (Memory Hold and User Off mode) as well as powering portions of the processor core for state retention (User Off only). The switcher mode control bits allow selective powering of the buck regulators for optimizing the supply behavior in the Low-power Off modes. Linear regulators and most functional blocks are disabled (the RTC module, and

Turn On event detection are maintained).

Memory Hold

RESETB and RESETBMCU are low, and both CLK32K and CLK32KMCU are disabled. If DRM is set, the CLK32KMCU is kept active. To ensure that SW1, SW2, and SW3 shut off in Memory Hold, appropriate mode settings should be used such as

SW1MHMODE = SW2MHMODE = SW3MHMODE = 0 (refer to the mode control description later in this chapter). Since SW4 should be powered in PFM mode, SW4MHMODE could be set to 1.





MC13892

57


OPERATING MODES

Any peripheral loading on SW4 should be isolated from the SW4 output node by the PWGT2 switch, which opens in both Lowpower off modes due to the RESETB transition. In this way, leakage is minimized from the power domain maintaining the memory subsystem.

Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and an the MEMHLDI interrupt bit is set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since software does not have to be loaded and expanded from flash. The startup out of Memory Hold is also referred to as Warm Boot.

No specific timer is running in this mode.

Buck regulators that are configured to stay on in MEMHOLD mode by their SWxMHMODE settings will not be turned off when coming out of MEMHOLD and entering a Warm Boot. The switchers will be reconfigured for their default settings as selected by the PUMS pin in the normal time slot that would affect them.

User Off

RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled. CLK32KMCU

(connected to the processor's CKIL input) is maintained in this mode if the CLK32KMCUEN and USEROFFCLK bits are both set, or if DRM is set.

The memory domain is held up by setting SW4UOMODE = 1. Similarly, the SW1, and/or SW2, and/or SW3 supply domains can be configured for SWxUOMODE = 1 to keep them powered through the User Off event. If one of the switchers can be shut down on in User Off, its mode bits would typically be set to 0.

Any peripheral loading on SW1 and/or SW2 should be isolated from the output node(s) by the PWGT1 switch, which opens in both Low-power Off modes due to the RESETB transition. In this way, leakage is minimized from the power domain maintaining the processor core.

Since power is maintained for the core (which is put into its lowest power state) and since MCU RESETBMCU does not trip, the processor's state may be quickly recovered when exiting USEROFF upon a turn on event. The CLK32KMCU clock can be used for very low frequency / low-power idling of the core(s), minimizing battery drain while allowing a rapid recovery from where the system left off before the USEROFF command.

Upon a turn on event, Warm Start state is entered, and the default power up values are loaded. A Warm Start out of User Off will result in an almost instantaneous startup of the system, since the internal states of the processor were preserved along with external memory. No specific timer is running in this mode.

Warm Start

Entered upon a Turn On event from User Off. The switchers and regulators are powered up sequentially to limit the inrush current; see the Power Up section for sequencing and default level details. If SW1, SW2, SW3, and/or SW4 were configured to stay on in User Off mode, they will not be turned off when coming out of User Off and entering a Warm Start. The buck regulators will be reconfigured for their default settings as selected by the PUMS pin in the respective time slot defined in the sequencer selection.

RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if enabled via the SPI. The reset timer starts running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is generated, and RESETB will go high.

Internal MemHold Power Cut

Refer to the next section for details about Power Cuts and the associated state machine response.

POWER CUT DESCRIPTION

When the supply at BP drops below the UVDET threshold due to battery bounce or battery removal, the Internal MemHold

Power Cut mode is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the RTC as well as the on chip memory registers and some other power control related bits. All other supplies will be disabled.

The maximum duration of a power cut is determined by the PCUT timer PCT[7:0] preset via SPI. When a PCUT occurs, the

PCUT timer will internally be decremented till it expires, meaning counted down to zero. The contents of PCT[7:0] does not reflect the actual count down value but will keep the programmed value and therefore does not have to be reprogrammed after each power cut.

If power is not reestablished above BPON before the PCUT timer expires, the state machine transitions to the Off mode at expiration of the counter, and clears the PCUTEXB bit by setting it to 0. This transition is referred to as an “unsuccessful” PCUT.

Upon re-application of power before expiration (an “successful PCUT”, defined as BP first rising above the UVDET threshold and then above the BPON threshold before the PCUT timer expires), a Cold Start is engaged.

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In order to distinguish a non-PCUT initiated Cold Start from a Cold Start after a PCUT, the PCI interrupt should be checked by software. The PCI interrupt is cleared by software or when cycling through the Off state.

Because the PCUT system quickly disables all of the power tree, the battery voltage may recover to a level with the appearance of a valid supply once the battery is unloaded. However, upon a restart of the IC and power sequencer, the surge of current through the battery and trace impedances can once again cause the BP node to drop below UVDET. This chain of cyclic power down / power up sequences is referred to as “ambulance mode”, and the power control system includes strategies to minimize the chance of a product falling into and getting stuck in ambulance mode.

First, the successful recovery out of a PCUT requires the BP node to rise above BPON, providing hysteretic margin from the

UVDET threshold. Secondly, the number of times the PCUT mode is entered is counted with the counter PCCOUNT[3:0], and the allowed count is limited to PCMAXCNT[3:0] set through the SPI. When the contents of both become equal, then the next

PCUT will not be supported and the system will go to Off mode.

After a successful power up after a PCUT (i.e., valid power is reestablished, the system comes out of reset, and the processor reassumes control), software should clear the PCCOUNT[3:0] counter. Counting of PCUT events is enabled via the

PCCOUNTEN bit. This mode is only supported if the power cut mode feature is enabled by setting the PCEN bit. When not enabled, in case of a power failure, the state machine will transition to the Off state. SPI control is not possible during a PCUT event and the interrupt line is kept low. SPI configuration for PCUT support should also include setting the PCUTEXPB=1 (see the Silent Restart from PCUT Event section later in this chapter).

Internal MemHold Power Cut

As described above, a momentary power interruption will put the system into the Internal MemHold Power Cut state if PCUTs are enabled. The backup coin cell will now supply the MC13892 core along with the 32 kHz crystal oscillator, the RTC system and coin cell backed up registers. All regulators and switchers will be shut down to preserve the coin cell and RTC as long as possible.

Both RESETB and RESETBMCU are tripped, bringing the entire system down along with the supplies and external clock drivers, so the only recovery out of a Power Cut state is to reestablish power and initiate a Cold Start.

If the PCT timer expires before power is reestablished, the system transitions to the Off state and awaits a sufficient supply recovery.

SILENT RESTART FROM PCUT EVENT

If a short duration power cut event occurs (such as from a battery bounce, for example), it may be desirable to perform a silent restart, so the system is re-initialized without alerting the user. This can be configured by setting the PCUTEXPB bit to a “1” at booting or after a Cold Start. This bit resets on RTCPORB, therefore any subsequent Cold Start can first check the status of

PCUTEXPB and the PCI bit. The PCUTEXPB is cleared to “0” when transitioning from PCUT to Off. If there was a PCUT interrupt and PCUTEXPB is still a “1”, then the state machine has not transitioned through Off, which confirms that the PCT timer has not expired during the PCUT event (i.e., a successful power cut). In case of a successful power cut, a silent restart may be appropriate.

If PCUTEXPB is found to be a “0” after the Cold Start where PCI is found to be a “1”, then it is inferred that the PCT timer has expired before power was reestablished, flagging an unsuccessful power cut or first power up, so the startup user greeting may be desirable for playback.

SILENT SYSTEM RESTART WITH WDI EVENT

A mechanism is provided for recovery if the system software somehow gets into an abnormal state which requires a system reset, but it is desired to make the reset a silent event so as to happen without end user awareness. The default response to WDI going low is for the state machine to transition to the Off state (when WDIRESET = 0). However, if WDIRESET = 1, the state machine will go to Cold Start without passing through Off mode

A WDIRESET event will generate a maskable WDIRESETI interrupt and also increment the PCCOUNT counter. This function is unrelated to PCUTs, but it shares the PCUT counter so that the number of silent system restarts can be limited by the programmable PCMAXCNT counter.

When PCUT support is used, the software should set the PCUTEXPB bit to “1”. Since this bit resets with RTCPORB, it will not be reset to “0” if a WDI falls and the state machine goes straight to the Cold Start state. Therefore, upon a restart, the software can detect a silent system restart, if there is a WDIRESETI interrupt and PCUTEXPB = 1. The application may then determine that an inconspicuous restart without showing may be more appropriate than launching into the welcoming routine.

A PCUT event does not trip the WDIRESETI bit.


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GLOBAL SYSTEM RESTART

A global system reset can be enabled through the GLBRSTENB SPI bit. The global reset on the MC13892A/C versions is active low so it is enabled when the GLBRSTENB = 0. In the MC13892B/D versions global reset is active high and it is enabled when the GLBRSTENB = 1. When global reset is enabled and the PWRON3 button is held for 12 seconds, the system will reset and the following actions will take place:

• Power down

• Disable the charger

• Reset all the registers including the RTCPORB registers

• Power back up after the difference between the 12 sec timer, and when the user releases the button as the power off time

(for example, if the power button was held for 12.1 s, then the time that the IC would be off would be only 100 mS)

If PWRON3 is held low for less than 12 seconds, it will act as a normal PWRON pin. This feature is enabled by default in the

MC13892A/C versions, and disabled by default in the MC13892B/D versions.

CLK32KMCU CLOCK DRIVER CONTROL THROUGH STATES

As described previously, the clocking behavior is influenced by the state machine is in and the setting of the clocking related

SPI bits. A summary is given in

Table 23

for the clock output CLK32KMCU.

Table 23. CLK32MCU Control Logic Table

Mode

Off, Memory Hold, Internal MEMHOLD PCUT

On, Cold Start, Warm Start, Watchdog, User Off Wait

User Off

DRM

1

0

0

0

0

1

0

1

CLK32KMCUEN

X

1

1

X

0

X

X

X

USEROFFCLK

X

1

X

0

X

X

X

X

Clock Output CLK32KMCU

Disabled

Enabled

Disabled

Enabled

Enabled

Disabled

Enabled

TURN ON EVENTS

When in Off mode, the MC13892 can be powered on via a Turn On event. The Turn On events are listed in

Table 24

. To indicate to the processor what event caused the system to power on, an interrupt bit is associated with each of the Turn On events. Masking the interrupts related to the turn on events will not prevent the part to turn on, except for the time of day alarm.

Power Button Press

PWRON1, PWRON2, or PWRON3 pulled low with corresponding interrupts and sense bits PWRON1I, PWRON2I, or

PWRON3I, and PWRON1S, PWRON2S, or PWRON3S. A power on/off button is connected here. The PWRONx can be hardware debounced through a programmable debouncer PWRONxDBNC[1:0] to avoid the application to power up upon a very short key press. In addition, a software debounce can be applied. BP should be above UVDET. The PWRONxI interrupt is generated for both the falling and the rising edge of the PWRONx pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges. The falling edge debounce timing can be extended with PWRONxDBNC[1:0] as defined in the following table. The PWRONxI interrupt is cleared by software or when cycling through the Off mode.

Table 24. PWRONx Hardware Debounce Bit Settings

Bits

PWRONxDBNC[1:0]

State Turn On Debounce (ms)

00

01

10

11

0

31.25

125

750

Falling Edge INT Debounce (ms)

31.25

31.25

125

750

Notes

48.

The sense bit PWRONxS is not debounced and follows the state of the PWRONx pin

Rising Edge INT Debounce (ms)

31.25

31.25

31.25

31.25

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Charger Attach

CHRGRAW is pulled high with corresponding interrupt and sense bits CHGDETI and CHGDETS. This is equivalent to plugging in a charger. BP should be above BPON. The charger turn on event is dependent on the charge mode selected. For

details on the charger detection and turn on, see Battery Interface and Control

.

Battery Attach

BP crossing the BPON threshold which corresponds to attaching a charged battery to the product. A corresponding BPONI interrupt is generated, which can be cleared by software or when cycling through the Off mode. Note that BPONI is also generated after a successful power cut and potentially when applying a charger.

USB Attach

VBUS pulled high with corresponding interrupt and sense bits BVALIDI and BVALIDS. This is equivalent to plugging in a USB cable. BP should be above BPON and the battery voltage above BATTON. For details on the USB detection, see

Connectivity

.

RTC Alarm

TOD and DAY become equal to the alarm setting programmed. This allows powering up a product at a preset time. BP should be above BPON. For details and related interrupts, see

Clock Generation and Real Time Clock .

System Restart

System restart may occur after a system reset. This is an optional function, see also the following Turn Off events section. BP should be above BPON.

TURN OFF EVENTS

Power Button Press

User shut down of a product is typically done by pressing the power button connected to the PWRONx pin. This will generate an interrupt (PWRONxI), but will not directly power off the part. The product is powered off by the processor's response to this interrupt, which will be to pull WDI low. Pressing the power button is therefore under normal circumstances not considered as a turn off event for the state machine.

Note that software can configure a user initiated power down via a power button press for transition to a Low-power off mode

(Memory Hold or User Off) for a quicker restart than the default transition into the Off state.

Power Button System Reset

A secondary application of the PWRON pin is the option to generate a system reset. This is recognized as a Turn Off event.

By default, the system reset function is disabled but can be enabled by setting the PWRONxRSTEN bits. When enabled, a 4 second long press on the power button will cause the device to go to the Off mode and as a result the entire application will power down. An SYSRSTI interrupt is generated upon the next power up. Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.

Thermal Protection

If the die gets overheated, the thermal protection will power off the part to avoid damage. A Turn On event will not be accepted while the thermal protection is still being tripped. The part will remain in Off mode until cooling sufficiently to accept a Turn On event. There are no specific interrupts related to this other than the warning interrupts.

Under-Voltage Detection

When the voltage at BP drops below the under-voltage detection threshold UVDET, the state machine will transition to Off mode if PCUT is not enabled, or if the PCT timer expires when PCUT is enabled.

TIMERS

The different timers as used by the state machine are in

Table 25

. This listing does not include RTC timers for timekeeping.

A synchronization error of up to one clock period may occur with respect to the occurrence of an asynchronous event. The duration listed below is therefore the effective minimum time period.


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OPERATING MODES

Table 25. Timer Main Characteristics

Timer

Under-voltage Timer

Reset Timer

Watchdog Timer

Power Cut Timer

Duration

4.0 ms

40 ms

128 ms

Programmable 0 to 8 seconds in 31.25 ms steps

TIMING DIAGRAMS

A Turn On event timing diagram example shows in

Figure 12 .

Figure 12. Power Up Timing Diagram

POWER UP

At power up, switchers and regulators are sequentially enabled in time slots of 2.0 ms steps to limit the inrush current after an initial delay of 8.0 ms, in which the core circuitry gets enabled. To ensure a proper power up sequence, the outputs of the switchers are discharged at the beginning of a Cold Start. For that reason, an 8.0 ms delay allows the outputs of the linear regulators to be fully discharged as well through the built-in discharge path. Time slots which include multiple regulator startups will be sub-sequenced for additional inrush balancing. The peak inrush current per event is limited. Any under-voltage detection at BP is masked while the power up sequencer is running.

The Power Up mode Select pins (PUMS1 and 2) are used to configure the startup characteristics of the regulators. Supply enabling and output level options are selected by hardwiring the PUMSx pins for the desired configuration. The state of the

PUMSx pins can be read out via the sense bits PUMSSxx[1:0]. Tying the PUMSx pins to ground corresponds to 00, open to 01,

VCOREDIG to 10, and VCORE to 11.

The recommended power up strategy for end products is to bring up as little of the system as possible at booting, essentially sequestering just the bare essentials, to allow processor startup and software to run. With such a strategy, the startup transients are controlled at lower levels, and the rest of the system power tree can be brought up by software. This allows optimization of supply ordering where specific sequences may be required, as well as supply default values. Software code can load up all of the required programmable options to avoid sneak paths, under/over-voltage issues, startup surges, etc., without any change in hardware. For this reason, the Power Gate drivers are limited to activation by software rather than the sequencer, allowing the core(s) to startup before any peripheral loading is introduced.

The power up defaults

Table 26

shows the initial setup for the voltage level of the switchers and regulators, and whether they get enabled.

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Table 26. Power Up Defaults Table i.MX

PUMS1

37/51

GND

37/51

Open

37/51

VCOREDIG

37/51

VCORE

35

GND

27/31

Open

PUMS2

SW1

(49)

SW2

(49)

SW3

(49)

SW4

(49)

SWBST

VUSB

VUSB2

VPLL

VDIG

VIOHI

VGEN2

VSD

Open

0.775

1.025

1.200

1.800

Off

3.300

(50)

2.600

1.800

1.250

2.775

3.150

Off

Open

1.050

1.225

1.200

1.800

Off

3.300

(50)

2.600

1.800

1.250

2.775

Off

Off

Open

1.050

1.225

1.200

1.800

Off

3.300

(50)

2.600

1.800

1.250

2.775

3.150

Off

Open

0.775

1.025

1.200

1.800

Off

3.300

(50)

2.600

1.800

1.250

2.775

Off

Off

GND

1.200

1.350

1.800

1.800

5.000

3.300

(52)

2.600

1.500

1.250

2.775

3.150

3.150

GND

1.200

1.450

1.800

1.800

5.000

3.300

(52)

2.600

1.500

1.250

2.775

3.150

3.150

Notes

49.

The switchers SWx are activated in PWM pulse skipping mode, but allowed when enabled by the startup sequencer.

50.

USB supply VUSB, is only enabled if 5.0 V is present on UVBUS.

51.

The following supplies are not included in the matrix since they are not intended for activation by the startup sequencer: VCAM, VGEN1,

VGEN3, VVIDEO, and VAUDIO

52.

SWBST = 5.0 V powers up and does VUSB regardless of 5.0 V present on UVBUS. By default VUSB will be supplied by SWBST.

The power up sequence is shown in

Table 27

. VCOREDIG, VSRTC, and VCORE are brought up in the pre-sequencer startup.

Once VCOREDIG is activated (i.e., at the first-time power application), it will be continuously powered as long as a valid coin cell is present.

Table 27. Power Up Sequence

Tap x 2ms

6

7

4

5

8

9

2

3

0

1

PUMS2 = Open (i.MX37, i.MX51)

SW2

SW4

VIOHI

VGEN2

SW1

SW3

VPLL

VDIG

-

VUSB

(55)

, VUSB2

PUMS2 = GND (i.MX35, i.MX27)

SW2

VGEN2

SW4

VIOHI, VSD

SWBST, VUSB

(56)

SW1

VPLL

SW3

VDIG

VUSB2

Notes

53.

Time slots may be included for blocks which are defined by the PUMS pin as disabled to allow for potential activation.

54.

The following supplies are not included in the matrix since they are not intended for activation by the startup sequencer: VCAM,

VGEN1, VGEN3, VVIDEO, and VAUDIO. SWBST is not included on the PUMS2 = Open column.

55.

USB supply VUSB, is only enabled if 5.0 V is present on UVBUS.

56.

SWBST = 5.0 V powers up and so does VUSB regardless of 5.0 V present on UVBUS. By default VUSB will be supplied by SWBST.





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OPERATING MODES

POWER MONITORING

The voltage at BPSNS and BP is monitored by detectors as summarized in Table 28 .

Table 28. BP Detection Thresholds

Falling Edge

Threshold in V

Bit setting Rising Edge

BPSNS1

1

1

0

0

BPSNS0

0

1

0

1

UVDET

2.55

2.55

2.55

2.55

LOBATL

2.8

2.9

3.0

3.1

LOBATH

3.0

3.1

3.3

3.4

BPON

3.2

3.2

3.2

3.2

Notes

57.

Default setting for BPSNS[1:0] is 00. The above specified thresholds are ±50 mV accurate for the indicated edge. A hysteresis is applied to the detectors on the order of 100 mV. BPON is monitoring BP. UVDET, LOBATL and LOBATH are monitoring BPSNS and thresholds are correlated.

The UVDET and BPON thresholds are related to the power on/off events as described earlier in this chapter. The LOBATH threshold is used as a weak battery warning. An interrupt LOBATHI is generated when crossing the threshold (dual edge). The

LOBATL threshold is used as a low battery detect. An interrupt LOBATLI is generated when dropping below the threshold. The sense bits are coded in line with previous generation parts.

Table 29. Power Monitoring Summary

BPSNS

< LOBATL

LOBATL-LOBATH

LOBATH-BPON

>BPON

BPONS

0

1

0

0

LOBATHS

1

1

0

0

LOBATLS

0

0

1

0

POWER SAVING

SYSTEM STANDBY

A product may be designed to go into DSM after periods of inactivity, such as if a music player completes a play list and no further activity is detected, or if a gaming interface sits idle for an extended period. Two Standby pins are provided for board level control of timing in and out of such deep sleep modes.

When a product is in DSM it may be able to reduce the overall platform current by lowering the switcher output voltage, disabling some regulators, or forcing some GPO low. This can be obtained by SPI configuration of the Standby response of the circuits along with control of the Standby pins.

To ensure that shared resources are properly powered when required, the system will only be allowed into Standby when both the STANDBY and the STANDBYSEC are activated. The states of the Standby pins only have influence in On mode. A command to transition to one of the Low-power Off states (User Off or Memory Hold, initiated with USEROFFSPI = 1) has priority over

Standby.

Note that the Standby pins are programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into account the programmed input polarities associated with each pin.

Table 30. Standby Pin and Polarity Control

STANDBY (Pin)

1 x

0 x

0

STANDBYINV (SPI bit)

1 x

0 x

1

STANDBYSEC (Pin)

x

1 x

0

0

STANDBYSECINV (SPI bit)

x

1 x

0

1

STANDBY Control

(58)

0

0

0

0

1

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Table 30. Standby Pin and Polarity Control

STANDBY (Pin)

0

1

1

STANDBYINV (SPI bit)

1

0

0

STANDBYSEC (Pin)

1

0

1

STANDBYSECINV (SPI bit)

0

1

0

STANDBY Control

Notes

58.

STANDBY = 0: System is not in Standby; STANDBY = 1: System is in Standby and Standby programmability is activated.

1

1

1

(58)

When requesting standby, a programmable delay (STBYDLY) of 0 to 3 clock cycles of the 32 kHz clock is applied before actually going into standby (i.e. before turning off some supplies). No delay is applied when coming out of standby.

Table 31. Delay of STANDBY- Initiated Response

STBYDLY[1:0]

00

01

10

11

Function (1)

No Delay

One 32 K period (default)

Two 32 K periods

Three 32 K periods

REGULATOR MODE CONTROL

The regulators with embedded pass devices (VDIG, VPLL, VIOHI, VUSB, VUSB2, and VAUDIO) have an adaptive biasing scheme, thus, there are no distinct operating modes such as a Normal mode and a Low-power mode. Therefore, no specific control is required to put these regulators in a Low-power mode.

The regulators with external pass devices (VSD, VVIDEO, VGEN1, and VGEN2) can also operate in a Normal and Low-power mode. However, since a load current detection cannot be performed for these regulators, the transition between both modes is not automatic and is controlled by setting the corresponding mode bits for the operational behavior desired.

The regulators VGEN3 and VCAM can be configured for using the internal pass device or external pass device as explained

in Power Control System

. For both configurations, the transition between Normal and Low-power modes is controlled by setting the VxMODE bit for the specific regulator. Therefore, depending on the configuration selected, the automatic Low-power mode is available.

The regulators can be disabled and the general purpose outputs can be forced low when going into Standby as described previously. Each regulator and GPO has an associated SPI bit for this. When the bit is not set, STANDBY is of no influence. The actual operating mode of the regulators as a function of STANDBY is not reflected through the SPI. In other words, the SPI will read back what is programmed, not the actual state.

Table 32. LDO Regulator Control (External Pass Device LDOs)

VxEN

0

1

1

1

1

1

VxMODE

X

X

0

0

1

1

VxSTBY

X

1

1

0

0

1

Notes

59.

This table is valid for regulators with an external pass device

60.

STANDBY refers to a Standby event as described earlier

STANDBY

X

0

1

X

X

1

For regulators with internal pass devices and general outputs, the previous table can be simplified.

Regulator Vx

Off

On

Low-power

On

Off

Low-power


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OPERATING MODES

Table 33. LDO Regulator Control (Internal Pass Device LDOs)

VxEN

0

1

1

1

VxSTBY

1

1

X

0

Notes

61.

This table is valid for regulators with an internal pass device

62.

STANDBY refers to a Standby event as described earlier

0

1

X

X

Off

On

On

Off

BUCK REGULATORS

Operational modes of the Buck regulators can be controlled by direct SPI programming, altered by the state of the STANDBY pins, by direct state machine influence, or by load current magnitude when so configured. Available modes include PWM with

No Pulse Skipping (PWM), PWM with Pulse Skipping (PWMPS), Pulse Frequency Mode (PFM), and Off. The transition between the two modes PWMPS and PFM can occur automatically, based on the load current. Therefore, no specific control is required to put the switchers in a Low-power mode. When the buck regulators are not configured in the Auto mode, power savings may be achieved by disabling switchers when not needed, or running them in PFM mode if loading conditions are light enough.

SW1, SW2, SW3, and SW4 can be configured for mode switching with STANDBY or autonomously based on load current with adaptive mode control (Auto). Additionally, provisions are made for maintaining PFM operation in USEROFF and MEMHOLD modes to support state retention for faster startup from the Low-power Off modes for Warm Start or Warm Boot.

Table 34 summarizes the Buck regulator programmability for Normal and Standby modes.

Table 34. Switcher Mode Control for Normal and Standby Operation

SWxMODE[3:0]

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

Normal mode

(63)

Off

PWM

PWMPS

PFM

Auto

PWM

PWM

NA

Auto

PWM

PWMPS

PWMPS

Auto

PWM

PWMPS

PFM

Standby Mode

(63)

Off

Off

Off

Off

Off

PWM

Auto

NA

Auto

PWMPS

PWMPS

Auto

PFM

PFM

PFM

PFM

Notes

63.

STANDBY defined as logical AND of STANDBY and STANDBYSEC pin

In addition to controlling the operating mode in Standby, the voltage setting can be changed. The transition in voltage is handled in a controlled slope manner, see

Supplies

, for details. Each switcher has an associated set of SPI bits for Standby mode set points. By default the Standby settings are identical to the non-Standby settings, which are initially defined by PUMS programming.

The actual operating mode of the switchers as a function of STANDBY pins is not reflected through the SPI. The SPI will read back what is programmed in SWxMODE[3:0], not the actual state that may be altered as described previously.

Table 35 and Table 36 show the switcher mode control in the Low-power Off states. Note that a Low-power Off activated SWx

should use the Standby set point as programmed by SWxSTBY[4:0]. The activated switcher(s) will maintain settings for mode and voltage until the next startup event. When the respective time slot of the startup sequencer is reached for a given switcher, its mode and voltage settings will be updated the same as if starting out of the Off state (except that switchers active through a

Low-power Off mode will not be off when the startup sequencer is started).

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Table 35. Switcher Control In Memory Hold

SWxMHMODE

0

1

Memory Hold Operational Mode

Off

PFM

(64)

Notes

64.

For Memory Hold mode, an activated SWx should use the Standby set point as programmed by SWxSTBY[4:0].

Table 36. Switcher Control In User Off

SWxUOMODE

0

1

User Off Operational Mode

Off

PFM

(65)

Notes

65.

For User Off mode, an activated SWx should use the Standby set point as programmed by

SWxSTBY[4:0].

POWER GATING SYSTEM

The Low-power Off states are provided to allow faster system booting from two pseudo Off conditions: Memory Hold, which keeps the external memory powered for self refresh, and User Off, which keeps the processor powered up for state retention.

For reduced current drain in Low-power Off states, parts of the system can benefit from power gating to isolate the minimum essentials for such operational modes. It is also necessary to ensure that the power budget on backed up domains are within the capabilities of switchers in PFM mode. An additional benefit of power gating peripheral loads during system startup is to enable the processor core to complete booting, and begin running software before additional supplies or peripheral devices are powered.

This allows system software to bring up the additional supplies and close power gating switches in the most optimum order, to avoid problems with supply sequencing or transient current surges. The power gating switch drivers and integrated control are included for optimizing the system power tree.

The power gate drivers could be used for other general power gating as well. The text herein assumes the standard application of PWGT1 for core supply power gating and PWGT2 for Memory Hold power gating.

USER OFF POWER GATING

User Off configuration maintains PFM mode switchers on both the processor and external memory power domains.

PWGTDRV1 is provided for power gating peripheral loads sharing the processor core supply domain(s) SW1, and/or SW2, and/ or SW3. In addition, PWGTDRV2 is provided support to power gate peripheral loads on the SW4 supply domain.

In the typical application, SW1, SW2, and SW3 will all be kept active for the processor modules in state retention, and SW4 retained for the external memory in self refresh mode. SW1, SW2, and SW3 power gating FET drive would typically be connected to PWGTDRV1 (for parallel NMOS switches); SW4 power gating FET drive would typically be connected to PWGTDRV2. When

Low-power Off mode is activated, the power gate drive circuitry will be disabled, turning off the NMOS power gate switches to isolate the maintained supply domains from any peripheral loading.

The power gate switch driver consist of a fully integrated charge pump (~5.0 V) which provides a low-power output to drive the gates of external NMOS switches placed between power sources and peripheral loading. The processor core(s) would typically be connected directly to the SW1 output node so that it can be maintained by SW1, while any circuitry that is not essential for booting or User Off operation is decoupled via the power gate switch. If multiple power domains are to be controlled together, power gating NMOS switches can share the PWGT1 gate drive. However, extra gate capacitance may require additional time for the charge pump gate drive voltage to reach its full value for minimum switch RDS_on.





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OPERATING MODES

Figure 13. Power Gating Diagram

MEMORY HOLD POWER GATING

As with the User Off power gating strategy described previously, Memory Hold power gating is intended to allow isolation of the SW4 power domain, to selected circuitry in Low-power modes while cutting off the switcher domain from other peripheral loads. The only difference is that processor supplies SW1, and/or SW2, and/or SW3, are shut down in Memory Hold, so just the external memory is maintained in self refresh mode.

An external NMOS is to be placed between the direct-connected memory supply and any peripheral loading. The PWGTDRV2 pin controls the gate of the external NMOS and is normally pulled up to a charge pumped voltage (~5.0 V). During Memory Hold or User Off, PWGTDRV2 will go low to turn off the NMOS switch and isolate memory on the SW4 power domain.

Figure 14. Memory Hold Circuit

EXITING FROM LOW-POWER OFF MODES

When a Turn On event occurs, any switchers that are active through Low-power Off modes will stay in PFM mode at their

Standby voltage set points until the applicable time slot of the startup sequencer. At that point, the respective switcher is updated for the PUMSx defined default state for mode and voltage. Subsequent closing of the power gate switches will be coordinated by software to complete restoration of the full system power tree.

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



OPERATING MODES

POWER GATING SPECIFICATIONS AND CONTROL

Table 37. Power Gating Characteristics

Parameter

Output Voltage V

OUT

Turn-on Time

(66)

,

(67)

Turn Off Time

Average Bias Current

PWGTx Input Voltage

DC Load Current

Load Capacitance

(66)

Condition

Output High

Output Low

Enable to V

OUT

= V

OUTMIN

-250 mV

Disable to V

OUT

< 1.0 V t > 500

 s after Enable

NMOS drain voltage

At PWGTDRVx output

Used as a condition for the other parameters

Min

–

0.6

–

0.5

5.0

–

–

–

Typ

5.40

–

50

–

1.0

–

–

–

Max

5.70

100

100

1.0

5.0

2.0

100

1.0

Units

V mV

 s

 s



A

V nA nF

Notes

66.

Larger capacitive loading values will lead to longer turn on times exceeding the given limits; smaller values will lead to larger ripple at the output.

67.

Input supply is assumed in the range of 3.0 < BP < 4.65 V; lower BP values may extend turn on time, and functionality not supported for BP less than ~2.7 V.

A power gate driver pulled low may be thought of as power gating being active since this is the condition where a power source is isolated (or power gated) from its loading on the other side of the switch. The power gate drive outputs are SPI controlled in the active modes as shown in

Table 38

.

Table 38. Power Gate Drive State Control

Mode

Off

Cold Start

Warm Start

Watchdog, On, User Off Wait

User Off, Memory Hold, Internal Memory Hold Power Cut

PWGTDRV1

L ow

Low

Low

SPI Controlled

Low

PWGTDRV2

Low

Low

Low

SPI Controlled

Low

When SPI controlled (Watchdog, On, and User Off Wait states), the PWGTDRVx power gate drive pin states are determined by SPI enable bits PWGTxSPIEN, according to

Table 39

.

Table 39. Power Gating Logic Table

PWGTxSPIEN

1

0

PWGTDRVx

Low

High

Notes

68.

Applicable for Watchdog, On and User Off Wait modes only. If PWGT1SPIEN

AND PWGT2SPIEN both = 1 then the charge pump is disabled.

GENERAL PURPOSE OUTPUTS

GPO drivers included can provide useful system level signaling with SPI enabling and programmable Standby control. Key use cases for GPO outputs include battery pack thermistor biasing and enabling of peripheral devices, such as light sensor(s), camera flash, or even supplemental regulators.

SPI enabling can be used for coordinating GPOs with ADC conversions for consumption efficiency and desired settling characteristics.

Four general purpose outputs are provided, summarized in

Table 40 and Table 41 (active high polarities assumed).


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OPERATING MODES

Table 40. GPO Control Bits

SPI Bit

GPOxEN

GPOxSTBY x = 1, 2, 3, or 4

GPO Control

GPOx enable

GPOx controlled by STANDBY

Table 41. GPO Control Scheme

GPOxEN

0

1

1

1

GPOxSTBY

1

1

X

0

0

1

X

X

Low

High

High

Low

Notes

69.

GPO1 is automatically made active high when a charger is

detected, see Battery Interface and Control for more information.

The GPO1 output is intended to be used for battery thermistor biasing. For accurate thermistor reading by the ADC, the output

resistance of the GPO1 driver is of importance; see ADC Subsystem

.

Table 42. GPO1 Driver Output Characteristics

Parameter

GPO1 Output Impedance

Condition

Output VCORE Impedance to VCORE

Min

200

Typ

–

Max

500

Units

Ohm

Finally, a muxing option is included to allow GPO4 to be configured for a muxed connection into Channel 7 of the GP ADC.

As an application example, for a dual light sensor application, Channel 7 can be toggled between the ADIN7 (ADINSEL7 = 00) and GPO4 (ADINSEL7 = 11) for convenient connectivity and monitoring of two sensors. The GPO4 pin is configured for ADC input mode by default (GPO4ADIN = 1) so that the GPO driver stage is high-impedance at power up. The GPO4 pin can be

configured by software for GPO operation with GPO4ADIN = 0. Refer to ADC Subsystem for GP ADC details.

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70






SUPPLIES

SUPPLIES

SUPPLY FLOW

The switched mode power supplies and the linear regulators are dimensioned to support a supply flow based upon Figure 15

.

Accessory

Charger

USB Cable

Interface

Protect and

Detect

Voltage &

Current

Control

Battery

BP

Power Audio

CC Charge

RTC,

MEMA/B

Coincell

Peripherals

UVBUS

SWBST

5.0V

SW4

1.8V

PGATE

IO and

Digital

External

Memory

VUSB

USB

PHY

VUSB2

Coin Cell

Vcoredig

Core

GPOs

Processor Interfaces

Serial Backlight

Drivers

Alternate hardwired bias option from SW4

Vcore

Vcam Viohi

Vpll Vdig VVIDEO

PNP

TV-DAC

SW1

0.6 to 1.15V

SW2

0.6 to 1.25V

SW3

1.25V

Peripherals

SOG Core

DVS Domain

PGATE

GP Core

DVS Domain

Internal

Processor

Memory

VAUDIO

Audio

Alternate hardwired bias option from external 2.2V switcher

Vsd

PNP

VGEN3

SD, Tflash

Peripherals

VGEN1

PNP

VGEN2

PNP

WLAN, BT MLC NAND

Camera

Peripherals

IO, EFUSE

Core PLLs

(Analog)

GPS Core

System

Supplies

Legend

External

Loads

Internal

Loads

Energy

Source

Figure 15. Supply Distribution

While maintaining the performance as specified, the minimum operating voltage for the supply tree is 3.0 V. For lower voltages, the performance may be degraded.

Table 43 summarizes the available power supplies.

Supply

SW1

SW2

SW3

SW4

SWBST

VIOHI

VPLL

VDIG

VSD

VUSB2

VVIDEO

VAUDIO

Table 43. Power Tree Summary

Purpose (Typical Application)

Buck regulators for processor core(s)

Buck regulators for processor SOG, etc.

Buck regulators for internal processor memory and peripherals

Buck regulators for external memory and peripherals

Boost regulator for USB OTG, Tri-color LED drivers

IO and Peripheral supply, eFuse support

Quiet Analog supply (PLL, GPS)

Low voltage digital (DPLL, GPS)

SD Card, external PNP

External USB PHY supply

TV DAC supply, external PNP

Audio supply

Output Voltage (in V)

0.600-1.375

0.600-1.375; 1.100-1.850

0.600-1.375; 1.100-1.850

0.600-1.375; 1.100-1.850

5.0

2.775

1.2/1.25/1.5/1.8

1.05/1.25/1.65/1.8

1.8/2.0/2.6/2.7/2.8/2.9/3.0/3.15

2.4/2.6/2.7/2.775

2.5/2.6/2.7/2.775

2.3/2.5/2.775/3.0

Load Capability (in mA)

1050

800

800

800

300

100

50

50

250

50

350

150


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SUPPLIES

Table 43. Power Tree Summary

Supply

VCAM

VGEN1

VGEN2

VGEN3

VUSB

Purpose (Typical Application)

Camera supply, internal PMOS

Camera supply, external PNP

General peripherals supply #1, external PNP


General peripherals supply #3, internal PMOS


USB Transceiver supply

Output Voltage (in V)

2.5/2.6/2.75/3.0

2.5/2.6/2.75/3.0

1.2/1.5/2.775/3.15

1.2/1.5/1.6/1.8/2.7/2.8/3.0/3.15

1.8/2.9

1.8/2.9

3.3

Load Capability (in mA)

65

250

200

350

50

250

100

BUCK REGULATOR SUPPLIES

Four buck regulators are provided with integrated power switches and synchronous rectification. In a typical application, SW1 and SW2 are used for supplying the application processor core power domains. Split power domains allow independent DVS control for processor power optimization, or to support technologies with a mix of device types with different voltage ratings. SW3 is used for powering internal processor memory as well as low voltage peripheral devices and interfaces which can run at the same voltage level. SW4 is used for powering external memory as well as low voltage peripheral devices and interfaces which can run at the same voltage level.

An anticipated platform use case applies SW1 and SW2 to processor power domains that require voltage alignment to allow direct interfacing without bandwidth limiting synchronizers.

The buck regulators have to be supplied from the system supply BP, which is drawn from the main battery or the battery charger (when present).

Figure 16 shows a high level block diagram of the buck regulators.

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72

Figure 16. Buck Regulator Architecture






SUPPLIES

The Buck regulator topology includes an integrated synchronous rectifier, meaning that the rectifying diode is implemented on the chip as a low ohmic FET. The placement of an external diode is therefore not required, but overall switcher efficiency may benefit from this. The buck regulators permit a 100% duty cycle operation.

During normal operation, several power modes are possible depending on the loading. For medium and full loading, synchronous PWM control is the most efficient, while maintaining a constant switching frequency. Two PWM modes are available: the first mode sacrifices low load efficiency for a continuous switching operation (PWM-NPS). The second mode offers better low load efficiency by allowing the absence of switching cycles at low output loading (PWM-PS). This pulse skipping feature improves efficiency by reducing dynamic switching losses by simply switching less often.

In its lowest power mode, the switcher can regulate using hysteresis control known as a Pulse Frequency Modulation (PFM) control scheme. The frequency spectrum in this case will be a function of input and output voltage, loading, and the external components. Due to its spectral variance and lighter drive capability, PFM mode is generally reserved for non-active radio modes and Deep Sleep operation.

Buck modes of operation are programmable for explicitly defined or load-dependent control (Adaptive). Refer to the Buck

regulators section in Power Control System

for details.

Common control bits available to each buck regulator may be designated with a suffix “x” within this specification, where x stands for 1, 2, 3, or 4 (i.e., SWx = SW1, SW2, SW3, and SW4).

The output voltages of the buck regulators are SPI configurable, and two output ranges are available, individually programmed with SWxHI for SW2, SW3, and SW4 bucks, SW1 is limited to only one output range. Presets are available for both the Normal and Standby operation. SW1 and SW2 also include pin controlled DVS operation. When transitioning from one voltage to another, the output voltage slope is controlled in steps of 25 mV per time step (time step as defined for DVS stepping for SW1 and SW2, fixed at 4.0

 s for SW3 and SW4). This allows for support of dynamic voltage scaling (DVS) by using SPI driven voltage steps, state machine defined modes, and direct DVSx pin control.

When initially activated, switcher outputs will apply controlled stepping to the programmed value. The soft start feature limits the inrush current at startup. A built-in current limiter ensures that during normal operation, the maximum current through the coil is not exceeded. This current limiter can be disabled by setting the SWILIMB bit.

Point of Load feedback is intended for minimizing errors due to board level IR drops.

SWITCHING FREQUENCY

The switchers are driven by a high frequency clock. By default, the PLL generates an effective 3.145728 MHz signal based upon the 32.768 kHz oscillator signal by multiplying it by 96. To reduce spurious radio channels, the PLL can be programmed via PLLX[2:0] to different values as shown in

Table 44

.

Table 44. PLL Multiplication Factor

PLLX[2:0]

000

001

010

011

100 (default)

101

110

111

Multiplication

Factor

96

99

102

105

84

87

90

93

Switching Frequency (Hz)

2 752 512

2 850 816

2 949 120

3 047 424

3 145 728

3 244 032

3 342 336

3 440 640

To reduce overall current drain, the PLL is automatically turned off if all switchers are in a PFM mode or turned off, and if the

PLL clock signal is not needed elsewhere in the system. The clocking system provides nearly instantaneously, a high frequency clock to the switchers when the switchers are activated or exit the PFM mode for PWM mode. The PLL can be configured for continuous operation by setting the SPI bit PLLEN = 1.





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SUPPLIES

Table 45. PLL Main Characteristics

Parameter

Frequency Accuracy

Condition

(70)

Bias Current

Start up Time

PLLEN = 1

1 Buck Regulator active

2 Buck Regulators active



Cold Start

PFM to PWM

Notes

70.

Clock input to PLL is 32.768 kHz

Min

–

–

–

–

–

–

–

–

Typ

130

145

–

–

–

50

100

115

Max

190

210

700

600

100

80

150

170

Units

ppm



A



A



A



A



A ns ns

Table 46. PLL Control Registers

Name

PLLEN

PLLX[2:0]

R/W

R/W

R/W

Reset Signal

RESETB

RESET

Reset

State

0

100

Description

1 = Forces PLL on

0 = PLL automatically enabled

Selects PLL multiplication factor

BUCK REGULATOR CORE

Table 47. Buck Regulators (SW1, 2, 3, 4) Output Voltage Programmability

Set point

20

21

22

23

16

17

18

19

24

25

26

27

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

SWx[4:0]

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

01000

01001

01010

01011

01100

01101

01110

01111

00000

00001

00010

00011

00100

00101

00110

00111

SWx Output, SWxHI = 0 (Volts)

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

0.600

0.625

0.650

0.675

0.700

0.725

0.750

0.775

SWx Output

(71)

, SWxHI = 1 (Volts)

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

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



SUPPLIES

Table 47. Buck Regulators (SW1, 2, 3, 4) Output Voltage Programmability

Set point SWx[4:0] SWx Output, SWxHI = 0 (Volts) SWx Output

(71)

, SWxHI = 1 (Volts)

28

29

30

31

11100

11101

11110

11111

1.300

1.325

1.350

1.375

1.800

1.825

1.850

1.850

71.

Output range not available for SW1. SW1 output range is 0.600-1.375, therefore SW1HI = 1 does not apply to SW1. The SW1HI bit should always be set to 0.

Since the startup default values of the buck regulators are dependent on the state of the PUMS pin, the SWxHI bit settings will likewise be determined by the PUMS pin. The settings are aligned to the likely application ranges for use cases as given in the

Defaults tables in

Power Control System . The following tables define the SWxHI bit states after a startup event is completed, but

can be reconfigured via the SPI if desired, if an alternate range is needed. Care should be taken when changing SWxHI bit to avoid unintended jumps in the switcher output. The SWxHI setting applies to Normal, Standby, and DVS set points for the corresponding switcher.

Table 48. SWxHI States for Power Up Defaults

PUMS1

PUMS2

SW1HI

SW2HI

SW3HI

SW4HI

Ground

Open

0

0

0

1

Open

Open

0

0

0

1

VCOREDIG

Open

0

0

0

1

VCORE

Open

0

0

0

1

Ground

Ground

0

1

1

1

Open

Ground

0

1

1

1

Note that the following efficiency curves were measured with the MC13892 in a socket.





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SUPPLIES

SW1 PFM mode Efficiency Vout = 0,725 V

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

0 5 10 15 20 25 30 35 40 45 50 55 60 65

Il oad (m A)

70 75 80 85 90 95 100

SW2 PFM mode Efficiency Vout = 1.250 V

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

0 5 10 15 20 25 30 35 40 45 50 55 60 65

Il oad (m A)

70 75 80 85 90 95 100

SW4 PFM mode Efficiency Vout = 1.800 V

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

0 5 10 15 20 25 30 35 40 45 50 55 60 65

Il oad (m A)

70 75 80 85 90 95 100

Figure 17. Buck Regulator PFM Efficiency

Vin = 2, 800 V

Vin = 3, 600 V

Vin = 4, 650 V

Vin = 2, 800 V

Vin = 3, 600 V

Vin = 4, 650 V

Vin = 2, 800 V

Vin = 3, 600 V

Vin = 4, 650 V

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



SUPPLIES

S W1 P WM No P ulse Ski pp ing mode Efficien cy V out = 0,725 V

100 %

90 %

80 %

70 %

60 %

50 %

40 %

30 %

20 %

10 %

0 %

0 1 0 20 3 0 40 50

Ilo a d (m A)

60 70 80 90 10 0

S W2 P WM No P ulse Ski pp ing mode Efficien cy V out = 1.250 V

100 %

90 %

80 %

70 %

60 %

50 %

40 %

30 %

20 %

10 %

0 %

0 1 0 20 3 0 40 50

Ilo a d (m A)

60 70 80 90 10 0

S W4 P WM No P ulse Ski pp ing mode Efficien cy V out = 1.800 V

100 %

90 %

80 %

70 %

60 %

50 %

40 %

30 %

20 %

10 %

0 %

0 1 0 20 3 0 40 50

Ilo a d (m A)

60 70 80 90 10 0

Vin = 3 ,00 0 V

Vin = 3 ,60 0 V

Vin = 4 ,65 0 V

Vin = 3 ,00 0 V

Vin = 3 ,60 0 V

Vin = 4 ,65 0 V

Vin = 3 ,00 0 V

Vin = 3 ,60 0 V

Vin = 4 ,65 0 V

S W4 P WM No P ul se S kipp ing mode Efficien cy V out = 1.800 V

100 %

90 %

80 %

70 %

60 %

50 %

40 %

30 %

20 %

10 %

0 %

0 50 1 00 1 50 20 0 2 50 30 0 35 0 400 450 5 00 5 50 60 0 65 0 700 750 8 00 850 9 00

Il oa d (mA)


100 %

90 %

80 %

70 %

60 %

50 %

40 %

30 %

20 %

10 %

0 %

0 50 1 00 1 50 20 0 2 50 30 0 35 0 400 450 5 00 5 50 60 0 65 0 700 750 8 00 850 9 00

Il oa d (mA)


100 %

90 %

80 %

70 %

60 %

50 %

40 %

30 %

20 %

10 %

0 %

0 50 1 00 1 50 20 0 2 50 30 0 35 0 400 450 5 00 5 50 60 0 65 0 700 750 8 00 850 9 00

Il oa d (mA)

Vin = 3,0 00 V

Vin = 3,6 00 V

Vin = 4,6 50 V

Vin = 3,0 00 V

Vin = 3,6 00 V

Vin = 4,6 50 V

Vin = 3,0 00 V

Vin = 3,6 00 V

Vin = 4,6 50 V

Figure 18. Buck Regulator PWM (No Pulse Skipping) Efficiency





MC13892

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SUPPLIES

100 %

90 %

80 %

70 %

60 %

50 %

40 %

30 %

20 %

10 %

0 %

0

100 %

90 %

80 %

70 %

60 %

50 %

40 %

30 %

20 %

10 %

0 %

0

100 %

90 %

80 %

70 %

60 %

50 %

40 %

30 %

20 %

10 %

0 %

0

S W1 P WM Pu lse S kip pi ng mo de E ffi ciency Vo ut = 0, 725 V

Vin = 3 ,00 0 V

Vin = 3 ,60 0 V

Vin = 4 ,65 0 V

S W1 PWM P ulse Ski ppi ng mo de E ffi ciency Vo ut = 0, 725 V

100 %

90 %

80 %

70 %

60 %

50 %

40 %

30 %

20 %

10 %

0 %

0 50 1 00 150 200 25 0 300 35 0 4 00 450 50 0 55 0 6 00 650 70 0 7 50 800 85 0 90 0 9 50 10 0

0

1 05

0

Il oa d (mA)

1 0 20 3 0 40 50

Ilo a d (mA)

60 70 80 90 10 0

S W2 P WM Pu lse S kip pi ng mo de E ffi ciency Vo ut = 1. 250 V

1 0

1 0

20 3 0 40 50

Ilo a d (mA)

60 70 80 90 10 0

Vin = 3 ,00 0 V

Vin = 3 ,60 0 V

Vin = 4 ,65 0 V

S W2 P WM Pu lse S kip pin g m od e E ffici ency V ou t = 1.250 V

100 %

90 %

80 %

70 %

60 %

50 %

40 %

30 %

20 %

10 %

0 %

0 50 1 00 1 50 20 0 25 0 300 350 4 00 4 50 50 0 55 0 600

Ilo a d (mA)

650 7 00 7 50 80 0 85 0 900

S W4 P WM Pu lse S kip pi ng mo de E ffi ciency Vo ut = 1. 800 V

20 3 0 40 50

Ilo a d (mA)

60 70 80 90 10 0

Vin = 3 ,00 0 V

Vin = 3 ,60 0 V

Vin = 4 ,65 0 V

S W4 PWM P ulse Ski ppi ng mo de E ffi ciency Vo ut = 1. 800 V

100 %

90 %

80 %

70 %

60 %

50 %

40 %

30 %

20 %

10 %

0 %

0 50 1 00 1 50 20 0 2 50 30 0 35 0 400 450 5 00 5 50 60 0 65 0 700

Il oa d (mA)

750 8 00 850 9 00

Figure 19. Buck Regulator PWM (Pulse Skipping) Efficiency

Vin = 3,0 00 V

Vin = 3,6 00 V

Vin = 4,6 50 V

Vin = 3, 000 V

Vin = 3, 600 V

Vin = 4, 650 V

Vin = 3,0 00 V

Vin = 3,6 00 V

Vin = 4,6 50 V

DYNAMIC VOLTAGE SCALING

To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor. SW1 and SW2 allow for three different set points with controlled transitions to avoid sudden output voltage changes, which could cause logic disruptions on their loads. Preset operating points for SW1 and SW2 can be set up for:

• Normal operation: output value selected by SPI bits SWx[4:0]. Voltage transitions initiated by SPI writes to SWx[4:0] are governed by the same DVS stepping rate that is programmed for DVSx pin initiated transitions.

• DVS: output can be higher or lower than normal operation for tailoring to application requirements. Configured by SPI bits

SWxDVS[4:0] and controlled by a DVSx pin transition.

• Standby (Deep Sleep): can be higher or lower than normal operation, but is typically selected to be the lowest state retention voltage of a given process. Set by SPI bits SWxSTBY[4:0] and controlled by a Standby event (STANDBY logically anded with

STANDBYSEC). Voltage transitions initiated by Standby are governed by the same DVS stepping that is programmed for

DVSx pin initiated transitions.

The following tables summarize the set point control and DVS time stepping applied to SW1 and SW2.

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



SUPPLIES

Table 49. DVS Control Logic Table for SW1 and SW2

STANDBY

(72)

0

0

1

DVSx Pin

0

1

X

Set Point Selected by

SWx[4:0]

SWxDVS[4:0]

SWxSTBY[4:0]

Notes

72.

STANDBY is the logical anding of STANDBY and STANDBYSEC

Table 50. DVS Speed Selection for SW1 and SW2

SWxDVSSPEED[1:0]

00

01 (default)

10

11

Function

25 mV step each 2.0

 s

25 mV step each 4.0

 s

25 mV step each 8.0

 s

25 mV step each 16

 s

Since the switchers have a strong sourcing capability but no active sinking capability, the rising slope is determined by the switcher, but the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation.

Note that there is a special mode of DVS control for Switcher Increment / Decrement (SID) operation described later in this chapter.

DVS pin controls are not included for SW3 and SW4. However, voltage transitions programmed through the SPI will step in increments of 25 mV per 4.0

 s, to allow SPI controlled voltage stepping with SWx[4:0]. Additionally, SW3 and SW4 include

Standby mode set point programmability.

Figure 20

shows the general behavior for the switchers when initiated with pin controlled DVS, SPI programming or standby control.

Figure 20. SW1 Voltage Stepping with Pin Controlled DVS

Note that the DVSx input pins are reconfigured for Switcher Increment / Decrement (SID) control mode when SPI bit

SIDEN = 1. Refer to the SID description below for further details.

SWITCHER INCREMENT / DECREMENT

A scheme for incrementing or decrementing the operating set points of SW1 and SW2 is desirable for improved Dynamic

Process and Temperature Compensation (DPTC) control in support of fine tuning power domains for the processor supply tree.

An increment command will increase the set point voltage by a single 25 mV step. A decrement command will decrease the set point by a single 25 mV step. The transition time for the step will be the same as programmed with SWxDVSSPEED[1:0] for DVS


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stepping. If a switcher runs out of programmable range (in either direction), as constrained by programmable stops, then the increment or decrement command shall be ignored.

The Switcher Increment / Decrement (SID) function is enabled with SIDEN = 1. This will reassign the function of the DVS1 and

DVS2 pins, from the default toggling between Normal and DVS operating modes, to a jog control mode for the switcher which

DVSx is assigned. Once enabled, the switcher being controlled will start at the Normal mode set point as programmed with

SWx[4:0] and await any jog commands from the processor. The adjustment scheme essentially intercepts the Normal mode set point SPI bits (i.e., but not DVS or Standby programmed set points), and makes any necessary adjustments based on jog up or jog down commands. The modified set point bits are then immediately passed to the switching regulator, which would then do a

DVS step in the appropriate direction. The SPI bits containing Normal mode programming are not directly altered.

When configured for SID mode, a high pulse on the DVSx pin will indicate one of 3 actions to take, with the decoding as a function of how many contiguous SPI clock falling edges are seen while the DVSx pin is held high.

Table 51. SID Control Protocol

Number of SPI CLK Falling

Edges while DVSx = 1

0

1

2

3 or more

Function

No action. Switcher stays at its presently programmed configuration

Jog down. Drive buck regulator output down a single DVS step

Jog up. Drive buck regulator output up a single DVS step

Panic Mode. DVS step the buck regulator output to the Normal mode value as programmed in the SPI register

The SID protocol is illustrated by way of example, assuming SIDEN = 1, and that DVS1 is controlling SW1. SW1 starts out at its default value of 1.250 V (SW1 = 11010) and is stepped both up and down via the DVS1 pin. The SPI bits SW1 = 11010 do not change. The set point adjustment takes place in the SID block prior to bit delivery to the switcher's digital control.

Starting Value

SW1 output

1.250

DVS

Up

1.275

DVS

Down

1.250

DVS

Down

1.225

DVS1

Up

Down

Down

SPICLK

1 2 1

1

SPICLK shut down when not used

Figure 21. SID Control Example for Increment & Decrement

SID Panic Mode is provided for rapid recovery to the programmed Normal mode output voltage, so the processor can quickly

recover to its high performance capability with a minimum of communication latency. In Figure 22

, Panic Mode recovery is illustrated as an Increment step, initiated by the detection of the second falling SPI clock edge, followed by a continuation to the programmed SW1[4:0] level (1.250 V in this example), due to the detection of the third contiguous falling edge of SPI clock while

DVS1 is held high.

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SID Panic Mode Example

DVS step all the way back to 1.250V

(SW1[4:0] programmed value = 1.250V)

Starting Value DVS

Up

SW1 output

1.050

DVS1

Up Panic

SPICLK

1 2 3

SPICLK shut down when not used

Figure 22. SID Control Example for Panic Mode Recovery

The system will not respond to a new jog command until it has completed a DVS step that may be in progress. Any missed jog requests will not be stored. For instance, if a switcher is stepping up in voltage with a 25 mV step over a 4.0

 s time, response to the DVSx pin for another step will be ignored until the DVS step period has expired. However, the Panic Mode step recovery should respond immediately upon detection of the third SPICLK edge while the corresponding DVSx pin is high, even if the initial decode of the jog up command is ignored, because it came in before the previous step was completed.

While in SID mode, programmable stops are used to set limits on how far up and how far down a SID-controlled buck regulator will be allowed to step. The SWxSIDMIN[3:0] and SWxSIDMAX[3:0] bits can be used to ensure that voltage stepping is confined to within the acceptable bounds for a given process technology used for the BB IC.

To contain all of the SWx voltage setting bits in single banks, the SWxSIDMIN[3:0] word is shortened to 4-bits, but should be decoded by logic to have an implied leading 0 (i.e., MSB = 0, but is not included in the programmable word). For instance,

SW1SIDMIN = 1000 (default value) should be decoded as 01000, which corresponds to 0.800 V (assuming SW1HI = 0).

Likewise, the SWxSIDMAX[3:0] word is shortened to 4-bits, but should be decoded by logic to have an implied leading 1

(MSB = 1, but is not included in the programmable word). For instance, SW1SIDMAX = 1010 (default value) should be decoded as 11010, which corresponds to 1.250 V (again, assuming SW1HI = 0).

A new SPI write for the active switcher output value with SWx[4:0] should take immediate effect, and this becomes the new baseline from which succeeding SID steps are referenced. The SWxDVS[4:0] value is not considered during SID mode. The system only uses the SWx[4:0] bits and the min/max stops SWxSIDMIN[3:0] and SWxSIDMAX[3:0].

When in SID mode, a STANDBY = 1 event (pin states of STANDBY and STANDBYSEC) will have the “immediate” effect (after any STBYDLY delay has timed out) of changing the set point and mode to those defined for Standby operation. Exiting Standby puts the system back to the normal mode set point with no stored SID adjustments -- the system will recalibrate itself again from the refreshed baseline.

BOOST REGULATOR

SWBST is a boost switching regulator with a fixed 5.0 V output. It runs at 2/3 of the switcher PLL frequency. SWBST supplies the VUSB regulator for the USB system in OTG mode, and it also supplies the power for the RGB LED's. When SWBST is configured to supply the VBUS pin in OTG mode, the feedback will be switched to sense the UVBUS pin instead of the SWBSTFB pin. Therefore, when driving the VBUS for OTG mode the output of the switcher may rise to 5.75 V to compensate for the voltage drops on the internal switches. Note that the parasitic leakage path for a boost regulator will cause the output voltage

SWBSTOUT and SWBSTFB to sit at a Schottky drop below the battery voltage whenever SWBST is disabled. The switching

NMOS transistor is integrated on-chip. An external fly back Schottky diode, inductor and capacitor are required.


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Figure 23. Boost Regulator Architecture

Enabling of SWBST is accomplished through the SWBSTEN SPI control bit.

Table 52. Switch Mode Supply SWBST Control Function Summary

Parameter

SWBSTEN

Value

0

1

Function

SWBST OFF

SWBST ON

5V Boost Efficiency

(Vin = 3.6V, Vou t = 5V)

100.00

95.00

90.00

85.00

80.00

0 1 00 2 00

Boost Load Current (mA)

Figure 24. Boost Regulator Efficiency

300

LINEAR REGULATORS

This section describes the linear regulators provided. For convenience, these regulators are named to indicate their typical or possible applications, but the supplies are not limited to these uses and may be applied to any loads within the specified regulator capabilities.

A low-power standby mode controlled by STANDBY is provided in which the bias current is aggressively reduced. This mode is useful for deep sleep operation where certain supplies cannot be disabled, but active regulation can be tolerated with lesser parametric requirements. The output drive capability and performance are limited in this mode. Refer to STANDBY Event

Definition and Control in

Power Control System for more details.

Some dedicated regulators are covered in their related chapters rather than in the Supplies chapter (i.e., the VUSB and VUSB2 supplies are included in

Connectivity ).

Apart from the integrated linear regulators, there are also GPO output pins provided to enable and disable discrete regulators or functional blocks, or to use as a general purpose output for any system need. For example, one application may be to enable a battery pack thermistor bias in synchronization with timed ADC conversions.

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All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at REFCORE. The bandgap and the rest of the core circuitry is supplied from VCORE. The performance of the regulators is directly dependent on the performance of VCOREDIG and the bandgap. No external DC loading is allowed on VCOREDIG or REFCORE. VCOREDIG

is kept powered as long as there is a valid supply and/or coin cell. Table 53 captures the main characteristics of the core circuitry.

Table 53. Core Specifications

Reference

VCOREDIG (Digital core supply)

VCORE (Analog core supply)

REFCORE (Bandgap / Regulator Reference)

Parameter

Output voltage in ON mode

(73) , (74)

Output voltage in Off mode

(74)

Bypass Capacitor

Output voltage in ON mode

(73) , (74)

Output voltage in Off mode

(74)

Bypass Capacitor

Output voltage

(73)

Absolute Accuracy

Temperature Drift

Bypass Capacitor

Target

1.5 V

1.2 V

2.2



F typ (0.65



F derated)

2.775 V

0.0 V

2.2



F typ (0.65



F derated)

1.20 V

0.50%

0.25%

100 nF typ (65 nF derated)

Notes

73.

3.0 V < BP < 4.65 V, no external loading on VCOREDIG, VCORE, or REFCORE. Extended operation down to UVDET, but no system malfunction.

74.

The core is in On mode when charging or when the state machine of the IC is not in the Off mode nor in the power cut mode. Otherwise, the core is in Off mode.

REGULATORS GENERAL CHARACTERISTICS

The following applies to all linear regulators unless otherwise specified.

• Specifications are for an ambient temperature of -40 to +85 °C.

• Advised bypass capacitor is the Murata™ GRM155R60G225ME15 which comes in a 0402 case.

• In general, parametric performance specifications assume the use of low ESR X5R ceramic capacitors with 20% accuracy and 15% temperature spread, for a worst case stack up of 35% from the nominal value. Use of other types with wider temperature variation may require a larger room temperature nominal capacitance value to meet performance specs over temperature. In addition, capacitor derating as a function of DC bias voltage requires special attention. Finally, minimum bypass capacitor guidelines are provided for stability and transient performance. Larger values may be applied; performance metrics may be altered and generally improved, but should be confirmed in system applications.

• Regulators which require a minimum output capacitor ESR (those with external PNPs) can avoid an external resistor if ESR is assured with capacitor specifications, or board level trace resistance.

• The output voltage tolerance specified for each of the linear regulators include process variation, temperature range, static line regulation, and static load regulation.

• The PSRR of the regulators is measured with the perturbed signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements care must be taken not to reach the drop out of the regulator under test.

• In the Low-power mode the output performance is degraded. Only those parameters listed in the Low-power mode section are guaranteed. In this mode, the output current is limited to much lower currents than in the Active mode.

• Regulator performance is degraded in the extended input voltage range. This means that the supply still behaves as a regulator and will try to hold up the output voltage by turning the pass device fully on. As a result, the bias current will increase and all performance parameters will be heavily degraded, such as PSRR and load regulation.

• Note that in some cases, the minimum operating range specifications may be conflicting due to numerous set point and biasing options, as well as the potential to run BP into one of the software or hardware shutdown thresholds. The specifications are general guidelines which should be interpreted with some care.

• When a regulator gets disabled, the output will be pulled towards ground by an internal pull-down. The pull-down is also activated when RESETB goes low.

• 32 kHz spur levels are specified for fully loaded conditions.


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• Short-circuit protection (SCP) is included on certain LDOs (see the SCP section later in this chapter). Exceeding the SCP threshold will disable the regulator and generate a system interrupt. The output voltage will not sag below the specified voltage for the rated current being drawn. For the lower current LDOs without SCP, they are less accessible to the user environment and essentially self-limiting.

• The power tree of a given application must be scrubbed for critical use cases to ensure consistency and robustness in the power strategy.

TRANSIENT RESPONSE WAVEFORMS

The transient load and line response are specified with the waveforms as depicted in Figure 25

. Note that the transient load response refers to the overshoot only, excluding the DC shift itself. The transient line response refers to the sum of both overshoot and DC shift. This is also valid for the mode transition response.

Figure 25. Transient Waveforms

SHORT-CIRCUIT PROTECTION

The higher current LDOs and those most accessible in product applications include short-circuit detection and protection

(VVIDEO, VAUDIO, VCAM, VSD, VGEN1, VGEN2, and VGEN3). The short-circuit protection (SCP) system includes debounced fault condition detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize chance of

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product damage. If a short-circuit condition is detected, the LDO will be disabled by resetting its VxEN bit while at the same time an interrupt SCPI will be generated to flag the fault to the system processor.

The SCPI interrupt is maskable through the SCPM mask bit.

The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, then not only is no interrupt generated, but also the regulators will not automatically be disabled upon a short-circuit detection. However, the built-in current limiter will continue to limit the output current of the regulator. Note that by default, the REGSCPEN bit is not set, so at startup none of the regulators that are in an overload condition will be disabled

VAUDIO AND VVIDEO SUPPLIES

The primary applications of these power supplies are for audio, and TV-DAC. However these supplies could also be used for other peripherals if one of these functions is not required. Low-power modes and programmable Standby options can be used to optimize power efficiency during Deep Sleep modes.

An external PNP is utilized for VVIDEO to avoid excess on-chip power dissipation at high loads, and large differential between

BP and output settings. For stability reasons a small minimum ESR may be required. In the Low-power mode for VVIDEO an internal bypass path is used instead of the external PNP. External PNP devices are always to be connected to the BP line in the application. The recommended PNP device is the ON Semiconductor NSS12100XV6T1G which is capable of handling up to

250 mW of continuous dissipation at minimum footprint and 75 °C of ambient. For use cases where up to 500mW of dissipation is required, the recommended PNP device is the ON Semiconductor



NSS12100UW3TCG. For stability reasons a small minimum ESR may be required.

VAUDIO is implemented with an integrated PMOS pass FET and has a dedicated input supply pin VINAUDIO.

The following tables contain the specifications for the VVIDEO, VAUDIO.

Table 54. VVIDEO and VAUDIO Voltage Control

Parameter

VVIDEO

VAUDIO

Value

00

01

10

11

00

01

10

11

Function

Output = 2.700 V

Output = 2.775 V

Output = 2.500 V

Output = 2.600 V

Output = 2.300 V

Output = 2.500 V

Output = 2.775 V

Output = 3.000 V

ILoad max

250 mA / 350 mA

250 mA / 350 mA

250 mA / 350 mA

250 mA / 350 mA

150 mA

150 mA

150 mA

150 mA

LOW VOLTAGE SUPPLIES

VDIG and VPLL are provided for isolated biasing of the Baseband system PLLs for clock generation in support of protocol and peripheral needs. Depending on the lineup and power requirements, these supplies may be considered for sharing with other loads, but noise injection must be avoided and filtering added if necessary, to ensure suitable PLL performance. The VDIG and

VPLL regulators have a dedicated input supply pin: VINDIG for the VDIG regulator, and VINPLL for the VPLL regulator. VINDIG and VINPLL can be connected to either BP or a 1.8V switched mode power supply rail, such as from SW4 for the two lower set points of each regulator VPLL[1:0] and VDIG[1:0] = [00], [01]. In addition, when the two upper set points are used VPLL[1:0] and

VDIG[1:0] = [10], [11], the inputs (VINDIG and VINPLL) can be connected to either BP of a 2.2 V nominal external switched mode power supply rail to improve power dissipation.

Table 55. VPLL and VDIG Voltage Control

Parameter

VPLL[1:0]

VDIG[1:0]

Value

00

01

10

11

00

01

10

11

Function

output = 1.2 V output = 1.25 V output = 1.5 V output = 1.8 V output = 1.05 V output = 1.25 V output = 1.65 V output = 1.8 V

ILoad max

50 mA

50 mA

50 mA

50 mA

50 mA

50 mA

50 mA

50 mA

Input Supply

BP or 1.8 V

BP or 1.8 V

BP or External Switcher


BP or 1.8 V

BP or 1.8 V




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PERIPHERAL INTERFACING

IC interfaces in the lineups generally fall in two categories: low voltage IO primarily associated with the AP IC and certain peripherals at SPIVCC level (powered from SW4), and a higher voltage interface level associated with other peripherals not compatible with the 1.8 V SPIVCC. VIOHI is provided at a fixed 2.775 V level for such interfaces, and may also be applied to other system needs within the guidelines of the regulator specifications. The input VINIOHI is not only used by the VIOHI regulator, but also by other blocks, therefore it should always be connected to BP, even if the VIOHI regulator is not used by the system.

VIOHI has an internal PMOS pass FET which will support loads up to 100 mA.

CAMERA

The camera module is supplied by the regulator VCAM. This allows powering the entire module independent of the rest of other parts of the system, as well as to select from a number of VCAM output levels for camera vendor flexibility. In applications with a dual camera, it is anticipated that only one of the two cameras is active at a time, allowing the VCAM supply to be shared between them.

VCAM has an internal PMOS pass FET which will support up to 2.0 Mpixel Camera modules (<65 mA). To support higher resolution cameras, an external PNP is provided. The external PNP configuration is offered to avoid excess on-chip power dissipation at high loads, and large differential between BP and output settings. For lower current requirements, an integrated

PMOS pass FET is included. The input pin for the integrated PMOS option is shared with the base current drive pin for the PNP option. The external PNP configuration must be committed as a hardwired board level implementation, while the operating mode is selected through the VCAMCONFIG bit after startup. The VCAM is not automatically enabled during the power up sequence, allowing software to properly set the VCAMCONFIG bit before the regulator is activated. The recommended PNP device is the

ON Semiconductor NSS12100XV6T1G which is capable of handling up to 250 mW of continuous dissipation at a minimum footprint and 75 °C of ambient. For use cases where up to 500 mW of dissipation is required, the recommended PNP device is the ON Semiconductor NSS12100UW3TCG. For stability reasons a small minimum ESR may be required.

The input VINCAM should always be connected to BP, even if the VCAM regulator is not used by the system.

Table 56. VCAM Voltage Control

Parameter

VCAM[1:0]

Value

00

01

10

11

Output Voltage

2.5 V

2.6 V

2.75 V

3.00 V

VCAMCONFIG=0

Internal Pass FET

65 mA

65 mA

65 mA

65 mA

ILoad max

VCAMCONFIG=1

External PNP

250 mA

250 mA

250 mA

250 mA

MULTI-MEDIA CARD SUPPLY

This supply domain is generally intended for user accessible multi-media cards, such as Micro-SD (TransFlash), RS-MMC, and the like. An external PNP is utilized for this LDO to avoid excess on-chip power dissipation at high loads and large differential between BP and output settings. The external PNP device is always connected to the BP line in the application. VSD may also be applied to other system needs within the guidelines of the regulator specifications. The recommended PNP device is the ON

Semiconductor NSS12100XV6T1G, which is capable of handling up to 250 mW of continuous dissipation at a minimum footprint and 75 °C of ambient. For use cases where up to 500 mW of dissipation is required, the recommended PNP device is the ON

Semiconductor NSS12100UW3TCG. For stability reasons a small minimum ESR may be required. At the 1.8 V set point, the

VSD regulator can be powered from an external buck regulator (2.2 V typ) for an efficiency advantage and reduced power dissipation in the pass devices.

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Table 57. VSD Voltage Control

Parameter

VSD[2:0]

Value

100

101

110

111

000

001

010

011

Output Voltage

1.80 V

2.00 V

2.60 V

2.70 V

2.80 V

2.90 V

3.00 V

3.15 V

ILoad max

250 mA

250 mA

250 mA

250 mA

250 mA

250 mA

250 mA

250 mA

Input Supply


BP

BP

BP

BP

BP

BP

BP

GEN1, GEN2, AND GEN3 REGULATORS

General purpose LDOs VGEN1, VGEN2, and VGEN3 are provided for expansion of the power tree to support peripheral devices, which could include WLAN, BT, GPS, or other functional modules. All the regulators include programmable set points for system flexibility. At the 1.2 V and 1.5 V set points, both VGEN1 and VGEN2 can be powered from an external buck regulator

(2.2 V typ) for an efficiency advantage, and reduced power dissipation in the pass devices. (Note that a connection to BP or the external buck regulator as the input to the regulators is a hardwired board level commitment, and not changed on-the-fly).

Table 58. VGEN1 Control Register Bit Assignments

Parameter

VGEN1[1:0]

Value

00

01

10

11 output = 1.20 V output = 1.50 V output = 2.775 V output = 3.15 V

Function ILoad max

(75)

200 mA

200 mA

200 mA

200 mA

Input Supply

BP or external switcher


BP

BP

Notes

75.

The max load given for VGEN1MODE = 0 and must take into account the capabilities of the external pass device and operating conditions, to manage its power dissipation. Load capability is 3.0 mA for VGEN1MODE = 1.

Table 59. VGEN2 Control Register Bit Assignments

Parameter

VGEN2[2:0]

Value

000

001

010

011

100

101

110

111

Function

output = 1.20 V output = 1.50 V output = 1.60 V output = 1.80 V output = 2.70 V output = 2.80 V output = 3.00 V output = 3.15 V

ILoad max

350 mA

350 mA

350 mA

350 mA

350 mA

350 mA

350 mA

350 mA

(76)

Input Supply



BP

BP

BP

BP

BP

BP

Notes

76.

The max load is given for as VGEN2MODE = 0, and must take into account the capabilities of the external pass device and operating conditions to manage its power dissipation. Load capability is 3.0 mA for VGEN2MODE = 1.

VGEN3 has an internal PMOS pass FET which will support loads up to 50 mA. For higher current capability, drive for an external PNP is provided. The external PNP configuration is offered to avoid excess on-chip power dissipation at high loads, and large differential between BP and output settings. The input pin for the integrated PMOS option is shared with the base current drive pin for the PNP option. The external PNP configuration must be committed as a hardwired board level implementation, while the operating mode is selected through the VGEN3CONFIG bit after startup. The VGEN3 is not automatically enabled during the power up sequence, allowing software to properly set the VGEN3CONFIG bit before the regulator is activated. The recommended PNP device is the ON Semiconductor NSS12100XV6T1G, which is capable of handling up to 250 mW of

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continuous dissipation at minimum footprint and 75 °C of ambient. For use cases where up to 500 mW of dissipation is required, the recommended PNP device is the ON Semiconductor NSS12100UW3TCG. For stability reasons a small minimum ESR may be required.

A short circuit condition will shut down the VGEN3 regulator and generate an interrupt for SCPI.

Table 60. VGEN3 Voltage Control

VGEN3 bit

0

1

Output Voltage

1.80 V

2.90 V

VGEN3CONFIG = 0

Internal Pass FET

50 mA

50 mA

ILoad max

VGEN3CONFIG = 1

External PNP

200 mA

200 mA

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BATTERY INTERFACE AND CONTROL

The battery management interface is optimized for applications with a single charger connector to which a standard wall charger or a USB host can be connected. It can also support dead battery operation and unregulated chargers.

CHARGE PATH

CHARGER LINE UP

The charge path is depicted in the following diagram.

Figure 26. Charge Path Block Diagram

Transistors M1 and M2 control the charge current and provide voltage regulation. The latter is used as the top off change voltage, and as the regulated supply voltage to the application in case of a dead battery operation. In order to support dead battery operation, a so called “serial path” charging configuration including M3 needs to be used. Then in case of a dead battery, the transistor M3 is made non-conducting and the internal trickle charge current charges the battery. If the battery is sufficiently charged, the transistor M3 is made conducting which connects the battery to the application just like during normal operation without a charger. In so called single path charging, M3 is replaced by a short and the pin BATTFET must be floating. Dead battery operation is not supported in this case. Transistors M1 and M2 become non-conducting if the charger voltage is too high.

The VBUS must be shorted to CHRGRAW in cases where the wall charger and VBUS voltages are contained on a common pin.

A current can be supplied from the battery to an accessory with all transistors M1, M2, and M3 conducting, by enabling the reverse supply mode. An unregulated wall charger configuration can be built, in which case CHRGSE1B must be pulled low. The battery current monitoring resistor R1 and the charge LED indicator are optional. More detail on the battery current monitoring can be found in

ADC Subsystem .

The preferred devices for M1 and M2 are Fairchild™ FDZ193P, due to their small package outline and thermal characteristics.

The preferred device for M3 is the On Semiconductor NTHS2101P for its low R

DSON

and small footprint.

CHARGER SIGNALS

The charger uses a number of thresholds for proper operation and will also signal various events to the processor through interrupts.

Table 61

summarizes the main signals given, including the control bits. For details see the related sections in this

chapter and the SPI bit summary in SPI Bitmap .

Table 61. Main Control Bit Signals

Name

Control Bits

VCHRG[2:0]

ICHRG[3:0]

TREN

Charger regulator voltage setting

Charger regulator current setting

Internal trickle charger enabling

Description


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Table 61. Main Control Bit Signals

THCHKB

CYCLB

Name

FETOVRD, FETCTRL

RVRSMODE

PLIM[1:0], PLIMDIS

CHRGLEDEN

CHGRESTART

CHGAUTOB

CHGAUTOVIB

Description

Battery thermistor check disable

SPI control over BATTFET pin (M3)

FETOVRD: 0 = BATTFET output are controlled by hardware

1 = BATTFET controlled by the state of the FETCTRL bit

FETOCTRL: 0 = BATTFET is driven high if FETOVRD is set

1 = BATTFET is driven low if FETOVRD is set

Reverse mode enabling

0 = Reverse mode disabled

1 = Reverse mode enabled

Power limiter setting and disabling

PLIMDIS: 0 = Power limiter enabled

1 = Power limiter disabled

Charge LED indicator enabling

0 = CHRGLED disabled

1 = CHRGLED enabled

Charger state machine restart

Selects between standalone or software controlled charging operation

0 = Standalone charging

1 = Software controlled charging

Allows for SPI control over-voltage and current settings in standalone charging mode

Controls charging resume behavior

0 = Enables cycling

1 = Disables cycling

Interrupt and Status bits

CHGDETI

CHGFAULTI

CHGFAULTS[1:0]

CHGENS

USBOVI

CHGSHORTI

CHGREVI

CHGCURRI

CCCVI

CHRGSE1BI

CHRGSE1BS

CHRGSSS

Thresholds

Charger attach

CHRGRAW over-voltage, excessive power dissipation, timeout, battery out of temperature range

Charger fault mode sense bits

Charger enable sense bit

USB over-voltage

Short-circuit detection in reverse mode

Charger path reverse current, detection based on CHGCURR threshold

Charge current threshold, detection based on CHGCURR threshold

Charger path regulation mode, detection based on BATTCYCL threshold

Wall Charger Detect

CHRSE1B pin sense

Charger configuration sense, serial versus single. A logic 1 indicates a serial path.

CHGCURR

BATTMIN

BPON

BATTON

BATTCYCL

CHRGISNS-BPSNS at 35 mA flowing into phone, used for end of charge detection, charger removal and charge current reversal

BATT at 3.0 V, used to increase charge current (40/80 mA and 80/560 mA), detect a dead battery insertion while charging

BP at 3.2 V, used to allow turn on when charging from USB, closes M3 when in serial path

BATT at 3.4 V, used to allow turn on when charging from USB, closes M3 when in serial path

BPSNS at 98% of charger voltage setting, used to restart charging, used by CCCVI

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BUILDING BLOCKS AND FUNCTIONS

The battery management interface consists of several building blocks and functions as depicted in the block diagram shown in the previous paragraph. These building blocks and functions are described below while the charger operation is described in the next section.

CHARGE PATH REGULATOR

The M1 and M2 are permanently used as a combined pass device for a super regulator, with a programmable output voltage and programmable current limit.

The voltage loop consists of M1, M2, and an amplifier with voltage feedback taken from the BPSNS pin. The value of the sense resistor is of no influence on the output voltage. The output voltage is programmable by SPI through VCHRG[2:0] bits.

Table 62. Charge Path Regulator Voltage Settings

VCHRG[2:0]

100

101

110

111

000

001

010

011 (default)

Charge Regulator Output Voltage (V)

3.800

4.100

4.150

4.200

4.250

4.300

4.375

4.450

The current loop is composed of the M1 and M2 as control elements, the external sense resistor, a programmable current limit, and an amplifier. The control loop will regulate the voltage drop over the external resistor. The value of the external resistor therefore is of influence on the charge current. The charge current is programmable by SPI through ICHRG[3:0] bits. Each setting corresponds to a common use case. Software controlled pulsed charging can be obtained by programming the current periodically to zero.

Table 63. Charge Path Regulator Current Limit Settings

Specific Use Case

Off

Standalone Charging Default for precharging, USB charging, and LPB

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0.0

80

240

320

400

480

560

640

720

800

880

960

1040

1200

1600

Fully On – M3

Open

Advised setting for USB charging with

PHY active

Standalone Charging Default

High Current Charger

High Current Charger

Externally Powered


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Table 64. Charge Path Regulator Characteristics

Parameter

Input Operating Voltage

Output voltage trimming accuracy

Output Voltage Spread

Current Limit Tolerance

(77)

Condition

CHRGRAW

VCHRG[2:0] = 011

Charge current 50 mA at T = 25 °C

VCHRG[2 :0] = 011, 1xx

Charge current 1.0 to 100 mA

Charge current > 100 mA and above

ICHRG[3:0] =0 001

ICHRG[3:0] = 0100

ICHRG[3:0] = 0110

All other settings

Min

BATTMIN

–

Start-up Overshoot

Configuration

Input Capacitance

Unloaded –

Load Capacitor

Cable Length

CHRGRAW

(78)

BPSNS

(79)

(78)

–

10

-

Notes

77.

Excludes spread and tolerances due to board routing and 100 mOhm sense resistor tolerances.

78.

An additional derating of 35% is allowed.

79.

This condition applies when using an external charger with a 3.0 m long cable.

-1.5

-3.0

68

360

500

–

Typ

–

–

2.2

–

–

400

560

–

–

–

80

–

Max

5.6

0.35

440

620

15

1.5

1.5

92

2.0

–

4.7

3.0

Units

V

% mA mA

%

%

% mA

%



F



F m

OVER-VOLTAGE PROTECTION

In order to protect the application, the voltage at the CHRGRAW pin is monitored. When crossing the threshold, the charge path regulator will be turned off immediately, by opening M1 and M2, while M3 gets closed. When the over-voltage condition disappears for longer than the debounce time, charging will resume and previously programmed SPI settings will be reloaded.

An interrupt CHGFAULTI is generated with associated CHGFAULTM mask bit with the CHGFAULTS[1:0] bits set to 01.

In order to ensure immediate protection, the control of M1, M2, and M3 occurs real-time, so asynchronously to the charger state machine. As a result, for over-voltage conditions of up to 30

 s, the charger state machine may not always end up in the over-voltage fault state, and therefore an interrupt may not always be generated.

Table 65. Charger Over-voltage Protection Characteristics

Parameter

Over-voltage Comparator High Voltage Threshold

Over-voltage Comparator Debounce Time

Condition

High to Low, Low to High

High to Low

Min

16

–

Typ

–

10

Max

20

–

Units

V ms

The VBUS pin is also protected against over-voltages. This will occur at much lower levels for CHRGRAW. When a VBUS over-voltage is detected the internal circuitry of the USB block is disconnected. A USBOVI is generated in this case. For more

details see Connectivity .

When the maximum voltage of the IC is exceeded, damage will occur to the IC and the state of M1 and M2 cannot be guaranteed. If the user wants to protect against these failure conditions, additional protection will be required.

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POWER DISSIPATION

Since the charge path operates in a linear fashion, the dissipation can be significant and care must be taken to ensure that the external pass FETs M1 and M2 are not over dissipating when charging. By default, the charge system will protect against this by a built-in power limitation circuit. This circuit will monitor the voltage drop between CHRGRAW and CHRGISNS, and the current through the external sense resistor connected between CHRGISNS and BPSNS. When required,.a duty cycle is applied to the M1 and M2 drivers and thus the charge current, in order to stay within the power budget. At the same time M3 is forced to conduct to keep the application powered. In case of excessive supply conditions, the power limiter minimum duty cycle may not be sufficiently small to maintain the actual power dissipation within budget. In that case, the charge path will be disabled and the

CHGFAULTI interrupt generated with the CHGFAULTS[1:0] bits set to 01.

The power budget can be programmed by SPI through the PLIM[1:0] bits. The power dissipation limiter can be disabled by setting the PLIMDIS bit. In this case, it is advised to use close software control to estimate the dissipated power in the external pass FETs. The power limiter is automatically disabled in serial path factory mode and in reverse mode.

Since a charger attachment can be a Turn-on event when a product is initially in the Off state, any non-default settings that are intended for PLIM[1:0] and PLIMDIS, should be programmed early in the configuration sequence, to ensure proper supply conditions adapted to the application. To avoid any false detection during power up, the power limiter output is blanked at the start of the charge cycle. As a safety precaution though, the power dissipation is monitored and the desired duty cycle is estimated. When this estimated duty cycle falls below the power limiter minimum duty cycle, the charger circuit will be disabled.

Table 66. Charger Power Dissipation Limiter Control

PLIM[1:0]

00 (default)

01

10

11

Power Limit (mW)

600

800

1000

1200

Table 67. Charger Power Dissipation Limiter Characteristics

Parameter

Power Limiter Accuracy

Power Limiter Control Period

Power Limiter Blanking Period

Power Limiter Minimum Duty Cycle

Condition

Up to 2x the power set by PLIM[1:0]

Upon charging enabling

Min

–

–

–

–

Typ

–

500

1500

10

Max

15

–

–

–

Units

% ms ms

%

REVERSE SUPPLY MODE

The battery voltage can be applied to an external accessory via the charge path, by setting the RVRSMODE bit high. The current through the accessory supply path is monitored via the charge path sense resistor R2, and can be read out via the ADC.

The accessory supply path is disabled and an interrupt CHGSHORTI is generated when the slow or fast threshold is crossed.

The reverse path is disabled when a current reversal occurs and an interrupt CHREVI is generated.

Table 68. Accessory Supply Main Characteristics

Parameter

Short-circuit Current Slow Threshold

Slow Threshold Debounce Time

Short-circuit Current Fast Threshold

Fast Threshold Debounce Time

Current Reversal Threshold

Condition

Current from Accessory

Min

500

–

–

–

–

Typ

–

1.0

–

100

CHGCURR

Max

–

–

1840

–

–

Units

mA ms mA

 s mA

INTERNAL TRICKLE CHARGE CURRENT SOURCE

An internal current source between BP and BATTISNS provides small currents to the battery in cases of trickle charging a dead battery. As can be seen under the description of the standalone charging, this source is activated by the charger state machine, and its current level is selected based on the battery voltage. The source can also be enabled in software controlled charging mode by setting the TREN bit. This source cannot be used in single path configurations because in that case,

BATTISNS and BP are shorted on the board.


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Table 69. Internal Trickle Charger Control

BATT

0 < BATT < BATTMIN

BATTMIN < BATT < BATTON

Trickle Charge Current (mA)

40

80

Table 70. Internal Trickle Charger Characteristics

Parameter

Trickle Charge Current Accuracy

Condition

Operating Voltage

Extended Operating Range

(80)

Notes

80.

The effective trickle current may be significantly reduced

BATTISNS

BP-BATTISNS

BP-BATTISNS

Min

–

0.0

1.0

0.3

Typ

–

–

–

–

Max

30

–

–

–

Units

V

V

%

V

CHARGER DETECTION AND COMPARATORS

The charger detection is based on three comparators. The “charger valid” monitors CHRGRAW, the “charger presence” that monitors the voltage drop between CHRGRAW and BPSNS, and the “CHGCURR” comparator that monitors the current through the sense resistor connected between CHRGISNS and BPSNS. A charger insertion is detected based on the charger presence comparator and the “charger valid” comparator both going high. For all but the lowest current setting, a charger removal is detected based on both the “charger presence” comparator going low and the charger current falling below CHGCURR. In addition, for the lowest current settings or if not charging, the “charger valid” comparator going low is an additional cause for charger removal detection. The table below summarizes the charger detection logic.

Table 71. Charger Detection

Setting ICHRG[3:0]

0000, 0001

Other Settings

Charger Valid

Comparator

1

X

0

1

X

X

Charger Presence

Comparator

1

0

X

0

1

X

CHGCURR Comparator

X

0

X

X

X

1

Charger Detected

No

No

Yes

No

Yes

Yes

In addition to the aforementioned comparators, three more comparators play a role in battery charging. These comparators are “BATTMIN”, which monitors BATT for the safe charging battery voltage, “BATTON”, which monitors BATT for the safe operating battery voltage, and “BATTCYCL”, which monitors BPSNS for the constant current to constant voltage transition. The

BATTMIN and BATTON comparators have a normal and a long (slow) debounced output. The slow output is used in some places in the charger flow to provide enough time to the battery protection circuit to reconnect the battery cell.

Table 72. Charger Detectors Main Characteristics

Parameter

BATTMIN Threshold

BATTON Threshold

BATTCYCL Threshold

Charger Presence

Charger Valid

CHGCURR Threshold

Condition

At BATT

At BATT

At BPSNS relative to VCHRG[2:0]

CHRGRAW-BPSNS

CHRGRAW

CHRGISNS-BPSNS, current from charger

Min

2.9

3.3

–

10

–

10

Typ

–

–

98

–

3.8

–

Max

3.1

3.5

–

50

–

50

Units

Volts

Volts

% mV

V mA

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Table 72. Charger Detectors Main Characteristics (continued)

Parameter

Debounce Period

Condition

BATTMIN, BATTON rising edge (normal

BATTMIN, BATTON rising edge (slow)

BATTMIN falling edge (slow)

BATTMIN falling edge (fast)

BATTCYCL dual edge

CHGCURR

Charger Detect dual edge

Min

–

–

–

–

–

–

–

Typ

32

1.0

1.0

1.0

100

1.0

100

Max

–

–

–

–

–

–

–

Units

ms s s s ms ms ms

Crossing the thresholds BATTCYCL and CHGCURR will generate the interrupts CCCVI and CHGCURRI respectively. These interrupts can be used as a simple way to implement a three-bar battery meter.

BATTERY THERMISTOR CHECK CIRCUITRY

A battery pack may be equipped with a thermistor, which value decreases over temperature (NTC). The relationship between temperature T (in Kelvin) and the thermistor value (RT) is well characterized and can be described as RT = R0*e^(B*(1/T-1/T0), with T0 being room temperature, R0 the thermistor value at T0 and B being the so called B-factor which indicates the slope of the thermistor over temperature. In order to read out the thermistor value, it is biased from GPO1 through a pull-up resistor R

PU

See also the ADC chapter. The battery thermistor check circuit compares the fraction of GPO1 at ADIN5 with two preset

.

thresholds, which correspond to 0 and 45 °C, see Table 73 . Charging is generally allowed when the thermistor is within the range,

see next section for details.

Table 73. Battery Thermistor Check Main Characteristics

Temperature Threshold

T

LOW

T

HIGH

Voltage at ADIN5

24/32 * GPO1

10/32 * GPO1

Corresponding Resistor Values

Rpu RT

10 k

10 k

30 k

4.5 k

Corresponding Temperature (in °C) *

B=3200 B=3500 B=3900

-3.0

+49

0.0

+46

+2.0

+44

CHARGE LED INDICATOR

Since normal LED control via the SPI bus is not always possible in the charging mode, an 8.0 mA max current sink is provided at the CHRGLED pin for an LED connected to CHRGRAW.

The LED will be activated when standalone charging is started, and will remain under control of the state machine also when the application is powered on. At the end of charge, the LED is automatically disabled. Through the CHRGLEDEN bit, the LED can be forced on. In software controlled charging, the LED is under full control of this CHRGLEDEN bit.

Table 74. Charge LED Drivers Main Characteristics

Parameter

Trickle LED current

Condition

CHRGLED = 2.5 V

CHRGLED = 0.7 V

Notes

81.

Above conditions represent respectively a USB and a collapsed charger case

Min

–

5.0

Typ

–

–

Max

8.0

–

Units

mA mA

Table 75. Charge LED Driver Control

CHRGLEDEN

0 (default)

1

CHRGLED

Auto

On


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CHARGER OPERATION

USB CHARGING

The USB VBUS line in this case, is used to provide a supply within the USB voltage limits and with at least 500 mA of current drive capability.

When trickle charging from the USB cable, it is important not to exceed the 100 mA, in case of a legacy USB bus. The appropriate charge current level ICHRG[2:0] = (0001) is 80 mA typical which accounts for the additional current through the charge LED indicator.

WALL CHARGING

No distinction can be made between a USB Host or a wall charger. Therefore, when attaching a wall charger, the CHRGSE1B pin must be forced low as a charger attach indicator. The CHRGSE1B pin has a built-in weak pull-up to VCORE. In the application, this pin is preferably pulled low, with for instance an NPN of which the base is pulled high through a resistor to

CHRGRAW. The state of the CHRGSE1B pin is reflected through the CHRGSE1BS bit. When CHRGSE1B changes state a

CHRGSE1BI is generated. No specific debounce is applied to the CHRGSE1B detector.

Table 76. Charger Detector Characteristics

Parameter

CHRGSE1B Pull-up

Logic Low

Logic High

Condition

To VCORE

Min

–

0.0

1.0

Typ

100

–

–

Max

–

0.3

VCORE

Units

kOhm

V

V

If an application is to support wall chargers and USB on separate connectors, it is advised to separate the VBUS and the

CHRGRAW on the PCB. For these applications, charging from USB is no longer possible. For proper operation, a 120 kOhm pull-down resistor should be placed at VBUS.

STANDALONE CHARGING

A standalone charge mode of operation is provided to minimize software interaction. It also allows for a completely discharged battery to be revived without processor control. This is especially important when charging from a USB host or when in single path configuration (M3 replaced by short, BATTFET floating). Since the default voltage and current setting of the charge path regulator may not be the optimum choice for a given application, these values can be reprogrammed through the SPI if the

CHGAUTOVIB bit is set. Note that the power limiter can be programmed independent of this bit being set.

Upon connecting a USB host to the application with a dead battery, the trickle cycle is started and the current set to the lowest charge current level (80 mA). When the battery voltage rises above the BATTON = 3.4 V threshold, a power up sequence is automatically initiated. The lowest charge current level remains selected until a higher charge current level is set through the SPI after negotiation with the USB host. In case of a power up failure, a second power up will not be initiated to avoid an ambulance mode, the charger circuitry will though continue to charge. The USB dead battery operation following the low-power boot scheme is described further in this chapter.

Upon connecting a charger to an application with a dead battery the behavior will be different for serial path and single path configurations.

In serial path (M3 present), the application will be powered up with the current through M1M2 set to 500 mA minimum. The internal trickle charge current source will be enabled, set to its lowest level (40 mA) up to BATTMIN, followed by the highest setting (80 mA). The internal trickle charge current is not programmable, but can be turned off by the SPI. In this mode, the voltage and current regulation to BP through the external pass devices M1M2 can be reprogrammed through the SPI. Once the battery is greater than BATTON, it will be connected to BP and further charged through M1/M2 at the same time as the application.

In single path (M3 replaced by a short, BATTFET floating), the battery (and therefore BP) is below the BPON threshold. This will be detected and the external charge path will be used to precharge the battery, up to BATTMIN at the lowest level (80 mA), and above at the 500 mA minimum level. Once exceeding BPON, a turn on event is generated and the voltage and current levels can be reprogrammed.

When in the serial path and upon initialization of the charger circuitry, and it appears BP stays below BPON, the application will not be powered up, and the same charging scheme is followed as for single path.

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The precharge will timeout and stop charging, in case it did not succeed in raising the battery to a high enough level: BATTON for internal precharge, external precharge in the case of USB, and BPON for the external precharge, in case of a charger. This is a fault condition and is flagged to the processor by the CHGFAULTI interrupt, and the CHGFAULTS[1:0] bits are set to 10.

The charging circuit will stop charging and generate a CHGCURRI interrupt after the battery is fully charged. This is detected by the charge current dropping below the CHGCURR limit. The charger automatically restarts if the battery voltage is below

BATTCYCL. Software can bypass this cyclic mode of operation by setting the CYCLB bit. Setting the bit does not prevent interrupts to be generated.

During charging, a charge timer is running. When expiring before the CHGCURR limit is reached, the charging will be stopped and an interrupt generated. The charge timer can be reset before it expires by setting the self clearing CHGTMRRST bit. After expiration, the charger needs to be restarted. Proper charge termination and restart is a relatively slow process. Therefore in both of the previous cases, the charging will rapidly resume, in case of a sudden battery bounce. This is detected by BP dropping below the BATTON threshold.

Out of any state and after a timeout, the charger state machine can be restarted by removing and reapplying the charger. A software restart can also be initiated by setting the self clearing CHGRESTART bit.

The state of the charger logic is reflected by means of the CHGENS bit. This bit is therefore a 1 in all states of the charger state machine, except when in a fault condition or when at the end of charge. In low-power boot mode, the bit is not set until the

ACKLPB bit is set. This also means that the CHGENS bit is not cleared when the power limiter interacts, or when the battery temperature is out of range. The charge LED At CHRGLED follows the state of the CHGENS bit with the exception that software can force the LED driver on.

The detection of a serial path versus a single path is reflected through the CHRGSSS bit. A logic 1 indicates a serial path. In cases of single path, the pin BATTFET must be left floating.

The charging circuit will stop charging, in case the die temperature of the IC exceeds the thermal protection threshold. The state machine will be re-initiated again when the temperature drops below this threshold.

Table 77. Charger Timer Characteristics

Parameter

Charger Timer

Precharge Timer

Condition

External precharge 80 mA

Internal precharge 40/80 mA

External precharge 400/560 mA

Min

–

–

–

Typ

120

270

60

Max

–

–

–

Units

min min min

Table 78. Charger Fault Conditions

Fault Condition

Cleared or no fault condition

Over-voltage at CHRGRAW

Excessive dissipation on M1/M2

Sudden battery drop below BATTMIN

Any charge timeout

Out of temperature

CHGFAULTS[1:0]

00

01

01

10

10

11

CHGFAULTI

Not generated

Rising edge

Rising edge

Rising edge

Rising edge

Dual edge

SOFTWARE CONTROLLED CHARGING

The charger can also be operated under software control. By setting CHGAUTOB = 1, full control of the charger settings is assumed by software. The state machine will no longer determine the mode of charging. The only exceptions to this are a charger removal, a charger over-voltage detection and excessive power dissipation in M1/M2.

For safety reasons, when a RESETB occurs, the software controlled charging mode is exited for the standalone charging operation mode.

In the software controlled charging mode, the internal trickle charger settings can be controlled as well as the M3 operation through FETCTRL (1 = conducting). The latter is only possible if the FETOVRD bit is set. If a sudden drop in BP occurs (BP <

BPON) while M3 is open, the charger control logic will immediately close M3 under the condition that BATT > BATTMIN.


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FACTORY MODE

In factory mode, power is provided to the application with no battery present. It is not a situation which should occur in the field.

The factory mode is differentiated from a USB Host by, in addition to a valid VBUS, a UID being pulled high to the VBUS level

during the attach, see Connectivity .

In case of a serial path (M3 present), the application will be powered up with M1M2 fully on. The M3 is opened (non conducting) to a separate BP from BATT. However, the internal trickle charge current source is not enabled. All the charger timers as well as the power limiter are disabled.

In case of a single path (M3 replaced by a short, BATTFET floating), the behavior is similar to a normal charging case. The application will power up and the charge current is set to the 500 mA minimum level. All the internal timers and pre-charger timers are enabled, while only the charger timer and power limiter function are disabled.

In both cases, by setting the CHGAUTOVIB bit, the charge voltage and currents can be programmed. When setting the

CHGAUTOB bit the factory mode is exited.

USB LOW-POWER BOOT

USB low-power boot allows the application to boot with a dead battery within the 100 mA USB budget until the processor has negotiated for the full current capability. This mode expedites the charging of the dead battery and allows the software to bring up the LCD display screen with the message “Charging battery”. This is enabled on the IC by hardwiring the MODE pin on the

PCB board, as shown in Table 79 .

Table 79. MODE Pin Programming

MODE Pin State

Ground

VCOREDIG

Mode

Normal Operation

Low-power Boot Allowed

Below are the steps required for USB low-power booting:

1. First step: detect a potential low-power boot condition, and qualify if it is enabled.

a) VBUS present and not in Factory Mode (either via a wall charger or USB host, since the IC has no knowledge of what kind of device is connected) b) BP<BPON (full power boot if BP>BPON) c) Board level enabling of LPB with MODE pin hardwired to VCOREDIG d) M3 included in charger system (Serial path charging, not Single). If all of these are true, then LPBS=1 and the system will proceed with LPB sequence. If any are false, LPBS = 0.

2. If LPBS = 0, then a normal booting of the system will take place as follows: a) MODE = GND. The INT pin should behave normally, i.e. can go high during Watchdog phase based on any unmasked interrupt. If BP>BATTON, the application will turn on. If BP < BATTON, the PMIC will default to trickle charge mode and a turn on event will occur when the battery is charged above the BATTON threshold. The processor does not support a low-power boot mode, so it powers up normally.

b) MODE = VCOREDIG. When coming from Cold Start the INT is kept low throughout the watchdog phase. The processor detects this and will boot normally. The INT behavior is becomes 'normal' when entering On mode, and also when entering watchdog phase from warm start.

3. If LPBS = 1, then the system will boot in low-power as follows: a) Cold Start is initiated in a “current starved bring-up” limited by the charger system's DAC step ICHRG[3:0] = 0001 to stay within 100 mA USB budget. The startup sequence and defaults as defined in the startup table will be followed.

Since VBUS is present the USB supplies will be enabled. The charge LED driver is maintained off.

b) After the power up sequence, but before entering Watchdog phase, thus releasing the reset lines, the charger DAC current is stepped up to ICHRG[3:0] = 0100. This is in advance of negotiation and the application has to ensure that the total loading stays below the un-negotiated 100 mA limit.

c) The INT pin is made high before entering watchdog phase and releasing RESETBMCU. All other interrupts are held off during the watchdog phase. The processor detects this and starts up in a Low-power mode at low clock speed.

d) The application processor will enable the PHY in serial FS mode for enumeration.

e) If the enumeration fails to get the stepped up current, the processor will bring WDI low. The power tree is shut down, and the charging system will revert to trickle recovery, LPBS reset to 0. (or any subsequent failure: WDI = 0). Also if

RESETB transitions to 0 while in LPB (i.e., if BP loading misbehaves and causes a UVDET for example), the system will transition to USB trickle recover, LPBS reset to 0.

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f) If the enumeration is successful to get the stepped up current the processor will hold WDI high and continues with the booting procedure.

• When the SPI is activated, the LPB interrupt LPBI can be cleared; other unmasked interrupts may now become active.

When leaving watchdog phase for the On mode, the interrupts will work 'normally' even if LPBI is not cleared.

• The SPI bit ACKLPB bit is set to enable the internal trickle charger. The charge LED gets activated. When the battery crosses the BATTMIN threshold the M3.transistor is automatically closed and the battery is charged with the current not taken by the application.

• When BP exceeds BPON, the charger state machine will successfully exit the trickle charge mode. This will make

LPBS = 0 which generates a LPBI. This interrupt will inform the processor that a full turn on is allowed. Once this happens the application code is allowed to run full speed.

BATTERY THERMISTOR CHECK OPERATION

By default, the battery thermistor value is taken into account for charging the battery. Upon detection of a supply at

CHRGRAW, the core circuitry powers up including VCORE. As soon as VCORE is ready, the output GPO1 is made active high, independently of the state of GPO1EN bit. The resulting voltage at ADIN5 is compared to the corresponding temperature thresholds. If the voltage at ADIN5 is within range, the charging will behave as described thus far, however if out of range the charger state machine will go to a wait state, pause the charge timers, and no current will be sourced to the battery. When the temperature comes back in range, charging is continued again. The actual behavior depends on the configuration the charger circuitry at the moment the temperature range is exceeded.

Table 80. Battery Thermistor Check Charger States

Configuration

Internal precharging on a charger

Internal precharging on USB in USB

Low-power Boot

All other non fault charging modes and configurations

State for temperature out of range

M1M2 = 560 mA / SPI setting,

M3 = Open, Itrickle = 0mA

M1M2 = 400 mA

M3 = Open, Itrickle = 0mA

M1M2 = 0 mA

M3 Closed

State for temperature back in range

ICin “On” State IC in “Off” State

Internal precharge Initialization

Low-power Boot Precharge

Initialization

Initialization

Initialization

The battery thermistor check can be disabled by setting the THCHKB bit. This is useful in applications where battery packs without thermistor may be used. This bit defaults to '0', which means that initial power up only can be achieved with an already charged battery pack or on a charger, but not on a USB Host without low-power boot support. Alternatively, one can bias ADIN5 to get within the temperature window. Setting the SPI bit to disable the thermistor check will also inhibit the automatic enabling of the GPO1 output. The GPO1 output still remains controllable through GPO1EN. As an additional feature, the charger state machine will end up in an out of temperature state when the die temperature is below -20 °C, independent of the setting of the

THCHKB bit.

Notes

:

When using the battery charger as the only source of power, as in a battery-less application, the following precautions should be observed:

• It is still necessary to connect ADIN5 to either VCOREDIG or a midpoint of a divider from GPIO1 to ground since the battery charger still interprets this voltage as the battery pack thermistor by default.

• The charger state machine ends up in an out of temperature state when the die temperature is below -20 °C. The battery charger path, thus, must not be used in battery-less applications expected to operate below -20 °C.

• Very careful budgeting of the total current consumption and voltage standoff from CHRGRAW to BPSNS must be made, since the power limiter is operational by default, and a battery less system won't have a source of current if the power dissipation limit is reached.

• If operating from a USB host the unit load limit (100 mA max.) must still be observed.

• If operating from a “wall charger”, and if there is no battery, there is an period of approximately 85 ms after RESETB is released, but before the current limit is set to a nominal 560 mA. If the total current demand is greater than this limit, the voltage may collapse and RESETB may pulse a few times (depending in part in the system load and dependence on

RESETB.) Therefore, at the end of this time, RESETB may or may not be active. It may be necessary to use one of the other turn on events (such as PWRONx) to turn it back on.


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ADC SUBSYSTEM

ADC SUBSYSTEM

CONVERTER CORE

The ADC core is a 10-bit converter. The ADC core and logic run on 2/3 of the switcher PLL generated frequency, so approximately 2.0 MHz. If an ADC conversion is requested while the PLL was not active, it will automatically be enabled by the

ADC. A 32.768 kHz equivalent time base is derived from this to the ADC time events. The ADC is supplied from VCORE. The

ADC core has an integrated auto calibration circuit which reduces the offset and gain errors.

The switcher PLL is programmable, see Supplies . When the switcher frequency is changed, the frequency applied to the ADC

converter will change accordingly. Although the conversion time is inversely proportional to the PLLX[2:0] setting, this will not influence the ADC performance. The locally derived 32.768 kHz will remain constant in order not to influence the different timings depending on this time base.

INPUT SELECTOR

The ADC has 8 input channels.

Table 81

gives an overview of the attributes of the A to D channels.

Table 81. ADC Inputs

Channel

0

ADA1[2:0]

ADA2[2:0]

000

1 001

2 010

Signal read

Battery Voltage (BATT)

Battery Current

(BATT-BATTISNSCC)

Application Supply (BPSNS)

Input Level

0 – 4.8 V

-60 mV – 60 mV

(82)

Scaling

/2 x20

0 – 4.8 V

0 – 12 V

0 – 20 V

-300 mV – 300 mV

(83)

/2

/5

/10 x4

3 011

Charger Voltage (CHRGRAW)

4

5

6

7

100

101

110

111

Charger Current

(CHRGISNS-BPSNS)

General Purpose ADIN5

(Battery Pack Thermistor)


Backup Voltage (LICELL)

General Purpose ADIN7/ADIN7B


General Purpose ADIN7B

Die Temperature

UID

Notes

82.

Equivalent to -3.0 to +3.0 A of current with a 20 mOhm sense resistor

83.

Equivalent to -3.0 to +3.0 A of current with a 100 mOhm sense resistor

0 – 2.4 V

0 – 2.4 V

0 – 3.6 V

0 – 2.4 V

0 – BP

0 – VIOHI

–

0 – 4.8 V x1

/2

–

/2 x1 x2/3 x1

/2

Scaled Version

0 – 2.4 V

-1.2 – 1.2 V

0 – 2.4 V

0 – 2.4 V

0 – 2.4 V

-1.2 – 1.2 V

0 – 2.4 V

0 – 2.4 V

0 – 2.4 V

0 – 2.4 V

0 – 2.4 V

0 – 1.4 V

1.2 – 2.4 V

0 – 2.4 V

The above table is valid when setting the bit ADSEL = 0 (default). If setting the bit to a 1, the touch screen interface related inputs are mapped on the ADC channels 4 to 7 and channels 0 to 3 become unused. For more details see the touch screen interface section.

Some of the internal signals are first scaled to adapt the signal range to the input range of the ADC. The charge current and the battery current are indirectly read out by the voltage drop over the resistor in the charge path and battery path respectively.

For details on scaling see the dedicated readings section.

In case the source impedance is not sufficiently low on the directly accessible inputs ADIN5, ADIN6, ADIN7, and the muxed

GPO4 path, an on chip buffer can be activated through the BUFFEN bit. If this bit is set, the buffer will be active on these specific inputs during an active conversion. Outside of the conversions the buffer is automatically disabled. The buffer will add some offset, but will not impact INL and DNL numbers except for input voltages close to zero.

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Table 82. ADC Input Specification

Parameter

Source Impedance

Input Buffer Offset

Input Buffer Input Range

Condition

No bypass capacitor at input

Bypass capacitor at input 10 nF

BUFFEN = 1

BUFFEN = 1

Min

–

–

-5.0

0.02

Typ

–

–

–

–

Max

5.0

30

5.0

2.4

Units

kOhm kOhm mV

V

When considerably exceeding the maximum input of the ADC at the scaled or unscaled inputs, the reading result will return a full scale. It has to be noted that this full scale does not necessarily yield a 1023 DEC reading, due to the offsets and calibration applied. The same applies for when going below the minimum input where the corresponding 0000 DEC reading may not be returned.

CONTROL

The ADC parameters are programmed by the processors via the SPI. Up to two ADC requests can be queued, and locally these requests are arbitrated and executed. When a conversion is finished, an interrupt ADCDONEI is generated. The interrupt can be masked with the ADCDONEM bit.

The ADC can start a series of conversions by a rising edge on the ADTRIG pin or through the SPI programming by setting the

ASC bit. The ASC bit will self clear once the conversions are completed. A rising edge on the ADTRIG pin will automatically make the ASC bit high during the conversions.

When started, always eight conversions will take place; either 1 for each channel (multiple channel mode, RAND = 0) or eight times the same channel (single channel mode, bit RAND = 1). In single channel mode, the to be converted channel needs to be selected with the ADA1[2:0] setting. This setting is not taken into account in multiple channel mode.

In order to perform an auto calibration cycle, a series of ADC conversions is started with ADCCAL = 1. The ADCCAL bit is cleared automatically at the end of the conversions and an ADCDONEI interrupt is generated. The calibration only needs to be performed before a first utilization of the ADC after a cold start.

The conversion will begin after a small synchronization error of a few microseconds plus a programmable delay from 1 (default) to 256 times the 32 kHz equivalent time base by programming the bits ATO[7:0]. This delay cannot be programmed to 0 times the 32 kHz in order to allow the ADC core to be initialized during the first 32 kHz clock cycle. The ATO delay can also be included between each of the conversions by setting the ATOX bit.

Once a series of eight A/D conversions is complete, they are stored in a set of eight internal registers and the values can be read out by software (except when having done an auto calibration cycle). In order to accomplish this, the software must set the

ADA1[2:0] and ADA2[2:0] address bits to indicate which values will be read out. This is set up by two sets of addressing bits to allow any two readings to be read out from the 8 internal registers. For example, if it is desired to read the conversion values stored in addresses 2 and 6, the software will need to set ADA1[2:0] to 010 and ADA2[2:0] to 110. A SPI read of the A/D result register will return the values of the conversions indexed by ADA1[2:0] and ADA2[2:0]. ADD1[9:0] will contain the value indexed by ADA1[2:0], and ADD2[9:0] will contain the conversion value indexed by ADA2[2:0].

An additional feature allows for automatic incrementing of the ADA1[2:0] and ADA2[2:0] addressing bits. This is enabled with bits ADINC1 and ADINC2. When these bits are set, the ADA1[2:0] and ADA2[2:0] addressing bits will automatically increment during subsequent readings of the A/D result register. This allows for rapid reading of the A/D results registers with a minimum of SPI transactions.

The ADC core can be reset by setting the self clearing ADRESET bit. As a result the internal data and settings will be reset but the SPI programming or readout results will not. To restart a new ADC conversion after a reset, all ADC SPI control settings should therefore be reprogrammed.


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ADC SUBSYSTEM

DEDICATED READINGS

CHANNEL 0 BATTERY VOLTAGE

The battery voltage is read at the BATT pin at channel 0. The battery voltage is first scaled as V(BATT)/2 in order to fit the input range of the ADC.

Table 83. Battery Voltage Reading Coding

Conversion Code ADDn[9:0]

Voltage at input ADC in V

1 111 111 111

1 000 010 100

0 000 000 000

2.400

1.250

0.000

Voltage at

BATT in V

4.800

2.500

0.000

CHANNEL 1 BATTERY CURRENT

The current flowing out of and into the battery can be read via the ADC, by monitoring the voltage drop over the sense resistor between BATT and BATTISNSCC. This function is enabled by setting BATTICON = 1.

The battery current can be read either in multiple channel mode or in single channel mode. In both cases, the battery terminal voltage at BATT, and the voltage difference between BATT and BATTISNS, are sampled simultaneously but converted one after the other. This is done to effectively perform the voltage and current reading at the same time. In multiple channel mode, the converted values are read at the assigned channel. In single channel mode and ADA1[2:0] = 001, the converted result is

available in 4 pairs of battery voltage and current reading as shown in Table 84 .

Table 84. Battery Current Reading Sequence

ADC Trigger

6

7

4

5

2

3

0

1

Signals Sampled

BATT, BATT – BATTISNSCC

–


–


–


–

BATT

Signal Converted

BATT – BATTISNSCC

BATT

BATT – BATTISNSCC

BATT

BATT – BATTISNSCC

BATT

BATT – BATTISNSCC

Readout

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Contents

BATT

BATT – BATTISNSCC

BATT

BATT – BATTISNSCC

BATT

BATT – BATTISNSCC

BATT

BATT – BATTISNSCC

If the BATTICON bit is not set, the ADC will return a 0 reading for channel 1.

The voltage difference between BATT and BATTISNS is first amplified to fit the ADC input range as V(BATT-BATTISNS)*20.

Since battery current can flow in both directions, the conversion is read out in 2's complement format. Positive readings correspond to the current flow out of the battery, and negative readings to the current flowing into the battery.

Table 85. Battery Current Reading Coding

Conversion Code,

ADDn[9:0]

0 111 111 111

0 000 000 001

0 000 000 000

1 111 111 111

1 000 000 000

Voltage at Input, ADC in mV

1200.00

2.346

0.0

-2.346

-1200.00

BATT – BATTISNS in mV

60

0.117

0.0

-0.117

-60

Current through

20 mOhm in mA

3000

5.865

0.0

5.865

3000

Current Flow

From battery

From battery

–

To battery

To battery

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The value of the sense resistor used, determines the accuracy of the result as well as the available conversion range. Note that excessively high values can impact the operating life of the device due to extra voltage drop across the sense resistor.

Table 86. Battery Current Reading Specification


Amplifier Gain

Amplifier Offset

Sense Resistor

Min

19

-2.0

–

Typ

20

–

20

Max

21

2.0

–

Units

mV mOhm

CHANNEL 2 APPLICATION SUPPLY

The application supply voltage is read at the BP pin at channel 2. The battery voltage is first scaled as V(BP)/2 in order to fit the input range of the ADC.

Table 87. Application Supply Voltage Reading Coding

Conversion Code

ADDn[9:0]

1 111 111 111

1 000 010 101

0 000 000 000

Voltage at input

ADC in V

2.400

1.250

0.000

Voltage at BP in V

4.800

2.500

0.000

CHANNEL 3 CHARGER VOLTAGE

The charger voltage is measured at the CHRGRAW pin at channel 3. The charger voltage is first scaled in order to fit the input range of the ADC. If the CHRGRAWDIV bit is set to a 1 (default), then the scaling factor is a divide by 5, when set to a 0 a divide by 10.

Table 88. Charger Voltage Reading Coding

Conversion Code

ADDn[9:0]

1 101 010 100

0 000 000 000


ADC in V

2.000

0.000

Voltage at CHGRAW in V,

CHRGRAWDIV = 0

20.000

0.000

Voltage at CHGRAW in V,

CHRGRAWDIV = 1

10.000

0.000

CHANNEL 4 CHARGER CURRENT

The charge current is read by monitoring the voltage drop over the charge current sense resistor. This resistor is connected between CHRGISNS and BPSNS. The voltage difference is first amplified to fit the ADC input range as V(CHRGISNS-BPSNS)*4.

The conversion is read out in a 2's complement format, see

Table 89 . The positive reading corresponds to the current flow from

charger to battery, the negative reading to the current flowing into the charger terminal. Unlike the battery current and voltage readings, the charger current readings are not interleaved with the charger voltage readings, so when RAND = 1 a total of 8 readings are executed. The conversion circuit is enabled by setting the CHRGICON bit to a one. If the CHRGICON bit is not set, the ADC will return a 0 reading for channel 4.

Table 89. Charge Current Reading Coding

Conversion Code

ADDn[9:0]

0 111 111 111

0 000 000 001

0 000 000 000

1 111 111 111

1 000 000 000


ADC in mV

1200

2.4

0.0

-2.346

-1200

CHRGISNS – BPSNS in mV

300.0

0.586

0.0

-0.586

-300.0

Current through

100 mOhm in mA

3000

5.865

0.0

5.865

3000

Current Flow

To application/battery

To application/battery

-

To charger connection

To charger connection

The value of the sense resistor used determines not only the accuracy of the result as well as the available conversion range, but also the charge current levels. It is therefore advised not to select another value than 100 mOhm.


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ADC SUBSYSTEM

CHANNEL 5 ADIN5 AND BATTERY THERMISTOR AND BATTERY DETECT

On channel 5, ADIN5 may be used as a general purpose unscaled input, but in a typical application, ADIN5 is used to read out the battery pack thermistor. The thermistor will have to be biased with an external pull-up to a voltage rail greater than the

ADC input range. In order to save current when the thermistor reading is not required, it can be biased from one of the general purpose IO's such as GPO1. A resistor divider network should assure the resulting voltage falls within the ADC input range in particular when the thermistor check function is used, see

Battery Thermistor Check Circuitry .

When the application is on and supplied by the charger, a battery removal can be detected by a battery thermistor presence check. When the thermistor terminal becomes high-impedance, the battery is considered being removed. This detection function is available at the ADIN5 input and can be enabled by setting the BATTDETEN bit. The voltage at ADIN5 is compared to the output voltage of the GPO1 driver, and when the voltage exceeds the battery removal detect threshold, the sense bit

BATTDETBS is made high and after a debounce the BATTDETBI interrupt is generated.

Table 90. Battery Removal Detect Specification

Parameter

Battery Removal Detect Threshold

(84)

Condition

Notes

84.

This is equivalent to a 10 kOhm pull-up and a 10 kOhm thermistor at -35 °C.

Min

–

Typ

31/32 * GPO1

Max

–

Units

V

CHANNEL 6 ADIN6 AND COIN CELL VOLTAGE

On channel 6, ADIN6 may be used as a general purpose unscaled input.

In addition, on channel 6, the voltage of the coin cell connected to the LICELL pin can be read (LICON=1). Since the voltage range of the coin cell exceeds the input voltage range of the ADC, the LICELL voltage is first scaled as V(LICELL)*2/3. In case the voltage at LICELL drops below the coin cell disconnect threshold (see

Clock Generation and Real Time Clock

), the voltage at LICELL can still be read through the ADC.

Table 91. Coin Cell Voltage Reading Coding

Conversion Code

ADDn[9:0]

Voltage at ADC input (V)

1 111 111 111

1 000 000 000

0 000 000 000

2.400

1.200

0.000

Voltage at LICELL (V)

3.6

1.8

0.0

CHANNEL 7 ADIN7 AND ADIN7B, UID AND DIE TEMPERATURE

On channel 7, ADIN7 may be used as a general purpose unscaled input (ADIN7DIV = 0) or as a divide by 2 scaled input

(ADIN7DIV = 1). The latter allows converting signals that are up to twice the ADC converter core input range. In a typical application, an ambient light sensor is connected here.

A second general purpose input ADIN7B is available on channel 7. This input is muxed on the GPO4 pin. The input voltage can be scaled by setting the ADIN7DIV bit. In the application, a second ambient light sensor is supposed to be connected here.

Note that the GPO4 will have to be configured to allow for the proper routing of GPO4 to the ADC, see General Purpose Outputs

.

In addition, on channel 7, the voltage of the USB ID line connected to the UID pin can be read. Since the voltage range of the

ID line exceeds the input voltage range of the ADC, the UID voltage is first scaled as V(UID)/2.

Table 92. UID Voltage Reading Coding

Conversion Code

ADDn[9:0]

Voltage at ADC input (V)

1 111 111 111

0 000 000 000

2.400

0.000

Voltage at UID (V)

4.80 - 5.25

0.0

Also on channel 7, the die temperature can be read out. The relation between the read out code and temperature is given in

Table 93

.

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ADC SUBSYSTEM

Table 93. Die Temperature Voltage Reading

Parameter

Die Temperature Read Out Code at 25 °C

Temperature change per LSB

Slope error

Minimum

–

–

–

Typical

680

+0.4244 °C

–

Maximum

–

–

5.0

Unit

Decimal

°C/LSB

%

Table 94. ADC Channel 7 Scaling Selection

ADIN7DIV

x x

0

1

0

1

ADIN7SEL1

0

1

0

0

1

1

ADIN7SEL0

1

0

0

0

1

1

Channel 7 Routing and Scaling

General purpose input ADIN7, Scaling = 1

General purpose input ADIN7, Scaling = 1 / 2

Die temperature

UID pin voltage, Scaling = 1 / 2

General purpose input ADIN7B, Scaling = 1

General purpose input ADIN7B, Scaling = 1 / 2

ADC ARBITRATION

The ADC converter and its control is based on a single ADC converter core with the possibility to store two requests, and to store both their results as shown in

Figure 27

. This allows two independent pieces of software to perform ADC requests.

Figure 27. ADC Request Handling

The programming for the two requests, the one to the 'ADC' and to the 'ADC BIS', uses the same SPI registers. The write access to the control of 'ADC BIS' is handled via the ADCBISn bits located at bit position 23 of the ADC control registers, which functions as an extended address bit. By setting this bit to a 1, the control bits which follow are destined for the 'ADC BIS'.

ADCBISn will always read back 0 and there is no read access to the control bits related to 'ADC BIS'. The read results from the

'ADC' and 'ADC BIS' conversions are available in two separate registers.

The following diagram schematically shows how the ADC control and result registers are set-up.





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ADC SUBSYSTEM

8 Bit Address Header 24 Bit Data

Location

43

ADC Control

Register 0

Location

44

ADC Control

Register 1

Location

45

ADC Result

Register ADC0

Location

46

ADC Control

Register 2

R/W

Bit

R/W

Bit

R/W

Bit

Address

Bits

Address

Bits

Address

Bits

Null

Bit

ADC

BIS0

Null

Bit

ADC

BIS1

Null

Bit

ADC Control

Bits

ADC Control

Bits

ADC Result

Bits

R/W

Bit

Address

Bits

Null

Bit

ADC

BIS2

ADC Control

Bits

Location

47

ADC Result

Register ADC1

R/W

Bit

Address

Bits

Null

Bit

ADC BIS Result

Bits

Figure 28. ADC Register Set for ADC BIS Access

There are two interrupts available to inform the processor when the ADC has finished its conversions, one for the standard

ADC conversion ADCDONEI, and one for the ADCBIS conversion ADCBISDONEI. These interrupts will go high after the conversion, and can be masked.

When two requests are queued, the request for which the trigger event occurs the first will be converted the first. During the conversion of the first request, an ADTRIG trigger event of the other request is ignored, if for the other request the TRIGMASK bit was set to 1. When this bit is set to 0, the other request ADTRIG trigger event is memorized, and the conversion will take place directly after the conversions of the first request are finished.

The following diagram shows the influence of the TRIGMASK bit. The TRIGMASK bit is particularly of use when an ADC conversion has to be lined up to a periodically ADTRIG initiated conversion. In case of ASC initiated conversions, the TRIGMASK bit is of no influence.

Figure 29. TRIGMASK Functional Diagram

To avoid results of previous conversions getting overwritten by a periodical ADTRIG signal, a single shot function is enabled by setting the ADONESHOT bit to a one. In that case, only at the first following conversion, an ADTRIG trigger event is accepted.

ASC events are not affected by this setting. Before performing a new single shot conversion, the ADONESHOT bit first needs to be cleared. Note that this bit is available for each of the conversion requests 'ADC' or 'ADC BIS', so can be set independently.

It is possible to queue two ADTRIG triggered conversions. Both conversions will be executed with a priority based on the

TRIGMASK setting. If both conversion requests have identical TRIGMASK settings, priority is given to the 'ADC' conversion over the 'ADC BIS' conversion. Note that the ADONESHOT is also taken into account.

To avoid that the ADTRIG input inadvertently triggers a conversion, the ADTRIGIGN bit can be set which will ignore any transition on the ADTRIG pin. The ADC completely ignores either ADTRIG or ASC pulses while ADEN is low. When reading conversion results, it is preferable to make ADEN = 0.

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ADC SUBSYSTEM

TOUCH SCREEN INTERFACE

The touch screen interface provides all circuitry required for the readout of a 4-wire resistive touch screen. The touch screen

X plate is connected to TSX1 and TSX2 while the Y plate is connected to TSY1 and TSY2. A local supply TSREF will serve as a reference. Several readout possibilities are offered.

In order to use the ADC inputs and properly convert and readout the values, the bit ADSEL should be set to a 1. This is valid for touch screen readings as well as for general purpose reading on the same inputs.

The touch screen operating modes are configured via the TSMOD[2:0] bits show in the following table.

Table 95. Touch Screen Operating Mode

TSMOD2

x

0

TSMOD1

0

0

TSMOD0

0

1

Mode

Inactive

Interrupt

Reserved

1

0

0

1

1 x

1 1 x

Touch Screen

Reserved

Description

Inputs TSX1, TSX2, TSY1, TSY2 can be used as general purpose ADC inputs

Interrupt detection is active. Generates an interrupt TSI when plates make contact. TSI is dual edge sensitive and 30 ms debounced

Reserved for a different interrupt mode

ADC will control a sequential reading of 2 times a XY coordinate pair and 2 times a contact resistance

Reserved for a different reading mode

In inactive mode, the inputs TSX1, TSX2, TSY1, and TSY2 can be used as general purpose inputs. They are respectively mapped on ADC channels 4, 5, 6, and 7.

In interrupt mode, a voltage is applied to the X-plate (TSX2) via a weak current source to VCORE, while the Y-plate is connected to ground (TSY1). When the two plates make contact both will be at a low potential. This will generate a pen interrupt to the processor. This detection does not make use of the ADC core or the TSREF regulator, so both can remain disabled.

In touch screen mode, the XY coordinate pairs and the contact resistance are read.

The X-coordinate is determined by applying TSREF over the TSX1 and TSX2 pins while performing a high-impedance reading on the Y-plate through TSY1. The Y coordinate is determined by applying TSREF between TSY1 and TSY2, while reading the

TSX1 pin.

The contact resistance is measured by applying a known current into the TSY1 terminal of the touch screen and through the terminal TSX2, which is grounded. The voltage difference between the two remaining terminals TSY2 and TSX1 is measured by the ADC, and equals the voltage across the contact resistance. Measuring the contact resistance helps in determining if the touch screen is touched with a finger or stylus.

To perform touch screen readings, the processor will have to select the touch screen mode, program the delay between the conversions via the ATO and ATOX settings, trigger the ADC via one of the trigger sources, wait for an interrupt indicating the conversion is done, and then read out the data. In order to reduce the interrupt rate and to allow for easier noise rejection, the touch screen readings are repeated in the readout sequence.

Table 96. Touch Screen Reading Sequence

ADC Conversion

6

7

4

5

2

3

0

1

Signals sampled

Readout Address

(85)

X position

X position

Dummy

Y position

Y position

Dummy

Contact resistance

Contact resistance

000

001

010

011

100

101

110

111

Notes

85.

Address as indicated by ADA1[2:0] and ADA2[2:0]

The dummy conversion inserted between the different readings is to allow the references in the system to be pre-biased for the change in touch screen plate polarity and will read out as '0'.





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ADC SUBSYSTEM

Figure 30

shows how the ATO and ATOX settings determine the readout sequence. The ATO should be set long enough so that the touch screen can be biased properly before conversions start.

Touchscreen Readout for ATOX=0

1/32K ATO+1 ATO+1 ATO+1

Trigger

Touchscreen

Polarization

Touchscreen Readout for ATOX=1

1/32K ATO+1

Conversions

0, 1, 2

End of Conversion 2

New Touchscreen

Polarization

Conversions

3, 4, 5

End of Conversion 5

New Touchscreen

Polarization

Conversions

6, 7

End of Conversion 7

Touchscreen

De-Polarization

ATO+1 ATO+1 ATO+1 Etc.

Trigger

Touchscreen

Polarization

Conversion 0 Conversion 1 Conversion 2 Conversion 3

End of Conversion 2

New Touchscreen

Polarization

Figure 30. Touch Screen Reading Timing

The main resistive touch screen panel characteristics are listed in

Table 5 . The switch matrix and readout scheme is designed

such that the on chip switch resistances are of no influence on the overall readout. The readout scheme however does not account for contact resistances as present in the touch screen connectors. Therefore, the touch screen readings will have to be calibrated by the user or in the factory where one has to point with a stylus the opposite corners of the screen.

When reading out the X-coordinate, the 10-bit ADC reading represents a 10-bit coordinate with '0' for a coordinate equal to

TSX2, and full scale '1023' when equal to TSX1. When reading out the Y-coordinate, the 10-bit ADC reading represents a 10-bit coordinate with '0' for a coordinate equal to TSY2, and full scale '1023' when equal to TSY1. When reading the contact resistance the 10-bit ADC reading represents the voltage drop over the contact resistance created by the known current source multiplied by two.

Table 97. Touchscreen Interface Characteristics

Parameter

Interrupt Threshold for Pressure Application

Interrupt Threshold for Pressure Removal

Current Source Inaccuracy

Condition

Over-temperature

Min

40

60

–

Typ

50

80

–

Max

60

95

20

Unit

kOhm kOhm

%

The reference for the touch screen is TSREF and is powered from VCORE. In touch screen operation, TSREF is a dedicated regulator. No other loads than the touch screen should be connected here. When the ADC performs non touch screen conversions, the ADC does not rely on TSREF and the reference can be disabled. In applications not supporting touch screen at all, the TSREF can be used as a low current general purpose regulator, or it can be kept disabled and the bypass capacitor omitted. The operating mode of TSREF can be controlled with the TSREFEN bit in the same way as some other general purpose

regulators are controlled, see Linear Regulators .

COULOMB COUNTER

As indicated earlier on in this Section, the current into and from the battery can be read out through the general purpose ADC as a voltage drop over the R1 sense resistor. Together with battery voltage reading, the battery capacity can be estimated. A more accurate battery capacity estimation can be obtained by using the integrated Coulomb Counter.

The Coulomb Counter (or CC) monitors the current flowing in/out of the battery by integrating the voltage drop across the battery current sense resistor R1, followed by an A to D conversion. The result of the A to D conversion is used to increase/ decrease the contents of a counter that can be read out by software. This function will require a 10



F output capacitor to perform

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ADC SUBSYSTEM

a first order filtering of the signal across R1. Due to the sampling of the A to D converter and the filtering applied, the longer the software waits before retrieving the information from the CC, the higher the accuracy. The capacitor will be connected between

the pins CFP and CFM, see Figure 31 .

Figure 31. Coulomb Counter Block Diagram

The CC results are available in the 2's complement CCOUT[15:0] counter. This counter is preferably reflecting 1 Coulomb per

LSB. As a reminder, 1 Coulomb is the equivalent of 1 Ampere during 1 second, so a current of 20 mA during 1 hour is equivalent to 72C. However, since the resolution of the A to D converter is much finer than 1C, the internal counts are first to be rescaled.

This can be done by setting the ONEC[14:0] bits. The CCOUT[15:0] counter is then increased by 1 with every ONEC[14:0] counts of the A to D converter. For example, ONEC[14:0] = 000 1010 0011 1101 BIN = 2621 DEC yields 1C count per LSB of

CCOUT[15:0] with R1 = 20 mOhm.

The CC can be reset by setting the RSTCC bit. This will reset the digital blocks of the CC and will clear the CCOUT[15:0] counter. The RSTCC bit gets automatically cleared at the end of the reset period which may take up to 40

 s. The CC is started by setting the STARTCC bit. The CC is disabled by setting this bit low again. This will not reset the CC settings nor its counters, so when restarting the CC with STARTCC, the count will continue.

When the CC is running it can be calibrated. An analog and a digital offset calibration is available. The digital portion of the

CC is by default permanently corrected for offset and gain errors. This function can be disabled by setting the CCCALDB bit.

However, this is not advisable.

In order to calibrate the analog portion of the CC, the CCCALA bit is set. This will disconnect the inputs of the CC from the sense resistor and will internally short them together. The CCOUT[15:0] counter will accumulate the analog error over time. The calibration period can be freely chosen by the implementer and depends on the accuracy required. By setting the ONEC[14:0] = 1

DEC this process is sped up significantly. By reading out the contents of the CCOUT[15:0] and taking into account the calibration period, software can now calculate the error and account for it. Once the calibration period has finished the CCCALA bit should be cleared again.

One optional feature is to apply a dithering to the A to D converter to avoid any error in the measurement due to repetitive events. To enable dithering the CCDITHER bit should be set. In order for this feature to be operational, the digital calibration should remain enabled, so the CCCALDB bit should not be set.

Table 98. Coulomb Counter Characteristics

Sense resistor R1

Sensed current

On consumption

Resolution


Placed in Battery path of

Charger system

Through R1

CC active

1LSB Increment

Min

-–



1.0

–

–

Typ

20

–

10

381.47

Max

–



3000

20

–

Unit

m

 mA



A



C





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ADC SUBSYSTEM

As follows from the previous description, using the CC requires a number of programming steps. A typical programming example is given below.

1. SPI Access 1: Initialize

• Reg 9: Write STARTCC = 1, RSTCC = 1, CCCALA = 1, CCDITHER = 1, CCCALDB = 0

• RSTCC will be self clearing

• Register 10 is NOT to be programmed since by default the ONEC[14:0] scaler is set to 1

2. Wait for analog calibration period

3. SPI Access 2: Set scaler

• Reg 10: Write ONEC to desired value for CC use, for instance 2621DEC

4. SPI Access 3: Read analog offset and reset CC

• Reg 9: Write STARTCC = 1, RSTCC = 1, CCCALA = 0, CCDITHER = 1, CCCALDB = 0

• During the write access, on the MISO read line the most recent CCOUT[15:0] is available

• RSTCC will be self clearing

From this point on the ACC is running properly and CCOUT[15:0] reflects the accumulated charge. In order to be sure the contents of the CCOUT[15:0] are valid, a CCFAULT bit is available. CCFAULT will be set '1' if the CCOUT content is no longer valid, this means the bit gets set when a fault condition occurs and stays latched till cleared by software. There is no interrupt associated to this bit. The following fault conditions are covered.

Counter roll over: CCOUT[15:0] = 8000HEX

This occurs when the contents of CCOUT[15:0] go from a negative to a positive value or vice versa. Software may interpret incorrectly the battery charge by this change in polarity. When CCOUT[15:0] becomes equal to 8000HEX the CCFAULT is set.

The counter stays counting so its contents can still be exploited.

Battery removal: 'BP<UVDET'

When removing and replacing the battery, the contents of the counter are no longer valid. A battery removal is characterized by the input supply to the IC dropping below the under voltage detect threshold, so BP<UVDET. To avoid false detection due to short power cuts, the CCFAULT is set only after a long debounce of 1 second.

Battery removal when charging: BATTDETBS = 1

The battery removal detection as described previously, is not applicable when charging, since the charger will continue to supply the application and the BP will not drop below UVDET. To still detect a battery removal, one can use the battery detect function as described in the channel description earlier in this chapter. When the sense bit BATTDETBS becomes a 1, the

CCFAULT is set only after a long debounce of 1 second.

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CONNECTIVITY

CONNECTIVITY

USB INTERFACE

The MC13892 contains the regulators required to supply the PHY contained in the i.MX51, i.MX37, i.MX35, and i.MX27 processors. The regulators used to power the external PHY in the i.MX51 and i.MX37 are VUSB, VUSB2, and VUSB for the i.MX35 and i.MX27 processors. The MC13892 also provides the 5.0 V supply for USB OTG operation. The USB interface may be used for portable product battery charging (refer to

Battery Interface and Control

for more details on the charging system).

Finally included are comparators/detectors for VBUS and ID detection. The USB interface is illustrated in the following diagram.

Figure 32. USB Interface

SUPPLIES

The VUSB regulator is used to supply 3.3 V to the external USB PHY. The UVBUS line of the USB interface is supplied by the host in the case of host mode operation, or by the integrated VBUS generation circuit, in the case of USB OTG mode operation.

The VBUS circuit is powered from the SWBST boost supply to ensure OTG current sourcing compliance through the normal discharge range of the main battery.

The VUSB regulator can be supplied from the UVBUS wire of the cable when supplied by a host in the case of host mode operation, or by the SWBST voltage brought in at the VINUSB pin and internally connected to the VBUS pin for OTG mode operation. The VUSBIN SPI bit is used to make the selection between host or OTG mode operation as defined in

Table 99

.


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CONNECTIVITY

Table 99. VUSB Input Source Control

Parameter

VUSBIN

Value

0

1

Function

Powered by Host: UVBUS powers VUSB

OTG mode: SWBST internally switched to supply the VUSB regulator, and SWBST will drive VBUS from the

VUSBIN pin as long as VBUSEN pin is logic high = 1

Notes

86.

Note that (VUSBIN = 1 and VBUSEN = 1) only closes the switch between the VINUSB and UVBUS pins, but does not enable the

SWBST boost regulator (which should be enabled with OTGSWBSTEN = 1).

87.

VUSBIN SPI bit initialized by PUMS2 pin configuration at cold start



PUMS2 = Open, VUSBIN = 0



PUMS2 = Ground, VUSBIN = 1

The VBUSEN pin along with the VUSBIN SPI bit shown in

Table 99

, control switching SWBST to drive VBUS in OTG mode.

When VBUSEN = 1 and VUSBIN = 1, SWBST will be driving the VBUS. In all other cases, the switch from VINUSB to UVBUS will be open. The VUSBIN SPI bit is initialized by the PUMS2 pin configuration at cold start. When the PUMS2 is open the

VUSBIN SPI bit will default to 0, and when PUMS2 is grounded the VUSBIN SPI bit will default to 1. When PUMS2 is grounded, the SWBST will also be enabled by default by setting the OTGSWBSTEN bit = 1. Note that (VBUSEN = 1 and VUSBIN = 1) only closes the switch between VINUSB and UVBUS pins, but does not enable SWBST (this needs to be enabled by setting the SPI bit OTGSWBSTEN = 1).

In OTG mode, VUSB and VUSB2 will be automatically enabled by setting the SPI bit VUSBIN to a 1. When SWBST is supplying the UVBUS pin (OTG Mode), it will generate VBUSVALID and BVALID interrupts. These interrupts should not be interpreted as being powered by the host by the software, and the VUSB supply will continue to be supplied by the SWBST output. To prevent the charger from charging in OTG mode, the charger should be put into software controlled mode by setting the CHGAUTOB = 1, and the charge current set to 0 prior to enabling the SWBST to supply the UVBUS pin.

The VUSB regulator defaults to on when PUMS2 = Ground, and is supplied by the SWBST output. If a USB host is attached, the switchover to supply the VUSB input by the USB cable (UVBUS pin) is a manual switchover, which will require the following steps via software to switch over properly: receive BVALID interrupt, disable the VUSB regulator (VUSBEN = 0), change the input

VUSB to UVBUS instead of SWBST (set VINUSB = 0), and then enable the VUSB regulator (VUSBEN = 1). It will be up to the processor to determine what type of device is connected, either a USB host or a wall charger, and take appropriate action.

When the PUMS2 = OPEN, the VUSB regulator will default to off, unless 5.0 V is present on the UVBUS pin. If UVBUS is

detected during cold start then the VUSB regulator will be enabled and powered on in the sequence, shown in Power Control

System , and it will default, which is supplied by the UVBUS pin. If UVBUS is not detected at cold start then the VUSB will default

to off. If UVBUS is detected later, the VUSB regulator will be automatically be enabled and supplied from the UVBUS pin.

The VUSB regulator can be enabled independent of OTG or Host Mode by setting the VUSBEN SPI bit The VUSBEN SPI bit is initialized by at startup based on the PUMS2 configuration. With PUMS2 OPEN, the VUSBEN will default to a 1 on power up and will reset to a 1, when either RESETB is valid or VBUS is invalid. This allows the VUSBEN regulator to be enabled automatically if the VUSB regulator was disabled by software. With PUMS2 = GND the VUSBEN bit will be enabled in the power up sequence shown in

Power Control System .

Since UVBUS is shared with the charger input at the board level (see


), the UVBUS node must be able to withstand the same high voltages as the charger. In over-voltage conditions, the VUSB regulator is disabled. The following tables show the USB supplies.

VUSB2 is implemented with an integrated PMOS pass FET and has a dedicated supply pin VINUSB2. The pin VINUSB2 should always be connected to BP even in cases where the regulators are not used by the application.

Table 100. VUSB2 Voltage Control

Parameter

VUSB2[1:0]

Value

00

01

10

11

Function

output = 2.400 V output = 2.600 V output = 2.700 V output = 2.775 V

ILoad max

50 mA

50 mA

50 mA

50 mA

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CONNECTIVITY

DETECTION COMPARATORS

VBUS detection and qualification is accomplished with two comparators, detailed in

Table 101 . Comparator results are used

to generate associated interrupts, and sense and masking bits are available through SPI (refer to

SPI Bitmap

). Comparator thresholds are specified for the minimum detect levels, and bits can be used in combination to qualify a VBUS window. Events are communicated via (INT pin) interrupts and managed through SPI registers to allow the application processor to turn off the

PHY.

As described in


, the battery charger system is designed to work with the USB system physical connector. The power input is then brought into an end product on the VBUS pin of the USB connector. For fault condition robustness, VBUS over-voltage protection is included to protect the system and flag an over-voltage situation to the processor via the USBOVI interrupt.

Table 101. USB Detect Specifications

Parameter

V

BUS

Valid Comparator trip level

Condition Min

4.4

Typ

–

Max

4.65

Units

V

V

BUS

Valid trip delay

BVALID Comparator Threshold

BVALID Trip Delay

Over-voltage Protection Level

Over-voltage Protection Disconnect Time

Including the USBI debounce

Rising trip delay

Falling trip delay

Rising and falling edge

Rising trip delay for turn on event

Falling trip delay for turn on event

Rising and falling edge

20

8.0

4.0

20

8.0

5.6

–

–

–

–

–

–

–

–

24

12

4.4

40

12

6.0

1.0

ms ms

V ms

V

 s

ID DETECTOR

The ID detector is primarily used to determine if a mini-A or mini-B style plug has been inserted into a mini-AB style receptacle on the application. However, it is also supports two additional modes which are outside of the USB standards: a factory mode and a non-USB accessory mode. The state of the ID detection can be read via the SPI to poll dedicated sense bits for a floating, grounded, or factory mode condition on the UID pin. There are also dedicated maskable interrupts for each UID condition as well.

The ID detector is based on an on-chip pull-up controlled by the IDPUCNTRL bit. If set high the pull-up is a current source, if set low it is a resistor. ID100KPU switches in an additional pull-up from VCORE to UID (independent of IDPUCNTRL). The UID voltage can be read out via the ADC channel ADIN7, see

ADC Subsystem .

The ID detector thresholds are listed in Table 102

. Further interpretations of non-USB accessory detection may be made for custom vendor applications by evaluation of the ADIN7 conversion reading.

Table 102. ID Detection Thresholds

UID Pin External

Connection

UID Pin Voltage

Resistor to Ground

Grounded

Floating

0.18 * VCORE < UID

< 0.77 * VCORE

0 < UID < 0.12 *

VCORE

0.89 * VCORE < UID

< VCORE

3.6V < UID

(88)

Voltage Applied

Notes

88.

UID maximum voltage is 5.25 V

IDFLOATS

0

0

1

1

IDGNDS

1

0

1

1

IDFACTORYS

0

0

0

1

Accessory

Non-USB accessory is attached (per CEA-

936-A spec)

A type plug (USB Default Slave) is attached (per CEA-936-A spec)

B type plug (USB Host, OTG default master or no device) is attached.

Factory mode





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LIGHTING SYSTEM

Table 103. USB OTG Specifications

Parameter

VBUS Input Impedance

UID 220K Pull-up

UID Pull-up

(89)

(89)

UID Parallel Pull-up

(89)

As A_device

Condition

IDPUCNTRL = 0, Resistor to VCORE

IDPUCNTRL = 1, Current source from VCORE

ID100KPU = 1, Resistor to VCORE

Min

40

132

4.75

60

Typ

-

220

5.0

100

Max

100

308

5.25

140

Units

k

 k





A k



Notes

89.

Note that the UID Pull-ups are not mutually exclusive of each other; they are independently controlled by their enable bits and thus multiple pull-ups can be engaged simultaneously.

LIGHTING SYSTEM

The lighting system includes backlight drivers for main display, auxiliary display, and keypad. The backlight LEDs are configured in series. Three additional drivers are provided for RGB or general purpose signaling.

BACKLIGHT DRIVERS

The backlight drivers LEDMD, LEDAD and LEDKP are independent current sink channels. Each driver channel features programmable current levels via LEDx[2:0] as well as programmable PWM duty cycle settings with LEDxDC[5:0]. By a combination of level and PWM settings, the backlight intensity can be adjusted, or a soft start and dimming feature can be implemented. The on period of the serial LED backlight drivers will be adapted to take into account that the serial LED switcher startup time is longer than one half the minimum of the period of the backlight drivers.

When applying a duty cycle of less than 100% the backlight drivers will be turned on and off at a repetition rate high enough to avoid flickering and or beat frequencies with the different types of displays. Also, to avoid high frequency spur coupling in the application, the switching edges of the output drivers are softened.

The current level is programmable in a low range mode and in a high range mode through the LEDxHI bit. This facilitates the current setting, in case two or more serial LED strings are connected in parallel to the same driver or when using super bright

LEDs.

Table 104. Backlight Drivers Current Programming

LEDx[2:0]

(90)

LEDx Current Level (mA)

LEDxHI = 0 LEDxHI = 1

000

001

010

011

6

9

0

3

100

101

110

111

12

15

18

21

Notes

90.

“x Represents MD, AD and KP

24

30

36

42

12

18

0

6

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LIGHTING SYSTEM

Table 105. Backlight Drivers Duty Cycle Programming

LEDxDC[5:0]

(91)

Duty Cycle

000000

000001

…

010000

0/32, Off

1/32

…

16/32

…

011111

…

31/32

100000 to 111111

Notes

91.

“x” represents MD, AD, or KP

32/32, Continuously On

Ramp up and ramp down patterns are implemented in hardware to reduce the burden of real time software control via the SPI to orchestrate dimming and soft start lighting effects. Ramp patterns for each of the drivers is accessed with the corresponding

LEDxRAMP bit.

The ramp itself is generated by increasing or decreasing the PWM duty cycle with a 1/32 step every 1/64 seconds. The ramp time is therefore a function of the initial set PWM cycle and the final PWM cycle. As an example, starting from 0/32 and going to

32/32 will take 500 ms, while going to from 8/32 to 16/32 takes 125 ms. Note that the ramp function is executed upon every change in PWM cycle setting when the corresponding LEDxRAMP = 1. If a PWM change is programmed via SPI when

LEDxRAMP = 0, then the change is immediate rather than spread out over a PWM sweep.

A maximum of only two backlight drivers can be activated at the same time, for instance, the main display plus keypad. If all three backlight drivers are enabled through the LEDxEN bits, meaning none of the duty cycles equals 0/32, then none of the drivers will be activated.

If two backlight drivers are enabled, they time-share the external boost regulator output. The drivers will automatically be enabled and disabled in a 50/50 percent fashion at a sufficiently high rate. The LED drive current will automatically be doubled to the same luminosity as in a single backlight driver configuration.

Figure 33

illustrates the time sharing principle. Assume the MD domain is represented by 6 series white LEDs, and the KP domain is represented by 3 ballasted stacks, that include 3 blue LEDs in each (a diagram of Serial LED configurations is included later in this chapter).

One Driver

Active

Two Drivers

Active

External

Boost

LEDKP

Current

LEDMD

Current

LEDMD

Active

LEDMD

Active

LEDKP

Active

LEDMD

Active

LEDKP

Active

Figure 33. Backlight Drivers Time Sharing Example

The “One Driver Active” case shows the general response when driving a single zone of 6 white LEDs. The “Two Drivers

Active” case shows the LEDMD zone driven at twice the current for half the time.





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LIGHTING SYSTEM

Table 106. Serial LED Driver Characteristics

Parameter

(92)

Output Current Setting

Current Programming Granularity

PWM Granularity

Repetition Rate

Absolute Accuracy

Matching

Glow and Dimming Speed

Condition

Low Range Mode

High Range Mode

Low Range Mode

High Range Mode

Not blinking

At 400 mV, 21 mA

Per 1/32 duty cycle step

Min

–

–

–

–

–

0.0

0.0

–

–

Typ

1/32

256

–

–

1/64*

–

–

3.0

6.0

Max

–

–

15

3.0

–

–

–

15

30

Units

mA mA

Hz

%

%

S

Notes

92.

Equivalent to 500 ms ramp time when going from 0/32 to 32/32

Figure 34

illustrates some possible configurations for the backlight driver. Note that when parallel strings are ganged together on a driver channel, ballasting resistance is recommended to help balance the currents in each leg.

External

Boost

External

Boost

External

Boost

LEDMD

6 LED Main Display

LEDKP

9 LED Keypad

LEDMD LEDAD

6 LED Main Display

3 LED Aux Display

LEDMD

6 LED Main Display

LEDAD LEDKP

12 LED Keypad Arrangement

2 LED Reduced Keypad Option

Figure 34. Serial LED Configurations

In the left most example in Figure 34

: LEDMD is set at 15 mA (low range), LEDKP is set at 30 mA (high range). When both are operated, then the LEDMD current will pulse at 30 mA and the LEDKP current at 60 mA. This provides an average of 15 mA through the main display backlight LEDs and 30 mA through the keypad backlights LEDs.

SIGNALING LED DRIVERS

The signaling LED drivers LEDR, LEDG, LEDB are independent current sink channels. Each driver channel features programmable current levels via LEDx[2:0] as well as programmable PWM duty cycle settings with LEDxDC[5:0]. By a combination of both, the LED intensity can be adjusted. By driving LEDs of different colors, color mixing can be achieved.

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LIGHTING SYSTEM

Table 107. Signaling LED Drivers Current Programming

LEDx[2:0]

(93)

100

101

110

111

000

001

010

011

Notes

93.

“x” represents for R, G and B

LEDx Current Level (mA)

12

15

18

21

0.0

3.0

6.0

9.0

Table 108. Signaling LED Drivers Duty Cycle Programming

LEDxDC[5:0]

(94)

000000

000001

…

010000

…

011111

1xxxxx

Notes

94.

“x” represents R, G and B

Duty Cycle

0/32, Off

1/32

…

16/32

…

31/32

32/32, Continuously On

Blue LEDs or bright green LEDs require more headroom than red and normal green signal LEDs. In the application, a 5.0 V or equivalent supply rail is therefore required. This is provided by the integrated boost regulator SWBST. To make software programming easier, an LEDSWBSTEN SPI bit has been provided in the Blue LED register to enable the boost regulator. Note the enable for the boost regulator is an OR of the following SPI bits (SWBSTEN, USBSWBSTEN, and LEDSWBSTEN). For more

details on the boost regulator and its control, see Supplies

.

As with the backlight driver channels, the signaling LED drivers include ramp up and ramp down patterns are implemented in hardware. Ramp patterns for each of the drivers is accessed with the corresponding LEDxRAMP bit.


32/32 will take 500 ms while going to from 8/32 to 16/32 takes 125 ms.

Note that the ramp function is executed upon every change in PWM cycle setting. If a PWM change is programmed via SPI when LEDxRAMP = 0, then the change is immediate rather than spread out over a PWM sweep.

For color mixing and in order to guarantee a constant color, the color mixing should be obtained by the current level setting so that the intensity is set through the PWM duty cycle.

In addition, programmable blink rates are provided. Blinking is obtained by lowering the PWM repetition rate of each of the drivers through LEDxPER[1:0], while the on period is determined by the duty cycle setting. To avoid high frequency spur coupling in the application, the switching edges of the output drivers are softened. During blinking, so LEDxPER[1:0] is not “00”, ramping and dimming patterns cannot be applied.

Table 109. Signal LED Drivers Period Control

LEDxPER[1:0]

00

01

10

11

Repetition Rate

1/256

1/8

1

2

Units

s s s s





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LIGHTING SYSTEM

Table 110. Signaling LED Driver Characteristics

Parameter

Absolute Accuracy

Matching

Leakage

Condition

At 400 mV, 21 mA

LEDxDC[5:0] = 000000

Min

–

–

–

Typ

–

–

–

Max

15

10

1.0

Units

%

%



A

Apart from using the signal LED drivers for driving LEDs they can also be used as general purpose open drain outputs for logic signaling or as generic PWM generator outputs. For the maximum voltage ratings.

the enable for the boost regulator is an OR of the following SPI bits (SWBSTEN, USBSWBSTEN, and LEDSWBSTEN). For

more details on the boost regulator and its control, see Supplies .

As with the backlight driver channels, the signaling LED drivers include ramp up and ramp down patterns are implemented in hardware. Ramp patterns for each of the drivers is accessed with the corresponding LEDxRAMP bit.


32/32 will take 500 ms while going to from 8/32 to 16/32 takes 125 ms.

Note that the ramp function is executed upon every change in PWM cycle setting. If a PWM change is programmed via SPI when LEDxRAMP = 0, then the change is immediate rather than spread out over a PWM sweep.

For color mixing and in order to guarantee a constant color, the color mixing should be obtained by the current level setting so that the intensity is set through the PWM duty cycle.

In addition, programmable blink rates are provided. Blinking is obtained by lowering the PWM repetition rate of each of the drivers through LEDxPER[1:0], while the on period is determined by the duty cycle setting. To avoid high frequency spur coupling in the application, the switching edges of the output drivers are softened. During blinking, so LEDxPER[1:0] is not “00”, ramping and dimming patterns cannot be applied.

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


SPI BITMAP

The complete SPI bitmap is given in Table 111 with one register per row for a general overview. A color coding is applied which indicates the type of reset for the bits.

Table 111. SPI Bitmap

MC13892 Bitmap Color Coding: Bits Reset by RESETB Bits Reset by RTCPORB Bits Reset by OFFB Bits Without Reset Bits Reloaded at Cold Start Reserved Bits Not Available Bits

31 30 29 28 27 26 25 24 23

Register

Register

Label

R/W

R/T

Address 5:0 Null

22 21 20

Data[23:16]

19 18 17 16 15 14 13 12 11

Data[15:7]

10 9 8 7 6 5 4 3

Data[7:0]

2 1 0

0

Interrupt

Status 0

R/W 0 0 0 0 0 0 0

Reserve d

Reserved CHGRGSE1BI IDGNDI IDFLOATI Reserved Reserved BVALIDI Reserved LOBATHI LOBATLI BPONI CHGCURRI CCCVI CHGSHORTI CHGREVI CHGFAULTI CHGDETI USBOVI IDFACTORYI VBUSVALIDI

1

Interrupt

Mask 0

R/W 0 0 0 0 0 1 0

Reserve d

Reserved CHGRGSE1BM IDGNDM IDFLOATM Reserved Reserved BVALIDM Reserved LOBATHM LOBATLM BPONM CHGCURRM CCCVM CHGSHORTM CHGREVM CHGFAULTM CHGDETM USBOVM IDFACTORYM VBUSVALIDM

2

Interrupt

Sense 0

R 0 0 0 0 1 0 0

Reserve d

Reserved Reserved IDGNDS IDFLOATS Reserved Reserved BVALIDS Reserved LOBATHS LOBATLS BPONS CHGCURRS CCCVS CHGFAULTS[1:0] CHGENS CHGDETS USBOVS IDFACTORYS VBUSVALIDS

TSI

TSM

3

Interrupt

Status 1

R/W 0 0 0 0 1 1 0 Spare BATTDETBI

4

Interrupt

Mask 1

R/W 0 0 0 1 0 0 0 Spare BATTDETBIM

Reserved Reserved Reserved Reserved


5

6

Interrupt

Sense 1

R 0 0 0 1 0 1 0 Spare BATTDETBS

Power Up

Mode

Sense

R 0 0 0 1 1 0 0 Spare Spare

7

Identificatio n

R 0 0 0 1 1 1 0


Reserved Reserved Spare Spare

SCPI

SCPM

Spare

Spare

Spare

ICIDCODE[5:0]

CLKI

Reserved

THWARNHI THWARNLI

CLKS THWARNHS THWARNLS

Spare

FAB[1:0]

LPBI

LPBS

MEMHLDI

CHRGSE1B

S

WARMI

CLKM THWARNHM THWARNLM LPBM MEMHLDM WARMM

PCI

PCM

CHRGSSS Reserved

FIN[1:0]

RTCRSTI

RTCRSTM SYSRSTM WDIRESTM PWRON2M

Reserved

ICID[2:0]

SYSRSTI WDIRESTI

Reserved

PWRON2I

PWRON2S

PUMS2S[1:0]

PWRON1I

PWRON1M

PWRON1S

PWRON3I

PWRON3M

PWRON3S

PUMS1S[1:0]

REV[4:0]

ADCBISDONEI ADCDONEI

ADCBISDONEM ADCDONEM

TODAI

TODAM

MODES[1:0]

1HZI

1HZM

8 Unused R/W 0 0 1 0 0 0 0

CCOUT[15:0] 9 Unused R/W 0 0 1 0 0 1 0

10 Unused R/W 0 0 1 0 1 0 0

11 Unused R/W 0 0 1 0 1 1 0

12 Unused R/W 0 0 1 1 0 0 0

13

Power

Control 0

R/W 0 0 1 1 0 1 0

COINCH

EN

14

Power

Control 1

R/W 0 0 1 1 1 0 0

VCOIN[2:0]

BATTDETE

N

Reserved BPSNS[1:0]

PCMAXCNT[3:0]

CCFAULT Reserved Reserved CCCALA CCCALDB CCDITHER RSTCC STARTCC

ONEC[14:0]

PCUTEXPB THSEL GLBRSTENB

CLK32KMC

UEN

USEROFFC

LK

DRM USEROFFSPI WARMEN PCCOUNTEN PCEN

PCCOUNT[3:0] PCT[7:0]


MC13892 Bitmap Color Coding:

15

31 30 29 28 27 26 25 24

Power

Control 2

R/W 0 0 1 1 1 1 0

23 22

STBYDLY[1:0]

Bits Reset by RESETB Bits Reset by RTCPORB Bits Reset by OFFB Bits Without Reset Bits Reloaded at Cold Start Reserved Bits Not Available Bits

21 20 19

Reserved Reserved Reserved

18 17 16 15

CLKDRV[1:0] Reserved Reserved

14 13

SPIDRV[1:0]

12 11 10 9 8

WDIRESET

STANDBYSE

CINV

STANDBYP

RIINV

PWRON3DBNC[1:0]

7 6 5 4 3 2 1 0

PWRON2DBNC[1:0] PWRON1BDBNC[1:0] PWRON3RSTENPWRON2RSTENPWRON1RSTEN RESTARTEN

16 Unused R/W 0 1 0 0 0 0 0

17 Unused R/W 0 1 0 0 0 1 0

18 Memory A R/W 0 1 0 0 1 0 0

19 Memory B R/W 0 1 0 0 1 1 0

MEMA[23:0]

MEMB[23:0]

20 RTC Time R/W 0 1 0 1 0 0 0 RTCCALMODE[1:0]

21 RTC Alarm R/W 0 1 0 1 0 1 0 RTCDIS

22 RTC Day R/W 0 1 0 1 1 0 0

23

RTC Day

Alarm

R/W 0 1 0 1 1 1 0

24 Switchers 0 R/W 0 1 1 0 0 0 0 SW1HI

25 Unused R/W 0 1 1 0 0 1 0 SW2HI

SW1SIDMIN[3:0]

SW2SIDMIN[3:0]

RTCCAL[4:0]

Spare

TOD[16:0]

TODA[16:0]

SW1DVS[4:0]

SW2DVS[4:0]

DAY[14:0]

DAYA[14:0]

SW1SIDMAX[3:0]

SW2SIDMAX[3:0]

SW1STBY[4:0]

SW2STBY[4:0]

SW1[4:0]

SW2[4:0]

26 Switchers 2 R/W 0 1 1 0 1 0 0 SW3HI Reserved SW3STBY[4:0] Spare SW3[4:0]

27 Unused R/W 0 1 1 0 1 1 0 SW4HI

28 Switchers 4 R/W 0 1 1 1 0 0 0

Reserve d

SWILIMB

29 Switchers 5 R/W 0 1 1 1 0 1 0

30

Regulator

Setting 0

R/W 0 1 1 1 1 0 0

31

Regulator

Setting 1

R/W 0 1 1 1 1 1 0

32

Regulator

Mode 0

R/W 1 0 0 0 0 0 0

33

34

Regulator

Mode 1

R/W 1 0 0 0 0 1 0

Power

Miscellane ous

R/W 1 0 0 0 1 0 0

PLLX[2:0]

SWBSTEN

Spare

SW4STBY[4:0]

PLLEN SW2DVSSPEED[1:0]

SW2UOM

ODE

SW2MHMI

DE

SW2MODE[3:0]

SW4UOMOD

E

SW4MHMIDE

VCAM[2:0] VGEN3 VUSB2[1:0]

Reserved SIDEN

SW4MODE[3:0]

VPLL[1:0]

Spare

SW1DVSSPEED[1:0]

SW1UOMO

DE

SW1MHMIDE

SW3UOMO

DE

SW3MHMIDE

VGEN[2:0] VDIG[1:0]

SW4[4:0]

SW1MODE[3:0]

SW3MODE[3:0]

VGEN[1:0]

VSD[2:0] VAUDIO[1:0] VVIDEO[1:0] Reserved

GPO4ADIN

Spare VUSB2STBYVUSB2EN Spare VPLLSTBY VPLLEN

VGEN2M

ODE

VGEN2STBY VGEN2EN Spare VDIGSTBY VDIGEN

VSDMODE VSDSTBY VSDEN Spare

VAUDIOST

BY

VAUDIOE

N

VVIDEOM

ODE

VVIDEOSTBY VVIDEOEN Reserved

Spare

VCAMCONFI

G

VCAMMOD

E

VCAMSTBY VCAMEN Spare

VIOHISTBY

Reserved

VIOHIEN VGEN1MODE

VGEN3CONFIG VGEN3MODE

VGEN1STBY VGEN1EN

VGEN3TBY VGEN3EN

Spare

PWGT2SPI

EN

PWGT1S

PIEN

GPO4STBY GPO4EN GPO3STBY GPO3EN GPO2STBY GPO2EN GPO1STBY GPO1EN REGSCPEN


MC13892 Bitmap

31 30 29 28 27 26 25 24 23

35 Unused R/W 1 0 0 0 1 1 0

Color Coding:

22 21

Bits Reset by RESETB Bits Reset by RTCPORB Bits Reset by OFFB

20 19 18 17 16 15 14 13 12 11

Bits Without Reset

10 9

Bits Reloaded at Cold Start

8 7 6 5

Reserved Bits

4 3 2

Not Available Bits

1 0

36 Audio Rx 0 R/W 1 0 0 1 0 0 0

37 Audio Rx 1 R/W 1 0 0 1 0 1 0

38 Audio Tx R/W 1 0 0 1 1 0 0

39

SSI

Network

R/W 1 0 0 1 1 1 0

40

41

Audio

Codec

R/W 1 0 1 0 0 0 0

Audio

Stereo

DAC

R/W 1 0 1 0 0 1 0

42 Unused R/W 1 0 1 0 1 0 0

43 ADC 0 R/W 1 0 1 0 1 1 0

ADCBIS

0

44 ADC 1 R/W 1 0 1 1 0 0 0

ADCBIS

1

ADONESHOT ADTRIGIGN ASC

45 ADC 2 R 1 0 1 1 0 1 0

Spare

ATOX

ADD2[9:0]

ADINC2 ADINC1

CHRGRA

WDIV

ATO[7:0]

TSMOD[2:0] Reserved TSREFEN ADIN7DIV ADRESET

ADA2[2:0] ADA1[2:0]

ADIN7SEL[1:0]

TRIGMASK

BUFFEN

ADSEL

BATICON

ADCCAL

CHRGICON

RAND

LICELLCON

ADEN

Spare Spare ADD1[9:0] Spare Spare

46 ADC 3 R/W 1 0 1 1 1 0 0

Reserve d

47 ADC 4 R 1 0 1 1 1 1 0

ICID[2:0]

ADDBIS2[9:0] Spare Spare ADDBIS1[9:0] Spare Spare

48 Charger 0 R/W 1 1 0 0 0 0 0

CHGAUT

OVIB

CYCLB

49

CHGAUTOB

CHRGREST CHGTMRRS

ART T

CHRGLE

DEN

PLIMDIS

USB 0 R/W 1 1 0 0 0 1 0

Reserve d

IDPUCNTRL Reserved Reserved Reserved

PLIM[1:0] RVRSMODE Spare FETCTRL FETOVRD THCHKB ACLPB TREN ICHRG[3:0]

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Spare Reserved Reserved

50

Charger

USB 1

R/W 1 1 0 0 1 0 0

51

LED

Control 0

R/W 1 1 0 0 1 1 0 LEDAD[2:0]

Spare Spare

LEDADDC[5:0]

Reserved

LEDADRA

MP

Reserved Reserved Reserved

OTGSWBS

TEN

Reserved ID100KPU Reserved Reserved

LEDADHI Spare LEDMD[2:0] LEDMDDC[5:0]

52

LED

Control 1

R/W 1 1 0 1 0 0 0

53

LED

Control 2

R/W 1 1 0 1 0 1 0

54

LED

Control 3

R/W 1 1 0 1 1 0 0

LEDG[2:0] LEDGDC[5:0]

Spare

LDEDGRA

MP

Spare

Spare

LEDGPER[1:0]

Spare

Spare

LEDSWBSTE

N

LEDKP[2:0]

LEDR[2:0]

LEDB[2:0]

LEDKPDC[5:0]

LEDRDC[5:0]

LEDBDC[5:0]

Reserved

VUSBEN

Reserved

LEKPDRAMP

LDEDRRAMP

LDEDBRAMP

VCHRG[2:0]

Reserved

LEDMDRAMP LEDMDHI

LEDKPHI

Reserved

VUSBIN

Spare

Spare

LEDRPER[1:0]

LEDBPER[1:0]


MC13892 Bitmap

31 30 29 28 27 26 25 24 23

55 Unused R/W 1 1 0 1 1 1 0

Color Coding:

22 21

56 Unused R/W 1 1 1 0 0 0 0

57

FSL Use

Only

R/W 1 1 1 0 0 1 0

58

FSL Use

Only

R/W 1 1 1 0 1 0 0

59

FSL Use

Only

R/W 1 1 1 0 1 1 0

60

FSL Use

Only

R/W 1 1 1 1 0 0 0

61

FSL Use

Only

R/W 1 1 1 1 0 1 0

62

FSL Use

Only

R/W 1 1 1 1 1 0 0

63

FSL Use

Only

R/W 1 1 1 1 1 1 0

Bits Reset by RESETB Bits Reset by RTCPORB Bits Reset by OFFB

20 19 18 17 16 15 14 13 12 11

Bits Without Reset

10 9

Bits Reloaded at Cold Start

8 7 6 5

Reserved Bits

4 3 2

Not Available Bits

1 0

SPI BITMAP

The 24 bit wide registers are numbered from 0 to 63, and are referenced throughout this document by register number, or representative name as given in the corresponding captions. The contents of all registers are given in the tables defined in this chapter; each table includes the following information:

Name:

Name of the bit. Spare bits are implemented in the design for future use, but are not assigned. Unused bits are not available in the design. Reserved bits are not implemented in the design, but are used on other PMICs.

Bit #:

The bit location in the register (0-23)

R/W:

Read / Write access and control

• R is read access

• W is write access

• R/W is read and write access

• RW1C is read and write access with write 1 to clear

• RWM is read and write access while the device can modify the bit

Reset:

Resetting signal

• RESETB, which is the same signal as the RESETB pin (so bit is held in reset as long as RESETB is low)

• RTCPORB which is the reset signal of the RTC module (so bit is no longer held in reset once RTC power is good)

• OFFB which is an internal signal generated when transitioning into the Off state

• NONE. There is no reset signal for hardwired bits nor for the bits of which the state is determined by the power up mode settings

Default:

The value after reset as noted in the Default column of the SPI map.

• Fixed defaults are explicitly declared as 0 or 1.

• * corresponds to Read / Write bits that are initialized at startup based on power up mode settings (board level pin connections) validated at the beginning of Cold or Warm Start. Bits are subsequently SPI modifiable.

• S corresponds to Read only sense bits that continuously monitor an input signal (sense signal is not latched).

• L corresponds to Read only sense bits that are latched at startup.

• X indicates that the state does not have an explicitly defined default value which can be specified. For instance, some bits default to a value which is dependent on the version of the IC.

Description:

A short description of the bit function, in some cases additional information is included

The following tables are intended to give a summarized overview, for details on the bit description, see the individual chapters.

Table 112. Register 0, Interrupt Status 0

Name

ADCDONEI

ADCBISDONEI

TSI

VBUSVALIDI

IDFACTORYI

USBOVI

CHGDETI

CHGFAULTI

CHGREVI

CHGSHORTI

CCCVI

CHGCURRI

BPONI

LOBATLI

LOBATHI

Reserved

BVALIDI

Reserved

Reserved

IDFLOATI

IDGNDI

Bit #

12

13

14

15

8

9

10

11

16

17

18

19

20

6

7

4

5

2

3

0

1

R/W

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

R

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

R

R

RW1C

RW1C

Reset

RESETB

RESETB

RESETB

OFFB

RESETB

RTCPORB

OFFB

RTCPORB

RESETB

RESETB

RESETB

RESETB

OFFB

RESETB

RESETB

OFFB

RESETB

RESETB

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Description

ADC has finished requested conversions

ADCBIS has finished requested conversions

Touch screen wake-up

VBUSVALID detect

ID factory mode detect

USB over-voltage detection

Charger attach

Charger fault detection

Charger path reverse current

Charger path short circuit

Charger path CC / CV transition detect

Charge current below threshold warning

BP turn on threshold

Low battery low threshold warning

Low battery high threshold warning

For future use

USB B-session valid interrupt

For future use

For future use

USB ID float detect

USB ID ground detect





MC13892

123

SPI BITMAP


Name

CHRGSE1BI

Reserved

Reserved

Bit #

21

22

23

R/W

RW1C

R

R

Table 113. Register 1, Interrupt Mask 0

Name

ADCDONEM

ADCBISDONEM

TSM

VBUSVALIDM

IDFACTORYM

USBOVM

CHGDETM

CHGFAULTM

CHGREVM

CHGSHORTM

CCCVM

CHGCURRM

BPONM

LOBATLM

LOBATHM

Reserved

BVALIDM

Reserved

Reserved

IDFLOATM

IDGNDM

CHRGSE1BM

Reserved

Reserved

Bit #

12

13

14

15

10

11

8

9

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R

R/W

R/W

R/W

R

R

Reset

RESETB

Default

0

0

0

Wall Charger detect

For future use

For future use

Description

Reset

RESETB

RESETB

RESETB

OFFB

RESETB

RTCPORB

OFFB

RTCPORB

RESETB

RESETB

RESETB

RESETB

OFFB

RESETB

RESETB

OFFB

RESETB

RESETB

RESETB

Default

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Description

ADCDONEI mask bit

ADCBISDONEI mask bit

TSI mask bit

VBUSVALIDI mask bit

ID factory mask bit

USBOVI mask bit

CHGDETI mask bit

CHGFAULTI mask bit

CHGREVI mask bit

CHGSHORTI mask bit

CCCV mask bit

CHGCURRI mask bit

BPONI mask bit

LOBATLI mask bit

LOBATHI mask bit

For future use

BVALIDI mask bit

For future use

For future use

IDFLOATI mask bit

IDGNDI mask bit

Wall Charger mask bit

For future use

For future use

Table 114. Register 2, Interrupt Sense 0

Name

Unused

Unused

Unused

VBUSVALIDS

IDFACTORYS

USBOVS

CHGDETS

CHGENS

CHGFAULTS0

CHGFAULTS1

CCCVS

CHGCURRS

BPONS

LOBATLS

LOBATHS

Bit #

3

4

5

6

7

0

1

2

11

12

13

14

8

9

10

R/W

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

MC13892

124

Reset

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

Default

S

S

S

S

0

0

0

0

S

S

S

S

S

S

S

Description

Not available

Not available

Not available

VBUSVALIDI sense bit

ID factory sense bit

USBOVI sense bit

CHGDETI sense bit

Charger enable sense bit

CHGREVI sense bit

CHRGFAULT sense bit 0

CHRGFAULT sense bit 1

CHGCURRI sense bit

BPONI sense bit

LOBATLI sense bit

LOBATHI sense bit





SPI BITMAP


Reserved

BVALIDS

Reserved

Reserved

IDFLOATS

IDGNDS

Reserved

Reserved

Reserved

Name Bit #

15

16

17

18

19

20

21

22

23

R/W

R

R

R

R

R

R

R

R

R

Reset

NONE

NONE

NONE


Name

1HZI

TODAI

PWRON3I

PWRON1I

PWRON2I

WDIRESETI

SYSRSTI

RTCRSTI

PCI

WARMI

MEMHLDI

LPBI

THWARNLI

THWARNHI

CLKI

Spare

SCPI

Reserved

Reserved

Reserved

Reserved

Unused

BATTDETBI

Spare

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

RW1C

R

R

R

R

R

RW1C

RW1C

Reset

RTCPORB

RTCPORB

OFFB

OFFB

OFFB

RTCPORB

RTCPORB

RTCPORB

OFFB

RTCPORB

RTCPORB

RTCPORB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

Default

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Default

0

0

S

S

0

0

0

0

S

Description

For future use

USB B-session valid sense

For future use

For future use

ID float sense bit

ID ground sense bit

For future use

For future use

For future use

Description

1.0 Hz time tick

Time of day alarm

PWRON3 event

PWRON1 event

PWRON2 event

WDI system reset event

PWRON system reset event

RTC reset event

Power cut event

Warm start event

Memory hold event

Low-power USB boot detection

Thermal warning low threshold

Thermal warning high threshold

Clock source change

For future use

Short-circuit protection trip detection

For future use

For future use

For future use

For future use

Not available

Battery removal detect

For future use


Name

1HZM

TODAM

PWRON3M

PWRON1M

PWRON2M

WDIRESETM

SYSRSTM

RTCRSTM

PCM

Bit #

6

7

4

5

8

2

3

0

1

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

RTCPORB

RTCPORB

OFFB

OFFB

OFFB

RTCPORB

RTCPORB

RTCPORB

OFFB

Default

1

1

1

1

1

1

1

1

1

1HZI mask bit

TODAI mask bit

PWRON3 mask bit

PWRON1 mask bit

PWRON2 mask bit

WDIRESETI mask bit

SYSRSTI mask bit

RTCRSTI mask bit

PCI mask bit

Description





MC13892

125

SPI BITMAP


Name

WARMM

MEMHLDM

LPBM

THWARNLM

THWARNHM

CLKM

Spare

SCPM

Reserved

Reserved

Reserved

Reserved

Unused

BATTDETBM

Spare

Bit #

21

22

23

17

18

19

20

13

14

15

16

9

10

11

12

R/W

R

R

R

R

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

RTCPORB

RTCPORB

RTCPORB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB


Name

Unused

Unused

PWRON3S

PWRON1S

PWRON2S

Unused

Unused

Unused

Unused

Unused

Unused

LPBS

THWARNLS

THWARNHS

CLKS

Spare

Unused

Reserved

Reserved

Reserved

Reserved

Unused

BATTDETBS

Spare

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

Reset

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

Default

S

0

S

S

0

0

0

0

0

0

S

0

S

S

0

0

S

0

0

0

0

0

0

0

Default

1

1

1

1

1

1

1

1

1

1

1

0

1

1

1

Description

WARMI mask bit

MEMHLDI mask bit

Low-power USB detect mask bit

THWARNLI mask bit

THWARNHI mask bit

CLKI mask bit

For future use

Short-circuit protection trip mask bit

For future use

For future use

For future use

For future use

Not available

Battery detect removal mask bit

For future use

Description

Not available

Not available

PWRON3I sense bit

PWRON1I sense bit

PWRON2I sense bit

Not available

Not available

Not available

Not available

Not available

Not available

Low-power USB boot sense bit

THWARNLI sense bit

THWARNHI sense bit

CLKI sense bit

For future use

Not available

For future use

For future use

For future use

For future use

Not available

Battery removal detect sense bit

For future use

Table 118. Register 6, Power Up Mode Sense

Name

MODES0

IMODES1

Bit #

0

1

R/W

R

R

Reset

NONE

NONE

Default

S

S

MODE sense decode

Description

MC13892

126





SPI BITMAP

Table 118. Register 6, Power Up Mode Sense

Name

PUMS1S0

PUMS1S1

PUMS2S0

PUMS2S1

Reserved

Reserved

R eserved

CHRGSSS (1)

CHRGSE1BS

Unused

Spare

Unused

Reserved

Unused

Unused

Unused

Spare

Spare

Reserved

Reserved

Spare

Spare

Bit #

14

15

16

17

10

11

12

13

8

9

6

7

4

5

2

3

18

19

20

21

22

23

R/W

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

Reset

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

Default

0

0

0

0

0

0

S

0

0

L

0

0

L

L

L

L

0

0

0

0

0

0

PUMS1 state

PUMS2 state

Description

For future use

For future use

For future use

Charger Serial/Single mode sense

CHRGSE1BS sense bit

Not available

For future use

Not available

For future use

Not available

Not available

Not available

For future use

For future use

For future use

For future use

For future use

For future use

Notes

95.

CHRGSSS will latch an updated sense value when the charger is enabled.

Table 119. Register 7, Identification

Name

REV0

REV1

REV2

REV3

REV4

Unused

ICID0

ICID1

ICID2

FIN0

FIN1

FAB0

FAB1

ICIDCODE0

ICIDCODE1

ICIDCODE2

ICIDCODE3

ICIDCODE4

ICIDCODE5

Unused

Unused

Unused

Bit #

12

13

14

15

10

11

8

9

6

7

4

5

2

3

0

1

16

17

18

19

20

21

R/W

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

Reset

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

Default

1

0

X

0

X

X

1

X

1

1

X

0

X

X

X

X

0

0

0

0

0

0

Revision

Not available

Generation ID

MC13892 fin version

MC13892 fab identifier

Not available

Not available

Not available

Description

IC ID Within generation





MC13892

127

SPI BITMAP

Table 119. Register 7, Identification

Unused

Unused

Name Bit #

22

23

R/W

R

R

Table 120. Register 8, Unused

Unused

Name Bit #

23-0

R/W

R

Table 121. Register 9, ACC 0

Name

STARTCC

RSTCC

CCDITHER

CCCALDB

CCCALA

Reserved

Reserved

CCFAULT

CCOUT0

CCOUT1

CCOUT2

CCOUT3

CCOUT4

CCOUT5

CCOUT6

CCOUT7

CCOUT8

CCOUT9

CCOUT10

CCOUT11

CCOUT12

CCOUT13

CCOUT14

CCOUT15

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R

R

R

R

R

R

R

R

R/W

RWC

R/W

R/W

R/W

R

R

R/W

R

R

R

R

R

R

R

R

Reset

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

Reset

Reset

Default

0

0

Default

0

Not available

Not available

Description

Description

Not available

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Description

1 = Run, 0=Stop

1 = Reset, self clearing

1 = ACC Dithering enabled, 0=ACC Dithering disabled

1 = Disable Digital Offset Cancellation

1 = Enable Analog Offset Calibration Mode

Reserved for future use for scaler

Reserved for future use (for scaler)

1 = CCOUT contents no longer valid

Coulomb Counter

MC13892

128





SPI BITMAP

Table 122. Register 10, ACC 1

Name

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

ONEC0

ONEC1

ONEC2

ONEC3

ONEC4

ONEC5

ONEC6

ONEC7

ONEC8

ONEC9

ONEC10

ONEC11

ONEC12

ONEC13

ONEC14

Unused

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R


Name

Unused

Bit #

23-0


Name

Unused

Bit #

23-0

R/W

R

R/W

R

Table 125. Register 13, Power Control 0

Name

PCEN

PCCOUNTEN

WARMEN

USEROFFSPI

DRM

USEROFFCLK

CLK32KMCUEN

GLBRSTENB

(96)

THSEL

PCUTEXPB

Unused

Unused

Bit #

4

5

6

2

3

0

1

7

8

9

10

11

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

RWM

R

R

Reset

RTCPORB

RTCPORB

RTCPORB

RESETB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RESETB

RTCPORB

Reset

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

Reset

Reset

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

Description

Accumulated Current Counter output

Not available

Not available

Not available

Not available

Not available

Not available

Not available

Not available

Not available

Default

0

Default

0

Description

Not available

Description

Not available

Default

0

0

1

0

0

0

0

0

0

0

0

0

Description

Power cut enable

Power cut counter enable

Warm start enable

SPI command for entering user off modes

Keeps VSRTC and CLK32KMCU on for all states

Keeps the CLK32KMCU active during user off

Enables the CLK32KMCU

Global Reset Function enabled on the PWRON3 pin

Thermal protection threshold select

PCUTEXPB=1 at a startup event indicates that PCUT timer did not expire (assuming it was set to 1 after booting)

Not available

Not available





MC13892

129

SPI BITMAP


Name

Unused

Unused

Unused

Unused

BPSNS0

BPSNS1

Reserved

BATTDETEN

VCOIN0

VCOIN1

VCOIN2

COINCHEN

Bit #

16

17

18

19

12

13

14

15

20

21

22

23

R/W

R/W

R/W

R

R/W

R

R

R

R

R/W

R/W

R/W

R/W

Reset

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

Notes

96.

MC13892A/C versions global reset is active low (GLBRSTENB = 0)



MC13892B/D versions global reset is active high (GLBRSTENB = 1)

Default

0

0

0

0

0

0

0

0

0

0

0

0

Not available

Not available

Not available

Not available

Description

For future use

Enables battery detect function

Coin cell charger voltage setting

Coin cell charger enable


Name

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

PCT0

PCT1

PCT2

PCT3

PCT4

PCT5

PCT6

PCT7

PCCOUNT0

PCCOUNT1

PCCOUNT2

PCCOUNT3

PCMAXCNT0

PCMAXCNT1

PCMAXCNT2

PCMAXCNT3

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R

R

R

R

R

R

R

Reset

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Power cut timer

Power cut counter

Not available

Not available

Not available

Not available

Not available

Not available

Not available

Not available

Description

Maximum allowed number of power cuts


Name

RESTARTEN

PWRON1RSTEN

PWRON2RSTEN

PWRON3RSTEN

Bit #

2

3

0

1

R/W

R/W

R/W

R/W

R/W

Reset

RTCPORB

RTCPORB

RTCPORB

RTCPORB

Default

0

0

0

0

Description

Enables automatic restart after a system reset

Enables system reset on PWRON1 pin



MC13892

130





SPI BITMAP


Name

PWRON1DBNC0

PWRON1DBNC1

PWRON2DBNC0

PWRON2DBNC1

PWRON3DBNC0

PWRON3DBNC1

STANDBYINV

STANDBYSECINV

WDIRESET

SPIDRV0

SPIDRV1

Reserved

Reserved

CLK32KDRV0

CLK32KDRV1

Reserved

Reserved

Reserved

STBYDLY0

STBYDLY1

Bit #

16

17

18

19

12

13

14

15

20

21

22

23

8

9

10

11

6

7

4

5

R/W

R/W

R/W

R/W

R

R

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R

R/W

R/W

Reset

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RESETB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RESETB

RESETB


Name

Unused

Bit #

23-0

R/W

R

Reset


Name

Unused

Bit #

23-0

R/W

R

Reset

Default

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

For future use

Standby delay control

Description

Sets debounce time on PWRON1 pin



If set then STANDBY is interpreted as active low

If set then STANDBYSEC is interpreted as active low

Enables system reset through WDI

SPI drive strength

For future use

CLK32K and CLK32KMCU drive strength (master control bits)

Default

0 Not available

Default

0 Not available

Description

Description





MC13892

131

SPI BITMAP

Table 130. Register 18, Memory A

Name

MEMA0

MEMA1

MEMA2

MEMA3

MEMA4

MEMA5

MEMA6

MEMA7

MEMA8

MEMA9

MEMA10

MEMA11

MEMA12

MEMA13

MEMA14

MEMA15

MEMA16

MEMA17

MEMA18

MEMA19

MEMA20

MEMA21

MEMA22

MEMA23

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Backup memory A

Description

MC13892

132





SPI BITMAP

Table 131. Register 19, Memory B

Name

MEMB0

MEMB1

MEMB2

MEMB3

MEMB4

MEMB5

MEMB6

MEMB7

MEMB8

MEMB9

MEMB10

MEMB11

MEMB12

MEMB13

MEMB14

MEMB15

MEMB16

MEMB17

MEMB18

MEMB19

MEMB20

MEMB21

MEMB22

MEMB23

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Table 132. Register 20, RTC Time

Name

TOD8

TOD9

TOD10

TOD11

TOD12

TOD13

TOD14

TOD15

TOD0

TOD1

TOD2

TOD3

TOD4

TOD5

TOD6

TOD7

TOD16

RTCCAL0

RTCCAL1

RTCCAL2

RTCCAL3

RTCCAL4

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

16

17

18

19

20

21

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Reset

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

Backup memory B

Description

Reset

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Time of day counter

RTC calibration count

Description





MC13892

133

SPI BITMAP

Table 132. Register 20, RTC Time

Name

RTCCALMODE0

RTCCALMODE1

Bit #

22

23

R/W

R/W

R/W

Table 133. Register 21, RTC Alarm

Name

TODA0

TODA1

TODA2

TODA3

TODA4

TODA5

TODA6

TODA7

TODA8

TODA9

TODA10

TODA11

TODA12

TODA13

TODA14

TODA15

TODA16

Spare

Spare

Spare

Spare

Spare

Spare

RTCDIS

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Table 134. Register 22, RTC Day

Name

DAY0

DAY1

DAY2

DAY3

DAY4

DAY5

DAY6

DAY7

DAY8

DAY9

DAY10

DAY11

DAY12

DAY13

DAY14

Bit #

12

13

14

10

11

8

9

6

7

4

5

2

3

0

1

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

RTCPORB

RTCPORB

Default

0

0

RTC calibration mode

Description

Default

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

0

Reset

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

Time of day alarm

For future use

Disable RTC

Description

Reset

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Day counter

Description

MC13892

134





Table 134. Register 22, RTC Day

Name

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Bit #

19

20

21

22

23

15

16

17

18

R/W

R

R

R

R

R

R

R

R

R

Reset

Table 135. Register 23, RTC Day Alarm

Name

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

DAYA0

DAYA1

DAYA2

DAYA3

DAYA4

DAYA5

DAYA6

DAYA7

DAYA8

DAYA9

DAYA10

DAYA11

DAYA12

DAYA13

DAYA14

Unused

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R

R

R

R

R

R

R

Reset

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

RTCPORB

Table 136. Register 24, Switchers 0

SW10

SW11

SW12

SW13

SW14

Name Bit #

2

3

0

1

4

R/W

R/W

R/W

R/W

R/W

R/W

Reset

NONE

NONE

NONE

NONE

NONE

Default

*

*

*

*

*

Default

0

0

0

0

0

0

0

0

0

Default

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

Not available

Day alarm

Not available

Description

Description

Description

SW1 setting in normal mode

SPI BITMAP





MC13892

135

SPI BITMAP


Name

SW1DVS0

SW1DVS1

SW1DVS2

SW1DVS3

SW1DVS4

SW1STBY0

SW1STBY1

SW1STBY2

SW1STBY3

SW1STBY4

SW1SIDMAX0

SW1SIDMAX1

SW1SIDMAX2

SW1SIDMAX3

SW1SIDMIN0

SW1SIDMIN1

SW1SIDMIN2

SW1SIDMIN3

SW1HI

Bit #

17

18

19

20

13

14

15

16

21

22

23

9

10

11

12

7

8

5

6

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W


Name

SW20

SW21

SW22

SW23

SW24

SW2DVS0

SW2DVS1

SW2DVS2

SW2DVS3

SW2DVS4

SW2STBY0

SW2STBY1

SW2STBY2

SW2STBY3

SW2STBY4

SW2SIDMAX0

SW2SIDMAX1

SW2SIDMAX2

SW2SIDMAX3

SW2SIDMIN0

SW2SIDMIN1

SW2SIDMIN2

SW2SIDMIN3

SW2HI

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

NONE

NONE

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

RESETB

RESETB

NONE

Reset

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

NONE

Default

0

0

0

1

0

1

*

*

0

1

*

*

*

*

*

*

*

*

*

Description

SW1 setting in DVS mode

SW1 setting in Standby mode

SW1 SID mode maximum level

SW1 SID mode minimum level (leading 0 implied)

SW1 output range selection

Default

*

0

*

*

*

*

*

*

*

*

*

*

*

*

*

*

1

*

0

0

1

0

1

0

Description


SW2 setting in DVS mode


SW2 SID mode maximum level

SW2 SID mode minimum level (leading 0 implied)


MC13892

136






Name

SW30

SW31

SW32

SW33

SW34

Spare

Spare

Spare

Spare

Spare

SW3STBY0

SW3STBY1

SW3STBY2

SW3STBY3

SW3STBY4

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Reserved

SW3HI

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R

R

R/W

R

R

R

R


Name

SW40

SW41

SW42

SW43

SW44

Spare

Spare

Spare

Spare

Spare

SW4STBY0

SW4STBY1

SW4STBY2

SW4STBY3

SW4STBY4

Bit #

12

13

14

10

11

8

9

6

7

4

5

2

3

0

1

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

NONE

Reset

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

Reset

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

Default

*

0

*

*

*

*

*

*

*

*

*

*

*

*

*

*

0

*

0

0

0

0

0

0

Description


For future use


Not available

For future use


Default

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

Description


For future use


SPI BITMAP





MC13892

137

SPI BITMAP


Name

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

SW4HI

Bit #

19

20

21

22

23

15

16

17

18

R/W

R

R

R

R

R/W

R

R

R

R

Reset

NONE

Default

0

0

0

0

*

0

0

0

0

Not available

Description



Name

SW1MODE0

SW1MODE1

SW1MODE2

SW1MODE3

SW1MHMODE

SW1UOMODE

SW1DVSSPEED0

SW1DVSSPEED1

SIDEN

Reserved

SW2MODE0

SW2MODE1

SW2MODE2

SW2MODE3

SW2MHMODE

SW2UOMODE

SW2DVSSPEED0

SW2DVSSPEED1

PLLEN

PLLX0

PLLX1

PLLX2

SWILIMB

Reserved

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

Reset

RESETB

RESETB

RESETB

RESETB

OFFB

OFFB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

OFFB

OFFB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

Default

0

0

0

1

0

1

0

0

1

0

0

0

0

1

0

1

0

0

1

0

0

1

0

0

SW1 operating mode

SW1 Memory Hold mode

SW1 User Off mode

SW1 DVS speed setting

SID mode enable

For future use

SW2 operating mode


SW2 User Off mode

SW2 DVS speed setting

Switcher PLL enable

Description

Switcher PLL multiplication factor

Switcher current limit disable

For future use

Notes

97.

SWxMODE[3:0] bits will be reset to their default values by the startup sequencer based on PUMS settings. An enabled switcher will default to PWM mode (no pulse skipping) for both Normal and Standby operation.


Name

SW3MODE0

SW3MODE1

SW3MODE2

SW3MODE3

SW3MHMODE

SW3UOMODE

Bit #

2

3

0

1

4

5

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

RESETB

RESETB

RESETB

RESETB

OFFB

OFFB

Default

0

1

0

1

0

0

SW3 operating mode

Description


SW3 User Off mode

MC13892

138





SPI BITMAP


Name

Unused

Unused

SW4MODE0

SW4MODE1

SW4MODE2

SW4MODE3

SW4MHMODE

SW4UOMODE

Unused

Unused

Unused

Unused

Unused

Unused

SWBSTEN

Unused

Unused

Unused

Bit #

18

19

20

21

14

15

16

17

22

23

10

11

12

13

8

9

6

7

R/W

R

R

R/W

R

R

R

R

R

R

R

R

R

R/W

R/W

R/W

R/W

R/W

R/W

Reset

RESETB

RESETB

RESETB

RESETB

OFFB

OFFB

NONE

Default

*

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

0

Not available

SW4 operating mode


SW4 User Off mode

Not available

SWBST enable

Not available

Description

Notes

98.

SWxMODE[3:0] bits will be reset to their default values by the startup sequencer based on PUMS settings. An enabled switcher will default to PWM mode (no pulse skipping) for both Normal and Standby operation.

Table 142. Register 30, Regulator Setting 0

Name

VCAM0

VCAM1

Spare

Unused

Unused

Unused

Unused

Unused

VGEN10

VGEN11

Unused

Unused

VDIG0

VDIG1

VGEN20

VGEN21

VGEN22

VPLL0

VPLL1

VUSB20

VUSB21

Unused

VGEN3

Unused

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

Reset

RESETB

RESETB

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

RESETB

RESETB

RESETB

RESETB

R/W

R/W

R/W

R/W

R/W

R/W

R

R/W

R

R/W

R/W

R

R

R/W

R/W

R/W

R/W

R

R

R

R

R/W

R/W

R/W

R

Default

1

0

*

0

*

*

*

*

*

*

*

*

0

0

0

0

0

0

0

0

0

0

0

1

VGEN1 setting

Not available

VDIG setting

VGEN2 setting

VPLL setting

VUSB2 setting

Not available

VGEN3 setting

Not available

VCAM setting

For future use

Not available

Not available

Not available

Not available

Not available

Description





MC13892

139

SPI BITMAP

Table 143. Register 31, Regulator Setting 1

Name

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

VSD12

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Reserved

Reserved

VVIDEO0

VVIDEO1

VAUDIO0

VAUDIO1

VSD10

VSD11

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

Reset

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

R/W

R

R

R

R

R/W

R

R

R

R

R

R/W

R/W

R/W

R/W

R/W

R/W

R

R

R

R

R

R

R

R

Table 144. Register 32, Regulator Mode 0

Name

VGEN1EN

VGEN1STBY

VGEN1MODE

VIOHIEN

VIOHISTBY

Spare

Unused

Unused

Unused

VDIGEN

VDIGSTBY

Spare

VGEN2EN

VGEN2STBY

VGEN2MODE

VPLLEN

VPLLSTBY

Spare

VUSB2EN

VUSB2STBY

Spare

Bit #

12

13

14

15

8

9

10

11

16

17

18

19

20

6

7

4

5

2

3

0

1

Reset

RESETB

RESETB

RESETB

NONE

RESETB

RESETB

NONE

RESETB

RESETB

NONE

RESETB

RESETB

NONE

RESETB

RESETB

RESETB

RESETB

RESETB

R/W

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R

Default

0

0

0

0

0

0

1

0

1

1

1

0

0

1

0

0

0

0

0

0

0

0

0

0

For future use

VVIDEO setting

VAUDIO setting

VSD setting

Not available

Description

Default

0

*

*

0

0

0

0

*

0

0

0

0

0

0

0

0

0

0

*

0

0

Description

VGEN1 enable

VGEN1 controlled by standby

VGEN1 operating mode

VIOHI enable

VIOHI controlled by standby

For future use

Not available

Not available

Not available

VDIG enable

VDIG controlled by standby

For future use

VGEN2 enable

VGEN2 controlled by standby


VPLL enable

VPLL controlled by standby

For future use

VUSB2 enable

VUSB2 controlled by standby

For future use

MC13892

140





SPI BITMAP


Name

Unused

Unused

Unused

Bit #

21

22

23

R/W

R

R

R

Reset


Name

VGEN3EN

VGEN3STBY

VGEN3MODE

VGEN3CONFIG

Reserved

Spare

VCAMEN

VCAMSTBY

VCAMMODE

VCAMCONFIG

Unused

Reserved

VVIDEOEN

VIDEOSTBY

VVIDEOMODE

VAUDIOEN

VAUDIOSTBY

Spare

VSDEN

VSDSTBY

VSDMODE

Unused

Unused

Unused

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

Reset

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

R/W

R/W

R/W

R

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R

R

Table 146. Register 34, Power Miscellaneous

Name

REGSCPEN

Unused

Unused

Unused

Unused

Unused

GPO1EN

GPO1STBY

GPO2EN

GPO2STBY

GPO3EN

GPO3STBY

GPO4EN

GPO4STBY

Unused

Bit #

12

13

14

8

9

10

11

6

7

4

5

2

3

0

1

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R/W

R

R

R

R

R

R/W

R/W

Reset

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

Default

0

0

0

Not available

Description

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Description

VGEN3 enable

VGEN3controlled by standby


VGEN3 with external PNP

For future use

For future use

VCAM enable

VCAM controlled by standby

VCAM operating mode

VCAM with external PNP

Not available

For future use

VVIDEO enable

VVIDEO controlled by standby

VVIDEO operating mode

VAUDIO enable

VAUDIO controlled by standby

For future use

VSD enable

VSD controlled by standby

VSD operating mode

Not available

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Description

Regulator short circuit protection enable

Not available

GPO1 enable

GPO1 controlled by standby

GPO2 enable


GPO3 enable


GPO4 enable


Not available





MC13892

141

SPI BITMAP

Table 146. Register 34, Power Miscellaneous

Name

PWGT1SPIEN

PWGT2SPIEN

Spare

Unused

Unused

Unused

GPO4ADIN

Unused

Unused

Bit #

19

20

21

22

23

15

16

17

18

R/W

R/W

R/W

R/W

R

R

R

R/W

R

R

Reset

RESETB

RESETB

RESETB

RESETB


Name

Unused

Bit #

23-0

R/W

R


Name

Unused

Bit #

23-0

R/W

R

Reset

Reset


Name

Unused

Bit #

23-0

R/W

R


Name

Unused

Bit #

23-0

R/W

R

Reset

Reset


Name

Unused

Bit #

23-0

R/W

R


Name

Unused

Bit #

23-0

R/W

R


Name

Unused

Bit #

23-0

R/W

R


Name

Unused

Bit #

23-0

R/W

R

Reset

Reset

Reset

Reset

Default

0

Default

0

Default

0

Default

0

Default

0

Default

0

Default

0

Default

0

Default

1

0

0

0

0

0

0

1

1

Power Gate 1 enable

Power Gate 2 enable

For future use

Description

Not available

GPO4 configured as ADC input (GPO drive tri-stated)

Not available

Not available

Not available

Not available

Not available

Not available

Not available

Not available

Not available

Description

Description

Description

Description

Description

Description

Description

Description

MC13892

142





SPI BITMAP

Table 155. Register 43, ADC 0

Name

LICELLCON

CHRGICON

BATICON

BUFFEN

ADIN7SEL0

ADIN7SEL1

Unused

Unused

ADRESET

ADIN7DIV

TSREFEN

Reserved

TSMOD0

TSMOD1

TSMOD2

CHRGRAWDIV

ADINC1

ADINC2

Unused

Spare

Unused

Unused

Unused

ADCBIS0

Bit #

12

13

14

15

10

11

8

9

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

RWM

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R

R

R

R

W

R/W

R/W

R

R/W


Name

ADA20

ADA21

ADA22

ATO0

ATO1

ATO2

ATO3

ATO4

ADEN

RAND

ADCCAL

ADSEL

TRIGMASK

ADA10

ADA11

ADA12

ATO5

ATO6

ATO7

ATOX

ASC

ADTRIGIGN

Bit #

12

13

14

15

10

11

8

9

6

7

4

5

2

3

0

1

16

17

18

19

20

21

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

RWM

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

RWM

R/W

Reset

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

Reset

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Default

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Description

Enables lithium cell reading

Enables charge current reading

Enables battery current reading

Input buffer enable

GP ADC Channel 7 mux selection 0

GP ADC Channel 7 mux selection 1

Not available

Reset GP ADC system

Divide by 2 enable for ADIN7

Enables the touch screen reference

For future use

Sets the touch screen interface mode

Sets CHRGRAW scaling to divide by 5

Auto increment for ADA1

Auto increment for ADA2

Not available

For future use

Not available

Access to the ADCBIS control

Description

Enables the ADC

Sets the single channel mode

ADC Calibration

Selects the set of inputs

Trigger event masking

Channel selection 1

Channel selection 2

Delay before first conversion

Sets ATO delay for any conversion

Starts conversion

Ignores the ADTRIG input





MC13892

143

SPI BITMAP


Name

ADONESHOT

ADCBIS1

Bit #

22

23

R/W

R/W

W


Name

ADD16

ADD17

ADD18

ADD19

Spare

Spare

ADD20

ADD21

Spare

Spare

ADD10

ADD11

ADD12

ADD13

ADD14

ADD15

ADD22

ADD23

ADD24

ADD25

ADD26

ADD27

ADD28

ADD29

Bit #

12

13

14

15

10

11

8

9

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R


Name

Unused

Unused

Unused

Unused

Unused

Unused

ICID0

ICID1

ICID2

Bit #

6

7

4

5

8

2

3

0

1

R/W

R

R

R

R

R

R

R

R

R

Reset

RESETB

RESETB

Default

0

0

Description

Single trigger event only

Access to the ADCBIS control

Reset

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

Reset

NONE

NONE

NONE

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

For 12-bit use

Description

Results for channel selection 1

For 12-bit use

Results for channel selection 2

Default

1

1

0

0

1

0

0

0

0

Not available

Generation ID

Description

MC13892

144






Name

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Reserved

Bit #

21

22

23

17

18

19

20

13

14

15

16

9

10

11

12

R/W

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R


Name

Spare

Spare

ADDBIS10

ADDBIS11

ADDBIS12

ADDBIS13

ADDBIS14

ADDBIS15

ADDBIS16

ADDBIS17

ADDBIS18

ADDBIS19

Spare

Spare

ADDBIS20

ADDBIS21

ADDBIS22

ADDBIS23

ADDBIS24

ADDBIS25

ADDBIS26

ADDBIS27

ADDBIS28

ADDBIS29

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

Reset Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Not available

For future use

Description

Reset

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

NONE

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

For 12-bit use

Description

Result for channel selection 1 of ADCBIS

For 12-bit use

Result for channel selection 2 of ADCBIS

SPI BITMAP





MC13892

145

SPI BITMAP

Table 160. Register 48, Charger 0

Name

VCHRG0

VCHRG1

VCHRG2

ICHRG0

ICHRG1

ICHRG2

ICHRG3

TREN

ACKLPB

THCHKB

FETOVRD

FETCTRL

Spare

RVRSMODE

Unused

PLIM0

PLIM1

PLIMDIS

CHRGLEDEN

CHGTMRRST

CHGRESTART

CHGAUTOB

CYCLB

CHGAUTOVIB

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R/W

R/W

R/W

R/W

R/W

RWM

R

R/W

R/W

R/W

R/W

RWM

RWM

RWM

RWM

R/W

R/W

R/W

R/W

RWM

RWM

R/W

R/W

R/W

Table 161. Register 49, USB 0

Name

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Spare

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Unused

Unused

Reserved

Reserved

Reserved

Bit #

12

13

14

15

10

11

8

9

6

7

4

5

2

3

0

1

16

17

18

19

20

21

R/W

R

R

R

R

R

R

R

R

R

R

R/W

R

R

R

R

R

R

R

R

R

R

R

Reset

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

Reset

RESETB

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

0

0

0

0

0

0

Default

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

Description

Sets the charge regulator output voltage

Sets the main charger DAC current

Enables the internal trickle charger current

Acknowledge Low-power Boot

Battery thermistor check disable

Allows BATTFET Control

BATTFET Control

For future use

Reverse mode enable

Not available

Power limiter setting

Power limiter disable

CHRGLED enable

Charge timer reset

Restarts charger state machine

Avoids automatic charging while on

Disables cycling

Allows V and I programming

For future use

For future use

Not available

For future use

Description

MC13892

146





SPI BITMAP

Table 161. Register 49, USB 0

Name

IDPUCNTRL

Reserved

Bit #

22

23

R/W

R/W

R

Reset

RESETB

Table 162. Register 50, Charger USB 1

Name

VUSBIN

Unused

Unused

0

1

2

Bit # R/W

R/W

R

R

Reset

NONE

VUSBEN 3 R/W

RESETB

NONE

Unused

Unused

Reserved

Reserved

ID100KPU

Reserved

OTGSWBSTEN

Reserved

Reserved

Reserved

Unused

Unused

Reserved

Spare

Spare

Unused

Unused

Unused

Unused

Unused

16

17

18

19

12

13

14

15

20

21

22

23

8

9

10

11

6

7

4

5

R

R

R

R

R

R

R

R

R

R/W

R/W

R

R

R

R

R

R/W

R

R/W

R

RESETB

RESETB

RESETB

RESETB

Default

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

*

0

*

0

0

Default

Table 163. Register 51, LED Control 0

Name

Spare

LEDMDHI

LEDMDRAMP

LEDMDDC0

LEDMDDC1

LEDMDDC2

LEDMDDC3

LEDMDDC4

LEDMDDC5

LEDMD0

LEDMD1

LEDMD2

Spare

LEDADHI

LEDADRAMP

Bit #

12

13

14

8

9

10

11

6

7

4

5

2

3

0

1

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Default

Description

UID pin pull up source select

For future use

Description

Slave or Host configuration for VBUS

Not available

VUSB enable (PUMS2=Open)

Also reset to 1 by invalid VBUS

VUSB enable (PUMS2=GND)

Not available

For future use

Switches in 100K UID pull-up

For future use

Enable SWBST for USB OTG mode

For future use

Not available

For future use

For future use

Not available

Description

For future use

Main display driver high current mode

Main display driver ramp enable

Main display driver duty cycle

Main display driver current setting

For future use

Auxiliary display driver high current mode

Auxiliary display driver ramp enable





MC13892

147

SPI BITMAP


Name

LEDADDC0

LEDADDC1

LEDADDC2

LEDADDC3

LEDADDC4

LEDADDC5

LEDAD0

LEDAD1

LEDAD2

Bit #

19

20

21

22

23

15

16

17

18

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB


Name

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Spare

LEDKPHI

LEDKPRAMP

LEDKPDC0

LEDKPDC1

LEDKPDC2

LEDKPDC3

LEDKPDC4

LEDKPDC5

LEDKP0

LEDKP1

LEDKP2

Spare

Spare

Spare

Unused

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R

R

R

R

R

R

R

Reset

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB


Name

LEDRPER0

LEDRPER1

LEDRRAMP

LEDRDC0

LEDRDC1

LEDRDC2

LEDRDC3

LEDRDC4

LEDRDC5

6

7

4

5

8

2

3

0

1

Bit # R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

0

0

0

0

0

0

0

0

0

Default

0

0

0

0

0

0

0

0

0

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Default

For future use

Not available

Description

Auxiliary display driver duty cycle

Auxiliary display driver current setting

Description

For future use

Keypad driver high current mode

Keypad driver ramp enable

Keypad driver duty cycle

Keypad driver current setting

Not available

Description

Red channel blink period

Red channel driver ramp enable

Red channel driver duty cycle

MC13892

148





SPI BITMAP


Name

LEDR0

LEDR1

LEDR2

LEDGPER0

LEDGPER1

LEDGRAMP

LEDGDC0

LEDGDC1

LEDGDC2

LEDGDC3

LEDGDC4

LEDGDC5

LEDG0

LEDG1

LEDG2

Bit #

21

22

23

17

18

19

20

13

14

15

16

9

10

11

12

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB


Name

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

LEDBPER0

LEDBPER1

LEDBRAMP

LEDBDC0

LEDBDC1

LEDBDC2

LEDBDC3

LEDBDC4

LEDBDC5

LEDB0

LEDB1

LEDB2

LEDSWBSTEN

Spare

Spare

Unused

Bit #

12

13

14

15

8

9

10

11

6

7

4

5

2

3

0

1

20

21

22

23

16

17

18

19

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R

R

R

R

R

R

R

Reset

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

RESETB

Table 167. Register 55, Not Used

Name

Unused

Bit #

23-0

R/W

R

Reset

0

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Default

Description

Red channel driver current setting

Green channel blink period

Green channel driver ramp enable

Green channel driver duty cycle

Green channel driver current setting

Description

Blue channel blink period

Blue channel driver ramp enable

Blue channel driver duty cycle

Blue channel driver current setting

Enable SWBST for RGB LED’s

For future use

Not available

Not available

Description





MC13892

149

SPI BITMAP

Table 168. Register 56, Not Used

Name

Unused

Bit #

23-0

R/W

R

Reset

Table 169. Register 57, FSL Use Only

Name

FSL Use Only

Bit #

23-0

R/W

R/W

Reset

RTCPORB


Name

FSL Use Only

Bit #

23-0

R/W

R/W

Reset

RTCPORB

0

Default

Default

FSL

Default

FSL

Not available


Name

FSL Use Only

Bit #

23-0

R/W

R/W

Reset

RTCPORB


Name

FSL Use Only

Bit #

23-0

R/W

R/W

Reset

RTCPORB


Name

FSL Use Only

Bit #

23:0

R/W

R/W

Reset

RTCPORB


Name

FSL Use Only

Bit #

23:0

R/W

R/W

Reset

RTCPORB


Name

FSL Use Only

Bit #

23:0

R/W

R/W

Reset

RTCPORB

Default

FSL

Default

FSL

Default

FSL

Default

FSL

Default

FSL

Description

Description

Description

Description

Description

Description

Description

Description

MC13892

150





TYPICAL APPLICATIONS

TYPICAL APPLICATIONS

Figure 35

contains a typical application of the MC13892. For convenience, components for use with the MC13892 are cited within this document. Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.

From Extenal Boost

Main

Battery

10u

Tied to

BATTISNSCC

R1

20m

M3

BP

10u

R2

100m

M2 M1

Charger/USB Input

(Tied to VBUS)

2.2u

SWBST

GNDADC

General Purpose ADC Inputs: i.e., Battery pack thermistor,

PA thermistor, Light Sensor, Etc.

Touch

Screen

Interface

ADIN5

ADIN6

ADIN7

TSX1

TSX2

TSY1

TSY2

TSREF

ADTRIG

From AP

From M3/R1 connection

(needs to be separate route from

BATTISNS)

BATTISNSCC

CFP

10uF

CFM

Battery Interface &

Protection

Charger Interface and Control:

4 bit DAC, Clamp, Protection,

Trickle Generation

LICELL, UID, Die Temp, GPO4

Voltage /

Current

Sensing &

Translation

Touch

Screen

Interface

BATT

MUX

Coulomb

Counter

10 Bit GP

ADC

Trigger

Handling

CCOUT

To SPI

A/D Result

A/D

Control

Coin Cell

Battery

SW4

AP CSPI

SPIVCC

CS

CLK

MOSI

MISO

GNDSPI

2.2u

100n

2.2u

VCORE

VCOREDIG

REFCORE

GNDCORE

To/From

USB Cable

ID

CHRGRAW

UID

UVBUS

From AP

VBUSEN

SWBST

VINUSB

VUSB

2.2u

OTG

5V

VUSB

Regulator

100n

LICELL

BP

Li Cell

Charger

SPI

Interface

+

Muxed

I2C

Optional

Interface

Reference

Generation

VBUS/ID

Detectors

LCELL

Switch

Shift Register

SPI

Registers

Shift Register

32 KHz

Internal

Osc

32 KHz

Crystal

Osc

To Enables & Control

Die Temp &

Thermal Warning

Detection

To Interrupt

Section

Package Pin Legend

MC13892

IC

Output Pin

Input Pin

Bi-directional Pin

MC13892

SPI

Control

Logic

Trim-In-Package

PUMS

Startup

Sequencer

Decode

Trim?

To

Trimmed

Circuits

Control

Logic

Backlight

LED Drive

SPI Result

Registers

Interrupt

Inputs

Enables &

Control

Core Control Logic, Timers, & Interrupts

Tri-Color

LED Drive

SW1

1050 mA

Buck

SW2

800 mA

Buck

SW3

800 mA

Buck

SW4

800 mA

Buck

DVS

CONTROL

PLL

Monitor

Timer

RTC +

Calibration

32 KHz

Buffers

Switchers

Best of

Supply

VSRTC

SWBST

300 mA

Boost

SPI Control

VVIDEO

VUSB2

VAUDIO

VVIOHI

VPLL

VDIG

VCAM

VSD

VGEN1

VGEN2

VGEN3

GPO

Control

PWR Gate

Drive & Chg

Pump

O/P

Drive

O/P

Drive

O/P

Drive

O/P

Drive

O/P

Drive

PWGTDRV1

PWGTDRV2

SW1IN

SW1OUT

GNDSW1

SW1FB

SW2IN

SW2OUT

GNDSW2

SW2FB

SW3IN

SW3OUT

GNDSW3

SW3FB

SW4IN

SW4OUT

GNDSW4

SW4FB

DVS1

DVS2

From AP

From AP

SWBSTIN

SWBSTOUT

SWBSTFB

GNDSWBST

BP

User Off

SW3

Processor

Internal

Memory

To 1.2V

Peripherals

SW4

BP

4.7u

BP

4.7u

1.5u

User Off, Memory Hold

SW1

Output

2 x22u

SW2

Output

2.2u

10u

BP

4.7u

To Memory

To 1.8V

Peripherals

2.2u

SW3

Output

10u

BP

4.7u

2.2u

SW4

Output

10u

BP

2.2u

4.7u

10u

SWBST

Output

(Boost)

Pass

FET

Pass

FET

Pass

FET

Pass

FET

Pass

FET

Pass

FET

Pass

FET

BP

VVIDEODRV

VVIDEO

VINUSB2

VUSB2

BP

2.2u

2.2u

VIINAUDIO

VAUDIO

VINIOHI

VIOHI

VINPLL

VPLL

BP

BP

BP

2.2u

2.2u

2.2u

VINDIG

VDIG

BP

VINCAMDRV

BP

2.2u

2.2u

VCAM

VSDDRV

VSD

BP

VGEN1DRV

VGEN1

2.2u

BP

VGEN2DRV

VGEN2

BP

2.2u

2.2u

BP

VINGEN3DRV

VGEN3

2.2u

GNDREG1

GNDREG2

GNDREG3

To/From

Peripherals

To/From

AP

1.0u

18p

32.768 KHz

Crystal

18p

To GND,

Open,

VCOREDIG or VCORE

On/Off

Button

To/From

AP

Figure 35. MC13892 Typical Application





MC13892

151

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit

www.freescale.com

and perform a keyword search using the “98A” listed below.

MC13892

152

VK SUFFIX

139-PIN

98ASA10820D

REVISION 0





PACKAGING






VK SUFFIX

139-PIN

98ASA10820D

REVISION 0

MC13892

153

PACKAGING


MC13892

154

VL SUFFIX

186-PIN

98ASA10849D

REVISION 0





PACKAGING






VL SUFFIX

186-PIN

98ASA10849D

REVISION 0

MC13892

155

ADDITIONAL DOCUMENTATION

ADDITIONAL DOCUMENTATION

Table 176. Additional Documentation

Document Number

MC13892ER

MC13783

Description

MC13892ER, Silicon Mask Errata

MC13783, Power Management and Audio Circuit

MC13892

156





REVISION HISTORY

REVISION HISTORY

REVISION DATE

14.0

15.0

16.0

17.0

18.0

19.0

DESCRIPTION

11/2011 • Added MC13892CJVK and MC13892CJVL to the ordering information

• Changed RT from 45 k to 4.5 k in Table 73

for T

HIGH

• In the Static Electrical Characteristics table, changed Input Operating Voltage - CHRGRAW from 17 V to 5.6 V on page 24.

• Changed Input Operating Voltage - CHRGRAW from 17 V to 5.6 V in Table 64 .

4/2012

• Added MC13892DJVK and MC13892DJVL to

Table 1, MC13892 Device Variations

.

4/2012

• Corrected Global Reset Functions in Table 1

5/2012

• Clarified the Global Reset function for silicon versions A, B, C and D throughout the document

• Section

PWRON1, 2 and 3 on page 37

• Section

Global System Restart on page 60

•

Table 125, Register 13, Power Control 0

10/2012 • Reformatted Table 111 so it can be seen in its entirety, rotated 90 degrees

• Rotated tables 112-114 to portrait format.

• Readjusted the footer position to match template.

4/2013

• No technical changes. Revised back page. Updated document properties. Added SMARTMOS sentence to first paragraph.

4/2014

• Added Additional note to Battery Thermistor Check Operation





MC13892

157

How to Reach Us:

Home Page:

freescale.com

Web Support:

freescale.com/support

Information in this document is provided solely to enable system and software implementers to use Freescale products.

There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document.

Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others.

Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions .

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.

© 2014 Freescale Semiconductor, Inc.

Document Number: MC13892

Rev. 19.0

4/2014