CPCI-6200 Installation and Use (May 2015)

CPCI-6200

Installation and Use

P/N: 6806800J66E

May 2015

©

Copyright 2015 Artesyn Embedded Technologies, Inc.

All rights reserved.

Trademarks

Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of

Artesyn Embedded Technologies, Inc.

©

2015 Artesyn Embedded Technologies, Inc. All other product or service names are the property of their respective owners.

Intel

®

is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

Java

™

and all other Java-based marks are trademarks or registered trademarks of Oracle America, Inc. in the U.S. and other countries.

Microsoft

®

, Windows

®

and Windows Me

®

are registered trademarks of Microsoft Corporation; and Windows XP

™

is a trademark of

Microsoft Corporation.

PICMG

®

, CompactPCI

®

, AdvancedTCA

™

and the PICMG, CompactPCI and AdvancedTCA logos are registered trademarks of the PCI

Industrial Computer Manufacturers Group.

UNIX

®

is a registered trademark of The Open Group in the United States and other countries.

Notice

While reasonable efforts have been made to assure the accuracy of this document, Artesyn assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Artesyn reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes.

Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to an Artesyn website. The text itself may not be published commercially in print or electronic form, edited, translated, or otherwise altered without the permission of Artesyn.

It is possible that this publication may contain reference to or information about Artesyn products (machines and programs), programming, or services that are not available in your country. Such references or information must not be construed to mean that

Artesyn intends to announce such Artesyn products, programming, or services in your country.

Limited and Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Artesyn.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in

Technical Data clause at DFARS 252.227-7013 (Nov. 1995) and of the Rights in Noncommercial Computer Software and

Documentation clause at DFARS 252.227-7014 (Jun. 1995).

Contact Address

Artesyn Embedded Technologies

Marketing Communications

2900 S. Diablo Way, Suite 190

Tempe, Arizona 85282


Lilienthalstr. 17-19

85579 Neubiberg/Munich

Germany

About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Safety Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Sicherheitshinweise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.2 Standard Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.3 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.4.1 Supported Board Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.4.2 Board Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.5 Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2 Hardware Preparation and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.2 Unpacking the CPCI Baseboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.3 Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.4 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.5 Installing Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.5.1 Installing a PMC Module on the CPCI Baseboard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.5.2 Installing the Rear Transition Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.6 Preparing the Baseboard for Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.6.1 Inspecting the CPCI Baseboard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.6.2 Equipment Required for Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2.6.3 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2.6.3.1 Board Configuration Switch, S1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2.6.3.2 IPMI Configuration Switch, S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.7 Installing the CPCI Baseboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.8 Removing the CPCI Baseboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

2.9 Connecting to a Console Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.10 Factory-Installed Linux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

CPCI-6200 Installation and Use (6806800J66E)

3

3 Controls, LEDs, and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.2 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.3 Connectors and Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.3.1 CPCI Bus Connector, J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.3.2 CPCI Bus Connector, J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.3.3 CPCI User I/O Connector, J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.3.4 CPCI Connector, J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.3.5 CPCI User I/O Connector, J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.3.6 PCI Mezzanine Card (PMC) Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.3.7 Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.3.8 USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.3.9 Serial Port Connector, J16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.3.10 Board Insertion/Extraction Connector, P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.3.11 DDR3 SO-DIMM Connectors, XJ1 and XJ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.3.12 PCI Express Expansion Connector, J17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.3.13 IPMI Debug and FW Programming Header, P3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.3.14 Processor Debug Header, P4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.3.15 Boundary Scan Header, P5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.3.16 Processor COP Header, P6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.3.17 PCI Express Switch Header, P7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.4 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.4.1 Onboard Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.4.2 Reset/Abort Switch, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.5 Front Panel LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.6 Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.2 MPC8572 Integrated Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.3 I2C Serial Interface and Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.3.1 I2C Bus 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.3.2 I2C Bus 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.3.3 I2C Bus 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.3.4 I2C Bus 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4


Contents

4.3.5 I2C Bus 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.3.6 I2C Bus 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.4 System Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.5 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.6 Ethernet Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.7 Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.7.1 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.7.2 MRAM (Magnetoresistive Random Access Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.7.3 Control and Timers PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.7.4 Serial COM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.8 DUART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.9 PCI Express Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.10 PCI/PCI-X Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.10.1 PCI Mezzanine Card Sites (PCI-X Bus 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.10.2 PCI 6466 Universal Bridge (PCI Bus 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.10.3 USB (PCI Bus 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

4.10.4 PCI Bus Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

4.11 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

4.11.1 System Controller Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.11.2 Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.11.3 Stand Alone Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.12 PCI Express Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.13 System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.14 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4.15 MPC8572 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.16 Reset Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.16.1 Abort/Reset Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.16.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

4.17 RTC Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.18 IPMI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.18.1 Programming the IPMI Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.19 Programmable Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.19.1 Local Bus Control CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.19.2 Reset CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.19.3 CPCI Control CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.19.4 Serial Multiplexer CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106


5

5 Transition Module Preparation and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

5.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.3 Preparing the Transition Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5.4 Rear Panel Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.5 On-Board Connectors and Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.5.1 IDE CompactFlash Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.5.2 PMC I/O Module Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5.5.2.1 Host IO Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.5.2.2 PMC I/O Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.5.3 CompactPCI User I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5.5.4 CompactPCI User I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.5.5 10/100/1000BaseTx Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

5.5.6 COM1 And COM2 Connectors (MXP Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

5.5.7 RJ-45 to DB-9 Adapter for COM1 to PC COM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

5.6 Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

5.6.1 CompactFlash Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

5.6.2 COM1 and COM2 Asynchronous Serial Ports Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

5.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

5.7.1 IDE Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

5.7.2 Ethernet Interface (CompactPCI Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5.7.3 Hot-Swap Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5.7.4 Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5.7.5 PMC I/O Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

5.7.6 Asynchronous Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

5.7.6.1 I/O Signal Multiplexing (IOMX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.7.6.2 Serial Port Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

5.7.6.3 Asynchronous Serial Port Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

5.7.6.4 Port Configuration Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

5.7.7 PMC I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5.7.8 PMC I/O Module Form Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.7.9 PMC I/O Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.7.10 Host I/O Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.7.11 PMC I/O Module Presence Detection and Identification . . . . . . . . . . . . . . . . . . . . . . . . . . 135

5.8 Installing the PIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

6


Contents

5.9 Installing the Transition Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

5.10 Removing the Transition Module in a Hot-Swap Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

6 MOTLoad Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

6.2 MOTLoad Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

6.3 MOTLoad Implementation and Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

6.4 MOTLoad Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

6.5 MOTLoad Utility Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

6.6 MOTLoad Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

6.7 Using MOTLoad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

6.7.1 Command Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

6.7.2 Command Line Help. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

6.7.3 Command Line Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

6.8 MOTLoad Command List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

7 Control via IPMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

7.1 Standard IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

7.1.1 Global IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

7.1.2 Watchdog Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

7.1.3 IPMI Messaging Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

7.1.4 SEL Device Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

7.1.5 SDR Repository Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

7.1.6 FRU Inventory Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

7.1.7 Sensor Device Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

7.1.8 Chassis Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

7.2 PICMG 2.9 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

7.3 Artesyn Specific Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

7.3.1 Firmware Upgrade Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

7.3.1.1 Start Firmware Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

7.3.1.2 Continue Firmware Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

7.3.1.3 Finish Firmware Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

7.3.2 OEM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

7.3.2.1 BMC/PM Change Role . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164


7

7.3.2.2 Get Geographical Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

7.4 FRU Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

7.5 Sensor Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

8 Memory Maps and Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

8.1 Default Processor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

8.2 CPCI-6200 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

8.3 Local Bus Controller Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

8.4 System I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

8.4.1 System Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

8.4.2 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

8.4.3 Front Panel LEDs Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

8.4.4 NOR Flash Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

8.4.5 Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

8.4.6 Interrupt Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

8.4.7 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

8.4.8 Presence Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

8.4.9 NAND Flash Chip 1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

8.4.10 NAND Flash Chip 1 Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

8.4.11 NAND Flash Chip 1 Presence Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

8.4.12 NAND Flash Chip 1 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

8.4.13 NAND Flash Chip 2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

8.4.14 NAND Flash Chip 2 Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

8.4.15 NAND Flash Chip 2 Presence Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

8.4.16 NAND Flash Chip 2 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

8.4.17 CPCI Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

8.4.18 Geographic Address Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

8.4.19 Watchdog Timer Load Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

8.4.20 Watchdog Timer Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

8.4.21 Watchdog Timer Resolution Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

8.4.22 Watchdog Timer Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

8.4.23 PLD Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

8.4.24 PLD Date Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

8.4.25 Test Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

8.4.26 Test Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

8


Contents

8.4.27 External Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

8.4.27.1 Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

8.4.27.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

8.4.27.3 Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

8.4.27.4 Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

8.5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

8.6 I2C Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

8.7 PCI/PCI-X Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

8.7.1 PCI IDSEL and Interrupt Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

8.7.2 PCI Vendor and Device IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

8.7.3 PCI Arbitration Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

A Replacing the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

A.1 Battery Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

A.2 Replacing the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

B Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

B.1 Artesyn Embedded Technologies - Embedded Computing Documentation . . . . . . . . . . . . . . . 229

B.2 Manufacturer’s Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

B.3 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231


9

10


List of Tables

Table 3-10

Table 3-11

Table 3-12

Table 3-13

Table 3-14

Table 3-15

Table 3-16

Table 3-17

Table 3-18

Table 3-19

Table 4-1

Table 4-2

Table 4-3

Table 4-4

Table 4-5

Table 4-6

Table 5-1

Table 5-2

Table 5-3

Table 5-4

Table 1-1

Table 1-2

Table 1-3

Table 2-1

Table 2-2

Table 2-3

Table 2-4

Table 3-1

Table 3-2

Table 3-3

Table 3-4

Table 3-5

Table 3-6

Table 3-7

Table 3-8

Table 3-9

Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Order Numbers for Baseboard Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Order Numbers for Related Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

CPCI-6200 Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Baseboard Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

S1 Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

S2 Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Onboard Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

CPCI Bus Connector Pinout, J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

CPCI Bus Connector Pinout, J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

CPCI User I/O Connector Pinout, J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

CPCI User I/O Connector Pinout, J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

PMC Connector Pinout, J11/J21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65



PMC Connector Pin Assignments, J14/J24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Front Panel Latch Pinout, P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

DDR3 SO-DIMMs Pinout, XJ1 and XJ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

PCI Express Expansion Connector Pinout, J17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

IPMI Debug Pinout, P3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Processor Debug Header Pinout, P4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Boundary Scan Header Pinout, P5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

COP Header Pinout, P6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

PCI Express Switch Header Pinout, P7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Front Panel Reset Switch Pinout, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

CPCI-6200 Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

PCI Buses 1 and 2 Frequency Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

System Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Reset Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Programming Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

CPCI-6115-MCPTM Rear Panel Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

On-Board Connectors and Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

CompactFlash IDE Connector Pin Assignments, J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

PMC I/O Module 1 - Host I/O Connector Pin Assignments, J10 . . . . . . . . . . . . . . . . . . . . . . 113


11

List of Tables

Table 7-8

Table 7-9

Table 7-10

Table 7-11

Table 7-12

Table 7-13

Table 7-14

Table 7-15

Table 7-16

Table 7-17

Table 7-18

Table 7-19

Table 7-20

Table 7-21

Table 7-22

Table 7-23

Table 7-24

Table 7-25

Table 7-26

Table 7-27

Table 5-5

Table 5-6

Table 5-7

Table 5-8

Table 5-9

Table 5-10

Table 5-11

Table 5-12

Table 6-1

Table 7-1

Table 7-2

Table 7-3

Table 7-4

Table 7-5

Table 7-6

Table 7-7

12

PMC I/O Module 2 - Host I/O Connector Pin Assignments, J20 . . . . . . . . . . . . . . . . . . . . . . .114

PMC I/O Modules 1 and 2 - PMC I/O Connector Pin Assignments, J14/24 . . . . . . . . . . . . .115

User I/O Connector Pinout, J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

User I/O Connector Pinout, J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

10BaseT/100BaseTx Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

COM1, COM2 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Wire Interconnection List RJ-45 to DB-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Multiplexing Sequence of the IOMX Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

MOTLoad Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Supported Global IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Supported Watchdog Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Supported Watchdog Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

Supported SEL Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

Supported SDR Repository Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Supported FRU Inventory Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Supported Sensor Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Supported Chassis Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Supported PICMG 2.9 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Firmware Upgrade Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

Response Data of Start Firmware Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

Request Data of Continue Firmware Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

Response Data of Continue Firmware Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

Request Data of Finish Firmware Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

Response Data of Finish Firmware Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

OEM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

Request Data of BMC/PM Change Role . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

Response Data of BMC/PM Change Role . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

Request Data of Get Geographical Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

Response Data of Get Geographical Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

FRU Information CPCI-6200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

IPMI Sensors Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

Aggregate T Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Aggregate V Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

CPCI Signal Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

CPU Status Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

Critical IRQ Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171


List of Tables

Table 8-4

Table 8-5

Table 8-6

Table 8-7

Table 8-8

Table 8-9

Table 8-10

Table 8-11

Table 8-12

Table 8-13

Table 8-14

Table 8-15

Table 8-16

Table 8-17

Table 8-18

Table 8-19

Table 8-20

Table 8-21

Table 8-22

Table 8-23

Table 7-28

Table 7-29

Table 7-30

Table 7-31

Table 7-32

Table 7-33

Table 7-34

Table 7-35

Table 7-36

Table 7-37

Table 7-38

Table 7-39

Table 7-40

Table 8-1

Table 8-2

Table 8-3

Ejector Switch Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Max1617Temp Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

CoreTemp Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

SEL Fullness Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Signal Status Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

VCC1_2 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

VCC1_5 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

VCC1_8 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

VCC3_3 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

VCC2_5 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

VCC5_0 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

VCC1_0 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

VPCore Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Default Processor Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

CPCI-6200 Address Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

LBC Memory Map and Chip Select Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

System I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

System Status Register, 0xF200_0000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

System Status Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

System Control Register, 0xF200_0001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

System Control Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Front Panel LED Control/Status Register, 0xF200_0002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Front Panel LED Control/Status Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

NOR Flash Control/Status Register, 0xF200_0003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

NOR Flash Control/Status Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Interrupt Register 1, 0xF200_0004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Interrupt Register 1 Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Interrupt Register 2, 0xF200_0005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Interrupt Register 2 Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Interrupt Mask Register, 0xF200_0006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Presence Detect Register, 0xF200_0008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Presence Detect Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

NAND Flash Chip 1 Control Register, 0xF200_0010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

NAND Flash Chip 1 Control Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

NAND Flash Chip 1 Select Register, 0xF200_0011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202


13

List of Tables

Table 8-40

Table 8-41

Table 8-42

Table 8-43

Table 8-44

Table 8-45

Table 8-46

Table 8-47

Table 8-48

Table 8-49

Table 8-50

Table 8-51

Table 8-52

Table 8-53

Table 8-54

Table 8-55

Table 8-56

Table 8-57

Table 8-58

Table 8-59

Table 8-24

Table 8-25

Table 8-26

Table 8-27

Table 8-28

Table 8-29

Table 8-30

Table 8-31

Table 8-32

Table 8-33

Table 8-34

Table 8-35

Table 8-36

Table 8-37

Table 8-38

Table 8-39

14

NAND Flash Chip 1 Select Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

NAND Flash Chip 1 Presence Register, 0xF200_0012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

NAND Flash Chip 1 Presence Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

NAND Flash Chip 1 Status Register, 0xF200_0013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

NAND Flash Chip 1 Status Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

NAND Flash Chip 2 Control Register, 0xF200_0014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

NAND Flash Chip 2 Control Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

NAND Flash Chip 2 Select Register, 0xF200_0015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

NAND Flash Chip 2 Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

NAND Flash Chip 2 Presence Register, 0xF200_0016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

NAND Flash Chip 2 Presence Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

NAND Flash Chip 2 Status Register, 0xF200_0017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

NAND Flash Chip 2 Status Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

CPCI Control/Status Register, 0xF200_0018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

CPCI Control/Status Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Geographic Address Read Register, 0xF200_0019 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Geographic Address Read Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

Watchdog Timer Load Register, 0xF200_0020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

Watchdog Timer Control Register, 0xF200_0024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

Watchdog Timer Control Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

Watchdog Timer Resolution Register, 0xE200_0025 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Watchdog Timer Resolution Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Watchdog Timer Counter Register, 0xF200_0026 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

PLD Revision Register, 0xF200_0030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

PLD Revision Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

PLD Date Code Register, 0xF200_0034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

PLD Date Code Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

Test Register 1, 0xF200_0038 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

Test Register 2, 0xF200_003C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

Prescaler Register, 0xE202_0000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

Tick Timer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Tick Timer Control Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Tick Timer Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

Tick Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

Interrupt Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

I2C Bus Device Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223


List of Tables

Table 8-60

Table 8-61

Table 8-62

Table B-1

Table B-2

Table B-3

IDSEL and Interrupt Mapping for PCI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Planar PCI Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

PCI Arbitration Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Artesyn Embedded Technologies - Embedded Computing Publications . . . . . . . . . . . . . 229

Manufacturers’ Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231


15

List of Tables

16


List of Figures

Figure 1-1

Figure 1-2

Figure 2-1

Figure 3-1

Figure 3-2

Figure 3-3

Figure 4-1

Figure 4-2

Figure 4-3

Figure 4-4

Figure 4-5

Figure 4-6

Figure 4-7

Figure 4-8

Figure 4-9

Figure 5-1

Figure 5-2

Figure 5-3

Figure 5-4

Figure 5-5

Figure 5-6

Figure 5-7

Figure 5-8

Figure 5-9

Figure 5-10

Figure 8-1

Figure 8-2

Declaration of Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Location of the Product Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Location of Configuration Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

USB Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Serial Port Connector Pinout, J16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

CPCI-6200 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Boot Block A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Boot Block B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

PCI Express Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

System Controller Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Stand Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Routing of Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

CPCI-6200 Clock Distribution Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

CPCI-6115-MCPTM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Connector and Header Locations (MXP Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

CompactFlash Jumper Settings (J2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

COM1 and COM2 Serial Port Jumpers (J6/J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Signal Multiplexing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

P2MX Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

CPCI-6115-MCPTM Serial Ports 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

PMC I/O Module Physical Representation (MXP Version) . . . . . . . . . . . . . . . . . . . . 133

Installing the PIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CPCI-6115-MCPTM Mating Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

CPCI-6200 Memory Map Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

PCI Interrupt Mapping to Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222


17

List of Figures

18


About this Manual

Overview of Contents

This manual is divided into the following chapters and appendices.



Introduction

provides an overview of the features of the product, including ordering and

other product information like the location of labels.







Hardware Preparation and Installation

discusses procedures on installing the CPCI

baseboard, PMC modules, and other accessories.

Controls, LEDs, and Connectors

provides information on connector pinouts and board and

front panel layouts.

Functional Description

discusses the main functional blocks on the product.





MOTLoad Firmware

provides an overview and description of basic MOTLoad use including implementation issues, a list of the initialization sequence, and a description of basic commands.

Control via IPMI

discusses the IPMI commands that the product supports.











Memory Maps and Addresses

provides details on the various registers and addresses used in

the product.

Replacing the Battery

provides instructions on how to replace the onboard battery.

Related Documentation

provides a list of documentation relevant to the product.

Safety Notes

lists the safety notes applicable to the product.

Sicherheitshinweise

lists the German version of the safety notes.

Abbreviations

This document uses the following abbreviations:

Abbreviation

ANSI

BMC

CE

COM

Definition

American National Standard Institute

Base Board Management Controller

Chip Enable

Communications


19



20

LBC

LFM

LSB

MPU

MRAM

MSB

GMII

GPCM

IEEE

IPMB

IPMC

IPMI

I2C

JTAG

ESD

ETSI

FCC

FRU

DMA

DRAM

DUART

ECC

Abbreviation

CPCI

CPLD

COP

CRC

DDR

DIMM

Definition

Compact PCI

Complex Programmable Logic Device

Common On-Chip Processor

Cyclic Redundancy Check

Double Data Rate

Dual Inline Memory Module

Direct Memory Access

Dynamic Random Access Memory

Dual Universal Asynchronous Receiver/Transmitter

Error Correction Code

Electrostatic Sensitive Device

European Telecommunication Standards Institute

Federal Communications Commission

Field Replaceable Unit

Gigabit Media Independent Interface

General Purpose Chip select Machine

Institute of Electrical and Electronics Engineers

Intelligent Platform Management Bus

Intelligent Platform Management Interface Controller

Intelligent Platform Management Interface

Inter Integrated Circuit

Joint Test Access Group

Local Bus Controller

Linear Feet per Minute

Least Significant Byte

Multi Purpose Unit

Magnetoresistive Random Access Memory

Most Significant Byte



PrPMC

Rcv

RTC

RTM

SBC

SDR

SDRAM

SEL

SMBus

SMT

SO-DIMM

SO-UDIMM

SPD

SRAM

PMC

PM

PLD

PLL

PHY

PIC

PIM

PICMG

Abbreviation

Msb

NEBS

NVRAM

PCI

PCIe or PCI-E

PCI-X


Definition

Most Significant Bit

Network Equipment Building System

Non-Volatile Random Access Memory

Peripheral Component Interconnect

Peripheral Component Interconnect Express

Peripheral Component Interconnect -X

Physical Interface

Programmable Interrupt Controller

PCI Mezzanine Card Input/Output Module

PCI Industrial Computer Manufacturers Group

PCI Mezzanine Card

Peripheral Management

Programmable Logic Device

Phase-Locked Loop

Processor PCI Mezzanine Card

Receive

Real-Time Clock

Rear Transition Module

Single Board Computer

Sensor Data Record

Synchronous Dynamic Random Access Memory

System Event Log

System Management Bus

Surface Mount Technology

Small-Outline Dual In-line Memory Module

Small-Outline Unbuffered Dual In-line Memory Module

Serial Presence Detect

Static Random Access Memory

21



Abbreviation

TSEC

UART

VIO

VME

VPD

Definition

Three-Speed Ethernet Controller

Universal Asynchronous Receiver/Transmitter

Input/Output Voltage

Versa Module Eurocard

Vital Product Data

Conventions

The following table describes the conventions used throughout this manual.

Notation

0x00000000

0b0000 bold

Screen

Courier + Bold

.

.

.

...

Reference

File > Exit

<text>

[text]

Description

Typical notation for hexadecimal numbers (digits are

0 through F), for example used for addresses and offsets

Same for binary numbers (digits are 0 and 1)

Used to emphasize a word

Used for on-screen output and code related elements or commands in body text

Used to characterize user input and to separate it from system output

Used for references and for table and figure descriptions

Notation for selecting a submenu

Notation for variables and keys

Notation for software buttons to click on the screen and parameter description

Repeated item for example node 1, node 2, ..., node

12

Omission of information from example/command that is not necessary at the time being

22



Notation

..

|

Description

Ranges, for example: 0..4 means one of the integers

0,1,2,3, and 4 (used in registers)

Logical OR

Indicates a hazardous situation which, if not avoided, could result in death or serious injury

Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury

Indicates a property damage message

No danger encountered. Pay attention to important information

Summary of Changes

This manual has been revised and replaces all prior editions.

Part Number

6806800J66A

6806800J66B

6806800J66C

6806800J66D

6806800J66E

Publication Date

September 2009

December 2010

August 2011

September 2014

May 2015

Description

First edition

Updated

MOTLoad Command List

on page 148

Updated

Appendix P, Safety Notes, on page 25

Re branded to Artesyn template.

Added Chapter 5, Transition Module Preparation and Installation on page 107.


23



24


Safety Notes

This section provides warnings that precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed during all phases of operation, service, and repair of this equipment. You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment.

Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment.

Artesyn intends to provide all necessary information to install and handle the product in this manual. Because of the complexity of this product and its various uses, we do not guarantee that the given information is complete. If you need additional information, ask your Artesyn representative.

This product is a Safety Extra Low Voltage (SELV) device designed to meet the EN60950-1 requirements for Information Technology Equipment. The use of the product in any other application may require safety evaluation specific to that application.

Only personnel trained by Artesyn or persons qualified in electronics or electrical engineering are authorized to install, remove or maintain the product. The information given in this manual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel.

Keep away from live circuits inside the equipment. Operating personnel must not remove equipment covers. Only factory authorized service personnel or other qualified service personnel is allowed to remove equipment covers for internal subassembly or component replacement or any internal adjustment.

Do not install substitute parts or perform any unauthorized modification of the equipment or the warranty may be voided. Contact your local Artesyn representative for service and repair to make sure that all safety features are maintained.

Artesyn and our suppliers take significant steps to make sure that there are no bent pins on the backplane or connector damage to the boards prior to leaving the factory. Bent pins caused by improper installation or by inserting boards with damaged connectors could void the Artesyn warranty for the backplane or boards.

This product operates with dangerous voltages that can cause injury or death. Use extreme caution when handling, testing, and adjusting this equipment and its components.


25

Safety Notes

EMC

FCC Class A

This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules, EN55022. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, can cause harmful interference to radio communications.

Operation of this equipment in a residential area is likely to cause harmful interference in which case the user is required to correct the interference at his own expense.

Use only shielded cables when connecting peripherals to assure that appropriate radio frequency emissions compliance is maintained. Installed blades must have the face plates installed and all vacant slots in the shelf must be covered.

For applications where this product is provided without a face plate, or where the face plate has been removed, your system chassis/enclosure must provide the required electromagnetic interference (EMI) shielding to maintain EMC compliance.

Board products are tested in a representative system to show compliance with the above mentioned requirements. A proper installation in a compliant system maintains the required performance.

As soon as you modify the product or change the default configuration you are responsible for complying with all relevant regulatory standards.

Installation

26

Damage of Circuits

Electrostatic discharge and incorrect installation and removal of the product can damage circuits or shorten their life.

Before touching the product make sure that your are working in an ESD-safe environment or wear an ESD wrist strap or ESD shoes. Hold the product by its edges and do not touch any components or circuits.


Safety Notes

Operation

Battery

High humidity and condensation on surfaces cause short circuits.

Do not operate the product outside the specified environmental limits. Make sure the product is completely dry and there is no moisture on any surface before applying power.

Personal Injury or Death

This product operates with dangerous voltages that can cause injury or death.

Use extreme caution when handling, testing, and adjusting this equipment and its components.

Installing another battery type than the one that is mounted at product delivery may cause data loss since other battery types may be specified for other environments or may have a shorter lifetime.

Only use the same type of lithium battery as is already installed.

PCB and Battery Holder Damage

Removing the battery with a screw driver may damage the PCB or the battery holder.

Do not use a screw driver to remove the battery from its holder.

Incorrect replacement of lithium batteries can result in a hazardous explosion.

When exchanging the on-board lithium battery, make sure that the new and the old battery are exactly the same battery models.

If the respective battery model is not available, contact your local Artesyn sales representative for the availability of alternative officially approved battery models.


27

Safety Notes

Hot Swap

Removing the product with the blue LED still blinking causes data loss.

Wait until the blue LED is permanently illuminated before removing the product.

Data Loss

Removing the RTM with the system power on and the blue LED on the front blade still flashing causes data loss.

Before removing the RTM from a powered system, power down the slot and the front blade’s payload by opening the lower handle of the front blade and wait until the blue LED is permanently ON.

28


Sicherheitshinweise

Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses

Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs, der

Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen enthalten sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für den Betrieb des

Systems innerhalb Ihrer Betriebsumgebung notwendig sind. Wenn Sie diese

Vorsichtsmaßnahmen oder Sicherheitshinweise, die an anderer Stelle diese Handbuchs enthalten sind, nicht beachten, kann das Verletzungen oder Schäden am System zur Folge haben.

Artesyn ist darauf bedacht, alle notwendigen Informationen zum Einbau und zum Umgang mit dem System in diesem Handbuch bereit zu stellen. Da es sich jedoch bei dem System um ein komplexes Produkt mit vielfältigen Einsatzmöglichkeiten handelt, können wir die

Vollständigkeit der im Handbuch enthaltenen Informationen nicht garantieren. Falls Sie weitere Informationen benötigen sollten, wenden Sie sich bitte an die für Sie zuständige

Geschäftsstelle von Artesyn.

Das Produkt wurde entwickelt, um die Sicherheitsanforderungen für SELV Geräte nach der

Norm EN 60950-1 für informationstechnische Einrichtungen zu erfüllen. Die Verwendung des

Produkts in einer anderen Anwendung erfordert eine Sicherheitsüberprüfung für diese spezifische Anwendung.

Einbau, Wartung und Betrieb dürfen nur von durch Artesyn ausgebildetem oder im Bereich

Elektronik oder Elektrotechnik qualifiziertem Personal durchgeführt werden. Die in diesem

Handbuch enthaltenen Informationen dienen ausschließlich dazu, das Wissen von

Fachpersonal zu ergänzen, können dieses jedoch nicht ersetzen.

Halten Sie sich von stromführenden Leitungen innerhalb des Systems fern. Entfernen Sie auf keinen Fall die Systemabdeckung. Nur werksseitig zugelassenes Wartungspersonal oder anderweitig qualifiziertes Wartungspersonal darf die Systemabdeckung entfernen, um

Systemkomponenten zu ersetzen oder andere Anpassungen vorzunehmen.

Installieren Sie keine Ersatzteile oder führen Sie keine unerlaubten Veränderungen am System durch, sonst verfällt die Garantie. Wenden Sie sich für Wartung oder Reparatur bitte an die für

Sie zuständige Geschäftsstelle von Artesyn. So stellen Sie sicher, dass alle sicherheitsrelevanten Aspekte beachtet werden.


29


Artesyn und unsere Zulieferer unternehmen größte Anstrengungen um sicherzustellen, dass sich Pins und Stecker von Boards vor dem Verlassen der Produktionsstätte in einwandfreiem

Zustand befinden. Verbogene Pins, verursacht durch fehlerhafte Installation oder durch

Installation von Boards mit beschädigten Steckern kann die durch Artesyn gewährte Garantie für Boards und Backplanes erlöschen lassen.

Dieses Produkt wird mit gefährlichen Spannungen betrieben, die zu Verletzungen und Tod führen können. Seien Sie im Umgang mit dem Produkt und beim Testen und Anpassen des

Produktes und seiner Komponenten äußerst vorsichtig.

EMV

FCC Class A

Das Produkt wurde getestet und erfüllt die für digitale Geräte der Klasse A gültigen Grenzwerte gemäß den FCC-Richtlinien Abschnitt 15 bzw. EN 55022 Klasse A. Diese Grenzwerte sollen einen angemessenen Schutz vor Störstrahlung beim Betrieb des Produkts in Geschäfts-,

Gewerbe- sowie Industriebereichen gewährleisten. Das Produkt arbeitet im

Hochfrequenzbereich und erzeugt Störstrahlung. Bei unsachgemäßem Einbau und anderem als in diesem Handbuch beschriebenen Betrieb können Störungen im Hochfrequenzbereich auftreten.

Diese Einrichtung kann im Wohnbereich Funkstörungen verursachen; in diesem Fall kann vom

Betreiber verlangt werden, angemessene Maßnahmen durchzuführen und dafür aufzukommen.

Benutzen Sie zum Anschließen von Peripheriegeräten ausschließlich abgeschirmte Kabel. So stellen Sie sicher, dass ausreichend Schutz vor Störstrahlung vorhanden ist. Die Blades müssen mit der Frontblende installiert und alle freien Steckplätze müssen mit Blindblenden abgedeckt sein.

Änderungen, die nicht ausdrücklich von Artesyn erlaubt sind, können Ihr Recht das System zu betreiben zunichte machen.

30



Wenn dieses Produkt ohne Frontblende ausgeliefert wird oder wenn die Frontblende entfernt wird, muss Ihr System die notwendigenSchutzmechnismen gegen elektromagnetische interferenzen bereitstellen, um die Einhaltung der eletromagnetischen Verträglichkeit des

Systems zu gewährleisten.

Boardprodukte werden in einem repräsentativen System getestet, um zu zeigen, dass das

Board den oben aufgeführten EMV-Richtlinien entspricht. Eine ordnungsgemäße Installation in einem System, welches die EMV-Richtlinien erfüllt, stellt sicher, dass das Produkt gemäß den

EMV-Richtlinien betrieben wird.

Sobald Sie das Produkt oder seine Standardkonfiguration verändern, müssen Sie dafür sorgen, dass alle relevanten Richtlinien eingehalten werden.

System Installation

Beschädigung von Schaltkreisen

Elektrostatische Entladung und unsachgemäßer Ein- und Ausbau des Produktes kann

Schaltkreise beschädigen oder ihre Lebensdauer verkürzen.

Bevor Sie das Produkt oder elektronische Komponenten berühren, vergewissern Sie sich, daß

Sie in einem ESD-geschützten Bereich arbeiten.

Betrieb

Beschädigung des Systems

Hohe Luftfeuchtigkeit und Kondensat auf den Oberflächen der Produkte kann zu

Kurzschlüssen führen.

Betreiben Sie die Produkte nur innerhalb der angegebenen Grenzwerte für die relative

Luftfeuchtigkeit und Temperatur und stellen Sie vor dem Einschalten des Stroms sicher, dass sich auf den Produkten kein Kondensat befindet.


31


Batterie

Datenverlust

Wenn Sie einen anderen Batterietyp installieren als der, der bei Auslieferung des Produktes installiert war, kann Datenverlust die Folge sein, da die neu installierte Batterie für andere

Umgebungsbedingungen oder eine andere Lebenszeit ausgelegt sein könnte.

Verwenden Sie daher den gleichen Batterietyp, der bei Auslieferung des Produktes installiert war.

Beschädigung des PCBs und der Batteriehalterung

Wenn Sie die Batterie mit einem Schraubendreher ausbauen, können das PCB und die

Batteriehalterung beschädigt werden.

Benutzen Sie keinesfalls einen Schraubendreher, um die Batterie aus der Halterung zu nehmen.

Beschädigung des Produktes

Fehlerhafter Austausch von Lithium-Batterien kann zu gefährlichen Explosionen führen.

Wenn SIe die Lithium-Batterie auf dem Produkt austauschen, stellen Sie sicher, dass die alte und die neue Batterie vom gleichen Typ sind.

Ist der Batterietyp nicht verfügbar, wenden Sie sich an Artesyn um herauszufinden, welcher

Batterietyp offiziell alternativ verwendet werden darf.

Hot Swap

Datenverlust

Wenn Sie das Produkt ausbauen, obwohl die blaue Hot-Swap LED noch blinkt, kann dies zu

Datenverlust führen.

Warten Sie daher, bis die blaue LED durchgehend leuchtet, bevor Sie das Produkt ausbauen.

32

Beschädigung des Produktes

Wenn Sie das RTM ausbauen, während das System läuft und die blaue LED auf dem Front Board noch blinkt, können Daten verloren gehen.

Schalten Sie deshalb vor dem Ausbau des RTMs den Slot, in dem es sich befindet, ab und fahren

Sie die Payload des Front Boards herunter, indem Sie den unteren Griff des Front Boards öffnen und warten, bis die blaue LED leuchtet ohne zu blinken.


Chapter 1

Introduction

1.1

Features

The CPCI-6200 is a high performance, hot swappable universal Compact PCI board based on the MPC8572 integrated processor.

Table 1-1 Summary of Features

Function

Processor

Host Controller

Memory Controller

System Memory

I

2

C

Flash

Features

 One 8572 integrated processor

 Two e500 cores with integrated 1 MB L2 cache

 32 KB data and instruction cache on each core

 Core frequency from 1.3 to 1.5 GHz

 Two integrated DDR3 SDRAM controllers

 Two integrated four-channel DMA controller

 Two integrated PCI Express interfaces (8 lanes of 2.5 Gb/s each)



Four integrated 10/100/1000 Ethernet controllers



One integrated DUART



Two integrated I

2

C controllers



One integrated programmable interrupt controller



One integrated local bus controller

 Two banks of DDR3 SDRAM with error-correcting code

(ECC)



Supports 2 or 4 GB



Provides up to 800 MHz DDR3 data rate

 One 8 KB VPD serial EEPROM

 Two 64 KB user configuration serial EEPROMs

 One real time clock (RTC) with battery back-up

 Dual temperature sensors

 Two SPDs for memory

 Connection to the PCIE expander and RTM



128 MB soldered flash with two alternate 1 MB boot sectors that can be selected via a hardware switch

 HW switch or SW bit write protection for the entire logical bank



Minimum of 4 GB user flash


33

Introduction

34

Table 1-1 Summary of Features (continued)

Function

NVRAM

PCI Express

I/O

Timers

CPCI Interface

IPMI Controller

Features



One 512 KB MRAM

 4x port to PCI Express expansion

 4x port to 6-port PCI Express switch for PCI Express interface

 One mini DB9 connector on the face plate (one serial channel)



Two RJ-45 connectors on the face plate with integrated

LEDs for two 10/100/1000 Ethernet channels

 Two 10/100/1000 Ethernet channels for rear J3 I/O

 One USB 2.0 channel on the face plate

 PMC site 1 front I/O and rear J3 I/O

 PMC site 2 front I/O and rear J5 I/O



Eight 32-bit MCP8572 timers



Four 32-bit timers in a PLD



One watchdog timer in PLD

Complies with the following:

 PCI Specification Revision 2.2

 PICMG 2.1 R2.0 CompactPCI Hot Swap Specification,

January 17, 2001



PICMG 2.0 R3.0 CompactPCI Core Specification, October

1, 1999

 PICMG 2.16 R1.0 CompactPCI Packet Switching

Backplane Specification, September 5, 2001



PICMG 2.9 R1.0 CompactPCI System Management

Specification



Renesas HD65F2166 processor



Six I

2

C bus



8-channel analog/digital converter



Three serial ports



512 KB flash



40 KB SRAM



1 MB (64K x 16 bit) external SRAM



External user EEPROM, SDR/FRU, SEL flash of 512 KB each


Introduction

Table 1-1 Summary of Features (continued)

Function

Others

Software Support

RTM

Features



One RESET/ABORT switch on the face plate



User/Fail LED on the face plate



Blue hot swap LED on the face plate



One standard 16-pin JTAG/COP header



Support for boundary scan

 VxWorks

 Linux

Compatible with RTM-CPCI-6115 (01-W3766F11A)


35

Introduction

1.2

Standard Compliances

The CPCI-6200 is designed to be CE compliant and to meet the following standard requirements.

Standard Description

UL 60950-1

EN 60950-1

IEC 60950-1

CAN/CSA C22.2 No 60950-1

CISPR 22

CISPR 24

EN 55022

EN 55024

FCC Part 15

Industry Canada ICES-003

VCCI Japan

AS/NZS CISPR 22

EN 300 386

NEBS Standard GR-1089 CORE

Safety Requirements (legal)

EMC requirements (legal) on system level

(predefined Artesyn system)

NEBS Standard GR-63-CORE

ETSI EN 300 019 series

Directive 2002/95/EC

Environmental Requirements

Directive on the restriction of the use of certain hazardous substances in electrical and electronic equipment (RoHS)

36


Introduction

Figure 1-1 Declaration of Conformity

Manufacturer’s Name:

E

C Declaration of Conformity

According to EN 17050-1:2004


Embedded Computing

Manufacturer’s Address:

Zhongshan General Carton Box Factory Co. Ltd. No 62, Qi

Guan Road West, Shiqi District, 528400 Zhongshan City

Guangdong, PRC

Declares that the following product, in accordance with the requirements of 2004/108/EC, 2006/95/EC, 2011/65/

EU and their amending directives,

Product: CPCI6200 Compact PCI Processor Board

Model Name/Number: CPCI6200-13-2G, CPCI6200-13-2G-CC, CPCI6200-15-4G has been designed and manufactured to the following specifications:

EN55022: 2006 Class A

EN55024 (A1: 2001 + A2: 2003): 1998

2011/65/EU RoHS Directive

As manufacturer we hereby declare that the product named above has been designed to comply with the relevant sections of the above referenced specifications. This product complies with the essential health and safety requirements of the above specified directives. We have an internal production control system that ensures compliance between the manufactured products and the technical documentation.

___________________________________________________

Tom Tuttle, Manager, Product Testing Services

___

09/23/2014______

Date (MM/DD/YYYY)


37

Introduction

1.3

Mechanical Data

The CPCI-6200 is a full 6U 18-layer board. It is designed with ruggedization holes to support ruggedization application. This board occupies a single CPCI card slot with PMC modules installed.

1.4

Ordering Information

Use the information in the following sections when ordering boards and accessories.

1.4.1

Supported Board Models

Table 1-2 Order Numbers for Baseboard Variants

Marketing Number

CPCI6200-13-2G

CPCI6200-15-4G

Description

MPC8572, 1.33 GHz, 2 GB SO-DIMM DDR3, 6E

MPC8572, 1.5 GHz, 4 GB SO-DIMM DDR3, 6E

1.4.2

Board Accessories

Table 1-3 Order Numbers for Related Products

Marketing Number

CPCI-6115-MCPTM-02

Description

Transition module/PIM carrier, two RJ-45 Ethernet connectors, one RJ-45 asynchronous serial port connector, COM2 accessible via PIM slots, two PIM slots.

38


1.5

Product Identification

Figure 1-2 Location of the Product Serial Number

Introduction

9105991

Serial Number Label


39

Introduction

40


Hardware Preparation and Installation

Chapter 2

2.1

Overview

This chapter provides instructions on preparing and installing the CompactPCI board.

A fully implemented CPCI-6200 consists of the baseboard, PMC modules, and an optional rear transition module.

2.2

Unpacking the CPCI Baseboard

1. Make sure that you receive all items of your shipment:





Printed Quick Start Guide and Safety Notes

CPCI-6200 baseboard



Optional items that were ordered

2. Check the board for damages, and report any damage to Artesyn.

3. Remove the desiccant bag shipped together with the board and dispose of it according to your country’s legislation.

The product is thoroughly inspected before shipment. If any damage occurred during transportation or any items are missing, contact Artesyn immediately.


41


2.3

Environmental Requirements

The environmental conditions must be tested and proven in the used system configuration.

These conditions refer to the surroundings of the board within the user environment.







Operating temperatures refer to the temperature of the air circulating around the board and not to the component temperature.

To ensure that the operating conditions are met, forced air cooling is required within the shelf environment.

The environmental values given in the table below only apply to the board without any accessories. If installing accessories, their environmental requirements must also be taken into account.

42

Product Damage

High humidity and condensation on surfaces cause short circuits.

Do not operate the product outside the specified environmental limits. Make sure the product is completely dry and there is no moisture on any surface before applying power.

Table 2-1 CPCI-6200 Environmental Requirements

Characteristics

Operating Temperature

Temperature Change

Forced Air Flow

Relative Humidity

Vibration

Operating

0°C to +55°C (32°F to 131°F) entry air with forced-air cooling

+/-0.5°C/min according to NEBS

Standard GR-63-CORE

8.7 LFM at 55°C (131 °F) ambient temperature

5% to 90% Non-Condensed

1.0 G sine sweep, 5–200 Hz,

0.25 octaves/min, all 3 axis

(operating)

Non-Operating

–40°C to +70°C (104°F to 158°F)

5% to 90%Non-Condensed

5–20 Hz at 0.01 g/Hz

20–200 Hz at -3.0 dB/octave

Random 5–20 Hz at 1 m/sec

Random 20–200 Hz at -3 dB/Octave



Table 2-1 CPCI-6200 Environmental Requirements (continued)

Characteristics

Shock

Operating

Half-sine, 11 ms, 30 ms

Free Fall

Non-Operating

Blade-level packaging

Half-sine, 6 ms at 180 ms

Blade-level packaging

100 mm (unpackaged) per GR-63-

CORE

2.4

Power Requirements

The board's power requirements depend on the installed hardware accessories. The following table gives examples of typical power requirements for a processor running without any accessories.

If you want to install any accessories, the load of the respective accessory has to be added to the load of the board variant you are using. For information on the accessories' power requirements, refer to the documentation delivered with the respective accessory or ask your local representative.

Table 2-2 Baseboard Power Requirements

Configuration

CPCI6200-13-2G (1.3 GHz, 2 GB memory)

CPCI6200-15-4G (1.5 GHz, 4 GB memory)

Maximum Power Requirement

3.3 V, 4.1 A, 13.5 W

5.0 V, 4.6 A, 23 W

3.3 V, 4.2 A, 13.8 W

5.0 V, 5.7 A, 28.5 W (Estimated)


43


2.5

Installing Accessories

2.5.1

Installing a PMC Module on the CPCI Baseboard

One double-width or two single-width PCI mezzanine cards (PMC) can be mounted on the

CPCI-6200 baseboard. Each PMC slot has four connectors that provide a PCI interface to two

PMC slots that provide user I/O to the backplane.

Damage of Circuits



This procedure assumes that the CPCI-6200 is installed in the system chassis.

1. Attach an ESD strap to your wrist, and then attach the other end of the ESD strap to the chassis as a ground.

The ESD strap must be secured to your wrist and to ground throughout the procedure.

2. Remove chassis or system cover(s) as necessary for access to the board.

44




3. Carefully remove the CPCI-6200 from the card slot and lay it flat, with connectors

J1 through J5 facing you.



4. Remove the PMC filler plate from the front panel of CPCI-6200.

PMC Alignment

PMC Filler Plate

Voltage Key

5. Make sure that hole on the PMC matches the voltage key on CPCI-6200.

Do not remove the PMC voltage key.

CPCI-6200 supports only 3.3 V I/O PMC modules.

6. Slide the edge connector of the PMC module into the front panel opening from behind, and then place the PMC module on top of the baseboard.


45


The four connectors on the underside of the PMC module should then connect smoothly with the corresponding connectors (J11/12/13/14) or (J21/22/23/24) on

CPCI-6200.

7. Insert the four short Phillips screws, provided with the PMC, through the holes on the bottom side of CPCI-6200 and into the PMC front bezel and rear standoffs, and then tighten the screws.

2.5.2

Installing the Rear Transition Module

For information on installing the rear transition module, see Chapter 5, Transition Module

Preparation and Installation

.

2.6

Preparing the Baseboard for Installation





Install the accessory kits, before installing the board, if necessary.

If memory modules have been installed, check that all socket locks of the board are closed before board installation.

2.6.1

Inspecting the CPCI Baseboard

You can use the CPCI-6200 as a system controller in a system slot, an intelligent I/O board in a peripheral slot, or in stand-alone mode.

The board is fully compliant to CompactPCI Hot Swap Specification PICMG 2.1 R2.0, and can run in both 3.3 V and 5 V CompactPCI system.

Before installing the CPCI-6200, make sure that switches are configured as desired. For more information, see

Hardware Configuration

on page 47

.

46



Perform the following steps before you install your board into the CompactPCI backplane to prevent possible backplane pin damage.

1. Inspect the board connectors to ensure that they are not damaged by previous insertions or accidental mishandling.

If any connector is damaged, do not install the board into the backplane to prevent the bending of pins.

2. Inspect the slot where the board will be installed for any bent pins on the backplane.

2.6.2

Equipment Required for Installation

You need the following items to do a complete installation:





CompactPCI or compatible system enclosure

System console terminal





Operating system and/or application software

Disk drives or other I/O, and controllers

2.6.3

Hardware Configuration

To produce the desired configuration and ensure proper operation of the board, you may need to carry out certain hardware modifications before installing the module.

Most options on the board are configured by software. Configuration changes are made by setting the bits in control registers after the board is installed in a system. The control registers

are described in

Memory Maps and Addresses

on page 185

and other vendor publications.


47


Switches are used to control options that are not software configurable. The switch settings are described in the succeeding sections.

Figure 2-1 Location of Configuration Switches

Board

Configuration

Switch, S1

IPMI

Configuration

Switch, S2

2.6.3.1

Board Configuration Switch, S1

The CPCI-6200 uses an 8-position SMT configuration switch to:







Control the flash bank write-protect.

Select the flash boot image.

Control the safe start ENV settings.

48



The default switch position is OFF.

Table 2-3 S1 Switch Settings

Switch

SW1

SW2

Name

SAFE_START

BOOT_SEL

SW3

SW4

SW5

SW6

SW7

SW8

FLASH_WP

JTAG_MODE

PMC1_PCI_FSEL

SA_MODE

LRO_SW

PWR12V_EN

ON

Use safe ENV setting

Board is booted from block

B of Flash A

OFF (Default)

Use normal ENV setting

Board is booted from block A of Flash A

Flash A is write protected Flash A write protection is off

JTAG operates in pass through mode

Normal operation

Max PCI freq can be

133 MHz on PMC1

Board operates in Stand

Alone Mode

Max PCI freq can be 100 MHz on PMC1

Normal operation

Reset caused by front panel switch, RTC, IPMI,

COP header is propagated to backplane PCI reset

+-12 V supplies are disabled

Reset caused by the front panel switch, RTC, IPMI, COP header is not propagated to backplane PCI reset

+-12 V supplies are enabled

When the SAFE_START switch is OFF, the normal ENV setting should be used. When it is on, the safe ENV settings should be used. This switch status is readable from System Status register 1, bit 5.

When the BOOT_SEL switch is OFF, the flash memory map is normal and boot block A is selected. When the switch is ON, boot block B is selected and mapped to the highest address.

When the FLASH_WP switch is OFF, the flash is not write-protected. When it is ON, the flash is write-protected i.e., writes to the flash devices are blocked by hardware.

When the JTAG_MODE switch is OFF, board operation is normal. When it is ON, the board is in pass through mode.

When the PMC1_PCI_FSEL switch is OFF, the maximum PCI bus operation is 100 MHz on PMC1.

When it is ON, the maximum PCI bus operation is 100 MHz on PMC1. For more information, see

PCI Bus Frequency

on page 93

.


49


When the SA_MODE switch is OFF, board operation is normal. When the switch is ON, the board operates in stand-alone mode i.e., it operates in a peripheral slot without the system board in the chassis.

When the LRO_SW switch is OFF, if the board is placed in reset, it is only a local reset. When the

switch in ON, the board reset is propagated to CPCI bus. For more information, see

Reset

Control Logic

on page 99 .

When the PWR12V_EN switch is OFF, the 12 V supply is enabled on the board and is available for the RTM. When the switch is ON, the 12 V supply is disabled. Use the switch at ON position when a 12 V supply is not available in the system or chassis.

2.6.3.2

IPMI Configuration Switch, S2

The CPCI-6200 uses an 8-position SMT configuration switch to control the IPMI controller settings.

The default switch position is OFF.

Table 2-4 S2 Switch Settings

Switch

SW1

Name

IPMI_DISABLE

SW2

SW3

SW4

SW5

SW6

SW7

SW8

IPMI_MODE_2

IPMI_MODE_1

-

IPMI_SYSEN

FORCE_PM

-

PMC2_PCI_FSEL

ON

Keep the IPMI controller in reset and thereby disable it

JTAG Debug mode

Reserved

Reserved

Force IPMI in system mode

Force IPMI in PM mode

Reserved

Max PCI freq can be 133 MHz on

PMC2

OFF (Default)

IPMI controller is enabled

Normal operation

Normal operation

Reserved

IPMI operates in non-system mode

IPMI operates in non-PM mode

Reserved

Max PCI freq can be 100 MHz on PMC2

50

When the IPMI_DISABLE switch is OFF, the IPMI device is enabled. When the switch ON, IPMI is disabled by asserting its reset.



When the IPMI_MODE_1 and IPMI_MODE_2 switches are OFF, the IPMI controller operates normally. When both switches are ON, the IPMI controller enters programming mode. Any other switch setting is not supported and treated as reserved.

When the IPMI_SYSEN switch is OFF, the IPMI operates in non-system mode. When the switch is ON, IPMI operates in system mode.

When the FORCE_PM switch is OFF, the IPMI operates in non-peripheral management mode.

When the switch is ON, IPMI operates in peripheral management (PM) mode.

When the PMC2_PCI_FSEL switch is OFF, the maximum 100 MHz PCI bus frequency can be used on PMC2. When the switch is ON, the maximum PCI bus frequency is 133 MHz. For more information, see

PCI Bus Frequency

on page 93

.

2.7

Installing the CPCI Baseboard

1. Attach an ESD strap to your wrist, and then attach the other end of the ESD strap to the chassis as a ground.

The ESD strap must be secured to your wrist and to ground throughout the procedure.

2. For a non-hot swap system, shut down the operating system.




3. Turn off the AC or DC power, and then remove the AC cord or DC power lines from the system.

4. Remove the chassis or system cover(s) as necessary for access to the CompactPCI modules.


51


5. Remove the filler panel from the appropriate card slot.

6. Set the VIO on the backplane to either +3.3 V or +5 V, depending on your

CompactPCI system signaling requirements, and ensure the backplane does not bus J3 or J5 signals.

7. Slide the baseboard into the appropriate slot.

Grasping the top and bottom injector handles, be sure the module is well seated in the P1 through P5 connectors on the backplane. Make sure you do not damage or bend connector pins.

8. Secure the baseboard in the chassis with the screws provided, making good contact with the transverse mounting rails to minimize RF emissions.

9. Replace the chassis or system cover(s), and make sure no cables are pinched.

10.Cable the peripherals to the panel connectors, and then reconnect the system to the AC or DC power source.

11.Turn the equipment power on.

After you have verified that all necessary hardware preparation has been done, that all connections have been made correctly and that the installation is complete, you can power up the system. The MPU, hardware and firmware initialization process is performed by the

MOTLoad power-up or system reset. The firmware initializes the devices on the baseboard in preparation for booting the operating system.

The firmware is shipped from the factory with an appropriate set of defaults. In most cases there is no need to modify the firmware configuration before you boot the operating system.

For more information on MOTLoad, see

MOTLoad Firmware

on page 143 .

52



2.8

Removing the CPCI Baseboard

The board is fully compliant to Compact PCI Hot Swap Specification PICMG 2.1 R2.0, and can run in both 3.3 V and 5 V Compact PCI systems.

Data Loss

Removing the RTM with the system power on and the blue LED on the front blade still flashing causes data loss.

Before removing the RTM from a powered system, power down the slot and the front blade’s payload by opening the lower handle of the front blade and wait until the blue LED is permanently ON.

Damage of Circuits



The following procedure describes how to remove the board from a system. It assumes that the system is powered and running system level management software. If the system is unpowered, disregard the blue LED and skip the respective step.

1. Unfasten the two screws on the front panel until the board is detached from the rack frame.

2. Press the red button to unlock handles.

3. Open handles until resistance is encountered.

The hot swap switch opens automatically.


53


4. Wait until blue hot swap LED lights up.

Data Loss

Removing the product with the blue LED still blinking causes data loss.

Wait until the blue LED is permanently illuminated before removing the product.

5. Remove the board from the slot by fully opening the ejector handles.

2.9

Connecting to a Console Port

When the CPCI-6200 is installed in the chassis, you are ready to connect peripherals and apply power to the board.

On the CPCI-6200 baseboard, the standard serial console port (COM1) serves as the MOTLoad debugger console port. The firmware console should be set up as follows:





Eight bits per character

One stop bit per character





Parity disabled (no parity)

Baud rate of 9600

9600 baud is the power-up default for serial ports on CPCI-6200 boards. After power-up you can reconfigure the baud rate if you wish, using the MOTLoad PF (Port Format) command via the command line interface. Whatever the baud rate, some type of hardware handshaking— either XON/OFF or via the RTS/CTS line—is desirable if the system supports it.

2.10 Factory-Installed Linux

A bootable ramdisk-based Linux image based on the 2.6.29.6 or later kernel is available in the

NOR flash. To boot this image, use the following MOTLoad commands:

CPCI6200> bmw -af8000000 -bf8ff0000 -c2000000

CPCI6200> execP -l2000400

54



The image should boot to the following prompt:

Emerson Network Power Embedded Computing Linux

Kernel 2.6.29.6 on a 2-processor CPCI6200 localhost login:

Login as root with no password.

If you want to use IPMI, load the IPMI SMBus driver using:

# modprobe ipmi_smb

Contact Artesyn for kernel patches and additional information on using Linux on the CPCI-

6200.


55


56


Chapter 3

Controls, LEDs, and Connectors

3.1

Board Layout

Figure 3-1 Board Layout

NAND Flash

J5

PMC 2

PCI Express x4 to PCI Bridge 1,2,3

IPMI Controller

PCI Express

Switch

JTAG Header

LBC PLD

COP Header

PCI x1 to

PCI Bridge

J3

PMC 1

J2

DDR3 DIMM

RTC

Battery

Boot Flash

DDR3 DIMM

J1

Configuration

Switch, S1

Configuration

Switch, S2 USB Controller

PCI Express Expansion

Connector

Processor


57


3.2

Front Panel

For more information on the front panel connectors, see

Front Panel LEDs

on page 79 .

58



3.3

Connectors and Headers

Table 3-1 Onboard Connectors

Reference Designator

J1

J2

J3

J4

J5

J6

J7

J11, J12, J13, J14

J21, J22, J23, J24

J16

J17

P1

P2

P3

P4

P5

Function

CPCI five-row J1

CPCI bus connector

CPCI five-row J2

CPCI bus connector

CPCI five-row J3

User I/O connector

Not used

CPCI five-row J5

User I/O connector

10/100/1000 Ethernet

Ethernet port on the front panel (ENET 1 and ENET2)

USB port on the front panel

PMC1

PMC2

Serial Port 1 (COM1)

Mini DB9 serial port on the front panel

PMC expansion to PMCspan

Board insertion/ejection

Switch connector on the front panel

Reset/abort switch on the front panel

IPMI serial port (COM2)

Planar header for debugging IPMI Serial Port

Processor debug header

Planar header for probing debug signals

Boundary scan header

Planar header for boundary scan and PLD/flash programming


59


Table 3-1 Onboard Connectors (continued)

Reference Designator

P6

P7

XJ1, XJ2

S1

S2

Function

Processor COP header

Planar header for processor COP emulation

Planar header for debugging the PCI Express switch device

DDR3 DIMM 1 and 2 Socket

204-pin SO-UDIMM socket for DDR3 DIMM

8-position switch

8-position switch for IPMI functionality

3.3.1

CPCI Bus Connector, J1

J1 is a five-row CPCI bus connector.

Table 3-2 CPCI Bus Connector Pinout, J1

23

22

21

20

Pin

25

24

Row A

+5.0 V

AD[1]

+3.3 V

AD[7]

+3.3 V

AD[12]

19

18

17

16

+3.3 V

SERR#

+3.3 V

DEVSEL#

15 +3.3 V

KEY AREA (Pins 12 - 14)

11

10

AD[18]

AD[21]

Row B

REQ64#

+5.0 V

AD[4]

GND

AD[9]

GND

AD[15]

GND

IPMB0_SCL

PCIXCAP

FRAME#

AD[17]

GND

Row C

ENUM#

V(IO)1

AD[3]

+3.3 V1

AD[8]

V(IO)

AD[14]

+3.3 V

IPMB0_SDA

V(IO)

IRDY#

AD[16]

+3.3 V

60

Row D

+3.3 V

AD[0]

+5.0 V1

AD[6]

M66EN

AD[11]

GND1

PAR

GND1

STOP#

BD_SEL#

GND1

AD[20]

Row E

+5.0 V

ACK64#

AD[2]

AD[5]

C/BE[0]#

AD[10]

AD[13]

C/BE[1]#

PERR#

LOCK#

TRDY#

C/BE[2]#

AD[19]



Table 3-2 CPCI Bus Connector Pinout, J1 (continued)

6

5

8

7

Pin

9

2

1

4

3

Row A

C/BE[3]#

AD[26]

AD[30]

REQ#

BRSVR1A5

IPMB_PWR

INTA#

TCK

+5.0 V

Row B

IDSEL

GND

AD[29]

GND

BRSVR1B5

HEALTHY#

INTB#

+5.0 V

-12 V

Row C

AD[23]

V(IO)

AD[28]

+3.3 V1

RST#

V(IO)1

INTC#

TMS

TRST#

3.3.2

CPCI Bus Connector, J2

J2 is a five-row CPCI bus connector.

Table 3-3 CPCI Bus Connector Pinout, J2

16

15

14

13

12

11

20

19

18

17

Pin Row A

22

21

GA4

RSV

RSV

GND

BRSVP2A18

BRSVP2A17

BRSVP2A16

BRSVP2A15

AD[35]

AD[38]

AD[42]

AD[45]

Row B

GA3

GND

GND

GND

BRSVP2B18

GND

BRSVP2B16

GND

AD[34]

GND

AD[41]

GND

RSV

RSV

AD[33]

V(IO)

AD[40]

V(IO)

Row C

GA2

RSV

RSV

RSV

BRSVP2C18

RSV


GND

RSV

GND

AD[37]

GND

AD[44]

Row D

GA1

RSV

GND

RSV

GND

RSV

Row D

GND1

AD[25]

GND1

CLK

GND1

INTP

+5.0 V1

TDO

+12 V

Row E

AD[22]

AD[24]

AD[27]

AD[31]

GNT#

INTS

INTD#

TDI

+5.0 V

Row E

GA0

RSV

RSV

RSV

BRSVP2E18

RSV

BRSVP2E16

RSV

AD[32]

AD[36]

AD[39]

AD[43]

61


Table 3-3 CPCI Bus Connector Pinout, J2 (continued)

3

2

5

4

1

7

6

9

8

Pin Row A

10 AD[49]

AD[52]

AD[56]

AD[59]

AD[63]

C/BE[5]#

V(IO)

RSV

RSV

RSV

Row B

AD[48]

GND

AD[55]

GND

AD[62]

64EN#

BRSVP2B4

GND

RSV

GND

Row C

AD[47]

V(IO)

AD[54]

V(IO)

AD[61]

V(IO)

C/BE[7]#

RSV

SYSEN#

1

RSV

Row D

GND

AD[51]

GND

AD[58]

GND

C/BE[4]#

GND

RSV

RSV

RSV

1. Defined as SYSEN#. This OV allows the CPCI-6200 to ensure that it is installed into a peripheral slot.

Row E

AD[46]

AD[50]

AD[53]

AD[57]

AD[60]

PAR64

C/BE[6]#

RSV

RSV

RSV

3.3.3

CPCI User I/O Connector, J3

J3 is a five-row user I/O CPCI connector.

Note: Row F is ground and is not shown in the table.

Table 3-4 CPCI User I/O Connector Pinout, J3

5

6

3

4

7

8

Pin

1

2

Row A

IPMI_PWR

PMCIO60

PMCIO55

PMCIO50

PMCIO45

PMCIO40

PMCIO35

PMCIO30

Row B

PMCIO64

PMCIO59

PMCIO54

PMCIO49

PMCIO44

PMCIO39

PMCIO34

PMCIO29

Row C

PMCIO63

PMCIO58

PMCIO53

PMCIO48

PMCIO43

PMCIO38

PMCIO33

PMCIO28

62

Row D

PMCIO62

PMCIO57

PMCIO52

PMCIO47

PMCIO42

PMCIO37

PMCIO32

PMCIO27

Row E

PMCIO61

PMCIO56

PMCIO51

PMCIO46

PMCIO41

PMCIO36

PMCIO31

PMCIO26



Table 3-4 CPCI User I/O Connector Pinout, J3 (continued)

14

15

16

17

18

19

Pin

9

10

11

12

13

Row A

PMCIO25

PMCIO20

PMCIO15

PMCIO10

PMCIO5

Row B

PMCIO24

PMCIO19

PMCIO14

PMCIO9

PMCIO4

+3.3V

+3.3V

G1_DB+ (RX2+) G1_DB- (RX2-)

G1_DA+ (TX2+) G1_DA- (TX2-)

G0_DB+ (RX1+) G0_DB- (RX1-)

G0_DA+ (TX1+) G0_DA- (TX1-)

GND +12V

+3.3V

GND

GND

GND

GND

-12V

Row C

PMCIO23

PMCIO18

PMCIO13

PMCIO8

PMCIO3

10/100/1000Base-T Ethernet signals:



G0_Dx–CH1 10/100/1000Base-T Ethernet



G1_Dx–CH2 10/100/1000Base-T Ethernet

PMC User I/O signals:



PMCIO(64:1)–PMC I/O



IPMI_PWR–+3.3 V derived from IPMB input power

Row D

PMCIO22

PMCIO17

PMCIO12

PMCIO7

PMCIO2

+5V

G1_DD+

G1_DC+

G0_DD+

G0_DC+

GND

3.3.4

CPCI Connector, J4

J4 is a five-row CPCI connector that is not used on the CPCI-6200. It is not populated.

3.3.5

CPCI User I/O Connector, J5

J5 is a five-row user I/O CPCI connector.

Row E

PMCIO21

PMCIO16

PMCIO11

PMCIO6

PMCIO1

+5V

G1_DD-

G1_DC-

G0_DD-

G0_DC-

GND


63


Row F is ground and is not shown in the table.

NC

NC

NC

NC

GND

NC

NC

PMCIO30

PMCIO25

PMCIO20

PMCIO15

PMCIO10

PMCIO5

NC

NC

Row A

TM_PRSNT#

PMCIO60

PMCIO55

PMCIO50

PMCIO45

PMCIO40

PMCIO35

Table 3-5 CPCI User I/O Connector Pinout, J5

12

13

14

15

8

9

10

11

6

7

4

5

2

3

Pin

1

20

21

22

16

17

18

19

NC

NC

NC

NC

NC

NC

NC

PMCIO29

PMCIO24

PMCIO19

PMCIO14

PMCIO9

PMCIO4

NC

NC

Row B

PMCIO64

PMCIO59

PMCIO54

PMCIO49

PMCIO44

PMCIO39

PMCIO34

PMCIO28

PMCIO23

PMCIO18

PMCIO13

PMCIO8

PMCIO3

NC

GND

Row C

PMCIO63

PMCIO58

PMCIO53

PMCIO48

PMCIO43

PMCIO38

PMCIO33

NC

NC

NC

NC

NC

TMCOM3#

NC

PMCIO27

PMCIO22

PMCIO17

PMCIO12

PMCIO7

PMCIO2

NC

NC

Row D

PMCIO62

PMCIO57

PMCIO52

PMCIO47

PMCIO42

PMCIO37

PMCIO32

NC

NC

I2C_CLK

MXCLK

MXDI

COM4_RXD

COM4_TXD

PMCIO26

PMCIO21

PMCIO16

PMCIO11

PMCIO6

PMCIO1

NC

NC

Row E

PMCIO61

PMCIO56

PMCIO51

PMCIO46

PMCIO41

PMCIO36

PMCIO31

NC

NC

I2C_DATA

MXSYNC#

MXDO

COM3_RXD

COM4_TXD

3.3.6

PCI Mezzanine Card (PMC) Connectors

There are four 64-pin connectors for each PMC slot on the CPCI-6200.

64



Connectors J11, J12, J13 and J14 are used for PMC1 while J21, J22, J23 and J24 are used for

PMC2.

Table 3-6 PMC Connector Pinout, J11/J21

37

39

41

43

29

31

33

35

45

47

49

21

23

25

27

13

15

17

19

5

7

9

11

Pin

1

3

FRAME#

GND

DEVSEL#

PCIXCAP

PCI_RSVD

PAR

VIO

AD12

AD09

TCK

GND

INTB#

PRESENT#

INTD#

GND

CLK

GND

REQ#/XGNT0#

VIO

AD28

AD25

GND

AD22

AD19

VIO

J11/J21

-12 V

INTA#

INTC#

+5 V

PCI_RSVD

NC (+3.3Vaux)

GND

GNT#/XREQ0#

+5 V

AD31

AD27

GND

C/BE3#

AD21

+5 V

AD17

GND

IRDY#

+5 V

LOCK#

PCI_RSVD

GND

AD15

AD11

+5 V

38

40

42

44

30

32

34

36

46

48

50

22

24

26

28

14

16

18

20

6

8

10

12

Pin

2

4


65


66

Table 3-6 PMC Connector Pinout, J11/J21 (continued)

Pin

51

53

55

57

59

61

63

GND

AD06

AD04

VIO

AD02

AD00

GND

J11/J21

C/BE0#

AD05

GND

AD03

AD01

+5 V

REQ64#


23

25

27

29

15

17

19

21

31

33

7

9

11

13

3

5

Pin

1

J12

+12 V

TMS

TDI

GND

PCI_RSVD

MOT_RSVD

RST#

+3.3 V

NC (PME#)

AD30

GND

AD24

IDSEL

+3.3 V

AD18

AD16

GND

J22

TRST#

TDO

GND

PCI_RSVD

PCI_RSVD

+3.3 V

MOT_RSVD

MOT_RSVD

GND

AD29

AD26

+3.3 V

AD23

AD20

GND

C/BE2#

IDSELB

Pin

52

54

56

58

60

62

64

24

26

28

30

16

18

20

22

32

34

8

10

12

14

4

6

Pin

2




53

55

57

59

45

47

49

51

61

63

Pin

35

37

39

41

43

J12

TRDY#

GND

PERR#

+3.3 V

C/BE1#

AD14

M66EN

AD08

AD07

+3.3 V

MOT_RSVD

MOT_RSVD

GND

ACK64#

GND

J22

+3.3 V

STOP#

GND

SERR#

GND

AD13

AD10

+3.3 V

REQB_L

GNTB_L

GND

EREADY

NC (RESETOUT_L)

+3.3 V

NC (MONARCH#)


7

9

11

13

3

5

Pin

1

15

17

PCI_RSVD

GND

C/BE6#

C/BE4# (Note 1)

VIO

AD63

AD61

GND

AD59

J13/J23

GND

C/BE7#

C/BE5#

GND

PAR64

AD62

GND

AD60

AD58


54

56

58

60

46

48

50

52

62

64

Pin

36

38

40

42

44

8

10

12

14

4

6

Pin

2

16

18

67


68

GND

AD47

AD45

VIO

AD43

AD41

GND

AD39

AD57

VIO

AD55

AD53

GND

AD51

AD49

AD37

GND

AD35

AD33

VIO

PCI_RSVD

PCI_RSVD

GND


37

39

41

43

29

31

33

35

Pin

19

21

23

25

27

53

55

57

59

45

47

49

51

61

63

J13/J23

GND

AD56

AD54

GND

AD52

AD50

GND

AD48

AD46

GND

AD44

AD42

GND

AD40

AD38

GND

AD36

AD34

GND

AD32

PCI_RSVD

GND

PCI_RSVD

Table 3-9 PMC Connector Pin Assignments, J14/J24

Pin

1 PMCIO1

J14/J24

PMCIO2

Pin

2


38

40

42

44

30

32

34

36

Pin

20

22

24

26

28

54

56

58

60

46

48

50

52

62

64


PMCIO33

PMCIO35

PMCIO37

PMCIO39

PMCIO41

PMCIO43

PMCIO45

PMCIO47

PMCIO49

PMCIO51

PMCIO53

PMCIO55

PMCIO3

PMCIO5

PMCIO7

PMCIO9

PMCIO11

PMCIO13

PMCIO15

PMCIO17

PMCIO19

PMCIO21

PMCIO23

PMCIO25

PMCIO27

PMCIO29

PMCIO31

Table 3-9 PMC Connector Pin Assignments, J14/J24 (continued)

45

47

49

51

53

55

37

39

41

43

29

31

33

35

21

23

25

27

13

15

17

19

Pin

3

5

7

9

11

PMCIO30

PMCIO32

PMCIO34

PMCIO36

PMCIO38

PMCIO40

PMCIO42

PMCIO44

PMCIO46

PMCIO48

PMCIO50

PMCIO52

PMCIO54

PMCIO56

J14/J24

PMCIO4

PMCIO6

PMCIO8

PMCIO10

PMCIO12

PMCIO14

PMCIO16

PMCIO18

PMCIO20

PMCIO22

PMCIO24

PMCIO26

PMCIO28

46

48

50

52

54

56

38

40

42

44

30

32

34

36

22

24

26

28

14

16

18

20

Pin

4

6

8

10

12


69


Table 3-9 PMC Connector Pin Assignments, J14/J24 (continued)

Pin

57

59

61

63

PMCIO57

PMCIO59

PMCIO61

PMCIO63

J14/J24

PMCIO58

PMCIO60

PMCIO62

PMCIO64

Pin

58

60

62

64

3.3.7

Ethernet Connector

There are two Ethernet ports on the front panel through a single connector J6.

J6 is a single housing with two RJ-45 ports. The pin configuration is based on IEEE standards

802.3ab-1999.

3.3.8

USB Connector

There is one standard 4-pin USB connector located on the front panel.

Figure 3-2 USB Connector Pinout

70



3.3.9

Serial Port Connector, J16

The serial port connector (COM1) is located on the front panel.

Figure 3-3 Serial Port Connector Pinout, J16

1

3

4

5

1

2

Not Connected

RXD

TXD

Not Connected

GND

5

6

9

Not Connected

RTS#

CTS#

Not Connected

6

7

8

9

Note: G1 and G2 are connected to ground.

3.3.10 Board Insertion/Extraction Connector, P1

A board insertion and extraction connector is located near the front panel. This connector is used to detect a board insertion or extraction event. The latch connector on the front panel is connected to this connector.

Table 3-10 Front Panel Latch Pinout, P1

2

3

Pin Number

1

G1

G2

Signal

GND

BOARD_EJECT

FP_EJECTSW

NC

NC

Pins 1 and 2 indicate board insertion or extraction status. Pin 2 is used with the PCI Bridge while pin 3 is used with the IPMI controller.

A closed latch indicates board insertion. In this case, pin 2 and 3 are shorted and

FP_EJECTSW = 1, BOARD_EJECT = 0.


71


3.3.11 DDR3 SO-DIMM Connectors, XJ1 and XJ2

The CPCI-6200 provides two 204-pin DDR3 SO-UDIMM connectors for installing DDR3

SDRAMs.

Table 3-11 DDR3 SO-DIMMs Pinout, XJ1 and XJ2

39

41

43

45

31

33

35

37

23

25

27

29

15

17

19

21

7

9

11

13

3

5

Pin Number Signal

1 VREFDQ

VSS 4

DQ0 6

Pin Number Signal

2

Pin Number

VSS 103

Signal Pin Number

A3 104

Signal

A4

DQ4 105

DQ5 107

A1

A0

106

108

A2

BA1

DQ1 8

VSS

DM0

DQ2

10

12

14

VSS 109

DQS0#

DQS0

VSS

111

113

115

VDD

CK0

CK0#

VDD

110

112

114

116

VDD

PAR_IN/CK1

ERR_OUT/CK1#

VDD

DQ3

VSS

DQ8

DQ9

VSS

DQS1#

DQS1

VSS

16

18

20

22

24

26

28

30

DQ6

DQ7

VSS

DQ12

DQ13

VSS

DM1

RESET#

117

119

121

123

125

127

129

131

A10/AP 118

BA0 120

WE#

VDD

CAS#

CS0#

CS1#

VDD

122

124

126

128

130

132

CS3#

CS2#

RAS#

VDD

ODT0

ODT1

A13

VDD

DQ10

DQ11

VSS

DQ16

DQ17

VSS

DQS2#

DQS2

40

42

44

46

32

34

36

38

VSS

DQ14

DQ15

VSS

DQ20

DQ21

DM2

VSS

133

135

137

139

141

143

145

147

DQ32

DQ33

134

136

VSS 138

DQS4# 140

DQS4

VSS

DQ34

DQ35

142

144

146

148

DQ36

DQ37

VSS

DM4

DQ38

DQ39

VSS

DQ44

72



Table 3-11 DDR3 SO-DIMMs Pinout, XJ1 and XJ2 (continued)

89

91

93

95

97

99

81

83

85

87

73

75

77

79

65

67

69

71

57

59

61

63

49

51

53

55

Pin Number

47

Signal

VSS

Pin Number

48

DQ18 50

DQ19 52

VSS 54

DQ24 56

Signal

DQ22

Pin Number Signal

149 VSS

DQ40 DQ23 151

VSS 153

DQ28 155

DQ29 157

Pin Number

150

152

DM5 158

Signal

DQ45

VSS

DQS5#

DQS5

VSS

DQ25 58

DM3

VSS

DQ26

DQ27

VSS

CB0

CB1

60

62

64

66

68

70

72

VSS 159

DQS3# 161

DQS3

VSS

DQ30

DQ31

VSS

CB4

163

165

167

169

171

173

DQ43

VSS

DQ48

DQ49

VSS

DQS6

162

164

166

168

170

DQS6# 172

174

DQ46

DQ47

VSS

DQ52

DQ53

VSS

DM6

DQ54

VSS

DQS8#

DQS8

VSS

CB2

CB3

VDD

CKE0

CKE1

BA2

VDD

A12/BC#

A8

A5

74

76

78

80

82

84

86

88

90

92

94

96

98

100

CB5

DM8

VSS

CB6

CB7

VREFCA

VDD

A15

A14

A9

VDD

A11

A7

A6

175

177

179

181

183

185

187

189

191

193

195

197

199

201

VSS

DQ50

DQ51

VSS

DQ56

DQ57

VSS

DM7

DQ58

DQ59

VSS

SA0

176

178

180

182

184

186

188

190

192

194

196

198

VDDSPD 200

SA1 202

DQ55

VSS

DQ60

DQ61

VSS

DQS7#

DQS7

VSS

DQ62

DQ63

VSS

EVENT#

SDA

SCL


73


Table 3-11 DDR3 SO-DIMMs Pinout, XJ1 and XJ2 (continued)

Pin Number Signal

101 VDD

Pin Number Signal

102 VDD

Pin Number Signal

203 VTT

Pin Number Signal

204 VTT

3.3.12 PCI Express Expansion Connector, J17

The CPCI-6200 provides PCI Express expansion capability through 76-pin Mictor connector.

GND

TX2_P

TX2_N

GND

TX3_P

TX3_N

GND

CLK_P

Signal

GND

TX0_P

TX0_N

GND

TX1_P

TX1_N

CLK_N

GND

NC

NC

INT#

GND

Table 3-12 PCI Express Expansion Connector Pinout, J17

29

31

33

35

37

39

21

23

25

27

13

15

17

19

Pin Number

1

3

5

7

9

11

30

32

34

36

38

40

22

24

26

28

14

16

18

20

Pin Number

2

4

6

8

10

12

GND

RX2_P

RX2_N

GND

RX3_P

RX3_N

GND

NC

Signal

GND

RX0_P

RX0_N

GND

RX1_P

RX1_N

NC

GND

NC

END#

RESET#

GND

74



GND

NC

NC

GND

NC

NC

GND

NC

Signal

NC

NC

GND

NC

NC

NC

TDI

TRST#

TMS

TCK

GND

GND

GND

GND

GND

Table 3-12 PCI Express Expansion Connector Pinout, J17 (continued)

59

61

63

65

51

53

55

57

Pin Number

41

43

45

47

49

75

G1

G3

G5

67

69

71

73

G7

G9

60

62

64

66

52

54

56

58

Pin Number

42

44

46

48

50

76

G2

G4

G6

68

70

72

74

G8

G10

GND

NC

NC

GND

NC

NC

GND

NC

Signal

NC

NC

GND

NC

NC

NC

TDO

I2C_CLK

I2C_DATA

PRESENT#

GND

GND

GND

GND

GND


75


3.3.13 IPMI Debug and FW Programming Header, P3

The CPCI-6200 provides one 4-pin planar header connected to IPMI serial port 2 for debugging and programming IPMI firmware.

Table 3-13 IPMI Debug Pinout, P3

2

3

Pin Number

1

4

Signal

TXD

GND

RXD

GND

3.3.14 Processor Debug Header, P4

The CPCI-6200 has a 10-pin header for debugging. This header can debug a DDR or LBC interface.

Table 3-14 Processor Debug Header Pinout, P4

5

7

9

Pin Number

1

3

Signal

GND

TRIG_IN

TRIG_OUT

MDVAL

3.3V

Signal

MCRCID_0

MCRCID_1

MCRCID_2

MCRCID_3

MCRCID_4

6

8

10

Pin Number

2

4

76



3.3.15 Boundary Scan Header, P5

The CPCI-6200 uses a standard 20-pin boundary scan port header that provides an interface for programming the onboard PLDs, and boundary scan testing and debugging.

Table 3-15 Boundary Scan Header Pinout, P5

15

17

19

7

9

11

13

3

5

Pin Number

1

Signal

TCK

TDO

TMS

TRST#

TDI

Key (no pin)

GND

GND

GND

GND

NC

NC

NC

Signal

GND

GND

GND

GND

BSCAN_EN#

NC

BSCAN_AW#

16

18

20

8

10

12

14

4

6

Pin Number

2

3.3.16 Processor COP Header, P6

The CPCI-6200 uses one standard 16-pin header to provide access to the COP function.

Table 3-16 COP Header Pinout, P6

7

9

11

13

3

5

Pin Number

1

Signal

CPU_TDO

CPU_TDI

Pull up

CPU_TCK

CPU_TMS

CPU_SRST#

CPU_HRST#

Signal

Not Connected

CPU_TRST#

CPU_VIO pull-up

CPU_CKSTPI#

Not Connected

GND (optional pull-down)

Key (no pin)

8

10

12

14

4

6

Pin Number

2


77


Table 3-16 COP Header Pinout, P6 (continued)

Pin Number

15

Signal

CPU_CKSTPO#

Signal

GND

Pin Number

16

3.3.17 PCI Express Switch Header, P7

There is one standard 10-pin header located on the CPCI-6200 that provides the debug capability of the PCI Express device PLX8624 using the I

2

C bus. The connector connects to the

Aardvark I

2

C/SPI Host Adapter. This header is only used for prototype debugging and is not installed in the released product.

Table 3-17 PCI Express Switch Header Pinout, P7

7

9

3

5

Pin Number

1

Signal

SCL

SDA

NC

NC

NC

Signal

GND

NC

NC

NC

GND

4

6

Pin Number

2

8

10

3.4

Switches

3.4.1

Onboard Switches

For information on switch settings, see

Hardware Configuration

on page 47 .

78



3.4.2

Reset/Abort Switch, P2

There is one push button switch located on the front panel that provides access to board reset and abort function.

Table 3-18 Front Panel Reset Switch Pinout, P2

Pin Number

1

2

Signal

FP_SWITCH

GND

This is a multifunction switch. When the switch is pushed for one to three seconds, an abort is issued. When switch is pushed for five or more seconds, it is treated as reset function.

3.5

Front Panel LEDs

The CPCI-6200 provides two physical (three logical) LEDs on the front panel.

The blue LED indicates hot swap status, and is used during board insertion and extraction.

The second LED is a bi-color LED: green and yellow.



The green LED is completely controlled by the user through the programmable register

Front Panel LEDs Control and Status Register

.



The yellow LED indicates failure. The yellow LED lights up when any one or more of the following conditions occur:

– HRESET is asserted.

– +5 V supply failed (5V_PGOOD signal is low).

– The system watchdog times out.

– A user has set bit 0=0 in Front Panel LEDs Control and Status Register.


79


3.6

Status Indicators

The CPCI-6200 provides four front panel status indicators as well as multiple planar status indicators that are used for general board function status and Ethernet link/speed/activity status.

Table 3-19 CPCI-6200 Status Indicators

Function

Board Fail/User 1

Location

Front panel

Label

User / Fail

Color

Orange

User 2

TSEC1 Link/Speed

TSEC1 Activity

TSEC2 Link/Speed

TSEC2 Activity

TSEC3 Link/Speed

TSEC3 Activity

Front panel

Front panel

Front panel

Front panel

Front panel

Onboard

Onboard

User / Fail

ENET 1 SPEED

ENET 1

ACT

ENET 2 SPEED

ENET 2

ACT

Yellow - D31

Green - D32

D28

Green

Off

Yellow

Green

Off

Blinking Green

Off

Yellow

Green

Off

Blinking Green

Off

Yellow

Green

Off

Blinking Green

Description

This indicator lights up during a hard reset and remains lit until software turns it off.

This LED is completely user programmable.

No link

10/100 BASE-T operation

1000 BASE-T operation

No activity

Activity is proportional to bandwidth utilization.

No link



No activity


No link



No activity


80



Table 3-19 CPCI-6200 Status Indicators (continued)

Function

TSEC4 Link/Speed

Location

Onboard

Label

Yellow - D30

Green - D29

TSEC4 Activity Onboard D27

Color

Off

Yellow

Green

Off

Blinking Green

Description

No link



No activity



81


82


Chapter 4

Functional Description

4.1

Overview

The CPCI-6200 is based on Freescale’s MPC8572 integrated processor. CPCI-6200 provides the following:





A USB 2.0 interface

Compact PCI interfaces









Dual 32–64 bit/33–133 MHz PCI/PCI-X PMC sites

128 MB of NOR flash and up to 8 GB of NAND flash

Up to 4 GB of DDR3 SDRAM

Quad 10/100/1000 Ethernet and three serial ports

This board supports front and rear I/O. Access to rear I/O is available with a rear transition module (RTM).

The CPCI-6200 provides front panel access to one serial port with a mini DB-9 connector, two10/100/1000 Ethernet ports with two RJ-45 connectors, and one USB port with a type A connector.

The front panel includes a bi-color LED as User/Fail indicator, hot swap blue LED, and a reset/abort switch.

The RTM provides rear panel access to two serial ports (one with an RJ-45 connector) and two

10/100/1000 Ethernet ports with two RJ-45 connectors. The RTM also provides two planar connectors for one PMC I/O Module (PIM) with front I/O.


83


84

Figure 4-1 CPCI-6200 Block Diagram

DDR 3 SDRAM

SO-DIMM Socket

(upto 2GB)

Flash A

128 MB

Flash B

4 – 8 GB

MRAM

512KB

CPLD

Timer/Reg

TL16C2550

DUART

SRAM

64K x 16

Renesas

H8S

IPMI

I

2

C

UART

I

2

C

I

2

C

USER

EEPROM

512 Kb

Temp

ADT7461

VPD /

FRU/ SDR

512 Kb

MUX

PLD

SEL

512 Kb

COM3

COM4

PHY

5482

I

2

C

DDR2/ 3

MC

LBC

DUART

DUART

Dual Core 8572

Processor

TSEC4

TSEC3

TSEC2

TSEC1

DDR2/3

MC

I

2

C

I

2

C

RTC

M41 T83

DDR 3 SDRAM

SO-DIMM Socket

(upto 2GB)

User

EEPROM

512Kb

I

2

C PCIe PCIe

VPD

EEPROM

64Kb

PCIe Expansion x1 x4 x4

E2P

Tsi384 x4

PCIe

Switch x4

E2P

Tsi384 x4

E2P

Tsi384

PMC1 I/O

Single-wide PMC1

PCI/PCI-X,64/32 Bit,

133/100/66/33 MHz

PMC2 I/O

Single-wide PMC2

PCI/PCI-X,64/32 Bit,

133/100/66/33 MHz

COM1

E2P

Tsi381

USB

Controller

XCVR

RS232

PHY

5482

PLX

PCI6466

PCI to PCI

Universal Bridge

SROM cPCI

J5

IPMB 0

IPMB 1 cPCI

J3 cPCI

J1/J2

Front

Panel



4.2

MPC8572 Integrated Processor

TheCPCI-6200 supports the MPC8572 (dual e500 core) processor. The MPC8572 is an integrated processor with built-in DDR2/3 memory controllers (it supports two sides, up to four banks per side), PCI Express interfaces, four 10/100/1000 Ethernet fast ports, dual universal asynchronous receiver and transmitter (DUART), I

2

C controller, local bus interface, etc.

The processor is configured to operate at 1.33 or 1.5 GHz core frequency with up to 800 MHz data rate DDR3 memory bus.

4.3

I

2

C Serial Interface and Devices

The CPCI-6200 has several I

2

C buses, including two on the processor. The following sections describe each bus and the serial devices connected to each bus.

4.3.1

I

2

C Bus 0

Bus 0 is connected between the IPMI controller and J1 connector as required by PICMG 2.0.

There is no onboard I

2

C device on this bus.

4.3.2

I

2

C Bus 1

Bus 1 is connected between the IPMI controller and J2 connector as required by PICMG 2.0.

There is no onboard I

2


4.3.3

I

2

C Bus 2

Bus 2 is connected between the IPMI controller and PCI Express expansion connector. There is no onboard I

2



85


4.3.4

I

2

C Bus 3

Bus 3 is connected between the IPMI controller and the following onboard I

2

C devices:





ADT7461 temperature sensor

64 KB user EEPROM





64 KB FRU/SDR EEPROM

64 KB SEL EEPROM used for system event log data

4.3.5

I

2

C Bus 4

Bus 4 is connected between the IPMI controller, processor, J5 connector and the following onboard I

2

C devices:



8 KB VPD EEPROM







Two 64 KB EEPROM for user configuration data storage

M41T83 Real Time Clock

SPD EEPROMs of DDR3 (on DIMM modules)

The I

2

C interface is routed to the J5 connector to provide access to the serial EEPROM located on the rear transition module.

4.3.6

I

2

C Bus 5

Bus 5 is connected between the IPMI controller and processor providing intercommunication between the two. There is no onboard I

2


4.4

System Memory

The MPC8572 includes two memory controllers, which operate in asynchronous mode i.e., the

DDR3 clocks are derived from a separate external clock oscillator.

This board supports one bank of memory on each controller, using either 1 GB or 2 GB DDR3

SODIMM. This provides memory configurations of 2 and 4 GB. This board also supports memory speeds of up to 400 MHz.

86



DDR3 memory is implemented using external SO-UDIMM, unbuffered, ECC-supported modules.

4.5

Timers

The timing functions are provided by eight 32-bit timers that are integrated into the processor.

These timers are clocked by the real-time clock (RTC) input, which is driven by a 1 MHz clock.

There are also four independent 32-bit timers in a programmable logic device (PLD). The clock source for the four 32-bit timers in the PLD is derived from 25 MHz. The timer prescaler register must be configured to generate the desired timer reference (default is 1 MHz).

4.6

Ethernet Interfaces

This board provides four 10/100/1000 full duplex Ethernet interfaces using the MPC8572 integrated Ethernet controllers. Two Broadcom BCM5482S PHYs are used. The Ethernet ports on the processor are configured to operate in reduced Gigabit media independence interface

(RGMII) mode. Two Gigabit Ethernet interfaces are routed to the RJ-45 connectors on the face plate. These connectors have integrated LEDs. The other two Gigabit Ethernet interfaces are routed to J3 for rear I/O.

4.7

Local Bus Interface

This board uses the processor's local bus controller (LBC) for access to onboard flash memory and I/O registers. The LBC has programmable timing modes to support devices of different access times, as well as device widths of 8, 16, and 32 bits. The CPCI-6200 uses the LBC in general purpose chip select machine (GPCM) mode to interface to two physical banks of onboard flash, MRAM, and onboard 32-bit timers, along with control and status registers.

4.7.1

Flash Memory

This board provides 128 MB of soldered NOR flash memory. Two AMD Spansion MirrorBit 3.0 V devices are configured to operate in 16-bit mode to form a 32-bit flash bank. This flash bank is connected to LBC Chip Select 0, and it also acts as the boot bank.

CPCI-6200 also includes a second NAND flash bank that is connected to LBC Chip Select 1. This bank can be up to 16 GB. However, only 4 and 8 GB are supported at this time.


87


A hardware flash bank write protect switch is provided on the CPCI-6200 to enable write protection of the NOR flash. Regardless of the state of the software flash write protect bit in the

NOR Flash Control/Status register, write protection is enabled when this switch is ON. When this switch is OFF, write protection is controlled by the state of the software flash write protect bits and can only be disabled by clearing this bit in the NOR FLASH Control/Status register. Note that the F_WE_HW bit reflects the state of the switch and is only software readable whereas the F_WP_SW bit supports both read and write operations.

CPCI-6200 provides a dual boot option. You can boot from one of two separate boot images in the boot flash bank called boot block A and boot block B. Boot blocks A and B are both 1 MB in size and are located at the top (highest address) 2 MB of the boot flash memory space. Boot block A is located at the highest 1 MB block, while boot block B is in the next highest 1 MB block. A flash boot block switch is used to select between block A and block B. When the switch is OFF, the flash memory map is normal and block A is selected. When the switch is ON, block

B is mapped to the highest address. The MAP_SELECT bit in the Flash Control/Status register can disable the jumper and restore the memory map to the normal configuration where block

A is selected.

For additional information, see

NOR Flash Control and Status Register

on page 194

and

Local Bus

Controller Memory Map

on page 187 .

Figure 4-2 Boot Block A

88



Figure 4-3 Boot Block B

4.7.2

MRAM (Magnetoresistive Random Access Memory)

This board includes a 512 KB MRAM device that is connected to the processor's local bus. This memory device provides a non-volatile memory that has unlimited writes, fast access, and long term data retention without power. The MRAM is organized as 256 K by 16.

4.7.3

Control and Timers PLD

The CPCI-6200 control and timers PLD resides on the local bus. This device provides the following functions:



Local bus address latch











Chip selects for flash banks and real time clock

System control and status registers

Four 32-bit tick timers

Watchdog timer

Real time clock 1 MHz reference clock


89


4.7.4

Serial COM Ports

This board supports four serial ports. Two serial ports, COM1 and COM2, are provided through the built-in DUART interface of the processor. The remaining two ports, COM3 and COM4, are provided by TL16C2550 on the local bus.

COM1 is routed to the front panel.

COM2 is for internal use only.

COM3 and COM4 are multiplexed through the serial MUX PLD and routed to the RTM through the J5 connector.

4.8

DUART Interface

The DUART interface provides two serial ports COM1 and COM2 to CPCI-6200. COM1 provides a front access asynchronous serial port interface using Serial Port 0 from the MPC8572 DUART.

The TTL-level signals SIN, SOUT, RTS and CTS from Serial Port 0 are routed through onboard

EIA-232 drivers and receivers to the mini DB-9 front panel connector.

COM2 provides an asynchronous serial port interface using Serial Port 1 from the MPC8572

DUART. COM2 is routed to the IPMI controller and is used internally to facilitate communication between processor and IPMI controller.

90



4.9

PCI Express Port

The processor is configured for two x4-lane PCI Express ports. PCIe 1 is connected to a six-port

PEX8624 PCI Express switch. PCIe 2 is connected to a PCI Express expansion connector. Port 0 of PEX8624 is configured as an upstream port while the rest is configured as downstream ports. Each downstream port is connected to a PCI/PCI-X bridge. Each PCI Express lane is capable of supporting a data rate of 2.5 Gb/s.

Figure 4-4 PCI Express Bus Topology

Dual Core 8572

Processor

PCIe 2 PCIe 1

PCIE5[3:0] x4

X4, Lane[0-3]

PCIe Expansion STN 0, Port 0

PCIE0[3:0]

X4, Lane[36-39] (used as X1 only)

X4, Lane[32-35]

PCIe

Switch

PEX8624

X4, Lane[24-27]

X4, Lane[28-31]

STN 1, Port 5

PCIE1[3:0]

STN 2, Port 9

PCIE4[0]

STN 2, Port 8

PCIE3[3:0]

STN 1, Port 6

PCIE2[3:0]

E2P

Tsi381

E2P

Tsi384

E2P

Tsi384

E2P

Tsi384

USB

PCI

Bus 4

PCI

Bridge

PCI

Bus 3

PCI-X

Bus 2

PMC 2

PCI-X

Bus 1

PMC 1


91


4.10 PCI/PCI-X Bus

Four separate PCI/PCI-X bus segments are implemented. These segments are connected to the processor through PCI Express bridges and a PCI Express switch.

PCI-X bus 1 and PCI-X bus 2 connect to PMC site 1 and PMC site 2, respectively, using a Tsi384 bridge. Both buses are configured dynamically to operate in 25/33/66 MHz PCI or

100/133 MHz PCI-X mode depending on the PMC installed.

PCI bus 3 connects to the PCI bridge (PCI6466) using a Tsi384 bridge and is configured for

66 MHz PCI mode.

PCI bus 4 connects to the USB controller using a Tsi381 bridge and is configured for 33 MHz PCI mode.

4.10.1 PCI Mezzanine Card Sites (PCI-X Bus 1 and 2)

This board provides two PMC sites that support standard PMCs or PrPMCs. Each PMC site has a separate PCI Express to PCI-X bridge.

The PMC connectors are placed to support two single-width PMCs or one double-width PMC.

Both PMC sites 1 and 2 support front PMC I/O and rear PMC I/O via the J3/J5 connectors. PMC

1 I/O is routed to the J3 connector while PMC 2 I/O is routed to J5 connector.

Only 3.3 V I/O PMC modules are supported.

4.10.2 PCI 6466 Universal Bridge (PCI Bus 3)

The Compact PCI interface for CPCI-6200 is provided by the PLX PCI6466 universal bridge.

The PCI6466 can operate in transparent and non-transparent mode, allowing CPCI-6200 to operate in the system slot or peripheral slot of a chassis. The primary side PCI bus operates with

64-bit, 66 MHz with PCI Express to PCI-X bridge. The secondary side (CPCI bus) can operate at

32-bit/33 MHz and 32–64 bit/66 MHz depending on the system configuration.

92



4.10.3 USB (PCI Bus 4)

The USB 2.0 host controller (NEC uPD720101) provides USB ports with integrated transceivers for connectivity with any USB-compliant device or hub. USB channel 1 is routed to a single USB connector located on the front panel. DC power to the front panel USB port is supplied via a

USB power switch. This power switch provides soft-start, current limiting, over current detection, and power enable for port 1.

4.10.4 PCI Bus Frequency

PCI 1 and 2 buses can operate from 33 MHz to 133 MHz depending on the PMC. The following table shows the frequency selection and supported configurations. The switch setting is controlled by the user while the rest of the signals are set automatically by the hardware.

Table 4-1 PCI Buses 1 and 2 Frequency Requirements

Mode and Bus Rate

PCI 25 MHz

PCI 33 MHz

PCI 50 MHz

PCI 66 MHz

PCI-X 50 MHz

PCI-X 66 MHz

PCI-X 100 MHz

PCI-X 133 MHz

Switch S1,

Position 5

1

ON

OFF

ON

OFF

OFF

OFF

OFF

ON

PCI_PCIXCAP PCI_SEL100

GND 1

GND

GND

GND

10K to ground

10K to ground

HIGH

HIGH

0

1

0

1

0

1

0

PCI_M66EN

0

0

1

1

1

1

1

1

1. Switch S1, Position 5 selects PCI 1 bus frequency, while Switch S2, position 8 selects PCI 2 bus frequency.

Note

Supported

Supported

Supported

Supported

Not Supported

Not Supported

Supported

Supported

4.11 Operation Modes

CPCI-6200 can be operated in three modes, with the PCI to PCI bridge (PCI6466) behaving differently in each mode.


93


4.11.1 System Controller Mode

In this mode, PCI6466 is configured in universal transparent mode.

The red lines indicate active signals, while the gray lines indicate inactive signals.

Figure 4-5 System Controller Mode

4.11.2 Peripheral Mode

In this mode, PCI6466 is configured in universal non-transparent mode.

94




Figure 4-6 Peripheral Mode

4.11.3 Stand Alone Mode

In this mode, PCI6466 is configured in non-transparent mode.


95



Figure 4-7 Stand Alone Mode

4.12 PCI Express Expansion

CPCI-6200 provides an additional module capability through the a 76-pin stacking connector.

This connector is connected to the second PCI Express port on the processor.

96



4.13 System Interrupts

CPCI-6200 provides several sources of interrupts that are handled by the processor. The processor supports 12 external interrupts. Interrupts coming through PCI Express switch

(PEX8624) are routed to the first four interrupts (IRQ0 – IRQ3). Interrupts coming through the

PCI Express expansion interface are routed to the next four interrupts (IRQ4-IRQ7). The remaining processor interrupts (IRQ8-IRQ11) are connected to LBPC CPLD interrupt sources.

Figure 4-8 Routing of Interrupt Sources


97


4.14 Clock Distribution

The clock function generates and distributes all of the clocks that are required for system operation.

The PCI Express clocks are generated using an eight-output differential clock driver. The

PCI/PCI-X bus clocks are generated by the bridge chips from the PCI Express clock. Additional clocks required by individual devices are generated near the devices using individual oscillators.

Figure 4-9 CPCI-6200 Clock Distribution Diagram

25MHz

Osc Clock

Buffer

25MHz

25MHz

25MHz

PHY 1

PHY 1

LBPC CPLD

25MHz

66.6

MHz

Osc

32. 6KHz

Crystal

PCIE0_CLK, 100MHz

PCIE1_CLK, 100MHz

PCIE2_CLK, 100MHz

Diff

Clock

Gen.

(ICS9F

G108)

PCIE4_CLK, 100MHz

PCIE7_CLK, 100MHz

PCIE5_CLK, 100MHz

PCIE3_CLK, 100MHz

PCIE6_CLK, 100MHz,

QA0

CLK_PCI3, 66MHz

QC2

CLK_DDR, 66MHz

QA1

P_PB_CLK, 66MHz

MPC

9446

QB0

33/66MHz

QC0

C_PLD_CLK, 66MHz

RTC

M41T83

10MHz

Osc

10MHz

Osc

1. 8MHz

Osc

MXCLK J5-D19

SMUX CPLD

Reset CPLD

8MHz

Osc

PCIe Switch

PCI1, TSi384

1 MHz

CLK_PCI1, 133/100/66MHz

H8S IPMI

PMC 1

PCI2, TSi384

CLK_PCI2, 100/66/33MHz

PMC 2

PCI4, TSi381

CLK_PCI4, 33MHz

PCIe Expan.

48MHz

Osc

PCI3, TSi384

Not Used

66.6 /

100MHz

Osc

125MHz

Osc

USB

PCIe

RTC

DDR3_CLK1

SYSCLK

Processor

8572

DDR3_CLK2

Ethernet

DDR3

SO-

DIMM

DDR3

SO-

DIMM

DDR CLK

PCI

6466

S_PB_CLK

66.6 MHz

Osc

(Not Used)

CPCI

CPLD

COM 3/4

TL16C552

Clock

Buffer

CY2309

PCI_BP_CLK0, 33/66MHz







J1 /

J2

98



4.15 MPC8572 System Clock

An oscillator drives the MPC8572 system clock. The following table details the clock frequencies for various processor configurations.

Table 4-2 System Clock Frequencies

Clock/CPU Configuration 1.33 GHz CPU Blade

SYSCLK (a)

CCB (Platform) (b)

66.67 MHz

533 MHz

Core 0/1 (c)

DDRCLK (d)

1.33 GHz

66.66 MHz

DDR3 clock to DIMM (e) 333 MHz

Notes b:a = 8:1 c:b = 5:2 e:d = 10:1

(divide by 2 internally)

1.5 GHz CPU Blade

100 MHz

600 MHz

1.5 GHz

66.66 MHz

400 MHz b:a = 6:1 c:b = 5:2 e:d = 12:1

(divide by 2 internally)

4.16 Reset Control Logic

There are multiple sources of reset on the CPCI-6200. The following table shows the reset sources and their effect on board reset. The effect of each reset source depends on the board's current status such as LRO switch setting, board in system or peripheral slot, Watchdog Control

Register value (WD_EN and SYS_RST), System Control Register value (SW_RST), CPCI Control and Status Register value (BP_RST_MASK), etc.

Table 4-3 Reset Sources

Reset Source

Power-up or Hot

Insertion

WD_EN SYS_RST

X

X

X

X

X

X

X

X

X

SW_RST

1

PB_RST_MASK LRO SW System Slot Function

X

X

X

X

ON

OFF

YES

NO

NO

Note 1

Note 1

Note 2


99


Table 4-3 Reset Sources (continued)

Reset Source

Abort/Reset

Switch, RTC,

IPMI, COP

HRESET

Software Reset

0

Watch Dog Local 1

0

0

1 Watch Dog

System

CPU X

X

X

0

X

X

WD_EN SYS_RST

X X

X

X

X

X

X

X

X

0

1

X

X

X

X

COP SRESET

COP TRESET

HSC Reset

X

X

X

X

IPMI Watch Dog

CPCI Backplane

Reset

X

X

X

X

X

X

SW_RST

1

X

X

X

X

1

1

1

1

0

0

X

X

X

X

X

X

X

X

PB_RST_MASK LRO SW System Slot Function

X

X

0

X

X

1

0

1

X

X

X

X

X

X

X

X

X

X

ON

OFF

ON

OFF

X

X

X

X

X

X

X

ON

OFF

X

X

X

X

X

YES

YES

NO

NO

YES

YES

NO

NO

X

X

YES

NO

NO

X

X

X

X

NO

Note 1

Note 2

Note 1

Note 2

Note 1

Note 2

Note 1

Note 2

Note 2

Note 1

Note 1

Note 1

Note 2

Note 3

Note 4

Note 5

Note 6

Note 1

1. Software reset (SW_RST) is generated when the software writes a valid pattern in the System Control Register.

Table 4-4 Reset Functions

Note

Reset Type

CPU, HRESET

CPU, SRESET

Note 1 Note 2

System Wide Local Reset

YES YES

NO NO

100

Note 3 Note 4 Note 5 Note 6

CPU SRESET CPU TRESET HSC Reset IPMI Reset

NO NO NO NO

YES NO NO NO



Table 4-4 Reset Functions (continued)

Note

Reset Type

Note 1 Note 2

System Wide Local Reset

CPU, TRESET

PCI / PCI-X

NO

YES

PHYs, COMs YES

USB, Flash, CPLDs YES

NO

YES

YES

YES

HSC Power

IPMI

NO

NO

PCI Bridge Primary YES

PCI Bridge

Secondary

YES

CPCI Backplane YES

NO

NO

YES

NO

NO

NO

NO

NO

NO

Note 3 Note 4 Note 5 Note 6

CPU SRESET CPU TRESET HSC Reset IPMI Reset

NO

NO

NO

NO

YES

NO

NO

NO

NO

NO

NO

NO

NO

NO

NO

NO

NO

NO

NO

NO

YES

NO

NO

NO

NO

YES

NO

NO

NO NO NO NO

4.16.1 Abort/Reset Switch

CPCI-6200 uses a single push button switch to provide both the abort and reset functions.

When the switch is depressed for less than three seconds, an abort interrupt is generated to the

MPC8572 PIC.

If the switch is held for more than three seconds, a board level reset is generated. For more information, see

Table 4-4 on page 100 .


101


4.16.2 Reset Timing

Different devices have different reset timing requirements. CPCI-6200 uses a Reset Control PLD to meet their requirements.

Table 4-5 Reset Timing Requirements

Device

8572

Reset Signal

CPU_HRESET_N

1

SRESET_N

2

Source of Reset

Reset CPLD

Minimum Reset

Time

Actual Reset

Time

260 μs

45 ns

PEX8624

1

Tsi384

1

Tsi384

1

Tsi384

1

Tsi384

1

5482, PHY_1

1

5482, PHY_2

1

CPCI CPLD

1

SMUX CPLD

1

LBPC CPLD

1

Reset CPLD

HRESET_N

HRESET_N

HRESET_N

HRESET_N

HRESET_N

HRESET_N

HRESET_N

Reset CPLD

Reset CPLD

Reset CPLD

Reset CPLD

Reset CPLD

Reset CPLD

Reset CPLD

HRESET_N

HRESET_N

HRESET_N

5V_PGOOD

Reset CPLD

Reset CPLD

Reset CPLD

MAX811M

3.3V_PGOOD MAX811S

HSC_RST_REQ_N Reset CPLD

1 μs

1 μs

1 μs

100 μs

1 μs

1 μs

1 μs

1 μs

2 μs

2 μs

LT1646, HSC

PCI-E Conn

1

TL16C2550

1

JTAG Router

PCI6466

PMC_1

2

PMC_2

3

HRESET Reset

3.3V_PGOOD

P_PB_RST_N

MAX811S

Reset CPLD

S_PB_RST_N Reset CPLD

PCI1_RST_N Tsi384_1

μs 125 μs

225 ms

1.35 ms

1.35 ms

125 μs

125 μs

125 μs

125 μs

125 μs

125 μs

125 μs

125 μs

125 μs

125 μs

200 ms

102



Table 4-5 Reset Timing Requirements (continued)

Device

USB

3

CPCI

Backplane

Reset

3

Flash A

1

Reset Signal Source of Reset

PCI4_RST_N Tsi381

PCI_BP_RST_N CPCI CPLD

1. With MotLoad reset command

2. PCI Specification

Minimum Reset

Time

1 ms

Actual Reset

Time

1.35 ms

4.17 RTC Battery

The CPCI-6200 provides onboard battery clips for holding a coin cell type battery. The clips allow for the quick and easy replacement of a 3 V button cell lithium battery (CR2430), which provides back-up power to the onboard M41T83 real-time clock (RTC). A battery switching circuit that is built into the RTC provides automatic switching between the 3.3 V and battery voltages. The battery is capable of providing backup power to the RTC for up to 12 years at nominal temperature.

For information on replacing the battery, see

Replacing the Battery

on page 227 .

4.18 IPMI Controller

The CPCI-6200 uses the Renesas 16-bit microcontroller H8S/2166 as IPMI controller. The controller has the following features:













115 I/O ports

Eight-channel analog-to-digital converter

Six I

2

C bus

Three serial ports

512 KB flash memory

40 KB SRAM


103


The controller operates at 32 MHz clock frequency derived from 7.37 MHz external oscillator.

An external SRAM is also added to increase the size of total SRAM available to IPMI firmware.

IPMI firmware resides in internal flash memory. A serial port and I

2

C bus is connected between

IPMI controller and processor for inter-communication.

You can set the IPMI controller to function as a baseboard management controller (BMC) or a peripheral management (PM) controller. The mode can be selected by a switch provided on the board. For more information on setting the IPMI controller, see

IPMI Configuration Switch, S2

on page 50

.

Various board signals are connected to the controller for managing and maintaining system event log functions.

4.18.1 Programming the IPMI Firmware

The CPCI-6200 provides a 4-pin planar header (P3) for programming IPMI firmware.

The IPMI firmware is programmed at the factory before the board is shipped. This section is included to explain how the firmware can be upgraded in the field if needed.

1. Set the switch S2 positions 2 and 3 to ON.

The IPMI controller enters programming mode. For more information, see

IPMI

Configuration Switch, S2

on page 50 .

2. Connect custom-made RS-232 cable to the computer and 4-pin planar header.

For more information, see

IPMI Debug and FW Programming Header, P3

on page 76

.

For information on custom RS-232 cable, contact Artesyn.

3. Download the firmware from the computer to the IPMI controller.

104



4.19 Programmable Devices

The CPCI-6200 uses many programmable devices that include Boot Flash, CPLDs and SROMs.

The following table shows the all programmable devices, their functions and programming methods.

Table 4-6 Programming Devices

U43

U69

U5

U39

U57

U34

U28

U30

U31

U36

Reference

Designator

U26

U27

U42

Description

EEPROM, 16KX8

EEPROM,16KX8

EEPROM,16KX8

EEPROM, 16KX8

EEPROM, 16KX8

EEPROM, 2 KB

CPLD, LC4128V, 100P TQFP CPCI Control PLD

CPLD, LC4064V, 48P TQFP Serial Mux PLD

CPLD 2210, BGA256

NOR FLASH, 512 MB

Local Bus Control PLD

BOOT Flash

NOR FLASH, 512 MB BOOT Flash

NAND FLASH, 4GX8, SLC Customer Use

NAND FLASH, 4GX8, SLC,

Function Pgm Method

PLX8624 Configuration N/A

Tsi384_1 Configuration N/A



Tsi381 Configuration N/A

PCI6466 Configuration MotLoad

Customer Use

ICT

ICT

ICT

MotLoad

MotLoad

Customer

Software

Customer

Software

U67

U49

U47

U48

U74

CPLD, LC4128V, 100P TQFP Reset Control PLD

EEPROM, 64K, SOIC-8 CPCI-6200 VPD

EEPROM 512K, 8P SOIC Customer Use

EEPROM 512K, 8P SOIC


Customer Use

IPMI, Customer Use

ICT

ICT

Customer

Software

Customer

Software

Customer

Software

Remark

Not Used

Not Used

Not Used

Not Used

Not Used

For customer use only

May not be populated on some boards





105


Table 4-6 Programming Devices (continued)

Reference

Designator

U84

Description


Function

IPMI, SEL

U12

U83

Microcontroller, TQFP144 IPMI Controller

EEPROM 512K, 8P SOIC IPMI FRU and SDR

Pgm Method

Customer

Software

ICT or through

P3 header

ICT or through

P3 header

Remark


0 to 1800 is address for FRU data; above

1800 is SDR data

4.19.1 Local Bus Control CPLD

This connects to the local bus controller of the processor. It provides access to boot flash,

NAND flash, MRAM, DUART and board registers. It also provides one watchdog timer, four tick timers, and collects interrupts from various sources and routes them to processor. It operates on a 25 MHz clock frequency.

4.19.2 Reset CPLD

This controls the reset function of the board. It generates reset for various board components

with varying timings. It also enables various power supplies. For more information, see

Reset

Control Logic

.

4.19.3 CPCI Control CPLD

This complex programmable logic device (CPLD) configures the PLX PCI bridge device for various operating modes. It controls PCI reset on back plane, enables CPCI signal terminations, collects interrupts from CPCI sources (in system slot) and routes them to the local bus control

CPLD. It also controls the hot swap LED. For more information, see

Operation Modes

.

4.19.4 Serial Multiplexer CPLD

This multiplexes the control lines of two serial port interfaces and routes them to the RTM through the backplane. This allows fewer signals to be routed to the RTM thereby conserving the total pin count requirement on J5 connector.

106


Chapter 5

Transition Module Preparation and Installation

5.1

Overview

This chapter provides hardware preparation and installation instructions for the CPCI-6115-

MCPTM transition module.

The CPCI-6115-MCPTM transition module provides additional I/O capabilities to the CPCI-

6200 SBC. The transition module is installed directly in the CompactPCI backplane in the rear transition board bay of the chassis and interfaces with the CPCI-6200 SBC through the J3 and

J5 connectors.

Rear panel connectors on the CPCI-6115-MCPTM include one of two configurations: two RJ-45 connectors for 10/100/1000BaseTx Ethernet and one RJ-45 connector for asynchronous serial port, COM1 (CompactPCI version); or four RJ-45 connectors for asynchronous serial ports,

COM1, COM2, COM3 and COM4 (MXP version). Only COM1 and COM2, however, are available on the CPCI-6200 SBC for use with the transition module. An additional two serial ports and the one EIDE channel are available on J3 and J5 from the baseboard.

The transition module supports two single-wide (74mm wide by 69mm long) PMC I/O modules. PMC I/O pins 1 through 64 of each PMC slot on the CPCI-6200 SBC are routed from the J3 and J5 connectors to the PMC I/O (PIM1 and PIM2) on the transition module. For a

detailed description of PMC I/O modules refer to the section titled

PMC I/O Modules

on page

126 .

Before installing your transition module, ensure that you have performed all tasks as described in

Chapter 2, Hardware Preparation and Installation for installing the CPCI-6200 prior to

configuring and installing the transition module.


107


5.2

Block Diagram

The block diagram for the CPCI-6115-MCPTM is shown in the following figure.

Figure 5-1 CPCI-6115-MCPTM Block Diagram

108



5.3

Preparing the Transition Module

The CPCI-6115-MCPTM (refer to

Figure 5-2 ) is used in conjunction with the CPCI-6200

baseboard. It includes the following features (IP version):

Figure 5-2 Connector and Header Locations (MXP Version)

J8

J5

PMC 1/O

MODULE 2

J20

J4

J24

PMC 1/O

MODULE 1

J10

J3

J14

J11

J1

J25

COM4

COM3

COM2

COM1

J6 J2









One 50-pin Type II connector for IDE CompactFlash cards or microdrives

Two PMC I/O modules (PIM)

Four asynchronous serial ports (COM1, COM2, COM3 and COM4)

I/O signal multiplexing (IOMUX)


109


5.4

Rear Panel Connectors

The rear panel port connectors on the CPCI-6115-MCPTM are listed in Table 5-1 and shown in

Figure 5-2 on page 109

. Refer to

Table 5-10 on page 121 for connector pinout information.

Table 5-1 CPCI-6115-MCPTM Rear Panel Connectors

Type

Serial Ports

Number Description

J25 Routed to four RJ-45 connectors for COM1, COM2, COM3, and

COM4 connections (MXP version). Note: COM3 and COM4 are not used.

5.5

On-Board Connectors and Headers

The following table lists the connectors and headers on the CPCI-6115-MCPTM. Use the links in the Location column to find the connector descriptions and pin assignments or jumper settings.

Table 5-2 On-Board Connectors and Headers

Connector/Header

CPCI-6115-MCPTM IDE CompactFlash Connector (J1)

CPCI-6115-MCPTM PMC I/O Module 1 - Host I/O Connector (J10)

CPCI-6115-MCPTM PMC I/O Module 2 - Host I/O Connector (J20)

CPCI-6115-MCPTM PMC I/O Modules 1 & 2 - PMC I/O (J14/J24)

CPCI-6115-MCPTM CompactPCI User I/O Connector (J3)

CPCI-6115-MCPTM CompactPCI User I/O Connector (J5)

CPCI-6115-MCPTM 10/100/1000BaseTx Connectors

COM1 Header (J6)

COM2 Header (J11)

Location

Table 5-3 on page 111







COM1 and COM2

Asynchronous Serial Ports

Jumpers

on page 123

COM1 and COM2

Asynchronous Serial Ports

Jumpers

on page 123

110



Table 5-2 On-Board Connectors and Headers (continued)

Connector/Header

CompactFlash Selection Header (J2)

Location

CompactFlash Jumper

on page 123

5.5.1

IDE CompactFlash Connector

One 50-pin Type II CompactFlash card header connector located on both standard and MXP versions of the CPCI-6115-MCPTM transition module provides the IDE interface to one

CompactFlash plug-in module. This CompactFlash interface is connected to the primary IDE channel. The pin assignments for these connectors are as follows:

Table 5-3 CompactFlash IDE Connector Pin Assignments, J1

11

12

13

14

7

8

9

10

15

16

17

5

6

3

4

Pin

1

2

GND

GND

GND

GND

+5 V

GND

GND

GND

GND

GND

DD3

DD4

DD5

DD6

DD7

CS1FX1_L

GND

J1

NO CONNECT

DD11

DD12

DD13

DD14

DD15

CS3FX1_L

NO CONNECT

DIOR_L

DIOW_L

+5 V

INTRQ1

+5 V

MASTER/SLAVE

NO CONNECT

DRESET_L

DIORDY

36

37

38

39

32

33

34

35

40

41

42

28

29

30

31

Pin

26

27


111


Table 5-3 CompactFlash IDE Connector Pin Assignments, J1 (continued)

Pin

18

19

20

21

22

23

24

25

DA2

DA1

DA0

DD0

DD1

DD2

NO CONNECT

NO CONNECT

J1

NO CONNECT

+5 V

DASP

PDIAG

DD8

DD9

DD10

GND

Pin

43

44

45

46

47

48

49

50

5.5.2

PMC I/O Module Connectors

There are two pairs of 64-pin surface mount connectors on both the standard and MXP version of the CPCI-6115-MCPTM to provide an interface for two optional add-on PMC I/O modules.

Each module has an identical PMC I/O connector and a unique Host I/O connector. All serial port signals are at TTL levels. The pin assignments are as follows:

On the host I/O connectors, a PMC I/O module only uses power, ground and the OUT-going serial port pins. A host I/O module could potentially use all pins except the OUT-going serial port.

On the PMC I/O connector, pin meaning is defined entirely by the PMC residing on the host.

A host I/O module would not use any pins on this connector.

112



5.5.2.1

Host IO Connectors

IN1_DCD

IN1_RXD

+5 V

IN1_DSR

IN1_CTS

IN1_RI

GND

IN2_TXD

IN2_DSR

IN2_RTS

+5 V

Not Connected

Not Connected

Not Connected

GND

Not Connected

Not Connected

Not Connected

+5 V

Not Connected

Not Connected

Not Connected

GND

Not Connected

Table 5-4 PMC I/O Module 1 - Host I/O Connector Pin Assignments, J10

21

23

25

27

13

15

17

19

5

7

9

11

Pin

1

3

37

39

41

43

29

31

33

35

45

47

J10

+12 V

IN1_TXD

IN1_DTR

IN1_RTS

+3.3 V

IN2_DCD

IN2_RXD

IN2_DTR

GND

IN2_CTS

IN2_RI

Not Connected

+3.3 V

Not Connected

Not Connected

Not Connected

GND

Not Connected

Not Connected

Not Connected

+3.3 V

Not Connected

Not Connected

Not Connected


22

24

26

28

14

16

18

20

6

8

10

12

Pin

2

4

38

40

42

44

30

32

34

36

46

48

113


114

Table 5-4 PMC I/O Module 1 - Host I/O Connector Pin Assignments, J10 (continued)

Pin

49

51

53

55

57

59

61

63

Not Connected

Not Connected

+5 V

OUT_DTR

OUT_CTS

OUT_RTS

-12 V

I2C_CLK

J10

GND

Not Connected

OUT_DCD

Not Connected

+3.3 V

OUT_RXD

OUT_TXD

I2C_DATA

Pin

50

52

54

56

58

60

62

64

Table 5-5 PMC I/O Module 2 - Host I/O Connector Pin Assignments, J20

21

23

25

27

13

15

17

19

29

31

5

7

9

11

Pin

1

3

Not Connected

DD3

+5 V

DD12

DD13

DD6

GND

DD15

CS3FX1_L

DIOR_L

+5 V

MASTER/SLAVE

IORDY

DA2

GND

DASP

J20

+12 V

DD11

DD4

DD5

+3.3 V

DD14

DD7

CS1FX1_L

GND

DIOW_L

DINTRQ1

DRESET_L

+3.3 V

DA1

DA0

DD0

22

24

26

28

14

16

18

20

30

32

6

8

10

12

Pin

2

4



Table 5-5 PMC I/O Module 2 - Host I/O Connector Pin Assignments, J20 (continued)

51

53

55

57

43

45

47

49

59

61

63

Pin

33

35

37

39

41

PDIAG

DD1

+5 V

DD9

Not Connected

Not Connected

GND

Not Connected

Not Connected

Not Connected

+5 V

OUT_DTR

OUT_CTS

OUT_RTS

-12 V

I2C_CLK

J20

GND

DD8

DD2

DD10

+3.3 V

Not Connected

Not Connected

Not Connected

GND

Not Connected

OUT_DCD

Not Connected

+3.3 V

OUT_RXD

OUT_TXD

I2C_DATA

5.5.2.2

PMC I/O Connectors

52

54

56

58

44

46

48

50

60

62

64

Pin

34

36

38

40

42

Table 5-6 PMC I/O Modules 1 and 2 - PMC I/O Connector Pin Assignments, J14/24

7

9

3

5

Pin

1 PMC IO1

PMC IO3

PMC IO5

PMC IO7

PMC IO9

J14/J24

PMC IO2

PMC IO4

PMC IO6

PMC IO8

PMC IO10

4

6

Pin

2

8

10


115


116

Table 5-6 PMC I/O Modules 1 and 2 - PMC I/O Connector Pin Assignments, J14/24 (continued)

PMC IO41

PMC IO43

PMC IO45

PMC IO47

PMC IO49

PMC IO51

PMC IO53

PMC IO55

PMC IO57

PMC IO59

PMC IO61

PMC IO63

PMC IO11

PMC IO13

PMC IO15

PMC IO17

PMC IO19

PMC IO21

PMC IO23

PMC IO25

PMC IO27

PMC IO29

PMC IO31

PMC IO33

PMC IO35

PMC IO37

PMC IO39

53

55

57

59

61

63

45

47

49

51

37

39

41

43

29

31

33

35

21

23

25

27

Pin

11

13

15

17

19

PMC IO38

PMC IO40

PMC IO42

PMC IO44

PMC IO46

PMC IO48

PMC IO50

PMC IO52

PMC IO54

PMC IO56

PMC IO58

PMC IO60

PMC IO62

PMC IO64

J14/J24

PMC IO12

PMC IO14

PMC IO16

PMC IO18

PMC IO20

PMC IO22

PMC IO24

PMC IO26

PMC IO28

PMC IO30

PMC IO32

PMC IO34

PMC IO36

54

56

58

60

62

64

46

48

50

52

38

40

42

44

30

32

34

36

22

24

26

28

Pin

12

14

16

18

20



5.5.3

CompactPCI User I/O Connector

Connector J3 is a 95-pin AMP Z-pack 2mm hard metric type AB connector. This connector routes the I/O signals for the PMC1 I/O, and two 10/100/1000Base-T ethernet ports. The pin assignments for J3 on the processor board and on the CPCI-6115-MCPTM are as follows:

(Outer row F is assigned and used as ground pins but is not shown in the table).

Table 5-7 User I/O Connector Pinout, J3

7

6

9

8

13

12

11

10

3

2

5

4

1

17

16

15

14

Pin

19

18

Row A Row B Row C

GND +12 V -12 V

LPa_DA+ (TX1+)* LPa_DA-(TX1-)* GND

LPa_DB+ (RX1+)* LPa_DB-(RX1-)* GND

LPb_DA+ (TX2+)* LPb_DA-(TX1-)* GND

LPb_DB+(RX2+)* LPb_DB-(RX2-)* GND

+3.3 V +3.3 V +3.3 V

PMC1IO5

PMC1IO10

PMC1IO15

PMC1IO20

PMC1IO25

PMC1IO30

PMC1IO35

PMC1IO40

PMC1IO45

PMC1IO50

PMC1IO55

PMC1IO60

IPMI_PWR

PMC1IO4

PMC1IO9

PMC1IO14

PMC1IO19

PMC1IO24

PMC1IO29

PMC1IO34

PMC1IO39

PMC1IO44

PMC1IO49

PMC1IO54

PMC1IO59

PMC1IO64

PMC1IO3

PMC1IO8

PMC1IO13

PMC1IO18

PMC1IO23

PMC1IO28

PMC1IO33

PMC1IO38

PMC1IO43

PMC1IO48

PMC1IO53

PMC1IO58

PMC1IO63

Row D

GND

LPa_DC+*

LPa_DD+*

LPb_DC+*

LPb_DD+*

+5 V

PMC1IO2

PMC1IO7

PMC1IO12

PMC1IO17

PMC1IO22

PMC1IO27

PMC1IO32

PMC1IO37

PMC1IO42

PMC1IO47

PMC1IO52

PMC1IO57

PMC1IO62

Row E

GND

LPa_DC-*

LPa_DD-*

LPb_DC-*

LPb_DD-*

+5 V

PMC1IO1

PMC1IO6

PMC1IO11

PMC1IO16

PMC1IO21

PMC1IO26

PMC1IO31

PMC1IO36

PMC1IO41

PMC1IO46

PMC1IO51

PMC1IO56

PMC1IO61

7

6

9

8

13

12

11

10

3

2

5

4

1

17

16

15

14

Pin

19

18


117


*Not connected on MXP version

Signal Description

PMCIO:

PMC1IO(64:1)

Ethernet:

PORTn_TXP

PORTn_TXN

PORTn_RXP

PORTn_RXN

PMC1 I/O signals 1 through 64 high side of differential transmit data low side of differential transmit data high side of differential receive data low side of differential receive data

5.5.4

CompactPCI User I/O Connector

Connector J5 is a 110 pin AMP Z-pack 2mm hard metric type B connector. This connector routes the I/O signals for the PMC2 I/O signals, the IDE port, four asynchronous serial ports and

I2C. The pin assignments for J5 on the processor board and the CPCI-6115-MCPTM are as follows:

(Outer row F is assigned and used as ground pins but is not shown in the table).

Table 5-8 User I/O Connector Pinout, J5

18

17

16

Pin Row A

22

21

DRESET_L

INTRQA

20

19

CS1FXA_L

Not

Connected

DIOWA_L

15

14

GND

DD9

DD5

DD0

DA0

DD14

DD10

DD6

DD1

Row B

COM4_TXD

COM4_RXD

CS3FXA_L

DIORDYA

Row C

COM3_TXD

COM3_RXD

DA2

DA1

TMCOM1_L

DD15

DD11

GND

DD2

Row D

COM2_TXD

COM2_RXD

MXDI

MXCLK

I2C_CLK

DIORA_L

DD12

DD7

DD3

Row E

COM1_TXD

COM1_RXD

MXDO

MXSYNC#

I2C_DATA 18

Not Connected 17

DD13 16

DD8

DD4

15

14

Pin

22

21

20

19

118



Table 5-8 User I/O Connector Pinout, J5 (continued)

2

1

4

3

6

5

8

7

Pin Row A

13 PMC2IO5

12

11

10

9

PMC2IO10

PMC2IO15

PMC2IO20

PMC2IO25

PMC2IO30

PMC2IO35

PMC2IO40

PMC2IO45

Row B

PMC2IO4

PMC2IO9

PMC2IO14

PMC2IO19

PMC2IO24

PMC2IO29

PMC2IO34

PMC2IO39

PMC2IO44

PMC2IO50

PMC2IO55

PMC2IO49

PMC2IO54

PMC2IO60 PMC2IO59

TMPRSNT_L PMC2IO64

Row C

PMC2IO3

PMC2IO8

PMC2IO13

PMC2IO18

PMC2IO23

PMC2IO28

PMC2IO33

PMC2IO38

PMC2IO43

PMC2IO48

PMC2IO53

PMC2IO58

PMC2IO63

Row D

PMC2IO2

PMC2IO7

PMC2IO12

PMC2IO17

PMC2IO22

PMC2IO27

PMC2IO32

PMC2IO37

PMC2IO42

PMC2IO47

PMC2IO52

PMC2IO57

PMC2IO62

Signal Descriptions

PMCIO:

PMC2IO(1:64)

EIDE Primary Port (ATA-2):

DIORA_L -

DIOWA_L -

DIORDYA -

DD(15:0) -

CS1FXA_L -

CS3FXA_L -

DA(2:0) -

DRESET_L -

Serial COM Ports 1-4:

PMC 2 I/O signals 1 through 64

I/O read

I/O write

indicates drive ready for I/O

IDE data lines chip select drive 0 or command register block select chip select drive 1 or command register block select drive register and data port address lines drive reset

Row E

PMC2IO1

PMC2IO6

PMC2IO11

PMC2IO16

PMC2IO21

PMC2IO26

PMC2IO31

PMC2IO36

PMC2IO41

PMC2IO46

PMC2IO51

PMC2IO56

PMC2IO61


2

1

4

3

6

5

8

7

Pin

13

12

11

10

9

119


Signal Descriptions

COMn_TD -

COMn_RD -

Miscellaneous:

TMPRSNT_L -

TMCOM1_L -

MXCLK -

MXSYNC_L -

MXDI -

MXDO -

I2C_CLK -

I2C_DATA -

COM Port n Transmit Data Output

COM Port n Receive Data Input indicates that the MCxx805TM is installed used to select COM1 active on processor board or on transition module multiplexed I/O signal clock, 10 MHz multiplexed I/O sync signal multiplexed I/O data-in signal from transition module multiplexed I/O data-out signal to transition module

I2C Serial Clock for transition module EEPROM

I2C Serial Data for transition module EEPROM

5.5.5

10/100/1000BaseTx Connectors

Two 10/100/1000BaseTx RJ-45 connectors are located on the rear panel of the standard version of the CPCI-6115-MCPTM to support Ethernet I/O from the CPCI-6200 SBC. The pin assignments for these connectors are as follows:

Table 5-9 10BaseT/100BaseTx Connector Pin Assignments

6

7

4

5

8

2

3

Pin

1

Signal

MDIO0+

MDIO0-

MDIO1+

MDIO2+

MDIO2-

MDIO1-

MDIO3+

MDIO3-

120



5.5.6

COM1 And COM2 Connectors (MXP Version)

Four RJ-45 connectors are located on the panel of the MXP version of the CPCI-6115-MCPTM to provide the interface to the COM1 and COM2 serial ports originating from the CPCI-6200

SBC. The CPCI-6200 only supports two serial ports, COM1 and COM2.

The COM1DIR jumper is a two position (three pin) jumper which controls the origin of the serial port. In one position, COM1 from the CPCI-6200 is enabled (and thereby disabling it on the

CPCI-6200 front panel connector). In the other position, the connector is redirected to the

PMC I/O module 1. The COM2DIR jumper is a two position (three pin) jumper which controls the origin of the serial port. In one position, COM2 from the CPCI-6200 is enabled. In the other position, the connector is redirected to the PMC I/O module 2.

The pin assignments for this connector is as follows:

Table 5-10 COM1, COM2 Connector Pin Assignments

6

7

4

5

8

2

3

Pin

1

Signal

DCD

RTS

GND

TXD

RXD

GND

CTS

DTR

5.5.7

RJ-45 to DB-9 Adapter for COM1 to PC COM1

The following information is provided for those users wishing to attach a console to an CPCI-

6200 COM1 port for the purpose of terminal emulation.

A prewired, completely shielded RJ-45 to DB-9 female adapter assembly with 8 position RJ-45 socket on one end to DB-9 socket on the other end is available through Artesyn. This can be ordered through Artesyn by requesting the following part number: MRJ45DB9ADP-01.


121


Connecting an CPCI-6200 to a PC terminal requires that the adapter described above be attached to a standard RJ-45-to-RJ-45 shielded cable with straight through signaling.

The pinout information for this adapter is in the following table:

Table 5-11 Wire Interconnection List RJ-45 to DB-9

RF-45 Signal

DCD

RTS

GND

TxD

RxD

GND

CTS

DTR

5

6

3

4

7

8

RJ-45 Pin

1

2

7

6

DB-9 Pin

4

8

5

2

3

OPEN

DB-9 Signal

DTR

CTS

GND

RxD

TxD

RTS

DSR

5.6

Jumper Settings

This section describes the jumper settings that are required for proper operation prior to installing the CPCI-6115-MCPTM transition module into a chassis backplane. Many boards are already factory configured based on customer requirements, but the jumper settings should be verified before installation.

Damage of the Product

Setting/resetting the switches during operation can cause damage of the product.

Check and change switch settings before you install the product.

122



5.6.1

CompactFlash Jumper

Jumper J2 controls the Master/Slave relationship between the planar socket (CompactFlash connector) and the PIM socket. By setting a jumper across pins 1 and 2 on jumper J2, the

CompactFlash device becomes the Master, and the PIM device becomes the Slave. By setting a jumper across pins 2 and 3 on jumper J2, the PIM device becomes the Master, and the

CompactFlash device becomes the Slave. If no jumper is installed, the board will default to the

CompactFlash as the Master device.

Figure 5-3 CompactFlash Jumper Settings (J2)

5.6.2

COM1 and COM2 Asynchronous Serial Ports Jumpers

The asynchronous serial ports (COM1 and COM2) are configured permanently as data circuit terminating equipment (DTE). The COM1 port is also routed to an RJ-45 connector on the front panel of the processor board. A terminal for COM1 may be connected to either the processor board or the transition module, but not both. If it is configured for the transition module, front panel access to COM1 is disabled.

Jumper J6 on the transition module controls the routing of the COM1 port to either the processor board front panel or through the PIM 1 socket on the transition module. When pins

1 and 2 are jumpered on J6, the COM1 signal is routed to the PIM1 socket on the transition module. When pins 2 and 3 are jumpered on J6 the COM1 signal is routed to the processor board front panel. Jumper J11 on the transition module controls the routing of the COM2 port


123


to either the processor board front panel or through the PIM2 socket on the transition module.

When pins 1 and 2 are jumpered on J11, the COM2 signal is routed to PIM2 on the transition module. When pins 2 and 3 are jumpered on J11, the COM2 signal is routed to the processor board front panel.

Figure 5-4 COM1 and COM2 Serial Port Jumpers (J6/J11)

5.7


The following subsections describe the major functional components of the CPCI-6115-

MCPTM transition module. There are certain differences between the IP version and the

CompactPCI model that are explained in the subsections where those differences apply.

5.7.1

IDE Flash

The CPCI-6200 SBC supports a single IDE channel routed to the J5 User I/O connector. The

CPCI-6115-MCPTM contains one 50-pin Type II connector which supports a removable IDE

CompactFlash memory card on the primary IDE channel. Refer to the

CompactFlash Jumper

on page 123 for the definition of this connector. The CompactFlash connector is not accessible

through the rear panel. The CPCI-6200 transition module must be removed in order to install a CompactFlash memory card.

124



Since the transition module receives its power from the host board through power pins on the backplane, it cannot be removed in a hot-swap chassis without first removing the associated host board, or by powering off the slot in some other way, via software or by toggling the lower lever of the associated host board, so the blue LED illuminates. Since the CompactFlash is an active component, and some PIMs are as well, damage to these active components may occur if the transition module is not properly powered down.

The CPCI-6115-MCPTM also routes the IDE signals to the host I/O connector of PMC I/O module 2. Refer to

Jumper Settings

on page 122 for more details.

Currently available CompactFlash memory cards provide from 2MB to 512MB. Once configured, this memory appears as a standard ATA (IDE) disk drive.

5.7.2

Ethernet Interface (CompactPCI Version)

The CPCI-6200 SBC provides three 10/100/1000Base-T Ethernet interfaces. Two of them are routed to the transition module and one is routed to the front panel.

The Ethernet Station Addresses are determined by the CPCI-6200 SBC and are not affected by the CPCI-6115-MCPTM.

5.7.3

Hot-Swap Support

The CPCI-6115-MCPTM is considered to be part of the CPCI-6200 SBC. Therefore, the CPCI-

6115-MCPTM cannot be swapped without first removing or powering down the CPCI-6200

SBC. All power for the CPCI-6115-MCPTM is provided from the CPCI-6200 SBC through pins on the J3 I/O connector.

5.7.4

Serial EEPROM

The CPCI-6115-MCPTM contains a 512 x 8 Serial EEPROM. The Serial EEPROM provides for storage of the transition module configuration information. The default I2C address for this

EEPROM is $A8, but optional resistors can be used allowing population options to configure this part to respond to any standard I2C address.


125


5.7.5

PMC I/O Modules

CPCI-6200 SBC supports two single-wide PMC sites. Each site provides four 64-pin EIA-E700

AAAB connectors to interface to a 32/64-bit IEEE P1386.1 PMC. One of the four connectors is dedicated to user I/O. Two PMC I/O modules are supported on the CPCI-6115-MCPTM, one per

PMC site on the CPCI-6200 SBC. The CPCI-6200 SBC maps the PMC user I/O pins onto the

CompactPCI J3 and J5 connectors. The CPCI-6115-MCPTM reverses the mapping and brings the signals to a 64-pin EIA-E700 AAAB connector to interface with the PMC I/O module. This causes a one-to-one correspondence in the pinout between the PMC on the CPCI-6200 SBC and the PMC I/O module on the CPCI-6115-MCPTM. Refer to the section titled PMC I/O Module for a detailed description of PMC I/O modules.

5.7.6

Asynchronous Serial Ports

The CPCI-6200 SBC contains two asynchronous serial ports that are routed to the J5 user I/O connector. Serial port 1 (COM1) is also wired as an RS-232 interface to an RJ-45 connector on the front panel. A jumper (J6) on the CPCI-6115-MCPTM enables the COM1 port either on the

CPCI-6200 SBC or the transition module. One version of the CPCI-6115-MCPTM employs four

RJ-45 connectors on the rear panel of the transition module for COM1, COM2, COM3 and

COM4 respectively. Note: only COM1 and COM2 can be used.

126



Due to pin limitations of the J5 connector, the CPCI-6200 SBC multiplexes the serial channel control signals between the CPCI-6200 SBC and the CPCI-6115-MCPTM. This hardware function is transparent to software. The block diagram for the signal multiplexing on the transition module is shown in the following figure:

Figure 5-5 Signal Multiplexing Diagram

5.7.6.1

I/O Signal Multiplexing (IOMX)

The CPCI-6115-MCPTM uses a PLD to generate the IOMUX function. The CPCI-6200 SBC uses a similar device. There are four pins that are used for the IOMX function: MXCLK, MXSYNC#,

MXDO and MXDI. MXCLK is the 10 MHz bit clock for the time-multiplexed data lines MXDO and

MXDI. MXSYNC# is asserted for one bit time at Time Slot 15 by the CPCI-6200 SBC. MXSYNC# is used by the CPCI-6115-MCPTM to synchronize with the CPCI-6200 SBC. MXDO is the timemultiplexed output line from the CPCI-6200 and MXDI is the time-multiplexed line from the


127


CPCI-6115-MCPTM. A 16-to-1 multiplexing scheme is used with a 10 MHz bit rate. Sixteen time slots are defined and allocated as follows:

Table 5-12 Multiplexing Sequence of the IOMX Function

8

9

10

11

6

7

4

5

12

13

14

15

2

3

0

1

MXDO

(From CPCI-6200 SBC)

Time Slot Signal Name

RTS3

DTR3

RTS1

RTS2

RTS4

DTR4

Reserved

Reserved

Reserved

DTR1

DTR2

Reserved

Reserved

Reserved

Reserved

Reserved

8

9

10

11

6

7

4

5

12

13

14

15

2

3

0

1

MXDI

(From CPCI-6115-MCPTM or CPCI-6106)

Time Slot Signal Name

CTS3

DSR3

DCD3

CTS1

RI3

CTS4

DSR4

DCD4

CTS2

RI4

RI1

DSR1

DCD1

RI2

DSR2

DCD2

128



MXSYNC# is clocked out using the falling edge of MXCLK and MDXO is clocked out with the rising edge of the MXCLK. MXDI is sampled at the rising edge of MXCLK (the CPCI-6115-

MCPTM synchronizes MXDI with MXCLK’s rising edge). The timing relationships among

MXCLK, MXSYNC#, MXDO, and MXDI are illustrated by the following figure:

Figure 5-6 P2MX Signal Timings

Serial Port Signal Descriptions

CTSn

DCDn clear to send data carrier detected

DSRn

DTRn

RIn

RTSn data set ready data terminal ready ring indicator request to send


129


5.7.6.2

Serial Port Redirection

It is expected that many PMCs will include a serial debug port in addition to their other I/O. The

CPCI-6115-MCPTM allows the COM1 and COM2 connectors to be redirected by means of 16:8 multiplexers to the PMC I/O modules so the PMC I/O module faceplate area does not have to be used to provide a connector to access the debug port. A jumper on the CPCI-6115-MCPTM switches the COM1 connector between either the serial port originating on CPCI-6200 SBC or the serial port originating on PMC I/O module 1 (if any). Likewise for COM2 and PMC I/O module 2.

The redirected serial channels are routed to pins reserved on the host I/O connector. A serial port (if any) originating on the PMC located on the CPCI-6200 SBC is connected to the PMC I/O module through the standard 64 bits of PMC user I/O. The PMC I/O module must then loop the serial port back out on its host I/O connector.

This approach allows the serial debug port to be assigned to any of the 64 PMC user I/O lines.

The mating PMC I/O module maps those lines onto the CPCI-6115-MCPTM serial channels. It is expected that future transition modules will reserve the same pins on the host I/O connector for this serial port function.

5.7.6.3

Asynchronous Serial Port Diagrams

The two asynchronous port configuration diagrams are shown on the following pages. The asynchronous serial ports are configured through jumper settings. Serial ports 1 and 2 are routed through connector J5.

Synchronous Port

Port 1

Port 2

Board Connector

J5

J5

Jumper Header

J6

J11

The next two figures illustrate the CPCI-6200 baseboard and CPCI-6115-MCPTM with the interconnections and jumper settings for DCE/DTE configuration on each serial port.

5.7.6.4

Port Configuration Diagrams

The following interface configuration diagrams describe the interface between the CPCI-6200

SBC and the CPCI-6115-MCPTM.

130



Figure 5-7 CPCI-6115-MCPTM Serial Ports 1 and 2


131


5.7.7

PMC I/O Module

The CPCI-6115-MCPTM provides additional I/O capabilities for the CPCI-6200 SBC. There are three distinct groups of I/O passed from the CPCI-6200 SBC to the CPCI-6115-MCPTM through the CompactPCI J3 and J5 connectors; MCxx905 SBC host I/O, PMC1 I/O and PMC2 I/O. CPCI-

6200 SBC host I/O functions are designed into the CPCI-6200 SBC and their presence or absence is determined when that board is built. This I/O cannot be configured at the system integration level. PMC I/O depends entirely upon which, if any, PMC is installed in one or both of the CPCI-6200 SBC PMC sites. To accommodate the pluggable nature of a PMC, a custom form factor pluggable I/O module is presented here. A physical representation of the CPCI-

6115-MCPTM and I/O modules is shown below.

132



Figure 5-8 PMC I/O Module Physical Representation (MXP Version)


133


5.7.8

PMC I/O Module Form Factor

The PMC I/O module form factor is identical to the single-wide PMC form factor with the following differences:



Shorter by 80mm





Deletes the +5 V and +3.3 V keys

Pn1 and Pn3 are deleted

The 80mm is “cut out of the middle” of the PMC I/O module. This means that features in the front half of the module keep their positioning relative to the front edge of the board while features in the back half of the board keep their positioning relative to the back edge of the board.

5.7.9

PMC I/O Connector

The mapping used by the CPCI-6200 SBC of the PMC I/O connectors onto the CompactPCI user

I/O connectors is reversed by the CPCI-6115-MCPTM. This allows the designer of a PMC to create a PMC I/O module without knowledge of how the CPCI-6200 SBC maps signals through the backplane. There is nothing to tie the PMC I/O module to the CPCI-6200 SBC platform and in this sense the module is “universal”.

5.7.10 Host I/O Connector

The second connector on the PMC I/O module is used to provide power and ground to the module. In addition, the remaining pins may be used for host I/O signals. Any host I/O functionality for which there is no space available, or which the cost of does not justify its presence on the standard board, may be implemented in a “host I/O module”. This functionality is special to the host (in this case the CPCI-6200 SBC) and so the host I/O module is not a “universal” module. However, if the host I/O connector pinout is reused on future transition modules, the host I/O module may be reused.

If possible, optional host I/O routed to the host I/O connector will be terminated in such a fashion that the host does not incorrectly determine that a device is connected to that I/O when no module is present. This termination must not interfere with normal operation of the

I/O when a module is present.

134



5.7.11 PMC I/O Module Presence Detection and Identification

Presence detection and identification of PMC I/O modules is currently an open issue. It is anticipated that PMCs and PMC I/O modules will be designed as pairs. Any and all of the 64 bits of PMC user I/O are available to the designers to use as they wish to detect and identify an installed PMC I/O module. No standard exists, or is likely to exist, so hopefully the method chosen will be sufficiently robust to prevent accidental misidentification of modules.

Host I/O modules also need to be detected and identified. To this end the I2C bus provided from the CPCI-6200 SBC is connected to both PMC I/O module sites. The addresses and content of the I2C devices to reside on the Host I/O module remain an open issue.

5.8

Installing the PIM

Procedure

If a PIM has already been installed on the CPCI-6115-MCPTM, or you are installing a transition module as it has been shipped from the factory, disregard this section, and proceed to the

main installation section titled

Installing the Transition Module

on page 138 . For PIM installation,

perform the following steps:

1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2. Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system.

3. Remove chassis or system cover(s) as necessary for access to the CompactPCI.

Product Damage

Inserting or removing modules in a non-hot-swap chassis with the power applied may result in damage to the module components. The CPCI-6115-MCPTM is not a hot-swap board, but it may be installed in a hot-swap chassis with power applied.

Remove the corresponding CPCI-6200 before the CPCI-6115-MCPTM is installed.


135



Dangerous voltages, capable of causing death, are present in this equipment.

Use extreme caution when handling, testing and adjusting.

4. Carefully remove the transition module from its CompactPCI card slot and lay it flat on a stable surface.

5. Remove the PIM filler from the front panel of the transition module.

136



6. Slide the face plate (front bezel) of the PIM module into the front panel opening from behind and pace the PIM module on top of the transition module, aligned with the appropriate two PIM connectors (P0 and P4). The two connectors on the underside of the PIM module should then connect smoothly with the corresponding connectors on the transition module (J10 and J14). Refer to the following figure for proper screw/board alignment.

Figure 5-9 Installing the PIM

7. Insert the four short Phillips screws, provided with the PIM, through the holes on the bottom side of the transition module into the PIM front bezel and rear standoffs. Tighten the screws.

8. With the CPCI-6115-MCPTM in the correct vertical position that matches the pin positioning of the backplane, carefully slide the transition module into the appropriate slot and seat tightly into the backplane.


137


9. Secure in place with the screws provided, making good contact with the transverse mounting rails to minimize RF emissions.

10.Replace the chassis or system cover(s), reconnect the system to the AC or DC power source, and turn the equipment power on, or if hot-swapping, you may now install the CPCI-6200.

5.9

Installing the Transition Module

After all peripheral modules have been installed and all of the appropriate jumpers have been set, you are ready to install the transition module in its chassis slot. At this point, follow the steps below:

Procedure

To Install the rear transition module, follow these steps:

1. Attach an ESD strap to your wrist. Attach the other end of the strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2. Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove the chassis or system cover(s) as necessary for access to the chassis backplane.


Dangerous voltages, capable of causing death, are present in this equipment.

Use extreme caution when handling, testing and adjusting.

138



Damage of Circuits


Before touching the product or electronic components, make sure that your are working in an ESD-safe environment.

3. With the CPCI-6115-MCPTM in the correct vertical position that matches the pin positioning of the backplane, carefully slide the transition module into the appropriate slot and seat tightly into the backplane. Refer to

Figure 5-10 on page

141

for the correct board/connector orientation.

4. Secure in place with the screws provided, making good contact with the transverse mounting rails to minimize RF emissions.

5. Replace the chassis or system cover(s), reconnect the system to the AC or DC power source and turn the equipment power on, or if hot-swapping, you may now install the CPCI-6106.


139


5.10 Removing the Transition Module in a Hot-Swap

Chassis

Although the CPCI-6200 SBC can be removed and inserted while power is applied in a hot-swap capable backplane, the CPCI-6115-MCPTMs are not hot-swap capable. Inserting or removing the transition module while the CPU board is active may affect the normal operation of the

CPU board. Even in a hot-swap capable chassis, the CPU back end power should be switched off

(or the chassis power shut down) prior to inserting or removing its corresponding transition module.

140



Figure 5-10 CPCI-6115-MCPTM Mating Configuration


141


142


Chapter 6

MOTLoad Firmware

6.1

Overview

This chapter describes the basic features of the MOTLoad firmware product. It is designed by

Artesyn as the next generation initialization, debugger and diagnostic tool for highperformance embedded board products.

In addition to an overview of the product, this chapter includes a list of standard MOTLoad commands and the default Compact PCI settings that you can change, as allowed by the firmware.

6.2

MOTLoad Description

The MOTLoad firmware package serves as a board power-up and initialization package, as well as a vehicle from which user applications can be booted. A secondary function of the MOTLoad firmware is to serve, in some respects, as a test suite that provides individual tests for certain devices.

MOTLoad is controlled through an easy-to-use, UNIX-like, command line interface. The

MOTLoad software package is similar to many end-user applications designed for the embedded market, such as the real time operating systems currently available.

For more information, see the MOTLoad Firmware Package User’s Manual listed in

Related

Documentation

on page 229 .

6.3

MOTLoad Implementation and Memory

Requirements

The implementation of the CPCI-6200 and its memory requirements are product specific. The

CPCI-6200 is offered with a wide range of memory (for example, DRAM, flash). Typically, the smallest amount of onboard DRAM that an Artesyn SBC has is 32 MB. Each supported Artesyn product line has its own unique CPCI-6200 binary image(s). Currently the largest CPCI-6200 compressed image is less than 1 MB in size.


143


6.4

MOTLoad Commands

CPCI-6200 supports two types of commands (applications): utilities and tests. Both types of commands are invoked from the CPCI-6200 command line in a similar fashion. Beyond that,

CPCI-6200 utilities and CPCI-6200 tests are distinctly different.

6.5

MOTLoad Utility Applications

The definition of a MOTLoad utility application is very broad. Simply stated, it is considered a

MOTLoad command if it is not a MOTLoad test. Typically, MOTLoad utility applications are applications that aid the user in some way (that is, they do something useful). From the perspective of MOTLoad, examples of utility applications are: configuration, data/status displays, data manipulation, help routines, data/status monitors, etc.

Operationally, MOTLoad utility applications differ from MOTLoad test applications in several ways:





Only one utility application operates at any given time (that is, multiple utility applications cannot be executing concurrently).

Utility applications may interact with the user. Most test applications do not.

6.6

MOTLoad Tests

A MOTLoad test application determines whether or not the hardware meets a given standard.

Test applications are validation tests. Validation is conformance to a specification. Most

MOTLoad tests are designed to directly validate the functionality of a specific single board computer (SBC) subsystem or component. These tests validate the operation of such SBC modules as: dynamic memory, external cache, NVRAM, real time clock, etc.

All MOTLoad tests are designed to validate functionality with minimal user interaction. Once launched, most MOTLoad tests operate automatically without any user interaction. There are a few tests where the functionality being validated requires user interaction (that is, switch tests, interactive plug-in hardware modules, etc.). Most MOTLoad test results (errordata/status-data) are logged, not printed. All MOTLoad tests/commands have complete and separate descriptions. For more information on these tests/commands, see the MOTLoad

Firmware Package User’s Manual.

144



All devices that are available to MOTLoad for validation/verification testing are represented by a unique device path string. Most MOTLoad tests require the operator to specify a test device at the MOTLoad command line when invoking the test.

A listing of all device path strings can be displayed through the devShow command. If an SBC device does not have a device path string, it is not supported by MOTLoad and cannot be directly tested. There are a few exceptions to the device path string requirement, like testing

RAM, which is not considered a true device and can be directly tested without a device path string. Refer to the devShow command description page in the MOTLoad Firmware Package

User’s Manual.

Most MOTLoad tests can be organized to execute as a group of related tests (a test suite) through the use of the testSuite command. The expert operator can customize their testing by defining and creating a custom testSuite(s). The list of built-in and user-defined

MOTLoad testSuites, and their test contents, can be obtained by entering testSuite -

dtestSuite

at the MOTLoad prompt. All testSuites that are included as part of a product specific MOTLoad firmware package are product specific. For more information, refer to the command description page in the MOTLoad Firmware Package User’s Manual.

Test results and test status are obtained through the testStatus, errorDisplay and

taskActive

commands. For more information, refer to the appropriate command description page in the MOTLoad Firmware Package User’s Manual.

6.7

Using MOTLoad

Interaction with MOTLoad is performed via a command line interface through a serial port on the SBC, which is connected to an X-terminal or other terminal emulator (for example,

Window’s Hypercomm). The default MOTLoad serial port settings are: 9600 baud, 8 bits, no parity.

6.7.1

Command Line Interface

The MOTLoad command line interface is similar to a UNIX command line shell interface.

Commands are initiated by entering a valid MOTLoad command (a text string) at the MOTLoad command line prompt and pressing the carriage-return key to signify the end of input.

MOTLoad then performs the specified action. An example of a MOTLoad command line prompt is shown below. The MOTLoad prompt changes according to what product it is used on

(for example, HXEB100, CPCI6200, MVME5500).


145


146

Example:

CPCI6200>

If an invalid MOTLoad command is entered at the MOTLoad command line prompt, MOTLoad displays a message that the command was not found.

Example:

CPCI6200> mytest

"mytest" not found

CPCI6200>

If the user enters a partial MOTLoad command string that can be resolved to a unique valid

MOTLoad command and presses the carriage-return key, the command will be executed as if the entire command string had been entered. This feature is a user-input shortcut that minimizes the required amount of command line input. MOTLoad is an ever changing firmware package, so user-input shortcuts may change as command additions are made.

Example:

CPCI6200> version

Copyright(C)2008-2009,Emerson Network Power-Embedded Computing,Inc.

All Rights Reserved

Copyright Motorola Inc. 1999-2007, All Rights Reserved

MOTLoad RTOS Version 2.0, PAL Version 1.1 RM02

Fri Sep 11 09:20:17 MST 2009

Example:

CPCI6200> ver

Copyright(C)2008-2009,Emerson Network Power-Embedded Computing,Inc.

All Rights Reserved

Copyright Motorola Inc. 1999-2007, All Rights Reserved

MOTLoad RTOS Version 2.0, PAL Version 1.1 RM02

Fri Sep 11 09:20:17 MST 2009

If the partial command string cannot be resolved to a single unique command, MOTLoad will inform the user that the command was ambiguous.

Example:



CPCI6200> te

"te" ambiguous

CPCI6200>

6.7.2

Command Line Help

Each MOTLoad firmware package has an extensive, product-specific help facility that can be accessed through the help command. The user can enter help at the MOTLoad command line to display a complete listing of all available tests and utilities.

Example

CPCI6200>help

For help with a specific test or utility the user can enter the following at the MOTLoad prompt:

help <command_name>

The help command also supports a limited form of pattern matching. Refer to the help command page.

Example

CPCI6200>help testRam

Usage: testRam [-aPh] [-bPh] [-iPd] [-nPh] [-tPd] [-v]

Description: RAM Test [Directory]

Argument/Option Description

-a Ph: Address to Start (Default = Dynamic Allocation)

-b Ph: Block Size (Default = 16KB)

-i Pd: Iterations (Default = 1)

-n Ph: Number of Bytes (Default = 1MB)

-t Ph: Time Delay Between Blocks in OS Ticks (Default = 1)

-v O: Verbose Output

CPCI6200>

6.7.3

Command Line Rules

There are a few things to remember when entering a MOTLoad command:





Multiple commands are permitted on a single command line, provided they are separated by a single semicolon(";").

Spaces separate the various fields on the command line (command/arguments/options).


147










The argument/option identifier character is always preceded by a hyphen (“-”) character.

Options are identified by a single character.

Option arguments immediately follow (no spaces) the option.

All commands, command options, device tree strings, etc., are case sensitive.

Example:

CPCI6200> flashProgram -d/dev/flash0 -n00100000

For more information on MOTLoad operation and function, refer to the MOTLoad Firmware

Package User’s Manual.

6.8

MOTLoad Command List

The following table provides a list of all current MOTLoad commands. Products supported by

MOTLoad may or may not employ the full command set. Typing help at the MOTLoad command prompt displays all commands supported by MOTLoad for a given product.

Table 6-1 MOTLoad Commands

Command as bcb bch bcw bdTempShow bfb bfh bfw blkCp blkFmt blkRd blkShow blkVe blkWr bmb bmh bmw br

Description

One-Line Instruction Assembler

Block Compare Byte/Halfword/Word

Display Current Board Temperature

Block Fill Byte/Halfword/Word

Block Copy

Block Format

Block Read

Block Show Device Configuration Data

Block Verify

Block Write

Block Move Byte/Halfword/Word

Assign/Delete/Display User-Program Break-Points

148



Table 6-1 MOTLoad Commands (continued)

Command bsb bsh bsw cm csb

, csh

, csw bvb bvh bvw cdDir cdGet clear devShow diskBoot downLoad ds echo elfLoader errorDisplay eval execProgram fatDir fatGet fdShow flashProgram flashShow gd gevDelete

Description

Block Search Byte/Halfword/Word

Block Verify Byte/Halfword/Word

ISO9660 File System Directory Listing

ISO9660 File System File Load

Clear the Specified Status/History Table(s)

Turns on Concurrent Mode

Checksum Byte/Halfword/Word

Display (Show) Device/Node Table

Disk Boot (Direct-Access Mass-Storage Device)

Down Load S-Record from Host

One-Line Instruction Disassembler

Echo a Line of Text

ELF Object File Loader

Display the Contents of the Test Error Status Table

Evaluate Expression

Execute Program

FAT File System Directory Listing

FAT File System File Load

Display (Show) File Descriptor

Flash Memory Program

Display Flash Memory Device Configuration Data

Go Execute User-Program Direct (Ignore Break-Points)

Global Environment Variable Delete


149


150 gt hbd hbx help gevList gevShow gn go l2CacheShow l3CacheShow mdb mdh mdw memShow mmb mmh mmw mpuFork mpuShow mpuSwitch netBoot netShow netShut netStats noCm pciDataRd pciDataWr


Command gevDump gevEdit gevInit

Description

Global Environment Variable(s) Dump (NVRAM Header +

Data)

Global Environment Variable Edit

Global Environment Variable Area Initialize (NVRAM

Header)

Global Environment Variable Labels (Names) Listing

Global Environment Variable Show

Go Execute User-Program to Next Instruction

Go Execute User-Program

Go Execute User-Program to Temporary Break-Point

Display History Buffer

Execute History Buffer Entry

Display Command/Test Help Strings

Display state of L2 Cache and L2CR register contents

Display state of L3 Cache and L3CR register contents

Memory Display Bytes/Halfwords/Words

Display Memory Allocation

Memory Modify Bytes/Halfwords/Words

Execute program from idle processor

Display multi-processor control structure

Resets board switching master MPU

Network Boot (BOOT/TFTP)

Display Network Interface Configuration Data

Disable (Shutdown) Network Interface

Display Network Interface Statistics Data

Turns off Concurrent Mode

Read PCI Device Configuration Header Register

Write PCI Device Configuration Header Register




stl stop taskActive tc td testDisk testEnetPtP testNvramRd testNvramRdWr testRam testRamAddr testRamAlt testRamBitToggle testRamBounce

Command pciDump pciShow pciSpace ping portSet portShow rd reset rs set sromRead sromWrite sta

Description

Dump PCI Device Configuration Header Register

Display PCI Device Configuration Header Register

Display PCI Device Address Space Allocation

Ping Network Host

Port Set

Display Port Device Configuration Data

User Program Register Display

Reset System

User Program Register Set

Set Date and Time

SROM Read

SROM Write

Symbol Table Attach

Symbol Table Lookup

Stop Date and Time (Power-Save Mode)

Display the Contents of the Active Task Table

Trace (Single-Step) User Program

Trace (Single-Step) User Program to Address

Test Disk

Ethernet Point-to-Point

NVRAM Read

NVRAM Read/Write (Destructive)

RAM Test (Directory)

RAM Addressing

RAM Alternating

RAM Bit Toggle

RAM Bounce


151


152


Command testRamCodeCopy testRamEccMonitor testRamMarch testRamPatterns testRamPerm testRamQuick testRamRandom testRtcAlarm testRtcReset testRtcRollOver testRtcTick testSerialExtLoop testSeriallntLoop testStatus testSuite testSuiteMake testThermoOp testThermoQ testThermoRange testWatchdogTimer tftpGet tftpPut time transparentMode tsShow upLoad version

Description

RAM Code Copy and Execute

Monitor for ECC Errors

RAM March

RAM Patterns

RAM Permutations

RAM Quick

RAM Random Data Patterns

RTC Alarm

RTC Reset

RTC Rollover

RTC Tick

Serial External Loopback

Serial Internal Loopback

Display the Contents of the Test Status Table

Execute Test Suite

Make (Create) Test Suite

Thermometer Temperature Limit Operational Test

Thermometer Temperature Limit Quick Test

Test That Board Temperature Is Within Range

Tests the accuracy of the watchdog timer device.

TFTP Get

TFTP Put

Display Date and Time

Transparent Mode (Connect to Host)

Display Task Status

Up Load Binary-Data from Target

Display Version String(s)




Command vmeCfg vpdDisplay vpdEdit waitProbe

Description

Manages user specified VME configuration parameters

VPD Display

VPD Edit

Wait for I/O Probe to Complete

Note:

Due to the difference in endianness of the board, the sromWrite command automatically swaps bytes as these are written into memory. The sromRead command accesses the actual memory contents and does not swap bytes as it reads. Therefore, the memory that is read through sromRead will look different from the source used by sromWrite.

For example, if the data being written start with this sequence:

15 16 1E 00 10 B5 65 40 00 CB 06 04 40 01 06 09

Then, the data retrieved through the sromRead command will appear as:

16 15 00 1E B5 10 40 65 CB 00 04 06 01 40 09 06

This behavior is normal for these commands on the CPCI-6200.


153


154


Chapter 7

Control via IPMI

7.1

Standard IPMI Commands

The IPMC is fully compliant to the Intelligent Platform Management Interface v.1.5. This section provides information on which IPMI commands are supported.

7.1.1

Global IPMI Commands

The IPMC supports the following global IPMI commands.

Table 7-1 Supported Global IPMI Commands

Command

Get Device ID

Master Write-Read

Cold Reset

Get Selftest Results

GetDeviceGUID

NetFn (Request/Response) CMD Comments

0x06/0x07

0x06/0x07

0x06/0x07

0x01

0x02 -

-

0x52 Only for accessing private I

2

C buses.

0x06/0x07

0x06/0x07

0x04 -

0x08 -

7.1.2

Watchdog Commands

The watchdog commands are supported by boards providing a system interface and a watchdog type 2 sensor.

Table 7-2 Supported Watchdog Commands

Command

Reset Watchdog Timer

Set Watchdog Timer

Get Watchdog Timer

NetFn (Request/Response)

0x06/0x07

0x06/0x07

0x06/0x07

CMD

0x22

0x24

0x25


155


7.1.3

IPMI Messaging Commands

The IPMC supports the following IPMI messaging commands.

Table 7-3 Supported Watchdog Commands

Command

Set BMC Global Enables

Get BMC Global Enables

Clear Message Flags

Get Message Flags

Enable Message Channel Receive

Get Message

Send Message

Read Event Message Buffer

Get BT Interface Capabilities


0x06/0x07

0x06/0x07

0x06/0x07

0x06/0x07

0x06/0x07

0x06/0x07

0x06/0x07

0x06/0x07

0x06/0x07

7.1.4

SEL Device Commands

The IPMC supports the following SEL device commands.

Table 7-4 Supported SEL Device Commands

Command

Get SEL Info

Get SEL Allocation Info

Reserve SEL

Get SEL Entry

Add SEL Entry

Clear SEL

Get SEL Time

Set SEL Time


0x0A/0x0B

0x0A/0x0B

0x0A/0x0B

0x0A/0x0B

0x0A/0x0B

0x0A/0x0B

0x0A/0x0B

0x0A/0x0B

156

CMD

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

CMD

0x40

0x41

0x42

0x43

0x44

0x47

0x48

0x49



7.1.5

SDR Repository Commands

The IPMC supports the following SDR repository commands.

Table 7-5 Supported SDR Repository Commands

Command

Get SDR Repository Info

Get SDR Repository Allocation Info

Reserve SDR Repository

Get SDR

Partial Add SDR

Clear SDR Repository

Get SDR Repository Time

Set SDR Repository Time


0x0A/0x0B

0x0A/0x0B

0x0A/0x0B

0x0A/0x0B

0x0A/0x0B

0x0A/0x0B

0x0A/0x0B

0x0A/0x0B

CMD

0x20

0x21

0x22

0x23

0x25

0x27

0x28

0x29

7.1.6

FRU Inventory Commands

The IPMC supports the following FRU inventory commands.

Table 7-6 Supported FRU Inventory Commands

Command

Get FRU Inventory Area Info

Read FRU Data

Write FRU Data

NetFn

(Request/Response) CMD Comments

0x0A/0x0B 0x10 -

0x0A/0x0B

0x0A/0x0B

0x11 -

0x12 This command returns the error code 0x80 if you attempt to write to the common header, Product

Info Area, Board Info Area, Chassis

Info Area, Board Connectivity record, Board Address table,

Board Power Distribution Record of FRU ID 0.


157


7.1.7

Sensor Device Commands

The IPMC supports the following sensor device commands.

Table 7-7 Supported Sensor Device Commands

Command

Get Device SDR Info

NetFn

(Request/Response) CMD

0x04/0x05

Get Device SDR 0x04/0x05

Reserve Device SDR Repository 0x04/0x05

0x20 -

0x21

0x22

-

-

Comments

Get Sensor Reading Factors

Set Sensor Hysteresis

Get Sensor Hysteresis

Set Sensor Threshold

0x04/0x05

0x04/0x05

0x04/0x05

0x04/0x05

0x23

0x24

-

-

0x25 -

0x26 Most of the threshold-based sensors have fixed thresholds.

Before using this command, check whether threshold setting is supported by using the Get

Device SDR command.

0x27 Get Sensor Threshold

Set Sensor Event Enable

Get Sensor Event Enable

Rearm Sensor Events

Get Sensor Reading

Set Sensor Type

Get Sensor Type

0x04/0x05

0x04/0x05

0x04/0x05

0x04/0x05

0x04/0x05

0x28

0x29

0x2A -

0x2D -

-

-

Set Event Receiver

Get Event receiver

Platform Event

0x04/0x05

0x04/0x05

0x04/0x05

0x04/0x05

0x2E

0x2F -

0x00 -

0x01 -

0x02 -

158



7.1.8

Chassis Device Commands

The IPMC supports the following chassis device commands.

Table 7-8 Supported Chassis Device Commands

Command

Get Chassis Capabilities

Get Chassis Status

Chassis Control

Get System Restart Cause

Set System Boot Options

Get System Boot Options


0x00/0x01

0x00/0x01

0x00/0x01

0x00/0x01

0x00/0x01

0x00/0x01

CMD

0x00

0x01

0x02

0x07

0x08

0x09

7.2

PICMG 2.9 Commands

The IPMC supports the following CompactPCI commands as defined in the PICMG 2.9 specification.

Table 7-9 Supported PICMG 2.9 Commands

Command

Get PICMG Properties

Get Address Info

Get Shelf Address Info


0x2C/0x2D

0x2C/0x2D

0x2C/0x2D

CMD

0x00

0x01

0x02


159


7.3

Artesyn Specific Commands

The Artesyn IPMC supports several commands which are not defined in the IPMI or PICMG 2.9 specification but are introduced by Artesyn: Firmware upgrade and status change commands.







Before sending any of these commands, the shelf management software must check whether the receiving IPMI controller is an Artesyn IPMI controller, that means IPMC, by using the IPMI command 'Get Device ID'. Sending Artesyn specific commands to IPMI controllers which are not delivered by Artesyn will lead to no or undefined results.

Implementing any of the Artesyn specific IPMI commands means that the software is not portable to other IPMI controllers that do not use the Artesyn IPMC firmware.

Make sure to use these commands with care. For example, it would be possible to use the

BMC/PM Change Role command to set the IPMC to active, even though the system already has an active BMC. As a result, the two IPMCs set as active BMC might not work or even conflict with each other. If such a mistake happens, reset the IPMC and correct the software.

7.3.1

Firmware Upgrade Commands

Artesyn offers three commands to upgrade the IPMC firmware which can be used to write an upgrade function:



Start Firmware Upgrade





Continue Firmware Upgrade

Finish Firmware Upgrade

The firmware upgrade session has to start with the Start Firmware Upgrade command which makes the target IPMC enter the firmware upgrade mode. The firmware image is sent to the target IPMC in several parts with multiple Continue Firmware Upgrade commands. Each part can have the size of an IPMB message length. When the whole firmware image is on the target

IPMC, the process has to be finished with the Finish Firmware Upgrade command. During the firmware upgrade mode, the Artesyn IPMC may only execute the Continue Firmware Upgrade and Get Device ID commands.

160



The following table shows the firmware upgrade commands together with their network function and command code.

Table 7-10 Firmware Upgrade Commands

Command Name

Start Firmware Upgrade

Continue Firmware Upgrade

Finish Firmware Upgrade

NetFn (Request/Response) CMD Description

0x08/0x09 0x1B

See

Start Firmware Upgrade

on page 161

0x08/0x09

0x08/0x09

0x1C

See

Continue Firmware

Upgrade

on page 162

0x1E

See

Finish Firmware Upgrade

on page 162

7.3.1.1

Start Firmware Upgrade

The Start Firmware Upgrade command puts the target IPMC into firmware upgrade mode. The command must be sent twice. Only the Firmware Upgrade commands and the Get Device ID command are supported in firmware upgrade mode.

7.3.1.1.1 Request Data

No request data needs to be provided for this command.

7.3.1.1.2 Response Data

The following table lists the response data applicable to the Start Firmware Upgrade command.

Table 7-11 Response Data of Start Firmware Upgrade

Byte

1

Data Field

Completion Code

0x00: Command executed successfully and target IPMC entered firmware upgrade mode

0x01..0xFF: Error, that means IPMC cannot enter into firmware upgrade mode


161


7.3.1.2

Continue Firmware Upgrade

The Continue Firmware Upgrade command writes a part of the firmware image to the target

IPMC. It also checks file integrity and makes the target IPMC leave the firmware upgrade mode if an error occurs. If an error occurs, the whole firmware upgrade sequence must be repeated beginning from the Start Firmware Upgrade command and the whole firmware upgrade image must be retransmitted.


The following table lists the request data applicable to the Continue Firmware Upgrade command.

Table 7-12 Request Data of Continue Firmware Upgrade

Byte

1..23

Data Field

Firmware content to be sent to the target IPMC.

The firmware image is a Motorola SREC file.

The whole message length is defined by the maximum IPMB message length.


The following table lists the response data of the Continue Firmware Upgrade command.

Table 7-13 Response Data of Continue Firmware Upgrade

Byte

1

Data Field

Completion Code

0x00: Command executed successfully

0x1..0xFF: Error, that means the IPMC left the firmware upgrade mode

7.3.1.3

Finish Firmware Upgrade

The Finish Firmware Upgrade command makes the target IPMC leave the firmware upgrade mode.

162




The following table lists the request data applicable to the Finish Firmware Upgrade command.

Table 7-14 Request Data of Finish Firmware Upgrade

Byte

1..23

Data Field

None


The following table lists the response data applicable to the Finish Firmware Upgrade command.

Table 7-15 Response Data of Finish Firmware Upgrade

Byte

1

Data Field

Completion Code

0: Command executed successfully

0x01..0xFF: Error

7.3.2

OEM Commands

The following table shows the OEM commands together with their network function and command code.

Table 7-16 OEM Commands

Command Name

BMC/PM Change Role

NetFn (Request/Response) CMD Description

0x30 0x03 See

BMC/PM Change Role

page 164 on

Get Geographical Address 0x30 0x04 See

Get Geographical Address

on page 164


163


7.3.2.1

BMC/PM Change Role

The BMC/PM Change Role command switches between the role of a BMC/PM. As a result its I2C addresses on IPMB0 and IPMB1 are configured to 0x20. Any message addressed to the system management software are passed to the host interface. The system management software must ensure that only one BMC is in the system. SDR will be updated to reflect I2C address changes.

The role of BMC/PM can also be defined via the onboard DIP switches. For a description refer to the Configuring the Board section.


The following table lists the request data applicable to the BMC/PM Change Role command.

Table 7-17 Request Data of BMC/PM Change Role

Byte

1

Data Field

Role:

0: BMC

1: reserved

2: PM


The following table lists the response data applicable to the BMC/PM Change Role command.

Table 7-18 Response Data of BMC/PM Change Role

Byte

1

Data Field

Completion code (IPMI)

7.3.2.2

Get Geographical Address

This command is used to get the geographical address of the slot which contains the management controller.

164




The following table lists the request data applicable to the Get Geographical Address command.

Table 7-19 Request Data of Get Geographical Address

-

Byte

-

Data Field


The following table lists the response data applicable to the Get Geographical Address command.

Table 7-20 Response Data of Get Geographical Address

2

3

Byte

1

4

Data Field

Completion code (IPMI)

Geographical address

I2C address of the management controller on the IPMB(s) bus(ses) in its current role

I2C address of the management controller on the IPMB(s) bus(ses) in PM role

If the management controller acts as PM, byte 3 and 4 are equal. If the management controller acts as BMC, byte 3 is 0x20 and byte 4 is the I2C address it will have if acting as PM. This last fixed information is needed by system management software to identify the management controller.


165


7.4

FRU Information

The CPCI-6200 provides the following FRU information in FRU ID 0.

Table 7-21 FRU Information CPCI-6200

Area

Internal use area

Board info area

Description

Not used

Manufacturing date/time

Board manufacturer

Value

Product info area

Multi record area

Board product name

Board serial number

Board part number

Product manufacturer

Product name

Product serial number

Product part number

User Info Area

Custom usage

Access

According to Intel's Platform Management

FRU information Storage Definition v1.0

Artesyn Embedded Technologies,

Embedded Computing r r

CPCI-6200

Defined by Artesyn

Defined by Artesyn

Artesyn Embedded Technologies,

Embedded Computing

CPCI-6200

Defined by Artesyn

Defined by Artesyn

This section is not applicable to CPCI-6200.

-

Min. 256 Byte available r/w r r r r r r r

7.5

Sensor Description

The CPCI-6200 provides the following sensors:

Table 7-22 IPMI Sensors Overview

Sensor Name

Aggregate T

Sensor Type

Artesyn-specific Discrete

Digital

Sensor

Number

0x99

Detailed SDR Description

See


166



Sensor Name

Aggregate V

CPCI Signal

CPU Status

Critical IRQ

Ejector Switch

ADT7461Temp

Core Temp

SEL Fullness

Signal Status

VCC1_2

VCC1_5

VCC1_8

VCC3_3

VCC2_5

VCC5_0

VCC1_0

VPCore

Table 7-22 IPMI Sensors Overview (continued)

Sensor Type


Digital


Digital

Processor


Digital


Digital

Temperature

Temperature

OEM


Digital

Voltage

Voltage

Voltage

Voltage

Voltage

Voltage

Voltage

Voltage

Sensor

Number

0x98

0x83

0x87

0x82

0x80

0x09

0x0A

0x64

0x85

0x08

0x06

0x01

0x02

0x05

0x03

0x07

0x04

The following tables describe the IPMI sensors in detail.

Detailed SDR Description

See


See


See


See


See


See


See


See


See


See


See


See


See


See


See


See


See



167


The AggregateT sensor reads all on-board temperature sensors and indicates whether a threshold of any evaluated sensor is asserted or not. The following table shows the main sensor data record field values of the AggregateT sensor.

Table 7-23 Aggregate T Sensor

Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type

Assertion Event Mask(Byte 15)


Deassertion Event Mask(Byte 17)


Threshold Mask(Byte 19)


Base Unit

Rearm mode

Hysteresis Support

Threshold Access Support

Event Message Control

Reading Definition

0x00

0x3F

0x00

0x3F

0x00

0x00

0x01

0x00

Raw Value

Aggregate T

0x00

0x99

0x06

0xD2

0x6F

0x3F

0x00

0x00

-

-

-

-

Description

-

Artesyn-specific Discrete Digital

-

Discrete (sensor-specific)

-

-

-

-

-

(unspecified)

Auto

No Hysteresis or unspecified

-

No Tresholds

Per Threshold / Discrete State

168



The AggregateV sensor reads all on-board voltage sensors and indicates whether a threshold of any evaluated sensor is asserted or not. The following table shows the main sensor data record field values of the AggregateV sensor.

Table 7-24 Aggregate V Sensor

Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Rearm mode

Hysteresis Support



Reading Definition

0x00

0x3F

0x00

0x3F

0x00

0x00

0x01

0x00

Raw Value

Aggregate V

0x00

0x98

0x06

0xD2

0x6F

0x3F

0x00

0x00

-

-

-

-

Description

-


-


-

-

-

-

-

(unspecified)

Auto


-

No Tresholds


Table 7-25 CPCI Signal Sensor

Feature

Sensor Name

Sensor LUN

Sensor Number

Raw Value

CPCI Signal

0x00

0x83

-

-

-

Description


169


170

Table 7-25 CPCI Signal Sensor (continued)

Feature

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Rearm mode

Hysteresis Support



Reading Definition

0x03

0x00

0x03

0x00

0x00

0x01

0x00

0x00

0x00

-

Raw Value

0x07

0xD2

0x6F

0x03

0x00

Table 7-26 CPU Status Sensor

Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type



Assertion Events

Raw Value

CPU Status

0x00

0x87

0x03

0x07

0x6F

0x02

-

0x00

-

Description

-

-



-

-

-

-

(unspecified)

Auto


No Tresholds

-


-

-

-

-

-

Description

-

Processor

-




Table 7-26 CPU Status Sensor (continued)

-

Feature



-

Deassertion Events



Base Unit

Rearm mode

Hysteresis Support



Reading Definition

0xFF

0x07

0x00

0x01

0x00

0x00

0x00

-

Raw Value

Event Offset: 1

0x02

0x00

-

Event Offset: 1

Table 7-27 Critical IRQ Sensor

Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type






Raw Value

Critical IRQ

0x00

0x82

0x07

0xD2

0x6F

0x0B

0x00

0x0B

0x00

0x0F


Description

Thermal Trip

-

-

-

Thermal Trip

-

-

(unspecified)

Auto


No Tresholds


-

-

-

-

-

-

-

-

Description

-


-


171


172

Table 7-27 Critical IRQ Sensor (continued)

Feature


Base Unit

Rearm mode

Hysteresis Support



Reading Definition

Raw Value

0x00

0x00

0x01

0x00

0x00

0x00

-

Table 7-28 Ejector Switch Sensor

Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Rearm mode

Hysteresis Support



0x00

0x01

0x00

0x01

0x00

0x00

0x01

0x00

0x00

0x00

Raw Value

Ejector Switch

0x00

0x80

0x07

0xD2

0x6F

0x01

-

Description

(unspecified)

Auto


No Tresholds

-


-

-

-

Description

-


-


-

-

-

-

-

(unspecified)

Auto


No Tresholds




Table 7-28 Ejector Switch Sensor (continued)

Feature

Reading Definition -

Raw Value

Table 7-29 Max1617Temp Sensor

Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Nominal Reading

Upper non-recoverable threshold

Upper critical threshold

Upper non-critical threshold

Lower non-recoverable threshold

Lower critical threshold

Lower non-critical threshold

Rearm mode

Hysteresis Support


0xE4

0xDA

0x76

0x79

0x7B

0x01

0x03

0x03

0x7A

0x95

0x7A

0x3F

0x3F

0x01

0xAA

0xEE

Raw Value

ADT7461Temp

0x00

0x09

0x03

0x01

0x01

0x95


-

Description

-

-

-

-

deg. C

42

110

-

-

-

Description

-

Temperature

-

Threshold

100

90

-10

-7

-5

Auto

Readable and Setable


173


174

Table 7-29 Max1617Temp Sensor (continued)

Feature


Reading Definition

Raw Value

0x00

Analog reading byte

Table 7-30 CoreTemp Sensor

Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type

Assertion Event Mask (Byte 15)

Assertion Event Mask (Byte 16)

Deassertion Event Mask (Byte 17)

Deassertion Event Mask (Byte 18)

Threshold Mask (Byte 19)

Threshold Mask (Byte 20)

Base Unit

Normal Reading







Rearm mode

Hysteresis Support

0xEE

0xE4

0xDA

0x76

0x79

0x7B

0x01

0x03

0x95

0x7A

0x95

0x7A

0x3F

0x3F

0x01

0xAA

Raw Value

CoreTemp

0x00

0x0A

0x03

0x01

0x01

Description


Analog sensor reading

-

-

Description

-

-

-

Temperature

Threshold

-7

-5

90

-10 deg. C

42

110

100

Auto




Table 7-30 CoreTemp Sensor (continued)

Feature



Reading Definition

Raw Value

0x03

0x00

Analog reading byte

Table 7-31 SEL Fullness Sensor

Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Nominal Reading







Rearm mode

0x50

0x4B

0x00

0x00

0x00

0x01

0x7A

0x80

0x7A

0x38

0x38

0x00

0x00

0x5A

Raw Value

SEL Fullness

0x00

0x64

0x06

0xD0

0x01

0x80

Description


Per Threshold/Discrete State


-

-

-

Description

-

OEM

-

Threshold

-

-

-

-

-

(unspecified)

0

90

80

75

(unspecified)

(unspecified)

(unspecified)

Auto


175


176

Table 7-31 SEL Fullness Sensor (continued)

Feature

Hysteresis Support



Reading Definition

Raw Value

0x02

0x02

0x00

Analog reading byte

Table 7-32 Signal Status Sensor

Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Rearm mode

Hysteresis Support



Reading Definition

0x08

0x00

0x08

0x00

0x0F

0x00

0x00

0x01

Raw Value

Signal Status

0x00

0x85

0x07

0xD2

0x6F

0x00

0x00

0x00

-

Description





-

-

Description

-

-



-

-

-

-

-

-

(unspecified)

Auto


No Tresholds

-




Table 7-33 VCC1_2 Sensor

Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Nominal Reading







Rearm mode

Hysteresis Support



Reading Definition

0x7A

0x95

0x7A

0x3F

0x3F

0x04

0x7C

0x88

Raw Value

VCC1_2

0x00

0x08

0x07

0x02

0x01

0x95

0x85

0x82

0x70

0x73

0x76

0x01

0x02

0x02

0x00

Analog reading byte

-

Volt

1.2

1.32

-

-

-

-

-

-

-

Description

-

Voltage

-

Threshold

1.29

1.26

1.14

1.11

1.08

Auto






177


178


Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Nominal Reading







Rearm mode

Hysteresis Support



Reading Definition

0x7A

0x95

0x7A

0x3F

0x3F

0x04

0x9B

0xAA

Raw Value

VCC1_5

0x00

0x06

0x07

0x02

0x01

0x95

0xA6

0xA2

0x8C

0x8F

0x93

0x01

0x03

0x03

0x00

Analog reading byte

-

Volt

1.5

1.65

-

-

-

-

-

-

-

Description

-

Voltage

-

Threshold

1.61

1.58

1.35

1.4

1.42

Auto








Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Nominal Reading







Rearm mode

Hysteresis Support



Reading Definition

0x7A

0x95

0x7A

0x3F

0x3F

0x04

0xB8

0xCA

Raw Value

VCC1_8

0x00

0x01

0x07

0x02

0x01

0x95

0xC5

0xC1

0xA6

0xAA

0xAF

0x01

0x03

0x03

0x00

Analog reading byte

-

Volt

1.8

1.98

-

-

-

-

-

-

-

Description

-

Voltage

-

Threshold

1.93

1.89

1.62

1.67

1.71

Auto






179


180


Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Nominal Reading







Rearm mode

Hysteresis Support



Reading Definition

0x7A

0x95

0x7A

0x3F

0x3F

0x04

0xA4

0xB4

Raw Value

VCC3_3

0x00

0x02

0x07

0x02

0x01

0x95

0xB0

0xAC

0x94

0x98

0x9C

0x01

0x03

0x03

0x00

Analog reading byte

-

Volt

3.3

3.63

-

-

-

-

-

-

-

Description

-

Voltage

-

Threshold

3.54

3.46

2.97

3.06

3.14

Auto








Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Nominal Reading







Rearm mode

Hysteresis Support



Reading Definition

0x7A

0x95

0x7A

0x3F

0x3F

0x04

0xB8

0xCA

Raw Value

VCC2_5

0x00

0x05

0x07

0x02

0x01

0x95

0xC5

0xC1

0xA6

0xAA

0xAF

0x01

0x03

0x03

0x00

Analog reading byte

-

Volt

2.5

2.75

-

-

-

-

-

-

-

Description

-

Voltage

-

Threshold

2.68

2.62

2.25

2.31

2.38

Auto






181


182


Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Nominal Reading







Rearm mode

Hysteresis Support



Reading Definition

0x7A

0x95

0x7A

0x3F

0x3F

0x04

0xAC

0xBD

Raw Value

VCC5_0

0x00

0x03

0x07

0x02

0x01

0x95

0xB8

0xB4

0x9B

0x9F

0xA3

0x01

0x03

0x03

0x00

Analog reading byte

-

Volt

5.00

5.50

-

-

-

-

-

-

-

Description

-

Voltage

-

Threshold

5.35

5.23

4.50

4.62

4.74

Auto








Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Nominal Reading







Rearm mode

Hysteresis Support



Reading Definition

0x7A

0x95

0x7A

0x3F

0x3F

0x04

0x66

0x70

Raw Value

VCC1_0

0x00

0x07

0x07

0x02

0x01

0x95

0x6D

0x6B

0x5C

0x5E

0x61

0x01

0x02

0x02

0x00

Analog reading byte

-

Volt

1.0

1.10

-

-

-

-

-

-

-

Description

-

Voltage

-

Threshold

1.07

1.05

0.90

0.92

0.95

Auto






183


184

Table 7-40 VPCore Sensor

Feature

Sensor Name

Sensor LUN

Sensor Number

Entity ID

Sensor Type

Event/Reading Type







Base Unit

Nominal Reading







Rearm mode

Hysteresis Support



Reading Definition

0x7A

0x95

0x7A

0x3F

0x3F

0x04

0x71

0x9E

Raw Value

VPCore

0x00

0x04

0x03

0x02

0x01

0x95

0x92

0x87

0x44

0x4F

0x5A

0x01

0x07

0x07

0x00

Analog reading byte

-

Volt

1.10

1.54

-

-

-

-

-

-

-

Description

-

Voltage

-

Threshold

1.42

1.31

0.66

0.77

0.88

Auto






Chapter 8

Memory Maps and Addresses

8.1

Default Processor Memory Map

The following table describes a default memory map from the point of view of the processor after a processor reset. Note that the e500 core only provides one default TLB entry to access boot code and it allows for accesses within the highest 4 KB of memory. In order to access the full 8 MB of default boot space (and the 1 MB of CCSR space), additional TLB entries must be set up within the e500 core for mapping these regions. For more information, see to the MPC8572

Reference Manual.

Table 8-1 Default Processor Address Map

Processor Address

Start

0x0_0000_0000

0x0_FF70_0000

0x0_FFF8_0000

End

0x0_FF6F_FFFF

0x0_FF7F_FFFF

0x0_FFFF_FFFF

Size

4087 MB

1 MB

8 MB

Definition

Not mapped

MPC8572 CCSR Registers

Flash


185


8.2

CPCI-6200 Memory Map

The following diagram and the succeeding table detail the physical memory map implemented by the MotLoad firmware.

Figure 8-1 CPCI-6200 Memory Map Diagram

0x0_0000_0000

System Memory

(3.5 GB)

0x0_DFFF_FFFF

0x0_E000_0000

0x0_EFFF_FFFF

0x0_E000_0000

0x0_F07F_FFFF

0x0_F080_0000

0x0_F0BF_FFFF

0x0_F0C0_0000

0x0_F0FF_FFFF

0x0_F100_0000

0x0_F10F_FFFF

0x0_F110_0000

0x0_F1FF_FFFF

0x0_F200_0000

PCI Memory 0

(256 MB)

PCI I/O 0

(8 MB)

PCI Memory 1

(4 MB)

PCI I/O 1

(4 MB)

CPU Internal Register

(1 MB)

Reserved

(15 MB)

LBC

(224 MB)

0x0_FFFF_FFFF

0x0_F200_0000

0x0_F200_FFFF

0x0_F201_0000

0x0_F201_FFFF

0x0_F202_0000

0x0_F202_FFFF

0x0_F203_0000

0x0_F203_7FFF

0x0_F203_8000

0x0_F203_FFFF

0x0_F204_0000

0x0_F23F_FFFF

0x0_F240_0000

0x0_F247_FFFF

0x0_F248_0000

0x0_F7FF_FFFF

0x0_F800_0000

0x0_FFFF_FFFF

Board Registers

(64 KB) CS3

Dual UART

(64 KB) CS4

32-bit Timers

(64 KB) CS5

NAND Flash 1

(32 KB) CS1

NAND Flash 2

(32 KB) CS1

Reserved

(3.75 MB)

MRAM

(512 KB) CS2

Reserved

(91.5 MB)

Flash A

(128 MB) CS0

186

Table 8-2 CPCI-6200 Address Memory Map

Processor Address

Start

0x0_0000_0000

End top_dram - 1

Size dram_size (3.5 GB max)

0x0_E000_0000

0x0_F000_0000

0x0_F080_0000

0x0_EFF_FFFF

0x0_F07F_FFFF

0x0_F0BF_FFFF

256 MB

8 MB

4 MB

Definition

System Memory (DDR3

SO-DIMMs)

PCI 0 Memory Space

PCI 0 I/O Space

PCI 1 Memory Space



Table 8-2 CPCI-6200 Address Memory Map (continued)

Processor Address

0x0_F0C0_0000

0x0_F100_0000

0x0_F110_0000

0x0_F200_0000

0x0_F0FF_FFFF

0x0_F10F_FFFF

0x0_F1FF_FFFF

0x0_FFFF_FFFF

Size

8 MB

1 MB

15 MB

224 MB

8.3

Local Bus Controller Memory Map

Definition

PCI 1 I/O Space

MPC8572 CCSR

Reserved

Local Bus Controller

Table 8-3 LBC Memory Map and Chip Select Assignments

4

5

2

3

0

1

LBC Bank/Chip

Select Local Bus Function

Boot flash bank

NAND flash bank

Size

128 MB

64 KB

MRAM 512 KB

Control/Status Registers 64 KB

Dual UART

32-bit Timers

64 KB

64 KB

Data Bus

Width

32 bits

8 bits

16 bits

32 bits

8 bits

32 bits

Address Range

F800_0000 - FFFF_FFFF

F203_0000 - F203_FFFF

F240_0000 - F247_FFFF

F200_0000 - F200_FFFF

F201_0000 - F201_FFFF

F202_0000 - F202_FFFF


187


8.4

System I/O Memory Map

System resources, including system control and status registers, external timers, flash, and

DUART, are mapped to a 224 MB address range that is accessible from the CPCI-6200 local bus via the MPC8572 LBC. The memory map is defined in the following table including the LBC bank chip select used to decode the register.

Table 8-4 System I/O Memory Map

Address

F200 0000

3

F200 0001

3

F200 0002

3

F200 0003

3

F200 0004

3

F200 0005

3

F200 0006

3

F200 0007

1

F200 0008

3

F200 0009–F200 000F

1

F200 0010

3

F200 0011

3

F200 0012

3

F200 0013

3

F200 0014

3

F200 0015

3

F200 0016

3

F200 0017

3

F200 0018

3

F200 0019

3

F200 001A–F200 001F

1

Definition

System Status Register

System Control Register

FP LEDs Control & Status Register

NOR Flash Control/Status Register

Interrupt Register 1

Interrupt Register 2

Interrupt Mask Register

Reserved

Presence Detect Register

Reserved

Nand Flash Chip 1 Control Register

Nand Flash Chip 1 Select Register

Nand Flash Chip 1 Presence Register

Nand Flash Chip 1 Status Register

Nand Flash Chip 2 Control Register

Nand Flash Chip 2 Select Register

Nand Flash Chip 2 Presence Register

Nand Flash Chip 2 Status Register

CPCI Control & Status Register

Geographic Address Read Register

Reserved

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

LBC Bank/Chip

Select

3

188



Table 8-4 System I/O Memory Map (continued)

Address

F200 0020

3

F200 0021

1

F200 0022

1

F200 0023

1

F200 0024

3

F200 0025

3

F200 0026

3

F200 0028–F200 002F

1

F200 0030

3

F200 0031

1

F200 0032

1

F200 0033

1

F200 0034

3

F200 0038

3

F200 003C

3

F200 0040–F200 FFFF

1

F201 0000–F201 2FFF

1

F201 3000–F201 3FFF

F201 4000–F201 4FFF

F201 5000–F201 FFFF

1

F202 0000

2

F202 0010

2

F202 0014

2

F202 0018

2

Definition

Watchdog Timer Load

Reserved

Reserved

Reserved

Watchdog Timer Control

Watchdog Timer Resolution

Watchdog Timer Count (16 bits)

Reserved

PLD Revision

Reserved

Reserved

Reserved

PLD Date Code (32 bits)

Test Register 1 (32 bits)

Test Register 2 (32 bits)

Reserved

Reserved

COM 3 (DUART channel 1)

COM 4 (DUART channel 2)

Reserved

External PLD Tick Timer Prescaler

Register

External PLD Tick Timer 1 Control

Register

External PLD Tick Timer 1 Compare

Register

External PLD Tick Timer 1 Counter

Register

5

5

4

5

4

4

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

LBC Bank/Chip

Select

5


189


190

Table 8-4 System I/O Memory Map (continued)

Address

F202 001C

2

F202 0020

2

F202 0024

F202 0028

F202 002C

F202 0030

F202 0034

F202 0038

F202 003C

F202 0040

F202 0044

F202 0048

2

2

2

2

2

2

2

2

2

1

F202 004C–F202 FFFF

2

F203 0000

3

F203 0001–F203 7FFF

F203 8000

3

F203 8001–F203 FFFF

1. Reserved for future implementation.

Definition

Reserved


Register


Register


Register

Reserved


Register


Register


Register

Reserved


Register


Register


Register

Reserved

Nand Chip 1 Data Register

Reserved

Nand Chip 2 Data Register

Reserved

2. 32-bit write only

3. Byte read/write capable

5

5

5

1

1

1

1

5

5

5

5

5

5

5

5

5

5

LBC Bank/Chip

Select



8.4.1

System Status Register

This is a read-only register that provides general board status information.

Table 8-5 System Status Register, 0xF200_0000

3

2

5

4

1

0

Bit

7

6

Field

PWR12V_EN_STS

PWR_12P_STS

PWR_12N_STS

SW5

SAFE_START R

PEX_8624_ERROR R

BD_TYPE

R

R

R

Operation

R

R

X

X

X

X

10

Reset

X

X

Table 8-6 System Status Register Field Definition

PWR12V_EN_STS

PWR_12P_STS

PWR_12N_STS

SW5

12V Power Enable Status from Switch

1 12 V is enabled.

0 12 V is disabled.

+12V Power Status

1

0

+12 V is good.

+12 V is not good.

-12V Power Status

1 -12 V is good.

1

0

0 -12 V is not good.

Switch 5 Status

Switch 5 is in OFF position (reserved).

Switch 5 is in ON position (reserved).


191


Table 8-6 System Status Register Field Definition (continued)

SAFE_START

PEX_8624_ERROR

BD_TYPE

ENV Safe Start

1 Indicates that firmware should use the safe

ENV settings

0 Indicates the ENV settings programmed in

NVRAM should be used by the firmware

PEX8624 Fatal Error

1

0

Indicates that the Fatal Error signal from the

PEX8624 is active

Indicates no Fatal Error signal from the

PEX8624

Board Type. These bits indicate the board type.

00 VME SBC

01

10

11

PrPMC

CPCI

Reserved

8.4.2

System Control Register

This register provides general board control bits.

Table 8-7 System Control Register, 0xF200_0001

2

1

4

3

0

6

5

Bit

7

Field

BRD_RST

RSVD

RSVD

RSVD

EEPROM_WP

RSVD

Operation

R/W

R

R

R

R/W

R

0

1

0

0

0

Reset

000

192



Table 8-8 System Control Register Field Definition

BRD_RST

RSVD

EEPROM_WP

Board Reset. These bits are used to force a hard reset of the board

101 xxx

Hard reset is generated.

Does not generate hard reset for any other bit patterns

Reserved

EEPROM Write Protect

1 Disable writes to the onboard EEPROM devices

0 Enable writes to the onboard EEPROM devices

8.4.3

Front Panel LEDs Control and Status Register

This register controls the front panel LEDs. It may be read by the system software to determine the state of the onboard status indicator LEDs, or written to by system software to make the corresponding onboard LEDs light up.

Table 8-9 Front Panel LED Control/Status Register, 0xF200_0002

2

1

4

3

0

6

5

Bit

7

Field

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

USR1_LED

USR2_LED

R

R

R

R/W

R/W

R

R

Operation

R

0

0

0

0

1

0

0

Reset

0


193


Table 8-10 Front Panel LED Control/Status Register Field Definition

RSVD

USR1_LED

USR2_LED

1

0

Reserved

User Green LED

Turn on the green LED.

Turn off green LED.

User / Failure Indicating Yellow LED

1 Turn on the yellow LED

0 Turn off yellow LED. The board can also turn on the LED if a failure condition is detected.

8.4.4

NOR Flash Control and Status Register

This register provides software-controlled bank write protect and map select functions as well as boot block select, bank write protect, and activity status for the NOR flash.

Table 8-11 NOR Flash Control/Status Register, 0xF200_0003

3

2

5

4

1

0

Bit

7

6

Field

RSVD

RSVD

RSVD

MAP_SEL

F_WP_SW

F_WP_HW

FBT_BLK_SEL

FLASH_RDY

R

R

Operation

R

R

R

R/W

R/W

R

1

X

0

0

X

1

Reset

0

0

Table 8-12 NOR Flash Control/Status Register Field Definition

RSVD Reserved

194



Table 8-12 NOR Flash Control/Status Register Field Definition (continued)

MAP_SEL

F_WP_SW

F_WP_HW

FBT_BLK_SEL

FLASH_RDY

Memory Map Select

1 Flash memory boot block A is selected and mapped to the highest address. See

Figure 4-2 on page 88

.

0 Flash memory map is controlled by the Flash Boot Block

Select switch.

Software flash bank write protect. This bit provides softwarecontrolled protection against inadvertent writes to the flash memory devices.

1

0

Flash is write-protected.

Flash bank is not write-protected, if the HW writeprotect bit is not set. This bit is set during reset and must be cleared by the system software to enable writing of the flash devices.

Hardware flash bank write protect switch status reflects the current state of the FLASH BANK WP switch.

1 Flash is write-protected.

0

1

Flash is not write-protected.

Flash Boot Block Select. This reflects the current state of the

BOOT BLOCK B SELECT switch.

Boot block B is selected and mapped to the highest address. See

Figure 4-3 on page 89 .

0 Boot block A is selected and mapped to the highest address. See

Figure 4-2 on page 88 .

Flash Ready. This bit provides the current state of the flash devices’ Ready/Busy# pins.

1 FLASH is ready.

0 FLASH is not ready.


195


8.4.5

Interrupt Register 1

This register may be read by the system software to determine which of the Ethernet PHYs originated their combined (OR'd) interrupt.

Table 8-13 Interrupt Register 1, 0xF200_0004

2

1

4

3

0

6

5

Bit

7

Field

RSVD

RSVD

RSVD

RSVD

PHY 4

PHY 3

PHY 2

PHY 1

R

R

R

R

R

R

R

Operation

R

0

0

0

0

0

0

0

Reset

0

Table 8-14 Interrupt Register 1 Field Definition

RSVD

PHY 4

PHY 3

PHY 2

PHY 1

Reserved

TSEC4 Interrupt

1 TSEC4 interrupt is asserted.

0 TSEC4 interrupt is not asserted.

TSEC3 Interrupt


TSEC3 interrupt is not asserted.

1

0

TSEC2 Interrupt


0 TSEC2 interrupt is not asserted.

TSEC1 Interrupt

TSEC1 interrupt is asserted.

TSEC1 interrupt is not asserted.

196



8.4.6

Interrupt Register 2

The CPCI CPLD, IPMI Controller, RTC, temperature sensor and abort switch interrupts are OR'd together. This register may be read by the system software to determine which device originated the interrupt.

Table 8-15 Interrupt Register 2, 0xF200_0005

3

2

5

4

1

0

Bit

7

6

Field

RSVD

RSVD

RSVD

CPCI_PLD_INT

IPMI_INT

RTC_INT

TEMP_INT

ABORT

R

R

R

R

R

R

Operation

R

R

0

0

0

0

0

0

Reset

0

0

Table 8-16 Interrupt Register 2 Field Definition

RSVD

CPCI_PLD_INT

IPMI_INT

RTC_INT

1

0

1

0

Reserved

Interrupt from CPCI Control CPLD

CPCI CPLD interrupt is asserted.

CPCI CPLD interrupt is not asserted.

IPMI Controller Interrupt

1 IPMI interrupt is asserted.

0 IPMI interrupt is not asserted.

RTC Interrupt

RTC interrupt is asserted.

RTC interrupt is not asserted.


197


Table 8-16 Interrupt Register 2 Field Definition (continued)

TEMP_INT

ABORT

Interrupt fromTemperature Sensor

1 Temp sensor interrupt is asserted.

0 Temp sensor interrupt is not asserted.

Abort Status. This bit reflects the current state of the onboard abort signal. This is a debounced version of the abort switch and may be used to determine the state of the abort switch.

1

0

Abort push button switch is pressed for less than three seconds.

Abort push button switch is not pressed.

8.4.7

Interrupt Mask Register

This register is used to enable or disable interrupts from the CPCI CPLD, IPMI Controller, RTC,

TEMP sensor and Abort switch. This register can be read or written by the system software.

Table 8-17 Interrupt Mask Register, 0xF200_0006

2

1

4

3

0

6

5

Bit

7

Field

RSVD

RSVD

RSVD

CPCI_PLD_INT_MASK

IPMI_INT_MASK

RTC_INT_MASK

TEMP_INT_MASK

ABORT_MASK

R/W

R/W

R/W

R/W

R/W

R

R

Operation

R

1

1

1

1

1

0

0

Reset

0

Table 8-18 Interrupt Mask Register

RSVD Reserved

198



Table 8-18 Interrupt Mask Register (continued)

CPCI_PLD_INT_MASK

IPMI_INT_MASK

RTC_INT_MASK

TEMP_INT_MASK

ABORT_MASK

Interrupt Mask for CPCI Control CPLD

1 CPCI CPLD interrupt generation is disabled.

0 CPCI CPLD is allowed to generate interrupt.

IPMI Controller Interrupt Mask

1

0

IPMI interrupt generation is disabled.

IPMI is allowed to generate interrupt.

RTC Interrupt Mask

1 RTC interrupt generation is disabled.

0 RTC is allowed to generate interrupt.

Interrupt Mask for Temperature Sensor

1

0

Temperature interrupt generation is disabled.

Temperature sensor is allowed to generate interrupt.

Abort Mask

1 Abort interrupt generation is disabled from push button switch.

0 Abort interrupt generation is allowed from push button switch.

8.4.8

Presence Detect Register

This register may be read by the system software to determine the presence of optional devices.

Table 8-19 Presence Detect Register, 0xF200_0008

6

5

Bit

7

4

Field

RSVD

RSVD

ERDY2

ERDY1

R

R

Operation

R

R

0

0

Reset

0

0


199


200

Table 8-19 Presence Detect Register, 0xF200_0008 (continued)

2

1

0

Bit

3

Field

RTM_PRSNT

XEP

PMC2P

PMC1P

R

R

R

Operation

R

X

X

X

Reset

X

Table 8-20 Presence Detect Register Field Definition

RSVD

ERDY2

ERDY1

RTM_PRSNT

XEP

PMC2P

Reserved

EREADY2. Indicates the enumeration status of PrPMC module installed in PMC site 2

1 PrPMC module installed in PMC site 2 is ready for enumeration.

1

0 PrPMC module is not ready for enumeration

EREADY1. Indicates the enumeration status of PrPMC module installed in PMC site 1

1

0

PrPMC module installed in PMC site 1 is ready for enumeration.

1

PrPMC module is not ready for enumeration.

RTM Present Status

1 RTM is installed.

0 RTM is not installed.

PCI Express Expander Present Status

1

0

PCI Express Expander module is installed.

PCI Express Expander module is not installed.

PMC Module 2 Present

1 PMC module is installed at PMC site 2.

0 PMC module is not installed at PMC site 2.



Table 8-20 Presence Detect Register Field Definition (continued)

PMC1P PMC Module 1 Present

1 PMC module is installed at PMC site 1.

0 PMC module is not installed at PMC site 1.

1. If PrPMC module is not installed, this bit is always 1.

8.4.9

NAND Flash Chip 1 Control Register

Table 8-21 NAND Flash Chip 1 Control Register, 0xF200_0010

3

2

5

4

1

0

Bit

7

6

Field

CLE

ALE

WP

RSVD

RSVD

RSVD

RSVD

RSVD

R

R

Operation

R/W

R/W

R

R

R/W

R

0

0

1

0

0

0

Reset

0

0

Table 8-22 NAND Flash Chip 1 Control Register Field Definition

CLE

ALE

Command Latch Enable

1 CLE is asserted when the device is accessed.

0 CLE is not asserted when the device is accessed.

Address Latch Enable

1 ALE is asserted when the device is accessed.


201


Table 8-22 NAND Flash Chip 1 Control Register Field Definition (continued)

0 ALE is not asserted when the device is accessed.

WP Write Protect

1

0

WP is asserted when the device is accessed.

WP is not asserted when the device is accessed.

RSVD Reserved

8.4.10 NAND Flash Chip 1 Select Register

Table 8-23 NAND Flash Chip 1 Select Register, 0xF200_0011

3

2

5

4

1

0

Bit

7

6

Field

CE1

CE2

CE3

CE4

RSVD

RSVD

RSVD

RSVD

R

R

Operation

R/W

R/W

R

R

R/W

R/W

0

0

0

0

0

0

Reset

0

0

Table 8-24 NAND Flash Chip 1 Select Register Field Definition

CE1 Chip Enable 1

1 CE1 is asserted when the device is accessed.

0 CE1 is not asserted when the device is accessed.

202



Table 8-24 NAND Flash Chip 1 Select Register Field Definition (continued)

CE2

CE3

CE4

RSVD

Chip Enable 2



Chip Enable 3

1

0

CE3 is asserted when the device is accessed.

CE3 is not asserted when the device is accessed.

Chip Enable 1


0

Reserved


8.4.11 NAND Flash Chip 1 Presence Register

Table 8-25 NAND Flash Chip 1 Presence Register, 0xF200_0012

3

2

5

4

1

0

Bit

7

6

Field

C1P

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

R

R

R

R

R

R

Operation

R

R

0

0

0

0

0

0

Reset

X

0


203


Table 8-26 NAND Flash Chip 1 Presence Register Field Definition

C1P

RSVD

Chip 1 Present

1 Chip 1 is installed on the board.

0

Reserved

Chip 1 is not installed on the board.

8.4.12 NAND Flash Chip 1 Status Register

Table 8-27 NAND Flash Chip 1 Status Register, 0xF200_0013

3

2

5

4

1

0

Bit

7

6

Field

RB1

RB2

RB3

RB4

RSVD

RSVD

RSVD

RSVD

R

R

R

R

R

R

Operation

R

R

0

0

1

1

0

0

Reset

1

1

Table 8-28 NAND Flash Chip 1 Status Register Field Definition

RB1

RB2

1

0

Ready/Busy 1

1 Device 1 is ready.

0 Device 1 is busy.

Ready/Busy 2

Device 2 is ready.

Device 2 is busy.

204



Table 8-28 NAND Flash Chip 1 Status Register Field Definition (continued)

RB3

RB4

RSVD

Ready/Busy 3


0 Device 3 is busy.

Ready/Busy 4

1

0

Reserved

Device 4 is ready.

Device 4 is busy.

8.4.13 NAND Flash Chip 2 Control Register

Table 8-29 NAND Flash Chip 2 Control Register, 0xF200_0014

2

1

4

3

0

6

5

Bit

7

Field

CLE

ALE

WP

RSVD

RSVD

RSVD

RSVD

RSVD

R

R

R

R

R

Operation

R/W

R/W

R/W

0

0

0

0

0

0

1

Reset

0

Table 8-30 NAND Flash Chip 2 Control Register Field Definition

CLE Command Latch Enable

1

0

CLE is asserted when the device is accessed.

CLE is not asserted when the device is accessed.


205


Table 8-30 NAND Flash Chip 2 Control Register Field Definition (continued)

ALE

WP

RSVD

1

0

Address Latch Enable

1 ALE is asserted when the device is accessed.

0

Write Protect

ALE is not asserted when the device is accessed.

WP is asserted when the device is accessed.

WP is not asserted when the device is accessed.

Reserved

8.4.14 NAND Flash Chip 2 Select Register

Table 8-31 NAND Flash Chip 2 Select Register, 0xF200_0015

2

1

4

3

0

6

5

Bit

7

Field

CE1

CE2

CE3

CE4

RSVD

RSVD

RSVD

RSVD

R

R

R/W

R

R

Operation

R/W

R/W

R/W

0

0

0

0

0

0

0

Reset

0

Table 8-32 NAND Flash Chip 2 Select Register

CE1 Chip Enable 1

1

0



206



Table 8-32 NAND Flash Chip 2 Select Register (continued)

CE2

CE3

CE4

RSVD

Chip Enable 2



Chip Enable 3

1

0



Chip Enable 4


0

Reserved


8.4.15 NAND Flash Chip 2 Presence Register

Table 8-33 NAND Flash Chip 2 Presence Register, 0xF200_0016

3

2

5

4

1

0

Bit

7

6

Field

C2P

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

R

R

R

R

R

R

Operation

R

R

0

0

0

0

0

0

Reset

X

0

Table 8-34 NAND Flash Chip 2 Presence Register Field Definition

C2P Chip 2 Present


207


Table 8-34 NAND Flash Chip 2 Presence Register Field Definition (continued)

RSVD

1

0

Reserved

Chip 2 is installed on the board.

Chip 2 is not installed on the board.

8.4.16 NAND Flash Chip 2 Status Register

Table 8-35 NAND Flash Chip 2 Status Register, 0xF200_0017

2

1

4

3

0

6

5

Bit

7

Field

RB1

RB2

RB3

RB4

RSVD

RSVD

RSVD

RSVD

R

R

R

R

R

R

R

Operation

R

0

0

1

0

0

1

1

Reset

1

Table 8-36 NAND Flash Chip 2 Status Register Field Definition

RB1

RB2

Ready/Busy 1

1

0

Device 1 is ready.

Device 1 is busy.

Ready/Busy 2


0 Device 2 is busy.

208



Table 8-36 NAND Flash Chip 2 Status Register Field Definition (continued)

RB3

RB4

RSVD

1

0

Ready/Busy 3


0 Device 3 is busy.

Ready/Busy 4

Device 4 is ready.

Device 4 is busy.

Reserved

8.4.17 CPCI Control and Status Register

This register controls CPCI functions.

Table 8-37 CPCI Control/Status Register, 0xF200_0018

2

1

4

3

0

6

5

Bit

7

Field

HS_LED_MASK

BP_RST_MASK

HS_LED_ON

SA_MODE

SYS_EN_STS

RSVD

RSVD

RSVD

Operation

R/W

R/W

R/W

R

R

R

R

R

1. Reset value is 0 for system slot and 1 for peripheral slot.

0

0

0

X

0

Reset

0

X

1

0

Table 8-38 CPCI Control/Status Register Field Definition

HS_LED_MASK Hot Swap (Blue) LED Mask

1 Disable the illumination of Blue LED.

0 Enable the illumination of Blue LED.


209


Table 8-38 CPCI Control/Status Register Field Definition (continued)

BP_RST_MASK

HS_LED_ON

SA_MODE

SYS_EN_STS

1

CPCI Backplane Reset Mask

1 Disable backplane CPCI bus reset.

0 Enable backplane CPCI bus reset.

Hot Swap (Blue) LED ON

1

0

Turn on Blue LED.

Don't turn on Blue LED.

Stand alone mode

1 Board operates in stand alone mode e.g. operate in non-system slot and without system slot board.

1

0

0 Board operates in normal mode.

System Slot Operation Status

Board is operating in CPCI system slot.

Board is operating in CPCI peripheral slot.

1. The software cannot turn off the hot swap LED by writing this bit to 0 if the hardware has turned on the LED. To turn it off, software must write 1 to mask bit above.

8.4.18 Geographic Address Read Register

210

Table 8-39 Geographic Address Read Register, 0xF200_0019

4

3

2

6

5

Bit

7

Field

GA4

GA3

GA2

GA1

GA0

RSVD

R

R

R

R

R

Operation

R

X

X

0

X

X

Reset

X



Table 8-39 Geographic Address Read Register, 0xF200_0019 (continued)

Bit

1

0

Field

RSVD

RSVD

Operation

R

R

Reset

0

0

Table 8-40 Geographic Address Read Register Field Definition

GA[4:0]

RSVD

Geographic Address Bits from Backplane. The value will depend upon the chassis slot used for the board.

Reserved

8.4.19 Watchdog Timer Load Register

3

2

5

4

1

0

Bit

7

6

Table 8-41 Watchdog Timer Load Register, 0xF200_0020

Field

LOAD

Operation Reset

Write only, read returns zero 0x0

LOAD—Counter Load; When the pattern 0xDB is written, the watchdog counter is loaded with the count value.


211


8.4.20 Watchdog Timer Control Register

Table 8-42 Watchdog Timer Control Register, 0xF200_0024

3

2

5

4

1

0

Bit

7

6

Field

WDG_EN

SYS_RST

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

R

R

R

R

R

R

Operation

R/W

R/W

0

0

0

0

0

0

Reset

0

0

Table 8-43 Watchdog Timer Control Register Field Definition

WDG_EN

SYS_RST

RSVD

Watch Dog Timer Enable

1 Watchdog timer is enabled.

0 Watchdog timer is disabled.

System Reset

1

0

Reserved

Board and CPCI Backplane reset is generated when a timeout occurs.

Board level reset is generated when a time out occurs.

212



8.4.21 Watchdog Timer Resolution Register

3

2

5

4

1

0

Bit

7

6

Table 8-44 Watchdog Timer Resolution Register, 0xE200_0025

Field

RSVD

RSVD

RSVD

RSVD

WDG_RES

Operation

R

R

R

R

R/W

Reset

0

0

0

0

0x9

Table 8-45 Watchdog Timer Resolution Register

RSVD Reserved


213


Table 8-45 Watchdog Timer Resolution Register (continued)

WDG_RES

0111

1000

1001

1010

1011

1100

1101

1110

1111

Watchdog Timer Resolution

0000 2 μs

0001

0010

4 μs

8 μs

0011

0100

0101

0110

16 μs

32 μs

64 μs

128 μs

256 μs

512 μs

1 ms (default)

2 ms

4 ms

8 ms

16 ms

32 ms

64 ms

8.4.22 Watchdog Timer Count Register

Table 8-46 Watchdog Timer Counter Register, 0xF200_0026

Bit

15:0

Field

WDG_COUNT

Operation

R/W

1

Reset

XX

1. This register is not byte writable. It must be written half word (16 bits).

214



WDG_COUNT—Count; These bits define the watchdog timer count value. When the watchdog counter is enabled or there is a write to the load register, the watchdog counter is set to the count value. When enabled, the watchdog counter will decrement at a rate defined by the resolution register. The counter will continue to decrement until it reaches zero or the software writes to the load register. If the counter reaches zero, a system or board level reset is generated.

8.4.23 PLD Revision Register

This register may be read by the system software to determine the current revision of the timers/registers PLD.

Table 8-47 PLD Revision Register, 0xF200_0030

2

1

4

3

0

6

5

Bit

7

Field

MAJOR_REV

MINOR_REV

Operation

R

R

Reset

XX

XX

Table 8-48 PLD Revision Register Field Definition

MAJOR_REV

MINOR_REV

PLD's Major Revision Bits. It starts from 00.

PLD's Minor Revision Bits. It starts with 01.


215


8.4.24 PLD Date Code Register

This is a 32-bit register that contains the build date code of the timers/registers PLD.

Table 8-49 PLD Date Code Register, 0xF200_0034

Bit

31:24

23:16

15:8

7:0

Field

YEAR

MONTH

DATE

DAY REV

R

R

Operation

R

R

Reset

XX

XX

XX

XX

Table 8-50 PLD Date Code Register Field Definition

YEAR

MONTH

DATE

DAY REV

Four-digit year value of PLD's build date in decimal

Two-digit month value of PLD's build date in decimal

Two-digit date value of PLD's build date in decimal

Revision of the day

8.4.25 Test Register 1

This is a 32-bit general purpose read/write register that is used by software for PLD test or general status bit storage.

Table 8-51 Test Register 1, 0xF200_0038

Bit

31:0

Field

TEST_1

Operation

R/W

Reset

XX

TEST_1— General purpose 32-bit R/W field

216



8.4.26 Test Register 2

This is a second 32-bit test register that reads back the complement of the data in Test Register

1.

Table 8-52 Test Register 2, 0xF200_003C

Bit

31:0

Field

TEST_2

Operation

R/W

Reset

XX

TEST_2—A read from this address will return the complement of the data pattern in Test

Register 1. A write to this address will write the uncomplemented data to register TEST_1.

8.4.27 External Timer Registers

The CPCI-6200 provides a set of tick timer registers that is used to access four external timers implemented in the PLD. These registers are 32-bit registers and are not byte writable.

8.4.27.1 Prescaler Register

Table 8-53 Prescaler Register, 0xE202_0000

Bit

31:8

7:0

Field

PRESCALE_ADJUST

Operation

R/W

Reset

0xE7

The PRESCALE_ADJUST value is determined by the following formula:

Prescaler Adjust = 256 - (CLKIN/CLKOUT)

Where:





CLKIN is the input clock source in MHz.

CLKOUT is the desired output clock reference in MHz.


217


The prescaler provides the clock required by each of the four timers. The input clock to the prescaler is 25 MHz. The default value is set for $E7 which gives a 1 MHz reference clock for a

25 MHz input clock source.

8.4.27.2 Control Registers



Tick Timer 1 Control Register—0xF202_0010 (32 bits)










6

5

8

7

Bit

31:11

10

9

2

1

4

3

0

Table 8-54 Tick Timer Control Registers

Field

RSVD

INTS

CINT

EN_INT

OVF

RSVD

COVF

COC

ENC

R

R/W

R/W

R/W

Operation

R

R

R/W

R/W

R

0

0

0

0

0

0

0

0

Reset

0

Table 8-55 Tick Timer Control Field Definition

RSVD

INTS

CINT

Reserved

Interrupt Status

Clear Interrupt

218



Table 8-55 Tick Timer Control Field Definition (continued)

EN_INT

OVF

COVF

COC

ENC

Enable Interrupt

1 Interrupt is enabled.

0 Interrupt is disabled.

Overflow bits. These bits are the output of the overflow counter. The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter. The overflow counter can be cleared by writing a 1 to the COVF bit.

Clear overflow bits. The overflow counter is cleared when a 1 is written to this bit.

Clear counter on compare

1

0

Counter is reset to 0 when it compares with the compare register.

Counter is not reset when it compares with the compare register.

Enable counter

1 Enable the counter increments.

0 Disable the counter increments.

8.4.27.3 Compare Registers



Tick Timer 1 Compare Register—0xF202_0014 (32 bits)







Tick Timer 2 Compare Register —0xF202_0024 (32 bits)



Table 8-56 Tick Timer Compare Registers

Bit

31:0

Field

Tick Timer Compare Value

Operation

R/W

Reset

0


219


The Tick Timer Counter is compared to the Compare Register. When they are equal, the tick timer interrupt is asserted and the Overflow Counter is incremented. If the clear-on-compare mode is enabled, the counter is also cleared. For periodic interrupts, this equation should be used to calculate the compare register value for a specific period (T):

Compare register value = T (μs) x (1 / Reference clock frequency in MHz)

When programming the tick timer for periodic interrupts, the counter should be cleared to zero by software and then enabled. If the counter does not initially start at 0, the time to the first interrupt may be longer or shorter than expected. The rollover time for the counter is 71.6 minutes with the default 1 MHz reference clock.

8.4.27.4 Counter Registers



Tick Timer 1 Counter Register—0xF202_0018 (32 bits)










Table 8-57 Tick Timer Counter Register

Bit

31:0

Field

Tick Timer Counter Value

Operation

R/W

Reset

0

When enabled, the tick timer counter register increments with the reference clock value.

Software may read or write the counter at any time.

220



8.5

Interrupt Controller

The CPCI-6200 uses the MPC8572 integrated programmable interrupt controller (PIC) to manage locally generated interrupts.The following table shows the external interrupting devices and interrupt assignments along with corresponding edge/levels and polarities.

Table 8-58 Interrupt Assignments

7

8

9

10

11

5

6

3

4

1

2

Interrupt Number Edge/Level

0 Level

Level

Level

Level

Level

Level

Level

Level

Level

Level

Level

Level

Low

Low

Low

Low

Low

Low

Low

Low

Low

Polarity

Low

Low

Low

1. External timers are implemented in a PLD.

2. External UARTs are implemented using a DUART.

Interrupt Source

PCI Express Port 1

PCI Express Port 1

PCI Express Port 1

PCI Express Port 1

PCI Express Port 2

PCI Express Port 2

PCI Express Port 2

PCI Express Port 2

PCI Express Expander

RTC, TEMP, Abort, IPMI, CPCI PLD

PHY’s

UARTs, External Timer

12

Refer to the MPC8572 reference manual for additional details regarding the operation of the

MPC8572 PIC.


221


The following figure shows how PCI interrupts are mapped to processor interrupts.

Figure 8-2 PCI Interrupt Mapping to Processor

PMC2

INTA_N

INTB_N

Primary

INTC_N

INTD_N

INTA_N

INTB_N

Secondary

INTC_N

INTD_N

CPCI CPLD

INTA_N

INTB_N

CPCI

INTC_N

INTD_N

PMC1

INTA_N

INTB_N

Primary

INTC_N

INTD_N

INTA_N

INTB_N

Secondary

INTC_N

INTD_N

USB CONT.

INTA_N

INTB_N

INTC_N

Tsi384 (PCI 1)

Tsi384 (PCI 2)

Tsi384 (PCI 3)

Tsi381 (PCI 4)

PEX8624

IRQ0_N

IRQ1_N

IRQ2_N

IRQ3_N

8572

(Processor)

8.6

I

2

C Device Addresses

A two-wire serial interface for the CPCI-6200 is provided by an I

2

C compatible serial controller integrated into the MPC8572. The MPC8572 I

2

C controller is used by the system software to read the contents of the various I

2

C devices located on the CPCI-6200.

222



Table 8-59 I

2

C Bus Device Addressing

I

2

C Bus

Bus 4

Bus 3

I

2

C Bus Address

0xA0

0xA2

0xA4

0xA6

0xA8 / 0xAA

0xAC

0xAE

0xD0

0x4C or 0x98

0xA0

0xA2

0xA4

0xA6

0xA8

0xAA

0xAC

0xAE

Device Address

A2 A1 A0

(binary)

000

001

010

011

100

110

111

N/A

NA

000

001

010

011

100

101

110

111

Size

(bytes)

N/A

256 x 8

256 x 8

64K x 8

512 x 8

64K x 8

8K x 8

N/A

N/A

64K x 8

64K x 8

Function

Reserved

DDR3 memory bank 1 SPD

DDR3 memory bank 2 SPD

1

1

User configuration 1

RTM VPD (off-board configuration)

User configuration 2

VPD (on-board configuration)

M41T83 real-time clock

ADT7461 temperature sensor

User configuration

VPD (on-board configuration)

64K x 8 System Event Log (SEL)

Reserved

Reserved

Reserved

Reserved

Reserved

1. Each SPD defines the physical attributes of each bank of memory.

8.7

PCI/PCI-X Configuration

The following sections detail the PCI/PCI-X configuration of the onboard PCI devices.


223


8.7.1

PCI IDSEL and Interrupt Assignment

Each PCI device has an associated address line connected via a resistor to its IDSEL pin for

Configuration Space accesses. Refer to the MPC8572, Tsi384, Tsi381 and PEX8624 datasheets for details on generating configuration cycles on each of the PCI buses.

Table 8-60 IDSEL and Interrupt Mapping for PCI Devices

PCI Bus

Device

Number Field

PCI1 (Tsi384) 0b0_0000

0b0_0001

PCI2 (Tsi384) 0b0_0000

0b0_0001

PCI3 (Tsi384) 0b0_0010

PCI4 (Tsi381) 0b0_0010

20

21

22

23

AD Line for IDSEL PCI Device or Slot Device/Slot INT to MPC8572 IRQ

INTA# INTB# INTC# INTD#

18

18

PMC1 Primary

PMC1 Secondary

PMC2 Primary

PMC2 Secondary

CPCI CPLD uPD720101 USB

IRQ1

IRQ2

IRQ0

IRQ1

IRQ2

IRQ3

IRQ2

IRQ3

IRQ1

IRQ2

IRQ3

IRQ0

IRQ3

IRQ0

IRQ2

IRQ3

IRQ0

IRQ1

IRQ0

IRQ1

IRQ3

IRQ0

IRQ1

NC

8.7.2

PCI Vendor and Device IDs

The following table shows the Vendor ID and the Device ID for each of the planar PCI devices on the CPCI-6200.

Table 8-61 Planar PCI Device Identification

Function

System Controller

PCI-E Switch

PCI-E-to-PCI Bridge

PCI-E-to-PCI-X Bridge

PCI - PCI Bridge

USB Controller

Device

MPC8572

PEX8624

Tsi381

Tsi384

PCI6466

μPD720101

Vendor ID

0x1957

0x10B5

0x10E3

0x10E3

0x10B5

0x1033

Device ID

0x0041

0x8624

0x8111

0x8114

0x6540

0x0035

224



8.7.3

PCI Arbitration Assignments

The integrated PCI/X arbiters internal to the Tsi381, Tsi384, and PCI6466 bridges provide PCI arbitration for the CPCI-6200.

Table 8-62 PCI Arbitration Assignments

1

2

PCI Bus

1

2

3

4

CPCI Bus

Arbitration Assignment

Tsi384 REQ/GNT[0]

Tsi384 REQ/GNT[1]

Tsi384 REQ/GNT[0]

Tsi384 REQ/GNT[1]

Tsi384 REQ/GNT[0]

Tsi381 REQ/GNT[0]

PCI6466 Secondary Side

REQ/GNT[6:0]

1. When CPCI-6200 operates in system slot

PCI Master(s)

PMC site 1 primary master

PMC site 1 secondary master

PMC site 2 primary master

PMC site 2 secondary master

PCI6466 primary Side

USB Controller

Backplane CPCI Devices

1


225


226


Appendix A

A

Replacing the Battery

A.1

Battery Location

For information on the battery’s functional description, see

RTC Battery

on page 103

.

RTC Battery


227


Product Damage

Incorrect replacement of lithium batteries can result in a hazardous explosion.

When exchanging the on-board lithium battery, make sure that the new and the old battery are exactly the same battery models.

If the respective battery model is not available, contact your local Artesyn sales representative for the availability of alternative officially approved battery models.

PCB and Battery Holder Damage

Removing the battery with a screw driver may damage the PCB or the battery holder.

Do not use a screw driver to remove the battery from its holder.

Data Loss

Installing another battery type than the one that is mounted at product delivery may cause data loss since other battery types may be specified for other environments or may have a shorter lifetime.

Only use the same type of lithium battery as is already installed.

A.2


1. Remove the old battery.

2. Install the new battery with the plus sign (+) facing up.

3. Dispose of the old battery according to your country’s legislation and in an environmentally safe way.

228


Appendix B

B

Related Documentation

B.1

Artesyn Embedded Technologies - Embedded

Computing Documentation

The publications listed below are referenced in this manual. You can obtain electronic copies of

Artesyn Embedded Technologies - Embedded Computing publications by contacting your local Artesyn sales office. For released products, you can also visit our Web site for the latest copies of our product documentation.

1. Go to www.artesyn.com/computing .

2. Under SUPPORT, click TECHNICAL DOCUMENTATION.

3. Under FILTER OPTIONS, click the Document types drop-down list box to select the type of document you are looking for.

4. In the Search text box, type the product name and click GO.

Table B-1 Artesyn Embedded Technologies - Embedded Computing Publications

Document Title

CPCI-6200 Quick Start Guide

CPCI-6200 Safety Notes

MOTLoad Firmware Package User's Manual

Publication Number

6806800J85

6806800J86

6806800C24


229


B.2

Manufacturer’s Publications

For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals. A source for the listed document is provided. Please note that, while these sources have been verified, the information is subject to change without notice.

Table B-2 Manufacturers’ Publications

Company

Advanced Micro

Devices http://www.amd.co

m

Analog Devices, Inc.

http://www.analog.c

om

Atmel Corporation http://www.atmel.co

m/

2-Wire Serial EEPROM 32K (4096 x 8), 64K (8192 x 8) AT24C32C, AT24C64C,

5174B-SEEPR-12/06 http://www.atmel.com/dyn/resources/prod_documents/doc5174.pdf

2-Wire Serial EEPROM 512K (65,536 x 8), Rev. 1116K-SEEPR-1/04 http://www.atmel.com/dyn/resources/prod_documents/doc1116.pdf

BCM5482S 10/100/1000BASE-T Gigabit Ethernet Transceiver, 5482S-DS06-R

2/15/07

Broadcom http://www.broadco

m.com

Freescale http://www.freescal

e.com

Maxim/Dallas

Semiconductor http://www.maximic.com/

NEC Electronics

America http://www.necelam

.com

Document Title and Publication Number

S29GLxxxN MirrorBitTM Flash Family S29GL512N, S29GL256N, S29GL128N

512 Megabit, 256 Megabit, and 128 Megabit, 3.0 Volt-only Page Mode Flash

Memory featuring 110 nm MirrorBit process technology, 27631 Revision A

Amendment 4, May 13, 2004 http://www.amd.com/usen/assets/content_type/white_papers_and_tech_docs/27631a4.pdf

ADT7461 Temperature Monitor, ADT7461 Rev B

MPC8572 Integrated Host Processor Reference Manual

MPC8572 Integrated Processor Hardware Specifications

MPC8572 Errata

MAX3221E/MAX3223E/MAX3243E, 19-1283 Rev 5, 10/03

MAX811/MAX812 4-Pin μP Voltage Monitors with Manual Reset Input, 19-

0411 Rev 3, 3/99

μPD720101 USB2.0 HOST CONTROLLER, S16265EJ3V0DS00, April 2003 http://www.necelam.com/docs/files/S16265EJ3V0DS00.pdf

230



Table B-2 Manufacturers’ Publications (continued)

Company

PLX Technology http://www.plxtech.

com/

STMicroelectronics http://www.st.com/s tonline/

Texas Instruments http://www.ti.com

Tundra www.tundra.com


PCI6466 PC I-to-PCI Bus Bridge User Manual, Version 1.0, April, 2005

ExpressLane PEX 8624AA 5-Port/24-Lane Versatile PCI Express Switch Data

Book, Version 0.92

M41T83 Serial Real-Time Clock, Rev 6, November 2007

TL16C2550, Dual UART with 16-Byte FIFO's, October 2006

Tsi384 PCI Express-to-PCI/PCI-X Bridge Data Book, 80E1000_MA001_06,

October 2007

Tsi381 PCI Express-to-PCI Bridge Data Book, 80F1100_MA001_05, December

2007

B.3

Related Specifications

For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is provided. Please note that, while these sources have been verified, the information is subject to change without notice.

Table B-3 Related Specifications

Source

Institute of Electrical and

Electronics Engineers, Inc.

PCI Special Interest Group http://www.pcisig.com


IEEE Standard for a Common Mezzanine Card Family: CMC,

IEEE1386, October 25, 2001

IEEE Standard Physical and Environmental Layer for PCI

Mezzanine Cards: IEEE1386.1, October 25, 2001

PCI Local Bus Specification, PCI Rev 2.2 December 18, 1998

PCI-X Electrical and Mechanical Addendum to the PCI Local

Bus Specification, PCI-X EM 2.0a, August 22, 2003

PCI-X Protocol Addendum to the PCI Local Bus Specification,

PCI-X PT 2.0a, July 22, 2003


231


Table B-3 Related Specifications (continued)

Source

PCI Industrial Manufacturers

Group (PICMG) http://www.picmig.com


CPCI Hot Swap Specification, PICMG 2.1 R 2.0

CPCI Base Specification, PICMG 2.0 R 3.0

CPCI System Management Specification, PICMG 2.9 R 1.0

CPCI Packet Switching Backplane Specification, PICMG 2.16

R1.0

Universal Serial Bus Specification, Revision 2.0 April 27, 2000 Universal Serial Bus http://www.usb.org/developers

/docs/

VITA Standards Organization http://www.vita.com/

PPMC, ANSI/VITA 32-2003

PCI-X on PMC, ANSI/VITA 39-2003

232


Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc.

All other product or service names are the property of their respective owners.

©

2015 Artesyn Embedded Technologies, Inc.

No results