datasheet for SPC564B74L7 by STMicroelectronics

SPC564Bxx
SPC56ECxx
32-bit MCU family built on the Power Architecture® for automotive
body electronics applications
Target specification
Features
■
■
Communication interfaces
– Up to 6 FlexCAN with 64 buffers each
– Up to 10 LINFlex/UART channels
– Up to 8 buffered DSPI channels
– I2C interface
– One FleyRay (dual-ch.) with 128 buffers
– Fast Ethernet Controller
■
Cryptographic Services Engine (CSE)
– AES-128 en/decryption, CMAC auth.
– Secured device boot mode
■
32-ch. eDMA with multiple request sources
■
Clock generation
– 4 to 40 MHz main oscillator
– 16 MHz internal RC oscillator
– Software-controlled FMPLL
– 128 kHz internal RC oscillator
– 32 kHz auxiliary oscillator
– Clock Monitoring Unit (CMU)
■
Low power capabilities
– Ultra low power STANDBY
– CAN Sampler to store CAN ID in STBY
– Fast wake-up and exectute from RAM
e200z4d, 32-bit Power Architecture®
– up to 120 MHz and 200 MIPs operation
■
e200z0h, 32-bit Power Architecture
– up to 80 MHz and 75 MIPs operation
■
Memory
– Up to 3 MByte on-chip Flash with ECC
– Up to 256 KByte on-chip SRAM with ECC
– 64KByte on-chip Data Flash with ECC
– 16-entry memory protection unit (MPU)
– User selectable Memory BIST
■
Interrupts
– 255 interrupt sources with 16 priority levels
– Up to 54 ext. IRQ including 30 wake-up
■
GPIOs: from 147 (QFP176) to 199 (BGA256)
■
System timer units
– 8-ch. 32-bit periodic interrupt timer (PIT)
– 4-channel 32-bit system timer (STM)
– Safety System Watchdog Timer (SWT)
– Real-time clock timer (RTC/API)
■
eMIOS, 16-bit counter timed I/O units
– Up to 64 channels with PWM/MC/IC/OC
■
■
Two ADC (10-bit and 12-bit)
– Up to 62 channels extendable to 90 ch.
– Multiple Analog Watchdog
Exhaustive debugging capability
– Nexus 3+ interface on LBGA256 only
– Nexus 1 on all devices
■
■
Dedicated diagnostic features for lighting
– Advanced shiffted PWM generation
– ADC conversion synchronized on PWM
Voltage supply
– Single 5 V or 3.3 V supply
– On-chip Vreg with external ballast transitor
■
Operating temperature range -40 to 125 °C
Table 1.
Device summary
Package
LQFP176
LQFP208
BGA256
December 2011
Part number
1.5 MByte
2 MByte
3 MByte
SPC564B64L7
SPC56EC64L7
SPC564B64L8
SPC56EC64L8
SPC56EC64B3
SPC564B70L7
SPC56EC70L7
SPC564B70L8
SPC56EC70L8
SPC56EC70B3
SPC564B74L7
SPC56EC74L7
SPC564B74L8
SPC56EC74L8
SPC56EC74B3
Doc ID 17478 Rev 4
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
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www.st.com
1
Contents
SPC564Bxx - SPC56ECxx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1
Document Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 15
4
3.1
Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3
Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1
Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2
NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
NVUSRO [PAD3V5V(0)] field description . . . . . . . . . . . . . . . . . . . . . . . 49
4.2.2
NVUSRO [PAD3V5V(1)] field description . . . . . . . . . . . . . . . . . . . . . . . 49
4.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.5
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.6
4.5.1
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.5.2
Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.6.1
I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.6.2
I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.6.3
I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.6.4
Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.6.5
I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.7
RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.8
Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 64
4.9
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4.2.1
4.8.1
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 64
4.8.2
VDD_BV options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.8.3
Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 66
Low voltage domain power consumption . . . . . . . . . . . . . . . . . . . . . . . . . 67
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
4.10
4.11
Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.10.1
Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.10.2
Flash memory power supply DC characteristics . . . . . . . . . . . . . . . . . . 71
4.10.3
Flash memory start-up/switch-off timings . . . . . . . . . . . . . . . . . . . . . . . 72
Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . . 72
4.11.1
Designing hardened software to avoid noise problems . . . . . . . . . . . . . 72
4.11.2
Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.11.3
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 73
4.12
Fast external crystal oscillator (4–40 MHz) electrical characteristics . . . . 74
4.13
Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . 76
4.14
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.15
Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . 79
4.16
Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 80
4.17
ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.17.1
4.18
4.19
5
6
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Fast Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.18.1
MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK) . 92
4.18.2
MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK) . . . . 92
4.18.3
MII Async Inputs Signal Timing (CRS and COL) . . . . . . . . . . . . . . . . . . 93
4.18.4
MII Serial Management Channel Timing (MDIO and MDC) . . . . . . . . . 94
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.19.1
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.19.2
DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.19.3
Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.19.4
JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.1
ECOPACK®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.2.1
LQFP176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 107
5.2.2
LQFP208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 109
5.2.3
LBGA256 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 111
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Appendix A Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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Contents
SPC564Bxx - SPC56ECxx
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SPC564Bxx and SPC56ECxx family comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPC564Bxx and SPC56ECxx series block summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PAD3V5V(0) field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PAD3V5V(1) field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LBGA256 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 57
MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 58
FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 58
Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
I/O supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Low voltage power domain electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Code flash memory—Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Data flash memory—Program and erase specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Flash memory power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 71
Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Fast external crystal oscillator (4 to 40 MHz) electrical characteristics. . . . . . . . . . . . . . . . 75
Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 78
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 80
Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 81
ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
ADC conversion characteristics (10-bit ADC_0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Conversion characteristics (12-bit ADC_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
MII Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MII transmit signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
MII Async Inputs Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
MII serial management channel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Doc ID 17478 Rev 4
5/118
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
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SPC564Bxx - SPC56ECxx
On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LQFP208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
LBGA256 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
SPC564Bxx and SPC56ECxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
176-pin LQFP configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
208-pin LQFP configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
256-pin BGA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Low voltage monitor vs. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Fast external crystal oscillator (4 to 40 MHz) electrical characteristics. . . . . . . . . . . . . . . . 75
Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
lEquivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 78
ADC_0 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADC_1 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
MII receive signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MII transmit signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
MII async inputs timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
MII serial management channel timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
DSPI classic SPI timing–master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DSPI classic SPI timing–master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DSPI classic SPI timing–slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
DSPI classic SPI timing–slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
DSPI modified transfer format timing–master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 100
DSPI modified transfer format timing–master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 100
DSPI modified transfer format timing–slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 101
DSPI modified transfer format timing–slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 101
DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Timing diagram - JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
LQFP176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
LQFP208 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
LBGA256 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Doc ID 17478 Rev 4
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Introduction
SPC564Bxx - SPC56ECxx
1
Introduction
1.1
Document Overview
This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the SPC564Bxx
and SPC56ECxx device. To ensure a complete understanding of the device functionality,
refer also to the SPC564Bxx and SPC56ECxx Reference Manual.
1.2
Description
The SPC564Bxx and SPC56ECxx is a new family of next generation microcontrollers built
on the Power Architecture embedded category. This document describes the features of the
family and options available within the family members, and highlights important electrical
and physical characteristics of the device.
The SPC564Bxx and SPC56ECxx family expands the range of the CSPC560B
microcontroller family. It provides the scalability needed to implement platform approaches
and delivers the performance required by increasingly sophisticated software architectures.
The advanced and cost-efficient host processor core of the SPC564Bxx and SPC56ECxx
automotive controller family complies with the Power Architecture embedded category,
which is 100 percent user-mode compatible with the original Power Architecture user
instruction set architecture (UISA). It operates at speeds of up to 120 MHz and offers high
performance processing optimized for low power consumption. It also capitalizes on the
available development infrastructure of current Power Architecture devices and is supported
with software drivers, operating systems and configuration code to assist with users
implementations.
8/118
Doc ID 17478 Rev 4
SPC564Bxx and SPC56ECxx family comparison(1)
Feature
SPC564B64
LQFP
176
Package
CPU
Execution speed(2)
LQFP
208
SPC56EC64
LQFP
176
LQFP
208
SPC564B70
SPC56EC70
BGA LQFP1 LQFP
256
76
208
LQFP
208
BGA
256
LQFP
176
LQFP
208
SPC56EC74
LQFP
176
LQFP
208
BGA
256
e200z4d
e200z4d + e200z0h
e200z4d
e200z4d + e200z0h
e200z4d
e200z4d + e200z0h
Up to 120 MHz
(e200z4d)
Up to 120 MHz
(e200z4d)
Up to 80 MHz
(e200z0h)(3)
Up to 120 MHz
(e200z4d)
Up to 120 MHz
(e200z4d)
Up to 80 MHz
(e200z0h)(3)
Up to 120 MHz
(e200z4d)
Up to 120 MHz
(e200z4d)
Up to 80 MHz
(e200z0h)(3)
Code flash memory
1.5 MB
2 MB
Data flash memory
SRAM
LQFP
176
SPC564B74
SPC564Bxx - SPC56ECxx
Table 2.
3 MB
4 x16 KB
128 KB
192 KB
160 KB
256 KB
Doc ID 17478 Rev 4
MPU
192 KB
256 KB
16-entry
(4)
32 ch
eDMA
10-bit ADC
dedicated(5),
(6)
shared with
12-bit ADC(7)
27 ch
33 ch
27 ch
33 ch
27 ch
33 ch
27 ch
33 ch
27 ch
33 ch
27 ch
33 ch
19 ch
12-bit ADC
dedicated(8)
10 ch
shared with
10-bit ADC(7)
19 ch
CTU
64 ch
Total timer I/O(9) eMIOS
10
SPI (DSPI)
9/118
CAN (FlexCAN)
8
(10)
6
Introduction
SCI (LINFlexD)
64 ch, 16-bit
SPC564Bxx and SPC56ECxx family comparison(1) (continued)
Feature
Package
SPC564B64
LQFP
176
LQFP
208
SPC56EC64
LQFP
176
LQFP
208
SPC564B70
BGA LQFP1 LQFP
256
76
208
FlexRay
SPC56EC70
LQFP
176
LQFP
176
LQFP
208
LQFP
176
LQFP
208
BGA
256
Yes
STCU
Ethernet
No
Yes
No
Yes
I2C
No
Yes
1
32 kHz oscillator (SXOSC)
Debug
BGA
256
SPC56EC74
Yes
(11)
GPIO(12)
LQFP
208
SPC564B74
Introduction
10/118
Table 2.
Yes
147
177
147
JTAG
177
199
147
177
Nexus3
+
Doc ID 17478 Rev 4
Cryptographic Services
Engine (CSE)
147
JTAG
177
199
Nexus
3+
147
177
147
177
JTAG
199
Nexus
3+
Optional
1. Feature set dependent on selected peripheral multiplexing; table shows example.
2. Based on 125 °C ambient operating temperature and subject to full device characterisation.
3. The e200z0h can run at speeds up to 80 MHz. However, if system frequency is >80 MHz (e.g., e200z4d running at 120 MHz) the e200z0h needs to run at 1/2 system
frequency. There is a configurable e200z0 system clock divider for this purpose.
4. DMAMUX also included that allows for software selection of 32 out of a possible 57 sources.
5. Not shared with 12-bit ADC, but possibly shared with other alternate functions.
6. There are 23 dedicated ANS plus 4 dedicated ANX channels on LQPF176. For higher pin count packages, there are 29 dedicated ANS plus 4 dedicated ANX channels.
7. 16x precision channels (ANP) and 3x standard (ANS).
8. Not shared with 10-bit ADC, but possibly shared with other alternate functions.
10. CAN Sampler also included that allows ID of CAN message to be captured when in low power mode.
11. STCU controls MBIST activation and reporting.
12. Estimated I/O count for proposed packages based on multiplexing with peripherals.
SPC564Bxx - SPC56ECxx
9. As a minimum, all timer channels can function as PWM or Input Capture and Output Control. Refer to the eMIOS section of the device reference manual for information on
the channel configuration and functions.
SPC564Bxx - SPC56ECxx
2
Block diagram
Block diagram
Figure 1 shows the detailed block diagram of the SPC564Bxx and
SPC56ECxx.
Doc ID 17478 Rev 4
11/118
Block diagram
Figure 1.
SPC564Bxx - SPC56ECxx
SPC564Bxx and SPC56ECxx block diagram
FEC
Nexus Port
FlexRay
Nexus 3+
Nexus
Voltage
regulator
NMI0
e200z0h
NMI1
e200z4d
64-bit 8 x 5 crossbar switch
CSE
JTAG Port
Instructions
(Master)
Data
(Master)
Instructions
(Master)
Data
(Master)
MPU
JTAGC
SRAM
2 × 128 KB
Code Flash Data Flash
64 KB
2 × 1.5 MB
2 × SRAM
controller
Flash memory
controller
(Slave)
Nexus 3+
NMI0
(Slave)
(Slave)
Interrupt requests
from peripheral
blocks
NMI1
Clocks
DMAMUX
MPU
registers
INTC
eDMA
CMU
16 x
Semaphores
CAN
Sampler
( Master)
FMPLL
STCU
8×
RTC/API 4 × STM
SWT
ECSM
MC_RGM MC_CGM MC_ME MC_PCU
PIT RTI
BAM
SSCM
WKPU
Peripheral Bridge
Interrupt
Request
10 ch(1)
1 × 12-bit
ADC
SIUL
Reset Control
External
Interrupt
Request
27 ch or 33 ch(2)
1 × 10-bit
ADC
CTU
2 × 32 ch
eMIOS
10 ×
LINFlexD
8×
DSPI
I2C
6×
FlexCAN
IMUX
GPIO &
Pad Control
(3)
(3)
I/O
Legend:
ADC
BAM
CSE
CAN
CMU
CTU
DMAMUX
DSPI
eDMA
FlexCAN
FEC
eMIOS
ECSM
FMPLL
FlexRay
I2C
IMUX
INTC
Notes:
1) 10 dedicated channels plus up to 19 shared channels. See the device-comparison table.
2) Package dependent. 27 or 33 dedicated channels plus up to 19 shared channels. See the device-comparison table.
3) 16 x precision channels (ANP) are mapped on input only I/O cells.
Analog-to-Digital Converter
Boot Assist Module
Cryptographic Services Engine
Controller Area Network (FlexCAN)
Clock Monitor Unit
Cross Triggering Unit
DMA Channel Multiplexer
Deserial Serial Peripheral Interface
enhanced Direct Memory Access
Controller Area Network controller modules
Fast Ethenet Controller
Enhanced Modular Input Output System
Error Correction Status Module
Frequency-Modulated Phase-Locked Loop
FlexRay Communication Controller
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
JTAGC
LINFlexD
MC_ME
MC_CGM
MC_PCU
MC_RGM
MPU
Nexus
NMI
PIT_RTI
RTC/API
SIUL
SRAM
SSCM
STM
SWT
STCU
WKPU
JTAG controller
Local Interconnect Network Flexible with DMA support
Mode Entry Module
Clock Generation Module
Power Control Unit
Reset Generation Module
Memory Protection Unit
Nexus Development Interface
Non-Maskable Interrupt
Periodic Interrupt Timer with Real-Time Interrupt
Real-Time Clock/ Autonomous Periodic Interrupt
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Self Test Control Unit
Wakeup Unit
Table 3 summarizes the functions of the blocks present on the SPC564Bxx and
SPC56ECxx.
12/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Table 3.
Block diagram
SPC564Bxx and SPC56ECxx series block summary
Block
Function
Analog-to-digital converter (ADC) Converts analog voltages to digital values
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock monitor unit (CMU)
Monitors clock source (internal and external) integrity
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Cryptographic Security Engine
(CSE)
Supports the encoding and decoding of any kind of data
Crossbar (XBAR) switch
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width
DMA Channel Multiplexer
(DMAMUX)
Allows to route DMA sources (called slots) to DMA channels
Deserial serial peripheral
interface (DSPI)
Provides a synchronous serial interface for communication with external
devices
Error Correction Status Module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host
(eDMA)
processor via “n” programmable channels.
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area
network)
Supports the standard CAN communications protocol
FMPLL (frequency-modulated
phase-locked loop)
Generates high-speed system clocks and supports programmable frequency
modulation
FlexRay (FlexRay communication
Provides high-speed distributed control for advanced automotive applications
controller)
Fast Ethernet Controller (FEC)
Ethernet Media Access Controller (MAC) designed to support both 10 and 100
Mbps Ethernet/IEEE 802.3 networks
Internal multiplexer (IMUX) SIUL
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2C™) bus
A two wire bidirectional serial bus that provides a simple and efficient method of
data exchange between devices
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests for both
e200z0h and e200z4d cores
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
Doc ID 17478 Rev 4
13/118
Block diagram
Table 3.
SPC564Bxx - SPC56ECxx
SPC564Bxx and SPC56ECxx series block summary (continued)
Block
Function
LinFlexD (Local Interconnect
Network Flexible with DMA
support)
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Memory protection unit (MPU)
Provides hardware access control for all memory references generated in a
device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the
device
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and
modetransition sequences in all functional states; also manages the power
control unit, reset generation module and clock generation module, and holds
the configuration, control and status registers accessible for applications
Non-Maskable Interrupt (NMI)
Handles external events that must produce an immediate response, such as
power down detection
Nexus Development Interface
(NDI)
Provides real-time development capabilities for e200z0h and e200z4d core
processor
Periodic interrupt timer/ Real
Time Interrupt Timer (PIT_RTI)
Produces periodic interrupts and triggers
Real-time counter (RTC/API)
A free running counter used for time keeping applications, the RTC can be
configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode). Supports autonomous
periodic interrupt (API) function to generate a periodic wakeup request to exit a
low power mode or an interrupt request
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integration unit lite (SIUL) of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status and configuration
module (SSCM)
Provides system configuration and status data (such as memory size and
status, device mode and security status), device identification data, debug
status port enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AutoSAR and operating
system tasks
Semaphores
Provides the hardware support needed in multi-core systems for sharing
resources and provides a simple mechanism to achieve lock/unlock operations
via a single write access.
Wake Unit (WKPU)
Supports external sources that can generate interrupts or wakeup events, of
which can cause non-maskable interrupt requests or wakeup events.
14/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
3
Package pinouts and signal descriptions
Package pinouts and signal descriptions
The available LQFP pinouts and the LBGA ballmaps are provided in the following figures.
For functional port pin description, see Table 6.
176-pin LQFP configuration
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PB[2]
PC[8]
PC[13]
PC[12]
PI[0]
PI[1]
PI[2]
PI[3]
PE[7]
PE[6]
PH[8]
PH[7]
PH[6]
PH[5]
PH[4]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV_A
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PI[4]
PI[5]
PH[12]
PH[11]
PG[11]
PG[10]
PE[15]
PE[14]
PG[15]
PG[14]
PE[12]
Figure 2.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
LQFP176
Top view
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV_B
VSS_HV
PG[0]
PG[1]
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PG[13]
PA[3]
PI[13]
PI[12]
PI[11]
VDD_LV
VSS_LV
PI[8]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
VDD_HV_ADC1
VSS_HV_ADC1
PB[11]
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
NOTE
1) VDD_HV_B supplies the IO voltage domain for the
pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7],
PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2],
PH[1], PH[0], PG[12], PG[13], and PA[3].
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV_A
PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PJ[3]
PJ[2]
PJ[1]
PJ[0]
PI[15]
PI[14]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
VDD_HV_A
VSS_HV
PD[8]
PB[4]
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PB[3]
PC[9]
PC[14]
PC[15]
PJ[4]
VDD_HV_A
VSS_HV
PH[15]
PH[13]
PH[14]
PI[6]
PI[7]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PEp[10]
A[0]
PE[11]
VSS_HV
VDD_HV_A
VSS_HV
RESET
VSS_LV
VDD_LV
VRC_CTRL
PG[9]
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PF[9]
PF[8]
PF[12]
PC[6]
2)Availability of port pin alternate functions depends
on product selection.
Doc ID 17478 Rev 4
15/118
Package pinouts and signal descriptions
208-pin LQFP configuration
LQFP208
Top view
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PJ[12]
PJ[11]
PA[4]
PK[0]
PJ[15]
PJ[14]
PJ[13]
PA[13]
PJ[10]
PJ[9]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV_A
PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PJ[3]
PJ[2]
PJ[1]
PJ[0]
PI[15]
PI[14]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
VDD_HV_A
VSS_HV
PD[8]
PB[4]
PB[3]
PC[9]
PC[14]
PC[15]
PJ[4]
VDD_HV_A
VSS_HV
PH[15]
PH[13]
PH[14]
P[I6]
P[I7]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV_A
VSS_HV
RESET
VSS_LV
VDD_LV
VRC_CTRL
PG[9]
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PK[1]
PK[2]
PK[3]
PK[4]
PK[5]
PK[6]
PK[7]
PK[8]
PF[9]
PF[8]
PF[12]
PC[6]
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
PB[2]
PC[8]
PC[13]
PC[12]
PL[0]
PK[15]
PK[14]
PK[13]
PK[12]
PK[11]
PK[10]
PK[9]
PI[0]
PI[1]
PI[2]
PI[3]
PE[7]
PE[6]
PH[8]
PH[7]
PH[6]
PH[5]
PH[4]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV_A
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PI[4]
PI[5]
PH[12]
PH[11]
PG[11]
PG[10]
PE[15]
PE[14]
PG[15]
PG[14]
PE[12]
Figure 3.
SPC564Bxx - SPC56ECxx
NOTE
1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14],
PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3].
2) Availability of port pin alternate functions depends on product selection.
16/118
Doc ID 17478 Rev 4
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV_B
VSS_HV
PG[0]
PG[1]
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PG[13]
PA[3]
PI[13]
PI[12]
PI[11]
PI[10]
VDD_LV
VSS_LV
PI[9]
PI[8]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
VDD_HV_A
VSS_HV
PD[12]
VDD_HV_ADC1
VSS_HV_ADC1
PB[11]
PD[11]
PD[10]
PD[9]
PJ[5]
PJ[6]
PJ[7]
PJ[8]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
SPC564Bxx - SPC56ECxx
Figure 4.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Package pinouts and signal descriptions
256-pin BGA configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PC[15]
PB[2]
PC[13]
PI[1]
PE[7]
PH[8]
PE[2]
PE[4]
PC[4]
PE[3]
PH[9]
PI[4]
PH[11]
PE[14]
PA[10]
PG[11]
PH[13]
PC[14]
PC[8]
PC[12]
PI[3]
PE[6]
PH[5]
PE[5]
PC[5]
PC[0]
PC[2]
PH[12]
PG[10]
PA[11]
PA[9]
PA[8]
PH[14]
VDD_HV
_A
PC[9]
PL[0]
PI[0]
PH[7]
PH[6]
VSS_LV
VDD_HV
_A
PA[5]
PC[3]
PE[15]
PG[14]
PE[12]
PA[7]
PE[13]
PG[5]
PI[6]
PJ[4]
PB[3]
PK[15]
PI[2]
PH[4]
VDD_LV
PC[1]
PH[10]
PA[6]
PI[5]
PG[15]
PF[14]
PF[15]
PH[2]
PG[3]
PI[7]
PH[15]
PG[2]
VDD_LV
VSS_LV
PK[10]
PK[9]
PM[1]
PM[0]
PL[15]
PL[14]
PG[0]
PG[1]
PH[0]
VDD_HV
_A
PA[2]
PG[4]
PA[1]
PE[1]
PL[2]
PM[6]
PL[1]
PK[11]
PM[5]
PL[13]
PL[12]
PM[2]
PH[1]
PH[3]
PG[12]
PG[13]
PE[8]
PE[0]
PE[10]
PA[0]
PL[3]
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
PK[12]
VDD_HV
_B
PI[13]
PI[12]
PA[3]
PE[9]
VDD_HV
_A
PE[11]
PK[1]
PL[4]
VSS_LV
VSS_LV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
PK[13]
VDD_HV
_A
VDD_LV
VSS_LV
PI[11]
VSS_HV
VRC_CT
RL
VDD_LV
PG[9]
PL[5]
VSS_LV
VSS_LV
VSS_LV
VSS_HV
VSS_HV
VSS_HV
PK[14]
PD[15]
PI[8]
PI[9]
PI[10]
RESET
VSS_LV
PG[8]
PC[11]
PL[6]
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VDD_LV
VDD_LV
PM[3]
PD[14]
PD[13]
PB[14]
PB[15]
PC[10]
PG[7]
PB[0]
PK[2]
PL[7]
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VDD_LV
VDD_LV
PM[4]
PD[12]
PB[12]
PB[13]
VDD_HV
_ADC1
L
PG[6]
PB[1]
PK[4]
PF[9]
PK[5]
PK[6]
PK[7]
PK[8]
PL[8]
PL[9]
PL[10]
PL[11]
PB[11]
PD[10]
PD[11]
VSS_HV_
ADC1
M
PK[3]
PF[8]
PC[6]
PC[7]
PJ[13]
VDD_HV
_A
PB[10]
PF[6]
VDD_HV
_A
PJ[1]
PD[2]
PJ[5]
PB[5]
PB[6]
PJ[6]
PD[9]
PF[12]
PF[10]
PF[13]
PA[14]
PJ[9]
PA[12]
PF[0]
PF[5]
PF[7]
PJ[3]
PI[15]
PD[4]
PD[7]
PD[8]
PJ[8]
PJ[7]
PF[11]
PA[15]
PJ[11]
PJ[15]
PA[13]
PF[2]
PF[3]
PF[4]
VDD_LV
PJ[2]
PJ[0]
PD[0]
PD[3]
PD[6]
VDD_HV
_ADC0
PB[7]
PJ[12]
PA[4]
PK[0]
PJ[14]
PJ[10]
PF[1]
XTAL
EXTAL
VSS_LV
PB[9]
PB[8]
PI[14]
PD[1]
PD[5]
VSS_HV_
ADC0
PB[4]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
G
H
J
K
N
P
R
T
Notes:
1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14],
PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3].
2)Availability of port pin alternate functions depends on product selection.
3.1
Pad types
In the device the following types of pads are available for system pins and functional port
pins:
S = Slow(a)
M = Medium(a), (b)
F = Fast(a), (b)
I = Input only with analog feature(a)
A = Analog
Doc ID 17478 Rev 4
17/118
Package pinouts and signal descriptions
3.2
SPC564Bxx - SPC56ECxx
System pins
The system pins are listed in Table 4.
Table 4.
System pin descriptions
Pad
type
RESET
config.
LQFP 208
LBGA 256
Port pin
LQFP 176
Pin number
I/O
M
Input, weak
pull-up only
after
PHASE2
29
29
K1
I/O
direction
Function
RESET
Bidirectional reset with Schmitt-Trigger
characteristics and noise filter.
EXTAL
Analog input of the oscillator amplifier
circuit. Needs to be grounded if oscillator
bypass mode is used.
I
A(1)
—
58
74
T8
XTAL
Analog output of the oscillator amplifier
circuit, when the oscillator is not in bypass
mode.
Analog input for the clock generator when
the oscillator is in bypass mode.
I/O
A(1)
—
56
72
T7
1. For analog pads, it is not recommended to enable IBE if APC is enabled to avoid extra current in middle range voltage.
3.3
Functional ports
The functional port pins are listed in Table 5.
a. See the I/O pad electrical characteristics in the device datasheet for details.
b. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium.
For example, Fast/Medium pad will be Medium by default at reset. Similarly, Slow/Medium pad will be Slow by
default. Only exception is PC[1] which is in medium configuration by default (refer to PCR.SRC in the reference
manual, Pad Configuration Registers (PCR0—PCR198)).
18/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Functional port pin descriptions
Function
Peripheral
I/O
direction(2)
Pad type
RESET
config.
LQFP 176
LQFP 208
LBGA256
Pin number
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
PCR[0]
AF0
AF1
AF2
AF3
—
—
GPIO[0]
E0UC[0]
CLKOUT
E0UC[13]
WKPU[19]
CAN1RX
SIUL
eMIOS_0
MC_CGM
eMIOS_0
WKPU
FlexCAN_1
I/O
I/O
O
I/O
I
I
M/S
Tristate
24
24
G4
PCR[1]
AF0
AF1
AF2
AF3
—
—
—
GPIO[1]
E0UC[1]
—
—
WKPU[2]
CAN3RX
NMI[0](3)
SIUL
eMIOS_0
—
—
WKPU
FlexCAN_3
WKPU
I/O
I/O
—
—
I
I
I
S
Tristate
19
19
F3
PCR[2]
AF0
AF1
AF2
AF3
—
—
GPIO[2]
E0UC[2]
—
MA[2]
WKPU[3]
NMI[1](3)
SIUL
eMIOS_0
—
ADC_0
WKPU
WKPU
I/O
I/O
—
O
I
I
S
Tristate
17
17
F1
PCR[3]
AF0
AF1
AF2
AF3
—
—
—
GPIO[3]
E0UC[3]
LIN5TX
CS4_1
RX_ER_CLK
EIRQ[0]
ADC1_S[0]
SIUL
eMIOS_0
LINFlexD_5
DSPI_1
FEC
SIUL
ADC_1
I/O
I/O
O
O
I
I
I
M/S
Tristate
114
138
G16
PA[4]
PCR[4]
AF0
AF1
AF2
AF3
—
—
GPIO[4]
E0UC[4]
—
CS0_1
LIN5RX
WKPU[9]
SIUL
eMIOS_0
—
DSPI_1
LINFlexD_5
WKPU
I/O
I/O
—
I/O
I
I
S
Tristate
51
61
T2
PA[5]
PCR[5]
AF0
AF1
AF2
GPIO[5]
E0UC[5]
LIN4TX
SIUL
eMIOS_0
LINFlexD_4
I/O
I/O
O
M/S
Tristate
146
170
C10
Port
pin
PA[0]
PA[1]
PA[2]
PA[3]
PCR
Doc ID 17478 Rev 4
19/118
Package pinouts and signal descriptions
20/118
LQFP 208
LBGA256
PA[10]
LQFP 176
PA[9]
RESET
config.
PA[8]
Pad type
PA[7]
Function
I/O
direction(2)
PA[6]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
PCR[6]
AF0
AF1
AF2
AF3
—
—
GPIO[6]
E0UC[6]
—
CS1_1
LIN4RX
EIRQ[1]
SIUL
eMIOS_0
—
DSPI_1
LINFlexD_4
SIUL
I/O
I/O
—
O
I
I
S
Tristate
147
171
D11
PCR[7]
AF0
AF1
AF2
AF3
—
—
—
GPIO[7]
E0UC[7]
LIN3TX
—
RXD[2]
EIRQ[2]
ADC1_S[1]
SIUL
eMIOS_0
LINFlexD_3
—
FEC
SIUL
ADC_1
I/O
I/O
O
—
I
I
I
M/S
Tristate
128
152
C15
PCR[8]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[8]
E0UC[8]
E0UC[14]
—
RXD[1]
EIRQ[3]
ABS[0]
LIN3RX
SIUL
eMIOS_0
eMIOS_0
—
FEC
SIUL
MC_RGM
LINFlexD_3
I/O
I/O
I/O
—
I
I
I
I
M/S
Input,
weak
pull-up
129
153
B16
PCR[9]
AF0
AF1
AF2
AF3
—
—
GPIO[9]
E0UC[9]
—
CS2_1
RXD[0]
FAB
SIUL
eMIOS_0
—
DSPI1
FEC
MC_RGM
I/O
I/O
—
O
I
I
M/S
Pulldown
130
154
B15
PCR[10]
AF0
AF1
AF2
AF3
—
—
—
GPIO[10]
E0UC[10]
SDA
LIN2TX
COL
ADC1_S[2]
SIN_1
SIUL
eMIOS_0
I2C
LINFlexD_2
FEC
ADC_1
DSPI_1
I/O
I/O
I/O
O
I
I
I
M/S
Tristate
131
155
A15
PCR
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
PB[1]
LBGA256
PB[0]
LQFP 208
PA[15]
LQFP 176
PA[14]
RESET
config.
PA[13]
Pad type
PA[12]
Function
I/O
direction(2)
PA[11]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
PCR[11]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[11]
E0UC[11]
SCL
—
RX_ER
EIRQ[16]
LIN2RX
ADC1_S[3]
SIUL
eMIOS_0
I2C
—
FEC
SIUL
LINFlexD_2
ADC_1
I/O
I/O
I/O
—
I
I
I
I
M/S
Tristate
132
156
B14
PCR[12]
AF0
AF1
AF2
AF3
—
—
GPIO[12]
—
E0UC[28]
CS3_1
EIRQ[17]
SIN_0
SIUL
—
eMIOS_0
DSPI1
SIUL
DSPI_0
I/O
—
I/O
O
I
I
S
Tristate
53
69
P6
PCR[13]
AF0
AF1
AF2
AF3
GPIO[13]
SOUT_0
E0UC[29]
—
SIUL
DSPI_0
eMIOS_0
—
I/O
O
I/O
—
M/S
Tristate
52
66
R5
PCR[14]
AF0
AF1
AF2
AF3
—
GPIO[14]
SCK_0
CS0_0
E0UC[0]
EIRQ[4]
SIUL
DSPI_0
DSPI_0
eMIOS_0
SIUL
I/O
I/O
I/O
I/O
I
M/S
Tristate
50
58
P4
PCR[15]
AF0
AF1
AF2
AF3
—
GPIO[15]
CS0_0
SCK_0
E0UC[1]
WKPU[10]
SIUL
DSPI_0
DSPI_0
eMIOS_0
WKPU
I/O
I/O
I/O
I/O
I
M/S
Tristate
48
56
R2
PCR[16]
AF0
AF1
AF2
AF3
GPIO[16]
CAN0TX
E0UC[30]
LIN0TX
SIUL
FlexCAN_0
eMIOS_0
LINFlexD_0
I/O
O
I/O
I
M/S
Tristate
39
39
L3
PCR[17]
AF0
AF1
AF2
—
—
—
GPIO[17]
—
E0UC[31]
LIN0RX
WKPU[4]
CAN0RX
SIUL
—
eMIOS_0
LINFlexD_0
WKPU
FlexCAN_0
I/O
—
I/O
I
I
I
S
Tristate
40
40
M2
PCR
Doc ID 17478 Rev 4
21/118
Package pinouts and signal descriptions
22/118
LBGA256
PB[7]
LQFP 208
PB[6]
LQFP 176
PB[5]
RESET
config.
PB[4]
Pad type
PB[3]
Function
I/O
direction(2)
PB[2]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
PCR[18]
AF0
AF1
AF2
AF3
GPIO[18]
LIN0TX
SDA
E0UC[30]
SIUL
LINFlexD_0
I2C
eMIOS_0
I/O
O
I/O
I/O
M/S
Tristate
176
208
A2
PCR[19]
AF0
AF1
AF2
AF3
—
—
GPIO[19]
E0UC[31]
SCL
—
WKPU[11]
LIN0RX
SIUL
eMIOS_0
I2C
—
WKPU
LINFlexD_0
I/O
I/O
I/O
—
I
I
S
Tristate
1
1
D4
PCR[20]
AF0
AF1
AF2
AF3
—
—
GPI[20]
—
—
—
ADC0_P[0]
ADC1_P[0]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
88
104
T16
PCR[21]
AF0
AF1
AF2
AF3
—
—
GPI[21]
—
—
—
ADC0_P[1]
ADC1_P[1]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
91
107
N13
PCR[22]
AF0
AF1
AF2
AF3
—
—
GPI[22]
—
—
—
ADC0_P[2]
ADC1_P[2]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
92
108
N14
PCR[23]
AF0
AF1
AF2
AF3
—
—
GPI[23]
—
—
—
ADC0_P[3]
ADC1_P[3]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
93
109
R16
PCR
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
LBGA256
PB[13]
LQFP 208
PB[12]
LQFP 176
PB[11]
RESET
config.
PB[10]
Pad type
PB[9](5)
Function
I/O
direction(2)
PB[8]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
PCR[24]
AF0
AF1
AF2
AF3
—
—
—
—
GPI[24]
—
—
—
ADC0_S[0]
ADC1_S[4]
WKPU[25]
OSC32k_XTAL(4)
SIUL
—
—
—
ADC_0
ADC_1
WKPU
SXOSC
I
—
—
—
I
I
I
I
I
—
61
77
T11
PCR[25]
AF0
AF1
AF2
AF3
—
—
—
—
GPI[25]
—
—
—
ADC0_S[1]
ADC1_S[5]
WKPU[26]
OSC32k_EXTAL4
SIUL
—
—
—
ADC_0
ADC_1
WKPU
SXOSC
I
—
—
—
I
I
I
I
I
—
60
76
T10
PCR[26]
AF0
AF1
AF2
AF3
—
—
—
GPIO[26]
SOUT_1
CAN3TX
—
ADC0_S[2]
ADC1_S[6]
WKPU[8]
SIUL
DSPI_1
FlexCAN_3
—
ADC_0
ADC_1
WKPU
I/O
O
—
—
I
I
I
S
Tristate
62
78
N7
PCR[27]
AF0
AF1
AF2
AF3
—
GPIO[27]
E0UC[3]
—
CS0_0
ADC0_S[3]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
I/O
I
S
Tristate
97
117
M13
PCR[28]
AF0
AF1
AF2
AF3
—
GPIO[28]
E0UC[4]
—
CS1_0
ADC0_X[0]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
S
Tristate
101
123
L14
PCR[29]
AF0
AF1
AF2
AF3
—
GPIO[29]
E0UC[5]
—
CS2_0
ADC0_X[1]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
S
Tristate
103
125
L15
PCR
Doc ID 17478 Rev 4
23/118
Package pinouts and signal descriptions
PC[4]
24/118
LBGA256
PC[3]
LQFP 208
PC[2]
LQFP 176
PC[1](6)
RESET
config.
PC[0](6)
Pad type
PB[15]
Function
I/O
direction(2)
PB[14]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
PCR[30]
AF0
AF1
AF2
AF3
—
GPIO[30]
E0UC[6]
—
CS3_0
ADC0_X[2]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
S
Tristate
105
127
K15
PCR[31]
AF0
AF1
AF2
AF3
—
GPIO[31]
E0UC[7]
—
CS4_0
ADC0_X[3]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
S
Tristate
107
129
K16
PCR[32]
AF0
AF1
AF2
AF3
GPIO[32]
—
TDI
—
SIUL
—
JTAGC
—
I/O
—
I
—
M/S
Input,
weak
pull-up
154
178
B10
PCR[33]
AF0
AF1
AF2
AF3
GPIO[33]
—
TDO
—
SIUL
—
JTAGC
—
I/O
—
O
—
F/M
Tristate
149
173
D9
PCR[34]
AF0
AF1
AF2
AF3
—
GPIO[34]
SCK_1
CAN4TX
—
EIRQ[5]
SIUL
DSPI_1
FlexCAN_4
—
SIUL
I/O
I/O
O
—
I
M/S
Tristate
145
169
B11
GPIO[35]
CS0_1
MA[0]
—
CAN1RX
CAN4RX
EIRQ[6]
SIUL
DSPI_1
ADC_0
—
FlexCAN_1
FlexCAN_4
SIUL
I/O
I/O
O
PCR[35]
AF0
AF1
AF2
AF3
—
—
—
S
Tristate
144
168
C11
AF0
AF1
AF2
AF3
ALT4
—
—
—
GPIO[36]
E1UC[31]
—
SIUL
eMIOS_1
—
I/O
I/O
—
FR_B_TX_EN
SIN_1
CAN3RX
EIRQ[18]
Flexray
DSPI_1
FlexCAN_3
SIUL
O
I
I
I
M/S
Tristate
159
183
A9
PCR
PCR[36]
Doc ID 17478 Rev 4
I
I
I
SPC564Bxx - SPC56ECxx
PC[11]
LBGA256
PC[10]
LQFP 208
PC[9]
LQFP 176
PC[8]
RESET
config.
PC[7]
Pad type
PC[6]
Function
I/O
direction(2)
PC[5]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
PCR[37]
AF0
AF1
AF2
AF3
ALT4
—
GPIO[37]
SOUT_1
CAN3TX
—
FR_A_TX
EIRQ[7]
SIUL
DSPI_1
FlexCAN_3
—
Flexray
SIUL
I/O
O
O
—
O
I
M/S
Tristate
158
182
B9
PCR[38]
AF0
AF1
AF2
AF3
GPIO[38]
LIN1TX
E1UC[28]
—
SIUL
LINFlexD_1
eMIOS_1
—
I/O
O
I/O
—
S
Tristate
44
52
N3
PCR[39]
AF0
AF1
AF2
AF3
—
—
GPIO[39]
—
E1UC[29]
—
LIN1RX
WKPU[12]
SIUL
—
eMIOS_1
—
LINFlexD_1
WKPU
I/O
—
I/O
—
I
I
S
Tristate
45
53
N4
PCR[40]
AF0
AF1
AF2
AF3
GPIO[40]
LIN2TX
E0UC[3]
—
SIUL
LINFlexD_2
eMIOS_0
—
I/O
O
I/O
—
S
Tristate
175
207
B3
PCR[41]
AF0
AF1
AF2
AF3
—
—
GPIO[41]
—
E0UC[7]
—
LIN2RX
WKPU[13]
SIUL
—
eMIOS_0
—
LINFlexD_2
WKPU
I/O
—
I/O
—
I
I
S
Tristate
2
2
C3
PCR[42]
AF0
AF1
AF2
AF3
GPIO[42]
CAN1TX
CAN4TX
MA[1]
SIUL
FlexCAN_1
FlexCAN_4
ADC_0
I/O
O
O
O
M/S
Tristate
36
36
L1
PCR[43]
AF0
AF1
AF2
AF3
—
—
—
GPIO[43]
—
—
MA[2]
CAN1RX
CAN4RX
WKPU[5]
SIUL
—
—
ADC_0
FlexCAN_1
FlexCAN_4
WKPU
I/O
—
—
O
I
I
I
S
Tristate
35
PCR
Doc ID 17478 Rev 4
35
K4
25/118
Package pinouts and signal descriptions
PC[15]
PD[0]
PD[1]
26/118
SIUL
eMIOS_0
—
—
Flexray
DSPI_2
SIUL
I/O
I/O
—
—
O
I
I
M/S
Tristate
173
PCR[45]
AF0
AF1
AF2
AF3
ALT4
GPIO[45]
E0UC[13]
SOUT_2
—
FR_DBG[1]
SIUL
eMIOS_0
DSPI_2
—
Flexray
I/O
I/O
O
—
O
M/S
Tristate
174
PCR[46]
AF0
AF1
AF2
AF3
ALT4
—
GPIO[46]
E0UC[14]
SCK_2
—
FR_DBG[2]
EIRQ[8]
SIUL
eMIOS_0
DSPI_2
—
Flexray
SIUL
I/O
I/O
I/O
—
O
I
M/S
Tristate
3
PCR[47]
AF0
AF1
AF2
AF3
ALT4
GPIO[47]
E0UC[15]
CS0_2
—
FR_DBG[3]
EIRQ[20]
SIUL
eMIOS_0
DSPI_2
—
Flexray
SIUL
I/O
I/O
I/O
—
O
I
M/S
Tristate
4
PCR[48]
AF0
AF1
AF2
AF3
—
—
—
GPI[48]
—
—
—
ADC0_P[4]
ADC1_P[4]
WKPU[27]
SIUL
—
—
—
ADC_0
ADC_1
WKPU
I
—
—
—
I
I
I
I
Tristate
77
93
R12
PCR[49]
AF0
AF1
AF2
AF3
—
—
—
GPI[49]
—
—
—
ADC0_P[5]
ADC1_P[5]
WKPU[28]
SIUL
—
—
—
ADC_0
ADC_1
WKPU
I
—
—
—
I
I
I
I
Tristate
78
94
T13
Doc ID 17478 Rev 4
205
206
3
4
LBGA256
GPIO[44]
E0UC[12]
—
—
FR_DBG[0]
SIN_2
EIRQ[19]
LQFP 208
PCR[44]
AF0
AF1
AF2
AF3
ALT4
—
—
PCR
LQFP 176
RESET
config.
PC[14]
Pad type
PC[13]
Function
I/O
direction(2)
PC[12]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
B4
A3
B2
A1
SPC564Bxx - SPC56ECxx
LBGA256
PD[7]
LQFP 208
PD[6]
LQFP 176
PD[5]
RESET
config.
PD[4]
Pad type
PD[3]
Function
I/O
direction(2)
PD[2]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
PCR[50]
AF0
AF1
AF2
AF3
—
—
GPI[50]
—
—
—
ADC0_P[6]
ADC1_P[6]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
79
95
N11
PCR[51]
AF0
AF1
AF2
AF3
—
—
GPI[51]
—
—
—
ADC0_P[7]
ADC1_P[7]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
80
96
R13
PCR[52]
AF0
AF1
AF2
AF3
—
—
GPI[52]
—
—
—
ADC0_P[8]
ADC1_P[8]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
81
97
P12
PCR[53]
AF0
AF1
AF2
AF3
—
—
GPI[53]
—
—
—
ADC0_P[9]
ADC1_P[9]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
82
98
T14
PCR[54]
AF0
AF1
AF2
AF3
—
—
GPI[54]
—
—
—
ADC0_P[10]
ADC1_P[10]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
83
99
R14
PCR[55]
AF0
AF1
AF2
AF3
—
—
GPI[55]
—
—
—
ADC0_P[11]
ADC1_P[11]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
84
100
P13
PCR
Doc ID 17478 Rev 4
27/118
Package pinouts and signal descriptions
PD[14]
28/118
LBGA256
PD[13]
LQFP 208
PD[12]
LQFP 176
PD[11]
RESET
config.
PD[10]
Pad type
PD[9]
Function
I/O
direction(2)
PD[8]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
PCR[56]
AF0
AF1
AF2
AF3
—
—
GPI[56]
—
—
—
ADC0_P[12]
ADC1_P[12]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
87
103
P14
PCR[57]
AF0
AF1
AF2
AF3
—
—
GPI[57]
—
—
—
ADC0_P[13]
ADC1_P[13]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
94
114
N16
PCR[58]
AF0
AF1
AF2
AF3
—
—
GPI[58]
—
—
—
ADC0_P[14]
ADC1_P[14]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
95
PCR[59]
AF0
AF1
AF2
AF3
—
—
GPI[59]
—
—
—
ADC0_P[15]
ADC1_P[15]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
96
PCR[60]
AF0
AF1
AF2
AF3
—
GPIO[60]
CS5_0
E0UC[24]
—
ADC0_S[4]
SIUL
DSPI_0
eMIOS_0
—
ADC_0
I/O
O
I/O
—
I
S
Tristate
100
120
L13
PCR[61]
AF0
AF1
AF2
AF3
—
GPIO[61]
CS0_1
E0UC[25]
—
ADC0_S[5]
SIUL
DSPI_1
eMIOS_0
—
ADC_0
I/O
I/O
I/O
—
I
S
Tristate
102
124
K14
PCR[62]
AF0
AF1
AF2
AF3
ALT4
—
GPIO[62]
CS1_1
E0UC[26]
—
FR_DBG[0]
ADC0_S[6]
SIUL
DSPI_1
eMIOS_0
—
Flexray
ADC_0
I/O
O
I/O
—
O
I
S
Tristate
104
126
K13
PCR
Doc ID 17478 Rev 4
115
M14
116
M15
SPC564Bxx - SPC56ECxx
LBGA256
PE[4]
LQFP 208
PE[3]
LQFP 176
PE[2]
RESET
config.
PE[1]
Pad type
PE[0]
Function
I/O
direction(2)
PD[15]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
PCR[63]
AF0
AF1
AF2
AF3
ALT4
—
GPIO[63]
CS2_1
E0UC[27]
—
FR_DBG[1]
ADC0_S[7]
SIUL
DSPI_1
eMIOS_0
—
Flexray
ADC_0
I/O
O
I/O
—
O
I
S
Tristate
106
128
J13
PCR[64]
AF0
AF1
AF2
AF3
—
—
GPIO[64]
E0UC[16]
—
—
CAN5RX
WKPU[6]
SIUL
eMIOS_0
—
—
FlexCAN_5
WKPU
I/O
I/O
—
—
I
I
S
Tristate
18
PCR[65]
AF0
AF1
AF2
AF3
GPIO[65]
E0UC[17]
CAN5TX
—
SIUL
eMIOS_0
FlexCAN_5
—
I/O
I/O
O
—
M/S
Tristate
20
PCR[66]
AF0
AF1
AF2
AF3
ALT4
—
—
GPIO[66]
E0UC[18]
—
—
FR_A_TX_EN
SIN_1
EIRQ[21]
SIUL
eMIOS_0
—
—
Flexray
DSPI_1
SIUL
I/O
I/O
—
—
O
I
I
M/S
Tristate
156
PCR[67]
AF0
AF1
AF2
AF3
—
—
GPIO[67]
E0UC[19]
SOUT_1
—
FR_A_RX
WKPU[29]
SIUL
eMIOS_0
DSPI_1
—
Flexray
WKPU
I/O
I/O
O
—
I
I
M/S
Tristate
157
PCR[68]
AF0
AF1
AF2
AF3
ALT4
—
GPIO[68]
E0UC[20]
SCK_1
—
FR_B_TX
EIRQ[9]
SIUL
eMIOS_0
DSPI_1
—
Flexray
SIUL
I/O
I/O
I/O
—
O
I
M/S
Tristate
160
PCR
Doc ID 17478 Rev 4
18
20
180
181
184
G2
F4
A7
A10
A8
29/118
Package pinouts and signal descriptions
PE[8]
PE[9]
PE[10]
PE[11]
30/118
SIUL
eMIOS_0
DSPI_1
ADC_0
Flexray
WKPU
I/O
I/O
I/O
O
I
I
M/S
Tristate
161
PCR[70]
AF0
AF1
AF2
AF3
—
GPIO[70]
E0UC[22]
CS3_0
MA[1]
EIRQ[22]
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
O
O
I
M/S
Tristate
167
PCR[71]
AF0
AF1
AF2
AF3
—
GPIO[71]
E0UC[23]
CS2_0
MA[0]
EIRQ[23]
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
O
O
I
M/S
Tristate
168
PCR[72]
AF0
AF1
AF2
AF3
GPIO[72]
CAN2TX
E0UC[22]
CAN3TX
SIUL
FlexCAN_2
eMIOS_0
FlexCAN_3
I/O
O
I/O
O
M/S
Tristate
21
PCR[73]
AF0
AF1
AF2
AF3
—
—
—
GPIO[73]
—
E0UC[23]
—
WKPU[7]
CAN2RX
CAN3RX
SIUL
—
eMIOS_0
—
WKPU
FlexCAN_2
FlexCAN_3
I/O
—
I/O
—
I
I
I
S
Tristate
22
PCR[74]
AF0
AF1
AF2
AF3
—
GPIO[74]
LIN3TX
CS3_1
E1UC[30]
EIRQ[10]
SIUL
LINFlexD_3
DSPI_1
eMIOS_1
SIUL
I/O
O
O
I/O
I
S
Tristate
23
PCR[75]
AF0
AF1
AF2
AF3
—
—
GPIO[75]
E0UC[24]
CS4_1
—
LIN3RX
WKPU[14]
SIUL
eMIOS_0
DSPI_1
—
LINFlexD_3
WKPU
I/O
I/O
O
—
I
I
S
Tristate
25
Doc ID 17478 Rev 4
185
191
192
21
22
23
25
LBGA256
GPIO[69]
E0UC[21]
CS0_1
MA[2]
FR_B_RX
WKPU[30]
LQFP 208
PCR[69]
AF0
AF1
AF2
AF3
—
—
PCR
LQFP 176
RESET
config.
PE[7]
Pad type
PE[6]
Function
I/O
direction(2)
PE[5]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
B8
B6
A5
G1
H1
G3
H3
SPC564Bxx - SPC56ECxx
PE[15]
PF[0]
PF[1]
PF[2]
SIUL
—
eMIOS_1
—
FEC
DSPI_2
SIUL
ADC_1
I/O
—
I/O
—
I
I
I
I
M/S
Tristate
133
PCR[77]
AF0
AF1
AF2
AF3
—
GPIO[77]
SOUT_2
E1UC[20]
—
RXD[3]
SIUL
DSPI_2
eMIOS_1
—
FEC
I/O
O
I/O
—
I
M/S
Tristate
127
PCR[78]
AF0
AF1
AF2
AF3
—
GPIO[78]
SCK_2
E1UC[21]
—
EIRQ[12]
SIUL
DSPI_2
eMIOS_1
—
SIUL
I/O
I/O
I/O
—
I
M/S
Tristate
136
PCR[79]
AF0
AF1
AF2
AF3
GPIO[79]
CS0_2
E1UC[22]
SCK_6
SIUL
DSPI_2
eMIOS_1
DSPI_6
I/O
I/O
I/O
I/O
M/S
Tristate
137
PCR[80]
AF0
AF1
AF2
AF3
—
GPIO[80]
E0UC[10]
CS3_1
—
ADC0_S[8]
SIUL
eMIOS_0
DSPI_1
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
63
PCR[81]
AF0
AF1
AF2
AF3
—
GPIO[81]
E0UC[11]
CS4_1
—
ADC0_S[9]
SIUL
eMIOS_0
DSPI_1
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
64
PCR[82]
AF0
AF1
AF2
AF3
—
GPIO[82]
E0UC[12]
CS0_2
—
ADC0_S[10]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
I/O
—
I
S
Tristate
65
Doc ID 17478 Rev 4
157
151
160
161
79
80
81
LBGA256
GPIO[76]
—
E1UC[19]
—
CRS
SIN_2
EIRQ[11]
ADC1_S[7]
LQFP 208
PCR[76]
AF0
AF1
AF2
AF3
—
—
—
—
PCR
LQFP 176
RESET
config.
PE[14]
Pad type
PE[13]
Function
I/O
direction(2)
PE[12]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
C14
C16
A14
C12
P7
T6
R6
31/118
Package pinouts and signal descriptions
PF[6]
PF[7]
PF[8]
PF[9]
PF[10]
32/118
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
66
PCR[84]
AF0
AF1
AF2
AF3
—
GPIO[84]
E0UC[14]
CS2_2
—
ADC0_S[12]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
67
PCR[85]
AF0
AF1
AF2
AF3
—
GPIO[85]
E0UC[22]
CS3_2
—
ADC0_S[13]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
68
PCR[86]
AF0
AF1
AF2
AF3
—
GPIO[86]
E0UC[23]
CS1_1
—
ADC0_S[14]
SIUL
eMIOS_0
DSPI_1
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
69
PCR[87]
AF0
AF1
AF2
AF3
—
GPIO[87]
—
CS2_1
—
ADC0_S[15]
SIUL
—
DSPI_1
—
ADC_0
I/O
—
O
—
I
S
Tristate
70
PCR[88]
AF0
AF1
AF2
AF3
GPIO[88]
CAN3TX
CS4_0
CAN2TX
SIUL
FlexCAN_3
DSPI_0
FlexCAN_2
I/O
O
O
O
M/S
Tristate
42
PCR[89]
AF0
AF1
AF2
AF3
—
—
—
GPIO[89]
E1UC[1]
CS5_0
—
CAN2RX
CAN3RX
WKPU[22]
SIUL
eMIOS_1
DSPI_0
—
FlexCAN_2
FlexCAN_3
WKPU
I/O
I/O
O
—
I
I
I
S
Tristate
41
PCR[90]
AF0
AF1
AF2
AF3
GPIO[90]
CS1_0
LIN4TX
E1UC[2]
SIUL
DSPI_0
LINFlexD_4
eMIOS_1
I/O
O
O
I/O
M/S
Tristate
46
Doc ID 17478 Rev 4
82
83
84
85
86
50
49
54
LBGA256
GPIO[83]
E0UC[13]
CS1_2
—
ADC0_S[11]
LQFP 208
PCR[83]
AF0
AF1
AF2
AF3
—
PCR
LQFP 176
RESET
config.
PF[5]
Pad type
PF[4]
Function
I/O
direction(2)
PF[3]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
R7
R8
P8
N8
P9
N2
M4
P2
SPC564Bxx - SPC56ECxx
PF[14]
PF[15]
PG[0]
SIUL
DSPI_0
eMIOS_1
—
LINFlexD_4
WKPU
I/O
O
I/O
—
I
I
S
Tristate
47
PCR[92]
AF0
AF1
AF2
AF3
GPIO[92]
E1UC[25]
LIN5TX
—
SIUL
eMIOS_1
LINFlexD_5
—
I/O
I/O
O
—
M/S
Tristate
43
PCR[93]
AF0
AF1
AF2
AF3
—
—
GPIO[93]
E1UC[26]
—
—
LIN5RX
WKPU[16]
SIUL
eMIOS_1
—
—
LINFlexD_5
WKPU
I/O
I/O
—
—
I
I
S
Tristate
49
PCR[94]
AF0
AF1
AF2
AF3
ALT4
GPIO[94]
CAN4TX
E1UC[27]
CAN1TX
MDIO
SIUL
FlexCAN_4
eMIOS_1
FlexCAN_1
FEC
I/O
O
I/O
O
I/O
M/S
Tristate
126
PCR[95]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[95]
E1UC[4]
—
—
RX_DV
CAN1RX
CAN4RX
EIRQ[13]
SIUL
eMIOS_1
—
—
FEC
FlexCAN_1
FlexCAN_4
SIUL
I/O
I/O
—
—
I
I
I
I
M/S
Tristate
125
PCR[96]
AF0
AF1
AF2
AF3
ALT4
GPIO[96]
CAN5TX
E1UC[23]
—
MDC
SIUL
FlexCAN_5
eMIOS_1
—
FEC
I/O
O
I/O
—
O
F
Tristate
122
Doc ID 17478 Rev 4
55
LBGA256
GPIO[91]
CS2_0
E1UC[3]
—
LIN4RX
WKPU[15]
LQFP 208
PCR[91]
AF0
AF1
AF2
AF3
—
—
PCR
LQFP 176
RESET
config.
PF[13]
Pad type
PF[12]
Function
I/O
direction(2)
PF[11]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
R1
51
P1
57
150
149
146
P3
D14
D15
E13
33/118
Package pinouts and signal descriptions
PG[7]
34/118
LBGA256
PG[6]
LQFP 208
PG[5]
LQFP 176
PG[4]
RESET
config.
PG[3]
Pad type
PG[2]
Function
I/O
direction(2)
PG[1]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
PCR[97]
AF0
AF1
AF2
AF3
—
—
—
GPIO[97]
—
E1UC[24]
—
TX_CLK
CAN5RX
EIRQ[14]
SIUL
—
eMIOS_1
—
FEC
FlexCAN_5
SIUL
I/O
—
I/O
—
I
I
I
M
Tristate
121
145
E14
PCR[98]
AF0
AF1
AF2
AF3
GPIO[98]
E1UC[11]
SOUT_3
—
SIUL
eMIOS_1
DSPI_3
—
I/O
I/O
O
—
M/S
Tristate
16
16
E4
PCR[99]
AF0
AF1
AF2
AF3
—
GPIO[99]
E1UC[12]
CS0_3
—
WKPU[17]
SIUL
eMIOS_1
DSPI_3
—
WKPU
I/O
I/O
I/O
—
I
S
Tristate
15
15
E1
PCR[100]
AF0
AF1
AF2
AF3
GPIO[100]
E1UC[13]
SCK_3
—
SIUL
eMIOS_1
DSPI_3
—
I/O
I/O
I/O
—
M/S
Tristate
14
14
F2
PCR[101]
AF0
AF1
AF2
AF3
—
—
GPIO[101]
E1UC[14]
—
—
WKPU[18]
SIN_3
SIUL
eMIOS_1
—
—
WKPU
DSPI_3
I/O
I/O
—
—
I
I
S
Tristate
13
13
D1
PCR[102]
AF0
AF1
AF2
AF3
GPIO[102]
E1UC[15]
LIN6TX
—
SIUL
eMIOS_1
LINFlexD_6
—
I/O
I/O
O
—
M/S
Tristate
38
38
M1
PCR[103]
AF0
AF1
AF2
AF3
—
—
GPIO[103]
E1UC[16]
E1UC[30]
—
LIN6RX
WKPU[20]
SIUL
eMIOS_1
eMIOS_1
—
LINFlexD_6
WKPU
I/O
I/O
I/O
—
I
I
S
Tristate
37
37
L2
PCR
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
PG[14]
PG[15]
LBGA256
PG[13]
LQFP 208
PG[12]
LQFP 176
PG[11]
RESET
config.
PG[10]
Pad type
PG[9]
Function
I/O
direction(2)
PG[8]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
PCR[104]
AF0
AF1
AF2
AF3
—
GPIO[104]
E1UC[17]
LIN7TX
CS0_2
EIRQ[15]
SIUL
eMIOS_1
LINFlexD_7
DSPI_2
SIUL
I/O
I/O
O
I/O
I
S
Tristate
34
34
K3
PCR[105]
AF0
AF1
AF2
AF3
—
—
GPIO[105]
E1UC[18]
—
SCK_2
LIN7RX
WKPU[21]
SIUL
eMIOS_1
—
DSPI_2
LINFlexD_7
WKPU
I/O
I/O
—
I/O
I
I
S
Tristate
33
33
J4
PCR[106]
AF0
AF1
AF2
AF3
—
GPIO[106]
E0UC[24]
E1UC[31]
—
SIN_4
SIUL
eMIOS_0
eMIOS_1
—
DSPI_4
I/O
I/O
I/O
—
I
S
Tristate
138
162
B13
PCR[107]
AF0
AF1
AF2
AF3
GPIO[107]
E0UC[25]
CS0_4
CS0_6
SIUL
eMIOS_0
DSPI_4
DSPI_6
I/O
I/O
I/O
I/O
M/S
Tristate
139
163
A16
PCR[108]
AF0
AF1
AF2
AF3
ALT4
GPIO[108]
E0UC[26]
SOUT_4
—
TXD[2]
SIUL
eMIOS_0
DSPI_4
—
FEC
I/O
I/O
O
—
O
M/S
Tristate
116
140
F15
PCR[109]
AF0
AF1
AF2
AF3
ALT4
GPIO[109]
E0UC[27]
SCK_4
—
TXD[3]
SIUL
eMIOS_0
DSPI_4
—
FEC
I/O
I/O
I/O
—
O
M/S
Tristate
115
139
F16
PCR[110]
AF0
AF1
AF2
AF3
—
GPIO[110]
E1UC[0]
LIN8TX
—
SIN_6
SIUL
eMIOS_1
LINFlexD_8
—
DSPI_6
I/O
I/O
O
—
I
S
Tristate
134
158
C13
PCR[111]
AF0
AF1
AF2
AF3
—
GPIO[111]
E1UC[1]
SOUT_6
—
LIN8RX
SIUL
eMIOS_1
DSPI_6
—
LINFlexD_8
I/O
I/O
O
—
I
M/S
Tristate
135
159
D13
PCR
Doc ID 17478 Rev 4
35/118
Package pinouts and signal descriptions
PH[6]
PH[7]
36/118
LBGA256
PH[5]
LQFP 208
PH[4]
LQFP 176
PH[3]
RESET
config.
PH[2]
Pad type
PH[1]
Function
I/O
direction(2)
PH[0]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
PCR[112]
AF0
AF1
AF2
AF3
ALT4
—
GPIO[112]
E1UC[2]
—
—
TXD[1]
SIN_1
SIUL
eMIOS_1
—
—
FEC
DSPI_1
I/O
I/O
—
—
O
I
M/S
Tristate
117
141
E15
PCR[113]
AF0
AF1
AF2
AF3
ALT4
GPIO[113]
E1UC[3]
SOUT_1
—
TXD[0]
SIUL
eMIOS_1
DSPI_1
—
FEC
I/O
I/O
O
—
O
M/S
Tristate
118
142
F13
PCR[114]
AF0
AF1
AF2
AF3
ALT4
GPIO[114]
E1UC[4]
SCK_1
—
TX_EN
SIUL
eMIOS_1
DSPI_1
—
FEC
I/O
I/O
I/O
—
O
M/S
Tristate
119
143
D16
PCR[115]
AF0
AF1
AF2
AF3
ALT4
GPIO[115]
E1UC[5]
CS0_1
—
TX_ER
SIUL
eMIOS_1
DSPI_1
—
FEC
I/O
I/O
I/O
—
O
M/S
Tristate
120
144
F14
PCR[116]
AF0
AF1
AF2
AF3
GPIO[116]
E1UC[6]
SOUT_7
—
SIUL
eMIOS_1
DSPI_7
—
I/O
I/O
O
—
M/S
Tristate
162
186
D7
PCR[117]
AF0
AF1
AF2
AF3
—
GPIO[117]
E1UC[7]
—
—
SIN_7
SIUL
eMIOS_1
—
—
DSPI_7
I/O
I/O
—
—
I
S
Tristate
163
187
B7
PCR[118]
AF0
AF1
AF2
AF3
GPIO[118]
E1UC[8]
SCK_7
MA[2]
SIUL
eMIOS_1
DSPI_7
ADC_0
I/O
I/O
I/O
O
M/S
Tristate
164
188
C7
PCR[119]
AF0
AF1
AF2
AF3
ALT4
GPIO[119]
E1UC[9]
CS3_2
MA[1]
CS0_7
SIUL
eMIOS_1
DSPI_2
ADC_0
DSPI_7
I/O
I/O
O
O
I/O
M/S
Tristate
165
189
C6
PCR
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Functional port pin descriptions (continued)
Function
Peripheral
I/O
direction(2)
Pad type
RESET
config.
LQFP 176
LQFP 208
LBGA256
Pin number
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
PCR[120]
AF0
AF1
AF2
AF3
GPIO[120]
E1UC[10]
CS2_2
MA[0]
SIUL
eMIOS_1
DSPI_2
ADC_0
I/O
I/O
O
O
M/S
Tristate
166
190
A6
PH[9](6) PCR[121]
AF0
AF1
AF2
AF3
—
GPIO[121]
—
—
—
TCK
SIUL
—
—
—
JTAGC
I/O
—
—
—
I
S
Input,
weak
pull-up
155
179
A11
PCR[122]
AF0
AF1
AF2
AF3
—
GPIO[122]
—
—
—
TMS
SIUL
—
—
—
JTAGC
I/O
—
—
—
I
M/S
Input,
weak
pull-up
148
172
D10
PCR[123]
AF0
AF1
AF2
AF3
GPIO[123]
SOUT_3
CS0_4
E1UC[5]
SIUL
DSPI_3
DSPI_4
eMIOS_1
I/O
O
I/O
I/O
M/S
Tristate
140
164
A13
PCR[124]
AF0
AF1
AF2
AF3
GPIO[124]
SCK_3
CS1_4
E1UC[25]
SIUL
DSPI_3
DSPI_4
eMIOS_1
I/O
I/O
O
I/O
M/S
Tristate
141
165
B12
PCR[125]
AF0
AF1
AF2
AF3
GPIO[125]
SOUT_4
CS0_3
E1UC[26]
SIUL
DSPI_4
DSPI_3
eMIOS_1
I/O
O
I/O
I/O
M/S
Tristate
9
9
B1
PCR[126]
AF0
AF1
AF2
AF3
GPIO[126]
SCK_4
CS1_3
E1UC[27]
SIUL
DSPI_4
DSPI_3
eMIOS_1
I/O
I/O
O
I/O
M/S
Tristate
10
10
C1
PCR[127]
AF0
AF1
AF2
AF3
GPIO[127]
SOUT_5
—
E1UC[17]
SIUL
DSPI_5
—
eMIOS_1
I/O
O
—
I/O
M/S
Tristate
8
8
E3
PCR[128]
AF0
AF1
AF2
AF3
GPIO[128]
E0UC[28]
LIN8TX
—
SIUL
eMIOS_0
LINFlexD_8
—
I/O
I/O
O
—
S
Tristate
172
196
C5
Port
pin
PH[8]
PH[10](6
)
PH[11]
PH[12]
PH[13]
PH[14]
PH[15]
PI[0]
PCR
Doc ID 17478 Rev 4
37/118
Package pinouts and signal descriptions
PI[7]
PI[8]
38/118
LBGA256
PI[6]
LQFP 208
PI[5]
LQFP 176
PI[4]
RESET
config.
PI[3]
Pad type
PI[2]
Function
I/O
direction(2)
PI[1]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
PCR[129]
AF0
AF1
AF2
AF3
—
—
GPIO[129]
E0UC[29]
—
—
WKPU[24]
LIN8RX
SIUL
eMIOS_0
—
—
WKPU
LINFlexD_8
I/O
I/O
—
—
I
I
S
Tristate
171
195
A4
PCR[130]
AF0
AF1
AF2
AF3
GPIO[130]
E0UC[30]
LIN9TX
—
SIUL
eMIOS_0
LINFlexD_9
—
I/O
I/O
O
—
S
Tristate
170
194
D6
PCR[131]
AF0
AF1
AF2
AF3
—
—
GPIO[131]
E0UC[31]
—
—
WKPU[23]
LIN9RX
SIUL
eMIOS_0
—
—
WKPU
LINFlexD_9
I/O
I/O
—
—
I
I
S
Tristate
169
193
B5
PCR[132]
AF0
AF1
AF2
AF3
GPIO[132]
E1UC[28]
SOUT_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
O
—
M/S
Tristate
143
167
A12
PCR[133]
AF0
AF1
AF2
AF3
ALT4
GPIO[133]
E1UC[29]
SCK_4
CS2_5
CS2_6
SIUL
eMIOS_1
DSPI_4
DSPI_5
DSPI_6
I/O
I/O
I/O
O
O
M/S
Tristate
142
166
D12
PCR[134]
AF0
AF1
AF2
AF3
ALT4
GPIO[134]
E1UC[30]
CS0_4
CS0_5
CS0_6
SIUL
eMIOS_1
DSPI_4
DSPI_5
DSPI_6
I/O
I/O
I/O
I/O
I/O
S
Tristate
11
11
D2
PCR[135]
AF0
AF1
AF2
AF3
ALT4
GPIO[135]
E1UC[31]
CS1_4
CS1_5
CS1_6
SIUL
eMIOS_1
DSPI_4
DSPI_5
DSPI_6
I/O
I/O
O
O
O
S
Tristate
12
12
E2
PCR[136]
AF0
AF1
AF2
AF3
—
GPIO[136]
—
—
—
ADC0_S[16]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
108
130
J14
PCR
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
PI[15]
LBGA256
PI[14]
LQFP 208
PI[13]
LQFP 176
PI[12]
RESET
config.
PI[11]
Pad type
PI[10]
Function
I/O
direction(2)
PI[9]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
PCR[137]
AF0
AF1
AF2
AF3
—
GPIO[137]
—
—
—
ADC0_S[17]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
—
131
J15
PCR[138]
AF0
AF1
AF2
AF3
—
GPIO[138]
—
—
—
ADC0_S[18]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
—
134
J16
PCR[139]
AF0
AF1
AF2
AF3
—
—
GPIO[139]
—
—
—
ADC0_S[19]
SIN_3
SIUL
—
—
—
ADC_0
DSPI_3
I/O
—
—
—
I
I
S
Tristate
111
135
H16
PCR[140]
AF0
AF1
AF2
AF3
—
GPIO[140]
CS0_3
CS0_2
—
ADC0_S[20]
SIUL
DSPI_3
DSPI_2
—
ADC_0
I/O
I/O
I/O
—
I
S
Tristate
112
136
G15
PCR[141]
AF0
AF1
AF2
AF3
—
GPIO[141]
CS1_3
CS1_2
—
ADC0_S[21]
SIUL
DSPI_3
DSPI_2
—
ADC_0
I/O
O
O
—
I
S
Tristate
113
137
G14
PCR[142]
AF0
AF1
AF2
AF3
—
—
GPIO[142]
—
—
—
ADC0_S[22]
SIN_4
SIUL
—
—
—
ADC_0
DSPI_4
I/O
—
—
—
I
I
S
Tristate
76
92
T12
PCR[143]
AF0
AF1
AF2
AF3
—
GPIO[143]
CS0_4
CS2_2
—
ADC0_S[23]
SIUL
DSPI_4
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
S
Tristate
75
91
P11
PCR
Doc ID 17478 Rev 4
39/118
Package pinouts and signal descriptions
PJ[6]
PJ[7]
40/118
LBGA256
PJ[5]
LQFP 208
PJ[4]
LQFP 176
PJ[3]
RESET
config.
PJ[2]
Pad type
PJ[1]
Function
I/O
direction(2)
PJ[0]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
PCR[144]
AF0
AF1
AF2
AF3
—
GPIO[144]
CS1_4
CS3_2
—
ADC0_S[24]
SIUL
DSPI_4
DSPI_2
—
ADC_0
I/O
O
O
—
I
S
Tristate
74
90
R11
PCR[145]
AF0
AF1
AF2
AF3
—
—
GPIO[145]
—
—
—
ADC0_S[25]
SIN_5
SIUL
—
—
——
ADC_0
DSPI_5
I/O
—
—
—
I
I
S
Tristate
73
89
N10
PCR[146]
AF0
AF1
AF2
AF3
—
GPIO[146]
CS0_5
CS0_6
CS0_7
ADC0_S[26]
SIUL
DSPI_5
DSPI_6
DSPI_7
ADC_0
I/O
I/O
I/O
I/O
I
S
Tristate
72
88
R10
PCR[147]
AF0
AF1
AF2
AF3
—
GPIO[147]
CS1_5
CS1_6
CS1_7
ADC0_S[27]
SIUL
DSPI_5
DSPI_6
DSPI_7
ADC_0
I/O
O
O
O
I
S
Tristate
71
87
P10
PCR[148]
AF0
AF1
AF2
AF3
GPIO[148]
SCK_5
E1UC[18]
—
SIUL
DSPI_5
eMIOS_1
—
I/O
I/O
I/O
—
M/S
Tristate
5
5
D3
PCR[149]
AF0
AF1
AF2
AF3
—
GPIO[149]
—
—
—
ADC0_S[28]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
—
113
N12
PCR[150]
AF0
AF1
AF2
AF3
—
GPIO[150]
—
—
—
ADC0_S[29]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
—
112
N15
PCR[151]
AF0
AF1
AF2
AF3
—
GPIO[151]
—
—
—
ADC0_S[30]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
—
111
P16
PCR
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
PJ[14]
LBGA256
PJ[13]
LQFP 208
PJ[12]
LQFP 176
PJ[11]
RESET
config.
PJ[10]
Pad type
PJ[9]
Function
I/O
direction(2)
PJ[8]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
PCR[152]
AF0
AF1
AF2
AF3
—
GPIO[152]
—
—
—
ADC0_S[31]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
S
Tristate
—
110
P15
PCR[153]
AF0
AF1
AF2
AF3
—
GPIO[153]
—
—
—
ADC1_S[8]
SIUL
—
—
—
ADC_1
I/O
—
—
—
I
S
Tristate
—
68
P5
PCR[154]
AF0
AF1
AF2
AF3
—
GPIO[154]
—
—
—
ADC1_S[9]
SIUL
—
—
—
ADC_1
I/O
—
—
—
I
S
Tristate
—
67
T5
PCR[155]
AF0
AF1
AF2
AF3
—
GPIO[155]
—
—
—
ADC1_S[10]
SIUL
—
—
—
ADC_1
I/O
—
—
—
I
S
Tristate
—
60
R3
PCR[156]
AF0
AF1
AF2
AF3
—
GPIO[156]
—
—
—
ADC1_S[11]
SIUL
—
—
—
ADC_1
I/O
—
—
—
I
S
Tristate
—
59
T1
PCR[157]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[157]
—
CS1_7
—
CAN4RX
ADC1_S[12]
CAN1RX
WKPU[31]
SIUL
—
DSPI_7
—
FlexCAN_4
ADC_1
FlexCAN_1
WKPU
I/O
—
O
—
I
I
I
I
S
Tristate
—
65
N5
PCR[158]
AF0
AF1
AF2
AF3
GPIO[158]
CAN1TX
CAN4TX
CS2_7
SIUL
FlexCAN_1
FlexCAN_4
DSPI_7
I/O
O
O
O
M/S
Tristate
—
64
T4
PCR
Doc ID 17478 Rev 4
41/118
Package pinouts and signal descriptions
PK[5]
PK[6]
42/118
LBGA256
PK[4]
LQFP 208
PK[3]
LQFP 176
PK[2]
RESET
config.
PK[1]
Pad type
PK[0]
Function
I/O
direction(2)
PJ[15]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
PCR[159]
AF0
AF1
AF2
AF3
—
GPIO[159]
—
CS1_6
—
CAN1RX
SIUL
—
DSPI_6
—
FlexCAN_1
I/O
—
O
—
I
M/S
Tristate
—
63
R4
PCR[160]
AF0
AF1
AF2
AF3
GPIO[160]
CAN1TX
CS2_6
—
SIUL
FlexCAN_1
DSPI_6
—
I/O
O
O
—
M/S
Tristate
—
62
T3
PCR[161]
AF0
AF1
AF2
AF3
—
GPIO[161]
CS3_6
—
—
CAN4RX
SIUL
DSPI_6
—
—
FlexCAN_4
I/O
O
—
—
I
M/S
Tristate
—
41
H4
PCR[162]
AF0
AF1
AF2
AF3
GPIO[162]
CAN4TX
—
—
SIUL
FlexCAN_4
—
—
I/O
O
—
—
M/S
Tristate
—
42
L4
PCR[163]
AF0
AF1
AF2
AF3
—
—
GPIO[163]
E1UC[0]
—
—
CAN5RX
LIN8RX
SIUL
eMIOS_1
—
—
FlexCAN_5
LINFlexD_8
I/O
I/O
—
—
I
I
M/S
Tristate
—
43
N1
PCR[164]
AF0
AF1
AF2
AF3
GPIO[164]
LIN8TX
CAN5TX
E1UC[1]
SIUL
LINFlexD_8
FlexCAN_5
eMIOS_1
I/O
O
O
I/O
M/S
Tristate
—
44
M3
PCR[165]
AF0
AF1
AF2
AF3
—
—
GPIO[165]
—
—
—
CAN2RX
LIN2RX
SIUL
—
—
—
FlexCAN_2
LINFlexD_2
I/O
—
—
—
I
I
M/S
Tristate
—
45
M5
PCR[166]
AF0
AF1
AF2
AF3
GPIO[166]
CAN2TX
LIN2TX
—
SIUL
FlexCAN_2
LINFlexD_2
—
I/O
O
O
—
M/S
Tristate
—
46
M6
PCR
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
PK[13]
PK[14]
LBGA256
PK[12]
LQFP 208
PK[11]
LQFP 176
PK[10]
RESET
config.
PK[9]
Pad type
PK[8]
Function
I/O
direction(2)
PK[7]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
PCR[167]
AF0
AF1
AF2
AF3
—
—
GPIO[167]
—
—
—
CAN3RX
LIN3RX
SIUL
—
—
—
FlexCAN_3
LINFlexD_3
I/O
—
—
—
I
I
M/S
Tristate
—
47
M7
PCR[168]
AF0
AF1
AF2
AF3
GPIO[168]
CAN3TX
LIN3TX
—
SIUL
FlexCAN_3
LINFlexD_3
—
I/O
O
O
—
M/S
Tristate
—
48
M8
PCR[169]
AF0
AF1
AF2
AF3
—
GPIO[169]
—
—
—
SIN_4
SIUL
—
—
—
DSPI_4
I/O
—
—
—
I
M/S
Tristate
—
197
E8
PCR[170]
AF0
AF1
AF2
AF3
GPIO[170]
SOUT_4
—
—
SIUL
DSPI_4
—
—
I/O
O
—
—
M/S
Tristate
—
198
E7
PCR[171]
AF0
AF1
AF2
AF3
GPIO[171]
SCK_4
—
—
SIUL
DSPI_4
—
—
I/O
I/O
—
—
M/S
Tristate
—
199
F8
PCR[172]
AF0
AF1
AF2
AF3
GPIO[172]
CS0_4
—
—
SIUL
DSPI_4
—
—
I/O
I/O
—
—
M/S
Tristate
—
200
G12
PCR[173]
AF0
AF1
AF2
AF3
—
GPIO[173]
CS3_6
CS2_7
SCK_1
CAN3RX
SIUL
DSPI_6
DSPI_7
DSPI_1
FlexCAN_3
I/O
O
O
I/O
I
M/S
Tristate
—
201
H12
PCR[174]
AF0
AF1
AF2
AF3
GPIO[174]
CAN3TX
CS3_7
CS0_1
SIUL
FlexCAN_3
DSPI_7
DSPI_1
I/O
O
O
I/O
M/S
Tristate
—
202
J12
PCR
Doc ID 17478 Rev 4
43/118
Package pinouts and signal descriptions
PL[5]
PL[6]
PL[7]
44/118
LBGA256
PL[4]
LQFP 208
PL[3]
LQFP 176
PL[2]
RESET
config.
PL[1]
Pad type
PL[0]
Function
I/O
direction(2)
PK[15]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
PCR[175]
AF0
AF1
AF2
AF3
—
—
GPIO[175]
—
—
—
SIN_1
SIN_7
SIUL
—
—
—
DSPI_1
DSPI_7
I/O
—
—
—
I
I
M/S
Tristate
—
203
D5
PCR[176]
AF0
AF1
AF2
AF3
GPIO[176]
SOUT_1
SOUT_7
—
SIUL
DSPI_1
DSPI_7
—
I/O
O
O
—
M/S
Tristate
—
204
C4
PCR[177]
AF0
AF1
AF2
AF3
GPIO[177]
—
—
—
SIUL
—
—
—
I/O
—
—
—
M/S
Tristate
—
—
F7
(7)
AF0
AF1
AF2
AF3
GPIO[178]
—
MDO0(8)
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
F5
PCR[179]
AF0
AF1
AF2
AF3
GPIO[179]
—
MDO1
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
G5
PCR[180]
AF0
AF1
AF2
AF3
GPIO[180]
—
MDO2
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
H5
PCR[181]
AF0
AF1
AF2
AF3
GPIO[181]
—
MDO3
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
J5
PCR[182]
AF0
AF1
AF2
AF3
GPIO[182]
—
MDO4
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
K5
PCR[183]
AF0
AF1
AF2
AF3
GPIO[183]
—
MDO5
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
L5
PCR
PCR[178]
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
PL[14]
PL[15]
PM[0]
LBGA256
PL[13]
LQFP 208
PL[12]
LQFP 176
PL[11]
RESET
config.
PL[10]
Pad type
PL[9]
Function
I/O
direction(2)
PL[8]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
Package pinouts and signal descriptions
PCR[184]
AF0
AF1
AF2
AF3
—
GPIO[184]
—
—
—
EVTI
SIUL
—
—
—
Nexus
I/O
—
—
—
I
S
Pull-up
—
—
M9
PCR[185]
AF0
AF1
AF2
AF3
GPIO[185]
—
MSEO0
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
M10
PCR[186]
AF0
AF1
AF2
AF3
GPIO[186]
—
MCKO
—
SIUL
—
Nexus
—
I/O
—
O
—
F/S
Tristate
—
—
M11
PCR[187]
AF0
AF1
AF2
AF3
GPIO[187]
—
MSEO1
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
M12
PCR[188]
AF0
AF1
AF2
AF3
GPIO[188]
—
EVTO
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
F11
PCR[189]
AF0
AF1
AF2
AF3
GPIO[189]
—
MDO6
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
F10
PCR[190]
AF0
AF1
AF2
AF3
GPIO[190]
—
MDO7
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
E12
PCR[191]
AF0
AF1
AF2
AF3
GPIO[191]
—
MDO8
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
E11
PCR[192]
AF0
AF1
AF2
AF3
GPIO[192]
—
MDO9
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
E10
PCR
Doc ID 17478 Rev 4
45/118
Package pinouts and signal descriptions
LBGA256
PM[6]
LQFP 208
PM[5]
LQFP 176
PM[4]
RESET
config.
PM[3]
Pad type
PM[2]
Function
I/O
direction(2)
PM[1]
Pin number
Peripheral
Port
pin
Functional port pin descriptions (continued)
Alternate
function(1)
Table 5.
SPC564Bxx - SPC56ECxx
PCR[193]
AF0
AF1
AF2
AF3
GPIO[193]
—
MDO10
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
E9
PCR[194]
AF0
AF1
AF2
AF3
GPIO[194]
—
MDO11
—
SIUL
—
Nexus
—
I/O
—
O
—
M/S
Tristate
—
—
F12
PCR[195]
AF0
AF1
AF2
AF3
GPIO[195]
—
—
—
SIUL
—
—
—
I/O
—
—
—
M/S
Tristate
—
—
K12
PCR[196]
AF0
AF1
AF2
AF3
GPIO[196]
—
—
—
SIUL
—
—
—
I/O
—
—
—
M/S
Tristate
—
—
L12
PCR[197]
AF0
AF1
AF2
AF3
GPIO[197]
—
—
—
SIUL
—
—
—
I/O
—
—
—
M/S
Tristate
—
—
F9
PCR[198]
AF0
AF1
AF2
AF3
GPIO[198]
—
—
—
SIUL
—
—
—
I/O
—
—
—
M/S
Tristate
—
—
F6
PCR
1. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA =
000 → AF0; PCR.PA = 001 → AF1; PCR.PA = 010 → AF2; PCR.PA = 011 → AF3; PCR.PA = 100 → ALT4. This is
intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless
of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported
as “—”.
2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMIO.PADSELx bitfields inside the SIUL module.
3. NMI[0] and NMI[1] have a higher priority than alternate functions. When NMI is selected, the PCR.PA field is ignored.
4. SXOSC’s OSC32k_XTAL and OSC32k_EXTAL pins are shared with GPIO functionality. When used as crystal pins, other
functionality of the pin cannot be used and it should be ensured that application never programs OBE and PUE bit of the
corresponding PCR to "1".
5. If you want to use OSC32K functionality through PB[8] and PB[9], you must ensure that PB[10] is static in nature as PB[10]
can induce coupling on PB[9] and disturb oscillator frequency.
6. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
It is up to the user to configure these pins as GPIO when needed.
7. When MBIST is enabled to run ( STCU Enable = 1), the application must not drive or tie PAD[178) (MDO[0]) to 0 V before
the device exits reset (external reset is removed) as the pad is internally driven to 1 to indicate MBIST operation. When
MBIST is not enabled (STCU Enable = 0), there are no restriction as the device does not internally drive the pad.
46/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Package pinouts and signal descriptions
8. These pins can be configured as Nexus pins during reset by the debugger writing to the Nexus Development Interface
"Port Control Register" rather than the SIUL. Specifically, the debugger can enable the MDO[7:0], MSEO[1:0], and MCKO
ports by programming NDI (PCR[MCKO_EN] or PCR[PSTAT_EN]). MDO[8:11] ports can be enabled by programming NDI
((PCR[MCKO_EN] and PCR[FPM]) or PCR[PSTAT_EN]).
Doc ID 17478 Rev 4
47/118
Electrical Characteristics
4
SPC564Bxx - SPC56ECxx
Electrical Characteristics
This section contains electrical characteristics of the device as well as temperature and
power considerations.
This product contains devices to protect the inputs against damage due to high static
voltages. However, it is advisable to take precautions to avoid application of any voltage
higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD
or VSS_HV). This could be done by the internal pull-up and pull-down, which is provided by
the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and
its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.
4.1
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 6 are used and
the parameters are tagged accordingly in the tables where appropriate.
Table 6.
Parameter classifications
Classification tag
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.
D
Those parameters are derived mainly from simulations.
Note:
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
4.2
NVUSRO register
Portions of the device configuration, such as high voltage supply is controlled via bit values
in the Non-Volatile User Options Register (NVUSRO). For a detailed description of the
NVUSRO register, see SPC564Bxx and SPC56ECxx Reference Manual.
48/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
4.2.1
Electrical Characteristics
NVUSRO [PAD3V5V(0)] field description
Table 7 shows how NVUSRO [PAD3V5V(0)] controls the device configuration for VDD_HV_A
domain.
Table 7.
PAD3V5V(0) field description
Value(1)
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
1. '1' is delivery value. It is part of shadow flash memory, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V(0,1) bit value.
4.2.2
NVUSRO [PAD3V5V(1)] field description
Table 8 shows how NVUSRO [PAD3V5V(1)] controls the device configuration the device
configuration for VDD_HV_B domain.
Table 8.
PAD3V5V(1) field description
Value(1)
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
1. '1' is delivery value. It is part of shadow flash memory, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V(0,1) bit value.
4.3
Absolute maximum ratings
Table 9.
Absolute maximum ratings
Value
Symbol
VSS_HV
Parameter
SR
Conditions
Digital ground on VSS_HV
pins
Unit
Min
Max
—
0
0
V
VDD_HV_A
Voltage on VDD_HV_A pins
SR with respect to ground
(VSS_HV)
—
–0.3
6.0
V
VDD_HV_B(1)
Voltage on VDD_HV_B pins
SR with respect to common
ground (VSS_HV)
—
–0.3
6.0
V
Voltage on VSS_LV (low
voltage digital supply) pins
SR
with respect to ground
(VSS_HV)
—
VSS_HV − 0.1
VSS_HV + 0.1
V
VSS_LV
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Electrical Characteristics
Table 9.
SPC564Bxx - SPC56ECxx
Absolute maximum ratings (continued)
Value
Symbol
Parameter
Conditions
Base control voltage for
external BCP68 NPN device
VRC_CTRL(2)
Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC
SR
reference) pin with respect to
ground (VSS_HV)
VSS_ADC
Voltage on VDD_HV_ADC0
VDD_HV_ADC0 SR with respect to ground
(VSS_HV)
VDD_HV_ADC1
(4)
Voltage on VDD_HV_ADC1
SR with respect to ground
(VSS_HV)
Max
Relative to VDD_LV
0
VDD_LV + 1
V
—
VSS_HV − 0.1
VSS_HV + 0.1
V
—
–0.3
6.0
VDD_HV_A − 0.3
VDD_HV_A+0.3
–0.3
6.0
Relative to VDD_HV_A(3)
—
Relative to VDD_HV_A(2)
VIN
SR
Voltage on any GPIO pin with Relative to
VDD_HV_A/HV_B
respect to ground (VSS_HV)
IINJPAD
SR
Injected input current on any
pin during overload condition
IINJSUM
Absolute sum of all injected
SR input currents during overload
condition
IAVGSEG(5)
TSTORAGE
Sum of all the static I/O
current within a supply
SR
segment
(VDD_HV_A or VDD_HV_B)
SR Storage temperature
Unit
Min
—
VDD_HV_A−0.3
V
V
VDD_HV_A+0.3
V
VDD_HV_A/HV_B VDD_HV_A/HV_B
−0.3
+0.3
–10
10
mA
—
–50
50
VDD = 5.0 V ± 10%,
PAD3V5V = 0
70
VDD = 3.3 V ± 10%,
PAD3V5V = 1
64
—
mA
–55(6)
150
°C
1. VDD_HV_B can be independently controlled from VDD_HV_A. These can ramp up or ramp down in any order. Design is robust
against any supply order.
2. This voltage is internally generated by the device and no external voltage should be supplied.
3. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is
6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V.
4. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be
within ±300 mV of VDD_HV_B when these channels are used for ADC_1.
5. Any temperature beyond 125 °C should limit the current to 50 mA (max).
6. This is the storage temperature for the flash memory.
Note:
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Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN > VDD_HV_A/HV_B or
VIN < VSS_HV), the voltage on pins with respect to ground (VSS_HV) must not exceed the
recommended values.
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Electrical Characteristics
4.4
Recommended operating conditions
Table 10.
Recommended operating conditions (3.3 V)
Value
Symbol
VSS_HV
Parameter
Conditions
SR Digital ground on VSS_HV pins
Unit
Min
Max
—
0
0
V
VDD_HV_A(1) SR
Voltage on VDD_HV_A pins with
respect to ground (VSS_HV)
—
3.0
3.6
V
VDD_HV_B(1) SR
Voltage on VDD_HV_B pins with
respect to ground (VSS_HV)
—
3.0
3.6
V
Voltage on VSS_LV (low
SR voltage digital supply) pins with
respect to ground (VSS_HV)
—
VSS_HV − 0.1
VSS_HV + 0.1
V
Relative to VDD_LV
0
VDD_LV + 1
V
—
VSS_HV − 0.1
VSS_HV + 0.1
V
—
3.0(5)
3.6
Relative to
VDD_HV_A(6)
VDD_HV_A − 0.1
VDD_HV_A + 0.1
—
3.0
3.6
Relative to
VDD_HV_A(6)
VDD_HV_A − 0.1
VDD_HV_A + 0.1
—
VSS_HV − 0.1
—
—
VDD_HV_A/HV_B
+ 0.1
−5
5
VSS_LV(2)
Base control voltage for
external BCP68 NPN device
VRC_CTRL(3)
VSS_ADC
VDD_HV_ADC0
(4)
VDD_HV_ADC1
(7)
VIN
Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC
SR
reference) pin with respect to
ground (VSS_HV)
Voltage on VDD_HV_ADC0
SR with respect to ground
(VSS_HV)
Voltage on VDD_HV_ADC1
SR with respect to ground
(VSS_HV)
SR
Voltage on any GPIO pin with
respect to ground (VSS_HV)
Injected input current on any
pin during overload condition
IINJPAD
SR
IINJSUM
Absolute sum of all injected
SR input currents during overload
condition
Relative to
VDD_HV_A/HV_B
—
V
V
V
mA
—
−50
50
—
—
0.5
V/µs
—
0.5
—
V/min
TVDD
SR
VDD_HV_A slope to ensure
correct power up(8)
TA
SR
Ambient temperature under
bias
fCPU up to
120 MHz + 2%
–40
125
TJ
SR
Junction temperature under
bias
—
−40
150
°C
1. 100 nF EMI capacitance and 10 µF bulk capacitance need to be provided between each VDD/VSS_HV pair.
2. 100 nF EMI capacitance and 10 µF bulk capacitance need to be provided between each of the four VDD_LV/VSS_LV supply
pairs. For details refer to the Power Management chapter of the SPC564Bxx and SPC56ECxx Reference Manual.
3. This voltage is internally generated by the device and no external voltage should be supplied.
4. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
5. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is
reset.
6. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is
6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V.
7. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be
within ±100 mV of VDD_HV_B when these channels are used for ADC_1.
8. Guaranteed by the device validation.
Table 11.
Recommended operating conditions (5.0 V)
Value
Symbol
VSS_HV
VDD_HV_A(1)
VDD_HV_B
VSS_LV(3)
Parameter
SR Digital ground on VSS_HV pins
SR
VDD_HV_ADC0
(5)
Voltage on VDD_HV_A pins with
respect to ground (VSS_HV)
—
—
Voltage drop
(2)
0
0
4.5
5.5
3.0
5.5
V
V
3.0
5.5
V
Ethernet/3.3 V functionality
(See the notes in all figures in
SR Section 3: Package pinouts and
signal descriptions” for the list of
channels operating in VDD_HV_B
domain)
—
3.0
3.6
V
Voltage on VSS_LV (Low voltage
SR digital supply) pins with respect to
ground (VSS_HV)
—
VSS_HV – 0.1
VSS_HV + 0.1
V
Relative to
VDD_LV
0
VDD_LV + 1
V
—
VSS_HV – 0.1
VSS_HV + 0.1
V
—
4.5
5.5
3.0
5.5
Relative to
VDD_HV_A(6)
VDD_HV_A – 0.1
VDD_HV_A + 0.1
—
4.5
5.5
3.0
5.5
VDD_HV_A − 0.1
VDD_HV_A + 0.1
—
VSS_HV –0.1
—
Relative to
VDD_HV_A/HV_B
—
VDD_HV_A/HV_B
+ 0.1
Base control voltage for external
BCP68 NPN device
Voltage on VSS_HV_ADC0,
VSS_HV_ADC1 (ADC reference)
SR
pin with respect to ground
(VSS_HV)
SR
Voltage on VDD_HV_ADC0 with
respect to ground (VSS_HV)
Voltage
Voltage
drop(2)
drop(2)
Relative to
VDD_HV_A(6)
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Max
—
Voltage on VDD_HV_ADC1 with
VDD_HV_ADC1
respect to ground (VSS_HV)
SR
(7)
VIN
Unit
Min
Generic GPIO functionality
VRC_CTRL(4)
VSS_ADC
Conditions
Voltage on any GPIO pin with
SR
respect to ground (VSS_HV)
Doc ID 17478 Rev 4
V
V
V
SPC564Bxx - SPC56ECxx
Table 11.
Electrical Characteristics
Recommended operating conditions (5.0 V) (continued)
Value
Symbol
Parameter
Conditions
Injected input current on any pin
during overload condition
IINJPAD
SR
IINJSUM
Absolute sum of all injected input
SR
currents during overload condition
—
Unit
Min
Max
–5
5
mA
—
–50
50
—
—
0.5
V/µs
—
0.5
—
V/min
TA C-Grade Part SR Ambient temperature under bias
—
−40
85
TJ C-Grade Part SR Junction temperature under bias
—
−40
110
TA V-Grade Part SR Ambient temperature under bias
—
−40
105
TJ V-Grade Part SR Junction temperature under bias
—
−40
130
TA M-Grade Part SR Ambient temperature under bias
—
−40
125
TJ M-Grade Part SR Junction temperature under bias
—
−40
150
TVDD
SR
VDD_HV_A slope to ensure correct
power up(8)
°C
1. 100 nF EMI capacitance and 10 µF bulk capacitance needs to be provided between each VDD_HV_A/HV_B/VSS_HV pair.
2. Full device operation is guaranteed by design from 3.0 V–5.5 V. OSC electrical characteristics (startup time, IDD, negative
resistance, ESR and duty cycle) will not be guaranteed to stay within the stated limits when operating below 4.5 V and
above 3.6 V. However, OSC functionality is guaranteed within the entire range (3.0 V–5.5 V).
3. 100 nF EMI capacitance and 40 µF bulk capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
4. This voltage is internally generated by the device and no external voltage should be supplied.
5. 100 nF capacitance needs to be provided between VDD_HV_(ADC0/ADC1)/VSS_HV_(ADC0/ADC1) pair.
6. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is
6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V.
7. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be
within ±100 mV of VDD_HV_B when these channels are used for ADC_1.
8. Guaranteed by device validation.
Note:
SRAM retention guaranteed to LVD levels.
4.5
Thermal characteristics
4.5.1
Package thermal characteristics
Table 12.
LQFP thermal characteristics(1)
Symbol
C
Parameter
Conditions(2)
RθJA
CC
D
Thermal resistance,
Single-layer
junction-to-ambient
board—1s
natural convection
RθJA
CC
D
Thermal resistance,
Four-layer
junction-to-ambient
board—2s2p(5)
natural convection
Pin
count
Doc ID 17478 Rev 4
Value(3)
Unit
Min
Typ
Max
176
—
—
44.4(4)
°C/W
208
—
—
TBD
°C/W
176
—
—
36.1
°C/W
208
—
—
TBD
°C/W
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
1. Thermal characteristics are targets based on simulation that are subject to change per device characterization.
2. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C.
3. All values need to be confirmed during device validation.
4. 1s board as per standard Jedec (JESD51-7) in natural convection
5. 2s2p board as per standard JEDEC (JESD51-7) in natural convection.
Table 13.
Symbol
RθJA
CC
LBGA256 thermal characteristics(1)
C
—
Parameter
Conditions
Thermal resistance, junction-to-ambient
natural convection
Value
Single-layer board—1s
TBD
Four-layer board—2s2p
TBD
Unit
°C/W
1. Thermal characteristics are targets based on simulation that are subject to change per device characterization.
4.5.2
Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using
Equation 1:
Equation 1 TJ = TA + (PD × RθJA)
Where:
TA is the ambient temperature in °C.
RθJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PI/O (PD = PINT + PI/O).
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal
power.
PI/O represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand,
PI/O may be significant, if the device is configured to continuously drive external modules
and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
Equation 2 PD = K / (TJ + 273 °C)
Therefore, solving equations Equation 1 and Equation 2:
Equation 3 K = PD × (TA + 273 °C) + RθJA × PD2
Where:
K is a constant for the particular part, which may be determined from Equation 3
by measuring PD (at equilibrium) for a known TA. Using this value of K, the values
of PD and TJ may be obtained by solving equations Equation 1 and Equation 2
iteratively for any value of TA.
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Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Electrical Characteristics
4.6
I/O pad electrical characteristics
4.6.1
I/O pad types
The device provides four main I/O pad types depending on the associated alternate
functions:
●
Slow pads—These pads are the most common pads, providing a good compromise
between transition time and low electromagnetic emission.
●
Medium pads—These pads provide transition fast enough for the serial communication
channels with controlled current to reduce electromagnetic emission.
●
Fast pads—These pads provide maximum speed. These are used for improved Nexus
debugging capability.
●
Input only pads—These pads are associated to ADC channels and 32 kHz low power
external crystal oscillator providing low input leakage.
●
Low power pads—These pads are active in standby mode for wakeup source.
Also, medium/slow and fast/medium pads are available in design which can be configured to
behave like a slow/medium and medium/fast pads depending upon the slew-rate control.
Medium and fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance.
4.6.2
I/O input DC characteristics
Table 14 provides input DC electrical characteristics as described in Figure 5.
Figure 5.
I/O input DC electrical characteristics definition
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1
(GPDI register of SIUL)
PDIx = ‘0’
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Electrical Characteristics
Table 14.
Symbol
SPC564Bxx - SPC56ECxx
I/O input DC electrical characteristics
C
Value(2)
(1)
Parameter
Conditions
Unit
Min
Typ
Max
VIH
SR P
Input high level CMOS (Schmitt
Trigger)
—
0.65VDD
—
VDD + 0.4
VIL
SR P
Input low level CMOS (Schmitt
Trigger)
—
−0.3
—
0.35VDD
Input hysteresis CMOS (Schmitt
Trigger)
—
0.1VDD
—
—
TA = −40 °C
—
2
—
No injection T = 25 °C
A
on adjacent
TA = 105 °C
pin
—
2
—
—
12
500
TA = 125 °C
—
70
1000
VHYS CC C
P
ILKG CC
P
D
Digital input leakage
P
WFI
SR P
WNFI SR P
V
nA
Width of input pulse rejected by
analog filter(3)
—
—
—
40(4)
ns
Width of input pulse accepted by
analog filter(3)
—
1000(4)
—
—
ns
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. All values need to be confirmed during device validation.
3. Analog filters are available on all wakeup lines.
4. The width of input pulse in between 40 ns to 1000 ns is indeterminate. It may pass the noise or may not depending on
silicon sample to sample variation.
4.6.3
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
Table 15.
Symbol
●
Table 15 provides weak pull figures. Both pull-up and pull-down resistances are
supported.
●
Table 16 provides output driver characteristics for I/O pads when in SLOW
configuration.
●
Table 17 provides output driver characteristics for I/O pads when in MEDIUM
configuration.
●
Table 18 provides output driver characteristics for I/O pads when in FAST configuration.
I/O pull-up/pull-down DC electrical characteristics
C
P
|IWPU|
CC
C
P
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Parameter
Value
Conditions(1),(2)
PAD3V5V = 0
VIN = VIL, VDD =
Weak pull-up
PAD3V5V =
5.0 V ± 10%
current absolute
1(3)
value
VIN = VIL, VDD =
PAD3V5V = 1
3.3 V ± 10%
Doc ID 17478 Rev 4
Unit
Min
Typ
Max
10
—
150
10
—
250
10
—
150
µA
SPC564Bxx - SPC56ECxx
Table 15.
I/O pull-up/pull-down DC electrical characteristics (continued)
Symbol
C
P
|IWPD|
Electrical Characteristics
CC
C
P
Parameter
Value
Conditions(1),(2)
Unit
Min
Typ
Max
10
—
150
10
—
250
10
—
150
VIN = VIH, VDD = PAD3V5V = 0
Weak pull-down 5.0 V ± 10%
PAD3V5V = 1
current absolute
value
VIN = VIH, VDD =
PAD3V5V = 1
3.3 V ± 10%
µA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 16.
SLOW configuration output buffer electrical characteristics
Symbol C
Parameter
P
Output high level
VOH CC C SLOW
configuration
Value
Conditions(1),(2)
IOH = −3 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
IOH = −3 mA,
Push Pull VDD = 5.0 V ± 10%, PAD3V5V =
1(3)
Unit
Min
Typ
Max
0.8VDD
—
—
0.8VDD
—
—
P
IOH = −1.5 mA,
V − 0.8
VDD = 3.3 V ± 10%, PAD3V5V = 1 DD
—
—
P
IOL = 3 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
0.1VDD
—
—
0.1VDD
—
—
0.5
Output low level
VOL CC C SLOW
configuration
P
IOL = 3 mA,
Push Pull VDD = 5.0 V ± 10%, PAD3V5V =
1(3)
IOL = 1.5 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
V
V
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
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Electrical Characteristics
Table 17.
Symbol
SPC564Bxx - SPC56ECxx
MEDIUM configuration output buffer electrical characteristics
C
Parameter
VOL
CC
CC
Output high level
MEDIUM
configuration
C
Unit
Min
Typ
Max
IOH = −3 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 0
0.8VDD
—
—
IOH = −1.5 mA,
Push Pull VDD = 5.0 V ± 10%,
PAD3V5V = 1(3)
0.8VDD
—
—
C
VOH
Value
Conditions(1),(2)
V
C
IOH = −2 mA,
VDD = 3.3 V ± 10%,
PAD3V5V = 1
VDD − 0.8
—
—
C
IOL = 3 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
0.2VDD
IOL = 1.5 mA,
Push Pull VDD = 5.0 V ± 10%,
PAD3V5V = 1(3)
—
—
0.1VDD
IOL = 2 mA,
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
Output low level
MEDIUM
configuration
C
C
V
—
0.5
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 18.
Symbol
FAST configuration output buffer electrical characteristics
C
Parameter
P
VOH
CC
C
C
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Output high
level
FAST
configuration
Value
Conditions(1),(2)
Unit
Min
Typ
Max
IOH = −14 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 0
0.8VDD
—
—
IOH = −7 mA,
Push Pull VDD = 5.0 V ± 10%,
PAD3V5V = 1(3)
0.8VDD
—
—
VDD − 0.8
—
—
IOH = −11 mA,
VDD = 3.3 V ± 10%,
PAD3V5V = 1
Doc ID 17478 Rev 4
V
SPC564Bxx - SPC56ECxx
Table 18.
FAST configuration output buffer electrical characteristics (continued)
Symbol
VOL
Electrical Characteristics
C
CC
Value
Conditions(1),(2)
Parameter
Unit
Min
Typ
Max
P
IOL = 14 mA,
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
0.1VDD
C
IOL = 7 mA,
Output low level
FAST
Push Pull VDD = 5.0 V ± 10%,
PAD3V5V = 1(3)
configuration
—
—
0.1VDD
C
IOL = 11 mA,
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
0.5
V
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus outputs (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
4.6.4
Output pin transition times
Table 19.
Output pin transition times
Symbol
C
D
T
Ttr
CC
Parameter
CL = 25 pF
CL = 50 pF
CC
VDD = 5.0 V ± 10%,
PAD3V5V = 0
D Output transition time CL = 100 pF
output pin(4)
D SLOW configuration CL = 25 pF
T
CL = 50 pF
D
CL = 100 pF
D
CL = 25 pF
CL = 50 pF
Output transition time
D output pin(4)
CL = 100 pF
MEDIUM
D
CL = 25 pF
configuration
T
CL = 50 pF
T
Ttr
D
CL = 100 pF
VDD = 3.3 V ± 10%,
PAD3V5V = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
CL = 25 pF
CL = 50 pF
Ttr
CC
Value(3)
Conditions(1),(2)
VDD = 5.0 V ± 10%,
PAD3V5V = 0
Output transition time C = 100 pF
L
D output pin(4)
CL = 25 pF
FAST configuration
CL = 50 pF
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF
Doc ID 17478 Rev 4
Unit
Min
Typ
Max
—
—
50
—
—
100
—
—
125
—
—
40
—
—
50
—
—
75
—
—
10
—
—
20
—
—
40
—
—
12
—
—
25
—
—
40
—
—
4
—
—
6
—
—
12
—
—
4
—
—
7
—
—
12
ns
ns
ns
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3. All values need to be confirmed during device validation.
4. CL includes device and package capacitances (CPKG < 5 pF).
4.6.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply is associated
to a VDD/VSS_HV supply pair as described in Table 20.
Table 21 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment
should remain below the IAVGSEG maximum value.
In order to ensure device functionality, the sum of the dynamic and static current of the I/O
on a single segment should remain below the IDYNSEG maximum value.
Table 20.
I/O supplies
Package
I/O Supplies
LBGA256
Equivalent to 208-pin LQFP segment pad distribution + G6, G11, H11, J11
LQFP208
pin6
(VDD_HV_A)
pin7
(VSS_HV)
pin27
(VDD_HV_A)
pin28
(VSS_HV)
pin73
(VSS_HV)
pin75
(VDD_HV_A)
pin101
(VDD_HV_A)
pin102
(VSS_HV)
pin132
(VSS_HV)
pin133
(VDD_HV_A)
pin147
(VSS_HV)
pin148
(VDD_HV_B)
pin174
(VSS_HV)
pin175
(VDD_HV_A)
—
LQFP176
pin6
(VDD_HV_A)
pin7
(VSS_HV)
pin27
(VDD_HV_A)
pin28
(VSS_HV)
pin57
(VSS_HV)
pin59
(VDD_HV_A)
pin85
(VDD_HV_A)
pin86
(VSS_HV)
pin123
(VSS_HV)
pin124
(VDD_HV_B)
pin150
(VSS_HV)
pin151
(VDD_HV_A)
—
—
Table 21.
Symbol
ISWTSLW(4)
ISWTMED
(4)
ISWTFST(4)
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I/O consumption
C
Peak I/O current for
CC D
CL = 25 pF
SLOW configuration
Peak I/O current for
CC D MEDIUM
configuration
Peak I/O current for
CC D
FAST configuration
Value(3)
Conditions(1),(2)
Parameter
CL = 25 pF
CL = 25 pF
Unit
Min
Typ
Max
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
19.9
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
15.5
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
28.8
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
16.3
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
113.5
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
52.1
Doc ID 17478 Rev 4
mA
mA
mA
SPC564Bxx - SPC56ECxx
Table 21.
Symbol
Electrical Characteristics
I/O consumption (continued)
C
Value(3)
Conditions(1),(2)
Parameter
Unit
Min
Typ
Max
—
—
2.22
—
—
3.13
—
—
6.54
—
—
1.51
—
—
2.14
—
—
4.33
—
—
6.5
—
—
13.32
CL = 100 pF, 13 MHz
—
—
18.26
CL = 25 pF, 13 MHz
—
—
4.91
—
—
8.47
—
—
10.94
—
—
21.05
—
—
33
—
—
55.77
—
—
14
—
—
20
CL = 100 pF, 40 MHz
—
—
34.89
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
70
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
65(4)
CL = 25 pF, 2 MHz
CL = 25 pF, 4 MHz
IRMSSLW
Root mean square
CL = 100 pF, 2 MHz
CC D I/O current for SLOW
CL = 25 pF, 2 MHz
configuration
CL = 25 pF, 4 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 2 MHz
CL = 25 pF, 13 MHz
IRMSMED
Root mean square
I/O current for
CC D
MEDIUM
configuration
CL = 25 pF, 40 MHz
CL = 25 pF, 40 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 13 MHz
CL = 25 pF, 40 MHz
CL = 25 pF, 64 MHz
IRMSFST
IAVGSEG
VDD = 5.0 V ± 10%,
PAD3V5V = 0
Root mean square
CL = 100 pF, 40 MHz
CC D I/O current for FAST
CL = 25 pF, 40 MHz
configuration
VDD = 3.3 V ± 10%,
CL = 25 pF, 64 MHz PAD3V5V = 1
Sum of all the static
SR D I/O current within a
supply segment
mA
mA
mA
mA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3. All values need to be confirmed during device validation.
4. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
4.7
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
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Electrical Characteristics
Figure 6.
SPC564Bxx - SPC56ECxx
Start-up reset requirements
VDD_HV_A
VDDMIN
RESET
VIH
VIL
device reset forced by RESET
Figure 7.
device start-up phase
Noise filtering on reset signal
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
Table 22.
Symbol
Reset electrical characteristics
C
Parameter
Value(2)
Conditions(1)
Unit
Min
Typ
Max
VIH
SR P
Input High Level CMOS
(Schmitt Trigger)
—
0.65VDD
—
VDD + 0.4
V
VIL
SR P
Input low Level CMOS
(Schmitt Trigger)
—
−0.3
—
0.35VDD
V
VHYS
CC C
Input hysteresis CMOS
(Schmitt Trigger)
—
0.1VDD
—
—
V
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Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Table 22.
Symbol
VOL
Ttr
Electrical Characteristics
Reset electrical characteristics (continued)
C
Parameter
CC P Output low level
Output transition time
CC D output pin(4)
MEDIUM configuration
Typ
Max
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
Push Pull, IOL = 1 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 1(3)
—
—
0.1VDD
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
CL = 25 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
10
CL = 50 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
20
CL = 100 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
40
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
12
CL = 50 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
25
CL = 100 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
40
—
—
—
40
ns
—
1000
—
—
ns
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
—
150
|IWPU|
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
—
150
10
—
250
Reset input not filtered
pulse
Weak pull-up current
CC P
absolute value
Unit
Min
WFRST SR P Reset input filtered pulse
WNFRST SR P
Value(2)
Conditions(1)
VDD = 5.0 V ± 10%, PAD3V5V =
1(5)
V
ns
µA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. All values need to be confirmed during device validation.
3. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to the RGM module section of the
device Reference Manual).
4. CL includes device and package capacitance (CPKG < 5 pF).
5. The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Doc ID 17478 Rev 4
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
4.8
Power management electrical characteristics
4.8.1
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply
VDD_LV from the high voltage supply VDD_HV_A. The following supplies are involved:
Figure 8.
●
HV: High voltage external power supply for voltage regulator module. This must be
provided externally through VDD_HV_A power pin.
●
LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is
generated by the on-chip VREG with an external ballast (BCP68 NPN device). It is
further split into four main domains to ensure noise isolation between critical LV
modules within the device:
–
LV_COR: Low voltage supply for the core. It is also used to provide supply for
FMPLL through double bonding.
–
LV_CFLA0/CFLA1: Low voltage supply for the two code Flash modules. It is
shorted with LV_COR through double bonding.
–
LV_DFLA: Low voltage supply for data Flash module. It is shorted with LV_COR
through double bonding.
–
LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double
bonding.
Voltage regulator capacitance connection
100 nf
VDD_LV
100 nf
VSS_LV VDD_LV
100 nf
VSS_LV VDD_LV
VSS_LV
40 µf
(4 × 10 µf)
PD0 (always on domain)
PD0 Logic
PD1 Switchable Domain
(FMPLL, Flash)
(CREGn)
VDD_LV
HPVDD
VSS_LV
Off chip
BCP68
NPN driver
VRC_CTRL
sw1 (<0.1Ω)
HPREG
LPVDD
10 µf
LPREG
Chip Boundary
(CDEC2)
VDD_BV
VDD_HV_A
HPVDD
LPVDD
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VSS_HV
100 nf
Doc ID 17478 Rev 4
32 KB
Split
56 KB
Split
8 KB
Split
CTRL
CTRL
CTRL
SPC564Bxx - SPC56ECxx
Electrical Characteristics
The internal voltage regulator requires external bulk capacitance (CREGn) to be connected
to the device to provide a stable low voltage digital supply to the device. Also required for
stability is the CDEC2 capacitor at ballast collector. This is needed to minimize sharp
injection current when ballast is turning ON. Apart from the bulk capacitance, user should
connect EMI/decoupling cap (CREGP) at each VDD_LV/VSS_LV pin pair.
Recommendations
●
The external NPN driver must be BCP68 type.
●
VDD_LV should be implemented as a power plane from the emitter of the ballast
transistor.
●
10 µF capacitors should be connected to the 4 pins closest to the outside of the
package and should be evenly distributed around the package. For BGA packages, the
balls should be used are D8, H14, R9, J3–one cap on each side of package.
–
There should be a track direct from the capacitor to this pin (pin also connects to
VDD_LV plane). The tracks ESR should be less than 100 mΩ.
–
The remaining VDD_LV pins (exact number will vary with package) should be
decoupled with 0.1 µF caps, connected to the pin as per 10 µF.
(see Section 4.4: Recommended operating conditions).
4.8.2
VDD_BV options
●
Option 1: VDD_BV shared with VDD_HV_A
VDD_BV must be star routed from VDD_HV_A from the common source. This is to
eliminate ballast noise injection on the MCU.
●
Option 2: VDD_BV independent of the MCU supply
VDD_BV > 2.6 V for correct functionality. The device is not monitoring this supply hence
the external component must meet the 2.6 V criteria through external monitoring if
required.
Table 23.
Symbol
Voltage regulator electrical characteristics
C
Value(2)
Conditions(1)
Parameter
CREGn
SR — External ballast stability capacitance
RREG
SR —
CREGP
Decoupling capacitance (Close to
SR —
the pin)
Typ
Max
—
40
—
60
µF
—
—
—
0.2
W
VDD_HV_A/HV_B/VSS_HV
pair
100
—
nF
VDD_LV/VSS_LV pair
100
—
nF
µF
Stability capacitor equivalent serial
resistance
CDEC2
Stability capacitance regulator
SR — supply (Close to the ballast
collector)
VMREG
CC P Main regulator output voltage
IMREG
SR —
Unit
Min
VDD_HV_A/VSS_HV
10
—
40
Before trimming
—
1.32
—
After trimming
—
1.28
—
—
—
350
Main regulator current provided to
VDD_LV domain
Doc ID 17478 Rev 4
—
V
mA
65/118
Electrical Characteristics
Table 23.
SPC564Bxx - SPC56ECxx
Voltage regulator electrical characteristics (continued)
Symbol
C
Value(2)
Conditions(1)
Parameter
Main regulator module current
consumption
Unit
Min
Typ
Max
IMREG = 200 mA
—
—
2
IMREGINT
CC D
IMREG = 0 mA
—
—
1
VLPREG
CC P Low power regulator output voltage After trimming
—
1.23
—
V
ILPREG
SR —
—
—
50
mA
—
—
600
D
ILPREGINT
CC
—
IVREGREF
Low power regulator current
provided to VDD_LV domain
—
ILPREG = 15 mA;
T
Low power regulator module current A = 55 °C
consumption
I
= 0 mA;
LPREG
IVREDLVD12
CC D
Main LVD current consumption
(switch-off during standby)
IDD_HV_A
CC D
In-rush current on VDD_HV_A(3)
during power-up
µA
—
20
—
TA = 55 °C
—
2
—
µA
TA = 55 °C
—
1
—
µA
—
—
600(4)
mA
TA = 55 °C
Main LVDs and reference current
CC D consumption (low power and main
regulator switched off)
mA
—
1. VDD_HV_A = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Assumption is VDD_HV_A is now supplying the external ballast. This current is the ballast inrush current.
4. Inrush current is seen more like steps of 600 mA peak. The startup of the regulator happens in steps of 50 mV in ~25 steps
to reach ~1.2 V VDD_LV. Each step peak current is within 600 mA
4.8.3
Voltage monitor electrical characteristics
The device implements a Power-on Reset module to ensure correct power-up initialization,
as well as four low voltage detectors to monitor the VDD_HV_A and the VDD_LV voltage while
device is supplied:
Note:
66/118
●
POR monitors VDD_HV_A during the power-up phase to ensure device is maintained in
a safe reset state
●
LVDHV3 monitors VDD_HV_A to ensure device is reset below minimum functional supply
●
LVDHV5 monitors VDD_HV_A when application uses device in the 5.0 V±10% range
●
LVDLVCOR monitors power domain No. 1 (PD1)
●
LVDLVBKP monitors power domain No. 0 (PD0). VDD_LV is same as PD0 supply.
When enabled, PD2 (RAM retention) is monitored through LVD_DIGBKP.
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Figure 9.
Electrical Characteristics
Low voltage monitor vs. Reset
VDDHV/LV
VLVDHVxH/LVxH
VLVDHVxL/LVxL
RESET
Table 24.
Symbol
Low voltage monitor electrical characteristics
C
Parameter
Value(2)
Conditions(1)
Unit
Min
Typ
Max
VPORUP
SR P Supply for functional POR module
—
1.0
—
5.5
VPORH
CC P Power-on reset threshold
—
1.5
—
2.6
VLVDHV3H
CC T LVDHV3 low voltage detector high threshold
—
2.7
—
2.85
VLVDHV3L
CC T LVDHV3 low voltage detector low threshold
—
2.6
—
2.74
VLVDHV5H
CC T LVDHV5 low voltage detector high threshold
—
4.3
—
4.5
VLVDHV5L
CC T LVDHV5 low voltage detector low threshold
—
4.2
—
4.4
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold
TA = 25 °C,
after trimming
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
V
1.14(3)
1.14(3)
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. The min. and max variation across process voltage and temperature will be available after device characterization.
Expected to be within 10 mV.
4.9
Low voltage domain power consumption
Table 25 provides DC electrical characteristics for significant application modes. These
values are indicative values; actual consumption depends on the application.
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Electrical Characteristics
Table 25.
Low voltage power domain electrical characteristics
Symbol
IDDMAX(4)
IDDRUN
IDDHALT
IDDSTOP
SPC564Bxx - SPC56ECxx
C
CC D
RUN mode maximum
average current
—
T RUN mode typical average
CC
current(7)
T
CC P HALT mode
CC
P
IDDSTDBY3
P
STANDBY3 mode
(96 KB RAM CC
(14)
P current
retained)
No clocks active
P
IDDSTDBY2
STANDBY2 mode
(64 KB RAM CC
current(15)
P
retained)
No clocks active
T
IDDSTDBY1
STANDBY1 mode
(8 KB RAM CC
current(16)
P
retained)
No clocks active
Adders in
LP mode
CC T
210
Unit
300(5),(6) mA
(10)
mA
110(8)
150(10)
mA
—
25
35
mA
TA = 25 °C
—
400(9)
TA = 150 °C
—
TA = 25 °C
TA = 25 °C
P
—
Max(3)
240(9),
at 80 MHz
No clocks active
Typ(2)
(9)
TA = 25 °C
—
current(12)
Min
175(8),
at 120 MHz
current(11)
STOP mode
Value
Conditions(1)
Parameter
—
1200(9),
(13)
µA
10(9)
30(9)
mA
—
60
175
µA
TA = 150 °C
—
1000
3000
µA
TA = 25 °C
—
45
135
µA
TA = 150 °C
—
800
2000
µA
TA = 25 °C
—
25
75
µA
TA = 150 °C
—
500
1000
µA
32 kHz OSC
—
TA = 25 °C
—
—
5
µA
4–40 MHz OSC
—
TA = 25 °C
—
—
3
mA
16 MHz IRC
—
TA = 25 °C
—
—
500
µA
128 kHz IRC
—
TA = 25 °C
—
—
5
µA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified All temperatures are based on an
ambient temperature.
2. Target typical current consumption for the following typical operating conditions and configuration. Process = typical,
Voltage = 1.2 V.
3. Target maximum current consumption for mode observed under typical operating conditions. Process = Fast, Voltage =
1.32 V.
4. Running consumption is given on voltage regulator supply (VDDREG). It does not include consumption linked to I/Os
toggling. This value is highly dependent on the application. The given value is thought to be a worst case value with all
cores and peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to be
noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce
peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible.
5. Higher current may sunk by device during power-up and standby exit. Please refer to in rush current in Table 23.
6. Maximum “allowed” current is package dependent.
7. Only for the “P” classification: Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPI as Master, PLL
as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer
reset enabled. RUN current measured with typical application with accesses on both code flash and RAM.
8. Subject to change, Configuration: 1 × e200z4d + 4 kbit/s Cache, 1 × eDMA (32 ch), 4 × FlexCAN (2 × 500 kbit/s, 2 ×
125 kbit/s), 10 × LINFlexD (20 kbit/s), 8 × DSPI (4 × 2 Mbit/s, 3 × 4 Mbit/s, 1 × 10 Mbit/s), 40 × PWM (200 Hz), 40 × ADC
Input, 1 × CTU (40 ch.), 1 × FlexRay (2 ch., 10 Mbit/s), 1 × RTC, 4 × PIT, 1 × SWT, 1 × STM. Ethernet and e200z0h
disabled. Also reduced timed I/O channels for smaller packages. RUN current measured with typical application with
accesses on both code flash and RAM.
9. This value is obtained from limited sample set
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SPC564Bxx - SPC56ECxx
Electrical Characteristics
10. Subject to change, Configuration: 1 × e200z4d + 4 kbit/s Cache, 1 × e200z0h (1/2 system frequency), CSE, 1 × eDMA
(10 ch.), 6 × FlexCAN (4 × 500 kbit/s, 2 × 125 kbit/s), 4 × LINFlexD (20 kbit/s), 6 × DSPI (2 × 2 Mbit/s, 3 × 4 Mbit/s,
1 × 10 Mbit/s), 16 × Timed I/O, 16 × ADC Input, 1 × FlexRay (2 ch., 10 Mbit/s), 1 × FEC (100 Mbit/s), 1 × RTC, 4 × PIT,
1 × SWT, 1 × STM. For lower pin count packages reduce the amount of timed I/O’s and ADC channels. RUN current
measured with typical application with accesses on both code flash and RAM.
11. Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz ON. 16 MHz XTAL clock. FlexCAN:
instances: 0, 1, 2 ON (clocked but no reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex: instances: 0, 1, 2
ON (clocked but no reception or transmission), instance: 3-9 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]PA[11] and PC[12]-PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication,
instance: 1-7 clocks gated). RTC/API ON. PIT ON. STM ON. ADC ON but no conversion except 2 analog watchdogs.
12. Only for the “P” classification: No clock, FIRC 16 MHz OFF, SIRC128 kHz ON, PLL OFF, HPvreg OFF, LPVreg ON. All
possible peripherals off and clock gated. Flash in power down mode.
13. This current is the maximum value at room temperature for any sample. The condition is same as note 11.
14. Only for the “P” classification: LPreg ON, HPVreg OFF, 96 KB RAM ON, device configured for minimum consumption, all
possible modules switched-off.
15. Only for the “P” classification: LPreg ON, HPVreg OFF, 64 KB RAM ON, device configured for minimum consumption, all
possible modules switched-off.
16. LPreg ON, HPVreg OFF, 8 KB RAM ON, device configured for minimum consumption, all possible modules switched OFF.
4.10
Flash memory electrical characteristics
4.10.1
Program/Erase characteristics
Table 26 shows the code flash memory program and erase characteristics.
Table 26.
Code flash memory—Program and erase specifications
Value
Symbol
C
Parameter
Min
Typ(1)
Initial
max(2)
Max(3)
Unit
Tdwprogram
Double word (64 bits) program time(4)
—
18
50
500
µs
T16Kpperase
16 KB block pre-program and erase time
—
200
500
5000
ms
T32Kpperase
C 32 KB block pre-program and erase time
128 KB block pre-program and erase time
—
300
600
5000
ms
—
600
1300
5000
ms
Teslat
D Erase Suspend Latency
—
—
30
30
µs
tESRT
C Erase Suspend Request Rate
20
—
—
—
ms
—
—
10
10
µs
—
—
30
30
µs
T128Kpperase
tPABT
tEAPT
CC D Program Abort Latency
D Erase Abort Latency
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Table 27 shows the data flash memory program and erase characteristics.
Table 27.
Data flash memory—Program and erase specifications
Value
Symbol
C
Parameter
Unit
Min
Typ(1)
Initial
max(2)
Max(3)
—
30
70
500
µs
C 16 KB block pre-program and erase time
—
700
800
5000
ms
Teslat
D Erase Suspend Latency
—
—
30
30
µs
tESRT
C Erase Suspend Request Rate
10
—
—
—
ms
—
—
12
12
µs
—
—
30
30
µs
Word (32 bits) program time(4)
Twprogram
T16Kpperase
tPABT
CC D Program Abort Latency
D Erase Abort Latency
tEAPT
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
Table 28.
Flash memory module life
Value
Symbol
P/E
C
CC
Retention CC
Parameter
Conditions
Unit
Min
Typ
Number of program/erase cycles per
block for 16 Kbyte blocks over the
operating temperature range (TJ)
—
100000
100000
cycles
Number of program/erase cycles per
C block for 32 Kbyte blocks over the
operating temperature range (TJ)
—
10000
100000
cycles
Number of program/erase cycles per
block for 128 Kbyte blocks over the
operating temperature range (TJ)
—
1000
100000
cycles
Blocks with 0–1000 P/E
cycles
20
—
years
Blocks with 10000 P/E
cycles
10
—
years
Blocks with 100000 P/E
cycles
5
—
years
C
Minimum data retention at 85 °C
average ambient temperature(1)
1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature
range.
ECC circuitry provides correction of single bit faults and is used to improve further
automotive reliability results. Some units will experience single bit corrections throughout
the life of the product with no impact to product reliability.
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Table 29.
Electrical Characteristics
Flash memory read access timing
Conditions(1)
Symbol
fREAD
C
CC
Parameter
Code flash
memory
Max
Data flash
memory
Unit
P
5 wait states
13 wait states
120 + 2%
C Maximum frequency for Flash
D reading
3 wait state
9 wait state
80 + 2%
3 wait
C
states(2)
—
MHz
—
64 + 2%
7 wait states
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. Wait states are subject to change per device characterization.
4.10.2
Flash memory power supply DC characteristics
Table 30 shows the flash memory power supply DC characteristics on external supply.
Table 30.
Symbol
Flash memory power supply DC electrical characteristics
Value(2)
Conditions(1)
Parameter
Unit
Min
ICFREAD(3)
IDFREAD
(3)
Code flash
Sum of the current consumption Flash memory module read memory
CC
fCPU = 120 MHz + 2%(4)
on VDD_HV_A on read access
Data flash
memory
Typ
Max
33
mA
13
Code flash
memory
52
Data flash
memory
13
Sum of the current consumption
ICFLPW(3) CC on VDD_HV_A during flash
memory low power mode
Code flash
memory
1.1
ICFPWD(3)
Code flash
memory
150
IDFPWD
Data flash
memory
150
Program/Erase on-going
Sum of the current consumption while reading flash memory
CC
on VDD_HV_A (program/erase)
registers
(3)
IDFMOD
fCPU = 120 MHz + 2% (4)
ICFMOD(3)
Sum of the current consumption
CC on VDD_HV_A during flash
(3)
memory power down mode
mA
mA
µA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Data based on characterization results, not tested in production.
4. fCPU 120 MHz + 2% can be achieved over full temperature 125 °C ambient, 150 °C junction temperature.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
4.10.3
Flash memory start-up/switch-off timings
Table 31.
Start-up time/Switch-off time
Symbol
C
Delay for flash memory module to exit
TFLARSTEXIT CC D
reset mode
TFLALPEXIT
TFLAPDEXIT
CC T
Delay for flash memory module to exit
low-power mode
Delay for flash memory module to exit
CC T
power-down mode
TFLALPENTRY CC T
Value
Conditions
Parameter
Unit
(1)
Code flash
memory
Data flash
memory
Code flash
memory
Code flash
memory
Data flash
memory
Delay for flash memory module to enter Code flash
memory
low-power mode
Min
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
125
—
—
Max
0.5
30
µs
0.5
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
4.11
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.11.1
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for the application.
●
●
Software recommendations − The software flowchart must include the management of
runaway conditions such as:
–
Corrupted program counter
–
Unexpected reset
–
Critical data corruption (control registers)
Pre-qualification trials − Most of the common failures (unexpected reset and program
counter corruption) can be reproduced by manually forcing a low state on the reset pin
or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When
unexpected behavior is detected, the software can be hardened to prevent
unrecoverable errors occurring (see application note Software Techniques For
Improving Microcontroller EMC Performance (AN1015)).
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4.11.2
Electrical Characteristics
Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission
test conforms to the IEC61967-1 standard, which specifies the general conditions for EMI
measurements.
EMI radiated emission measurement(1)(2)
Table 32.
Value
Symbol
C
Parameter
Conditions
Unit
Min
—
SR — Scan range
Typ
Max
—
0.150
fCPU SR — Operating frequency
—
—
120
—
MHz
VDD_LV SR — LV operating voltages
—
—
1.28
—
V
—
—
18 dBµV
—
—
14(3) dBµV
SEMI CC T Peak level
No PLL frequency
VDD = 5 V, TA = 25 °C,
modulation
LQFP176 package
Test conforming to IEC 61967-2, ± 2% PLL frequency
fOSC = 40 MHz/fCPU = 120 MHz modulation
1000 MHz
1. EMI testing and I/O port waveforms per IEC 61967-1, -2, -4.
2. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local
marketing representative.
3. All values need to be confirmed during device validation.
4.11.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pin). This test
conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the
application note Electrostatic Discharge Sensitivity Measurement (AN1181).
Table 33.
Symbol
ESD absolute maximum ratings(1)(2)
Ratings
Conditions
Class
Max value(3)
VESD(HBM)
Electrostatic discharge voltage
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C
2000
VESD(MM)
Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
VESD(CDM)
Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
Unit
V
500
750 (corners)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
3. Data based on characterization results, not tested in production.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply over-voltage is applied to each power supply pin.
●
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 34.
Latch-up results
Symbol
Parameter
LU
4.12
Static latch-up class
Conditions
Class
TA = 125 °C
conforming to JESD 78
II level A
Fast external crystal oscillator (4–40 MHz) electrical
characteristics
The device provides an oscillator/resonator driver. Figure 10 describes a simple model of
the internal oscillator driver and provides an example of a connection for an oscillator or a
resonator.
Table 35 provides the parameter description of 4 MHz to 40 MHz crystals used for the
design simulations.
Figure 10. Crystal oscillator and resonator connection scheme
EXTAL
C1
Crystal
XTAL
XTAL
RD
DEVICE
VDD
I
R
EXTAL
EXTAL
Resonator
DEVICE
XTAL
DEVICE
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C2
SPC564Bxx - SPC56ECxx
Electrical Characteristics
Note:
XTAL/EXTAL must not be directly used to drive external circuits.
Table 35.
Crystal description
Crystal
motional
capacitance
(Cm) fF
Crystal
motional
inductance
(Lm) mH
Load on
xtalin/xtalout
C1 = C2
(pF)(1)
Shunt
capacitance
between
xtalout
and xtalin
C0(2) (pF)
Nominal
frequency
(MHz)
NDK crystal
reference
Crystal
equivalent
series
resistance
ESR Ω
4
NX8045GB
300
2.68
591.0
21
2.93
8
300
2.46
160.7
17
3.01
10
150
2.93
86.6
15
2.91
120
3.11
56.5
15
2.93
120
3.90
25.3
10
3.00
50
6.18
2.56
8
3.49
12
NX5032GA
16
40
NX5032GA
1. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all
the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package,
etc.).
Figure 11.
Fast external crystal oscillator (4 to 40 MHz) electrical characteristics
S_MTRANS bit (ME_GS register)
1
0
VXTAL
1/fMXOSC
VFXOSC
90%
VFXOSCOP
10%
TMXOSCSU
Table 36.
Symbol
fFXOSC
valid internal clock
Fast external crystal oscillator (4 to 40 MHz) electrical characteristics
C
SR —
Parameter
Fast external crystal
oscillator frequency
Value(2)
Conditions(1)
—
Doc ID 17478 Rev 4
Unit
Min
Typ
Max
4.0
—
40.0
MHz
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Electrical Characteristics
Table 36.
Symbol
SPC564Bxx - SPC56ECxx
Fast external crystal oscillator (4 to 40 MHz) electrical characteristics (continued)
C
Parameter
gmFXOSC
CC C Fast external crystal VDD = 3.3 V ± 10%
oscillator
transconductance VDD = 5.0 V ± 10%
VFXOSC
fOSC = 40 MHz
Oscillation
For both VDD = 3.3 V ±
CC T
amplitude at EXTAL 10%, VDD = 5.0 V ±
10%
VFXOSCOP
CC P
Value(2)
Conditions(1)
Oscillation
operating point
Unit
—
VDD = 3.3 V ± 10%,
fOSC = 40 MHz
IFXOSC
(3)
VDD = 5.0 V ± 10%,
Fast external crystal f
OSC = 40 MHz
CC T oscillator
VDD = 3.3 V ± 10%,
consumption
fOSC = 16 MHz
Typ
Max
8.699
13.159
15.846
9.440
13.159
16.859
—
0.95
—
—
1.8
—
2
2.2
—
2.3
2.5
—
1.3
1.5
mA/V
V
V
mA
VDD = 5.0 V ± 10%,
fOSC = 16 MHz
TFXOSCSU
Min
f
= 40 MHz
Fast external crystal OSC
For both VDD = 3.3 V ±
CC T oscillator start-up
10%, VDD = 5.0 V ±
time
10%
—
1.6
1.8
—
—
5
ms
VIH
Input high level
SR P CMOS
(Schmitt Trigger)
Oscillator bypass
mode
0.65VDD_HV_A
—
VDD_HV_A + 0.4
V
VIL
Input low level
SR P CMOS
(Schmitt Trigger)
Oscillator bypass
mode
−0.3
—
0.35VDD_HV_A
V
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled
peripherals).
4.13
Slow external crystal oscillator (32 kHz) electrical
characteristics
The device provides a low power oscillator/resonator driver.
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Electrical Characteristics
Figure 12. Crystal oscillator and resonator connection scheme
OSC32K_EXTAL
OSC32K_EXTAL
Resonator
Crystal
C1
RP
OSC32K_XTAL
OSC32K_XTAL
C2
DEVICE
Note:
DEVICE
OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.
Figure 13. lEquivalent circuit of a quartz crystal
C0
Crystal
C1
Cm
C2
Rm
Lm
C1
Table 37.
C2
Crystal motional characteristics(1)
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
Lm
Motional inductance
—
—
11.796
—
KH
Cm
Motional capacitance
—
—
2
—
fF
Load capacitance at OSC32K_XTAL and
OSC32K_EXTAL with respect to ground(2)
—
18
—
28
pF
C1/C2
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Electrical Characteristics
Table 37.
SPC564Bxx - SPC56ECxx
Crystal motional characteristics(1) (continued)
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
Max
—
—
65
AC coupled @ C0 = 4.9 pF(4)
—
—
50
(4)
—
—
35
pF(4)
—
—
30
AC coupled @ C0 = 2.85
pF(4)
Rm(3)
Motional resistance
AC coupled @ C0 = 7.0 pF
AC coupled @ C0 = 9.0
kW
1. The crystal used is Epson Toyocom MC306.
2. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It
includes all the parasitics due to board traces, crystal and package.
3. Maximum ESR (Rm) of the crystal is 50 kΩ.
4. C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins.
Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics
OSCON bit (OSC_CTL register)
1
0
VOSC32K_XTAL
1/fLPXOSC32K
VLPXOSC32K
90%
10%
TLPXOSC32KSU
Table 38.
Symbol
Slow external crystal oscillator (32 kHz) electrical characteristics
C
SR —
Slow external crystal oscillator
frequency
gmSXOSC
CC —
Slow external crystal oscillator
transconductance
VSXOSC
CC T Oscillation amplitude
ISXOSCBIAS CC T Oscillation bias current
Value(2)
Conditions(1)
Parameter
fSXOSC
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valid internal clock
Unit
Min
Typ
Max
32
32.768
40
VDD = 3.3 V ± 10%,
17.45
—
28.23
VDD = 5.0 V ± 10%
17.79
—
29.91
—
1.2
1.4
1.7
V
—
1.2
—
4.4
µA
—
Doc ID 17478 Rev 4
kHz
µA/V
SPC564Bxx - SPC56ECxx
Table 38.
Electrical Characteristics
Slow external crystal oscillator (32 kHz) electrical characteristics (continued)
Symbol
C
Value(2)
Conditions(1)
Parameter
Unit
Min
Typ
Max
ISXOSC
CC T
Slow external crystal oscillator
consumption
—
—
—
7
µA
TSXOSCSU
CC T
Slow external crystal oscillator
start-up time
—
—
—
2(3)
s
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.
4.14
FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to
generate a fast system clock from the main oscillator driver.
Table 39.
FMPLL electrical characteristics
Symbol
C
Unit
Min
Typ
Max
—
4
—
64
MHz
FMPLL reference clock duty
cycle(3)
—
40
—
60
%
FMPLL output clock
frequency
—
16
—
120
MHz
fPLLIN
SR — FMPLL reference clock(3)
ΔPLLIN
SR —
fPLLOUT CC P
Value(2)
Conditions(1)
Parameter
120 + 2%(4) MHz
fCPU
SR — System clock frequency
—
—
—
fFREE
CC P Free-running frequency
—
20
—
150
MHz
tLOCK
CC P FMPLL lock time
Stable oscillator (fPLLIN = 16
MHz)
40
100
µs
ΔtLTJIT
CC — FMPLL long term jitter
fPLLIN = 40 MHz (resonator),
fPLLCLK @ 120 MHz, 4000
cycles
—
—
6
(for < 1ppm)
ns
CC C FMPLL consumption
TA = 25 °C
—
—
3
mA
IPLL
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. PLLIN clock retrieved directly from 4-40 MHz XOSC or 16 MIRC. Input characteristics are granted when oscillator is used
in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN.
4. fCPU 120 + 2% MHz can be achieved at 125 °C.
4.15
Fast internal RC oscillator (16 MHz) electrical characteristics
The device provides a 16 MHz main internal RC oscillator. This is used as the default clock
at the power-up of the device and can also be used as input to PLL.
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Electrical Characteristics
Table 40.
Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol
fFIRC
SPC564Bxx - SPC56ECxx
C
Parameter
Conditions
CC P Fast internal RC oscillator high
SR — frequency
Fast internal RC oscillator high
IFIRCRUN(3) CC T frequency current in running
mode
IFIRCPWD
Typ
Max
TA = 25 °C, trimmed
—
16
—
—
12
TA = 25 °C, trimmed
—
—
200
µA
TA = 25 °C
—
—
100
nA
TA = 55 °C
—
—
200
nA
TA = 125 °C
—
—
1
µA
sysclk = off
—
500
—
sysclk = 2 MHz
—
600
—
sysclk = 4 MHz
—
700
—
sysclk = 8 MHz
—
900
—
sysclk = 16 MHz
—
1250
—
VDD = 5.0 V ± 10%
—
—
2.0
VDD = 3.3 V ± 10%
—
—
5
VDD = 5.0 V ± 10%
—
—
2.0
VDD = 3.3 V ± 10%
—
—
5
+1
Fast internal RC oscillator high
IFIRCSTOP CC T frequency and system clock
TA = 25 °C
current in stop mode
C
TFIRCSU
CC
— Fast internal RC oscillator start— up time
—
ΔFIRCPRE
TA = 55 °C
TA = 125 °C
20
Fast internal RC oscillator
CC C precision after software
trimming of fFIRC
TA = 25 °C
−1
—
Fast internal RC oscillator
trimming step
TA = 25 °C
—
1.6
—
−5
—
ΔFIRCTRIM CC C
ΔFIRCVAR
Unit
Min
D
Fast internal RC oscillator high
CC D frequency current in power
down mode
D
Value(2)
(1)
Fast internal RC oscillator
variation over temperature and
CC C supply with respect to fFIRC at
TA = 25 °C in high-frequency
configuration
MHz
µA
µs
%
%
+5
%
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
4.16
Slow internal RC oscillator (128 kHz) electrical
characteristics
The device provides a 128 kHz low power internal RC oscillator. This can be used as the
reference clock for the RTC module.
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SPC564Bxx - SPC56ECxx
Table 41.
Symbol
fSIRC
Electrical Characteristics
Slow internal RC oscillator (128 kHz) electrical characteristics
C
Value(2)
(1)
Parameter
Conditions
CC P Slow internal RC oscillator low
SR — frequency
Unit
Min
Typ
Max
TA = 25 °C, trimmed
—
128
—
—
100
—
150
TA = 25 °C, trimmed
—
—
5
µA
µs
ISIRC(3)
CC C
Slow internal RC oscillator low
frequency current
TSIRCSU
CC P
Slow internal RC oscillator start-up
TA = 25 °C, VDD = 5.0 V ± 10%
time
—
8
12
ΔSIRCPRE
CC C
Slow internal RC oscillator precision
after software trimming of fSIRC
−2
—
+2
ΔSIRCTRIM
Slow internal RC oscillator trimming
CC C
step
ΔSIRCVAR
Slow internal RC oscillator variation
in temperature and supply with
CC C
High frequency configuration
respect to fSIRC at TA = 55 °C in high
frequency configuration
TA = 25 °C
kHz
%
—
—
2.7
—
−10
—
+10
%
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
4.17
ADC electrical characteristics
4.17.1
Introduction
The device provides two Successive Approximation Register (SAR) analog-to-digital
converters (10-bit and 12-bit).
Note:
Due to ADC limitations, the two ADCs cannot sample a shared channel at the same time
i.e., their sampling windows cannot overlap if a shared channel is selected. If this is done,
neither of the ADCs can guarantee their conversion accuracies.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Figure 15. ADC_0 characteristic and error definitions
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
5
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error OSE
Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is
considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin;
furthermore, it sources charge during the sampling phase, when the analog signal source is
a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the value of source
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Electrical Characteristics
impedance of the transducer or circuit supplying the analog signal to be measured. The filter
at the input pins must be designed taking into account the dynamic characteristics of the
input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: CS being substantially a switched capacitance, with a frequency
equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For
instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330
kΩ is obtained (REQ = 1 / (fc × CS), where fc represents the conversion rate at the
considered channel). To minimize the error induced by the voltage partitioning between this
resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external
circuit must be designed to respect the Equation 4:
Equation 4
R +R +R +R
+R
S
F
L
SW
AD
• --------------------------------------------------------------------------- < 1--- LSB
VA
R EQ
2
Equation 4 generates a constraint for external network design, in particular on resistive path.
Internal switch resistances (RSW and RAD) can be neglected with respect to external
resistances.
Figure 16. Input equivalent circuit (precise channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
VA
Filter
Current Limiter
RF
RL
CF
CP1
Channel
Selection
Sampling
RSW1
RAD
CP2
CS
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL Current Limiter Resistance
RSW1 Channel Selection Switch Impedance
RADSampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Figure 17. Input equivalent circuit (extended channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
Filter
RS
Current Limiter
RF
RL
CF
VA
CP1
Channel
Selection
Extended
Switch
Sampling
RSW1
RSW2
RAD
CP3
CP2
CS
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL Current Limiter Resistance
RSW Channel Selection Switch Impedance (two contributions RSW1 and RSW2)
RADSampling Switch Impedance
CP Pin Capacitance (three contributions, CP1, CP2 and CP3)
CS Sampling Capacitance
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the
equivalent circuit reported in Figure 16): A charge sharing phenomenon is installed when
the sampling phase is started (A/D switch close).
Figure 18. Transient behavior during sampling phase
Voltage Transient on CS
VCS
VA
VA2
ΔV < 0.5 LSB
1
2
τ1 < (RSW + RAD) CS << TS
VA1
τ2 = RL (CS + CP1 + CP2)
TS
t
In particular two different transient periods can be distinguished:
1.
A first and quick charge transfer from the internal capacitance CP1 and CP2 to the
sampling capacitance CS occurs (CS is supposed initially completely discharged):
considering a worst case (since the time constant in reality would be faster) in which
CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and
CS are in series, and the time constant is
Equation 5
τ = (R
+R
)
1
SW
AD
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CP • CS
• ---------------------C +C
P
S
SPC564Bxx - SPC56ECxx
Electrical Characteristics
Equation 5 can again be simplified considering only CS as an additional worst
condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time TS is always much
longer than the internal time constant:
Equation 6
τ 1 < ( R SW + R AD ) • C S « T S
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the
voltage VA1 on the capacitance according to Equation 7:
Equation 7
V A1 • ( C S + C P1 + C P2 ) = V A • ( C P1 + C P2 )
2.
A second charge transfer involves also CF (that is typically bigger than the on-chip
capacitance) through the resistance RL: again considering the worst case in which CP2
and CS were in parallel to CP1 (since the time constant in reality would be faster), the
time constant is:
Equation 8
τ 2 < R L • ( C S + C P1 + C P2 )
In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time TS, a constraints on
RL sizing is obtained:
Equation 9
10 • τ 2 = 10 • R L • ( C S + C P1 + C P2 ) < TS
Of course, RL shall be sized also according to the current limitation constraints, in
combination with RS (source impedance) and RF (filter resistance). Being CF
definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the
charge transfer transient) will be much higher than VA1. Equation 10 must be respected
(charge balance assuming now CS already charged at VA1):
Equation 10
VA2 • ( C S + C P1 + C P2 + C F ) = V A • C F + V A1 • ( C P1 + C P2 + C S )
The two transients above are not influenced by the voltage source that, due to the presence
of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on
CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with
respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Figure 19. Spectral representation of input signal
Analog source bandwidth (VA)
TC < 2 RFCF (Conversion rate vs. filter pole)
Noise
fF = f0 (Anti-aliasing filtering condition)
2 f0 < fC (Nyquist)
f0
f
Anti-aliasing filter (fF = RC filter pole)
fF
Sampled signal spectrum (fC = Conversion rate)
f0
f
fC
f
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of
the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at
least 2f0; it means that the constant time of the filter is greater than or at least equal to twice
the conversion period (TC). Again the conversion period TC is longer than the sampling time
TS, which is just a portion of it, even when fixed channel continuous conversion mode is
selected (fastest conversion rate at a specific channel): in conclusion it is evident that the
time constant of the filter RFCF is definitively much higher than the sampling time TS, so the
charge level on CS cannot be modified by the analog signal source during the time in which
the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce
the accuracy error due to the voltage drop on CS; from the two charge balance equations
above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS:
Equation 11
C P1 + C P2 + C F + C S
VA
----------- = -------------------------------------------------------V A2
C P1 + C P2 + C F
From this formula, in the worst case (when VA is maximum, that is for instance 5 V),
assuming to accept a maximum error of half a count, a constraint is evident on CF value:
Equation 12 ADC_0 (10-bit)
C F > 2048 • C S
Equation 13 ADC_1 (12-bit)
C F > 8192 • C S
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Electrical Characteristics
ADC electrical characteristics
Table 42.
ADC input leakage current
Value
Symbol C
Parameter
C
ILKG CC
C
C
Unit
TA = −40 °C
Input leakage current
P
Table 43.
Conditions
TA = 25 °C
TA = 105 °C
No current injection on adjacent pin
TA = 125 °C
Min
Typ
Max
—
1
—
—
1
—
—
8
200
—
45
400
nA
ADC conversion characteristics (10-bit ADC_0)
Symbol
C
Parameter
Value
Conditions(1)
Unit
Min
Typ
Max
Voltage on
VSS_HV_ADC0
VSS_ADC0 SR — (ADC_0 reference)
pin with respect to
ground (VSS_HV)(2)
—
−0.1
—
0.1
V
Voltage on
VDD_HV_ADC0 pin
VDD_ADC0 SR — (ADC_0 reference)
with respect to
ground (VSS_HV)
—
VDD_HV_A − 0.1
—
VDD_HV_A + 0.1
V
VAINx
SR —
Analog input
voltage(3)
—
VSS_ADC0 − 0.1
—
VDD_ADC0 + 0.1
V
fADC0
SR —
ADC_0 analog
frequency
—
6
—
32 + 2%
MHz
ADC_0 power up
delay
—
—
—
1.5
µs
fADC = 32 MHz
500
—
fADC = 32 MHz
0.625
—
fADC = 30 MHz
0.700
—
—
—
—
3
pF
tADC0_PU SR —
tADC0_S CC T Sample time(4)
tADC0_C CC P Conversion time(5),(6)
ns
µs
CS
ADC_0 input
CC D sampling
capacitance
CP1
CC D
ADC_0 input pin
capacitance 1
—
—
—
3
pF
CP2
CC D
ADC_0 input pin
capacitance 2
—
—
—
1
pF
CP3
CC D
ADC_0 input pin
capacitance 3
—
—
—
1
pF
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Electrical Characteristics
Table 43.
SPC564Bxx - SPC56ECxx
ADC conversion characteristics (10-bit ADC_0) (continued)
Symbol
C
Parameter
Value
Conditions(1)
Unit
Min
Typ
Max
RSW1
CC D
Internal resistance of
analog source
—
—
—
3
kΩ
RSW2
CC D
Internal resistance of
analog source
—
—
—
2
kΩ
RAD
CC D
Internal resistance of
analog source
—
—
—
2
kΩ
−5
—
5
IINJ
Current
injection on
one ADC_0
SR — Input current Injection
input, different
from the
converted one
VDD =
3.3 V ± 10%
VDD =
5.0 V ± 10%
mA
−5
—
5
| INL |
CC T
Absolute value for
No overload
integral non-linearity
—
0.5
1.5
LSB
| DNL |
CC T
Absolute differential
non-linearity
—
0.5
1.0
LSB
| OFS |
CC T Absolute offset error
—
—
0.5
—
LSB
| GNE |
CC T Absolute gain error
—
—
0.6
—
LSB
−2
0.6
2
TUEP
Without current injection
P Total unadjusted
error(7) for precise
CC
T channels, input only With current injection
pins
T Total unadjusted
Without current injection
error(7) for extended
T channel
With current injection
−3
TUEX
CC
No overload
3
−3
−4
1
3
4
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. Analog and digital VSS_HV must be common (to be tied together externally).
3. VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
4. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the end of
the sample time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tADC0_S depend on programming.
5. Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay.
6. Refer to ADC conversion table for detailed calculations.
7. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
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LSB
LSB
SPC564Bxx - SPC56ECxx
Electrical Characteristics
Figure 20. ADC_1 characteristic and error definitions
Offset Error OSE
Gain Error GE
4095
4094
4093
4092
4091
1 LSB ideal = AVDD / 4096
4090
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
5
(5)
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)
Offset Error OSE
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Electrical Characteristics
Table 44.
SPC564Bxx - SPC56ECxx
Conversion characteristics (12-bit ADC_1)
Symbol
Value
Conditions(1)
Parameter
Unit
Min
SR
Voltage on
VSS_HV_ADC1
(ADC_1 reference) —
pin with respect to
ground (VSS_HV)(2)
VDD_ADC13
SR
Voltage on
VDD_HV_ADC1
pin (ADC_1
reference) with
respect to ground
(VSS_HV)
VAINx(3),(4)
SR
fADC1
tADC1_PU
VSS_ADC1
tADC1_S
Typ
Max
−0.1
0.1
V
—
VDD_HV_A − 0.1
VDD_HV_A + 0.1
V
Analog input
voltage(5)
—
VSS_ADC1 − 0.1
VDD_ADC1 + 0.1
V
SR
ADC_1 analog
frequency
—
8 + 2%
32 + 2%
MHz
SR
ADC_1 power up
delay
—
Sample time(6)
VDD=5.0 V
—
CC
1.5
µs
440
ns
Sample time(6)
VDD=3.3 V
—
530
fADC1 = 32 MHz
2
fADC 1= 30 MHz
2.1
fADC 1= 20 MHz
3
fADC1 = 15 MHz
3.01
Conversion time(7),
(8)
VDD=5.0 V
Conversion time(7),
(6)
tADC1_C
CC
VDD =5.0 V
Conversion time(7),
(6)
µs
VDD=3.3 V
Conversion time(7),
(6)
VDD =3.3 V
CS
CC
ADC_1 input
sampling
capacitance
—
5
pF
CP1
CC
ADC_1 input pin
capacitance 1
—
3
pF
CP2
CC
ADC_1 input pin
capacitance 2
—
1
pF
CP3
CC
ADC_1 input pin
capacitance 3
—
1.5
pF
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SPC564Bxx - SPC56ECxx
Table 44.
Electrical Characteristics
Conversion characteristics (12-bit ADC_1) (continued)
Symbol
Parameter
Value
Conditions(1)
Unit
Min
Typ
Max
RSW1
CC
Internal resistance
of analog source
—
1
kΩ
RSW2
CC
Internal resistance
of analog source
—
2
kΩ
RAD
CC
Internal resistance
of analog source
—
0.3
kΩ
IINJ
SR
Input current
Injection
Current
injection
on one
ADC_1
input,
different
from the
converted
one
VDD = 3.3
V ± 10%
−5
—
5
VDD = 5.0
V ± 10%
−5
—
5
mA
INLP
CC
Absolute Integral
non-linearityPrecise channels
No overload
1
3
LSB
INLS
CC
Absolute Integral
non-linearityStandard channels
No overload
1.5
5
LSB
DNL
CC
Absolute
Differential nonlinearity
No overload
0.5
1
LSB
OFS
CC
Absolute Offset
error
—
2
LSB
GNE
CC
Absolute Gain
error
—
2
LSB
CC
Total Unadjusted
Error for precise
channels, input
only pins
(9)
TUEP
TUES(9)
CC
Total Unadjusted
Error for standard
channel
Without current
injection
−6
6
With current injection
−8
8
Without current
injection
−10
10
LSB
With current injection
−12
12
LSB
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. Analog and digital VSS_HV must be common (to be tied together externally).
3. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be
within ±100 mV of VDD_HV_B when these channels are used for ADC_1.
4. VDD_HV_ADC1 can operate at 5V condition while VDD_HV_B can operate at 3.3V provided that ADC_1 channels coming
from VDD_HV_B domain are limited in max swing as VDD_HV_B.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
5. VAINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
6. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end of
the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tADC1_S depend on programming.
7. Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay.
8. Refer to ADC conversion table for detailed calculations.
9. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
4.18
Fast Ethernet Controller
MII signals use CMOS signal levels compatible with devices operating at 3.3 V. Signals are
not TTL compatible. They follow the CMOS electrical characteristics.
4.18.1
MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%.
There is no minimum frequency requirement. In addition, the system clock frequency must
exceed four times the RX_CLK frequency in 2:1 mode and two times the RX_CLK frequency
in 1:1 mode.
Table 45.
MII Receive Signal Timing
Spec
Characteristic
Min
Max
Unit
M1
RXD[3:0], RX_DV, RX_ER to
RX_CLK setup
5
—
ns
M2
RX_CLK to RXD[3:0], RX_DV,
RX_ER hold
5
—
ns
M3
RX_CLK pulse width high
35%
65%
RX_CLK period
M4
RX_CLK pulse width low
35%
65%
RX_CLK period
Figure 21. MII receive signal timing diagram
M3
RX_CLK (input)
M4
RXD[3:0] (inputs)
RX_DV
RX_ER
M1
4.18.2
M2
MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%.
There is no minimum frequency requirement. In addition, the system clock frequency must
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Electrical Characteristics
exceed four times the TX_CLK frequency in 2:1 mode and two times the TX_CLK frequency
in 1:1 mode.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from
either the rising or falling edge of TX_CLK, and the timing is the same in either case. This
options allows the use of non-compliant MII PHYs.
Refer to the Fast Ethernet Controller (FEC) chapter of the SPC564B74 and SPC56EC74
Reference Manual for details of this option and how to enable it.
MII transmit signal timing(1)
Table 46.
Spec
Characteristic
Min
Max
Unit
M5
TX_CLK to TXD[3:0],
TX_EN, TX_ER invalid
5
—
ns
M6
TX_CLK to TXD[3:0],
TX_EN, TX_ER valid
—
25
ns
M7
TX_CLK pulse width high
35%
65%
TX_CLK period
M8
TX_CLK pulse width low
35%
65%
TX_CLK period
1. Output pads configured with SRE = 0b11.
Figure 22. MII transmit signal timing diagram
M7
TX_CLK (input)
M5
M8
TXD[3:0] (outputs)
TX_EN
TX_ER
M6
4.18.3
MII Async Inputs Signal Timing (CRS and COL)
Table 47.
MII Async Inputs Signal Timing(1)
Spec
Characteristic
Min
Max
Unit
M9
CRS, COL minimum pulse width
1.5
—
TX_CLK period
1. Output pads configured with SRE = 0b11.
Figure 23. MII async inputs timing diagram
CRS, COL
M9
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Electrical Characteristics
4.18.4
SPC564Bxx - SPC56ECxx
MII Serial Management Channel Timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
MII serial management channel timing(1)
Table 48.
Spec
Characteristic
Min
Max
Unit
M10
MDC falling edge to
MDIO output invalid
(minimum
propagation delay)
0
—
ns
M11
MDC falling edge to
MDIO output valid
(max prop delay)
—
25
ns
M12
MDIO (input) to MDC
rising edge setup
28
—
ns
M13
MDIO (input) to MDC
rising edge hold
0
—
ns
M14
MDC pulse width
high
40%
60%
MDC period
M15
MDC pulse width low
40%
60%
MDC period
1. Output pads configured with SRE = 0b11.
Figure 24.
MII serial management channel timing diagram
M14
M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
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SPC564Bxx - SPC56ECxx
Electrical Characteristics
4.19
On-chip peripherals
4.19.1
Current consumption
Table 49.
On-chip peripherals current consumption(1)
Value(2)
Symbol
C
Parameter
Unit
Conditions
Min
500
Kbps
IDD_HV_A(CAN)
CAN
(FlexCAN)
CC D supply
current on
VDD_HV_A
eMIOS
supply
IDD_HV_A(eMIOS) CC D
current on
VDD_HV_A
IDD_HV_A(SCI)
SCI (LINFlex)
supply
CC D
current on
VDD_HV_A
125
Kbps
Total (static +
dynamic)
consumption:
FlexCAN in loopback mode
XTAL@8 MHz used
as CAN engine clock
source
Message sending
period is 580 µs
Static consumption:
eMIOS channel OFF
Global prescaler enabled
Dynamic consumption:
It does not change varying
the frequency (0.003 mA)
Total (static + dynamic)
consumption:
LIN mode
Baudrate: 20 Kbps
Ballast static consumption
(only clocked)
IDD_HV_A(SPI)
SPI (DSPI)
supply
CC D
current on
VDD_HV_A
Ballast dynamic consumption
(continuous communication):
Baudrate: 2 Mbit
Trasmission every 8 µs
Frame: 16 bits
VDD =
5.5 V
IDD_HV_A(ADC)
ADC supply
CC D current on
VDD_HV_A
VDD =
5.5 V
Ballast static
consumption (no
conversion)
Ballast dynamic
consumption
(continuous
conversion)
Doc ID 17478 Rev 4
Typ
Max
7.652 × fperiph + 84.73
8.0743 × fperiph + 26.757
28.7 × fperiph
3
µA
4.7804 × fperiph + 30.946
1
16.3 × fperiph
0.0409 × fperiph
mA
0.0049 × fperiph
95/118
Electrical Characteristics
Table 49.
SPC564Bxx - SPC56ECxx
On-chip peripherals current consumption(1) (continued)
Value(2)
Symbol
C
Parameter
ADC_0
supply
VDD =
IDD_HV_ADC0 CC D current on
5.5 V
VDD_HV_ADC0
VDD =
5.5 V
ADC_1
supply
IDD_HV_ADC1 CC D current on
VDD_HV_ADC1 V =
DD
5.5 V
IDD_HV(FLASH)
IDD_HV(PLL)
Unit
Conditions
CFlash +
DFlash
CC D supply
current on
VDD_HV_ADC
VDD =
5.5 V
PLL supply
CC D current on
VDD_HV
VDD =
5.5 V
Min
Typ
Max
Analog static
consumption (no
conversion)
—
200
—
µA
Analog dynamic
consumption
(continuous
conversion)
—
4
—
mA
Analog static
consumption (no
conversion)
300 × fperiph
µA
Analog dynamic
consumption
(continuous
conversion)
6
mA
—
13.25
mA
—
0.0031 × fperiph
1. Operating conditions: TA = 25 °C, fperiph = 8 MHz to 120 MHz.
2. fperiph is in absolute value.
4.19.2
DSPI characteristics
Table 50.
DSPI timing
Spec
Characteristic
Symbol
Unit
Min
Max
tSCK
Refer
note(1)
—
ns
1
DSPI Cycle Time
—
Internal delay between pad associated to SCK and pad
associated to CSn in master mode for CSn1->0
ΔtCSC
—
115
ns
—
Internal delay between pad associated to SCK and pad
associated to CSn in master mode for CSn1->1
ΔtASC
15
—
ns
2
CS to SCK Delay(2)
tCSC
7
—
ns
3
After SCK Delay(3)
tASC
15
—
ns
4
SCK Duty Cycle
tSDC
0.4 × tSCK
0.6 × tSCK
ns
—
Slave Setup Time
(SS active to SCK setup time)
tSUSS
5
—
ns
96/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Table 50.
Electrical Characteristics
DSPI timing (continued)
Spec
Characteristic
Symbol
Unit
Min
Max
—
Slave Hold Time
(SS active to SCK hold time)
tHSS
10
—
ns
5
Slave Access Time
(SS active to SOUT valid)(4)
tA
—
42
ns
6
Slave SOUT Disable Time
(SS inactive to SOUT High-Z or invalid)
tDIS
—
25
ns
7
CSx to PCSS time
tPCSC
0
—
ns
8
PCSS to PCSx time
tPASC
0
—
ns
9
Data Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)(5)
Master (MTFE = 1, CPHA = 1)
tSUI
36
5
36
36
—
—
—
—
ns
ns
ns
ns
10
Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)(5)
Master (MTFE = 1, CPHA = 1)
tHI
0
4
0
0
—
—
—
—
ns
ns
ns
ns
11
Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
—
—
—
—
12
37
12
12
ns
ns
ns
ns
12
Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
0(6)
9.5
0(7)
0(8)
—
—
—
—
ns
ns
ns
ns
tSUO
tHO
1. This value of this parameter is dependent upon the external device delays and the other parameters mentioned in this
table.
2. The maximum value is programmable in DSPI_CTARn [PSSCK] and DSPI_CTARn [CSSCK]. For SPC564B74 and
SPC56EC74, the spec value of tCSC will be attained only if TDSPI x PSSCK x CSSCK > ΔtCSC .
3. The maximum value is programmable in DSPI_CTARn [PASC] and DSPI_CTARn [ASC]. For SPC564B74 and
SPC56EC74, the spec value of tASC will be attained only if TDSPI x PASC x ASC > ΔtASC.
4. The parameter value is obtained from tSUSS and tSUO for slave.
5. This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b00.
6. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 0) is −2 ns.
7. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 0) is −2 n.
8. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 1) is −2 ns.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Figure 25. DSPI classic SPI timing–master, CPHA = 0
2
3
CSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
SIN
First Data
Last Data
Data
12
SOUT
First Data
11
Data
Last Data
Note: Numbers shown reference Table 50.
Figure 26. DSPI classic SPI timing–master, CPHA = 1
CSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
SIN
Data
First Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Note: Numbers shown reference Table 50.
98/118
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SPC564Bxx - SPC56ECxx
Electrical Characteristics
Figure 27. DSPI classic SPI timing–slave, CPHA = 0
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
First Data
SOUT
9
6
Data
Last Data
Data
Last Data
10
First Data
SIN
11
12
Note: Numbers shown reference Table 50.
Figure 28. DSPI classic SPI timing–slave, CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 50.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Figure 29. DSPI modified transfer format timing–master, CPHA = 0
3
CSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
SIN
10
First Data
Last Data
Data
12
SOUT
11
First Data
Last Data
Data
Note: Numbers shown reference Table 50.
Figure 30. DSPI modified transfer format timing–master, CPHA = 1
CSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
First Data
Data
12
SOUT
First Data
Data
Last Data
11
Last Data
Note: Numbers shown reference Table 50.
100/118
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Electrical Characteristics
Figure 31. DSPI modified transfer format timing–slave, CPHA = 0
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
First Data
SOUT
Data
6
Last Data
10
9
Data
First Data
SIN
12
11
5
Last Data
Note: Numbers shown reference Table 50.
Figure 32. DSPI modified transfer format timing–slave, CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
12
First Data
SOUT
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Note: Numbers shown reference Table 50.
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Figure 33. DSPI PCS strobe (PCSS) timing
8
7
PCSS
CSx
Note: Numbers shown reference Table 50.
4.19.3
Nexus characteristics
Table 51.
Nexus debug port timing(1)
Spec
Characteristic
Symbol
Min
Max
Unit
1
MCKO Cycle
Time(2)
tMCYC
16.3
—
ns
2
MCKO Duty
Cycle
tMDC
40
60
%
3
MCKO Low to
MDO, MSEO,
EVTO Data
Valid(3)
tMDOV
–0.1
0.25
tMCYC
4
EVTI Pulse Width
tEVTIPW
4.0
—
tTCYC
5
EVTO Pulse
Width
tEVTOPW
1
6
TCK Cycle
Time(4)
tTCYC
40
—
ns
7
TCK Duty Cycle
tTDC
40
60
%
8
TDI, TMS Data
Setup Time
tNTDIS, tNTMSS
8
—
ns
9
TDI, TMS Data
Hold Time
tNTDIH, tNTMSH
5
—
ns
10
TCK Low to TDO
Data Valid
tJOV
0
25
ns
tMCYC
1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured
from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDDE = 4.0 – 5.5 V, TA = TL to TH, and
CL = 30 pF with SRC = 0b11.
2. MCKO can run up to 1/2 of full system frequency. It can also run at system frequency when it is <60 MHz.
3. MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
4. The system clock frequency needs to be three times faster than the TCK frequency.
102/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Electrical Characteristics
Figure 34. Nexus output timing
1
2
MCKO
3
MDO
MSEO
EVTO
Output Data Valid
5
EVTI
4
Doc ID 17478 Rev 4
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Electrical Characteristics
SPC564Bxx - SPC56ECxx
Figure 35. Nexus TDI, TMS, TDO timing
6
7
TCK
8
9
TMS, TDI
10
TDO
4.19.4
JTAG characteristics
Table 52.
JTAG characteristics
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tJCYC
CC
D TCK cycle time
64
—
—
ns
2
tTDIS
CC
D TDI setup time
10
—
—
ns
3
tTDIH
CC
D TDI hold time
5
—
—
ns
4
tTMSS
CC
D TMS setup time
10
—
—
ns
5
tTMSH
CC
D TMS hold time
5
—
—
ns
6
tTDOV
CC
D TCK low to TDO valid
—
—
33
ns
104/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Table 52.
Electrical Characteristics
JTAG characteristics (continued)
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
7
tTDOI
CC
D TCK low to TDO invalid
6
—
—
ns
—
tTDC
CC
D TCK Duty Cycle
40
—
60
%
—
tTCKRISE
CC
D TCK Rise and Fall Times
—
—
3
ns
Figure 36. Timing diagram - JTAG boundary scan
TCK
2/4
DATA INPUTS
3/5
INPUT DATA VALID
6
DATA OUTPUTS
OUTPUT DATA VALID
7
DATA OUTPUTS
Note: Numbers shown reference Table 52.
Doc ID 17478 Rev 4
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Package characteristics
SPC564Bxx - SPC56ECxx
5
Package characteristics
5.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
106/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Package characteristics
5.2
Package mechanical data
5.2.1
LQFP176 package mechanical drawing
Figure 37. LQFP176 package mechanical drawing
Doc ID 17478 Rev 4
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Package characteristics
Table 53.
SPC564Bxx - SPC56ECxx
LQFP176 mechanical data(1)
inches(2)
mm
Symbol
Min
Typ
Max
Min
Typ
Max
A
1.400
1.600
A1
0.050
0.150
0.002
A2
1.350
1.450
0.053
0.057
b
0.170
0.270
0.007
0.011
C
0.090
0.200
0.004
0.008
D
23.900
24.100
0.941
0.949
E
23.900
24.100
0.941
0.949
e
0.063
0.500
0.020
HD
25.900
26.100
1.020
1.028
HE
25.900
26.100
1.020
1.028
L(3)
0.450
0.750
0.018
0.030
L1
1.000
0.039
ZD
1.250
0.049
ZE
1.250
0.049
q
0°
7°
0°
7°
Tolerance
mm
inches
ccc
0.080
0.0031
1. Controlling dimension: millimeter
2. Values in inches are converted from mm and rounded to 4 decimal digits.
3. L dimension is measured at gauge plane at 0.25 mm above the seating plane
108/118
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
5.2.2
Package characteristics
LQFP208 package mechanical drawing
Figure 38. LQFP208 mechanical drawing
Note: Exact shape of each corner is optional.
Table 54.
LQFP208 mechanical data
mm
Ref
Min
A
A1
Typ
Max
1.6
0.05
Doc ID 17478 Rev 4
0.15
109/118
Package characteristics
Table 54.
SPC564Bxx - SPC56ECxx
LQFP208 mechanical data (continued)
mm
Ref
Min
Typ
Max
A2
1.35
1.40
1.45
b
0.17
0.22
0.27
c
0.09
D
29.8
30
30.2
D1
27.8
28
28.2
D3
25.5
e
0.5
E
29.8
30
30.2
E1
27.8
28
28.2
E3
L
25.5
0.45
L1
K
0.6
0.75
1
0
ccc
110/118
0.2
3.5
7.0
0.08
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
5.2.3
Package characteristics
LBGA256 package mechanical drawing
Figure 39. LBGA256 mechanical drawing
Doc ID 17478 Rev 4
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Package characteristics
Table 55.
SPC564Bxx - SPC56ECxx
LBGA256 mechanical data
mm
Ref
Min
A
1.210
A1
0.300
A2
Typ
1.700
0.300
A4
0.800
b
0.400
0.500
0.600
D
16.800
17.000
17.200
D1
E
15.000
16.800
E1
112/118
17.000
17.200
15.000
e
0.900
1.000
1.100
Z
0.750
1.000
1.250
ddd
Note:
Max
0.200
The package is designed according to the Jedec standard No 95-1 Section 14 dedicated to
Ball Grid Array Package Design Guide.
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
6
Ordering information
Ordering information
Figure 40. Ordering information scheme
Example code:
SPC56
Product identifier
4
Core
C
Family
L7
74
C
8
E
0
Y
Memory Package Temperature CPU Frequency EEPROM Options Conditioning
Y = Tray
X = Tape and Reel
0 = No option
E = Ethernet
C = CSE + Ethernet
0 = NO EEPROM
E = EEPROM
8 = 80 MHz
9 = 120 MHz
B = –40 to 105 °C
C = –40 to 125 °C
L7 = LQFP176
L8 = LQFP208
B3 = LBGA256
74 = 3 MB
70 = 2 MB
64 = 1.5 MB
B = Body
C = Gateway
4 = e200z4d
E = e200z4d + e200
z0h
SPC56 = Power
Architecture in
90 nm
Doc ID 17478 Rev 4
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Abbreviations
SPC564Bxx - SPC56ECxx
Appendix A
Abbreviations
Table 56 lists abbreviations used but not defined elsewhere in this document.
Table 56.
Abbreviations
Abbreviation
CS
114/118
Meaning
Chip select
EVTO
Event out
MCKO
Message clock out
MDO
Message data out
MSEO
Message start/end out
MTFE
Modified timing format enable
SCK
Serial communications clock
SOUT
Serial data out
TBD
To be defined
TCK
Test clock input
TDI
Test data input
TDO
Test data output
TMS
Test mode select
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Revision history
Revision history
Table summarizes revisions to this document
.
Revision history
Date
Revision
01-Jun-2010
1
Changes
Initial Release
–
–
–
–
17-Dec-2010
2
Editing and formatting updates throughout the document.
Updated Voltage regulator capacitance connection figure.
Added a new sub-section “VDD_BV Options”
Program and erase specifications:
Updated Tdwprogram TYP to 22 us
Updated T128Kpperase Max to 5000 ms
Added tESUS parameter
– Added recommendation in the Voltage regulator electrical characteristics section.
– Added Crystal description table in Fast external crystal oscillator (4 to 140 MHz)
electrical characteristics section and corrected the cross-reference to the same.
– Added new sections - Pad types, System pins and functional ports
– Updated TYP numbers in the Flash program and erase specifications table
– Added a new table: Program and erase specifications (Data Flash)
– Flash read access timing table: Added Data flash memory numbers
– Flash power supply DC electrical characteristics table: Updated IDFREAD and
IDFMOD values for Data flash, Removed IDFLPW parameter
– Updated feature list.
– SPC564Bxx and SPC56ECxx family comparison table: Updated ADC channels
and added ADC footnotes.
– SPC564Bxx and SPC56ECxx block diagram: Updated ADC channels and added
legends.
– SPC564Bxx and SPC56ECxx series block summary: Added new blocks.
– Functional Port Pin Descriptions table: Added OSC32k_XTAL and
OSC32k_EXTAL function at PB8 and PB9 port pins.
– Electrical Characteristics: Replaced VSS with VSS_HV throughout the section.
– Absolute maximum ratings, Recommended operating conditions (3.3 V) and
Recommended operating conditions (5.0 V) tables: VRC_CTRL min is updated to
"0".
– Recommended operating conditions (3.3 V) and Recommended operating
conditions (5.0 V) tables: Clarified VIN parameter, clarified footnote 2 in both
tables.
– LQFP thermal characteristics section: Added numbers for LQFP packages.
– Low voltage power domain electrical characteristics table: Clarified footnotes
based upon review comments.
– Code flash memory—Program and erase specifications: Updated tESRT to
20 ms.
– ADC electrical characteristics section: Replace ADC0 with ADC_0 and ADC1 with
ADC_1 throughout the document.
DSPI characteristics section: Replaced PCSx with CSx in all figures and tables.
Doc ID 17478 Rev 4
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Revision history
SPC564Bxx - SPC56ECxx
Revision history (continued)
Date
28-Apr-2011
116/118
Revision
3
Changes
– Replaced VIL min from –0.4 V to –0.3 V in the following tables:
- I/O input DC electrical characteristics
- Reset electrical characteristics
- Fast external crystal oscillator (4 to 40 MHz) electrical characteristics
– Updated Crystal oscillator and resonator connection scheme figure
– Specified NPN transistor as the recommended BCP68 transistor throughout the
document
– Code and Data flash memory—Program and erase specifications tables:
Renamed the parameter tESUS to Teslat
– Revised the footnotes in the “Functional port pin descriptions” table.
– In the “System pin descriptions” table, added a footnote to the A pads regarding
not using IBE.
For ports PB[12–15], changed ANX to ADC0_X.
– Revised the presentation of the ADC functions on the following ports:
PB[4–7]
PD[0–11]
– ADC conversion characteristics (10-bit ADC_0) table and Conversion
characteristics (12-bit ADC_1) table- Updated footnote 5 and 7 respectively for the
definition of the conversion time.
– Data flash memory—Program and erase specifications: Updated Twprogram to 500
µs and T16Kpperase to 500 µs. Corrected Teslat classsification from “C” to “D”.
– Code flash memory—Program and erase specifications: Corrected Teslat
classification from “C” to “D”.
– Flash Start-up time/Switch-off time: Changed TFLARSTEXIT classification from “C”
to “D”.
– Functional port pin description: Added a footnote at the PB [9] port pin.
– Absolute maximum ratings table: Added footnote 1.
– Low voltage power domain electrical characteristics table: Updated IDDHALT,
IDDSTOP, IDDSTBY3, IDDSTDBY2, IDDSTDBY1.
– Updated commercial product code structure.
– Slow external crystal oscillator (32 kHz) electrical characteristics table: Updated
gmSXOSC, VSXOSC, ISXOSCBIAS and ISXOSC.
– FMPLL electrical characteristics table: Updated ΔtLTJIT.
– Fast internal RC oscillator (16 MHz) electrical characteristics table: Updated
TFIRCSU and IFIRCPWD.
– MII serial management channel timing table: Updated M12
– JTAG characteristics table: Updated tTDOV.
– Low voltage monitor electrical characteristics table: Updated VLVDHV3H,
VLVDHV3L, VLVDHV5H, VLVDHV5L.
– DSPI electricals table: Updated spec 1, 5, 6. Updated footnote 2 and 3. Added
ΔtCSC, ΔtASC, tSUSS, tHSS.
– IO consumption table: Updated all parameter values.
– DSPI electricals: Updated ΔtCSC max to 115 ns.
– Low voltage power domain electrical characteristics table: Added footnote 9.
– ADC electrical characteristics: Added 2 notes above 10-bit and 12-bit conversion
tables.
Doc ID 17478 Rev 4
SPC564Bxx - SPC56ECxx
Revision history
Revision history (continued)
Date
01-Dec-2011
Revision
Changes
4
– Interchanged the denominator with numerator in Equation 11 of Input impedance
and ADC accuracy section
– Removed the note (All ADC conversion characteristics described in the table
below are applicable only for the precision channels. The data for semi-precision
and extended channels is awaited and same will be subsequently updated in later
revs.) in the ADC electrical characteristics section.
– Table 49 (On-chip peripherals current consumption). Replaced IDD_HV_ADC
with IDD_HV_ADC0 and IDD_HV_ADC1 values as per ADC specs
– In Table 43, the minimum sample time of ADC0 changed to 500 at 32 MHz
– In Table 43, removed the entry for sample time at 30 MHz
– In Table 44, changed TUEX to TUES and INLX to INLS (Extended channels are
not supported by the device. So, changed to standard channel.)
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SPC564Bxx - SPC56ECxx
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