MIXED SIGNAL MICROCONTROLLER MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1

MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
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MIXED SIGNAL MICROCONTROLLER
FEATURES
1
•
•
•
•
•
•
Low Supply Voltage Range: 1.8 V to 3.6 V
Ultra-Low Power Consumption
– Active Mode: 220 µA at 1 MHz, 2.2 V
– Standby Mode: 0.5 µA
– Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, up to 12-MHz System
Clock
Basic Clock Module Configurations
– Internal Frequencies up to 12 MHz With
Two Calibrated Frequencies
– Internal Very-Low-Power Low-Frequency
(LF) Oscillator
– High-Frequency (HF) Crystal up to 16 MHz
– Resonator
– External Digital Clock Source
•
•
•
•
•
•
•
•
•
•
Up to Three 24-Bit Sigma-Delta
Analog-to-Digital (A/D) Converters With
Differential PGA Inputs
16-Bit Timer_A With Three Capture/Compare
Registers
Serial Communication Interface (USART),
Asynchronous UART or Synchronous SPI
Selectable by Software
16-Bit Hardware Multiplier
Brownout Detector
Supply Voltage Supervisor/Monitor with
Programmable Level Detection
Serial Onboard Programming, No External
Programming Voltage Needed Programmable
Code Protection by Security Fuse
On-Chip Emulation Module
Family Members are Summarized in Table 1.
For Complete Module Descriptions, See the
MSP430x2xx Family User's Guide, Literature
Number SLAU144
DESCRIPTION
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430AFE2x3 devices are ultra-low-power mixed signal microcontrollers integrating three independent
24-bit sigma-delta A/D converters, one 16-bit timer, one 16-bit hardware multiplier, USART communication
interface, watchdog timer, and 11 I/O pins.
The MSP430AFE2x2 devices are identical to the MSP430AFE2x3, except that there are only two 24-bit
sigma-delta A/D converters integrated.
The MSP430AFE2x1 devices are identical to the MSP430AFE2x3, except that there is only one 24-bit
sigma-delta A/D converter integrated.
Available family members are summarized in Table 1.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
Table 1. Family Members (1)
Device
Flash
(KB)
SRAM
(Byte)
EEM
SD24_A
Converters
16-Bit
MPY
Timer_A (2)
USART
(UART/
SPI)
Clocks
I/O
Package
Type (3)
MSP430AFE253IPW
16
512
1
3
1
3
1
HF, DCO,
VLO
11
24-TSSOP
MSP430AFE233IPW
8
512
1
3
1
3
1
HF, DCO,
VLO
11
24-TSSOP
MSP430AFE223IPW
4
256
1
3
1
3
1
HF, DCO,
VLO
11
24-TSSOP
MSP430AFE252IPW
16
512
1
2
1
3
1
HF, DCO,
VLO
11
24-TSSOP
MSP430AFE232IPW
8
512
1
2
1
3
1
HF, DCO,
VLO
11
24-TSSOP
MSP430AFE222IPW
4
256
1
2
1
3
1
HF, DCO,
VLO
11
24-TSSOP
MSP430AFE251IPW
16
512
1
1
1
3
1
HF, DCO,
VLO
11
24-TSSOP
MSP430AFE231IPW
8
512
1
1
1
3
1
HF, DCO,
VLO
11
24-TSSOP
MSP430AFE221IPW
4
256
1
1
1
3
1
HF, DCO,
VLO
11
24-TSSOP
(1)
(2)
(3)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Development Tool Support
All MSP430™ microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging
and programming through easy-to-use development tools. Recommended hardware options include:
• Debugging and Programming Interface
– MSP-FET430UIF (USB)
– MSP-FET430PIF (Parallel Port)
• Debugging and Programming Interface with Target Board
– MSP-TS430PW24
• Production Programmer
– MSP-GANG430
2
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
Functional Block Diagram
XT2IN XT2OUT
DVCC DVSS
AVCC AVSS
ACLK
Basic
Clock
System+
SMCLK
MCLK
12MHz
CPU
MAB
incl. 16
Registers
MDB
16KB
8KB
4KB
512B
512B
256B
Flash
RAM
BOR
Watchdog
WDT+
15/16-bit
P1.x
8
Hardware
Multiplier
(16x16)
P2.x
3
Port P1
Port P2
8 I/O
Interrupt
capability
Pull-up/
down
resistors
3 I/O
Interrupt
capability
Pull-up/
down
resistors
SD24_A
(w/o BUF)
Timer_A3
USART0
3 Converter
2 Converter
1 Converter
3 CC
Registers
UART
or SPI
Function
MPY,
MPYS,
MAC,
MACS
Emulation
2BP
JTAG
Interface
SVS/SVM
Spy-Bi
Wire
RST/NMI
Pin Designation, MSP430AFE2x3IPW
A0.0+
1
24
P2.0/STE0/TA0/TDI/TCLK
A0.0-
2
23
P1.7/UCLK0/TA1/TDO/TDI
A1.0+
3
22
P1.6/SOMI0/TA2/TCK
A1.0-
4
21
P1.5/SIMO0/SVSOUT/TMS
AVCC
5
20
P1.4/URXD0/SD2DO
AVSS
6
19
P1.3/UTXD0/SD1DO
VREF
7
18
P1.2/TA0/SD0DO
A2.0+
8
17
P1.1/TA1/SDCLK
A2.0-
9
16
DVCC
MSP430AFE2x3
TEST/SBWTCK
10
15
P2.7/XT2OUT
RST/NMI/SBWTDIO
11
14
P2.6/XT2IN
P1.0/SVSIN/TACLK/SMCLK/TA2
12
13
DVSS
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
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Pin Designation, MSP430AFE2x2IPW
A0.0+
1
24
P2.0/STE0/TA0/TDI/TCLK
A0.0-
2
23
P1.7/UCLK0/TA1/TDO/TDI
A1.0+
3
22
P1.6/SOMI0/TA2/TCK
A1.0-
4
21
P1.5/SIMO0/SVSOUT/TMS
AVCC
5
20
P1.4/URXD0
AVSS
6
19
P1.3/UTXD0/SD1DO
VREF
7
18
P1.2/TA0/SD0DO
NC
8
17
P1.1/TA1/SDCLK
NC
9
16
DVCC
TEST/SBWTCK
10
15
P2.7/XT2OUT
RST/NMI/SBWTDIO
11
14
P2.6/XT2IN
P1.0/SVSIN/TACLK/SMCLK/TA2
12
13
DVSS
A.
MSP430AFE2x2
Connect NC pins to analog ground (AVSS)
Pin Designation, MSP430AFE2x1IPW
1
24
P2.0/STE0/TA0/TDI/TCLK
A0.0-
2
23
P1.7/UCLK0/TA1/TDO/TDI
NC
3
22
P1.6/SOMI0/TA2/TCK
NC
4
21
P1.5/SIMO0/SVSOUT/TMS
AVCC
5
20
P1.4/URXD0
AVSS
6
19
P1.3/UTXD0
VREF
7
18
P1.2/TA0/SD0DO
NC
8
17
P1.1/TA1/SDCLK
NC
9
16
DVCC
TEST/SBWTCK
MSP430AFE2x1
10
15
P2.7/XT2OUT
RST/NMI/SBWTDIO
11
14
P2.6/XT2IN
P1.0/SVSIN/TACLK/SMCLK/TA2
12
13
DVSS
B.
4
A0.0+
Connect NC pins to analog ground (AVSS)
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MSP430AFE2x2
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SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
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Table 2. Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
A0.0+
1
I
SD24_A positive analog input A0.0 (1)
A0.0-
2
I
SD24_A negative analog input A0.0 (1)
A1.0+
3
I
SD24_A positive analog input A1.0 (not available on MSP430AFE2x1) (1)
A1.0-
4
I
SD24_A negative analog input A1.0 (not available on MSP430AFE2x1) (1)
AVCC
5
Analog supply voltage, positive terminal. Must not power up prior to DVCC.
AVSS
6
Analog supply voltage, negative terminal
VREF
7
I/O
A2.0+
8
I
SD24_A positive analog input A2.0 (not available on MSP430AFE2x2 and
MSP430AFE2x1) (1)
A2.0-
9
I
SD24_A negative analog input A2.0 (not available on MSP430AFE2x2 and
MSP430AFE2x1) (1)
TEST/SBWTCK
10
I
Selects test mode for JTAG pins on P1.5 to P1.7 and P2.0.
The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input for device programming and test.
RST/NMI/SBWTDIO
11
I
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output for device programming and test.
I/O
Input for an external reference voltage/
output for internal reference voltage (can be used as mid-voltage)
General-purpose digital I/O pin
Analog input to supply voltage supervisor
Timer_A3, clock signal TACLK input
SMCLK signal output
Timer_A3, compare: Out2 Output
P1.0/SVSIN/TACLK/SMCLK/TA2
12
DVSS
13
P2.6/XT2IN
14
I/O
Input terminal of crystal oscillator
General-purpose digital I/O pin
P2.7/XT2OUT
15
I/O
Output terminal of crystal oscillator
General-purpose digital I/O pin
DVCC
16
P1.1/TA1/SDCLK
17
I/O
General-purpose digital I/O pin
Timer_A3, capture: CCI1A and CCI1B inputs, compare: Out1 output
SD24_A bit stream clock output
P1.2/TA0/SD0DO
18
I/O
General-purpose digital I/O pin
Timer_A3, capture: CCI0A and CCI0B inputs, compare: Out0 output
SD24_A bit stream data output for channel 0
P1.3/UTXD0/SD1DO
19
I/O
General-purpose digital I/O pin
Transmit data out - USART0/UART mode
SD24_A bit stream data output for channel 1 (not available on MSP430AFE2x1)
P1.4/URXD0/SD2DO
20
I/O
General-purpose digital I/O pin
Receive data in - USART0/UART mode
SD24_A bit stream data output for channel 2 (not available on MSP430AFE2x2 and
MSP430AFE2x1)
Digital supply voltage, negative terminal
Digital supply voltage, positive terminal.
P1.5/SIMO0/SVSOUT/TMS
21
I/O
General-purpose digital I/O
Slave in/master out of USART0/SPI mode
SVS: output of SVS comparator
JTAG test mode select. TMS is used as an input port for device programming and
test.
P1.6/SOMI0/TA2/TCK
22
I/O
General-purpose digital I/O pin
Slave out/master in of USART0/SPI mode
Timer_A3, compare: Out2 output
JTAG test clock. TCK is the clock input port for device programming and test.
I/O
General-purpose digital I/O pin
External clock input - USART0/UART or SPI mode, clock output - USART0/SPI
mode.
Timer_A3, compare: Out1 output
JTAG test data output port. TDO/TDI data output or programming data input
terminal.
P1.7/UCLK0/TA1/TDO/TDI
(1)
23
It is recommended to short unused analog input pairs and connect them to analog ground.
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MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
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Table 2. Terminal Functions (continued)
TERMINAL
NAME
P2.0/STE0/TA0/TDI/TCLK
6
NO.
24
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I/O
I/O
DESCRIPTION
General-purpose digital I/O pin
Slave transmit enable - USART0/SPI mode.
Timer_A3, compare: Out0 output
JTAG test data input or test clock input for device programming and test.
Copyright © 2010–2011, Texas Instruments Incorporated
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
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SHORT-FORM DESCRIPTION
CPU
The MSP430™ CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
Instruction Set
General-Purpose Register
R11
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
The CPU is integrated with 16 registers that provide
reduced
instruction
execution
time.
The
register-to-register operation execution time is one
cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses and can be handled with
all instructions.
Table 3. Instruction Word Formats
EXAMPLE
OPERATION
Dual operands, source-destination
INSTRUCTION FORMAT
ADD R4,R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC → (TOS), R8 → PC
JNE
Jump-on-equal bit = 0
Relative jump, unconditional/conditional
Table 4. Address Mode Descriptions
ADDRESS MODE
D
(2)
SYNTAX
EXAMPLE
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) → M(TONI)
Absolute
✓
✓
MOV &MEM,&TCDAT
M(MEM) → M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
(1)
(2)
S
(1)
OPERATION
S = source
D = destination
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MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
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Operating Modes
The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation.
An interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode ( AM)
– All clocks are active.
• Low-power mode 0 (LPM0)
– CPU is disabled.
– ACLK and SMCLK remain active. MCLK is disabled.
• Low-power mode 1 (LPM1)
– CPU is disabled ACLK and SMCLK remain active. MCLK is disabled.
– DCO dc-generator is disabled if DCO not used in active mode.
• Low-power mode 2 (LPM2)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator remains enabled.
– ACLK remains active.
• Low-power mode 3 (LPM3)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator is disabled.
– ACLK remains active.
• Low-power mode 4 (LPM4)
– CPU is disabled.
– ACLK is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator is disabled.
– Crystal oscillator is stopped.
8
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MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 5. Interrupt Vector Addresses
INTERRUPT SOURCE
INTERRUPT FLAG
Power up
External reset
Watchdog
Flash key violation
PC out-of-range (1)
PORIFG
RSTIFG
WDTIFG
KEYV
NMI
Oscillator fault
Flash memory access violation
PRIORITY
Reset
0FFFEh
15, highest
(Non)maskable,
(Non)maskable,
(Non)maskable
0FFFCh
14
0FFFAh
13
0FFF8h
12
(2)
NMIIFG
OFIFG
ACCVIFG (2)
(3)
SD24CCTLx SD24OVIFG,
SD24CCTLx SD24IFG (2) (4)
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
USART0 Receive
URXIFG0
Maskable
0FFF2h
9
USART0 Transmit
UTXIFG0
Maskable
0FFF0h
8
0FFEEh
7
Maskable
0FFECh
6
Maskable
0FFEAh
5
Maskable
0FFE8h
4
0FFE6h
3
0FFE4h
2
Timer_A3
I/O Port P1 (eight flags)
I/O Port P2 (three flags)
(2)
(3)
(4)
WORD ADDRESS
SD24_A
Timer_A3
(1)
SYSTEM
INTERRUPT
TA0CCR0 CCIFG
(4)
TA0CCR1 CCIFG,
TA0CCR2 CCIFG,
TA0CTL TAIFG (2) (4)
P1IFG.0 to P1IFG.7 (2)
P2IFG.0 to P2IFG.2
(4)
(2) (4)
Maskable
0FFE2h
1
0FFE0h
0, lowest
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
Multiple source flags
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Interrupt flags are located in the module.
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Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw
rw-0, 1
rw-(0), (1)
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable 1
Address
7
6
5
4
1
0
00h
UTXIE0
URXIE0
ACCVIE
NMIIE
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
WDTIE
OFIE
NMIIE
ACCVIE
URXIE0
UTXIE0
3
2
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval
timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
USART0: UART and SPI receive interrupt enable
USART0: UART and SPI transmit interrupt enable
Table 7. Interrupt Enable 2
Address
7
6
5
4
3
2
1
0
01h
Table 8. Interrupt Flag Register 1
Address
7
6
4
3
2
1
0
02h
UTXIFG0
URXIFG0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-1
rw-0
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
WDTIFG
OFIFG
RSTIFG
PORIFG
NMIIFG
URXIFG0
UTXIFG0
5
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
Power-on reset interrupt flag. Set on VCC power up.
Set via RST/NMI-pin
USART0: UART and SPI receive interrupt flag
USART0: UART and SPI transmit interrupt flag
Table 9. Interrupt Flag Register 2
Address
7
6
5
4
3
2
1
0
03h
10
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Table 10. Module Enable Register 1
Address
7
6
04h
UTXE0
URXE0
USPIE0
rw-0
rw-0
URXE0
UTXE0
USPIE0
5
4
3
2
1
0
2
1
0
USART0: UART mode receive enable
USART0: UART mode transmit enable
USART0: SPI mode transmit and receive enable
Table 11. Module Enable Register 2
Address
7
6
5
4
3
05h
Memory Organization
Table 12. Memory Organization
MSP430AFE22x
MSP430AFE23x
MSP430AFE25x
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
4 KB
0xFFFF to 0xFFE0
0xFFFF to 0xF000
8 KB
0xFFFF to 0xFFE0
0xFFFF to 0xE000
16 KB
0xFFFF to 0xFFE0
0xFFFF to 0xC000
Information memory
Size
Flash
256 Byte
0x10FFh to 0x1000
256 Byte
0x10FFh to 0x1000
256 Byte
0x10FFh to 0x1000
Size
256 Byte
0x02FF to 0x0200
512 Byte
0x03FF to 0x0200
512 Byte
0x03FF to 0x0200
16-bit
8-bit
8-bit SFR
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
RAM
Peripherals
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for an internal digitally controlled
oscillator (DCO), a high-frequency crystal oscillator, and an internal very-low-power low-frequency oscillator
(VLO). The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic
clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from the VLO
• Main clock (MCLK), the system clock used by the CPU
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
Table 13. DCO Calibration Data
(Provided From Factory in Flash Information Memory Segment A)
DCO FREQUENCY
8 MHz
12 MHz
CALIBRATION REGISTER
SIZE
ADDRESS
CALBC1_8MHZ
byte
010FDh
CALDCO_8MHZ
byte
010FCh
CALBC1_12MHZ
byte
010FBh
CALDCO_12MHZ
byte
010FAh
Brownout, Supply Voltage Supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off. The supply voltage supervisor (SVS) circuitry detects if supply voltage drops below a user-selectable
level and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (SVM) (the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have
ramped to VCC(min) at that time. The user must ensure that the default DCO settings are not changed until VCC
reaches VCC(min) . If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
Digital I/O
There are two I/O ports implemented: 8-bit port P1 and 3-bit port P2.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all eight bits of port P1 and three bits of port P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
Because there are only three I/O pins implemented from port P2, bits [5:1] of all port P2 registers read as 0, and
write data is ignored.
Watchdog Timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be disabled or configured as an interval timer and can generate interrupts at
selected time intervals.
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Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 14. Timer_A3 Signal Connections
INPUT PIN NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
12 - P1.0
TACLK
INCLK
18 - P1.2
TA0
CCI0A
TA0
CCI0B
DVSS
GND
24-PIN PW
12 - P1.0
18 - P1.2
17 - P1.1
17 - P1.1
DVCC
VCC
TA1
CCI1A
TA1
CCI1B
DVSS
GND
DVCC
VCC
DVSS
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
MODULE BLOCK
Timer
MODULE OUTPUT
SIGNAL
OUTPUT PIN
NUMBER
24-PIN PW
NA
18 - P1.2
CCR0
TA0
24 - P2.0
17 - P1.1
CCR1
TA1
23 - P1.7
12 - P1.0
CCR2
TA2
22 - P1.6
USART0
The MSP430AFE2xx devices have one hardware universal synchronous/asynchronous receive transmit
(USART0) peripheral module that is used for serial data communication. The USART0 module supports
synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit
and receive channels. The maximum operational frequency for the USART0 module is 8 MHz.
Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8,
8x16, and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as
signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
SD24_A
The SD24_A module integrates up to three independent 24-bit sigma-delta A/D converters. Each channel is
designed with fully differential analog input pair and programmable gain amplifier input stage. In addition to
external analog inputs, an internal VCC sense and temperature sensor are also available.
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Peripheral File Map
Table 15. Peripherals With Word Access
Timer_A3
Capture/compare register 2
TACCR2
0x0176
Capture/compare register 1
TACCR1
0x0174
Capture/compare register 0
TACCR0
0x0172
Timer_A register
TAR
0x0170
Capture/compare control 2
TACCTL2
0x0166
Capture/compare control 1
TACCTL1
0x0164
Capture/compare control 0
TACCTL0
0x0162
Timer_A control
TACTL
0x0160
Timer_A interrupt vector
TAIV
0x012E
Sum extend
SUMEXT
0x013E
Result high word
RESHI
0x013C
Result low word
RESLO
0x013A
Second operand
OP2
0x0138
Multiply signed + accumulate/operand 1
MACS
0x0136
Multiply + accumulate/operand 1
MAC
0x0134
Multiply signed/operand 1
MPYS
0x0132
Multiply unsigned/operand 1
MPY
0x0130
Flash control 3
FCTL3
0x012C
Flash control 2
FCTL2
0x012A
Flash control 1
FCTL1
0x0128
Watchdog Timer+
Watchdog/timer control
WDTCTL
0x0120
SD24_A
(also see Table 16)
General Control
SD24CTL
0x0100
Channel 0 Control
SD24CCTL0
0x0102
Channel 1Control
SD24CCTL1
0x0104
Channel 2 Control
SD24CCTL2
0x0106
Channel 0 conversion memory
SD24MEM0
0x0110
Channel 1 conversion memory
SD24MEM1
0x0112
Channel 2 conversion memory
SD24MEM2
0x0114
SD24 Interrupt vector word register
SD24IV
0x01AE
Hardware Multiplier
Flash Memory
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Table 16. Peripherals With Byte Access
SD24_A
(also see Table 15)
Channel 0 Input Control
SD24INCTL0
0x00B0
Channel 1 Input Control
SD24INCTL1
0x00B1
Channel 2 Input Control
SD24INCTL2
0x00B2
Channel 0 Preload
SD24PRE0
0x00B8
Channel 1 Preload
SD24PRE1
0x00B9
Channel 2 Preload
SD24PRE2
0x00BA
Reserved (Internal SD24_A Configuration 1)
SD24CONF1
0x00BF
Transmit buffer
U0TXBUF
0x0077
Receive buffer
U0RXBUF
0x0076
Baud rate
U0BR1
0x0075
Baud rate
U0BR0
0x0074
Modulation control
U0MCTL
0x0073
Receive control
U0RCTL
0x0072
Transmit control
U0TCTL
0x0071
USART control
U0CTL
0x0070
Basic clock system control 3
BCSCTL3
0x0053
Basic clock system control 2
BCSCTL2
0x0058
Basic clock system control 1
BCSCTL1
0x0057
DCO clock frequency control
DCOCTL
0x0056
Brownout, SVS
SVS control register (reset by brownout signal)
SVSCTL
0x0055
Port P2
Port P2 selection 2
P2SEL2
0x0042
Port P2 resistor enable
P2REN
0x002F
Port P2 selection
P2SEL
0x002E
Port P2 interrupt enable
P2IE
0x002D
Port P2 interrupt edge select
P2IES
0x002C
Port P2 interrupt flag
P2IFG
0x002B
Port P2 direction
P2DIR
0x002A
Port P2 output
P2OUT
0x0029
Port P2 input
P2IN
0x0028
Port P1 selection 2 register
P1SEL2
0x0041
Port P1 resistor enable
P1REN
0x0027
Port P1 selection
P1SEL
0x0026
Port P1 interrupt enable
P1IE
0x0025
Port P1 interrupt edge select
P1IES
0x0024
Port P1 interrupt flag
P1IFG
0x0023
Port P1 direction
P1DIR
0x0022
Port P1 output
P1OUT
0x0021
Port P1 input
P1IN
0x0020
SFR module enable 2
ME2
0x0005
SFR module enable 1
ME1
0x0004
SFR interrupt flag 2
IFG2
0x0003
SFR interrupt flag 1
IFG1
0x0002
SFR interrupt enable 2
IE2
0x0001
SFR interrupt enable 1
IE1
0x0000
USART0
Basic Clock System+
Port P1
Special Function
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Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS
-0.3 V to 4.1 V
Voltage applied to any pin (2)
-0.3 V to VCC + 0.3 V
±2 mA
Diode current at any device terminal
Storage temperature, Tstg (3)
(1)
(2)
(3)
Unprogrammed device
-55°C to 150°C
Programmed device
-40°C to 85°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions (1)
(2)
MIN
VCC
Supply voltage
Supply voltage
TA
Operating free-air temperature
fSYSTEM
Processor frequency
(maximum MCLK frequency) (1) (2)
(see Figure 1)
(1)
(2)
(3)
MAX
UNIT
During program
execution (3)
1.8
3.6
V
During program/erase
flash memory
2.2
3.6
V
-40
85
°C
VCC = 1.8 V, Duty cycle = 50% ±10%
dc
4.15
VCC = 2.7 V, Duty cycle = 50% ±10%
dc
9
VCC ≥ 3.3 V, Duty cycle = 50% ±10%
dc
12
AVCC = DVCC = VCC
VSS
NOM
(1)
AVSS = DVSS = VSS
0
V
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
The operating voltage range for SD24_A is 2.5 V to 3.6 V
Legend :
System Frequency −MHz
12 MHz
Supply voltage range
during flash memory
programming
9 MHz
Supply voltage range
during program execution
6.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V
3.6 V
Supply Voltage − V
A.
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
B.
If high frequency crystal used is above 12 MHz and selected to source CPU clock then MCLK divider should be
programmed appropriately to run CPU below 8 MHz.
Figure 1. Operating Area
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Active Mode Supply Current (into DVCC + AVCC) Excluding External Current (1)
PARAMETER
IAM,
IAM,
(1)
1MHz
12MHz
TEST CONDITIONS
TA
Active mode (AM)
current at 1 MHz
fDCO = fMCLK = fSMCLK = DCO default
frequency (approximately 1 MHz),
fACLK = fVLO = 12 kHz,
Program executes in flash,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current at 12 MHz
fDCO = fMCLK = fSMCLK = 12 MHz,
fACLK = fVLO = 12 kHz,
Program executes in flash,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
VCC
MIN
TYP
2.2 V
220
3V
350
3.3 V
4.0
MAX
UNIT
µA
4.5
mA
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
Typical Characteristics – Active-Mode Supply Current (Into DVCC + AVCC)
4
5
fDCO = 12 MHz
3.5
4
Active Mode Supply Current - mA
Active Mode Supply Current - mA
4.5
3.5
fDCO = 8 MHz
3
2.5
2
1.5
1
fDCO = 1 MHz
0.5
VCC = 3 V,
TA = 85°C
3
VCC = 3 V,
TA = 25°C
2.5
VCC = 2.2 V,
TA = 85°C
2
1.5
1
VCC = 2.2 V,
TA = 25°C
0.5
0
0
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
3.75
VCC - Supply Voltage - V
Figure 2. Active-Mode Current vs VCC, TA = 25°C
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4
0
2
4
6
8
fDCO - DCO Frequency - MHz
10
12
Figure 3. Active-Mode Current vs DCO Frequency
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Low-Power-Mode Supply Currents (Into VCC) Excluding External Current
PARAMETER
TA
VCC
Low-power mode 0
(LPM0) current (2)
fMCLK = 0 MHz,
fSMCLK = fDCO = DCO default frequency
(approximately 1 MHz),
fACLK = fVLO = 12 kHz,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
25°C
2.2 V
65
µA
ILPM2
Low-power mode 2
(LPM2) current (3)
fMCLK = fSMCLK = 0 MHz,
fDCO = DCO default frequency
(approximately 1 MHz),
fACLK = fVLO = 12 kHz,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
22
µA
ILPM3,VLO
Low-power mode 3
(LPM3) current (3)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = fVLO = 12 kHz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
0.5
1.0
0.7
Low-power mode 4
(LPM4) current (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = fVLO = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
0.1
ILPM4
1.1
2.5
ILPM0
(1)
(2)
(3)
(4)
TEST CONDITIONS
(1)
MIN
25°C
2.2 V
85°C
TYP
MAX
UNIT
µA
µA
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
Typical Characteristics – LPM4 Current
6.0
VCC = 3.6 V
VCC = 3 V
ILPM4 - Low-power Mode Current - µA
5.0
VCC = 2.2 V
VCC = 1.8 V
4.0
3.0
2.0
1.0
0.0
-40
-20
0
20
40
60
80
100
120
TA - Temperature - °C
Figure 4. ILPM4 -- LPM4 Current vs Temperature
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Schmitt-Trigger Inputs (Ports Px and RST/NMI)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT-
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ - VIT-)
RPull
Pullup/pulldown resistor
(not RST/NMI pin)
For pullup: VIN = VSS;
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
VCC
MIN
TYP
MAX
UNIT
0.45 VCC
0.75 VCC
1.35
2.25
0.25 VCC
0.55 VCC
3V
0.75
1.65
3V
0.3
1.0
V
3V
20
50
kΩ
3V
35
V
V
5
pF
Leakage Current (Ports Px)
PARAMETER
Ilkg(Px.y)
(1)
(2)
TEST CONDITIONS
High-impedance leakage current
VCC
(1) (2)
MIN
TYP
3V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs (Ports Px)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
IOH(max) = -6 mA (1)
3V
VCC – 0.2
V
VOL
Low-level output voltage
IOL(max) = 6 mA (1)
3V
VSS + 0.2
V
(1)
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency (Ports Px)
PARAMETER
fPx.y
Port output frequency (with load)
fPort_CLK
(1)
(2)
Clock output frequency
TEST CONDITIONS
VCC
Px.y, CL = 20 pF, RL = 1 kΩ (1) (2)
3V
12
MHz
3V
16
MHz
Px.y, CL = 20 pF
(2)
MIN
TYP
MAX
UNIT
A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics – Outputs
One output loaded at a time.
TYPICAL LOW -LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOL TAGE
TYPICAL LOW -LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOL TAGE
50.0
VCC = 2.2 V
P1.0
TA = 25°C
20.0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
25.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P1.0
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
TA = 25°C
40.0
VOL − Low-Level Output V oltage − V
0.5
1.0
Figure 5.
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
3.0
3.5
0.0
VCC = 2.2 V
P1.0
−5.0
−10.0
−15.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
VOH − High-Level Output V oltage − V
Figure 7.
20
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
−25.0
0.0
2.0
Figure 6.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−20.0
1.5
VOL − Low-Level Output V oltage − V
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VCC = 3 V
P1.0
−10.0
−20.0
−30.0
−40.0
−50.0
0.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output V oltage − V
Figure 8.
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POR/Brownout Reset (BOR) (1)
(2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(start)
See Figure 9
dVCC/dt ≤ 3 V/s
0.7 ×
V(B_IT-)
V(B_IT-)
See Figure 9 through Figure 11
dVCC/dt ≤ 3 V/s
1.42
V
Vhys(B_IT-)
See Figure 9
dVCC/dt ≤ 3 V/s
120
mV
td(BOR)
See Figure 9
2000
µs
t(reset)
Pulse length needed at RST/NMI pin
to accepted reset internally
(1)
(2)
3V
2
V
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) +
Vhys(B_IT) is ≤ 1.8 V.
During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default DCO settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 9. POR/Brownout Reset (BOR) vs Supply Voltage
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
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Typical Characteristics – POR/Brownout Reset (BOR)
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
t pw − Pulse Width − µs
1 ns
t pw − Pulse Width − µs
Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
tf = tr
1
t pw − Pulse Width − µs
1000
tf
tr
t pw − Pulse Width − µs
Figure 11. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
22
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
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Supply Voltage Supervisor (SVS) / Supply Voltage Monitor (SVM) (1)
PARAMETER
TEST CONDITIONS
MIN
dVCC/dt > 30 V/ms (see Figure 12)
t(SVSR)
VLD ≉ 0
V(SVSstart)
VLD ≉ 0, VCC/dt ≤ 3 V/s (see Figure 12)
VCC/dt ≤ 3 V/s (see Figure 12)
Vhys(SVS_IT-)
VCC/dt ≤ 3 V/s (see Figure 12), external voltage applied on
SVSIN
VLD = 1
VLD = 2 to 14
15
mV
VLD = 15
10
mV
1.8
2.1
VLD = 3
2.2
VLD = 4
2.3
2.24
2.5
VLD = 7
2.65
VLD = 8
(1)
(2)
(3)
2.9
2.6
V
3.13
3.05
VLD = 11
3.2
VLD = 12
3.35
VLD = 15
2.05
2.8
2.69
3.24
3.5 3.76 (3)
3.7 (3)
VLD = 14
VLD ≠ 0, VCC = 3 V
2.4
VLD = 6
VLD = 13
ICC(SVS)
1.9
VLD = 2
VLD = 10
(1)
V
mV
VLD = 9
VCC/dt ≤ 3 V/s (see Figure 12), external voltage applied on
SVSIN
1.7
120
VLD = 5
V(SVS_IT-)
µs
12
1.55
VLD = 1
VCC/dt ≤ 3V/s (see Figure 12)
µs
100
(2)
UNIT
µs
2000
SVS on, switch from VLD = 0 to VLD ≉ 0, VCC =3 V
tsettle
MAX
100
dVCC/dt ≤ 30 V/ms
td(SVSon)
TYP
1.1
1.2
1.3
12
17
µA
The current consumption of the SVS module is not included in the ICC current consumption data.
tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≉ 0 to a different VLD value
somewhere between 2 and 15. The overdrive is assumed to be > 50 mV.
The recommended operating voltage range is limited to 3.6 V.
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
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Typical Characteristics – SVS
Software sets VLD > 0:
SVS is active
AVCC
V(SVS_IT-- )
V(SVSstart)
Vhys(SVS_IT-- )
Vhys(B_IT-- )
V(B_IT-- )
VCC(start)
Brownout
Brownout
Region
Brownout
Region
1
0
SVS out
t d(BOR)
SVS CircuitisActiveFromVLD>toV
1
0
td(SVSon)
Set POR
1
CC
td(BOR)
< V(B_IT-- )
td(SVSR)
undefined
0
Figure 12. SVS Reset (SVSR) vs Supply Voltage
VCC
3V
t pw
2
Rectangular Drop
VCC(min)
VCC(min) -- V
1.5
Triangular Drop
1
1 ns
1ns
VCC
3V
0.5
t pw
0
1
10
100
1000
tpw – Pulse Width – µs
VCC(min)
tf = tr
tf
tr
t – Pulse Width – µs
Figure 13. VCC(min) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
24
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
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Main DCO Characteristics
•
•
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage =
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
DCO Frequency
PARAMETER
VCC
Supply voltage range
TEST CONDITIONS
VCC
MIN
TYP
MAX
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
RSELx = 15
3.0
3.6
0.10
0.14
V
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
3.3 V
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
3.3 V
0.12
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
3.3 V
0.15
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
3.3 V
0.21
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
3.3 V
0.30
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
3.3 V
0.41
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
3.3 V
0.58
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
3.3 V
0.80
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
3.3 V
1.15
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
3.3 V
1.60
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
3.3 V
2.30
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
3.3 V
3.40
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
3.3 V
4.25
MHz
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
3.3 V
5.80
M Hz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
3.3 V
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
3.3 V
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3.3 V
15.30
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3.3 V
21.00
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3.3 V
1.35
ratio
SDCO
Frequency step between tap
DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
3.3 V
1.08
ratio
Duty cycle
Measured at SMCLK output
3.3 V
50
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0.06
UNIT
7.80
8.6
11.25
MHz
MHz
13.9
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MHz
%
25
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
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Calibrated DCO Frequencies – Tolerance
PARAMETER
TA
VCC
MIN
TYP
MAX
UNIT
8-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3.3V
0°C to 85°C
3.3 V
7.76
8
8.24
MHz
8-MHz tolerance over VCC
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3.3V
30°C
2.7 V to 3.6 V
7.76
8
8.24
MHz
8-MHz tolerance overall
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3.3V
-40°C to 85°C
2.7 V to 3.6 V
7.52
8
8.48
MHz
12-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3.3V
0°C to 85°C
3.3 V
11.64
12
12.36
MHz
12-MHz tolerance over VCC
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3.3V
30°C
3.3 V to 3.6 V
11.64
12
12.36
MHz
12-MHz tolerance overall
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3.3V
-40°C to 85°C
3.3 V to 3.6 V
11.28
12
12.72
MHz
TYP
MAX
UNIT
(1)
TEST CONDITIONS
This is the frequency change from the measured frequency at 30°C over temperature.
Wake-Up From Lower-Power Modes (LPM3/4)
PARAMETER
TEST CONDITIONS
tDCO,LPM3/4
DCO clock wake-up time from
LPM3/4 (1)
tCPU,LPM3/4
CPU wake-up time from
LPM3/4 (2)
(1)
(2)
VCC
fDCO = DCO default frequency
(approximately 1 MHz)
MIN
1.5
µs
1 / fMCLK +
tDCO,LPM3/4
µs
3V
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4
DCO Wake Time − us
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 14. Clock Wake-Up Time From LPM3 vs DCO Frequency
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
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Internal Very-Low-Power Low-Frequency Oscillator (VLO)
TA
VCC
MIN
TYP
MAX
fVLO
VLO frequency
PARAMETER
-40°C to 85°C
3V
4
12
22
dfVLO/dT
VLO frequency temperature drift (1)
-40°C to 85°C
3V
dfVLO/dVCC
VLO frequency supply voltage drift (2)
25°C
1.8 V to 3.6 V
(1)
(2)
UNIT
kHz
0.5
%/°C
4
%/V
Calculated using the box method: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...85°C)/[85°C - (-40°C)]
Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)
Crystal Oscillator (XT2) (1)
PARAMETER
TEST CONDITIONS
fXT2,HF0
XT2 oscillator crystal frequency,
HF mode 0
fXT2,HF1
XT2 oscillator crystal frequency,
HF mode 1
fXT2,HF2
XT2 oscillator crystal frequency,
HF mode 2
fXT2,HF,logic
OAHF
CL,eff
XT2 oscillator logic-level
square-wave input frequency,
HF mode
Oscillation allowance for HF
crystals (see Figure 15 and
Figure 16)
Integrated effective load
capacitance, HF mode (2)
(1)
(2)
(3)
(4)
(5)
Oscillator fault frequency
MIN
XT2OFF = 0, XT2Sx = 0
1.8 V to 3.6 V
XT2OFF = 0, XT2Sx = 1
XT2OFF = 0, XT2Sx = 2
XT2OFF = 0, XT2Sx = 3
MAX
UNIT
0.4
1
MHz
1.8 V to 3.6 V
1
4
MHz
1.8 V to 2.2 V
2
10
2.2 V to 3.0 V
2
12
3.0 V to 3.6 V
2
16
1.8 V to 2.2 V
0.4
10
2.2 V to 3.0 V
0.4
12
3.0 V to 3.6 V
0.4
16
2700
XT2OFF = 0, XT2Sx = 1
fXT2,HF = 4 MHz,
CL,eff = 15 pF
800
XT2OFF = 0, XT2Sx = 2
fXT2,HF = 16 MHz,
CL,eff = 15 pF
300
XT2OFF = 0, Measured at
P1.0/SVSIN/TACLK/SMCLK/TA2,
fXT2,HF = 10 MHz
XT2OFF = 0, Measured at
P1.0/SVSIN/TACLK/SMCLK/TA2,
fXT2,HF = 16 MHz
(4)
TYP
XT2OFF = 0, XT2Sx = 0
fXT2,HF = 1 MHz,
CL,eff = 15 pF
XT2OFF = 0 (3)
Duty cycle
fFault,HF
VCC
XT2OFF = 0, XT2Sx = 3 (5)
50
pF
60
3V
%
40
3V
MHz
Ω
1
40
MHz
30
50
60
300
kHz
To improve EMI on the XT2 oscillator the following guidelines should be observed:
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
Measured with logic-level input frequency, but also applies to operation with crystals.
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Typical Characteristics – XT2 Oscillator
100000.00
1800.0
LFXT1Sx = 2
10000.00
1000.00
LFXT1Sx = 2
100.00
XT Oscillator Supply Current − uA
Oscillation Allowance − Ohms
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
LFXT1Sx = 1
LFXT1Sx = 1
200.0
LFXT1Sx = 0
10.00
0.10
1.00
10.00
100.00
0.0
0.0
LFXT1Sx = 0
4.0
Crystal Frequency − MHz
8.0
12.0
16.0
20.0
Crystal Frequency − MHz
Figure 15. Oscillation Allowance vs Crystal Frequency,
CL,eff = 15 pF, TA = 25°C
Figure 16. XT2 Oscillator Supply Current vs Crystal
Frequency, CL,eff = 15 pF, TA = 25°C
SD24_A, Power Supply and Recommended Operating Conditions
PARAMETER
AVCC
ISD24
fSD24
28
Analog supply voltage
Analog supply current: 1 active
SD24_A channel including
internal reference
Analog front-end input clock
frequency
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TEST CONDITIONS
VCC
AVCC = DVCC
AVSS = DVSS = 0 V
SD24LP = 0, fSD24 = 1 MHz,
SD24OSR = 256
TYP
2.5
800
GAIN: 4, 8, 16
900
3V
V
µA
800
GAIN: 32
SD24LP = 1 (low-power mode enabled)
UNIT
1100
1200
GAIN: 1
SD24LP = 0 (low-power mode disabled)
MAX
3.6
GAIN: 1, 2
GAIN: 32
SD24LP = 1, fSD24 = 0.5 MHz,
SD24OSR = 256
MIN
900
3V
0.03
1
0.03
0.5
1.1
MHz
Copyright © 2010–2011, Texas Instruments Incorporated
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
SD24_A, Input Range (1)
PARAMETER
VID,FSR
TEST CONDITIONS
MIN
Bipolar mode, SD24UNI = 0
Differential full scale input
voltage range
SD24REFON = 1
TYP
+VREF /
2GAIN
0
+VREF /
2GAIN
SD24GAINx = 1
±500
SD24GAINx = 2
±250
SD24GAINx = 4
±125
SD24GAINx = 8
±62
SD24GAINx = 16
±31
SD24GAINx = 32
±15
SD24GAINx = 1
MAX
-VREF /
2GAIN
Unipolar mode, SD24UNI = 1
Differential input voltage
range for specified
performance (2)
VID
VCC
UNIT
mV
mV
200
ZI
Input impedance (one input
pin to AVSS)
fSD24 = 1 MHz
ZID
Differential input impedance
(IN+ to IN-)
fSD24 = 1 MHz
VI
Absolute input voltage range
AVSS - 1
AVCC
V
VIC
Common-mode input voltage
range
AVSS - 1
AVCC
V
(1)
(2)
SD24GAINx = 32
SD24GAINx = 1
SD24GAINx = 32
3V
kΩ
75
3V
300
400
100
150
kΩ
All parameters pertain to each SD24_A channel.
The full-scale range is defined by VFSR+ = +(VREF/2)/GAIN and VFSR- = -(VREF/2)/GAIN. If VREF is sourced externally, the analog input
range should not exceed 80% of VFSR+ or VFSR-; that is, VID = 0.8 VFSR- to 0.8 VFSR+. If VREF is sourced internally, the given VID ranges
apply.
SD24_A, Performance (fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1)
PARAMETER
G
Nominal gain
EOS
Offset error
ΔEOS/ΔT
Offset error temperature
coefficient
CMRR
Common-mode rejection
ratio
TEST CONDITIONS
VCC
MIN
TYP
SD24GAINx = 1
1
SD24GAINx = 2
1.96
SD24GAINx = 4
SD24GAINx = 8
3V
7.62
15.04
SD24GAINx = 32
28.35
SD24GAINx = 32
SD24GAINx = 1
SD24GAINx = 32
SD24GAINx = 1, Common-mode input signal:
VID = 500 mV, fIN = 50 Hz, 100 Hz
SD24GAINx = 32, Common-mode input signal:
VID = 16 mV, fIN = 50 Hz, 100 Hz
±0.2
3V
3V
UNIT
3.86
SD24GAINx = 16
SD24GAINx = 1
MAX
±1.5
±4
±20
±20
±100
%FSR
ppm
FSR/°C
>90
3V
dB
>75
AC PSRR
AC power supply
rejection ratio
SD24GAINx = 1, VCC = 3 V ± 100 mV,
fVCC = 50 Hz
3V
>80
dB
XT
Crosstalk
SD24GAINx = 1, VID = 500 mV,
fIN = 50 Hz, 100 Hz
3V
<-100
dB
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SD24_A, Temperature Sensor and Built-In VCC Sense
PARAMETER
TEST CONDITIONS
TCSensor
Sensor temperature coefficient
VOffset,sensor
Sensor offset voltage
Sensor output voltage (1) (2)
VCC,Sense
VCC divider at input 5
RSource,VCC
Source resistance of VCC
divider at input 5
(2)
MIN
TYP
MAX
1.18
1.32
1.46 mV/°C
-100
VSensor
(1)
VCC
Temperature sensor voltage at TA = 85°C
Temperature sensor voltage at TA = 30°C
3V
100
420
475
515
350
402
442
fSD24 = 1 MHz, SD24OSRx = 256,
SD24REFON = 1
UNIT
mV
mV
VCC/1
1
V
20
kΩ
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor (273 + T [°C]) + VOffset,sensor [mV]
Results based on characterization and/or production test, not TCSensor or VOffset,sensor. Measured with fSD24 = 1 MHz, SD24OSRx = 256,
SD24REFON = 1.
SD24_A, Built-In Voltage Reference
VCC
MIN
TYP
MAX
UNIT
VREF
Internal reference voltage
PARAMETER
SD24REFON = 1, SD24VMIDON = 0
3V
1.14
1.2
1.26
V
IREF
Reference supply current
SD24REFON = 1, SD24VMIDON = 0
3V
200
320
µA
TC
Temperature coefficient
SD24REFON = 1, SD24VMIDON = 0 (1)
3V
18
50
ppm/°C
CREF
VREF load capacitance
SD24REFON = 1, SD24VMIDON = 0 (2)
ILOAD
VREF(I) maximum load current
SD24REFON = 1, SD24VMIDON = 0
3V
tON
Turn-on time
SD24REFON = 0→1, SD24VMIDON = 0,
CREF = 100nF
3V
DC PSR
DC power supply rejection
ΔVREF/ΔVCC
SD24REFON = 1, SD24VMIDON = 0,
VCC = 2.5 V to 3.6 V
(1)
(2)
TEST CONDITIONS
100
nF
±200
nA
5
ms
µV/V
100
Calculated using the box method: (MAX(-40...85°C) - MIN(-40...85°C)) / MIN(-40...85°C) / (85°C - (-40°C))
There is no capacitance required on VREF. However, a capacitance of at least 100 nF is recommended to reduce any reference voltage
noise.
SD24_A, Reference Output Buffer
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VREF,BUF
Reference buffer output
voltage
SD24REFON = 1, SD24VMIDON = 1
3V
1.2
IREF,BUF
Reference supply + reference
output buffer quiescent
SD24REFON = 1, SD24VMIDON = 1
current
3V
430
CREF(O)
Required load capacitance
on VREF
SD24REFON = 1, SD24VMIDON = 1
ILOAD,Max
Maximum load current on
VREF
SD24REFON = 1, SD24VMIDON = 1
Maximum voltage variation vs
|ILOAD| = 0 to 1 mA
load current
tON
30
Turn-on time
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SD24REFON = 0→1, SD24VMIDON = 0→1,
CREF = 470 nF
MAX
V
650
470
3V
µA
nF
3V
3V
UNIT
-15
100
±1
mA
+15
mV
µs
Copyright © 2010–2011, Texas Instruments Incorporated
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
SD24_A, External Reference Input
VCC
MIN
TYP
MAX
VREF(I) Input voltage range
PARAMETER
SD24REFON = 0
TEST CONDITIONS
3V
1.0
1.25
1.5
V
IREF(I)
SD24REFON = 0
3V
50
nA
Input current
UNIT
USART0
PARAMETER
TEST CONDITIONS
MIN
TYP
fUSART USART clock frequency
t(τ)
(1)
USART0: deglitch time
(1)
VCC = 3 V, SYNC = 0, UART mode
150
280
MAX
UNIT
8
MHz
500
ns
The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t(τ) to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD0 line.
Timer_A3
PARAMETER
TEST CONDITIONS
fTA
Timer_A3 clock frequency
SMCLK, Duty cycle = 50% ± 10%
tTA,cap
Timer_A3, capture timing
TA0, TA1
VCC
MIN
TYP
MAX
fSYSTEM
3V
UNIT
MHz
20
ns
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
fFTG
Flash timing generator frequency
IPGM
Supply current from VCC during program
2.2 V/3.6 V
1
IERASE
Supply current from VCC during erase
2.2 V/3.6 V
1
257
(1)
tCPT
Cumulative program time
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
2.2 V/3.6 V
UNIT
3.6
V
476
kHz
5
mA
7
mA
10
ms
20
104
Program/erase endurance
MAX
ms
105
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
(2)
30
tFTG
tBlock,
0
Block program time for first byte or word
(2)
25
tFTG
1-63
Block program time for each additional byte or
word
(2)
18
tFTG
Block program end-sequence wait time
(2)
6
tFTG
Mass erase time
(2)
10593
tFTG
Segment erase time
(2)
4819
tFTG
tBlock,
tBlock,
End
tMass Erase
tSeg Erase
(1)
(2)
100
cycles
years
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the flash controller's state machine (tFTG = 1 / fFTG).
Copyright © 2010–2011, Texas Instruments Incorporated
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
TEST CONDITIONS
(1)
MIN
CPU halted
MAX
UNIT
1.6
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
MIN
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
3V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
3V
0.025
15
µs
tSBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge (1))
3V
1
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time
3V
15
100
µs
fTCK
TCK input frequency (2)
3V
0
10
MHz
RInternal
Internal pulldown resistance on TEST
3V
25
90
kΩ
(1)
(2)
TEST CONDITIONS
TYP
60
Tools accessing the Spy-Bi-Wire interface must wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
32
TEST CONDITIONS
TA = 25°C
MIN
MAX
UNIT
2.5
6
V
7
V
100
mA
1
ms
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, or emulation feature is possible, and JTAG is switched to
bypass mode.
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Copyright © 2010–2011, Texas Instruments Incorporated
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
APPLICATION INFORMATION
Port P1 Pin Schematic: P1.0 Input/Output With Schmitt Trigger
Pad Logic
To SVS Mux
VLD = 15
P1REN.0
DVSS
0
DVCC
1
1
0
P1DIR.0
P1SEL2.0
Direction
0: Input
1: Output
1
From Timer_A3
0
SMCLK
1
1
P1OUT.0
0
P1.0/SVSIN/TACLK/SMCLK/TA2
Bus
Keeper
EN
P1SEL.0
P1IN.0
EN
To Timer_A3
D
P1IE.0
P1IRQ.0
EN
Q
Set
P1IFG.0
P1SEL.0
Interrupt
Edge Select
P1IES.0
Table 17. Port P1 (P1.0) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
I: 0, O: 1
0
X
SVSIN (VLD = 15)
X
X
X
Timer_A3.TACLK
0
1
0
SMCLK
1
1
1
Timer_A3.TA2
1
1
0
P1.0 (I/O)
P1.0/SVSIN/TACLK/SMCLK/TA2
(1)
0
CONTROL BITS / SIGNALS (1)
X = don't care
Copyright © 2010–2011, Texas Instruments Incorporated
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
Port P1 Pin Schematic: P1.1 and P1.2 Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
From SD24_A
0
DVCC
1
1
0
P1DIR.x
P1SEL2.x
From Timer_A3
DVSS
Direction
0: Input
1: Output
1
0
1
1
P1OUT.x
0
P1.1/TA1/SDCLK
P1.2/TA0/SD0DO
Bus
Keeper
EN
P1SEL.x
P1IN.x
EN
To Timer_A3
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge Select
Table 18. Port P1 (P1.1 and P1.2) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.1 (I/O)
P1.1/TA1/SDCLK
1
(1)
34
P1SEL.x
P1SEL2.x
I: 0, O: 1
0
X
0
1
0
Timer_A3.TA1
1
1
0
1
1
1
I: 0, O: 1
0
X
Timer_A3.CCI0A and CCI0B
0
1
0
Timer_A3.TA0
1
1
0
SD0DO
1
1
1
P1.2 (I/O)
2
P1DIR.x
Timer_A3.CCI1A and CCI1B
SDCLK
P1.2/TA0/SD0DO
CONTROL BITS / SIGNAL (1)
X = don't care
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Copyright © 2010–2011, Texas Instruments Incorporated
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
Port P1 Pin Schematic: P1.3 Input/Output With Schmitt Trigger
Pad Logic
P1REN.3
DVSS
0
DVCC
1
P1DIR.3
1
0
1
Direction
0: Input
1: Output
1
USART0
direction
0
SD24_A data
1
USART0
data out
0
P1OUT.3
0
1
P1.3/UTXD0/SD1DO
P1SEL.3
P1SEL2.3
Bus
Keeper
EN
P1IN.3
EN
Not used
D
P1IE.3
EN
P1IRQ.3
Q
Set
P1IFG.3
P1SEL.3
P1IES.3
Interrupt
Edge Select
Table 19. Port P1 (P1.3) Pin Functions
PIN NAME (P1.x)
x
P1.3/UTXD0/SD1DO
3
FUNCTION
P1.3 (I/O)
(1)
CONTROL BITS / SIGNALS (1)
P1DIR.x
P1SEL.x
P1SEL2.x
I: 0, O: 1
0
X
UTXD0
X
1
0
SD1DO
1
1
1
X = don't care
Copyright © 2010–2011, Texas Instruments Incorporated
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
Port P1 Pin Schematic: P1.4 Input/Output With Schmitt Trigger
Pad Logic
P1REN.4
DVSS
0
DVCC
1
P1DIR.4
1
0
1
Direction
0: Input
1: Output
1
USART0
direction
0
P1SEL2.4
P1OUT.4
0
SD24_A data
1
P1.4/URXD0/SD2DO
P1SEL.4
Bus
Keeper
EN
P1IN.4
EN
USART0
data in
D
P1IE.4
P1IRQ.4
EN
Q
Set
P1IFG.4
P1SEL.4
P1IES.4
Interrupt
Edge Select
Table 20. Port P1 (P1.4) Pin Functions
PIN NAME (P1.x)
x
P1.4/URXD0/SD2DO
4
FUNCTION
P1.4 (I/O)
(1)
36
CONTROL BITS / SIGNALS (1)
P1DIR.x
P1SEL.x
P1SEL2.x
I: 0, O: 1
0
X
URXD0
X
1
0
SD2DO
1
1
1
X = don't care
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
Port P1 Pin Schematic: P1.5 to P1.7 Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
P1DIR.x
Direction
0: Input
1: Output
0
DVSS
0
DVCC
1
1
1
1
USART0
direction
0
Module X out
1
P1OUT.x
USART0
data out
0
1
0
P1SEL.x
P1SEL2.x
P1.5/SIMO0/SVSOUT/TMS
P1.6/SOMI0/TA2/TCK
P1.7/UCLK0/TA1/TDO/TDI
Bus
Keeper
EN
P1IN.x
EN
USART0
data in
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
P1SEL.x
Interrupt
Edge Select
P1IES.x
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
Table 21. Port P1 (P1.5 to P1.7) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P1.x)
x
5
P1.5/SIMO0/SVSOUT/TMS
6
P1.6/SOMI0/TA2/TCK
FUNCTION
P1.5 (I/O)
P1.7/UCLK0/TA1/TDO/TDI
(1)
(2)
P1SEL.x
P1SEL2.x
JTAG
Mode (2)
I: 0; O: 1
0
X
0
SIMO0
X
1
0
0
SVSOUT
1
1
1
0
TMS
X
X
X
1
P1.6 (I/O)
I: 0; O: 1
0
X
0
SOMI0
X
1
0
0
Timer_A3.TA2
1
1
1
0
TCK
7
P1DIR.x
P1.7 (I/O)
UCLK0
X
X
X
1
I: 0; O: 1
0
X
0
X
1
0
0
Timer_A3.TA1
1
1
1
0
TDO/TDI
X
X
X
1
X = don't care
JTAG Mode is not a register bit but signal generated internally when 4-wire JTAG option is selected in IDE
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
Port P2 Pin Schematic: P2.0 Input/Output With Schmitt Trigger
P2REN.0
Pad Logic
P2DIR.0
Direction
0: Input
1: Output
0
DVSS
0
DVCC
1
1
1
1
USART0
direction
0
Timer_A3 out
1
USART0
data out
0
P2OUT.0
0
1
P2.0/STE0/TA0/TDI/TCLK
P2SEL.0
P2SEL2.0
Bus
Keeper
EN
P2IN.0
EN
USART0
data in
D
P2IE.0
EN
P2IRQ.0
Q
Set
P2IFG.0
P2SEL.0
P2IES.0
Interrupt
Edge Select
To JTAG
From JTAG
Table 22. Port P2 (P2.0) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P2.x)
x
0
P2.0/STE0/TA0/TDI/TCLK
(1)
(2)
38
FUNCTION
P2.0 (I/O)
STE0
P2DIR.x
P2SEL.x
P2SEL2.x
JTAG
Mode (2)
I: 0; O: 1
0
X
0
X
1
0
0
Timer_A3.TA0
1
1
1
0
TDI/TCLK
X
X
X
1
X = don't care
JTAG Mode is not a register bit but signal generated internally when 4-wire JTAG option is selected in IDE
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger
BCSCTL3.XT2Sx = 11
P2.7/XT2OUT
XT2 off
0
XT2CLK
1
P2SEL.7
Pad Logic
P2REN.6
P2DIR.6
DVSS
0
DVCC
1
1
0
Direction
0: Input
1: Output
1
P2OUT.6
0
Module X OUT
1
P2.6/XT2IN
Bus
Keeper
EN
P2SEL.6
P2IN.6
EN
Module X IN
D
P2IE.6
EN
P2IRQ.6
Q
Set
P2IFG.6
P2SEL.6
P2IES.6
Interrupt
Edge Select
Table 23. Port P2 (P2.6) Pin Functions
Pin Name (P2.x)
P2.6/XT2IN
x
6
FUNCTION
P2.6 (I/O)
XT2IN (default)
Copyright © 2010–2011, Texas Instruments Incorporated
CONTROL BITS / SIGNALS
P2DIR.6
P2SEL.6
I: 0; O: 1
0
0
1
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger
BCSCTL3.XT2Sx = 11
P2.6/XT2IN
XT2 off
0
XT2CLK
From P2.6/XT2IN
1
P2SEL.6
Pad Logic
P2REN.7
P2DIR.7
DVSS
0
DVCC
1
1
0
Direction
0: Input
1: Output
1
P2OUT.7
0
Module X OUT
1
P2.7/XT2OUT
Bus
Keeper
EN
P2SEL.7
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
Set
P2IFG.7
P2SEL.7
P2IES.7
Interrupt
Edge Select
Table 24. Port P2 (P2.7) Pin Functions
PIN NAME (P2.x)
P2.7/XT2OUT
40
x
7
FUNCTION
P2.7 (I/O)
XT2OUT (default)
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CONTROL BITS / SIGNALS
P2DIR.7
P2SEL.7
I: 0, O: 1
0
0
1
Copyright © 2010–2011, Texas Instruments Incorporated
MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
JTAG Fuse Check Mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V or 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is
being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR, the fuse
check mode has the potential to be activated.
The fuse check current flow only when the fuse check mode is active and the TMS pin is in a low state (see
Figure 17). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITF
ITEST
Figure 17. Fuse Check Mode Current
NOTE
The CODE and RAM data protection is ensured if the JTAG fuse is blown.
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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
www.ti.com
REVISION HISTORY
REVISION
42
COMMENTS
SLAS701
Product Preview release
SLAS701A
Production Data release
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Copyright © 2010–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
28-Oct-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430AFE221IPW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
430AFE221
MSP430AFE221IPWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
430AFE221
MSP430AFE222IPW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE222
MSP430AFE222IPWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE222
MSP430AFE223IPW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE223
MSP430AFE223IPWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
430AFE223
MSP430AFE231IPW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE231
MSP430AFE231IPWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE231
MSP430AFE232IPW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE232
MSP430AFE232IPWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE232
MSP430AFE233IPW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE233
MSP430AFE233IPWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE233
MSP430AFE251IPW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE251
MSP430AFE251IPWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE251
MSP430AFE252IPW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE252
MSP430AFE252IPWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE252
MSP430AFE253IPW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
430AFE253
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
28-Oct-2014
Status
(1)
Package Type Package Pins Package
Drawing
Qty
MSP430AFE253IPWR
ACTIVE
TSSOP
PW
24
XMS430AFE253IPWR
OBSOLETE
TSSOP
PW
24
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TBD
Call TI
Call TI
-40 to 85
Device Marking
(4/5)
430AFE253
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Feb-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430AFE221IPWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
MSP430AFE222IPWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
MSP430AFE223IPWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
MSP430AFE231IPWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
MSP430AFE232IPWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
MSP430AFE233IPWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
MSP430AFE251IPWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
MSP430AFE252IPWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
MSP430AFE253IPWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Feb-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430AFE221IPWR
TSSOP
PW
24
2000
367.0
367.0
38.0
MSP430AFE222IPWR
TSSOP
PW
24
2000
367.0
367.0
38.0
MSP430AFE223IPWR
TSSOP
PW
24
2000
367.0
367.0
38.0
MSP430AFE231IPWR
TSSOP
PW
24
2000
367.0
367.0
38.0
MSP430AFE232IPWR
TSSOP
PW
24
2000
367.0
367.0
38.0
MSP430AFE233IPWR
TSSOP
PW
24
2000
367.0
367.0
38.0
MSP430AFE251IPWR
TSSOP
PW
24
2000
367.0
367.0
38.0
MSP430AFE252IPWR
TSSOP
PW
24
2000
367.0
367.0
38.0
MSP430AFE253IPWR
TSSOP
PW
24
2000
367.0
367.0
38.0
Pack Materials-Page 2
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