Simple Design Techniques for Optimizing Efficiency and Overvoltage Spike of Synchronous Rectification in DC to DC Converters IFAT PMM APS SE DS Mößlacher Christian Guillemant Olivier Edition 2011-02-02 Published by Infineon Technologies Austria AG 9500 Villach, Austria © Infineon Technologies Austria AG 2011. All Rights Reserved. Attention please! Information Warnings AN 2012-03 Authors: We Listen to Your Comments Olivier.Guillemant@infineon.com 1 Abstract ........................................................................................................................................................ 4 2 Introduction .................................................................................................................................................. 4 3 Choosing the optimum RDS(on) .................................................................................................................... 5 4 Optimizing the Snubber Network ............................................................................................................... 7 5 Optimizing the SR Gate Timing ................................................................................................................10 6 Optimizing the Package ............................................................................................................................11 6.1 Package Contribution to the Product RDS(on) ....................................................................................11 6.2 Improving the Figure of Merit ...........................................................................................................12 6.3 Improving the Switching Behavior ...................................................................................................14 7 Conclusion .................................................................................................................................................15 8 References .................................................................................................................................................15 1 Abstract Due to continuous increase of the packaging density and the more and more restricted energy guidelines ® (80PLUS [1]), the efficiency of switched-mode power supplies (SMPS) has to be successively improved to go above 90 %. One of the main losses are the diode forward losses of the secondary side rectification of an isolated power converter. Thus, reaching high efficiency is only possible with synchronous rectification (SR), using modern power MOSFETs. This measure can be a trade-off between low efficiency at light output loads due to increased switching losses and high voltage overshoots violating the maximum voltage rating of the synchronous MOSFETs versus efficiency gain. This paper proposes simple to implement design techniques for optimizing overall system efficiency and reducing voltage overshoots for speeding up the SMPS design process. 2 Introduction The secondary side rectification stage of a switched-mode power supply is typically realized with power diodes. As these diodes have a forward voltage drop of 0.5 V and higher they lead, in combination with the large output currents, to huge conduction losses. To reduce these losses modern power MOSFETs with onstate resistances of few milliohms can be used, which offer a big potential to improve overall system efficiency, especially at high-current operation. A closer comparison of these two variations of rectification shows, that replacing the power diodes by MOSFETs can lead to issues like low efficiency at light output loads or high voltage overshoots at turn-off. This comes from the switching capacitances, which are typically higher for MOSFETs than for diodes [4]. To overcome this drawback a detailed analysis of the optimum RDS(on) has to be performed. Another important issue is the gate timing of the SR MOSFETs. This parameter can highly influence efficiency and overvoltage spike of the converter. To get the whole advantage of modern silicon technologies, the right choice of the package is also an essential topic. Leadless SMD packages help to improve efficiency and dynamic behavior by reducing the parasitic resistive and inductive part of the package. 3 Choosing the optimum RDS(on) For choosing the optimum RDS(on) of a given MOSFET technology and therefore optimizing for highest efficiency, a well balanced ratio between switching losses and conduction losses has to be found. The description to calculate these losses can be found in a separate paper [2]. At low output loads, the conduction losses play only a minor role while switching losses are the dominant factor. Going for higher loads the ratio turns around and conduction losses become dominant. For an easy calculation of the optimum RDS(on) class for a given SR MOSFET technology, a model is developed. Therefore a MOSFET technology parameter, FOM (figure of merit), is introduced. This FOM gives an indication how the technology will perform in the system, e.g. FOMQg or FOMQoss. The FOM is an indicator for the expected gate drive losses or losses from the output capacitance. As the capacitances of a MOSFET are inverse proportional to the RDS(on) this product will stay the same over the whole RDS(on) classes of one fixed technology. Knowing the switching frequency f sw, the gate driving voltage Vg, the secondary side transformer voltage VT, the FOMQg and the FOMQoss, the optimum RDS(on) can be calculated at a defined MOSFET current IRMS. Following FOMs have to be defined: FOM Qg RDS (on) Qg @Vg Equation 1 FOM Qoss RDS (on Qoss@VT Equation 2 The charge always has to be calculated at the respective voltage, meaning Qoss at the transformer voltage VT and Qg at the gate driving voltage Vg. Every formula for calculating the power losses can be expressed via the RDS(on) of the MOSFET by introducing constant terms. 2 Pv _ cond I RMS RDS (on) Equation 3 Pv _ gate Qg Vg f sw Equation 4 Pv _ oss 1 VT Qoss@VT f sw 2 Equation 5 Following constant terms can be defined for each of the above mentioned formulas: ccond I 2 Equation 6 cgate FOM Qg f sw Vg Equation 7 coss FOM Qoss 1 VT f sw 2 Equation 8 The total power losses are now defined: Pv ccond RDS ( on) cgate 1 RDS ( on) coss 1 Equation 9 RDS ( on) By calculating the derivation of this formula, the optimum RDS(on) is defined. dPv 1 1 ccond cgate 2 coss 2 0 dRDS ( on) RDS ( on) RDS ( on) RDS ( on) _ opt cgate coss ccond FOM Qg f sw Vg 1 FOM Qoss VT f sw 2 2 I RMS Equation 10 Equation 11 To achieve a balanced efficiency over the whole load range, a reasonable choice of the MOSFET current has to be done. Going for a full load optimization will give good efficiency results at high output currents. But this approach will dramatically decrease efficiency at low loads and increase the number of parallel MOSFETs to a not acceptable value. Therefore an optimum has to be found, in order to achieve a relative constant efficiency value over the whole output current range. To illustrate this issue, efficiency with different optimization approaches can be seen in figure 1. These efficiency charts show the calculated efficiency of a 12V synchronous rectification stage with a transformer voltage of 40V, a gate driving voltage of 10V and a switching frequency of 100kHz. Taking a 75V SR MOSFET technology and calculating the optimum R DS(on) for 10A MOSFET current, gives high efficiency at low currents but very low efficiency at high currents. Going for a 50A optimization will give non acceptable efficiency at low currents, but reaches the maximum at full load. An optimum solution for this setup would be an optimization for 20A, which gives an overall balanced efficiency. 100 efficiency [%] 99.5 99 98.5 10 A optimization 98 20 A optimization 50 A optimization 97.5 5 10 15 20 25 30 35 40 45 50 output current [A] 4 Optimizing the Snubber Network A second lever for performance optimization is the choice and design of the snubber network (figure 2), which is responsible for the damping of the voltage overshoot at the SR MOSFET [3]. Taking a simple RC snubber network, which is a series RC combination in parallel to the output capacitance of the MOSFET, creates extra losses. Reason for this is that the snubber capacitance has to be charged and discharged every switching cycle, resulting in switching losses: Equation 12 Psnub_ loss 1 Csnub VT2 f sw 2 RC snubber RCD snubber Vout R D R Q Coss C Coss C Going from this RC combination to a RCD snubber network, losses can be reduced. If the voltage over the MOSFET is rising above the voltage over the snubber capacitance, the diode becomes conductive and the energy is transferred into this capacitance, clamping the overvoltage level (figure 3). overshoot without snubber clamped voltage (VH) V VT C charged through diode VDS MOSFET C discharged through resistor VH V at Cap VL The RC time constant has to be adjusted properly, in a way that the voltage over C is not lower than the transformer voltage. In this case the snubber capacitance is decoupled from the MOSFET output capacitance and therefore does not contribute to the capacitive turn off losses. Additionally, it’s possible to recover a part of the energy stored in the RCD snubber capacitance by discharging it to the output of the converter, instead to ground. With this method an increase of efficiency of the tested DC/DC converter in low load range up to 0.6% was achieved (figure 4). 93.0 92.5 92.0 efficiency [%] 91.5 91.0 90.5 90.0 89.5 RC snubber 89.0 RCD snubber 88.5 88.0 10 15 20 25 30 output current [A] 35 40 45 50 To get an optimized behavior of this RCD network, the loop MOSFET – diode - capacitor has to me minimized. The lower the inductance, the higher the response time and therefore the higher the effectiveness of the snubber. For the application this means low inductive SMD components have to be used and placed as near as possible to the MOSFET. Ideally this RCD network avoids any additional losses, while allowing to recover some part of the energy of the overshoot. With the following calculation a rough estimation of the values for the resistance and the capacitance can be done. First of all the energy which is stored in the voltage overshoot has to be known [2]. E VT 1 Qoss@VT Qrr 2 Equation 13 This energy then gets transferred into the capacitance of the snubber network: E 1 CFET @ VT Csnub VH2 VL2 2 Equation 14 Out of this consideration, the capacitance of the snubber can be estimated. 2 VT 1 Qoss Qrr 2 Csnub CFET @VT 2 VH VL2: Equation 15 Depending on Csnub the resistor for discharging the capacitor can be calculated: V (t ) VH Vout e t Rsn u bCsn u b Vout VL t VL Vout e Rsn u bCsn u b VH Vout Equation 16 1 V V t ln L out Rsnub Csnub VH Vout V V Rsnub f sw Csnub ln L out VH Vout 1 These formulas will give a first estimation for the values R snub and Csnub. An exact adjustment has to be done by trial and error in the application, as also a lot of external parasitics contribute to the behavior of the snubber network. 5 Optimizing the SR Gate Timing Another important impact on the voltage overshoot is coming from the gate timing of the SR MOSFET. As typically the body diode is conductive before the SR MOSFET is turned off, special attention has to given to the on-time. The longer the body diode is flooded, the higher the Q rr will be. Higher Qrr means higher inductive turn-off energy, which directly impacts the height of the voltage overshoot. To assure minimum reverse recovery charge the body diode conduction time has to be minimized, see figure 5. Going from 150ns flooding time to 20ns will in this case decrease the voltage overshoot by 20V. Timings below 20ns are critical, as a current shoot through can easily occur. This means again higher overshoots and worse efficiency. A certain minimum dead time has to be guaranteed over the whole load range, as the timing will Qrr* [nC] vary with current. 60 120 50 100 40 80 30 60 20 40 Qrr* Overshoot 10 Poly. (Overshoot) 20 Poly. (Qrr*) 0 0 20 40 60 80 100 Body diode conduction time [ns] 120 140 0 160 6 Optimizing the Package Looking into the past, the standard package type for a power switch was the TO220 package. The reason for this was the excellent cooling capability and the easy handling at the mounting process. As nowadays the silicon technologies have dramatically improved, the on-state resistances of low voltage power switches are in the range of 2mOhms or less, but the resistive part of the same package stayed the same. This means, the percental resistive contribution of the package to the whole R DS(on) has dramatically increased. Standard through-hole types like the TO220 are now limiting modern silicon technologies. This requires to rethink the packaging strategy towards a lower resistive contribution to get out more of modern silicon switches. [6] 6.1 Package Contribution to the Product RDS(on) Taking modern MOSFET 30V technologies, an on-state resistance as low as 1.2mOhm can be reached in a TO-220 package. Taking into account, that the resistance of the packaging (TO-220) is in the range of 1mOhm, the package contribution to the total R DS(on) is roughly 80%, see figure 6. Accordingly, the resistive silicon content is only about 20%, which clarifies the today’s situation of low ohmic MOSFET silicon. Not the silicon, but the package is hindering lower on-state resistances in standard through-hole packages [5]. Going to SMD package types, like the D²PAK, the influence of the package can already be decreased. A further, much more progressive step is to use leadless SMD package types. This cuts down the package contribution by 50% compared to a TO-220 and enables higher performances of the product. This high resistive package contribution is primarily affecting MOSFETs with lower breakdown-voltage. The higher the MOSFET voltage class, the higher the RDS(on) will be. This in turn means a lower percental contribution of the package resistance to the total R DS(on). Taking a 150V technology, the package contribution is only in the range of 5% to 20%, while for 30V MOSFETs the range is 40% to 80%. 90 80 package contribution [%] 30V 70 60V 60 100V 150V 50 40 30 20 10 0 TO-220 TO-263 - D²PAK leadless SMD Figure 6. Package contribution to the whole resistance of the product 6.2 Improving the Figure of Merit To evaluate the performance of a MOSFET technology, the FOM Qg can give an indication. FOM Qg Rsilicon Qg Equation 17 For a given silicon technology this parameter is a constant, as the capacitances of a MOSFET are indirect proportional to the RDS(on). Taking into account different package types, the FOM Qg is not constant any more. The package resistance adds a constant value to the silicon resistance. FOM Qg Rsilicon Rpackage Qg Equation 18 This results in different FOMQg values for different packages and different RDS(on) classes of a given MOSFET technology. The impact of the package resistance increases as the silicon resistance decreases, see figure 7. The left two bars show two different packages with the same silicon inside. The right side shows the same setup but a higher RDS(on) class. 250 TO-220 leadless SMD FOM [mOhm * nC] 200 25% reduction 150 50% reduction 100 4mOhm 2mOhm 50 3mOhm 1mOhm 0 same silicon low ohmic same silicon high ohmic Figure 7. Impact of the package and the RDS(on) class to the FOMQg For the lower RDS(on) class the package has a much higher influence to the FOM Qg. Changing the package from TO-220 to a leadless SMD version can reduce the FOMQg up to 50% in case of a 2mOhm switch. The higher the RDS(on), the lower the impact of the package. 94 93 efficiency [%] 92 91 leadless SMD 90 TO-220 89 88 10 20 30 output current [A] 40 50 Through an experimental verification of the theory, exactly the forecasted results can be seen (figure 8). The leadless SMD package shows a better efficiency over the whole output load range, although the same silicon is used. 6.3 Improving the Switching Behavior Comparing a leadless package with a TO-220, not only the resistive package contribution is much lower, but also the parasitic inductances are smaller. Due to the leadless design and the bonding with a clip, inductances are fairly reduced and can reach values as low as 0.2nH while a TO-220 package is in the range of 10nH and more. This inductance combined with high di/dt values at the turn-off process of a MOSFET is inducing voltages at the gate connection, which can reach the threshold level. This can provoke an inductive turn-on, resulting in a shoot-through with bad efficiency or even destruction of the switch. Not only inductive turn-on effects but also high voltage overshoots at the turn-off process can occur with TO220 packages. Low inductive leadless SMD packages can minimize this effect. In a 12V synchronous rectification stage, a reduction of 10V could be realized just be replacing the TO-220 package with a low inductive one, see figure 9. With reduced voltage stress smaller voltage classes of the MOSFET can be used to further optimize the system. 90 80 10V reduction overshoot [V] UDS voltage overshoot 70 60 50 40 10 20 30 output current [A] 40 50 7 Conclusion For achieving highest efficiency in synchronous rectification, simply replacing the diodes by MOSFETs will not lead to success. A careful and detailed analysis of the whole system is necessary. By choosing the optimum RDS(on) value of the MOSFET, adjusting the gate timing or adapting the snubber network, higher efficiencies can be achieved and the design process is simplified. A further high potential lever for improved performance is the right choice of the MOSFET package type. Modern silicon technologies are more and more hindered by standard packages and their parasitics. Leadless SMD packages help to improve efficiency and the dynamic behavior by reducing the parasitic resistive and inductive part. Switching losses are reduced and the risk of an inductive turn-on can be minimized, while at the same time voltage overshoots are limited. A combination of all mentioned methods can highly increase the potential for efficiency and improve switching behavior of the SR MOSFET. 8 References [1] http://www.plugloadsolutions.com/80PlusPowerSupplies.aspx, February 2012. [2] C. Mößlacher, Dr. L. Görgens: Improving Efficiency of Synchronous Rectification by Analysis of the MOSFET Power Loss Mechanism, PCIM, 2009, Nürnberg – Germany. [3] Rudy Severns: Design of Snubbers for Power Circuits, www.cde.com/tech/design.pdf, July 2009. [4] Ionel Dan Jitaru: Higher Efficiency Power Conversion through Intelligent Power Processing, Chapter 2, PCIM, 2008, Nürnberg – Germany. [5] Dr. Lutz Görgens, “Maximizing the Effect of Modern Low Voltage Power MOSFETs”, APEC, 2009. [6] Jason Zhang, “Choosing The Right Power MOSFET Package”, Application Note, International Rectifier, February 2004.

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