AT49SN6416(T)

Features
• 1.65V - 1.95V Read/Write
• High Performance
•
•
•
•
•
•
•
•
•
•
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– Random Access Time – 70 ns
– Page Mode Read Time – 20 ns
– Synchronous Burst Frequency – 66 MHz
– Configurable Burst Operation
Sector Erase Architecture
– Eight 4K Word Sectors with Individual Write Lockout
– One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout
Typical Sector Erase Time: 32K Word Sectors – 700 ms; 4K Word Sectors – 200 ms
Four Plane Organization, Permitting Concurrent Read in Any of the Three Planes not
Being Programmed/Erased
– Memory Plane A: 25% of Memory Including Eight 4K Word Sectors
– Memory Plane B: 25% of Memory Consisting of 32K Word Sectors
– Memory Plane C: 25% of Memory Consisting of 32K Word Sectors
– Memory Plane D: 25% of Memory Consisting of 32K Word Sectors
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 35 µA Standby
VPP Pin for Write Protection and Accelerated Program Operations
RESET Input for Device Initialization
CBGA Package
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Common Flash Interface (CFI)
64-megabit
(4M x 16)
Burst/Page
Mode 1.8-volt
Flash Memory
AT49SN6416
AT49SN6416T
1. Description
The AT49SN6416(T) is a 1.8-volt 64-megabit Flash memory. The memory is divided
into multiple sectors and planes for erase operations. The device can be read or
reprogrammed off a single 1.8V power supply, making it ideally suited for In-System
programming. The device can be configured to operate in the asynchronous/page
read (default mode) or burst read mode. The burst read mode is used to achieve a
faster data rate than is possible in the asynchronous/page read mode. If the AVD and
the CLK signals are both tied to GND and the burst configuration register is configured
to perform asynchronous reads, the device will behave like a standard asynchronous
Flash memory. In the page mode, the AVD signal can be tied to GND or can be pulsed
low to latch the page address. In both cases the CLK can be tied to GND.
The AT49SN6416(T) is divided into four memory planes. A read operation can
occur in any of the three planes which is not being programmed or erased. This concurrent operation allows improved system performance by not requiring the system to
wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
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time and let the user read data from or program data to any of the remaining sectors. There is no
reason to suspend the erase or program operation if the data to be read is in another memory
plane.
The VPP pin provides data protection and faster programming times. When the V PP input
is below 0.4V, the program and erase functions are inhibited. When VPP is at 0.9V or above,
normal program and erase operations can be performed. With VPP at 10.0V, the program (Dualword Program command) operation is accelerated.
2. Pin Configurations
2.1
Pin Name
Pin Function
I/O0 - I/O15
Data Inputs/Outputs
A0 - A21
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
AVD
Address Latch Enable
CLK
Clock
RESET
Reset
WP
Write Protect
VPP
Write Protection and Power Supply for Accelerated Program Operations
WAIT
WAIT
VCCQ
Output Power Supply
NC
No Connect
56-ball CBGA (Top View)
1
A
B
C
D
E
F
G
2
2
3
4
5
6
7
8
A11
A8 VSS VCC VPP A18
A6
A4
A12
A9
A20 CLK RESET A17
A5
A3
A13 A10 A21 AVD WE A19
A7
A2
A15 A14 WAIT A16 I/O12 WP
NC
A1
VCCQ I/O15 I/O6 I/O4 I/O2 I/O1 CE
A0
VSS I/O14 I/013 I/O11 I/O10 I/O9 I/O0 OE
I/O7 VSS I/O5 VCC I/O3 VCCQ I/O8 VSS
AT49SN6416(T)
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AT49SN6416(T)
3. Device Operation
3.1
Command Sequences
When the device is first powered on, it will be in the read mode. Command sequences are used
to place the device in other operating modes such as program and erase. The command
sequences are written by applying a low pulse on the WE input with CE low and OE high or by
applying a low-going pulse on the CE input with WE low and OE high. Prior to the low-going
pulse on the CE or WE signal, the address input may be latched by a low-to-high transition on
the AVD signal. If the AVD is not pulsed low, the address will be latched on the first rising edge of
the WE or CE. Valid data is latched on the rising edge of the WE or the CE pulse, whichever
occurs first. The addresses used in the command sequences are not affected by entering the
command sequences.
3.2
Burst Configuration Command
The Program Burst Configuration Register command is used to program the burst configuration
register. The burst configuration register determines several parameters that control the read
operation of the device. Bit B15 determines whether synchronous burst reads are enabled or
asynchronous reads are enabled. Since the page read operation is an asynchronous operation,
bit B15 must be set for asynchronous reads to enable the page read feature. The rest of the bits
in the burst configuration register are used only for the burst read mode. Bits B13 - B11 of the
burst configuration register determine the clock latency for the burst mode. The latency can be
set to two, three, four, five or six cycles. The “Clock Latency versus Input Clock Frequency” table
is shown on page 21. The “Burst Read Waveform” as shown on page 32 illustrates a clock
latency of four; the data is output from the device four clock cycles after the first valid clock edge
following the high-to-low AVD edge. The B10 bit of the configuration register determines the
polarity of the WAIT signal. The B9 bit of the burst configuration register determines the number
of clocks that data will be held valid (see Figure 8-1). The Hold Data for 2 Clock Cycles Read
Waveform is shown on page 32. The clock latency is not affected by the value of the B9 bit. The
B8 bit of the burst configuration register determines when the WAIT signal will be asserted.
When synchronous burst reads are enabled, a linear burst sequence is selected by setting bit
B7. Bit B6 selects whether the burst starts and the data output will be relative to the falling edge
or the rising edge of the clock. Bits B2 - B0 of the burst configuration register determine whether
a continuous or fixed-length burst will be used and also determine whether a four-, eight- or sixteen-word length will be used in the fixed-length mode. All other bits in the burst configuration
register should be programmed as shown on page 21. The default state (after power-up or
reset) of the burst configuration register is also shown on page 21.
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3.3
Asynchronous Read
There are two types of asynchronous reads – AVD pulsed and standard asynchronous reads.
The AVD pulsed read operation of the device is controlled by CE, OE, and AVD inputs. The outputs are put in the high-impedance state whenever CE or OE is high. This dual-line control gives
designers flexibility in preventing bus contention. The data at the address location defined by
A0 - A21 and captured by the AVD signal will be read when CE and OE are low. The address
location passes into the device when CE and AVD are low; the address is latched on the low-tohigh transition of AVD. Low input levels on the OE and CE pins allow the data to be driven out of
the device. The access time is measured from stable address, falling edge of AVD or falling
edge of CE, whichever occurs last. During the AVD pulsed read, the CLK signal may be static
high or static low. For standard asynchronous reads, the AVD and CLK signal should be tied to
GND. The asynchronous read diagrams are shown on page 29.
3.4
Page Read
The page read operation of the device is controlled by CE, OE, and AVD inputs. The CLK input
is ignored during a page read operation and should be tied to GND. The page size is four words.
During a page read, the AVD signal can transition low and then transition high, transition low and
remain low, or can be tied to GND. If a high to low transition on the AVD signal occurs, as shown
in Page Read Cycle Waveform 1, the page address is latched by the low-to-high transition of the
AVD signal. However, if the AVD signal remains low after the high-to-low transition or if the AVD
signal is tied to GND, as shown in Page Read Cycle Waveform 2, then the page address (determined by A21 - A2) cannot change during a page read operation. The first word access of the
page read is the same as the asynchronous read. The first word is read at an asynchronous
speed of 70 ns. Once the first word is read, toggling A0 and A1 will result in subsequent reads
within the page being output at a speed of 20 ns. If the AVD and the CLK pins are both tied to
GND, the device will behave like a standard asynchronous Flash memory. The page read diagrams are shown on page 30.
3.5
Synchronous Reads
Synchronous reads are used to achieve a faster data rate than is possible in the asynchronous/page read mode. The device can be configured for continuous or fixed-length burst
access. The burst read operation of the device is controlled by CE, OE, CLK and AVD inputs.
The initial read location is determined as for the AVD pulsed asynchronous read operation; it can
be any memory location in the device. In the burst access, the address is latched on the first
valid clock edge when AVD is low or the rising edge of the AVD signal, whichever occurs first.
The CLK input signal controls the flow of data from the device for a burst operation. After the
clock latency cycles, the data at the next burst address location is read for each following clock
cycle.
Figure 3-1.
Word Boundary
Word D0 - D3
D0 D1
D2
Word D4 - D7
D3 D4
D5
D6 D7
Word D8 - D11
D8 D9 D10 D11 D12 D13 D14 D15
4-word Boundary
4
Word D12 - D15
16-word Boundary
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AT49SN6416(T)
3.6
Continuous Burst Read
During a continuous burst read, any number of addresses can be read from the memory. When
operating in the linear burst read mode (B7 = 1) with the burst wrap bit (B3 = 1) set, the device
may incur an output delay when the burst sequence crosses the first 16-word boundary in the
memory (see Figure 3-1). If the starting address is aligned with a 4-word boundary (D0, D4, D8
or D12), there is no delay. If the starting address is not aligned with a 4-word boundary, an output delay is incurred. The delay depends on the starting address (see Table 3-1). The delay
takes place only once, and only if the burst sequence crosses a 16-word boundary. To indicate
that the device is not ready to continue the burst, the device will drive the WAIT pin low (B10 and
B8 = 0) during the clock cycles in which new data is not being presented. Once the WAIT pin is
driven high (B10 and B8 = 0), the current data will be valid. The WAIT signal will be tri-stated
when the CE or OE signal is high.
Table 3-1.
Output Delay
Starting Address
Output Delay
Hold Data for 1 Clock Cycle, B9 = 0
Output Delay
Hold Data for 2 Clock Cycles, B9 = 1
D1, D5, D9, D13
1 Clock Cycle
2 Clock Cycle
D2, D6, D10, D14
2 Clock Cycles
4 Clock Cycles
D3, D7, D11, D15
3 Clock Cycles
6 Clock Cycles
In the “Burst Read Waveform” as shown on page 32, the valid address is latched at point A. For
the specified clock latency of four, data D11 is valid within 13 ns of clock edge B. The low-to-high
transition of the clock at point C results in D12 being read. The transition of the clock at point D
results in a burst read of D15. The clock transition at point E does not cause new data to appear
on the output lines because the WAIT signal goes low (B10 and B8 = 0) after the clock transition,
which signifies that the first boundary in the memory has been crossed and that new data is not
available. The clock transition at point F does cause a burst read of data D16 because the WAIT
signal goes high (B10 and B8 = 0) after the clock transition indicating that new data is available.
Additional clock transitions, like at point G, will continue to result in burst reads.
3.7
Fixed-length Burst Reads
During a fixed-length burst mode read, four, eight or sixteen words of data may be burst from the
device, depending upon the configuration. The device supports a linear burst mode. The burst
sequence is shown on page 22. When operating in the linear burst read mode (B7 = 1) with the
burst wrap bit (B3 = 1) set, the device may incur an output delay when the burst sequence
crosses the first 16-word boundary in the memory. If the starting address is aligned with a
4-word boundary (D0, D4, D8 or D12), there is no delay. If the starting address is not aligned
with a 4-word boundary an output delay is incurred. The delay depends on the starting address
(see Table 3-1). The delay takes place only once, and only if the burst sequence crosses a
16-word boundary. To indicate that the device is not ready to continue the burst, the device will
drive the WAIT pin low (B10 and B8 = 0) during the clock cycles in which new data is not being
presented. Once the WAIT pin is driven high (B10 and B8 = 0), the current data will be valid. The
WAIT signal will be tri-stated when the CE or OE signal is high.
The “Four-word Burst Read Waveform” on page 33 illustrates a fixed-length burst cycle. The
valid address is latched at point A. For the specified clock latency of four, data D0 is valid within
13 ns of clock edge B. The low-to-high transition of the clock at point C results in D1 being read.
Similarly, D2 and D3 are output following the next two clock cycles. Returning CE high ends the
read cycle. There is no output delay in the burst access wrap mode (B3 = 0).
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3.8
Burst Suspend
The Burst Suspend feature allows the system to temporarily suspend a synchronous burst operation if the system needs to use the Flash address and data bus for other purposes. Burst
accesses can be suspended during the initial latency (before data is received) or after the device
has output data. When a burst access is suspended, internal array sensing continues and any
previously latched internal data is retained.
Burst Suspend occurs when CE is asserted, the current address has been latched (either rising
edge of AVD or valid CLK edge), CLK is halted, and OE is deasserted. The CLK can be halted
when it is at VIH or VIL. To resume the burst access, OE is reasserted and the CLK is restarted.
Subsequent CLK edges resume the burst sequence where it left off.
Within the device, OE gates the WAIT signal. Therefore, during Burst Suspend the WAIT signal
reverts to a high-impedance state when OE is deasserted. See “Burst Suspend Waveform” on
page 33.
3.9
Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET pin halts the
present device operation and puts the outputs of the device in a high-impedance state. When a
high level is reasserted on the RESET pin, the device returns to read mode.
3.10
Erase
Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a
logical “1”. The entire memory can be erased by using the Chip Erase command or individual
planes can be erased by using the Plane Erase command or individual sectors can be erased by
using the Sector Erase command.
3.10.1
Chip Erase
Chip Erase is a two-bus cycle operation. The automatic erase begins on the rising edge of the
last WE pulse. Chip Erase does not alter the data of the protected sectors. The hardware reset
during chip erase will stop the erase, but the data will be of an unknown state.
3.10.2
Plane Erase
As an alternative to a full Chip Erase, the device is organized into four planes that can be individually erased. The Plane Erase command is a two-bus cycle operation. The plane whose address
is valid at the second rising edge of WE will be erased. The Plane Erase command does not
alter the data in the protected sectors.
3.10.3
Sector Erase
The device is organized into multiple sectors that can be individually erased. The Sector Erase
command is a two-bus cycle operation. The sector whose address is valid at the second rising
edge of WE will be erased provided the given sector has not been protected.
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AT49SN6416(T)
3.11
Word Programming
The device is programmed on a word-by-word basis. Programming is accomplished via the
internal device command register and is a two-bus cycle operation. The programming address
and data are latched in the second cycle. The device will automatically generate the required
internal programming pulses. Please note that a “0” cannot be programmed back to a “1”; only
erase operations can convert “0”s to “1”s.
3.12
Flexible Sector Protection
The AT49SN6416(T) offers two sector protection modes, the Softlock and the Hardlock. The
Softlock mode is optimized as sector protection for sectors whose content changes frequently.
The Hardlock protection mode is recommended for sectors whose content changes infrequently.
Once either of these two modes is enabled, the contents of the selected sector is read-only and
cannot be erased or programmed. Each sector can be independently programmed for either the
Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled.
3.12.1
Softlock and Unlock
The Softlock protection mode can be disabled by issuing a two-bus cycle Unlock command to
the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To
enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the
selected sector.
3.12.2
Hardlock and Write Protect (WP)
The Hardlock sector protection mode operates in conjunction with the Write Protection (WP) pin.
The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock software command to the selected sector. The state of the Write Protect pin affects whether the
Hardlock protection mode can be overridden.
• When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be
unlocked and the contents of the sector is read-only.
• When the WP pin is high, the Hardlock protection mode is overridden and the sector can be
unlocked via the Unlock command.
To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.
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Table 3-2.
Hardlock and Softlock Protection Configurations in Conjunction with WP
Softlock
Erase/
Prog
Allowed?
VPP
WP
Hardlock
VCC
0
0
0
Yes
No sector is locked
VCC
0
0
1
No
Sector is Softlocked. The Unlock
command can unlock the sector.
VCC
0
1
1
No
Hardlock protection mode is
enabled. The sector cannot be
unlocked.
VCC
1
0
0
Yes
No sector is locked.
VCC
1
0
1
No
Sector is Softlocked. The Unlock
command can unlock the sector.
VCC
1
1
0
Yes
Hardlock protection mode is
overridden and the sector is not
locked.
Comments
VCC
1
1
1
No
Hardlock protection mode is
overridden and the sector can be
unlocked via the Unlock
command.
VIL
x
x
x
No
Erase and Program Operations
cannot be performed.
Figure 3-2.
Sector Locking State Diagram
UNLOCKED
LOCKED
60h/
D0h
60h/01h
[000]
[001]
60
h/2
Fh
Power-Up/Reset
Default
60h/
2Fh
WP = VIL = 0
Hardlocked
[011]
60h/D0h
[110]
60h/
01h
60h/
2Fh
WP = VIH = 1
60h/
D0h
[100]
Hardlocked is disabled by
WP = VIH
[111]
60h/
2Fh
Power-Up/Reset
Default
60h/
01h
[101]
60h/D0h = Unlock Command
60h/01h = Softlock Command
60h/2Fh = Hardlock Command
Note:
8
1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a sector
is defined by the state of WP and the two bits of the sector-lock status D[1:0].
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AT49SN6416(T)
3.12.3
Sector Protection Detection
A software method is available to determine if the sector protection Softlock or Hardlock features
are enabled. When the device is in the software product identification mode a read from the I/O0
and I/O1 at address location 00002H within a sector will show if the sector is unlocked, softlocked, or hardlocked.
Table 3-3.
3.13
Sector Protection Status
I/O1
I/O0
Sector Protection Status
0
0
Sector Not Locked
0
1
Softlock Enabled
1
0
Hardlock Enabled
1
1
Both Hardlock and Softlock Enabled
Read Status Register
The status register indicates the status of device operations and the success/failure of that operation. The Read Status Register command causes subsequent reads to output data from the
status register until another command is issued. To return to reading from the memory, issue a
Read command.
The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H
when a Read Status Register command is issued.
The contents of the status register [SR7:SR0] are latched on the falling edge of OE or CE
(whichever occurs last), which prevents possible bus errors that might occur if status register
contents change while being read. CE or OE must be toggled with each subsequent status read,
or the status register will not indicate completion of a Program or Erase operation.
When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the
remaining bits in the status register indicate whether the WSM was successful in performing the
preferred operation (see Table 3-4).
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3.14
Read Status Register In The Burst Mode
The waveform below shows a status register read during a program operation. The two-bus
cycle command for a program operation is given followed by a read status register command.
Following the read status register command, the AVD signal is pulsed low to latch the valid
address at point A. With the OE signal pulsed low and for the specified clock latency of three, the
status register output is valid within 13 ns from clock edge B. The same status register data is
output on successive clock edges. To update the status register output, the AVD signal needs to
be pulsed low and the next data is available after a clock latency of three. The status register
output is also available after the chosen clock latency during an erase operation.
Figure 3-3.
Read Status Register in the Burst Mode
A
B
CLK
CE
OE
AVD
WE
A0 - A21
I/O0 - I/O15
WAIT
Note:
10
XX
ADDRESS
40H/10H
DATA
70H
00H
80H
(1)
1. The WAIT signal is for a burst configuration setting of B10 and B8 = 0.
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AT49SN6416(T)
Table 3-4.
Status Register Bit Definition
WSMS
ESS
ES
PRS
VPPS
PSS
SLS
PLS
7
6
5
4
3
2
1
0
Notes
SR7 WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check Write State Machine bit first to determine Word Program
or Sector Erase completion, before checking program or erase
status bits.
SR6 = ERASE SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1” – ESS bit remains set to “1” until
an Erase Resume command is issued.
SR5 = ERASE STATUS (ES)
1 = Error in Sector Erase
0 = Successful Sector Erase
When this bit is set to “1”, WSM has applied the max number of
erase pulses to the sector and is still unable to verify successful
sector erasure.
SR4 = PROGRAM STATUS (PRS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1”, WSM has attempted but failed to
program a word
SR3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP status bit does not provide continuous indication of VPP
level. The WSM interrogates VPP level only after the Program or
Erase command sequences have been entered and informs the
system if VPP has not been switched on. The VPP is also checked
before the operation is verified by the WSM.
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1”. PSS bit remains set to “1”
until a Program Resume command is issued.
SR1 = SECTOR LOCK STATUS
1 = Prog/Erase attempted on a locked sector; Operation aborted.
0 = No operation to locked sectors
If a Program or Erase operation is attempted to one of the locked
sectors, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
SR0 = Plane Status (PLS)
Indicates program or erase status of the addressed plane.
Note:
1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.
Table 3-5.
Status Register Device WSMS and Write Status Definition
WSMS
(SR7)
PLS
(SR0)
0
0
The addressed plane is performing a program/erase operation.
0
1
A plane other than the one currently addressed is performing a program/erase operation.
1
x
No program/erase operation is in progress in any plane. Erase and Program suspend bits (SR6, SR2)
indicate whether other planes are suspended.
Description
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3.15
Erase Suspend/erase Resume
The Erase Suspend command allows the system to interrupt a sector erase or plane erase operation. The erase suspend command does not work with the Chip Erase feature. Using the erase
suspend command to suspend a sector erase operation, the system can program or read data
from a different sector within the same plane. Since this device is organized into four planes,
there is no need to use the erase suspend feature while erasing a sector when you want to read
data from a sector in another plane. After the Erase Suspend command is given, the device
requires a maximum time of 15 µs to suspend the erase operation. After the erase operation has
been suspended, the plane that contains the suspended sector enters the erase-suspend-read
mode. The system can then read data or program data to any other sector within the device. An
address is not required during the Erase Suspend command. During a sector erase suspend,
another sector cannot be erased. To resume the sector erase operation, the system must write
the Erase Resume command. The Erase Resume command is a one-bus cycle command,
which does require the plane address. Read, Read Status Register, Product ID Entry, Clear Status Register, Program, Program Suspend, Erase Resume, Sector Softlock/Hardlock, Sector
Unlock are valid commands during an erase suspend.
3.16
Program Suspend/program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different word within the memory. After the Program Suspend command is
given, the device requires a maximum of 10 µs to suspend the programming operation. After the
programming operation has been suspended, the system can then read from any other word
within the device. An address is not required during the program suspend operation. To resume
the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the
erase suspend and program suspend are the same, and the command sequence for the erase
resume and program resume are the same. Read, Read Status Register, Product ID Entry, Program Resume are valid commands during a Program Suspend.
3.17
128-bit Protection Register
The AT49SN6416(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are
designated as block A and block B. The data in block A is non-changeable and is programmed
at the factory with a unique number. The data in block B is programmed by the user and can be
locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the two-bus cycle Program Protection Register command must be used as
shown in the “Command Definition Table” on page 19. To lock out block B, the two-bus cycle
lock protection register command must be used as shown in the “Command Definition Table”.
Data bit D1 must be zero during the second bus cycle. All other data bits during the second bus
cycle are don’t cares. To determine whether block B is locked out, the status of sector B command is given. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be
reprogrammed. Please see the “Protection Register Addressing Table” on page 20 for the
address locations in the protection register. To read the protection register, the Product ID Entry
command is given followed by a normal read operation from an address within the protection
register. After determining whether block B is protected or not or reading the protection register,
the Read command must be given to return to the read mode.
12
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
3.18
Common Flash Interface (CFI)
CFI is a published, standardized data structure that may be read from a flash device. CFI allows
system software to query the installed device to determine the configurations, various electrical
and timing parameters, and functions supported by the device. CFI is used to allow the system
to learn how to interface to the flash device most optimally. The two primary benefits of using
CFI are ease of upgrading and second source availability. The command to enter the CFI Query
mode is a one-bus cycle command which requires writing data 98h to any address. The CFI
Query command can be written when the device is ready to read data or can also be written
when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI
data at the addresses given in “Common Flash Interface Definition Table” on page 37. To return
to the read mode, the read command should be issued.
3.19
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49SN6416(T) in the following
ways: (a) VCC sense: if VCC is below 1.2V (typical), the device is reset and the program and
erase functions are inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense
level, the device will automatically time-out 10 ms (typical) before programming. (c) Program
inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
(e) VPP is less than VILPP.
3.20
Input Levels
While operating with a 1.65V to 1.95V power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 2.5V without adversely affecting the operation of the
device. The I/O lines can be driven from 0 to VCCQ + 0.6V.
3.21
Output Levels
For the AT49SN6416(T), output high levels are equal to VCCQ - 0.1V (not VCC). VCCQ must be
regulated between 1.65V - 2.25V.
13
3464C–FLASH–2/05
3.22
Word Program Flowchart
3.23
Word Program Procedure
Bus
Operation
Start
Write 40,
Word Address
Write Data,
Word Address
Command
Write
Program
Setup
Data = 40
Addr = Location to program
Write
Data
Data = Data to program
Addr = Location to program
Read
None
Status register data: Toggle CE
or
OE to update status register
Idle
None
Check SR7
1 = WSM Ready
0 = WSM Busy
(Setup)
(Confirm)
Program
Suspend
Loop
Read Status
Register
No
0
SR7 =
Suspend?
Yes
1
Full Status
Check
(If Desired)
Comments
Repeat for subsequent Word Program operations.
Full status register check can be done after each program, or
after a sequence of program operations.
Write FF after the last operation to set to the Read state.
Program
Complete
3.24
Full Status Check Flowchart
Read Status
Register
SR3 =
1
VP P Range
Error
3.25
Full Status Check Procedure
Bus
Operation
Command
Idle
None
Check SR3:
1 = VPP Error
Idle
None
Check SR4:
1 = Data Program Error
Idle
None
Check SR1:
1 = Sector locked; operation
aborted
0
SR4 =
1
Program
Error
0
SR1 =
1
Device
Protect Error
0
Comments
SR3 MUST be cleared before the Write State Machine allows
further program attempts.
If an error is detected, clear the status register before
continuing operations – only the Clear Status Register
command clears the status register error bits.
Program
Successful
14
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
3.26
Program Suspend/Resume Flowchart
Program Suspend/Resume Procedure
Bus
Operation
Start
Write B0
Any Address
3.27
(Program Suspend)
Write 70
Any Address
(Read Status)
within
the Same Plane
Command
Program
Suspend
Write
Read
Status
Data = 70
Addr = Any address within the
Same Plane
Read
None
Status register data: Toggle CE
or
OE to update status register
Addr = Any address
Idle
None
Check SR7
1 = WSM Ready
0 = WSM Busy
Idle
None
Check SR2
1 = Program suspended
0 = Program completed
Write
Read Array
Read
None
Write
Program
Resume
0
1
SR2 =
0
Program
Completed
1
Write FF
Suspend Plane
(Read Array)
Read
Data
Done
Reading
Write FF
No
Read
Data
Yes
Write D0
Any Address
(Program Resume)
Program
Resumed
Write 70H
Any Address
within
the Same Plane
(Read
Array)
Data = B0
Addr = Sector address to
Suspend (SA)
Write
Read Status
Register
SR7 =
Comments
Data = FF
Addr = Any address within the
Suspended Plane
Read data from any sector in the
memory other than the one being
programmed
Data = D0
Addr = Any address
If the Suspend Plane was placed in Read mode:
(Read Status)
Write
Read
Status
Return Plane to Status mode:
Data = 70
Addr = Any address within the
Same Plane
15
3464C–FLASH–2/05
3.28
Erase Suspend/Resume Flowchart
3.29
Erase Suspend/Resume Procedure
Bus
Operation
Start
Write B0,
Any Address
(Erase Suspend)
Write 70,
Any Address
(Read Status)
Command
0
Erase
Suspend
Write
Read
Status
Data = 70
Addr = Any address
Read
None
Status register data: Toggle CE
or
OE to update status register
Addr = Any address within the
Same Plane
Idle
None
Check SR7
1 = WSM Ready
0 = WSM Busy
Idle
None
Check SR6
1 = Erase suspended
0 = Erase completed
Write
Read or
Program
Read or
Write
None
Write
Program
Resume
1
SR6 =
0
Erase
Completed
1
Read
or Program?
Read
No
Program
Loop
Done?
Yes
(Erase Resume)
Write D0,
Any Address
Write FF
Erase
Resumed
Read Array
Data
Write 70H
Any Address
within
the Same Plane
(Read Status)
(Read Array)
Data = FF or 40
Addr = Any address
Read or program data from/to
sector other than the one being
erased
Data = D0
Addr = Any address
If the Suspended Plane was placed in Read mode or a
Program loop:
Write
16
Data = B0
Addr = Any address within the
Same Plane
Write
Read Status
Register
SR7 =
Comments
Read
Status
Return Plane to Status mode:
Data = 70
Addr = Any address within the
Same Plane
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
3.30
Sector Erase Flowchart
3.31
Sector Erase Procedure
Bus
Operation
Start
Write 20,
Sector Address
(Sector Erase)
Write D0,
(Erase Confirm)
Sector Address
Suspend
Erase
Loop
Read Status
Register
Command
Write
Sector
Erase
Setup
Data = 20
Addr = Sector to be erased (SA)
Write
Erase
Confirm
Data = D0
Addr = Sector to be erased (SA)
Read
None
Status register data: Toggle CE
or
OE to update status register data
Idle
None
Check SR7
1 = WSMS Ready
0 = WSMS Busy
No
Suspend
Erase
0
SR7 =
Yes
1
Full Erase
Status Check
(If Desired)
Repeat for subsequent sector erasures.
Full status register check can be done after each sector erase,
or after a sequence of sector erasures.
Write FF after the last operation to enter read mode.
Sector Erase
Complete
3.32
Comments
Full Erase Status Check Flowchart
Full Erase Status Check Procedure
Bus
Operation
Command
Idle
None
Check SR3:
1 = VPP Range Error
Command
Sequence Error
Idle
None
Check SR4, SR5:
Both 1 = Command Sequence
Error
1
Sector Erase
Error
Idle
None
Check SR5:
1 = Sector Erase Error
1
Sector Locked
Error
Idle
None
Check SR1:
1 = Attempted erase of locked
sector; erase aborted.
Read Status
Register
SR3 =
3.33
1
VP P Range
Error
0
SR4, SR5 =
1,1
0
SR5 =
Comments
0
SR1 =
0
Sector Erase
Successful
SR1, SR3 must be cleared before the Write State Machine
allows further erase attempts.
Only the Clear Status Register command clears SR1, SR3,
SR4, SR5.
If an error is detected, clear the status register before
attempting an erase retry or other error recovery.
17
3464C–FLASH–2/05
3.34
Protection Register Programming
Flowchart
Write C0,
PR Address
Write PR
Address & Data
SR7 =
Program
PR Setup
Data = C0
Addr = First Location to Program
(Confirm Data)
Write
Protection
Program
Data = Data to Program
Addr = Location to Program
Read
None
Status register data: Toggle CE
or
OE to update status register data
Idle
None
Check SR7
1 = WSMS Ready
0 = WSMS Busy
0
Full Status
Check
(If Desired)
Program Protection Register operation addresses must be
within the protection register address space. Addresses
outside this space will return an error.
Repeat for subsequent programming operations.
Full status register check can be done after each program, or
after a sequence of program operations.
Write FF after the last operation to return to the Read mode.
Program
Complete
Full Status Check Flowchart
Read Status
Register Data
0, 1
1, 1
Register Locked;
Program Aborted
0
Program
Successful
18
Full Status Check Procedure
Bus
Operation
Command
Idle
None
Check SR1, SR3, SR4:
0,1,1 = VPP Range Error
Idle
None
Check SR1, SR3, SR4:
0,0,1 = Programming Error
Idle
None
Check SR1, SR3, SR4:
1, 0,1 = Sector locked; operation
aborted
Program Error
0
SR1, SR4 =
3.37
VP P Range Error
0
SR1, SR4 =
Comments
Write
1
1, 1
Command
(Program Setup)
Read Status
Register
SR3, SR4 =
Protection Register Programming
Procedure
Bus
Operation
Start
3.36
3.35
Comments
SR3 must be cleared before the Write State Machine allows
further program attempts.
Only the Clear Status Register command clears SR1, SR3,
SR4.
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
4. Command Definition Table
Command
Sequence
Bus
Cycles
1st Bus
Cycle
Addr
2nd Bus
Cycle
Data
(2)
Addr
Data
Read
1
Chip Erase
2
XX
21
Addr
D0
Plane Erase
2
XX
22
Addr
D0
20
(3)
D0
Sector Erase
2
Word Program
Dual Word Program
(10)
Erase/Program Suspend
Erase/Program Resume
Product ID Entry
(11)(12)
Sector Softlock
Sector Hardlock
Sector Unlock
SA
(4)
3
Addr0
E0
1
XX
B0
1
2
2
2
2
Clear Status Register
1
Lock Protection Register – Sector B
(3)
Addr
1
2
2
40/10
SA
(4)
Addr
DIN
Addr0
DIN0
(2)
D0
(2)
90
SA
(3)
60
SA(3)
01
SA
(3)
60
(3)
2F
(3)
D0
PA
PA
(3)
60
(2)
70
SA
PA
XX
SA
SA
XX
C0
(13)
(13)
C0
XX(9)
XXXX 80
FFFD
(13)
DOUT(6)
XXXX 80
90
XXXX 80
Program Burst Configuration Register
2
Addr(7)
60
Addr(7)
90
(8)
CFI Query
1
Notes:
DIN1
DIN
(13)
2
2
Addr1
DOUT(5)
XX
Status of Sector B Protection
Read Burst Configuration Register
Data
50
(9)
XXXX 80
Addr
FF
2
Read Status Register
Program Protection Register
PA
3rd Bus
Cycle
(2)
PA
XX
XXX
03
DOUT
98
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS
FORMAT shown for each bus cycle is as follows: A7 - A0 (Hex). Address A21 through A8 are don’t care.
2. PA is the plane address (A21 - A20). Any address within a plane can be used.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 23 - 26 for
details).
4. The first bus cycle address should be the same as the word address to be programmed.
5. The status register bits are output on I/O7 - I/O0.
6. If data bit D1 is “0”, sector B is locked. If data bit D1 is “1”, sector B can be reprogrammed.
7. See “Burst Configuration Register Table” on page 21. Bits B15 - B0 of the burst configuration register determine A15 - A0.
Addresses A16 - A21 can select any plane.
For the AT49SN6416T:
8. For the AT49SN6416:
xxx = 000005 Burst Configuration Register Data from Plane A
xxx = 100005 Burst Configuration Register Data from Plane B
xxx = 200005 Burst Configuration Register Data from Plane C
xxx = 300005 Burst Configuration Register Data from Plane D
xxx = 000005 Burst Configuration Register Data from Plane D
xxx = 100005 Burst Configuration Register Data from Plane C
xxx = 200005 Burst Configuration Register Data from Plane B
xxx = 300005 Burst Configuration Register Data from Plane A
9. Any address within the user programmable protection register region. Please see “Protection Register Addressing Table” on
page 20.
10. This fast programming option enables the user to program two words in parallel only when VPP = 10V. The addresses, Addr0
and Addr1, of the two words, DIN0 and DIN1, must only differ in address A0. This command should be used during manufacturing purposes only.
11. During the second bus sycle, the manufacturer code is read from address PA+00000H, the device code is read from address
PA+00001H, and the data in the protection register is read from addresses 000081H - 000088H (AT49SN6416) or
addresses 3F8081H - 3F8088H (AT49SN6416T).
12. The plane address should be the same during the first and second bus cycle.
13. For the AT49SN6416, xxxx = 0000H. For the AT49SN6416T, xxxx = 3F80H.
19
3464C–FLASH–2/05
5. Absolute Maximum Ratings*
*NOTICE:
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages Except VPP
(Including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
VPP Input Voltage
with Respect to Ground ......................................... 0V to 10.0V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
All Output Voltages
with Respect to Ground ...........................-0.6V to VCCQ + 0.6V
6. Protection Register Addressing Table
Word
Use
Block
A7
A6
A5
A4
A3
A2
A1
A0
0
Factory
A
1
0
0
0
0
0
0
1
1
Factory
A
1
0
0
0
0
0
1
0
2
Factory
A
1
0
0
0
0
0
1
1
3
Factory
A
1
0
0
0
0
1
0
0
4
User
B
1
0
0
0
0
1
0
1
5
User
B
1
0
0
0
0
1
1
0
6
User
B
1
0
0
0
0
1
1
1
7
User
B
1
0
0
0
1
0
0
0
Notes:
20
1. For the AT49SN6416, all address lines not specified in the above table, A21 - A8, must be 0 when accessing the Protection
Register.
2. For the AT49SN6416T, all address lines not specified in the above table, A21 - A8, must be 3F80H when accessing the
Protection Register.
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
7. Burst Configuration Register Table
B15 Program (AT49SN6416)
B15 Program (AT49SN6416T)
B15 Read
0
Synchronous Burst Reads Enabled
1(1)
Asynchronous BurstReads Enabled
1
Synchronous Burst Reads Enabled
0(1)
Asynchronous BurstReads Enabled
0
Synchronous Burst Reads Enabled
1
Asynchronous BurstReads Enabled
B14
Reserved for future use
B13 - B11:(2)
B10
B9
B8
Clock Latency of Two
011
Clock Latency of Three
100
Clock Latency of Four
101
Clock Latency of Five
110(1)
Clock Latency of Six
0
WAIT Signal is Asserted Low
1(1)(3)
WAIT Signal is Asserted High
0
Hold Data for One Clock
1(1)
Hold Data for Two Clocks
0
WAIT Asserted during Clock Cycle in which Data is Valid
1(1)
B7
1
WAIT Asserted One Clock Cycle before Data is Valid
(1)
Linear Burst Sequence
Burst Starts and Data Output on Falling Clock Edge
0
B6
1(1)
B5 - B4
00
B3
B2 - B0
Notes:
010
Burst Starts and Data Output on Rising Clock Edge
(1)
Reserved for Future Use
0
Reserved for future use
1(1)
Don’t Wrap Accesses Within Burst Length set by B2 - B0
001
Four-word Burst
010
Eight-word Burst
011
Sixteen-word Burst
111(1)
Continuous Burst
1. Default State
2. Burst configuration setting of B13 - B11 = 010 (clock latency of two), B9 = 1 (hold data for two clock cycles) and B8 = 1
(WAIT asserted one clock cycle before data is valid) is not supported.
3. Data is not ready when WAIT is asserted.
8. Clock Latency versus Input Clock Frequency
Minimum Clock Latency
(Minimum Number of Clocks Following Address Latch)
Input Clock Frequency
5, 6
≤ 66 MHz
4
≤ 61 MHz
2, 3
≤ 40 MHz
Figure 8-1.
Output Configuration
CLK
1 CLK
Data Hold
(B9 = 0)
I/00 - I/015
2 CLK
Data Hold
(B9 = 1)
I/00 - I/015
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
21
3464C–FLASH–2/05
9. Sequence and Burst Length
Burst Addressing Sequence (Decimal)
4-word Burst Length
B2 – B0 = 001
8-word Burst Length
B2 – B0 = 010
16-word Burst Length
B2 – B0 = 011
Continuous Burst
B2 – B0 = 111
Linear
Linear
Linear
Linear
Start Addr.
(Decimal)
Wrap
B3 = 1
0
1
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2...14-15
0-1-2-3-4-5-6...
1
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3...15-16
1-2-3-4-5-6-7...
2
1
2-3-4-5
2-3-4-5-6-7-8-9
2-3-4...16-17
2-3-4-5-6-7-8...
3
1
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5...17-18
3-4-5-6-7-8-9...
4
1
4-5-6-7-8-9-10-11
4-5-6...18-19
4-5-6-7-8-9-10...
5
1
5-6-7-8-9-10-11-12
5-6-7...19-20
5-6-7-8-9-10-11...
6
1
6-7-8-9-10-11-12-13
6-7-8...20-21
6-7-8-9-10-11-12...
7
1
7-8-9-10-11-12-13-14
7-8-9...21-22
7-8-9-10-11-12-13...
...
...
...
...
...
14
1
14-15...28-29
14-15-16-17-18-19-20
15
1
15-16...29-30
15-16-17-18-19-20-21
22
...
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
10. Memory Organization –
AT49SN6416
10. Memory Organization –
AT49SN6416 (Continued)
x16
Plane
Sector
x16
Size (Words)
Address Range (A21 - A0)
Plane
Sector
Size (Words)
Address Range (A21 - A0)
A
SA0
4K
00000 - 00FFF
A
SA36
32K
E8000 - EFFFF
A
SA1
4K
01000 - 01FFF
A
SA37
32K
F0000 - F7FFF
A
SA2
4K
02000 - 02FFF
A
SA38
32K
F8000 - FFFFF
A
SA3
4K
03000 - 03FFF
B
SA39
32K
100000 - 107FFF
A
SA4
4K
04000 - 04FFF
B
SA40
32K
108000 - 10FFFF
A
SA5
4K
05000 - 05FFF
B
SA41
32K
110000 - 117FFF
A
SA6
4K
06000 - 06FFF
B
SA42
32K
118000 - 11FFFF
A
SA7
4K
07000 - 07FFF
B
SA43
32K
120000 - 127FFF
A
SA8
32K
08000 - 0FFFF
B
SA44
32K
128000 - 12FFFF
A
SA9
32K
10000 - 17FFF
B
SA45
32K
130000 - 137FFF
A
SA10
32K
18000 - 1FFFF
B
SA46
32K
138000 - 13FFFF
A
SA11
32K
20000 - 27FFF
B
SA47
32K
140000 - 147FFF
A
SA12
32K
28000 - 2FFFF
B
SA48
32K
148000 - 14FFFF
A
SA13
32K
30000 - 37FFF
B
SA49
32K
150000 - 157FFF
A
SA14
32K
38000 - 3FFFF
B
SA50
32K
158000 - 15FFFF
A
SA15
32K
40000 - 47FFF
B
SA51
32K
160000 - 167FFF
A
SA16
32K
48000 - 4FFFF
B
SA52
32K
168000 - 16FFFF
A
SA17
32K
50000 - 57FFF
B
SA53
32K
170000 - 177FFF
A
SA18
32K
58000 - 5FFFF
B
SA54
32K
178000 - 17FFFF
A
SA19
32K
60000 - 67FFF
B
SA55
32K
180000 - 187FFF
A
SA20
32K
68000 - 6FFFF
B
SA56
32K
188000 - 18FFFF
A
SA21
32K
70000 - 77FFF
B
SA57
32K
190000 - 197FFF
A
SA22
32K
78000 - 7FFFF
B
SA58
32K
198000 - 19FFFF
A
SA23
32K
80000 - 87FFF
B
SA59
32K
1A0000 - 1A7FFF
A
SA24
32K
88000 - 8FFFF
B
SA60
32K
1A8000 - 1AFFFF
A
SA25
32K
90000 - 97FFF
B
SA61
32K
1B0000 - 1B7FFF
A
SA26
32K
98000 - 9FFFF
B
SA62
32K
1B8000 - 1BFFFF
A
SA27
32K
A0000 - A7FFF
B
SA63
32K
1C0000 - 1C7FFF
A
SA28
32K
A8000 - AFFFF
B
SA64
32K
1C8000 - 1CFFFF
A
SA29
32K
B0000 - B7FFF
B
SA65
32K
1D0000 - 1D7FFF
A
SA30
32K
B8000 - BFFFF
B
SA66
32K
1D8000 - 1DFFFF
A
SA31
32K
C0000 - C7FFF
B
SA67
32K
1E0000 - 1E7FFF
A
SA32
32K
C8000 - CFFFF
B
SA68
32K
1E8000 - 1EFFFF
A
SA33
32K
D0000 - D7FFF
B
SA69
32K
1F0000 - 1F7FFF
A
SA34
32K
D8000 - DFFFF
B
SA70
32K
1F8000 - 1FFFFF
A
SA35
32K
E0000 - E7FFF
C
SA71
32K
200000 - 207FFF
23
3464C–FLASH–2/05
10. Memory Organization –
AT49SN6416 (Continued)
10. Memory Organization –
AT49SN6416 (Continued)
x16
Plane
24
Sector
x16
Size (Words)
Address Range (A21 - A0)
Plane
Sector
Size (Words)
Address Range (A21 - A0)
C
SA72
32K
208000 - 20FFFF
D
SA103
32K
300000 - 307FFF
C
SA73
32K
210000 - 217FFF
D
SA104
32K
308000 - 30FFFF
C
SA74
32K
218000 - 21FFFF
D
SA105
32K
310000 - 317FFF
C
SA75
32K
220000 - 227FFF
D
SA106
32K
318000 - 31FFFF
C
SA76
32K
228000 - 22FFFF
D
SA107
32K
320000 - 327FFF
C
SA77
32K
230000 - 237FFF
D
SA108
32K
328000 - 32FFFF
C
SA78
32K
238000 - 23FFFF
D
SA109
32K
330000 - 337FFF
C
SA79
32K
240000 - 247FFF
D
SA110
32K
338000 - 33FFFF
C
SA80
32K
248000 - 24FFFF
D
SA111
32K
340000 - 347FFF
C
SA81
32K
250000 - 257FFF
D
SA112
32K
348000 - 34FFFF
C
SA82
32K
258000 - 25FFFF
D
SA113
32K
350000 - 357FFF
C
SA83
32K
260000 - 267FFF
D
SA114
32K
358000 - 35FFFF
C
SA84
32K
268000 - 26FFFF
D
SA115
32K
360000 - 367FFF
C
SA85
32K
270000 - 277FFF
D
SA116
32K
368000 - 36FFFF
C
SA86
32K
278000 - 27FFFF
D
SA117
32K
370000 - 377FFF
C
SA87
32K
280000 - 287FFF
D
SA118
32K
378000 - 37FFFF
C
SA88
32K
288000 - 28FFFF
D
SA119
32K
380000 - 387FFF
C
SA89
32K
290000 - 297FFF
D
SA120
32K
388000 - 38FFFF
C
SA90
32K
298000 - 29FFFF
D
SA121
32K
390000 - 397FFF
C
SA91
32K
2A0000 - 2A7FFF
D
SA122
32K
398000 - 39FFFF
C
SA92
32K
2A8000 - 2AFFFF
D
SA123
32K
3A0000 - 3A7FFF
C
SA93
32K
2B0000 - 2B7FFF
D
SA124
32K
3A8000 - 3AFFFF
C
SA94
32K
2B8000 - 2BFFFF
D
SA125
32K
3B0000 - 3B7FFF
C
SA95
32K
2C0000 - 2C7FFF
D
SA126
32K
3B8000 - 3BFFFF
C
SA96
32K
2C8000 - 2CFFFF
D
SA127
32K
3C0000 - 3C7FFF
C
SA97
32K
2D0000 - 2D7FFF
D
SA128
32K
3C8000 - 3CFFFF
C
SA98
32K
2D8000 - 2DFFFF
D
SA129
32K
3D0000 - 3D7FFF
C
SA99
32K
2E0000 - 2E7FFF
D
SA130
32K
3D8000 - 3DFFFF
C
SA100
32K
2E8000 - 2EFFFF
D
SA131
32K
3E0000 - 3E7FFF
C
SA101
32K
2F0000 - 2F7FFF
D
SA132
32K
3E8000 - 3EFFFF
C
SA102
32K
2F8000 - 2FFFFF
D
SA133
32K
3F0000 - 3F7FFF
D
SA134
32K
3F8000 - 3FFFFF
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
11. Memory Organization –
AT49SN6416T (Continued)
11. Memory Organization –
AT49SN6416T
x16
x16
Plane
Sector
Size (Words)
Address Range (A21 - A0)
Plane
Sector
Size (Words)
Address Range (A21 - A0)
D
SA0
32K
00000 - 07FFF
C
SA36
32K
120000 - 127FFF
D
SA1
32K
08000 - 0FFFF
C
SA37
32K
128000 - 12FFFF
D
SA2
32K
10000 - 17FFF
C
SA38
32K
130000 - 137FFF
D
SA3
32K
18000 - 1FFFF
C
SA39
32K
138000 - 13FFFF
D
SA4
32K
20000 - 27FFF
C
SA40
32K
140000 - 147FFF
D
SA5
32K
28000 - 2FFFF
C
SA41
32K
148000 - 14FFFF
D
SA6
32K
30000 - 37FFF
C
SA42
32K
150000 - 157FFF
D
SA7
32K
38000 - 3FFFF
C
SA43
32K
158000 - 15FFFF
D
SA8
32K
40000 - 47FFF
C
SA44
32K
160000 - 167FFF
D
SA9
32K
48000 - 4FFFF
C
SA45
32K
168000 - 16FFFF
D
SA10
32K
50000 - 57FFF
C
SA46
32K
170000 - 177FFF
D
SA11
32K
58000 - 5FFFF
C
SA47
32K
178000 - 17FFFF
D
SA12
32K
60000 - 67FFF
C
SA48
32K
180000 - 187FFF
D
SA13
32K
68000 - 6FFFF
C
SA49
32K
188000 - 18FFFF
D
SA14
32K
70000 - 77FFF
C
SA50
32K
190000 - 197FFF
D
SA15
32K
78000 - 7FFFF
C
SA51
32K
198000 - 19FFFF
D
SA16
32K
80000 - 87FFF
C
SA52
32K
1A0000 - 1A7FFF
D
SA17
32K
88000 - 8FFFF
C
SA53
32K
1A8000 - 1AFFFF
D
SA18
32K
90000 - 97FFF
C
SA54
32K
1B0000 - 1B7FFF
D
SA19
32K
98000 - 9FFFF
C
SA55
32K
1B8000 - 1BFFFF
D
SA20
32K
A0000 - A7FFF
C
SA56
32K
1C0000 - 1C7FFF
D
SA21
32K
A8000 - AFFFF
C
SA57
32K
1C8000 - 1CFFFF
D
SA22
32K
B0000 - B7FFF
C
SA58
32K
1D0000 - 1D7FFF
D
SA23
32K
B8000 - BFFFF
C
SA59
32K
1D8000 - 1DFFFF
D
SA24
32K
C0000 - C7FFF
C
SA60
32K
1E0000 - 1E7FFF
D
SA25
32K
C8000 - CFFFF
C
SA61
32K
1E8000 - 1EFFFF
D
SA26
32K
D0000 - D7FFF
C
SA62
32K
1F0000 - 1F7FFF
D
SA27
32K
D8000 - DFFFF
C
SA63
32K
1F8000 - 1FFFFF
D
SA28
32K
E0000 - E7FFF
B
SA64
32K
200000 - 207FFF
D
SA29
32K
E8000 - EFFFF
B
SA65
32K
208000 - 20FFFF
D
SA30
32K
F0000 - F7FFF
B
SA66
32K
210000 - 217FFF
D
SA31
32K
F8000 - FFFFF
B
SA67
32K
218000 - 21FFFF
C
SA32
32K
100000 - 107FFF
B
SA68
32K
220000 - 227FFF
C
SA33
32K
108000 - 10FFFF
B
SA69
32K
228000 - 22FFFF
C
SA34
32K
110000 - 117FFF
B
SA70
32K
230000 - 237FFF
C
SA35
32K
118000 - 11FFFF
B
SA71
32K
238000 - 23FFFF
25
3464C–FLASH–2/05
11. Memory Organization –
AT49SN6416T (Continued)
11. Memory Organization –
AT49SN6416T (Continued)
x16
Plane
26
Sector
x16
Size (Words)
Address Range (A21 - A0)
Plane
Sector
Size (Words)
Address Range (A21 - A0)
B
SA72
32K
240000 - 247FFF
A
SA105
32K
348000 - 34FFFF
B
SA73
32K
248000 - 24FFFF
A
SA106
32K
350000 - 357FFF
B
SA74
32K
250000 - 257FFF
A
SA107
32K
358000 - 35FFFF
B
SA75
32K
258000 - 25FFFF
A
SA108
32K
360000 - 367FFF
B
SA76
32K
260000 - 267FFF
A
SA109
32K
368000 - 36FFFF
B
SA77
32K
268000 - 26FFFF
A
SA110
32K
370000 - 377FFF
B
SA78
32K
270000 - 277FFF
A
SA111
32K
378000 - 37FFFF
B
SA79
32K
278000 - 27FFFF
A
SA112
32K
380000 - 387FFF
B
SA80
32K
280000 - 287FFF
A
SA113
32K
388000 - 38FFFF
B
SA81
32K
288000 - 28FFFF
A
SA114
32K
390000 - 397FFF
B
SA82
32K
290000 - 297FFF
A
SA115
32K
398000 - 39FFFF
B
SA83
32K
298000 -29FFFF
A
SA116
32K
3A0000 - 3A7FFF
B
SA84
32K
2A0000 - 2A7FFF
A
SA117
32K
3A8000 - 3AFFFF
B
SA85
32K
2A8000 - 2AFFFF
A
SA118
32K
3B0000 - 3B7FFF
B
SA86
32K
2B0000 - 2B7FFF
A
SA119
32K
3B8000 - 3BFFFF
B
SA87
32K
2B8000 - 2BFFFF
A
SA120
32K
3C0000 - 3C7FFF
B
SA88
32K
2C0000 - 2C7FFF
A
SA121
32K
3C8000 - 3CFFFF
B
SA89
32K
2C8000 - 2CFFFF
A
SA122
32K
3D0000 - 3D7FFF
B
SA90
32K
2D0000 - 2D7FFF
A
SA123
32K
3D8000 - 3DFFFF
B
SA91
32K
2D8000 - 2DFFFF
A
SA124
32K
3E0000 - 3E7FFF
B
SA92
32K
2E0000 - 2E7FFF
A
SA125
32K
3E8000 - 3EFFFF
B
SA93
32K
2E8000 - 2EFFFF
A
SA126
32K
3F0000 - 3F7FFF
B
SA94
32K
2F0000 - 2F7FFF
A
SA127
4K
3F8000 - 3F8FFF
B
SA95
32K
2F8000 - 2FFFFF
A
SA128
4K
3F9000 - 3F9FFF
A
SA96
32K
300000 - 307FFF
A
SA129
4K
3FA000 - 3FAFFF
A
SA97
32K
308000 - 30FFFF
A
SA130
4K
3FB000 - 3FBFFF
A
SA98
32K
310000 - 317FFF
A
SA131
4K
3FC000 - 3FCFFF
A
SA99
32K
318000 - 31FFFF
A
SA132
4K
3FD000 - 3FDFFF
A
SA100
32K
320000 - 327FFF
A
SA133
4K
3FE000 - 3FEFFF
A
SA101
32K
328000 - 32FFFF
A
SA134
4K
3FF000 - 3FFFFF
A
SA102
32K
330000 - 337FFF
A
SA103
32K
338000 - 33FFFF
A
SA104
32K
340000 - 347FFF
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
12. DC and AC Operating Range
AT49SN6416(T)-70
Operating Temperature (Case)
Industrial
-40°C - 85°C
VCC Power Supply
1.65V - 1.95V
13. Operating Modes
Mode
CE
Read
Burst Read
(3)
OE
WE
RESET
VPP(4)
Ai
I/O
VIL
VIL
VIH
VIH
X
Ai
DOUT
VIL
VIL
VIH
VIH
X
Ai
DOUT
Ai
DIN
X
High Z
Program/Erase
VIL
VIH
VIL
VIH
VIHPP(5)
Standby/Program
Inhibit
VIH
X(1)
X
VIH
X
X
X
VIH
VIH
X
X
VIL
X
VIH
X
X
X
X
X
VILPP(6)
Output Disable
X
VIH
X
VIH
X
Reset
X
X
X
VIL
X
Program Inhibit
Product Identification
Software
Notes:
1.
2.
3.
4.
5.
6.
VIH
High Z
X
High Z
A0 = VIL, A1 - A21 = VIL
Manufacturer Code(3)
A0 = VIH, A1 - A21 = VIL
Device Code(3)
X can be VIL or VIH.
Refer to AC programming waveforms.
Manufacturer Code: 001FH; Device Code: 00DE - AT49SN6416; 00D8H - AT49SN6416T.
The VPP pin can be tied to VCC. For faster program operations, VPP can be set to 9.5V ± 0.5V.
VIHPP (min) = 0.9V.
VILPP (max) = 0.4V.
27
3464C–FLASH–2/05
14. DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
1
µA
Output Leakage Current
VI/O = 0V to VCC
1
µA
ISB1
VCC Standby Current CMOS
CE = VCCQ - 0.3V to VCC
35
µA
ICC(1)
VCC Active Current
f = 66 MHz; IOUT = 0 mA
30
mA
ICCRE
VCC Read While Erase Current
f = 66 MHz; IOUT = 0 mA
50
mA
ICCRW
VCC Read While Write Current
f = 66 MHz; IOUT = 0 mA
50
mA
VIL
Input Low Voltage
0.4
V
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
Note:
Min
VCCQ - 0.2
IOL = 100 µA
IOL = 2.1 mA
V
0.1
0.25
IOH = -100 µA
VCCQ - 0.1
IOH = -400 µA
1.4
V
V
1. In the erase mode, ICC is 30 mA.
15. Input Test Waveforms and Measurement Level
1.4V
AC
DRIVING
LEVELS
0.9V
AC
MEASUREMENT
LEVEL
0.4V
tR, tF < 5 ns
16. Output Test Load
VCCQ
1.8K
OUTPUT
PIN
1.3K
30 pF
17. Pin Capacitance
f = 1 MHz, T = 25°C(1)
CIN
COUT
Note:
28
Typ
Max
Units
Conditions
4
6
pF
VIN = 0V
8
12
pF
VOUT = 0V
1. This parameter is characterized and is not 100% tested.
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
18. AC Asynchronous Read Timing Characteristics
Symbol
Parameter
tACC1
Min
Max
Units
Access, AVD To Data Valid
70
ns
tACC2
Access, Address to Data Valid
70
ns
tCE
Access, CE to Data Valid
70
ns
tOE
OE to Data Valid
20
ns
tAHAV
Address Hold from AVD
9
ns
tAVLP
AVD Low Pulse Width
10
ns
tAVHP
AVD High Pulse Width
10
ns
tAAV
Address Valid to AVD
10
ns
tDF
CE, OE High to Data Float
tOH
Output Hold from OE, CE or Address, Whichever Occurred First
tRO
RESET to Output Delay
25
0
ns
ns
150
ns
19. AVD Pulsed Asynchronous Read Cycle Waveform(1)(2)
tCE
CE
tDF
I/O0-I/O15
DATA VALID
tACC2
tDF
A2 -A21
tAHAV
tAAV
tACC2
A0 -A1
tAAV
tAVHP
(1)
tAHAV
AVD
tAVLP
tACC1
tOE
OE
tRO
RESET
Notes:
1. After the high-to-low transition on AVD, AVD may remain low as long as the address is stable.
2. CLK may be static high or static low.
20. Asynchronous Read Cycle Waveform(1)(2)(3)(4)
tRC
ADDRESS VALID
A0 - A21
CE
tCE
tOE
OE
tDF
tOH
tACC2
tRO
RESET
I/O0 - I/O15
Notes:
HIGH Z
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. AVD and CLK should be tied low.
29
3464C–FLASH–2/05
21. AC Asynchronous Read Timing Characteristics
Symbol
Parameter
tACC1
Min
Max
Units
Access, AVD To Data Valid
70
ns
tACC2
Access, Address to Data Valid
70
ns
tCE
Access, CE to Data Valid
70
ns
tOE
OE to Data Valid
20
ns
tAHAV
Address Hold from AVD
9
ns
tAVLP
AVD Low Pulse Width
10
ns
tAVHP
AVD High Pulse Width
10
ns
tAAV
Address Valid to AVD
10
ns
tDF
CE, OE High to Data Float
25
ns
tRO
RESET to Output Delay
150
ns
tPAA
Page Address Access Time
20
ns
22. Page Read Cycle Waveform 1(1)
tCE
CE
tDF
I/O0-I/O15
DATA VALID
tACC2
tDF
A2 -A21
tAAV
tAHAV
tPAA
tACC2
A0 -A1
tAAV
tAVHP
(1)
tAHAV
AVD
tAVLP
tACC1
tOE
OE
tRO
RESET
Note:
1. After the high-to-low transition on AVD, AVD may remain low as long as the page address is stable.
23. Page Read Cycle Waveform 2(1)
tCE
CE
tDF
I/O0-I/O15
DATA VALID
tACC2
tDF
A2 -A21
tPAA
tACC2
A0 -A1
(1)
AVD
VIL
tOE
OE
tRO
RESET
Note:
30
1. AVD may remain low as long as the page address is stable.
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
24. AC Burst Read Timing Characteristics
Symbol
Parameter
Min
Max
tCLK
CLK Period
15
ns
tCKH
CLK High Time
4
ns
tCKL
CLK Low Time
4
ns
tCKRT
CLK Rise Time
3.5
ns
tCKFT
CLK Fall Time
3.5
ns
tACK
Address Valid to Clock
7
ns
tAVCK
AVD Low to Clock
7
ns
tCECK
CE Low to Clock
7
ns
tCKAV
Clock to AVD High
3
ns
tQHCK
Output Hold from Clock
3
ns
tAHCK
Address Hold from Clock
8
ns
tCKRY
Clock to WAIT Delay
tCESAV
CE Setup to AVD
10
ns
tAAV
Address Valid to AVD
10
ns
tAHAV
Address Hold From AVD
9
ns
tCKQV
CLK to Data Delay
13
ns
tCEQZ
CE High to Output High-Z
10
ns
13
Units
ns
25. Burst Read Cycle Waveform
tCLK
tCKH
...
...
...
CLK
tCKL
tAHCK
tCECK
CE
tCE
tCESAV
tAVCK
(2)
AVD
tACK
tCKAV
tAAV
I/O0-I/O15
tCKQV
tAHAV
tCEQZ
tQHCK
D3
D4
... D14
D15
D16
D17
A0-A21
OE
tCKRY
tCKRY
WAIT (1)
Notes:
1. The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and B8 = 0. The WAIT Signal (solid
line) shown is for a burst configuration setting of B10 = 1 and B8 = 0.
2. After the high-to-low transition on AVD, AVD may remain low.
31
3464C–FLASH–2/05
26. Burst Read Waveform (Clock Latency of 4)
B
A
D
C
F
E
G
CLK
CE
AVD
OE
VALID
A0-A21
D11
I/O0-I/O15
WAIT
Note:
(1)
D12
D13
D14
D16
D15
D17
D18
HIGH Z
HIGH Z
1. Dashed line reflects a B10 and B8 setting of 0 in the configuration register. Solid line reflects a B10 setting of 0 and B8
setting of 1 in the configuration register.
27. Hold Data for 2 Clock Cycles Read Waveform (Clock Latency of 4)
AVD
CLK
CE
OE
A0-A21
A9
I/O0-I/O15
D9
D10
D11
D12
D13
D14
D15
D16
WAIT(1)
Note:
32
1. The Dashed line reflects a burst configuration register setting of B10 and B8 = 0, B9 = 1. Solid line reflects a burst configuration register setting of B10 = 0, B8 and B9 = 1.
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
28. Four-word Burst Read Waveform (Clock Latency of 4)
B
A
C
CLK
CE
AVD
OE
VALID
A0-A21
I/O0-I/O15
WAIT
Note:
D0
(1)
D1
D2
D3
HIGH Z
HIGH Z
1. The WAIT signal shown is for a burst configuration register of B10 and B8 = 1.
29. Burst Suspend Waveform
tCLK
(2)
tCKH
...
CLK
tCKL
tAHCK
tCECK
CE
tCE
tCEAV
tAVCK
AVD
tACK
tCKAV
tAAV
I/O0-I/O15
tCKQV
tAHAV
tCEQZ
tQHCK
D0
D1
D1
D2
A0-A21
tDF
tOE
OE
WAIT (2)
Notes:
1. The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and B8 = 0. The WAIT Signal (solid
line) shown is for a burst configuration setting of B10 = 1 and B8 = 0.
2. During Burst Suspend, CLK signal can be held low or high.
33
3464C–FLASH–2/05
30. AC Word Load Characteristics 1
Symbol
Parameter
Min
Max
Units
tAAV
Address Valid to AVD High
10
ns
tAHAV
Address Hold Time from AVD High
9
ns
tAVLP
AVD Low Pulse Width
10
ns
tDS
Data Setup Time
50
ns
tDH
Data Hold Time
0
ns
tCESAV
CE Setup to AVD
10
ns
tWP
CE or WE Low Pulse Width
35
ns
tWPH
CE or WE High Pulse Width
25
ns
tWEAV
WE High Time to AVD Low
25
ns
tCEAV
CE High Time to AVD Low
25
ns
31. AC Word Load Waveforms 1
31.1
WE Controlled(1)
CE
I/O0-I/O15
DATA VALID
A0 -A21
tAAV
tAHAV
AVD
tDS
tAVLP
tDH
tWEAV
tWP
WE
Note:
1. After the high-to-low transition on AVD, AVD may remain low as long as the CLK input does not toggle.
31.2
CE Controlled(1)
WE
I/O0-I/O15
DATA VALID
A0 -A21
tAAV
tAHAV
AVD
tDS
tAVLP
tCESAV
CE
Note:
34
tWP
tDH
tCEAV
1. After the high-to-low transition on AVD, AVD may remain low as long as the CLK input does not toggle.
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
32. AC Word Load Characteristics 2
Symbol
Parameter
Min
Max
Units
tAS
Address Setup Time to WE and CE High
50
ns
tAH
Address Hold Time
0
ns
tDS
Data Setup Time
50
ns
tDH
Data Hold Time
0
ns
tWP
CE or WE Low Pulse Width
35
ns
tWPH
CE or WE High Pulse Width
25
ns
33. AC Word Load Waveforms 2
33.1
WE Controlled(1)
CE
I/O0 - I/O15
DATA VALID
A0 - A21
WE
AVD
Note:
1. The CLK input should not toggle.
33.2
CE Controlled(1)
VIL
WE
I/O0 - I/O15
DATA VALID
A0 - A21
CE
AVD
Note:
VIL
1. The CLK input should not toggle.
35
3464C–FLASH–2/05
34. Program Cycle Characteristics
Symbol
Parameter
Min
tBP
Word Programming Time
tWC
Write Cycle Time
tSEC1
Typ
Max
Units
22
µs
Sector Erase Cycle Time (4K word sectors)
200
ms
tSEC2
Sector Erase Cycle Time (32K word sectors)
700
ms
tES
Erase Suspend Time
15
µs
tPS
Program Suspend Time
10
µs
tERES
Delay between Erase Resume and Erase Suspend
500
µs
35. Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tBP
tWP
WE
tWPH
tDH
tAS
tAH
(1)
A0 - A21
ADDRESS
XX
tWC
I/O0 - I/O15
tDS
INPUT DATA
Note 3
VIL
AVD
36. Sector, Plane or Chip Erase Cycle Waveforms
OE
(2)
CE
tWP
tWPH
WE
tDH
tAS
A0 - A21
tAH
(1)
XX
Note 4
tWC
I/O0 - I/O15
AVD
Notes:
36
tDS
tSEC1/2
Note 5
D0
WORD 0
WORD 1
VIL
1.
2.
3.
4.
Any address can be used to load data.
OE must be high only when WE and CE are both low.
The data can be 40H or 10H.
For chip erase, any address can be used. For plane erase or sector erase, the address depends on what plane or sector is
to be erased.
5. For chip erase, the data should be 21H, for plane erase, the data should be 22H, and for sector erase, the data should
be 20H.
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
37. Common Flash Interface Definition Table
Address
AT49SN6416T
AT49SN6416
Comments
10h
0051h
0051h
“Q”
11h
0052h
0052h
“R”
12h
0059h
0059h
“Y”
13h
0003h
0003h
14h
0000h
0000h
15h
0041h
0041h
16h
0000h
0000h
17h
0000h
0000h
18h
0000h
0000h
19h
0000h
0000h
1Ah
0000h
0000h
1Bh
0016h
0016h
VCC min write/erase
1Ch
0019h
0019h
VCC max write/erase
1Dh
00B5h
0009h
VPP min voltage
1Eh
00C5h
000Ah
VPP max voltage
1Fh
0004h
0004h
Typ word write – 16 µs
20h
0000h
0000h
21h
0009h
0009h
Typ block erase – 500 ms
22h
0010h
0010h
Typ chip erase – 64,300 ms
23h
0004h
0004h
Max word write/typ time
24h
0000h
0000h
n/a
25h
0003h
0003h
Max block erase/typ block erase
26h
0003h
0003h
Max chip erase/ typ chip erase
27h
0017h
0017h
Device size
28h
0001h
0001h
x16 device
29h
0000h
0000h
x16 device
2Ah
0000h
0000h
Multiple byte write not supported
2Bh
0000h
0000h
Multiple byte write not supported
2Ch
0002h
0002h
2 regions, x = 2
2Dh
007Eh
0007h
64K bytes, Y = 126 (Top); 8K bytes, Y = 7 (Bottom)
2Eh
0000h
0000h
64K bytes, Y = 126 (Top); 8K bytes, Y = 7 (Bottom)
2Fh
0000h
0020h
64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom)
30h
0001h
0000h
64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom)
31h
0007h
007Eh
8K bytes, Y = 7 (Top); 64K bytes, Y = 126 (Bottom)
32h
0000h
0000h
8K bytes, Y = 7 (Top); 64K bytes, Y = 126 (Bottom)
33h
0020h
0000h
8K bytes, Z = 32 (Top);64K bytes, Z = 256 (Bottom)
34h
0000h
0001h
8K bytes, Z = 32 (Top);64K bytes, Z = 256 (Bottom)
37
3464C–FLASH–2/05
37. Common Flash Interface Definition Table (Continued)
Address
AT49SN6416T
AT49SN6416
Comments
VENDOR SPECIFIC EXTENDED QUERY
41h
0050h
0050h
“P”
42h
0052h
0052h
“R”
43h
0049h
0049h
“I”
44h
0031h
0031h
Major version number, ASCII
45h
0030h
0030h
Minor version number, ASCII
46h
00BFh
00BFh
Bit 0 – chip erase supported, 0 – no, 1 – yes
Bit 1 – erase suspend supported, 0 – no, 1 – yes
Bit 2 – program suspend supported, 0 – no, 1 – yes
Bit 3 – simultaneous operations supported, 0 – no, 1 – yes
Bit 4 – burst mode read supported, 0 – no, 1 – yes
Bit 5 – page mode read supported, 0 – no, 1 – yes
Bit 6 – queued erase supported, 0 – no, 1 – yes
Bit 7 – protection bits supported, 0 – no, 1 – yes
47h
0000h
0001h
Bit 0 – top (“0”) or bottom (“1”) boot block device
Undefined bits are “0”
000Fh
Bit 0 – 4 word linear burst with wrap around, 0 – no, 1 – yes
Bit 1 – 8 word linear burst with wrap around, 0 – no, 1 – yes
Bit 2 – 16 word linear burst with wrap around, 0 – no, 1 – yes
Bit 3 – continuous burst, 0 – no, 1 – yes
Undefined bits are “0”
48h
38
000Fh
49h
0001h
0001h
Bit 0 – 4 word page, 0 – no, 1 – yes
Bit 1 – 8 word page, 0 – no, 1 – yes
Undefined bits are “0”
4Ah
0080h
0080h
Location of protection register lock byte, the section’s first byte
4Bh
0003h
0003h
# of bytes in the factory prog section of prot register – 2*n
4Ch
0003h
0003h
# of bytes in the user prog section of prot register – 2*n
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
38. Ordering Information
38.1
Standard Package
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
30
0.035
AT49SN6416-70CI
56C2
Industrial
(-40° to 85°C)
70
30
0.035
AT49SN6416T-70CI
56C2
Industrial
(-40° to 85°C)
Package Type
56C2
56-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
39
3464C–FLASH–2/05
39. Packaging Information
39.1
56C2 – CBGA
D
0.12 C
C Seating Plane
E
Side View
A1
Top View
A
D1
0.875 mm Ref
8 7
6
5
4
3
2 1
A
B
C
E1
D
COMMON DIMENSIONS
(Unit of Measure = mm)
E
F
G
e
2.75 mm Ref
e
Øb
SYMBOL
MIN
NOM
MAX
A
–
–
1.00
A1
0.21
–
–
D
6.90
7.00
7.10
D1
Bottom View
E
NOTE
5.25 TYP
9.90
10.00
E1
4.50 TYP
e
0.75 TYP
Øb
0.35 TYP
10.10
1/9/04
R
40
2325 Orchard Parkway
San Jose, CA 95131
TITLE
56C2, 56-ball (8 x 7 Array), 7 x 10 x 1.0 mm Body, 0.75 mm Ball Pitch
Ceramic Ball Grid Array Package (CBGA)
DRAWING NO.
56C2
REV.
A
AT49SN6416(T)
3464C–FLASH–2/05
AT49SN6416(T)
40. Revision History
Revision No.
History
Revision A – March 2004
•
Initial Release
•
Timing diagrams on pages 31, 32, and 33 were changed such
that the default state is now shown as a solid line (shown as
dashed line before).
Added a note in the “Burst Configuration Register Table”
regarding the usee of Clock Latency of Two.
Wrap option removed on pages 3, 21 and 22.
Revision B – April 2004
•
•
•
•
•
Revision C – January 2005
•
•
•
•
Converted datasheet to New Template.
Removed “Preliminary” from the datasheet.
Changed the VPP value to 9.5V + 0.5V in the text, table
on page 19, and CFI table. VPP text also changed to show
that a high voltage on VPP improves only the programming time.
Changed the ISB1 spec to 35 µA.
Modified note 11 and added note 12 on page 19.
Modified note 1 and added note 2 on page 20.
Modified the B15 section in the
“Burst Configuration Register Table” on page 21
41
3464C–FLASH–2/05
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