DCDC Converter Sup Buck

DCDC Converter
35A Highly Integrated SupIRBuck®
Single-Input Voltage, Synchronous
Buck Regulator
FEATURES
SupIRBuck
IR3846
DESCRIPTION
 Single 5V to 21V application
 Wide Input Voltage Range from 1.5V to 21V with
external Vcc
 Output Voltage Range: 0.6V to 0.86*PVin
 0.5% accurate Reference Voltage
 Enhanced line/load regulation with Feed-Forward
 Programmable Switching Frequency up to
1.5MHz
 Internal Digital Soft-Start
 Enable input with Voltage Monitoring Capability
 Remote Sense Amplifier with True Differential
Voltage Sensing
 Thermally compensated current limit and Hiccup
Mode Over Current Protection
 Smart LDO to enhance efficiency
 Vp for tracking applications and sequencing
 Vref is available externally to enable margining
 External synchronization with Smooth Clocking
 Dedicated output voltage sensing for power good
indication and overvoltage protection which
remains active even when Enable is low.
 Enhanced Pre-Bias Start up
 Body Braking to improve transient
 Integrated MOSFET drivers and Bootstrap diode
 Thermal Shut Down
 Post Package trimmed rising edge dead-time
 Programmable Power Good Output with tracking
 Small Size 5mm x 7mm PQFN
o
o
 Operating Junction Temp: -40 C<Tj<125 C
 Lead-free, Halogen-free and RoHS Compliant
®
The IR3846 SupIRBuck is an easy-to-use, fully
integrated and highly efficient DC/DC regulator. The
onboard PWM controller and MOSFETs make IR3846
a space-efficient solution, providing accurate power
delivery for low output voltage and high current
applications.
IR3846 is a versatile regulator which offers
programmability of switching frequency and current
limit while operating in wide input and output voltage
range.
The switching frequency is programmable from 300
kHz to 1.5MHz for an optimum solution.
It also features important protection functions, such as
Over Voltage Protection (OVP), Pre-Bias startup,
hiccup current limit and thermal shutdown to give
required system level security in the event of fault
conditions.
APPLICATIONS
 Netcom Applications
 Embedded Telecom Systems
 Server Application
 Distributed Point of Load Power Architectures
 Storage Applications
ORDERING INFORMATION
Base Part
Number
IR3846
Package Type
PQFN 5mm x 7mm
Standard Pack
Orderable Part
Form
Quantity
Number
Tape and Reel
4000
IR3846MTRPBF
IR3846
PBF
TR
M
1
Rev 3.5
Lead Free
Tape and Reel
Package Type
Feb 05, 2016
IR3846
BASIC APPLICATION
5V <Vin<21V
Vp
S_Ctrl
Vin PVin
Boot
Vo
SW
OCSet
Vsns
RS+
VCC
PGood
PGood
RS-
Rt/Sync
RSo
FB
Enable
Vref
Comp
Gnd
PGnd
Figure 1: IR3846 Basic Application Circuit
Figure 2: Efficiency [Vin=12V, Fsw=600kHz]
PIN DIAGRAM
5mm X 7mm POWER QFN
Top View
2
Rev 3.5
Feb 05, 2016
IR3846
FUNCTIONAL BLOCK DIAGRAM
Vin
Smart
LDO
VCC
VCC
THERMAL
SHUTDOWN
DCM
LGnd
UVcc
UVcc
Comp
Vp
Vref
FAULT
CONTROL
OC
POR
OV
+
+
E/A
+
-
VREF
0.6V
FB
TSD
Boot
FAULT
PVin
FB
HDrv
Vref
Vp
Intl_SS
DRIVER
OVER
VOLTAGE
POR
POR
Vsns
VCC
100K
S_Ctrl
Enable
POR
FAULT
UVEN
RSRS+
PVin
DIGITAL
SOFT
START
BODY
BREAKING
CONTROL
ZC
POR
POR
CONTROL
LOGIC
OC
Vp
VREF
FB
+
RSo
SW
LDrv
PGnd
SSOK
UVEN
UVcc
HDin
LDin
CLK
+
ZERO CROSSING
COMPARATOR
OVER CURRENT
OCset
DCM
Rt/Sync
PGD
Figure 3: IR3846 Simplified Block Diagram
3
Rev 3.5
Feb 05, 2016
IR3846
PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
1
PVin
2, 3, 22, 23, 26
NC
4
Boot
5
Enable
Enable pin to turning on and off the IC.
6
Rt/Sync
Use an external resistor from this pin to LGND to set the switching
frequency, very close to the pin. This pin can also be used for external
synchronization.
7
OCset
Current limit setpoint. This pin allows the trip point to be set to one of
three possible settings by either floating, tying to VCC or tying to PGnd.
8
Vsns
Input voltage for power stage. Bypass capacitors between PVin and
PGND should be connected very close to this pin and PGND; also forms
input to feedforward block
No Connect
Supply voltage for high side driver
Sense pin for OVP and PGood
Inverting input to the error amplifier. This pin is connected directly to the
output of the regulator or to the output of the remote sense amplifier, via
resistor divider to set the output voltage and provide feedback to the
error amplifier.
9
FB
10
COMP
11
RSo
12, 25
PGND
Power ground. This pin should be connected to the system’s power
ground plane. Bypass capacitors between PVin and PGND should be
connected very close to PVIN pin (pin 1) and this pin.
13
LGND
Signal ground for internal reference and control circuitry.
14
S_Ctrl
Soft start/stop control. A high logic input enables the device to go into the
internal soft start; a low logic input enables the output soft discharged.
Pin is internally pulled high when this function is not used.
15
RS-
Remote Sense Amplifier input. Connect to ground at the load.
16
RS+
Remote Sense Amplifier input. Connect to output at the load.
17
Vref
External reference voltage can be used for margining operation. A
capacitor between 100pF and 180pF should be connected between this
pin and LGnd. Tie to LGnd for tracking function.
18
Vp
Used for voltage sequencing and tracking. Leave open if sequencing or
tracking is not needed, ensuring that there is no capacitor on the pin.
19
PGD
Power Good status pin. Output is open drain. Connect a pull up resistor
from this pin to VCC.
20
Vin
21
VCC/LDO_out
24
SW
4
Rev 3.5
Output of error amplifier. An external resistor and capacitor network is
typically connected from this pin to FB to provide loop compensation.
Remote Sense Amplifier Output
Input Voltage for LDO.
Bias Voltage for IC and driver section, output of LDO. Add a minimum of
4.7uF bypass cap from this pin to PGnd.
Switch node. This pin is connected to the output inductor.
Feb 05, 2016
IR3846
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
PVin
Vin
VCC
SW
BOOT
BOOT to SW
Input/Output pins
RS+, RS-, RSo, PGD, Enable, OCset, S_Ctrl
PGND to LGND, RS- to LGND
Junction Temperature Range
Storage Temperature Range
Machine Model
ESD
Human Body Model
Charged Device Model
Moisture Sensitivity level
RoHS Compliant
-0.3V to 25V
-0.3V to 25V
-0.3V to 8V (Note 1)
-0.3V to 25V (DC), -4V to 25V (AC, 100ns)
-0.3V to 33V
-0.3V to VCC + 0.3V (Note 2)
-0.3V to 3.9V
-0.3V to 8V (Note 1)
-0.3V to + 0.3V
-40°C to 150°C
-55°C to 150°C
Class A
Class 1C
Class III
JEDEC Level 2 @ 260°C
Yes
Note:
1. VCC must not exceed 7.5V for Junction Temperature between -10°C and -40°C.
2. Must not exceed 8V.
THERMAL INFORMATION
Thermal Resistance, Junction to Case (θJC_TOP)
Thermal Resistance, Junction to PCB (θJB)
Thermal Resistance, Junction to Ambient (θJA) (Note 3)
30 °C/W
2.71 °C/W
14.3 °C/W
Note:
3. Thermal resistance (θJA) is measured with components mounted on a high effective thermal conductivity
test board in free air.
5
Rev 3.5
Feb 05, 2016
IR3846
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
SYMBOL
DEFINITION
*
**
MIN
1.5
5.0
4.5
4.5
0.6
0
300
-40
PVin
Input Bus Voltage *
Vin
Supply Voltage
VCC
Supply Voltage **
Boot to SW
Supply Voltage
VO
Output Voltage
IO
Output Current
Fs
Switching Frequency
TJ
Junction Temperature
SW node must not exceed 25V
When VCC is connected to an externally regulated supply, also connect Vin.
UNIT
MAX
21
21
7.5
7.5
0.86 PVin
±35
1500
125
V
A
kHz
°C
ELECTRICAL CHARACTERISTICS
o
Unless otherwise specified, these specification apply over, 1.5V < PVin < 21V, 4.5V< VCC < 7.5V, 0 C < TJ <
o
125 C.
o
Typical values are specified at T A = 25 C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
PLOSS
Vin = PVin = 12V, VO =
1.2V, IO = 35A, Fs =
600kHz, L=0.250uH,
TA = 25°C, Note 4
5.3
Rds(on)_Top
VBoot – VSW = 6.8V,
ID = 35A, Without Cu
Clip, Tj = 25°C
3.1
Rds(on)_Bot
VCC =6.8V, ID = 35A,
With Cu Clip,
Tj = 25°C
1.27
MAX
UNIT
Power Loss
Power Loss
W
MOSFET Rds(on)
Top Switch
Bottom Switch
4
mΩ
1.64
Reference Voltage
Feedback Voltage
VFB
Accuracy
0.6
V
Vref=0.6V,
0°C < Tj < 105°C
-0.5
+0.5
Vref=0.6V,
-40°C < Tj < 125°C
-1.0
+1.0
%
Sink Current
Isink_Vref
Vref=0.7V
12.7
16.0
19.3
Source Current
Isrc_Vref
Vref=0.5V
12.7
16.0
19.3
Vref Comparator Threshold
6
Rev 3.5
Vref_disable
Vref Pin connected
externally
0.15
µA
V
Feb 05, 2016
IR3846
PARAMETER
SYMBOL
CONDITIONS
Vref_enable
MIN
TYP
MAX
0.4
UNIT
V
Supply Current
Vin Supply Current
(Standby)
Iin(Standby)
Vin=21V, Enable low,
No Switching
Iin(Dyn)
Vin=21V, Enable high,
Fs = 600kHz
Icc(Standby)
Enable low, VCC=7V,
No Switching
Icc(Dyn)
Enable high, VCC=7V,
Fs = 600kHz
VCC–Start–Threshold
VCC_UVLO_Start
VCC Rising Trip Level
4.0
4.2
4.4
VCC–Stop–Threshold
VCC_UVLO_Stop
VCC Falling Trip Level
3.7
3.9
4.2
Vin Supply Current (Dyn)
VCC Supply Current
(Standby)
VCC Supply Current (Dyn)
300
300
425
µA
40
mA
425
µA
40
mA
Under Voltage Lockout
Enable–Start–Threshold
Enable_UVLO_Start
Supply ramping up
1.14
1.2
1.36
Enable–Stop–Threshold
Enable_UVLO_Stop
Supply ramping down
0.9
1.0
1.06
Enable leakage current
Ien
Enable=3.3V
1
V
V
µA
Oscillator
Rt Voltage
1
Frequency Range
FS
Ramp Amplitude
Vramp
Rt=80.6k
270
300
330
Rt=39.2k
540
600
660
Rt=15k
1350
1500
1650
PVin=6.8V, PVin(max)
slew rate=1V/us,
Note 4
1.02
PVin=12V, PVin(max)
slew rate=1V/us,
Note 4
1.8
PVin=16V, PVin(max)
slew rate=1V/us,
Note 4
2.4
0.16
Ramp Offset
Ramp (os)
Note 4
Min Pulse Width
Tmin (ctrl)
Note 4
Fixed Off Time
Note 4
Max Duty Cycle
Dmax
Sync Frequency Range
Sync Pulse Duration
7
200
Fs=300kHz,
PVin=Vin=12V
86
Note 4
270
100
Sync Level Threshold
Rev 3.5
High
Low
V
kHz
Vp-p
V
50
ns
230
ns
%
1650
200
kHz
ns
3
0.6
V
Feb 05, 2016
IR3846
PARAMETER
SYMBOL
CONDITIONS
MIN
Vos_Vref
VFb – Vref, Vref =
0.6V
VFb – Vp, Vp = 0.6V
TYP
MAX
UNIT
-1.5
+1.5
%
Vref
-1.5
+1.5
%Vp
Error Amplifier
Input Offset Voltage
Vos_Vp
Input Bias Current
IFb(E/A)
-0.5
+0.5
µA
Input Bias Current
IVp(E/A)
0
4
µA
Sink Current
Isink(E/A)
0.4
0.85
1.2
mA
Isource(E/A)
4
7.5
11
mA
Source Current
Slew Rate
Gain-Bandwidth Product
SR
Note 4
7
12
20
V/µs
GBWP
Note 4
20
30
40
MHz
Gain
Note 4
100
110
120
dB
1.7
2
2.3
V
100
mV
DC Gain
Maximum Output
Voltage
Vmax(E/A)
Minimum Output Voltage
Vmin(E/A)
Common Mode Voltage
Vcm_Vp
Note 4
0
1.2
V
Vmarg_Vref
Note 4
0.4
1.2
V
3
9
MHz
Margining Range
Remote Sense Differential Amplifier
Unity Gain Bandwidth
BW_RS
Note 4
DC Gain
Gain_RS
Note 4
Offset Voltage
Offset_RS
Source Current
Vref=0.6V,
0°C < Tj < 85°C
Vref=0.6V,
-40°C < Tj < 125°C
6.4
110
-1.5
0
-2
dB
1.5
mV
2
mV
Isource_RS
3
13
20
mA
Sink Current
Isink_RS
0.4
1
2
mA
Slew Rate
Slew_RS
2
4
8
V/µs
RS+ input impedance
Rin_RS+
45
63
85
kohm
RS- input impedance
Rin_RS-
Maximum Voltage
Vmax_RS
Minimum Voltage
Min_RS
Note 4, Cload = 100pF
Note 4
V(VCC) – V(RSo)
63
0.5
1
kohm
1.5
50
V
mV
Internal Digital Soft Start
Soft Start Clock
Soft Start Ramp Rate
S_CTRL Threshold
8
Clk_SS
Note 4
180
200
220
kHz
Ramp(SS_Start)
Note 4
0.3
0.4
0.5
mV /
µs
High
Rev 3.5
2.4
V
Feb 05, 2016
IR3846
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Low
MAX
UNIT
0.6
V
960
mV
1
µA
Bootstrap Diode
Forward Voltage
I(Boot) = 30mA
360
520
Switch Node
SW = 0V, Enable = 0V
SW Leakage Current
lsw
SW = 0V, Enable =
HIGH, Vp=0 V
Internal Regulator (VCC/LDO)
Output Voltage
VCC
VCC dropout
VCC_drop
Short Circuit Current
Ishort
Zero-crossing
Comparator Delay
Tdly_zc
Zero-crossing
Comparator Offset
Vos_zc
Vin(min) = 7.2V, Io=030mA, Cload = 2.2uF,
DCM=0
6.3
Vin(min) = 7.2V, Io=030mA, Cload = 2.2uF,
DCM=1
4
6.8
7.1
V
4.4
Vin = 7V, Io=70 mA,
Cload = 2.2uF
4.8
0.7
Note 4
V
70
mA
256 /
Fs
s
Note 4
0
mV
Fb > Vref, Sw duty
cycle, Note 3
0
%
Body Braking
BB Threshold
BB_threshold
FAULTS
Power Good
Power Good Low Upper
Threshold
Power Good Low Upper
Threshold Falling delay
VPG_low(upper)
VPG_low(upper)_Dly
Power Good High Lower
Threshold
Power Good High Lower
Threshold Rising Delay
VPG_high(lower)
VPG_high(lower)_Dly
Power Good Low Lower
Threshold
9
Rev 3.5
VPG_low(lower)
Vsns Rising,
0.4V < Vref < 1.2V
115
120
125
% Vref
Vsns Rising,
Vref < 0.1V
115
120
125
% Vp
Vsns >
VPG_low(upper)
1.5
2.5
3.5
µs
Vsns Rising,
0.4V < Vref < 1.2V
95
% Vref
Vsns Rising,
Vref < 0.1V
95
% Vp
1.28
ms
Vsns falling,
0.4V < Vref < 1.2V
90
% Vref
Vsns falling,
90
%Vp
Vsns rising
Feb 05, 2016
IR3846
PARAMETER
SYMBOL
Power Good Low Lower
Threshold Falling delay
VPG_low(lower)_Dly
CONDITIONS
0.1V < Vref
Vsns <
VPG_low(lower)
MIN
TYP
MAX
UNIT
101
150
199
µs
0.5
V
PGood Voltage Low
PG (voltage)
IPGood = -5mA
Tracker Comparator
Upper Threshold
VPG(tracker_upper)
Vp Rising, Vref < 0.1V
0.4
V
Tracker Comparator
Lower Threshold
VPG(tracker_lower)
Vp Falling, Vref < 0.1V
0.3
V
Tracker Comparator
Delay
Tdelay(tracker)
Vp Rising, Vref < 0.1V
1.28
ms
Over Voltage Protection (OVP)
OVP Trip Threshold
OVP (trip)
OVP Fault Prop Delay
OVP (delay)
Vsns Rising,
0.45V < Vref < 1.2V
115
120
125
% Vref
Vsns Rising,
Vref < 0.1V
115
120
125
% Vp
Vsns rising
1.5
2.5
3.5
µs
OCSet=VCC, VCC =
6.8V, TJ = 25°C
41
44.4
48
A
OCSet=floating, VCC
= 6.8V, TJ = 25°C
32
35
38
A
OCSet=PGnd, VCC
=6.8V, TJ = 25°C
24
26.88
30
A
Over-Current Protection
OC Trip Current
ITRIP
Hiccup blanking time
Tblk_Hiccup
Note 4
20.48
ms
Thermal Shutdown
Note 4
145
°C
Hysteresis
Note 4
20
°C
Thermal Shutdown
Notes:
4. Guaranteed by design but not tested in production.
10
Rev 3.5
Feb 05, 2016
IR3846
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = 12V, VCC = Internal LDO, Io=0-35A, Fs= 600kHz, Room Temperature, LFM=200. Note that the
losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves.
The table below shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.2
1.8
3.3
5.0
11
LOUT (uH)
0.25
0.33
0.33
0.33
Rev 3.5
P/N
744309025 (Wurth Electronik)
744309033 (Wurth Electronik)
744309033 (Wurth Electronik)
744309033 (Wurth Electronik)
DCR (mΩ)
0.165
0.165
0.165
0.165
Feb 05, 2016
IR3846
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, Vin = VCC = 5V, Io=0-35A, Fs= 600kHz, Room Temperature, LFM=200. Note that the losses of the
inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table
below shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.2
1.8
3.3
5.0
12
LOUT (uH)
0.25
0.33
0.33
0.33
Rev 3.5
P/N
744309025 (Wurth Electronik)
744309033 (Wurth Electronik)
744309033 (Wurth Electronik)
744309033 (Wurth Electronik)
DCR (mΩ)
0.165
0.165
0.165
0.165
Feb 05, 2016
IR3846
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = VCC = 5V, Io=0-35A, Fs= 600kHz, Room Temperature, LFM=200. Note that the losses of the
inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table
below shows the indicator used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
1.2
13
LOUT (uH)
0.19
0.19
Rev 3.5
P/N
SL40307A-R19KHF (ITG)
SL40307A-R19KHF (ITG)
DCR (mΩ)
0.200
0.200
Feb 05, 2016
IR3846
THERMAL DERATING CURVES
Measurements are done on IR3846 Evaluation board. PCB is a 6 layer board with 2 oz copper and FR4 material.
Vin=PVin=12V, Vout =1.2V, VCC=internal LDO (6.8V), Fs = 600kHz
Vin=PVin=12V, Vout =3.3V, VCC=internal LDO (6.8V), Fs = 600kHz
Note: International Rectifier Corporation specifies current rating of SupIRBuck devices conservatively. The
continuous current load capability might be higher than the rating of the device if input voltage is 12V typical and
switching frequency is below 600kHz. However, the maximum current is limited by the internal current limit and
designers need to consider enough guard bands between load current and minimum current limit to guarantee
that the device does not trip at steady state condition.
14
Rev 3.5
Feb 05, 2016
IR3846
MOSFET RDSON VARIATION OVER TEMPERATURE
15
Rev 3.5
Feb 05, 2016
IR3846
TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C)
16
Rev 3.5
Feb 05, 2016
IR3846
TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C)
17
Rev 3.5
Feb 05, 2016
IR3846
18
Rev 3.5
Feb 05, 2016
IR3846
TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C)
OCset=VCC
OCset=Float
OCset=GND
OCset=VCC
OCset=Float
OCset=GND
OCset=VCC
OCset=Float
OCset=GND
19
Rev 3.5
Feb 05, 2016
IR3846
THEORY OF OPERATION
set thresholds. Normal operation resumes once VCC
and Enable rise above their thresholds.
DESCRIPTION
The IR3846 uses a PWM voltage mode control
scheme with external compensation to provide good
noise immunity and maximum flexibility in selecting
inductor values and capacitor types.
The switching frequency is programmable from
300kHz to 1.5MHz and provides the capability of
optimizing the design in terms of size and
performance.
IR3846 provides precisely regulated output voltage
programmed via two external resistors from 0.6V to
0.86*PVin.
The IR3846 operates with an internal bias supply
(LDO) which is connected to the VCC pin. This allows
operation with single supply. The bias voltage is
variable according to load condition. If the output load
current is less than half of the peak-to-peak inductor
current, a lower bias voltage, 4.4V, is used as the
internal gate drive voltage; otherwise, a higher
voltage, 6.8V, is used.
This feature helps the converter to reduce power
losses. The device can also be operated with an
external bias from 4.5V to 7.5V, allowing an extended
operating input voltage (PVin) range from 1.5V to 21V.
For using the internal LDO supply, the Vin pin should
be connected to PVin pin. If an external bias is used, it
should be connected to VCC pin and the Vin pin
should be shorted to VCC pin.
The device utilizes the on-resistance of the low side
MOSFET (synchronous Mosfet) as current sense
element. This method enhances the converter’s
efficiency and reduces cost by eliminating the need for
external current sense resistor.
IR3846 includes two low Rds(on) MOSFETs using IR’s
HEXFET technology. These are specifically designed
for high efficiency applications.
UNDER-VOLTAGE LOCKOUT AND POR
The under-voltage lockout circuit monitors the voltage
of VCC pin and the Enable input. It assures that the
MOSFET driver outputs remain in the off state
whenever either of these two signals drops below the
20
Rev 3.5
The POR (Power On Ready) signal is generated when
all these signals reach the valid logic level (see
system block diagram). When the POR is asserted the
soft start sequence starts (see soft start section).
ENABLE
The Enable features another level of flexibility for
startup. The Enable has precise threshold which is
internally monitored by Under-Voltage Lockout
(UVLO) circuit. Therefore, the IR3846 will turn on only
when the voltage at the Enable pin exceeds this
threshold, typically, 1.2V.
If the input to the Enable pin is derived from the bus
voltage by a suitably programmed resistive divider, it
can be ensured that the IR3846 does not turn on until
the bus voltage reaches the desired level as shown in
Figure 4. Only after the bus voltage reaches or
exceeds this level and voltage at the Enable pin
exceeds its threshold, IR3846 will be enabled.
Therefore, in addition to being a logic input pin to
enable the IR3846, the Enable feature, with its precise
threshold, also allows the user to implement an
Under-Voltage Lockout for the bus voltage (PVin). It
can help prevent the IR3846 from regulating at low
PVin voltages that can cause excessive input current.
12V
10.2V
PVin
Vcc
> 1.2V
EN
1.2V
EN_UVLO_START
Intl_SS
Figure 4: Normal Start up, device turns on when the
bus voltage reaches 10.2V
A resistor divider is used at EN pin from PVin to turn
on the device at 10.2V.
Feb 05, 2016
IR3846
PVin=Vin
Vcc
Vp
> 1.0V
EN
> 1.2V
input. In this operating mode Vref is left floating.
Figure 6 shows the recommended startup sequence
for sequenced operation of IR3846 with Enable used
as logic input. Figure 7 shows the recommended
startup sequence for tracking operation of IR3846 with
Enable used as logic input. For this mode of
operation, Vref should be connected to LGND.
PRE-BIAS STARTUP
Intl_SS
IR3846 is able to start up into pre-charged output,
which prevents oscillation and disturbances of the
output voltage.
Vo
Figure 5: Recommended startup for Normal operation
PVin=Vin
Vcc
Vp
> 1.2V
EN
Intl_SS
The output starts in asynchronous fashion and keeps
the synchronous MOSFET (Sync FET) off until the
first gate signal for control MOSFET (Ctrl FET) is
generated. Figure 8 shows a typical Pre-Bias
condition at start up. The sync FET always starts with
a narrow pulse width (12.5% of a switching period)
and gradually increases its duty cycle with a step of
12.5% until it reaches the steady state value. The
number of these startup pulses for each step is 16
and it’s internally programmed. Figure 9 shows the
series of 16x8 startup pulses.
Vo
[V]
Vo
Figure 6: Recommended startup for sequencing
operation (ratiometric or simultaneous)
Pre-Bias
Voltage
PVin=Vin
[Time]
Vcc
Figure 8: Pre-Bias startup
VDDQ
Vp
EN
VDDQ/2
...
HDRv
12.5%
> 1.2V
...
LDRv
Vref
...
...
25%
...
...
87.5%
...
...
...
0V
16
16
End of
PB
...
Vo
VTT Tracking
Figure 7: Recommended startup for memory tracking
operation (Vtt-DDR)
Figure 5 shows the recommended startup sequence
for the normal (non-tracking, non-sequencing)
operation of IR3846, when Enable is used as a logic
21
Rev 3.5
Figure 9: Pre-Bias startup pulses
SOFT-START
IR3846 has an internal digital soft-start to control the
output voltage rise and to limit the current surge at the
start-up. To ensure correct start-up, the soft-start
sequence initiates when the Enable and VCC rise
Feb 05, 2016
IR3846
above their UVLO thresholds and generate the Power
On Ready (POR) signal. The internal soft-start
(Intl_SS) signal linearly rises with the rate of 0.4mV/µs
from 0V to 1.5V. Figure 10 shows the waveforms
during soft start. The normal Vout startup time is fixed,
and is equal to:
Tstart 
0.75V  0.15V   1.5mS
0.4mV / S
Table 1: Switching Frequency(Fs) vs. External
Resistor(Rt)
Rt (KΩ)
80.6
60.4
48.7
39.2
34
29.4
26.1
23.2
21
19.1
17.4
16.2
15
(1)
During the soft start the over-current protection (OCP)
and over-voltage protection (OVP) is enabled to
protect the device for any short circuit or over voltage
condition.
POR
3.0V
Freq
(KHz)
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1.5V
0.75V
SHUTDOWN
Intl_SS
0.15V
IR3846 can be shutdown by pulling the Enable pin
below its 1.0V threshold. During shutdown the high
side and the low side drivers are turned off.
Vout
t1 t2
t3
Figure 10: Theoretical operation waveforms during
soft-start (non tracking / non sequencing)
OPERATING FREQUENCY
The switching frequency can be programmed between
300kHz – 1500kHz by connecting an external resistor
from Rt pin to LGnd. Table 1 tabulates the oscillator
frequency versus Rt.
OVER CURRENT PROTECTION
The Over Current (OC) protection is performed by
sensing the inductor current through the RDS(on) of the
Synchronous MOSFET. This method enhances the
converter’s efficiency, reduces cost by eliminating a
current sense resistor and any layout related noise
issues. The Over Current (OC) limit can be set to one
of three possible settings by floating the OCset pin, by
pulling up the OCset pin to VCC, or pulling down the
OCset pin to PGnd. The current limit scheme in the
IR3846 uses an internal temperature compensated
current source to achieve an almost constant OC limit
over temperature.
Over Current Protection circuit senses the inductor
current flowing through the Synchronous MOSFET.
To help minimize false tripping due to noise and
transients, inductor current is sampled for about 30 nS
on the downward inductor current slope approximately
12.5% of the switching period before the inductor
current valley. However, if the Synchronous MOSFET
is on for less than 12.5% of the switching period, the
current is sampled approximately 40nS after the start
of the downward slope of the inductor current. When
22
Rev 3.5
Feb 05, 2016
IR3846
the sampled current is higher than the OC Limit, an
OC event is detected.
When an Over Current event is detected, the
converter enters hiccup mode. Hiccup mode is
performed by latching the OC signal and pulling the
Intl_SS signal to ground for 20.48 mS (typ.). OC
signal clears after the completion of hiccup mode and
the converter attempts to return to the nominal output
voltage using a soft start sequence. The converter will
repeat hiccup mode and attempt to recover until the
overload or short circuit condition is removed.
Because the IR3846 uses valley current sensing, the
actual DC output current limit will be greater than OC
limit. The DC output current is approximately half of
peak to peak inductor ripple current above selected
OC limit. OC Limit, inductor value, input voltage,
output voltage and switching frequency are used to
calculate the DC output current limit for the converter.
Equation (2) to determine the approximate DC output
current limit.
I OCP  I LIMIT 
IOCP
ILIMIT
Δi
i
2
(2)
= DC current limit hiccup point
= Current Limit Valley Point
= Inductor ripple current
Current Limit
Hiccup
Tblk_Hiccup
20.48 mS*
IL
0
HDrv
...
0
LDrv
...
0
PGD
*typical filter delay
0
Figure 11: Timing Diagram for Current Limit Hiccup
THERMAL SHUTDOWN
Temperature sensing is provided inside IR3846. The
o
trip threshold is typically 145 C. When trip threshold is
exceeded, thermal shutdown turns off both MOSFETs
and resets the internal soft start.
23
Rev 3.5
Automatic restart is initiated when the sensed
temperature drops within the operating range. There
o
is a 20 C hysteresis in the thermal shutdown
threshold.
REMOTE VOLTAGE SENSING
True differential remote sensing in the feedback loop
is critical to high current applications where the output
voltage across the load may differ from the output
voltage measured locally across an output capacitor
at the output inductor, and to applications that require
die voltage sensing.
The RS+ and RS- pins of the IR3846 form the inputs
to a remote sense differential amplifier (RSA) with
high speed, low input offset and low input bias current
which ensure accurate voltage sensing and fast
transient response in such applications.
The input range for the differential amplifier is limited
to 1.5V below the VCC rail. Note that IR3846
incorporates a smart LDO which switches the VCC rail
voltage depending on the loading. When determining
the input range assume the part is in light load and
using the lower VCC rail voltage.
There are two remote sense configurations that are
usually implemented. Figure 12 shows a general
remote sense (RS) configuration. This configuration
allows the RSA to monitor output voltages above
VCC. A resistor divider is placed in between the
output and the RSA to provide a lower input voltage to
the RSA inputs. Typically, the resistor divider is
calculated to provide VREF (0.6V) across the RSA
inputs which is then outputted to RSo. The input
impedance of the RSA is 63 KOhms typically and
should be accounted for when determining values for
the resistor divider. To account for the input
impedance, assume a 63 KOhm resistor in parallel to
the lower resistor in the divider network.
The
compensation is then designed for 0.6V to match the
RSo value.
Low voltage applications can use the second remote
sense configuration. When the output voltage range
is within the RSA input specifications, no resistor
divider is needed in between the converter output and
RSA. The second configuration is shown in Figure
13. The RSA is used as a unity gain buffer and
compensation is determined normally.
Feb 05, 2016
IR3846
Vout
(< VCC-1.5V)
-
RSo
Compensation
Resistor Divider
RS+
+
RSA
RS-
+
FB
-
+
Vout
(< VCC-1.5V)
-
RS+
RSo
Vo
RSA
RS-
Compensation
Figure 12: General Remote Sense Configuration
+
IR3846 incorporates an internal phase lock loop (PLL)
circuit which enables synchronization of the internal
oscillator to an external clock. This function is
important to avoid sub-harmonic oscillations due to
beat frequency for embedded systems when multiple
point-of-load (POL) regulators are used. A multifunction pin, Rt/Sync, is used to connect the external
clock. If the external clock is present before the
converter turns on, Rt/Sync pin can be connected to
the external clock signal solely and no other resistor is
needed. If the external clock is applied after the
converter turns on, or the converter switching
frequency needs to toggle between the external clock
frequency and the internal free-running frequency, an
external resistor from Rt/Sync pin to LGnd is required
to set the free-running frequency.
When an external clock is applied to Rt/Sync pin after
the converter runs in steady state with its free-running
frequency, a transition from the free-running
frequency to the external clock frequency will happen.
This transition is to gradually make the actual
switching frequency equal to the external clock
frequency, no matter which one is higher. When the
external clock signal is removed from Rt/Sync pin, the
switching frequency is also changed to free-running
Synchronize to the
external clock
Free Running
Frequency
-
EXTERNAL SYNCHRONIZATION
Rev 3.5
An internal circuit is used to change the PWM ramp
slope according to the clock frequency applied on
Rt/Sync pin. Even though the frequency of the
external synchronization clock can vary in a wide
range, the PLL circuit keeps the ramp amplitude
constant, requiring no adjustment of the loop
compensation. PVin variation also affects the ramp
amplitude, which will be discussed separately in FeedForward section.
FB
Figure 13: Remote Sense Configuration for Vout less
than VCC-1.5V
24
gradually. In order to minimize the impact from these
transitions to output voltage, a diode is recommended
to add between the external clock and Rt/Sync pin.
Figure 14 shows the timing diagram of these
transitions.
Return to freerunning freq
...
SW
Gradually change
Gradually change
...
Fs1
SYNC
Fs1
Fs2
Figure 14: Timing Diagram for Synchronization
to the external clock (Fs1>Fs2 or Fs1<Fs2)
FEED-FORWARD
Feed-Forward (F.F.) is an important feature, because
it can keep the converter stable and preserve its load
transient performance when PVin varies. The PWM
ramp amplitude (Vramp) is proportionally changed
with PVin to maintain PVin/Vramp almost constant
throughout PVin variation range (as shown in Figure
15). The PWM ramp amplitude is adjusted to 0.15 of
PVin. Thus, the control loop bandwidth and phase
margin can be maintained constant. Feed-forward
function can also minimize impact on output voltage
from fast PVin change. F.F. is disabled when
PVin<6.2V and the PWM ramp is typically 0.9V. For
PVin<6.2V, PVin voltage should be accounted for
when calculating control loop parameters.
Feb 05, 2016
IR3846
21V
12V
12V
6.8V
PVin
PWM Ramp
Amplitude =
0.15xPVin
0
PWM Ramp
...
IL
...
...
0
...
PWM Ramp
Amplitude = 3.15V
PWM Ramp
Amplitude = 1.8V
256/Fs
PWM Ramp
Amplitude = 1.02V
Ramp Offset
0
Vcc/
LDO
6.8V
4.4V
6.8V
0
Figure 15: Timing Diagram for Feed-Forward (F.F.)
Function
SMART LOW DROPOUT REGULATOR (LDO)
IR3846 has an integrated low dropout (LDO) regulator
which can provide gate drive voltage for both drivers.
In order to improve overall efficiency over the whole
load range, LDO voltage is set to 6.8V (typ.) at mid- or
heavy load condition to reduce Rds(on) and thus
MOSFET conduction loss; and it is reduced to 4.4V
(typ.) at light load condition to reduce gate drive loss.
The smart LDO selects its output voltage according to
the load condition by sensing the inductor current (IL).
At light load condition, the inductor current can fall
below zero as shown in Figure 16. A zero crossing
comparator is used to detect when the inductor
current falls below zero at the LDrv Falling Edge. If the
comparator detects zero crossing events for 256
consecutive switching cycles, the smart LDO reduces
its output to 4.4V. The LDO voltage will remain low
until a zero crossing is not detected. Once a zero
crossing is not detected, the counter is reset and LDO
voltage returns to 6.8V. Figure 16 shows the timing
diagram. Whenever the device turns on, LDO always
starts with 6.8V, then goes to 4.4V / 6.8V depending
upon the load condition. However, if only Vin is
applied with Enable low, the LDO output is 4.4V.
Figure 16: Time Diagram for Smart LDO
Users can configure the IR3846 to use a single supply
or dual supplies. Depending on the configuration used
the PVin, Vin and VCC pins are connected differently.
Below several configurations are shown.
In an
internally biased configuration, the LDO draws from
the Vin pin and provides a gate drive voltage, as
shown in Figure 17. By connecting Vin and PVin
together as shown in the Figure 18, IR3846 is an
internally biased single supply configuration that runs
off a single supply.
IR3846 can also use an external bias to provide gate
drive voltage for the drivers instead of the internal
LDO. To use an external bias, connected Vin and
VCC to the external bias. PVin can use a separate rail
as shown in Figure 19 or run off the same rail as Vin
and VCC.
Vin
PVin
Vin PVin
IR3846
VCC
PGND
Figure 17: Internally Biased Configuration
25
Rev 3.5
Feb 05, 2016
IR3846
Vin
OUTPUT VOLTAGE TRACKING AND
Vin PVin
SEQUENCING
IR3846
VCC
PGND
Figure 18: Internally Biased Single Supply
Configuration
Ext VCC
PVin
Vin PVin
IR3846
VCC
PGND
Figure 19: Externally Biased Configuration
When the Vin voltage is below 6.8V, the internal LDO
enters the dropout mode at medium and heavy load.
The dropout voltage increases with the switching
frequency. Figure 20 shows the LDO voltage for
600kHz
and
1000kHz
switching
frequency
respectively.
IR3846 can accommodate user programmable
tracking and/or sequencing options using Vp, Vref,
Enable, and Power Good pins. In the block diagram
presented on page 3, the error-amplifier (E/A) has
been depicted with three positive inputs. Ideally, the
input with the lowest voltage is used for regulating the
output voltage and the other two inputs are ignored. In
practice the voltage of the other two inputs should be
at least 200mV greater than the low-voltage input so
that their effects can completely be ignored. Vp is
pulled up to an internal rail via a high impedance path.
For normal operation, Vp and Vref is left floating (Vref
should have a bypass capacitor).
Therefore, in normal operating condition, after Enable
goes high, the internal soft-start (Intl_SS) ramps up
the output voltage until Vfb (voltage of feedback/Fb
pin) reaches about 0.6V. Then Vref takes over and the
output voltage is regulated.
Tracking-mode operation is achieved by connecting
Vref to LGND. Then, while Vp = 0V, Enable is taken
above its threshold so that the soft-start circuit
generates Intl_SS signal. After the Intl_SS signal
reaches the final value (refer to Figure 7), ramping up
the Vp input will ramp up the output voltage. In
tracking mode, Vfb always follows Vp which means
Vout is always proportional to Vp voltage (typical for
DDR/Vtt rail applications). The effective Vp range is
0V~1.2V.
In sequencing mode of operation (simultaneous or
ratiometric), Vref is left floating and Vp is kept to
ground level until Intl_SS signal reaches the final
value. Then Vp is ramped up and Vfb follows Vp.
When Vp>0.6V the error-amplifier switches to Vref
and the output voltage is regulated with Vref. The
final Vp voltage after sequencing startup should
between 0.8V ~ 3.0V.
Figure 20: LDO_Out Voltage in dropout mode
26
Rev 3.5
Feb 05, 2016
IR3846
Enable (Master)
5V <Vin<21V
1.2V
Vp
VCC
Vp
Vref=0.6V
Enable (slave)
Vin PVin
Vo1
(master)
Boot
SW
OCSet
Vsns
RS+
PGood
Soft Start (slave)
Vo1 (master)
(a)
Enable
Vcc/
LDO_out
PGood
RS-
Rt/SYNC
RSo
RA
Fb
Comp
Vref
Gnd
PGnd
RB
Vo2 (slave)
Vo1 (master)
5V<Vin<21V
(b)
Vo1(master)
Vo2 (slave)
RE
Vp
RF
Figure 21: Typical waveforms for sequencing mode of
operation: (a) simultaneous, (b) ratiometric
Enable
Vin PVin
Vcc/
LDO_out
Vo2
(slave)
Boot
SW
OCSet
Vsns
RS+
PGood
PGood
RS-
Rt/SYNC
RSo
RC
Fb
Comp
Vp (Master)
Vref
Gnd
PGnd
RD
VCC
Vref=0V
Enable (Master and Slave)
Soft Start (Master and Slave)
Vo1 (master)
(a)
Vo2 (slave)
Vo1 (master)
(b)
Vo2 (slave)
Figure 22: Typical waveforms in tracking mode of
operation: (a) simultaneous, (b) ratiometric
27
Rev 3.5
Figure 23: Application Circuit for Simultaneous and
Ratiometric Sequencing
Tracking and sequencing operations can be
implemented to be simultaneous or ratiometric (refer
to Figure 21 and Figure 22). Figure 23 shows typical
circuit configuration for sequencing operation. With
this power-up configuration, the voltage at the Vp pin
of the slave reaches 0.6V before the Fb pin of the
master. If RE/RF =RC/RD, simultaneous startup is
achieved. That is, the output voltage of the slave
follows that of the master until the voltage at the Vp
pin of the slave reaches 0.6 V. After the voltage at the
Vp pin of the slave exceeds 0.6V, the internal 0.6V
reference of the slave dictates its output voltage. In
reality the regulation gradually shifts from Vp to
internal Vref. The circuit shown in Figure 23 can also
be used for simultaneous or ratiometric tracking
operation if Vref of the slave is connected to LGND.
Table 2 summarizes the required conditions to
achieve
simultaneous/ratiometric
tracking
or
sequencing operations.
Feb 05, 2016
IR3846
Table 2: Required Conditions for Simultaneous /
Ratiometric Tracking and Sequencing (Figure 23)
Operating
Mode
Normal
(Nonsequencing,
Non-tracking)
Simultaneous
Sequencing
Ratiometric
Sequencing
Vref
(Slave)
Vp
Required
Condition
0.6
(Floating)
Floating
―
Ramp
up from
0V
Ramp
up from
0V
Ramp
up from
0V
Ramp
up from
0V
RA/RB >
RE/RF =
RC/RD
RA/RB >
RE/RF >
RC/RD
RE/RF =
RC/RD
0.6V
0.6V
Simultaneous
Tracking
0V
Ratiometric
Tracking
0V
RE/RF >
RC/RD
The threshold is set differently in different operating
modes and the results of the comparison sets the
PGood signal. Figure 24, Figure 25 and Figure 26
show the timing diagram of the PGood signal at
different operating modes. Vsns signal is also used by
OVP comparator for detecting output over voltage
condition. PGood signal is low when Enable is low.
Vref
0.6V
0
1.2*VREF
0.90*VREF
Vsns
0
OVP
Latch
PGD
0
1.28 mS 150 uS 1.28 mS
VREF
This pin reflects the internal reference voltage which is
used by the error amplifier to set the output voltage. In
most operating conditions this pin is only connected to
an external bypass capacitor and it is left floating. A
minimum 100pF ceramic capacitor is required from
stability point of view. In tracking mode this pin should
be pulled to LGND. For margining applications, an
external voltage source is connected to Vref pin and
overrides the internal reference voltage. The external
voltage source should have a low internal resistance
(<100Ω) and be able to source and sink more than
25µA.
POWER GOOD OUTPUT (TRACKING,
SEQUENCING, VREF MARGINING)
IR3846 continually monitors the output voltage via the
sense pin (Vsns) voltage. The Vsns voltage is an input
to the window comparator with upper and lower
threshold of 1.2*VREF and 0.95*VREF respectively.
PGood signal is high whenever Vsns voltage is within
the PGood comparator window thresholds. Hysteresis
has been applied to the lower threshold, PGood signal
goes low when Vsns drops below 0.9*VREF instead
of 0.95*VREF. The PGood pin is open drain and it
needs to be externally pulled high. High state
indicates that output is in regulation.
28
0.95*VREF
Rev 3.5
2.5 uS
Figure 24: Non-sequence, Non-tracking Startup
and Vref Margin (Vp pin floating)
Vp
0.4V
0.3V
0
1.2*Vp
Vsns
0.95*Vp
0
PGD
0
1.28 mS
Figure 25: Vp Tracking (Vref = 0V)
Feb 05, 2016
IR3846
1.2*VREF
Intl_SS
0
Vsns
0
Vref
0
VREF
HDrv
0
0.6V
(1V<Vp<3.3V)
0.6V
LDrv
0
Vp
0
1.2*Vref
Vsns
0
0.95*Vref
Comp
0
2.5 uS
PGD
0
PGD
0
1.28 mS
Figure 27: Timing Diagram for OVP in non-tracking
mode
Figure 26: Vp Sequence and Vref Margin
SOFT-START / SOFT-STOP (S_CTRL)
OVER-VOLTAGE PROTECTION (OVP)
Over-voltage protection in IR3846 is achieved by
comparing sense pin voltage Vsns to a pre-set
threshold. In non-tracking mode, OVP threshold can
be set at 1.2*Vref; in tracking mode, it can be at
1.2*Vp. When Vsns exceeds the over voltage
threshold, an over voltage trip signal asserts after 2.5
uS (typ.) delay. The high side drive signal HDrv is
latched off immediately and PGood flags are set low.
The low side drive signal is kept on until the Vsns
voltage drops below the threshold. HDrv remains
latched off until a reset is performed by cycling VCC.
OVP is active when enable is high or low.
Vsns voltage is set by the voltage divider connected to
the output and it can be programmed externally.
Figure 27 shows the timing diagram for OVP in nontracking mode.
S_Ctrl allows for the gradual charging and discharging
of Vout to its final value by controlling the Soft-Start
and Soft-Stop functions. Soft-Start and Soft-Stop is
the gradual charging and discharging of Vout,
respectfully. Both functions use the internal Intl_SS
ramp to regulate the rate Vout charges and
discharges. Soft-Start feature is enabled when S_Ctrl
and EN are asserted high. S_Ctrl is internally pulled
high, so that EN typically controls the rise of Vout. To
delay the charging of Vout, keep S_Ctrl low while
setting EN. Then assert S_Ctrl high to initiate the
Intl_SS ramp (Soft-Start). Vout follows Intl_SS and
ramps up until it reaches its steady state. For SoftStop, S_Ctrl needs to be pulled low before EN goes
low. When S_Ctrl falls below its lower threshold,
Intl_SS becomes a decreasing ramp with the same
rate as the Soft-Start ramp. Vout follows this ramp and
discharges softly until completely shut down. Figure
28 shows the timing diagram of S_Ctrl controlled softstart and soft-stop.
If the Enable pin goes low before S_Ctrl, the converter
shuts down without Soft-Stop. Both gate drivers are
turned off immediately and Vout discharges to zero.
Figure 29 shows the timing diagram of Enable
controlled soft-start and soft-stop.
29
Rev 3.5
Feb 05, 2016
IR3846
V
di L
  o , without body braking
dt
L
Enable
0
IL
VD
S_Ctrl
0
0.65V
0.65V
Intl
_SS
0.15V
0.15V
0
Vout
0
Figure 28: Timing Diagram for S_Ctrl controlled SoftStart / Soft-Stop
Vo
L
(4)
= Inductor current
= Forward voltage drop of the body diode of
the Sync FET.
= output voltage
= Inductor value
The Body Braking mechanism is kept OFF during prebias operation. Also, in the event of an extremely
severe load step-down transient causing OVP, the
Body Brake is overridden by the OVP latch, which
turns on the Sync FET.
MINIMUM ON TIME CONSIDERATIONS
The minimum ON time is the shortest amount of time
for Ctrl FET to be reliably turned on. This is very
critical parameter for low duty cycle, high frequency
applications. Conventional approach limits the pulse
width to prevent noise, jitter and pulse skipping. This
results to lower closed loop bandwidth.
S_Ctrl
0
Enable
1.2V
1.0V
0
0.65V
Intl
_SS
0.15V
0
Vout 0
Figure 29: Timing Diagram for Enable controlled SoftStart / Shutdown
BODY BRAKING
TM
The Body Braking feature of the IR3846 allows
improved transient response for step-down load
transients. A severe step-down load transient would
cause an overshoot in the output voltage and drive the
Comp pin voltage down until control saturation occurs
demanding 0% duty cycle and the PWM input to the
Control FET driver is kept OFF. When the first such
skipped pulse occurs, the IR3846 enters Body Braking
mode, wherein the Sync FET also turned OFF. The
inductor current then decays by freewheeling through
the body diode of the Sync FET. Thus, with Body
Braking, the forward voltage drop of the body diode
provides and additional voltage to discharge the
inductor current faster to the light load value as shown
in equation (3) and equation (4) below:
V  VD
di L
, with body braking
 o
dt
L
30
Rev 3.5
(3)
IR has developed a proprietary scheme to improve
and enhance minimum pulse width which utilizes the
benefits of voltage mode control scheme with higher
switching frequency, wider conversion ratio and higher
closed loop bandwidth, the latter results in reduction
of output capacitors. Any design or application using
IR3846 must ensure operation with a pulse width that
is higher than the minimum on-time. This is necessary
for the circuit to operate without jitter and pulseskipping, which can cause high inductor current ripple
and high output voltage ripple.
t on 
Vout
D

Fs PVin  Fs
(5)
In any application that uses IR3846, the following
condition must be satisfied:
t on(min)  t on
Vout
PV in  Fs
V
 PVin  Fs  out
t on(min)
t on(min) 
(6)
(7)
(8)
The minimum output voltage is limited by the
reference voltage and hence Vout(min) = 0.6V.
Therefore, for Vout(min) = 0.6V,
Feb 05, 2016
IR3846
 PVin  Fs 
Vout
t on(min)
0.6V
 PVin  Fs 
 12V / S
50nS
(9)
plot of the maximum duty ratio vs. the switching
frequency with built in input voltage feed forward
mechanism.
Therefore, at the maximum recommended input
voltage 21V and minimum output voltage, the
converter should be designed at a switching
frequency that does not exceed 571 kHz. Conversely,
for operation at the maximum recommended
operating frequency (1.5 MHz) and minimum output
voltage (0.6V). The input voltage (PVin) should not
exceed 8V, otherwise pulse skipping may happen.
MAXIMUM DUTY RATIO
A certain off-time is specified for IR3846. This
provides an upper limit on the operating duty ratio at
any given switching frequency. The off-time remains
at a relatively fixed ratio to switching period in low and
mid frequency range, while in high frequency range
this ratio increases, thus the lower the maximum duty
ratio at which IR3846 can operate. Figure 30 shows a
Figure 30: Maximum duty cycle vs. switching
frequency
TYPICAL OPERATING WAVEFORM
DESIGN EXAMPLE
PVin
IR3846
The following example is a typical application for
IR3846. The application circuit is shown in Figure 37.
R1
Enable
R2
Vin = PVin = 12V
Fs = 600kHz
Vo = 1.2V
Io = 35A
Ripple Voltage = ± 1% * Vo
ΔVo = ± 4% * Vo (for 30% load transient)
Figure 31: Using Enable pin for UVLO implementation
For a typical Enable threshold of VEN = 1.2 V
Enabling the IR3846
PV in(min) 
As explained earlier, the precise threshold of the
Enable lends itself well to implementation of a UVLO
for the Bus Voltage as shown in Figure 31.
R2  R1
R2
 V EN  1.2
R1  R2
V EN
PVin(min)  V EN
(10)
(11)
For PVin (min)=9.2V, R1=49.9K and R2=7.5K ohm is a
good choice.
Programming the frequency
For Fs = 600 kHz, select Rt = 39.2 KΩ, using Table 1.
31
Rev 3.5
Feb 05, 2016
IR3846
Output Voltage Programming
Output voltage is programmed by reference voltage
and external voltage divider. The FB pin is the
inverting input of the error amplifier, which is internally
referenced to VREF. The divider ratio is set to equal
VREF at the FB pin when the output is at its desired
value. When an external resistor divider is connected
to the output as shown in Figure 32, the output
voltage is defined by using the following equation:
 R 
Vo  Vref  1  5 
 R6 
 Vref
R6  R5  
V V
ref
 o
voltage Vin. However, if the value of C1 is
appropriately chosen, the voltage Vc across C1
remains approximately unchanged and the voltage at
the Boot pin becomes:
VBoot  PVin  Vcc  VD
(15)
Cvin
PVin
+ VD -
Boot
Vcc
(12)
C1




(13)
+
Vc
-
SW
L
IR3846
For the calculated values of R5 and R6, see feedback
compensation section.
PGnd
Figure 33: Bootstrap circuit to generate Vc voltage
Vout
IR3846
A bootstrap capacitor of value 0.1uF is suitable for
most applications.
R5
FB
R6
Input Capacitor Selection
Figure 32: Typical application of the IR3846 for
programming the output voltage
The ripple currents generated during the on time of
the control FETs should be provided by the input
capacitor. The RMS value of this ripple for each
channel is expressed by:
I RMS  I o  D  1  D
Bootstrap Capacitor Selection
To drive the Control FET, it is necessary to supply a
gate voltage at least 4V greater than the voltage at the
SW pin, which is connected to the source of the
Control FET. This is achieved by using a bootstrap
configuration, which comprises the internal bootstrap
diode and an external bootstrap capacitor (C1). The
operation of the circuit is as follows: When the sync
FET is turned on, the capacitor node connected to SW
is pulled down to ground. The capacitor charges
towards Vcc through the internal bootstrap diode
(Figure 33), which has a forward voltage drop VD. The
voltage Vc across the bootstrap capacitor C1 is
approximately given as:
Vc  Vcc  VD
(14)
When the control FET turns on in the next cycle, the
capacitor node connected to SW rises to the bus
32
Rev 3.5
D
Where:
D
IRMS
Io
Vin
(16)
Vo
Vin
(17)
= Duty Cycle
= RMS value of the input capacitor current
= output current.
= Power Stage input voltage
Io=35A and D = 0.1, the IRMS = 10.5A.
Ceramic capacitors are recommended due to their
peak current capabilities. They also feature low ESR
and ESL at higher frequency which enables better
efficiency. For this application, it is advisable to have
7x22uF,
25V
ceramic
capacitors,
Feb 05, 2016
IR3846
GRM31CR61E226KE15L from Murata. In addition to
these, although not mandatory, a 1x330uF, 25V SMD
capacitor EEV-FK1E331P from Panasonic may also
be used as a bulk capacitor and is recommended if
the input power supply is not located close to the
converter.
Inductor Selection
Inductors are selected based on output power,
operating frequency and efficiency requirements. A
low inductor value causes large ripple current,
resulting in the smaller size, faster response to a load
transient but may also result in reduced efficiency and
high output noise. Generally, the selection of the
inductor value can be reduced to the desired
maximum ripple current in the inductor (Δi). The
optimum point is usually found between 20% and 50%
ripple of the output current. For the buck converter,
the inductor value for the desired operating ripple
current can be determined using the following relation:
i
1
; t  D 
t
Fs
Vo
L  Vin  Vo  
Vin  i  Fs
Vin  Vo  L 
Where:
Vin
V0
Δi
Fs
Δt
D
(18)
= Maximum input voltage
= Output Voltage
= Inductor Ripple Current
= Switching Frequency
= On time for Control FET
= Duty Cycle
Output Capacitor Selection
The voltage ripple and transient requirements
determine the output capacitors type and values. The
criterion is normally based on the value of the
Effective Series Resistance (ESR). However the
actual capacitance value and the Equivalent Series
Inductance (ESL) are other contributing components.
These components can be described as:
Rev 3.5
V0( ESR)  I L  ESR
 V V 
V0( ESL)   in o   ESL
 L 
I L
V0(C ) 
8  Co  Fs
(19)
Where:
ΔV0 = Output Voltage Ripple
ΔIL = Inductor Ripple Current
Since the output capacitor has a major role in the
overall performance of the converter and determines
the result of transient response, selection of the
capacitor is critical. The IR3846 can perform well with
all types of capacitors.
As a rule, the capacitor must have low enough ESR to
meet output ripple and load transient requirements.
If Δi ≈ 30%*Io, then the inductor is calculated to be
0.24μH. Select L=0.25μH, 744309025, from Wurth
Electronik which provides an inductor suitable for this
application.
33
Vo  Vo ESR   Vo ESL  Vo(C )
The goal for this design is to meet the voltage ripple
requirement in the smallest possible capacitor size.
Therefore it is advisable to select ceramic capacitors
due to their low ESR and ESL and small size. Six of
Murata GRM31CR60J107ME39L (100uF/1206/X5R/
6.3V) capacitors is a good choice.
It is also recommended to use a 0.1µF ceramic
capacitor at the output for high frequency filtering.
Feedback Compensation
The IR3846 is a voltage mode controller. The control
loop is a single voltage feedback path including error
amplifier and error comparator. To achieve fast
transient response and accurate output regulation, a
compensation circuit is necessary. The goal of the
compensation network is to provide a closed-loop
transfer function with the highest 0 dB crossing
frequency and adequate phase margin (greater than
o
45 ).
The output LC filter introduces a double pole, 40dB/decade gain slope above its corner resonant
o
frequency, and a total phase lag of 180 . The resonant
frequency of the LC filter is expressed as follows:
Feb 05, 2016
IR3846
FLC 
1
VOUT
Z IN
C POLE
2    Lo  Co
R3
(20)
C3
R5
Zf
Fb
Figure 34 shows gain and phase of the LC filter. Since
o
we already have 180 phase shift from the output filter
alone, the system runs the risk of being unstable.
E/A
R6
Comp
Ve
VREF
Gain(dB)
Phase
Gain
H(s) dB
0dB
00
-40dB/Decade
FZ
-900
-1800
FLC
Frequency
FLC
Frequency
Figure 34: Gain and Phase of LC filter
The error amplifier can be compensated either in type
II or type III compensation. Local feedback with Type
II compensation is shown in Figure 35.
This method requires that the output capacitor have
enough ESR to satisfy stability requirements. If the
output capacitor’s ESR generates a zero at 5kHz to
50kHz, the zero generates acceptable phase margin
and the Type II compensator can be used.
The ESR zero of the output capacitor is expressed as
follows:
34
1
2    ESR  Co
Rev 3.5
Frequency
POLE
Figure 35: Type II compensation network and its
asymptotic gain plot
The transfer function (Ve/Vout) is given by:
The IR3846 uses a voltage-type error amplifier with
high-gain and high-bandwidth. The output of the
amplifier is available for DC gain control and AC
phase compensation.
FESR 
F
(21)
Z
Ve
1  sR3C3
 H ( s)   f  
Vout
Z IN
sR5C3
(22)
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a
gain and zero, expressed by:
H (s) 
Fz 
R3
R5
1
2    R3  C3
(23)
(24)
First select the desired zero-crossover frequency (Fo):
Fo  FESR and Fo  (1 / 5 ~ 1 / 10)  Fs
(25)
Feb 05, 2016
IR3846
Use the following equation to calculate R3:
R3 
Vramp  Fo  FESR  R5
2
Vin    FLC
VOUT
ZIN
C4
(26)
R4
Where:
Vramp = Amplitude of the oscillator Ramp Voltage
Fo = Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
R5 = Feedback Resistor
Vin = Maximum Input Voltage
β
= (RS+ - RS-) / Vo
FLC = Resonant Frequency of the Output Filter
C2
R3
C3
R5
Zf
Fb
R6
E/ A
Ve
Comp
VREF
Gain (dB)
|H(s)| dB
To cancel one of the LC filter poles, place the zero
before the LC filter resonant frequency pole:
FZ  75%  FLC
1
FZ  0.75 
2   Lo  Co
FZ1
(27)
One more capacitor is sometimes added in parallel
with C3 and R3. This introduces one more pole which
is mainly used to suppress the switching noise.
By replacing Zin and Zf, according to Figure 36, the
transfer function can be expressed as:
(28)
  R3  FS 
1
C3

1
  R3  FS
(29)
For a general unconditional stable solution for any
type of output capacitors with a wide range of ESR
values, we use a local feedback with a type III
compensation
network.
The
typically
used
compensation network for voltage-mode controller is
shown in Figure 36.
35
Rev 3.5
1  sR3C3 1  sC4 R4  R5 

 C  C3 
 1  sR4C4 
sR5 C2  C3 1  sR3  2
 C2  C3 

(30)
The pole sets to one half of the switching frequency
which results in the capacitor CPOLE:
1
Frequency
Zf
Ve
 H ( s)  
Vout
Z IN
H ( s)  
CPOLE 
FP3
Again, the transfer function is given by:
The additional pole is given by:
1
C  CPOLE
2  3
C3  CPOLE
FP2
Figure 36: Type III Compensation network and its
asymptotic gain plot
Use equation (24), (25) and (26) to calculate C3.
Fp 
FZ 2
The compensation network has three poles and two
zeros and they are expressed as follows:
FP1  0
(31)
1
2  R4  C4
1
1
FP 3 

 C  C3  2  R3  C2

2  R3  2
C

C
3 
 2
FP 2 
(32)
(33)
Feb 05, 2016
IR3846
1
2  R3  C3
1
1


2  C4  R4  R5  2  C4  R5
FZ 1 
FZ 2
(34)
(35)
Cross over frequency is expressed as:
Fo  R3  C 4   
Vin
1

Vramp 2  Lo  Co
(36)
Based on the frequency of the zero generated by the
output capacitor and its ESR, relative to the crossover
frequency, the compensation type can be different.
Table 3 shows the compensation types for relative
locations of the crossover frequency.
Lo
Co
to the RSA, β = 1. Please refer to the Remote
Sensing Amplifier section)
= 0.250 µH
= 6 x 100µF, ESR≈3mΩ each
It must be noted here that the value of the
capacitance used in the compensator design must be
the small signal value. For instance, the small signal
capacitance of the 100µF capacitor used in this
design is 56µF at 1.2 V DC bias and 600 kHz
frequency. It is this value that must be used for all
computations related to the compensation. The small
signal value may be obtained from the manufacturer’s
datasheets, design tools or SPICE models.
Alternatively, they may also be inferred from
measuring the power stage transfer function of the
converter and measuring the double pole frequency
FLC and using equation (20) to compute the small
signal Co.
Table 3: Different types of compensators
Compensator
Type
FESR vs FO
Typical Output
Capacitor
Type II
FLC < FESR < FO <
FS/2
Electrolytic
Type III
FLC < FO < FESR
SP Cap,
Ceramic
The higher the crossover frequency is, the potentially
faster the load transient response will be. However,
the crossover frequency should be low enough to
allow attenuation of switching noise. Typically, the
control loop bandwidth or crossover frequency (Fo) is
selected such that:
These result to:
FLC = 17.4 kHz
FESR = 947 kHz
Fs/2 = 300 kHz
Select crossover frequency F0=100 kHz
Since FLC<F0<Fs/2<FESR, Type III is selected to place
the pole and zeros.
Detailed calculation of compensation Type III:
Desired Phase Margin Θ = 70°
Fo  1/5 ~ 1/10 * Fs
The DC gain should be large enough to provide high
DC-regulation accuracy. The phase margin should be
o
greater than 45 for overall stability.
FZ 2  Fo
1  sin 
 14.1 kHz
1  sin 
FP 2  Fo
1  sin 
 567.1 kHz
1  sin 
Select:
The specifications for designing channel 1:
Vin = 12V
Vo = 1.2V
Vramp= 1.8V (This is a function of Vin, pls. see
Feed-Forward section)
Vref = 0.6V
β
= (RS+ - RS-) / Vo (This assumes the resistor
divider placed between Vout and the RSA
scales down the output voltage to Vref. If the
RSA is not used or Vout is connected directly
36
Rev 3.5
FZ1  0.5  FZ 2  7.05 kHz and
FP3  0.5  Fs  300 kHz
Select C4 = 2.2nF.
Calculate R3, C3 and C2:
Feb 05, 2016
IR3846
2    Fo  Lo  Co  Vramp
R3 
C4  Vin  
; R3 = 3.60 kΩ,
Select: R3 = 2.7 kΩ
1
; C3 = 8.49 nF,
2    FZ 1  R3
C3 
In this design IR3846, the PGood outer limits are set
at 95% and 120% of VREF. PGood signal is asserted
1.3ms after Vsns voltage reaches 0.95*0.6V=0.57V
(Figure 37). As long as the Vsns voltage is between
the threshold ranges, Enable is high, and no fault
happens, the PGood remains high.
The following formula can be used to set the PGood
threshold. Vout (PGood_TH) can be taken as 95% of Vout.
Choose Rsns1=4.02 KΩ.
Select: C3 = 8.2 nF
1
; C2 = 196 pF,
2    FP 3  R3
C2 
Setting the Power Good Threshold
Select: C2 = 160 pF
 Vout( PGood _ TH )

Rsns 2  
 1  Rsns1
 0.95  VREF

(37)
Rsns2 = 4.02 kΩ, Select 4.02 kΩ.
Calculate R4, R5 and R6:
1
; R4 = 127.6 Ω,
R4 
2    C4  FP 2
Vout _ OVP  VREF  1.2 
Select R4 = 127 Ω
1
; R5 = 5.13 kΩ,
2    C4  FZ 2
R5 
Vref
  Vo   Vref
Rsns1  Rsns 2
Rsns1
(38)
Vout_OVP = 1.44 V
Selecting Power Good Pull-Up Resistor
Select R5 = 4.02 kΩ
R6 
OVP comparator also uses Vsns signal for OverVoltage detection. With above values for Rsns2 and
Rsns1, OVP trip point (Vout_OVP) is
 R5 ; R6 = 4.02 kΩ,
The PGood is an open drain output and require pull
up resistors to VCC. The value of the pull-up resistors
should limit the current flowing into the PGood pin to
less than 5mA. A typical value used is 10kΩ.
Select R6 = 4.02 kΩ
If (β x Vo) equals Vref, R6 is not used.
37
Rev 3.5
Feb 05, 2016
IR3846
TYPICAL APPLICATION
INTERNALLY BIASED SINGLE SUPPLY
Vin
Cpvin1
330uF
Cpvin2
7 x 22uF
Ren2
49.9 K
Cpvin3
0.1uF
Ren1
7.5 K
En
PVin
Cboot
0.1uF
Boot
S_Ctrl
SW
Vin
Cvin
1uF
VSNS
Vp
Vcc
Cvcc
10uF
Rpg
10 K
IR3846
RSo
PGood
Comp
Vref
Cref
100pF
Rt/Sync
Rt
39.2 K
RS+
Rsns2
4.02 K
Rsns1
4.02 K
Cout
6 x 100uF
Vo
Co1
0.1 uF
RS-
OCselect
PGood
Lo
0.250uH
FB
AGND
Rbode
20
Cc3
160pF
PGND
Cc2
8.2nF
Rc2
2.7 K
Rfb2
4.02 K
Cc1
2200pF
Rc1
127
Rfb1
4.02 K
Figure 37: Application circuit for a 12V to 1.2V, 35A Point of Load Converter Using the Internal LDO
Suggested Bill of Material for application circuit 12V to 1.2V
Part Reference
Cpvin1
Cpvin2
Cref
Cvin
Cvcc
Cpvin3 Cboot Co1
Cc1
Cc2
Cc3
Cout1
Qty
1
7
1
1
1
3
1
1
1
6
Value
330uF
22uF
100pF
1.0uF
10uF
0.1uF
2200pF
8.2nF
160pF
100uF
L0
1
0.250uH
Rbd
Rc1
Rc2
Ren1
Ren2
Rfb1 Rfb2
Rsns1Rsns1
Rt
Rpg
1
1
1
1
1
U1
38
Manufacturer
Panasonic
Murata
Murata
Murata
TDK
Murata
Murata
Murata
Murata
Murata
Wurth
Electronik Inc.
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Part Number
EEV-FK1E331P
GRM31CR61E226KE15L
GRM1885C1H101JA01D
GRM188R61E105KA12D
C1608X5R1A106M
GRM188R71E104KA01D
GRM188R71H222KA01D
GRM188R71H822KA01D
GRM1885C1H161JA01D
GRM31CR60J107ME39L
20
127
2.7K
7.5K
49.9K
Description
SMD, electrolytic, 25V, 20%
1206, 25V, X5R, 10%
0603, 50V, C0G, 5%
0603, 25V, X5R, 20%
0603, 10V, X5R, 20%
0603, 25V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, NPO, 5%
1206, 6.3V, X5R, 20%
250nH,14x13x9mm
DCR=0.165ohm
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
4
4.02K
Thick Film, 0603, 1/10W, 1%
Panasonic
ERJ-3EKF4021V
1
1
39.2K
10K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
ERJ-3EKF3922V
ERJ-3EKF1002V
1
IR3846
PQFN 5x7mm
Panasonic
Panasonic
International
Rectifier
Rev 3.5
744309025
ERJ-3EKF20R0V
ERJ-3EKF1270V
ERJ-3EKF2701V
ERJ-3EKF7501V
ERJ-3EKF4992V
IR3846MPBF
Feb 05, 2016
IR3846
EXTERNALLY BIASED DUAL SUPPLIES
PVin
Cpvin1
330uF
Cpvin2
7 x 22uF
Ren2
49.9 K
Cpvin3
0.1uF
Ren1
7.5 K
En
Vin
PVin
SW
Vin
Cvin
1uF
VSNS
Vp
Rpg
10 K
IR3846
OCselect
PGood
Rt/Sync
FB
AGND
Cout
6 x 100 uF
Vo
Co1
0.1 uF
RS-
Comp
Vref
Rt
39.2 K
Rsns2
4.02 K
Rsns1
4.02 K
RSo
PGood
Cref
100pF
Lo
0.250uH
RS+
Vcc
Cvcc
10uF
Cboot
0.1uF
Boot
Rbode
20
Cc3
160pF
PGND
Cc2
8.2nF
Rc2
2.7 K
Rfb2
4.02 K
Cc1
2200pF
Rc1
127
Rfb1
4.02 K
Figure 38: Application circuit for a 12V to 1.2V, 25A Point of Load Converter using external 5V VCC
Suggested Bill of Material for application circuit 12V to 1.2V using external 5V VCC
Part Reference
Cpvin1
Cpvin2
Cref
Cvin
Cvcc
Cpvin3 Cboot Co1
Cc1
Cc2
Cc3
Cout1
Qty
1
7
1
1
1
3
1
1
1
6
Value
330uF
22uF
100pF
1.0uF
10uF
0.1uF
2200pF
8.2nF
160pF
100uF
L0
1
0.250uH
Rbd
Rc1
Rc2
Ren1
Ren2
Rfb1 Rfb2
Rsns1Rsns1
Rt
Rpg
1
1
1
1
1
U1
39
Manufacturer
Panasonic
Murata
Murata
Murata
TDK
Murata
Murata
Murata
Murata
Murata
Wurth
Electronik Inc.
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Part Number
EEV-FK1E331P
GRM31CR61E226KE15L
GRM1885C1H101JA01D
GRM188R61E105KA12D
C1608X5R1A106M
GRM188R71E104KA01D
GRM188R71H222KA01D
GRM188R71H822KA01D
GRM1885C1H161JA01D
GRM31CR60J107ME39L
20
127
2.7K
7.5K
49.9K
Description
SMD, electrolytic, 25V, 20%
1206, 25V, X5R, 10%
0603, 50V, C0G, 5%
0603, 25V, X5R, 20%
0603, 10V, X5R, 20%
0603, 25V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, NPO, 5%
1206, 6.3V, X5R, 20%
250nH,14x13x9mm
DCR=0.165ohm
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
4
4.02K
Thick Film, 0603, 1/10W, 1%
Panasonic
ERJ-3EKF4021V
1
1
39.2K
10K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
ERJ-3EKF3922V
ERJ-3EKF1002V
1
IR3846
PQFN 5x7mm
Panasonic
Panasonic
International
Rectifier
Rev 3.5
744309025
ERJ-3EKF20R0V
ERJ-3EKF1270V
ERJ-3EKF2701V
ERJ-3EKF7501V
ERJ-3EKF4992V
IR3846MPBF
Feb 05, 2016
IR3846
EXTERNALLY BIASED SINGLE SUPPLY
Vin
Cpvin1
330uF
Cpvin2
7 x 22uF
Ren2
41.2 K
Cpvin3
0.1uF
Ren1
21 K
En
PVin
SW
Vin
Cvin
1uF
VSNS
Vp
Vcc
Cvcc
10uF
Rpg
10 K
Comp
Vref
Rt/Sync
Rt
39.2 K
FB
AGND
Rsns2
4.53 K
Rsns1
4.53 K
Cout
6 x 100 uF
Vo
Co1
0.1 uF
RSRSo
PGood
Cref
100pF
Lo
0.190uH
RS+
IR3846
OCselect
PGood
Cboot
0.1uF
Boot
Rbode
20
Cc3
100pF
PGND
Cc2
8.2nF
Rc2
3.9 K
Rfb2
4.53 K
Cc1
2200pF
Rc1
78.7
Rfb1
4.53 K
Figure 39: Application circuit for a 5V to 1.2V, 25A Point of Load Converter
Suggested bill of material for application circuit 5V to 1.2V
Part Reference
Cpvin1
Cpvin2
Cref
Cvin
Cvcc
Cpvin3 Cboot Co1
Cc1
Cc2
Cc3
Cout1
Qty
1
7
1
1
1
3
1
1
1
6
Value
330uF
22uF
100pF
1.0uF
10uF
0.1uF
2200pF
8.2nF
100pF
100uF
Description
SMD, electrolytic, 25V, 20%
1206, 25V, X5R, 10%
0603, 50V, C0G, 5%
0603, 25V, X5R, 20%
0603, 10V, X5R, 20%
0603, 25V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, X7R, 10%
0603, 50V, NPO, 5%
1206, 6.3V, X5R, 20%
L0
1
0.190uH
10x6.8x7.3mm, DCR=0.20mΩ
Rbd
Rc1
Rc2
Ren1
Ren2
Rfb1 Rfb2
Rsns1Rsns1
Rt
Rpg
1
1
1
1
1
20
78.7
3.9K
21K
41.2K
4
U1
40
Part Number
EEV-FK1E331P
GRM31CR61E226KE15L
GRM1885C1H101JA01D
GRM188R61E105KA12D
C1608X5R1A106M
GRM188R71E104KA01D
GRM188R71H222KA01D
GRM188R71H822KA01D
GRM1885C1H101JA01D
GRM31CR60J107ME39L
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
Manufacturer
Panasonic
Murata
Murata
Murata
TDK
Murata
Murata
Murata
Murata
Murata
InterTechnical,LLC
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
4.53K
Thick Film, 0603, 1/10W, 1%
Panasonic
ERJ-3EKF4531V
1
1
39.2K
10K
Thick Film, 0603, 1/10W, 1%
Thick Film, 0603, 1/10W, 1%
ERJ-3EKF3922V
ERJ-3EKF1002V
1
IR3846
PQFN 5x7mm
Panasonic
Panasonic
International
Rectifier
Rev 3.5
SL40307A-R19KHF
ERJ-3EKF20R0V
ERJ-3EKF78R7V
ERJ-3EKF3901V
ERJ-3EKF2102V
ERJ-3EKF4122V
IR3846MPBF
Feb 05, 2016
IR3846
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=0-35A, Fs=600kHz, Room Temperature, No Air Flow
Figure 40: Startup with full load, Enable Signal
CH1:Vin, CH2:Vout, CH3:PGood, CH4:Enable
Figure 41: Startup with full load, VCC signal
CH1:Vin, CH2:Vout, CH3:PGood, CH4:VCC
Figure 42: Vout Startup with Pre-Bias, 1.08V
Ch2:Vout, CH3:PGood
Figure 43: Recovery from Hiccup
CH2:Vout, CH3:PGood, CH4:Iout
Figure 44: Inductor Switch Node at full load
CH2:SW
Figure 45: Output Voltage Ripple at full load
CH2:Vout
41
Rev 3.5
Feb 05, 2016
IR3846
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=3.5-14A, Fs=600kHz, Room Temperature, No air flow
Figure 46: Vout Transient Response, 3.5A to 14.0A step at 2.5A/uSec
CH2:Vout, CH4:Iout
42
Rev 3.5
Feb 05, 2016
IR3846
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=24.5-35A, Fs=600kHz, Room Temperature, No air flow
Figure 47: Vout Transient Response, 24.5A to 35A step at 2.5A/uSec
CH2:Vout, CH4:Iout
43
Rev 3.5
Feb 05, 2016
IR3846
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=35A, Fs=600kHz, Room Temperature, No air flow
Figure 48: Bode Plot with 35A load: Fo = 100.6 kHz, Phase Margin = 52.5 Degrees
44
Rev 3.5
Feb 05, 2016
IR3846
TYPICAL OPERATING WAVEFORMS
Vin=PVin=12V, Vout=1.2V, Iout=0-35A, Fs=600kHz, Room Temperature, No air flow
Figure 49: Efficiency versus load current
Figure 50: Power Loss versus load current
45
Rev 3.5
Feb 05, 2016
IR3846
LAYOUT RECOMMENDATIONS
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to perform
with less than expected results.
Make the connections for the power components in
the top layer with wide, copper filled areas or
polygons. In general, it is desirable to make proper
use of power planes and polygons for power
distribution and heat dissipation.
The inductor, input capacitors, output capacitors and
the IR3846 should be as close to each other as
possible. This helps to reduce the EMI radiated by the
power traces due to the high switching currents
through them. Place the input capacitor directly at the
PVin pin of IR3846.
The feedback part of the system should be kept away
from the inductor and other noise sources.
The critical bypass components such as capacitors for
PVin, Vin and VCC should be close to their respective
pins. It is important to place the feedback components
including feedback resistors and compensation
components close to Fb and Comp pins.
In a multilayer PCB use at least one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are referenced.
The goal is to localize the high current path to a
separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout at
a single point. It is recommended to place all the
compensation parts over the analog ground plane in
top layer.
The Power QFN is a thermally enhanced package.
Based on thermal performance it is recommended to
use at least a 6-layers PCB. To effectively remove
heat from the device the exposed pad should be
connected to the ground plane using vias. Figure
51a-f illustrates the implementation of the layout
guidelines outlined above, on the IRDC3846 6-layer
demo board.
Vout
- Ground path between
VIN- and VOUT- should
be minimized with
maximum copper
- Bypass caps should be
placed as close as
possible to their
connecting pins
PGND
PVin
- Filled vias placed
under PGND and
PVin pads to help
thermal performance.
- Compensation parts
should be placed
as close as possible
to the Comp pins
- Single point connection
between AGND &
PGND, should be placed
near the part and kept
away from noise sources
AGND
PGND
- SW node copper is
kept only at the top
layer to minimize the
switching noise
Figure 51a: IRDC3846 Demo board Layout Considerations – Top Layer
46
Rev 3.5
Feb 05, 2016
IR3846
Vout
PVin
PGND
Figure 51b: IRDC3846 Demo board Layout Considerations – Bottom Layer
PGND
Figure 51c: IRDC3846 Demo board Layout Considerations – Mid Layer 1
PGND
Figure 51d: IRDC3846 Demo board Layout Considerations – Mid Layer 2
47
Rev 3.5
Feb 05, 2016
IR3846
Vout
PVin
PGND
Figure 51e: IRDC3846 Demo board Layout Considerations – Mid Layer 3
-Feedback and Vsns traces
routing should be kept away from
noise sources
PGND
Remote Sense Traces
- tap output where voltage value is
critical.
- Avoid noisy areas and noise coupling.
- RS+ and RS- lines near each other.
- Minimize trace resistance.
Figure 51f: IRDC3846 Demo board Layout Considerations – Mid Layer 4
48
Rev 3.5
Feb 05, 2016
IR3846
PCB METAL AND COMPONENT PLACEMENT
Evaluations have shown that the best overall
performance is achieved using the substrate/PCB
layout as shown in following figures. PQFN devices
should be placed to an accuracy of 0.050mm on both
X and Y axes. Self-centering behavior is highly
dependent on solders and processes, and
experiments should be run to confirm the limits of selfcentering on specific processes. For further
®
information, please refer to “SupIRBuck Multi-Chip
Module (MCM) Power Quad Flat No-Lead (PQFN)
Board Mounting Application Note.” (AN1132)
PAD SIZES
PCB SPACING
49
Rev 3.5
Feb 05, 2016
IR3846
SOLDER RESIST


IR recommends that the larger Power or Land
Area pads are Solder Mask Defined (SMD).
This allows the underlying Copper traces to be
as large as possible, which helps in terms of
current carrying capability and device cooling
capability.
When using SMD pads, the underlying copper
traces should be at least 0.05mm larger (on
each edge) than the Solder Mask window, in
order to accommodate any layer to layer
misalignment. (i.e. 0.1mm in X & Y).
PAD SIZES

However, for the smaller Signal type leads
around the edge of the device, IR recommends
that these are Non Solder Mask Defined or
Copper Defined.

When using NSMD pads, the Solder Resist
Window should be larger than the Copper Pad
by at least 0.025mm on each edge, (i.e.
0.05mm in X & Y), in order to accommodate any
layer to layer misalignment.

Ensure that the solder resist in-between the
smaller signal lead areas are at least 0.15mm
wide, due to the high x/y aspect ratio of the
solder mask strip.
PAD SPACING
2
50
Rev 3.5
Feb 05, 2016
IR3846
STENCIL DESIGN
 Stencils for PQFN can be used with thicknesses of
0.100-0.250mm (0.004-0.010"). Stencils thinner
than 0.100mm are unsuitable because they
deposit insufficient solder paste to make good
solder joints with the ground pad; high
reductions sometimes create similar problems.
Stencils in the range of 0.125mm-0.200mm
(0.005-0.008"), with suitable reductions, give the
best results.
 Evaluations have shown that the best overall
performance is achieved using the stencil design
shown in following figure. This design is for a
stencil thickness of 0.127mm (0.005"). The
reduction should be adjusted for stencils of other
thicknesses.
SOLDER PASTE STENCIL PAD SIZES
51
Rev 3.5
Feb 05, 2016
IR3846
SOLDER PASTE STENCIL PAD SPACING
(DETAIL 1)
SOLDER PASTE STENCIL PAD SPACING
(DETAIL 2)
MARKING INFORMATION
PIN 1
LOGO
PART NUMBER
SITE/DATE/MARKING CODE
3846
?YWW?
XXXX
LOT CODE
Figure 52: Marking Information
52
Rev 3.5
Feb 05, 2016
IR3846
PACKAGING INFORMATION
DIMENSION TABLE
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
SIDE VIEW (Back)
PIN
1
A3
A
B
0.203 Ref
b1
0.45
0.50
0.55
b2
0.30
0.35
0.40
b3
0.20
0.25
0.30
b4
0.325
0.375
0.425
D
1
5.00 BSC
E
SIDE VIEW (Left)
SIDE VIEW (Right)
TOP VIEW
C
SIDE VIEW (Front)
7.00 BSC
D1
3.450
3.500
3.550
E1
1.725
1.775
1.825
D2
0.725
0.775
0.825
E2
1.292
1.342
1.392
D3
1.823
1.873
1.923
E3
1.932
1.982
2.032
L1
0.35
0.40
0.45
L2
0.822
0.872
0.922
e1
0.500 BSC
e2
0.625 BSC
e3
1.125 BSC
e4
1.250 BSC
e5
0.925 BSC
e6
1.373 BSC
e7
0.825 BSC
e8
0.750 BSC
aaa
0.05
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
N
34
PIN 1
(R0.20)
1
1
53
Rev 3.5
Feb 05, 2016
IR3846
ENVIRONMENTAL QUALIFICATIONS
Industrial
Qualification Level
Moisture Sensitivity Level
5mm x 7mm PQFN
Class A
Machine Model
(JESD22-A115A)
<200V
Human Body Model
(JESD22-A114F)
ESD
MSL2
Charged Device Model
(JESD22-C101D)
RoHS Compliant
Class 1C
1000V to <2000V
Class III
500V to ≤1000V
Yes
REVISION HISTORY
Rev.
54
Date
Description
3.0
8/1/2013
Initial DR3 Release
3.1
10/3/2013
Correct typos and equation
Added thermal derating data
3.2
4/16/2014
Update ordering options
Correct typos
3.3
11/19/2014
Change MSL
Correct packaging information
Correct block diagram
Correct typos
3.4
11/6/2015
Correct package marking
Correct package drawings
3.5
2/5/2016
Update POD, converted to Infineon format
Rev 3.5
Feb 05, 2016
IR3846
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2016
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated
herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims
any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of
intellectual property rights of any third party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated
in this document and any applicable legal requirements, norms and standards concerning customer’s products
and any use of the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your
nearest Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications
where a failure of the product or any consequences of the use thereof can reasonably be expected to result in
personal injury.
55
Rev 3.5
Feb 05, 2016