AN-737: How ADIsimADC Models an ADC (Rev. B) PDF

AN-737
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
How ADIsimADC Models an ADC
by Brad Brannon and Tom MacLeod
CONVERTER MODELING
Converter modeling has often been overlooked, omitted,
or accomplished using an ideal data converter model. With
more and more systems using mixed-signal technology, the
importance of system modeling is ever increasing. Coupled
with shortened design cycles and pressure for first pass success,
this drives the continuing importance of complete system
modeling. ADIsimADC™ has been developed to answer this
growing need.
Often ideal converter models are used for functional modeling,
but these fail to give the required details of performance to
determine if a particular device meets the desired goals of the
system. This is why ADIsimADC has been developed. For the
first time, ADIsimADC provides a means for users to validate
performance of a particular converter in their system, using
their conditions to determine the applicability of a selected
device. While ADIsimADC does not emulate every characteristic of an ADC, it goes a long way towards achieving the goal
of allowing users to model real converters in their system
simulations.
BIT EXACT vs. BEHAVIORAL
A bit exact model is a model that, given a known stimulus,
provides a known and predictable output. ADIsimADC is not a
bit exact model. These types of models are often found in digital
systems. In dealing with analog functions, there is never a known
response for a given input because of noise, distortion, and
other nonlinearities. While some portion of the response may
be predictable, much of the remainder is subject to distortion,
noise, and even part-to-part variation. Additionally, to provide
a bit exact model requires providing circuit simulation files,
such as SPICE models, that process transient response. However,
these models are large, complex, very slow and, in the end,
provide limited accuracy. A reduced or equivalent SPICE model
reduces the complexity, but is not able to provide adequate
modeling of fine details of static and dynamic performance.
A behavior model eliminates the complexity and, at the same
time, allows modeling of fine performance details not possible
to attain with a circuit file. ADIsimADC in conjunction with
VisualAnalog™ acts as a standalone converter evaluation tool.
ADIsimADC™ can also be used with many other third party
simulation tools, including ADS from Agilent Technologies,
VSS from Applied Wave Research, Inc, National Instrument
tools, as well as MATLAB® and C++. Usage information with
these tools can be found at www.analog.com/ADIsimADC.
MODEL vs. HARDWARE
Modeling a system or an ADC should never be a substitute for
building and characterizing a real system. It is one thing to model a
circuit, but it is another matter to actually build it and test it.
As with any analog or mixed-signal device, proper layout and
configuration is required to achieve the performance shown in
simulation. Therefore, it is important that all layout rules and
guidelines be followed as shown in the product data sheet (see
Figure 4). An example is the importance of providing adequate
power supply bypass capacitors. Because mixed-signal devices
include some amount of digital circuitry, digital switching noise
is often a problem, and failure to provide capacitors to moderate
these switching currents can significantly reduce performance
of even the best devices. Other support devices are often required
around the converter, including additional capacitors, inductors,
and resistors. The best way to know what is required is to consult
the product data sheet and the evaluation board schematic.
WHICH SPECIFICATIONS ARE IMPORTANT TO
MODEL?
ADIsimADC is targeted to provide realistic performance of real
devices. Which specification is important to model depends on
what kind of analysis the user is trying to perform. For example,
control loops need accurate transfer function and delay information, while radio systems may require an accurate representation of noise and distortion. ADIsimADC models many of the
critical specifications of data converters, including: offset, gain,
sample rate, bandwidth, jitter, latency, and both ac and dc linearity.
(See the AN-835 Application Note Understanding High Speed
ADC Testing and Evaluation, for additional information on ac
linearity.)
This application note describes these specifications in detail and
how ADIsimADC treats them.
Rev. B | Page 1 of 8
AN-737
Application Note
TABLE OF CONTENTS
Converter Modeling ......................................................................... 1
Bandwidth ..........................................................................................5
Bit Exact vs. Behavioral.................................................................... 1
Distortion: Dynamic and Static .......................................................5
Model vs. Hardware ......................................................................... 1
Jitter .....................................................................................................6
Which Specifications Are Important to Model?........................... 1
Latency ................................................................................................7
Gain, Offset, and DC Linearity ....................................................... 3
Conclusion..........................................................................................7
Sample Rate ....................................................................................... 5
References ...........................................................................................7
Rev. B | Page 2 of 8
Application Note
AN-737
GAIN, OFFSET, AND DC LINEARITY
The full-scale range of the converter is defined by the design of
the converter. It can be fixed, selectable, or variable. Gain error
of a converter is the deviation from the nominal value, often
called the input span. Because an ADC is a voltage input device,
the full-scale range is specified in volts at dc or low frequency.
Offset is defined as the deviation of the actual major carrier transition from one-half of the full-scale range of the converter. This
can be measured by shorting the input(s) to one-half of the full
scale. Many devices have internal connections that bias the input
pins to set up the input common-mode voltage (see Figure 1).
On such devices, it is not necessary to make this connection
externally. The input can be floated in the case of a single-ended
input, or shorted together in the case of differential inputs. Devices
that do not have connections internally to the common-mode
voltage must be externally connected (see Figure 2). As with input
span, the common-mode voltage can be either fixed or adjustable.
The device data sheet should be consulted to determine how it
is configured.
The dc linearity (see Figure 3) for an ADC is determined by the
quantization method and the static transfer function of the
converter. There are many types of converters, each of which
has a unique transfer function and produces different results at
dc and at high frequency. In the References section, see the
Brannon (2001) and Kester (2004) references for more information about the different types of converters, and how the transfer
function affects a converter performance.
1.0
0.8
0.6
0.4
0.2
AVCC
DNL
BUF
T/H
–0.4
500Ω
–0.6
500Ω
–0.8
T/H
VINB
CPAR
CPIN
CPAR
QS1
QH1 CS
–
+
QS2
CH
04907-002
VINA
QS2
CS
15,000
13,500
12,000
Figure 3. Typical Converter DNL, an Important Contributor to the Converter
Transfer Function
CH
QS1
10,500
CONVERTER CODE
Figure 1. Typical Analog Input with Internal Common-Mode Voltage
CPIN
9000
04907-001
VCL
7500
–1.0
0
BUF
AIN
04907-004
BUF
AVCC
6000
VCH
VREF
4500
VCL
3000
AIN
0
–0.2
1500
VCH
ADIsimADC does not allow either the input span or the
common mode to be changed. Different converter models are
provided for devices with multiple input spans. The common
mode is fixed for all devices and cannot be changed. If it is
desired to model a system that uses a different common-mode
range, the difference can be subtracted by an external offset.
Figure 2. Typical Analog Input Without Internal Common-Mode Voltage
Rev. B | Page 3 of 8
Figure 4. Typical Evaluation Board Schematic: Shows Typical Support Components
J5
J3
49.9
R35
AIN
(SEE NOTE 1)
DO NOT INSTALL
60.4
R2
DO NOT INSTALL
OPT_CLK
J4
ENC
R1
C3
0.1U
C4
C5
0.01U
100
0.1U
T2
OPTIONAL
VCC
OUT
14
L1
4.7NH
R10
500
8
10
12
6
5
4
7
0.1U
C29
5
6
U4
5
+V
R3
500
500
T3
V−
6
2
R5
C28
3
4
5
6
7
500
1
F5
F3
2
4
VAL
VREF
5
0.1U
C30
E1
178
R15
AIN
AIN
R14
100
R13
66.5
+3P3V
0.1U
C32
VREF
1
13
12
11
10
9
8
7
6
5
4
3
2
GND
AIN
AIN
GND
AVCC
AVCC
GND
ENCODE
ENCODE
GND
VREF
GND
DVCC
U1
52
DR _OU T
14
51
50
15
16
48
47
46
45
44
17
AD6644/AD6645
49
18
19
0.1U
C8
20
21
22
43
23
42
0.1U
C7
24
41
25
40
GND
AVCC
GND
AVCC
DNC
OVR
DVCC
GND
DMID
D0
D1
D2
D3
26
27
28
29
30
31
32
33
34
35
36
37
38
39
+5VA
9
8
7
6
5
4
9
+5VA
J1
6
5
4
3
2
1
+3P3V
PREF
10
11
12
13
14
15
2
3
16
1
100
RN3
10
7
8
11
6
13
14
15
16
12
100
RN1
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
-5V
+5V
10U
C31
+3P3VIN
F1
8
12
F2
11
12
13
14
15
16
RN4
0.01U
C4 0
10U
C2
10U
C1
+3P3V
0.1U
9
U6
10
11
12
13
14
15
1
10U
0 .0 1 U
C18
0.01U
C11
0.1U
C23
NC7SZ32
4
C38
0.01U
C17
2
E2
0.1U
C10
F4
GND
3
16
10
11
12
13
14
15
16
2
5
+V
+3P3VD
1
9
C39
0.1U
C16
0.1U
C9
BUFLAT 100
8
7
6
5
4
3
2
18
17
1
+3P3VD
19
20
RN2
BUFLAT 100
7
11
6
5
4
3
2
1
13
+3P3VD
BUFLAT
14
15
16
17
18
19
20
+3P3V_XTL
3. AC-COUPLED ENCODE IS STANDARD. C5, C6, C33, C34, R1, R11−R14 AND U8 ARE NOT INSTALLED.
IF PECL ENCODE IS REQUIRED, CR1 AND T2 ARE NOT INSTALLED.
2. AC-COUPLED AIN IS STANDARD, R3, R4, R5, R8 AND U3 ARE NOT INSTALLED.
IF DC-COUPLED AIN IS REQUIRED, C30, R15 AND T3 ARE NOT INSTALLED.
Q7
Q6
Q5
Q4
Q3
Q2
Q1
+3P3VIN
74LCX574
GND
D7
D6
D5
D4
D3
D2
D1
Q0
VCC
CLOCK
U2
OUT_EN
D0
CLOCK
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
74LCX574
GND
D7
D6
D5
D4
D3
D2
D1
D0
OUT_EN
U7
1. R2 IS INSTALLED FOR INPUT MATCHING ON THE PRIMARY OF T3. R15 IS NOT INSTALLED.
R15 IS INSTALLED FOR INPUT MATCHING ON THE SECONDARY OF T3, R2 IS NOT INSTALLED.
NOTES:
+5VA
+5VA
(SEE NOTE 1)
R6
25.5
25.5
R7
+3P3V_XTL
2
+5VA
ENC
ENC
C34
0.1U
INSTALL JUMPER
C15
0.1U
BUFLAT
VOCM
AD8138ARM
U3
NC
V+
+5VA
8
1
-5V
500
R4
C27
1
C22
0.1U
2
CR1
OPT_LAT
3
C33
0.1U
DR_OUT
ADT4-1WT
4:1
IMPEDANCE RATIO
3
1
DO NOT INSTALL
R8
4
1
R12
100
R11
66.5
DC-COUPLED AIN OPTION
(SEE NOTE 2)
GND
3
NC7SZ32
2
1
+3P3VD
66.66MHz (AD6644)
80MHz (AD6645)
GN D
GND' OUT'
OE' VCC'
OE
Y1
+3P3V
7
R9
500
5
3
1
VEE
Q
Q
VCC
MC100LVEL16
VBB
D
D
NC
ADT4-1WT
4:1
IMPEDANCE RATIO
1
3
4
3
2
8
D13
1
D12
GN D
U8
+5VA
D11
GN D
+5VA
D9
GN D
DO NOT INSTALL
DC-COUPLED ENCODE OPTION (SEE NOTE 3)
D8
C1
+3P3V
DVC C
GN D
GN D
GN D
C2
+5VA
0.0
0.0
D7
GN D
DR Y
AVC C
+5V A
D10
AVC C
+5V A
AVC C
+5V A
D6
AVC C
+5V A
D5
GN D
D4
AVC C
+5V A
Rev. B | Page 4 of 8
B00
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
0.01U
C19
0.01U
C12
0.1U
C24
OVR
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J2
0.01U
C20
+5VA
0.01U
C13
0.1U
C25
+3P3VD
E6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HEADER40
0 .0 1 U
C21
0.01U
C14
0.1U
C26
04907-032
C6
0.01U
AN-737
Application Note
Application Note
AN-737
SAMPLE RATE
BANDWIDTH
ENOB (BITS), FS
04907-006
10
1M
10M
DISTORTION: DYNAMIC AND STATIC
Due to an ADC’s finite bandwidth, there is also a fundamental
slew rate limitation, or dynamic limitation. This slew rate
limitation is one source of distortion within an ADC. As the
input frequency of a data converter is swept from dc to some
upper frequency, the SFDR performance and the harmonic
performance of the converter decline (see Figure 7).
100
95
WORST OTHER SPUR
HARMONICS (dBc)
90
95
WORST SPUR @ AIN = 2.2MHz
85
80
HARMONICS
(SECOND, THIRD)
75
65
60
80
04907-007
70
ENCODE = 80MSPS @ AIN = –1dBFS
TEMPERATURE 25°C
85
0
20
40
60
80
100 120 140
ANALOG FREQUENCY (MHz)
160
180
200
Figure 7. Typical Converter Performance vs. Analog Input Frequency
75
SNR @ AIN = 2.2MHz
04907-005
70
65
15
100
1k
10k
100k
ADC INPUT FREQUENCY (Hz)
Figure 6. Typical Converter Analog Bandwidth
100
SNR, WORST-CASE SPURIOUS (dB AND dBc)
ENOB (BITS), –20dB INPUT
1
As the analog input frequency is increased, attenuation in the
amplitude response effectively increases the apparent full-scale
range of the converter, causing a roll-off in the response of the
converter. The frequency where the response has diminished by
3 dB is called the 3 dB bandwidth of the converter.
90
FPBW = 1MHz
GAIN (dB), FS INPUT
ENOB
Converter performance changes as both the sample rate and
analog input frequency change. From a sample rate point of
view, most good converters provide consistent performance
from the minimum to the maximum specified sample rates (see
Figure 5). At sample rates below the minimum, some converters
fail to operate properly. This may be due to charges stored on
on-chip capacitors that are discharging or drooping, causing
incorrect data conversion. Therefore, the converter data sheet
should be consulted to determine the minimum usable sample
rate. Above the maximum sample rate, one of two problems
may occur. The device may not be able to pass on-chip digital
signals from one stage to the next. This is the result of running
out of setup or hold time on chip. The other problem is failure
of a critical analog signal to stabilize during the time allocated
to the process. One such example is acquisition time for a hold
capacitor. As before, the data sheet should be consulted to
determine the maximum sample rate. ADIsimADC uses the
specified sample rate to determine how the converter should
perform. However, outside the specified range of the device, the
model produces all zero results.
30
45
60
75
ENCODE FREQUENCY (MHz)
90
105
Figure 5. Typical Converter Performance vs. Sample Rate Bandwidth
A converter’s performance rolls off according to its frequency
response as the analog input frequency increases (see Figure 6).
This is modeled in ADIsimADC and results in a reduced response
within the model. To counter this loss, the input signal amplitude
must increase above the span specified as the default for the
model, resulting in an input that appears to be above the fullscale range of the converter. In reality, this signal is attenuated
by package and device parasitics, as well as the filter formed by
the hold capacitor of the sample-and-hold amplifier (SHA),
and, therefore, the signal is actually within the specified span.
Because distortion limitations are due at least in part to slew
rate issues, the amplitude of the signal input can be reduced
while keeping the analog frequency constant, resulting in a
reduced slew rate and improved harmonics and distortion
relative to the full scale of the converter. While these spurs do
not always follow the classic trend of nth-order products, this
trend can often be weakly observed. As the signal levels are
reduced, dynamic effects diminish, but static effects rapidly
replace them as the dominant contributor to distortion.
Static distortion is distortion due to the transfer function of
the converter (see Figure 8). This distortion often has some very
unpredictable results. This may include spurs that change
rapidly as a function of input level, and can exhibit both positive
and negative slope characteristics. Largely, these spurs are due
to the architecture characteristics of the converter. Different
converters have different static transfer functions, resulting in
very different distortion responses. Additionally, because these
Rev. B | Page 5 of 8
AN-737
Application Note
tJITTER = 50fs
SNR (dB)
111
16
tJITTER = 1ps
14
tJITTER = 10ps
80
12
10
tJITTER = 100ps
60
101
18
8
MISSING
CODE
tJITTER = 1ns
40
6
011
4
20
010
04907-009
DIGITAL OUTPUT
110
]
rms
tJITTER = 0.1ps
100
100
[
SNRIDEAL = –20log 2πfANALOG t JITTER
120
ENOB
are analog components, each part within the same design
exhibit different responses to an input signal. Therefore, on a
part-to-part basis, some variation exists.
100
1
FULL-SCALE SINE WAVE ANALOG INPUT FREQUENCY
04907-008
001
000
Figure 9. Typical Converter Performance vs. Jitter
There are two sources of jitter. The first is the native or internal
jitter to the device. Because most contemporary converter designers seek to minimize the internal jitter by various techniques,
internal jitter is usually the smaller (but not negligible) of the
two types. The second and major source of jitter is the external
clock jitter. When the model is computing the noise due to jitter,
these two jitter sources are combined prior to the noise being
computed.
FS
ANALOG INPUT
Figure 8. Typical Data Conversion Transfer Function
ADIsimADC attempts to model the nominal performance of
the data converter. While it does an excellent job, some part-topart variation is normal. Consult the converter data sheet to
determine what performance variation can be expected.
JITTER
ADIsimADC estimates the instantaneous slew rate of the input
signal and multiplies this by a Gaussian modeled jitter noise
source with a sigma equal to the combined rms values of the
internal and external jitter. The result is a jitter contribution to
the noise that accurately models the effects of jitter as a function
of both the analog input frequency and amplitude level. The default
for external jitter is that of the setup used during characterization
of the device. However, the user can set this to any value.
In addition to the analog input slew rate limitations of the
converter, one of the most difficult aspects of sampling high
frequency analog signals is jitter. Jitter is the sample-to-sample
variation in the sampling process at the front end of every data
converter. At low analog input frequencies, the jitter is negligible.
However, at high analog input frequencies, errors made in the
analog sampling process due to jitter can cause significant
degradation (see Figure 9). While the sampling time errors can
be on the order of femtoseconds, the resulting limitations in
SNR can be significant (see the AN-501 Application Note,
Aperture Uncertainty and ADC System Performance, available at
www.analog.com). Although there are multiple contributors to
overall noise, at high frequencies, jitter is clearly the dominant
factor, especially for high resolution converters, as shown in
Equation 1.


SNR   20 log  2f ana log t jitterrms



2
2 
2
 2V Noise
2 
2  1   

rms


   N  

 
2N
 3  2 

 

Rev. B | Page 6 of 8
(1)
Application Note
AN-737
LATENCY
REFERENCES
Many types of converters include a delay between the sample
time and when valid data appears on the digital outputs. SAR
and flash converters generally provide output data immediately
after the sample period. Multistage converters, such as pipelined
and Σ-Δ converters, do not offer an output for many clock
cycles. This is a concern for control systems and other systems
where latency is important. ADIsimADC models latency in
terms of whole values of the clock period. This has the effect of
producing invalid data at the beginning of a conversion period
while the pipeline fills, as well as producing valid data after the
end of the conversion period while the pipeline flushes. Care
must be taken when using the model to properly account for the
pipeline delay either by flushing the buffer or by other means.
Brannon, Brad. 2006. AN-501 Application Note Aperture
Uncertainty and ADC System Performance. Analog Devices,
Inc. (March).
CONCLUSION
Brannon, Brad. 2001. “DNL and Some of Its Effects on
Converter Performance.” Wireless Design and Development
(June).
Brannon, Brad and Rob Reeder. 2006. AN-835 Application Note
Understanding High Speed ADC Testing and Evaluation.
Analog Devices, Inc. (April).
Kester, Walt, ed. 2004. Analog-to-Digital Conversion. Analog
Devices, Inc. ISBN 0-916550-27-3.
Looney, Mark. Analog-to-Digital Converter (ADC) Signal-toNoise Ratio (SNR) Analysis. Unpublished paper.
ADIsimADC is a useful tool for simulating ADC performance
under specific operating conditions. The software emulates real
world conditions, enabling more complete system modeling.
While it is not a replacement for hardware, it is a good first step
to understanding how an ADC works in a system design.
Rev. B | Page 7 of 8
AN-737
Application Note
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN04907-0-4/09(B)
Rev. B | Page 8 of 8