Bank Number VREF Pin Name/Function Optional Function(s)

Pin Information for the MAX®10 10M04DA Device
Version 1.1
Note (1)
Bank Number
VREF
Pin Name/Function
Optional Function(s)
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
ADC1IN1
ADC1IN9
ADC1IN2
ADC1IN16
ADC1IN3
ADC1IN11
ADC1IN4
ADC1IN12
ADC1IN5
ADC1IN13
ADC1IN6
ADC1IN14
ADC1IN7
ADC1IN15
ADC1IN8
ADC1IN10
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
PT-10M04DA-1.1
Copyright© 2014 Altera Corp
Configuration Function
JTAGEN
TMS
Dedicated Tx/Rx Channel
Emulated LVDS Output Channel
IO Performance
F256
DIFFIO_RX_L1n
DIFFIO RX L2n
DIFFIO_RX_L1p
DIFFIO_RX_L2p
DIFFIO RX L3n
DIFFIO_RX_L4n
DIFFIO_RX_L3p
DIFFIO RX L4p
DIFFIO_RX_L5n
DIFFIO_RX_L6n
DIFFIO RX L5p
DIFFIO_RX_L6p
DIFFIO_RX_L7n
DIFFIO RX L8n
DIFFIO_RX_L7p
DIFFIO_RX_L8p
DIFFOUT_L1n
DIFFOUT L2n
DIFFOUT_L1p
DIFFOUT_L2p
DIFFOUT L3n
DIFFOUT_L4n
DIFFOUT_L3p
DIFFOUT L4p
DIFFOUT_L5n
DIFFOUT_L6n
DIFFOUT L5p
DIFFOUT_L6p
DIFFOUT_L7n
DIFFOUT L8n
DIFFOUT_L7p
DIFFOUT_L8p
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
DIFFIO_RX_L11n
DIFFOUT_L11n
DIFFIO RX L11p
DIFFIO_RX_L12n
DIFFIO_RX_L12p
DIFFIO RX L14n
DIFFIO_RX_L14p
DIFFIO_RX_L16n
DIFFIO RX L16p
DIFFIO_RX_L18n
DIFFIO_RX_L19n
DIFFIO RX L18p
DIFFIO_RX_L19p
DIFFIO_RX_L20n
DIFFIO RX L21n
DIFFIO_RX_L20p
DIFFIO_RX_L21p
DIFFIO RX L22n
DIFFOUT L11p
DIFFOUT_L12n
DIFFOUT_L12p
DIFFOUT L14n
DIFFOUT_L14p
DIFFOUT_L16n
DIFFOUT L16p
DIFFOUT_L18n
DIFFOUT_L19n
DIFFOUT L18p
DIFFOUT_L19p
DIFFOUT_L20n
DIFFOUT L21n
DIFFOUT_L20p
DIFFOUT_L21p
DIFFOUT L22n
DIFFIO_RX_L22p
DIFFOUT_L22p
DIFFIO_RX_L25n
DIFFIO_RX_L25p
DIFFIO RX L27n
DIFFIO_RX_L27p
DIFFIO_TX_RX_B1n
DIFFIO RX B2n
DIFFIO_TX_RX_B1p
DIFFIO_RX_B2p
DIFFIO TX RX B3n
DIFFIO_RX_B4n
DIFFIO_TX_RX_B3p
DIFFIO RX B4p
DIFFIO_TX_RX_B5n
DIFFIO_RX_B6n
DIFFIO TX RX B5p
DIFFIO_RX_B6p
DIFFIO_TX_RX_B7n
DIFFIO RX B8n
DIFFIO_TX_RX_B7p
DIFFIO_RX_B8p
DIFFIO TX RX B9n
DIFFOUT_L25n
DIFFOUT_L25p
DIFFOUT L27n
DIFFOUT_L27p
DIFFOUT_B1n
DIFFOUT B2n
DIFFOUT_B1p
DIFFOUT_B2p
DIFFOUT B3n
DIFFOUT_B4n
DIFFOUT_B3p
DIFFOUT B4p
DIFFOUT_B5n
DIFFOUT_B6n
DIFFOUT B5p
DIFFOUT_B6p
DIFFOUT_B7n
DIFFOUT B8n
DIFFOUT_B7p
DIFFOUT_B8p
DIFFOUT B9n
DIFFIO_TX_RX_B9p
DIFFOUT_B9p
DIFFIO_TX_RX_B10n
DIFFIO_RX_B11n
DIFFIO TX RX B10p
DIFFIO_RX_B11p
DIFFIO_TX_RX_B12n
DIFFIO RX B13n
DIFFIO_TX_RX_B12p
DIFFIO_RX_B13p
DIFFIO TX RX B14n
DIFFIO_TX_RX_B14p
DIFFIO_TX_RX_B16n
DIFFIO TX RX B16p
DIFFIO_TX_RX_B18n
DIFFIO_RX_B19n
DIFFIO TX RX B18p
DIFFIO_RX_B19p
DIFFIO_TX_RX_B20n
DIFFOUT_B10n
DIFFOUT_B11n
DIFFOUT B10p
DIFFOUT_B11p
DIFFOUT_B12n
DIFFOUT B13n
DIFFOUT_B12p
DIFFOUT_B13p
DIFFOUT B14n
DIFFOUT_B14p
DIFFOUT_B16n
DIFFOUT B16p
DIFFOUT_B18n
DIFFOUT_B19n
DIFFOUT B18p
DIFFOUT_B19p
DIFFOUT_B20n
DIFFIO_TX_RX_B20p
DIFFOUT_B20p
DIFFIO TX RX B21n
DIFFIO_TX_RX_B21p
DIFFIO_TX_RX_B27n
DIFFIO TX RX B27p
DIFFIO_RX_R1p
DIFFIO_RX_R2p
DIFFIO RX R1n
DIFFIO_RX_R2n
DIFFOUT B21n
DIFFOUT_B21p
DIFFOUT_B27n
DIFFOUT B27p
DIFFOUT_R1p
DIFFOUT_R2p
DIFFOUT R1n
DIFFOUT_R2n
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
F5
C4
F4
C3
H5
E3
G5
F2
G2
C2
F1
B2
E1
B1
D1
C1
G6
H2
J1
H3
G1
H1
J5
H6
J3
J2
M3
L1
L3
K2
J6
M2
K6
L2
N2
M1
P1
N1
K5
L6
N3
N4
P4
P2
N5
R1
M6
R3
L7
R2
R4
T3
P5
T2
R6
T5
R5
T4
M7
T7
L8
T6
R7
T8
P6
R8
P9
T9
P8
R9
M8
M9
T11
R10
P10
R11
P11
R12
M10
T13
L9
T12
P13
P12
M11
L10
P14
T14
R14
T15
VREFB1N0
TCK
TDI
TDO
CLK0n
CLK0p
CLK1n
CLK1p
DPCLK0
VREFB2N0
DPCLK1
PLL L CLKOUTn
PLL_L_CLKOUTp
VREFB3N0
VREFB4N0
Pin List F256
Page 1 of 8
Pin Information for the MAX®10 10M04DA Device
Version 1.1
Note (1)
Bank Number
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PT-10M04DA-1.1
Copyright© 2014 Altera Corp
VREF
Pin Name/Function
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Input_only
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
GND
Optional Function(s)
Configuration Function
Dedicated Tx/Rx Channel
Emulated LVDS Output Channel
IO Performance
F256
DIFFIO_RX_R3p
DIFFIO RX R3n
DIFFIO_RX_R5p
DIFFIO_RX_R6p
DIFFIO RX R5n
DIFFIO_RX_R6n
DIFFIO_RX_R7p
DIFFOUT_R3p
DIFFOUT R3n
DIFFOUT_R5p
DIFFOUT_R6p
DIFFOUT R5n
DIFFOUT_R6n
DIFFOUT_R7p
DIFFIO_RX_R7n
DIFFOUT_R7n
DIFFIO RX R8p
DIFFIO_RX_R8n
DIFFIO_RX_R10p
DIFFIO RX R11p
DIFFIO_RX_R10n
DIFFIO_RX_R11n
DIFFIO RX R14p
DIFFIO_RX_R15p
DIFFIO_RX_R14n
DIFFIO RX R15n
DIFFIO_RX_R16p
DIFFIO_RX_R17p
DIFFIO RX R16n
DIFFIO_RX_R17n
DIFFIO_RX_R18p
DIFFIO RX R18n
DIFFIO_RX_R20p
DIFFIO_RX_R20n
DIFFIO RX R22p
DIFFIO_RX_R23p
DIFFIO_RX_R22n
DIFFIO RX R23n
DIFFIO_RX_R26p
DIFFOUT R8p
DIFFOUT_R8n
DIFFOUT_R10p
DIFFOUT R11p
DIFFOUT_R10n
DIFFOUT_R11n
DIFFOUT R14p
DIFFOUT_R15p
DIFFOUT_R14n
DIFFOUT R15n
DIFFOUT_R16p
DIFFOUT_R17p
DIFFOUT R16n
DIFFOUT_R17n
DIFFOUT_R18p
DIFFOUT R18n
DIFFOUT_R20p
DIFFOUT_R20n
DIFFOUT R22p
DIFFOUT_R23p
DIFFOUT_R22n
DIFFOUT R23n
DIFFOUT_R26p
DIFFIO RX R26n
DIFFOUT R26n
DIFFIO_RX_R27p
DIFFIO RX R28p
DIFFIO_RX_R27n
DIFFIO_RX_R28n
DIFFIO RX R33p
DIFFIO_RX_R34p
DIFFIO_RX_R33n
DIFFIO RX R34n
DIFFIO_RX_T1p
DIFFIO_RX_T2p
DIFFIO RX T1n
DIFFIO_RX_T2n
DIFFIO_RX_T3p
DIFFOUT_R27p
DIFFOUT R28p
DIFFOUT_R27n
DIFFOUT_R28n
DIFFOUT R33p
DIFFOUT_R34p
DIFFOUT_R33n
DIFFOUT R34n
DIFFOUT_T1p
DIFFOUT_T2p
DIFFOUT T1n
DIFFOUT_T2n
DIFFOUT_T3p
DIFFIO_RX_T3n
DIFFOUT_T3n
DIFFIO RX T8p
DIFFIO_RX_T8n
DIFFIO_RX_T10p
DIFFIO RX T10n
DIFFIO_RX_T12p
DIFFIO_RX_T12n
DIFFIO RX T14p
DIFFIO_RX_T15p
DIFFIO_RX_T14n
DIFFIO RX T15n
DIFFIO_RX_T16p
DIFFIO_RX_T17p
DIFFIO RX T16n
DIFFIO_RX_T17n
DIFFIO_RX_T18p
DIFFOUT T8p
DIFFOUT_T8n
DIFFOUT_T10p
DIFFOUT T10n
DIFFOUT_T12p
DIFFOUT_T12n
DIFFOUT T14p
DIFFOUT_T15p
DIFFOUT_T14n
DIFFOUT T15n
DIFFOUT_T16p
DIFFOUT_T17p
DIFFOUT T16n
DIFFOUT_T17n
DIFFOUT_T18p
DIFFIO_RX_T18n
DIFFOUT_T18n
DIFFIO_RX_T19p
DIFFOUT_T19p
DIFFIO RX T19n
DIFFIO_RX_T20p
DIFFIO_RX_T21p
DIFFIO RX T20n
DIFFIO_RX_T21n
DIFFIO_RX_T22p
DIFFIO RX T23p
DIFFIO_RX_T22n
DIFFIO_RX_T23n
DIFFIO RX T24p
DIFFIO_RX_T25p
DIFFIO_RX_T24n
DIFFIO RX T25n
DIFFIO_RX_T26p
DIFFIO_RX_T26n
DIFFOUT T19n
DIFFOUT_T20p
DIFFOUT_T21p
DIFFOUT T20n
DIFFOUT_T21n
DIFFOUT_T22p
DIFFOUT T23p
DIFFOUT_T22n
DIFFOUT_T23n
DIFFOUT T24p
DIFFOUT_T25p
DIFFOUT_T24n
DIFFOUT T25n
DIFFOUT_T26p
DIFFOUT_T26n
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
High_Speed
High_Speed
High Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
Low Speed
Low_Speed
Low_Speed
L11
L12
N14
M15
P15
M14
N16
R15
P16
R16
K11
K12
K14
M16
L15
L16
J11
J14
J12
K15
J15
H15
J16
H16
D16
C16
H11
H12
G14
G16
G15
F16
G11
B15
G12
B16
F14
E15
E14
E16
D14
D15
C14
C15
D12
C13
E11
C12
F11
A14
F12
A15
F10
E10
B13
A13
D9
C9
F9
B12
E9
B11
C10
A11
B10
A12
B8
A10
B7
A9
F8
B9
E8
A8
B6
A7
C6
A6
B5
B4
C5
A5
F7
A3
E7
A2
B3
A4
T16
T10
VREFB5N0
CLK2p
CLK2n
CLK3p
CLK3n
DPCLK3
VREFB6N0
DPCLK2
PLL R CLKOUTp
PLL_R_CLKOUTn
VREFB7N0
DEV CLRn
DEV_OE
VREFB8N0
CONFIG SEL
nCONFIG
CRC_ERROR
nSTATUS
CONF_DONE
Pin List F256
Page 2 of 8
Pin Information for the MAX®10 10M04DA Device
Version 1.1
Note (1)
Bank Number
VREF
Pin Name/Function
Optional Function(s)
Configuration Function
Dedicated Tx/Rx Channel
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
REFGND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCD_PLL1
VCCD_PLL2
VCCIO1A
VCCIO1A
VCCIO1B
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO8
VCCIO8
VCCIO8
NC
NC
NC
VCCA1
VCCA2
VCCA3
VCCA4
VCCA_ADC
VCCINT
ADC_VREF
ANAIN1
Emulated LVDS Output Channel
IO Performance
F256
T1
R13
P7
P3
N9
N15
N12
M4
L14
K9
K7
K3
K16
K1
J10
H7
H14
G8
G3
G10
F15
E6
E13
D6
D3
C8
C11
B14
A16
A1
E2
K8
K10
J9
J8
J7
H9
H8
H10
G9
G7
M5
D13
H4
G4
J4
L4
K4
N8
N7
N6
N11
N10
M13
L13
K13
J13
H13
G13
F13
D11
D10
D8
D7
C7
N13
F3
D4
L5
E12
D5
M12
E5
F6
E4
D2
Note:
(1) For more information about pin definition and pin connection guidelines, refer to the
MAX 10 FPGA Device Family Pin Connection Guidelines.
PT-10M04DA-1.1
Copyright© 2014 Altera Corp
Pin List F256
Page 3 of 8
Pin Information for the MAX®10 10M04DA Device
Version 1.1
Note (1)
Bank Number
VREF
Pin Name/Function
Optional Function(s)
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB1N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB2N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
ADC1IN1
ADC1IN9
ADC1IN2
ADC1IN16
ADC1IN3
ADC1IN11
ADC1IN4
ADC1IN12
ADC1IN5
ADC1IN13
ADC1IN6
ADC1IN14
ADC1IN7
ADC1IN15
ADC1IN8
ADC1IN10
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
PT-10M04DA-1.1
©
Copyright 2014 Altera Corp
Configuration Function
Dedicated Tx/Rx Channel
Emulated LVDS Output Channel
IO Performance
U324
TMS
DIFFIO_RX_L1n
DIFFIO_RX_L2n
DIFFIO_RX_L1p
DIFFIO_RX_L2p
DIFFIO_RX_L3n
DIFFIO_RX_L4n
DIFFIO_RX_L3p
DIFFIO_RX_L4p
DIFFIO_RX_L5n
DIFFIO_RX_L6n
DIFFIO_RX_L5p
DIFFIO_RX_L6p
DIFFIO_RX_L7n
DIFFIO_RX_L8n
DIFFIO_RX_L7p
DIFFIO_RX_L8p
DIFFIO_RX_L9n
DIFFIO_RX_L10n
DIFFIO_RX_L9p
DIFFIO_RX_L10p
DIFFIO_RX_L11n
DIFFOUT_L1n
DIFFOUT_L2n
DIFFOUT_L1p
DIFFOUT_L2p
DIFFOUT_L3n
DIFFOUT_L4n
DIFFOUT_L3p
DIFFOUT_L4p
DIFFOUT_L5n
DIFFOUT_L6n
DIFFOUT_L5p
DIFFOUT_L6p
DIFFOUT_L7n
DIFFOUT_L8n
DIFFOUT_L7p
DIFFOUT_L8p
DIFFOUT_L9n
DIFFOUT_L10n
DIFFOUT_L9p
DIFFOUT_L10p
DIFFOUT_L11n
TCK
DIFFIO_RX_L11p
DIFFOUT_L11p
TDI
DIFFIO_RX_L12n
DIFFIO_RX_L13n
DIFFIO_RX_L12p
DIFFIO_RX_L13p
DIFFIO_RX_L14n
DIFFIO_RX_L15n
DIFFIO_RX_L14p
DIFFIO_RX_L15p
DIFFIO_RX_L16n
DIFFIO_RX_L17n
DIFFIO_RX_L16p
DIFFIO_RX_L17p
DIFFIO_RX_L18n
DIFFIO_RX_L19n
DIFFIO_RX_L18p
DIFFIO_RX_L19p
DIFFIO_RX_L20n
DIFFIO_RX_L21n
DIFFIO_RX_L20p
DIFFIO_RX_L21p
DIFFIO_RX_L22n
DIFFOUT_L12n
DIFFOUT_L13n
DIFFOUT_L12p
DIFFOUT_L13p
DIFFOUT_L14n
DIFFOUT_L15n
DIFFOUT_L14p
DIFFOUT_L15p
DIFFOUT_L16n
DIFFOUT_L17n
DIFFOUT_L16p
DIFFOUT_L17p
DIFFOUT_L18n
DIFFOUT_L19n
DIFFOUT_L18p
DIFFOUT_L19p
DIFFOUT_L20n
DIFFOUT_L21n
DIFFOUT_L20p
DIFFOUT_L21p
DIFFOUT_L22n
DIFFIO_RX_L22p
DIFFOUT_L22p
DIFFIO_RX_L23n
DIFFIO_RX_L24n
DIFFIO_RX_L23p
DIFFIO_RX_L24p
DIFFIO_RX_L25n
DIFFIO_RX_L26n
DIFFIO_RX_L25p
DIFFIO_RX_L26p
DIFFIO_RX_L27n
DIFFIO_RX_L28n
DIFFIO_RX_L27p
DIFFIO_RX_L28p
DIFFIO_TX_RX_B1n
DIFFIO_RX_B2n
DIFFIO_TX_RX_B1p
DIFFIO_RX_B2p
DIFFIO_TX_RX_B3n
DIFFIO_RX_B4n
DIFFIO_TX_RX_B3p
DIFFIO_RX_B4p
DIFFIO_TX_RX_B5n
DIFFIO_RX_B6n
DIFFIO_TX_RX_B5p
DIFFIO_RX_B6p
DIFFIO_TX_RX_B7n
DIFFIO_RX_B8n
DIFFIO_TX_RX_B7p
DIFFIO_RX_B8p
DIFFIO_TX_RX_B9n
DIFFOUT_L23n
DIFFOUT_L24n
DIFFOUT_L23p
DIFFOUT_L24p
DIFFOUT_L25n
DIFFOUT_L26n
DIFFOUT_L25p
DIFFOUT_L26p
DIFFOUT_L27n
DIFFOUT_L28n
DIFFOUT_L27p
DIFFOUT_L28p
DIFFOUT_B1n
DIFFOUT_B2n
DIFFOUT_B1p
DIFFOUT_B2p
DIFFOUT_B3n
DIFFOUT_B4n
DIFFOUT_B3p
DIFFOUT_B4p
DIFFOUT_B5n
DIFFOUT_B6n
DIFFOUT_B5p
DIFFOUT_B6p
DIFFOUT_B7n
DIFFOUT_B8n
DIFFOUT_B7p
DIFFOUT_B8p
DIFFOUT_B9n
DIFFIO_TX_RX_B9p
DIFFOUT_B9p
DIFFIO_TX_RX_B10n
DIFFIO_RX_B11n
DIFFIO_TX_RX_B10p
DIFFIO_RX_B11p
DIFFOUT_B10n
DIFFOUT_B11n
DIFFOUT_B10p
DIFFOUT_B11p
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
D4
C2
E4
D2
G6
B1
H6
C1
F5
D1
E5
E1
G3
F1
F2
G1
G7
H2
H7
H1
J7
J3
J8
J4
H3
J2
H4
J1
J6
K2
K7
K1
K4
L1
K3
L2
L3
M1
M3
M2
K8
N1
L8
P1
M4
R1
N3
R2
R3
P2
T3
P3
L7
T1
M7
T2
N4
U1
P4
U2
R4
U3
T4
V2
P6
V3
P5
V4
R5
U5
R6
V5
T5
T7
T6
T8
N7
U6
N8
V6
R8
U7
R9
V7
JTAGEN
VREFB1N0
TDO
CLK0n
CLK0p
CLK1n
CLK1p
DPCLK0
VREFB2N0
DPCLK1
PLL_L_CLKOUTn
PLL_L_CLKOUTp
VREFB3N0
Pin List U324
Page 4 of 8
Pin Information for the MAX®10 10M04DA Device
Version 1.1
Note (1)
Bank Number
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
PT-10M04DA-1.1
©
Copyright 2014 Altera Corp
VREF
Pin Name/Function
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB3N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB4N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB5N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
Configuration Function
Dedicated Tx/Rx Channel
Emulated LVDS Output Channel
IO Performance
U324
DIFFIO_TX_RX_B12n
DIFFIO_RX_B13n
DIFFIO_TX_RX_B12p
DIFFIO_RX_B13p
DIFFIO_TX_RX_B14n
DIFFIO_RX_B15n
DIFFIO_TX_RX_B14p
DIFFIO_RX_B15p
DIFFIO_TX_RX_B16n
DIFFIO_RX_B17n
DIFFIO_TX_RX_B16p
DIFFIO_RX_B17p
DIFFIO_TX_RX_B18n
DIFFIO_RX_B19n
DIFFIO_TX_RX_B18p
DIFFIO_RX_B19p
DIFFIO_TX_RX_B20n
DIFFOUT_B12n
DIFFOUT_B13n
DIFFOUT_B12p
DIFFOUT_B13p
DIFFOUT_B14n
DIFFOUT_B15n
DIFFOUT_B14p
DIFFOUT_B15p
DIFFOUT_B16n
DIFFOUT_B17n
DIFFOUT_B16p
DIFFOUT_B17p
DIFFOUT_B18n
DIFFOUT_B19n
DIFFOUT_B18p
DIFFOUT_B19p
DIFFOUT_B20n
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
V9
U8
U9
V8
M8
V10
M9
V11
T9
V12
T10
U11
P10
U12
N11
U13
M10
T11
L10
T12
R10
V13
R11
V14
R12
T13
R13
T14
R14
V15
T15
U15
U16
V16
U17
V17
N14
T16
P14
R16
M12
U18
M11
T18
N15
N16
M15
M16
R15
P16
P15
P17
L12
T17
L11
R17
L15
L16
K15
K16
R18
N18
P18
M18
K12
M17
K11
L18
L17
K18
K17
J18
H18
H17
G18
G17
J11
J12
J15
J16
H15
H16
H11
F18
VREFB4N0
DIFFIO_TX_RX_B20p
DIFFOUT_B20p
DIFFIO_TX_RX_B21n
DIFFIO_RX_B22n
DIFFIO_TX_RX_B21p
DIFFIO_RX_B22p
DIFFIO_TX_RX_B23n
DIFFIO_RX_B24n
DIFFIO_TX_RX_B23p
DIFFIO_RX_B24p
DIFFIO_TX_RX_B25n
DIFFIO_RX_B26n
DIFFIO_TX_RX_B25p
DIFFIO_RX_B26p
DIFFIO_TX_RX_B27n
DIFFIO_RX_B28n
DIFFIO_TX_RX_B27p
DIFFIO_RX_B28p
DIFFIO_RX_R1p
DIFFIO_RX_R2p
DIFFIO_RX_R1n
DIFFIO_RX_R2n
DIFFIO_RX_R3p
DIFFIO_RX_R4p
DIFFIO_RX_R3n
DIFFIO_RX_R4n
DIFFIO_RX_R5p
DIFFIO_RX_R6p
DIFFIO_RX_R5n
DIFFIO_RX_R6n
DIFFIO_RX_R7p
DIFFOUT_B21n
DIFFOUT_B22n
DIFFOUT_B21p
DIFFOUT_B22p
DIFFOUT_B23n
DIFFOUT_B24n
DIFFOUT_B23p
DIFFOUT_B24p
DIFFOUT_B25n
DIFFOUT_B26n
DIFFOUT_B25p
DIFFOUT_B26p
DIFFOUT_B27n
DIFFOUT_B28n
DIFFOUT_B27p
DIFFOUT_B28p
DIFFOUT_R1p
DIFFOUT_R2p
DIFFOUT_R1n
DIFFOUT_R2n
DIFFOUT_R3p
DIFFOUT_R4p
DIFFOUT_R3n
DIFFOUT_R4n
DIFFOUT_R5p
DIFFOUT_R6p
DIFFOUT_R5n
DIFFOUT_R6n
DIFFOUT_R7p
DIFFIO_RX_R7n
DIFFOUT_R7n
DIFFIO_RX_R8p
DIFFIO_RX_R9p
DIFFIO_RX_R8n
DIFFIO_RX_R9n
DIFFIO_RX_R10p
DIFFIO_RX_R11p
DIFFIO_RX_R10n
DIFFIO_RX_R11n
DIFFIO_RX_R12p
DIFFIO_RX_R13p
DIFFIO_RX_R12n
DIFFIO_RX_R13n
DIFFIO_RX_R14p
DIFFIO_RX_R15p
DIFFIO_RX_R14n
DIFFIO_RX_R15n
DIFFIO_RX_R16p
DIFFIO_RX_R17p
DIFFIO_RX_R16n
DIFFIO_RX_R17n
DIFFIO_RX_R18p
DIFFIO_RX_R19p
DIFFIO_RX_R18n
DIFFIO_RX_R19n
DIFFIO_RX_R20p
DIFFIO_RX_R20n
DIFFIO_RX_R22p
DIFFIO_RX_R23p
DIFFIO_RX_R22n
DIFFIO_RX_R23n
DIFFIO_RX_R26p
DIFFOUT_R8p
DIFFOUT_R9p
DIFFOUT_R8n
DIFFOUT_R9n
DIFFOUT_R10p
DIFFOUT_R11p
DIFFOUT_R10n
DIFFOUT_R11n
DIFFOUT_R12p
DIFFOUT_R13p
DIFFOUT_R12n
DIFFOUT_R13n
DIFFOUT_R14p
DIFFOUT_R15p
DIFFOUT_R14n
DIFFOUT_R15n
DIFFOUT_R16p
DIFFOUT_R17p
DIFFOUT_R16n
DIFFOUT_R17n
DIFFOUT_R18p
DIFFOUT_R19p
DIFFOUT_R18n
DIFFOUT_R19n
DIFFOUT_R20p
DIFFOUT_R20n
DIFFOUT_R22p
DIFFOUT_R23p
DIFFOUT_R22n
DIFFOUT_R23n
DIFFOUT_R26p
VREFB5N0
CLK2p
CLK2n
CLK3p
CLK3n
DPCLK3
VREFB6N0
Pin List U324
Page 5 of 8
Pin Information for the MAX®10 10M04DA Device
Version 1.1
Note (1)
Bank Number
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PT-10M04DA-1.1
©
Copyright 2014 Altera Corp
VREF
Pin Name/Function
Optional Function(s)
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB6N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB7N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
VREFB8N0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Input_only
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
GND
GND
GND
GND
GND
DPCLK2
Configuration Function
PLL_R_CLKOUTp
PLL_R_CLKOUTn
Dedicated Tx/Rx Channel
Emulated LVDS Output Channel
IO Performance
U324
DIFFIO_RX_R26n
DIFFOUT_R26n
DIFFIO_RX_R27p
DIFFIO_RX_R28p
DIFFIO_RX_R27n
DIFFIO_RX_R28n
DIFFIO_RX_R29p
DIFFIO_RX_R30p
DIFFIO_RX_R29n
DIFFIO_RX_R30n
DIFFIO_RX_R31p
DIFFIO_RX_R32p
DIFFIO_RX_R31n
DIFFIO_RX_R32n
DIFFIO_RX_R33p
DIFFIO_RX_R34p
DIFFIO_RX_R33n
DIFFIO_RX_R34n
DIFFIO_RX_T1p
DIFFIO_RX_T2p
DIFFIO_RX_T1n
DIFFIO_RX_T2n
DIFFIO_RX_T3p
DIFFOUT_R27p
DIFFOUT_R28p
DIFFOUT_R27n
DIFFOUT_R28n
DIFFOUT_R29p
DIFFOUT_R30p
DIFFOUT_R29n
DIFFOUT_R30n
DIFFOUT_R31p
DIFFOUT_R32p
DIFFOUT_R31n
DIFFOUT_R32n
DIFFOUT_R33p
DIFFOUT_R34p
DIFFOUT_R33n
DIFFOUT_R34n
DIFFOUT_T1p
DIFFOUT_T2p
DIFFOUT_T1n
DIFFOUT_T2n
DIFFOUT_T3p
DIFFIO_RX_T3n
DIFFOUT_T3n
DIFFIO_RX_T4p
DIFFIO_RX_T5p
DIFFIO_RX_T4n
DIFFIO_RX_T5n
DIFFIO_RX_T6p
DIFFIO_RX_T7p
DIFFIO_RX_T6n
DIFFIO_RX_T7n
DIFFIO_RX_T8p
DIFFIO_RX_T9p
DIFFIO_RX_T8n
DIFFIO_RX_T9n
DIFFIO_RX_T10p
DIFFIO_RX_T11p
DIFFIO_RX_T10n
DIFFIO_RX_T11n
DIFFIO_RX_T12p
DIFFIO_RX_T13p
DIFFIO_RX_T12n
DIFFIO_RX_T13n
DIFFIO_RX_T14p
DIFFIO_RX_T15p
DIFFIO_RX_T14n
DIFFIO_RX_T15n
DIFFIO_RX_T16p
DIFFIO_RX_T17p
DIFFIO_RX_T16n
DIFFIO_RX_T17n
DIFFIO_RX_T18p
DIFFOUT_T4p
DIFFOUT_T5p
DIFFOUT_T4n
DIFFOUT_T5n
DIFFOUT_T6p
DIFFOUT_T7p
DIFFOUT_T6n
DIFFOUT_T7n
DIFFOUT_T8p
DIFFOUT_T9p
DIFFOUT_T8n
DIFFOUT_T9n
DIFFOUT_T10p
DIFFOUT_T11p
DIFFOUT_T10n
DIFFOUT_T11n
DIFFOUT_T12p
DIFFOUT_T13p
DIFFOUT_T12n
DIFFOUT_T13n
DIFFOUT_T14p
DIFFOUT_T15p
DIFFOUT_T14n
DIFFOUT_T15n
DIFFOUT_T16p
DIFFOUT_T17p
DIFFOUT_T16n
DIFFOUT_T17n
DIFFOUT_T18p
DIFFIO_RX_T18n
DIFFOUT_T18n
DIFFIO_RX_T19p
DIFFOUT_T19p
DIFFIO_RX_T19n
DIFFIO_RX_T20p
DIFFIO_RX_T21p
DIFFIO_RX_T20n
DIFFIO_RX_T21n
DIFFIO_RX_T22p
DIFFIO_RX_T23p
DIFFIO_RX_T22n
DIFFIO_RX_T23n
DIFFIO_RX_T24p
DIFFIO_RX_T25p
DIFFIO_RX_T24n
DIFFIO_RX_T25n
DIFFIO_RX_T26p
DIFFIO_RX_T27p
DIFFIO_RX_T26n
DIFFIO_RX_T27n
DIFFOUT_T19n
DIFFOUT_T20p
DIFFOUT_T21p
DIFFOUT_T20n
DIFFOUT_T21n
DIFFOUT_T22p
DIFFOUT_T23p
DIFFOUT_T22n
DIFFOUT_T23n
DIFFOUT_T24p
DIFFOUT_T25p
DIFFOUT_T24n
DIFFOUT_T25n
DIFFOUT_T26p
DIFFOUT_T27p
DIFFOUT_T26n
DIFFOUT_T27n
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
High_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
Low_Speed
H12
E18
F15
G16
G15
F16
E16
D18
D16
E17
G11
C18
G12
B18
E15
D17
D15
C17
E14
B17
D14
B16
D12
A17
D13
A16
C16
A15
C15
A14
C14
B14
C13
B13
F11
C12
F12
B12
C11
A13
B11
A12
D10
A11
D9
A10
F10
A9
G10
A8
B9
C10
B8
C9
D8
A7
D7
B7
G9
A6
H9
A5
C6
C8
B5
C7
C5
A4
C4
B4
G8
A3
H8
B3
D6
A2
D5
B2
V18
V1
U4
U14
U10
R7
VREFB7N0
DEV_CLRn
DEV_OE
VREFB8N0
CONFIG_SEL
nCONFIG
CRC_ERROR
nSTATUS
CONF_DONE
Pin List U324
Page 6 of 8
Pin Information for the MAX®10 10M04DA Device
Version 1.1
Note (1)
Bank Number
VREF
Pin Name/Function
Optional Function(s)
Configuration Function
Dedicated Tx/Rx Channel
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
REFGND
VCC
VCC
VCC
VCC
VCCD_PLL1
VCCD_PLL2
VCCIO1A
VCCIO1A
VCCIO1B
VCCIO1B
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO8
VCCIO8
VCCIO8
VCCIO8
NC
NC
VCCA1
VCCA2
VCCA3
VCCA4
VCCA_ADC
VCCINT
ADC_VREF
ANAIN1
Emulated LVDS Output Channel
IO Performance
U324
N5
N2
N17
N12
N10
M14
L4
K9
K6
K13
J17
J10
H14
G4
G2
F8
F17
E6
E13
E10
D3
B6
B15
B10
A18
A1
E3
L9
K10
J9
H10
N6
F13
H5
G5
K5
J5
M5
L6
L5
P9
P8
P7
N9
P12
P11
M13
L14
L13
K14
J14
J13
H13
G14
G13
E12
E11
D11
F9
E9
E8
E7
N13
F7
M6
F14
F6
P13
F4
C3
F3
E2
Note:
(1) For more information about pin definition and pin connection guidelines, refer to the
MAX 10 FPGA Device Family Pin Connection Guidelines.
PT-10M04DA-1.1
©
Copyright 2014 Altera Corp
Pin List U324
Page 7 of 8
Pin Information for the MAX®10 10M04DA Device
Version 1.1
Version Number
Date
1.0
9/22/2014
1.1
12/15/2014
PT-10M04DA-1.1
Copyright© 2014 Altera Corp.
Changes Made
Initial release.
-Updated the BOOT_SEL pin name to CONFIG_SEL pin name.
-Removed differential pair pins for non-differential function support.
Revision History
Page 8 of 8