IPC-SA103A-DT
SATA Device
Core
HYDRA SATA Bridge
withAppNCQ
Overview
IntelliProp’s IPC-SA103A-DT is an industry standard Serial-ATA
(SATA) device interface core that allows companies to build high
speed storage devices. The protocol interface is compliant to the
SATA 3.0 specification as defined by the Serial ATA International
Organization (SATA-IO). The IPC-SA103A-DT is fully verified
using a coverage driven methodology in pseudo random
simulation.
IPC-SA103A-DT
SATA Device App Core
SATA Device App Core Facts
Applications
The IPC-SA103A-DT is available for integration into device ASIC
or FPGA designs to provide an industry compliant SATA 1.5 Gb/s,
SATA 3.0 Gb/s, or SATA 6.0 Gb/s interface. Some of the target
applications for the IPC-SA103A-DT are:
Provided with Core
Documentation
Comprehensive User Documentation
Design File Formats
Encrypted Verilog
Constraints Files
UCF, XDC, or SDC
Verification
ModelSim verification model and

Internal connections to computer motherboards

E-SATA storage
Instantiation Templates

HDD or SDD
Reference Designs &
Application Notes
testbench with SATA Host Model
Additional Items
Synthesis and place and route scripts
Simulation Script, Sample Vectors,
Reference Designs
Features

VHDL/Verilog
Simulation Tool Used
Fully compliant to the SATA 1.5Gb/s, 3.0Gb/s, and
Modelsim 10.1a or newer
Support
6.0Gb/s industry specifications
The core is delivered and warranted against defects for 6

Application layer (command based) interface

Data Interface through FIFOs

Processor interface for register access

Supports either SerDes, PIPE, or SAPIS interface

Synchronous design for easy integration

Verilog/VHDL Support
FPGA Support:

Power Modes (partial/slumber)

IntelliProp’s SATA Core is available for integration into
FPGA devices or other silicon processes.
Built in Self Test
months from delivery. Phone and email technical support is
included for 6 months from the delivery date.
Notes
Other simulators are available. Please contact IntelliProp for
more information.
IntelliProp Inc.
URL: www.IntelliProp.com
E-mail: info@IntelliProp.com
303-774-0535
105 S. Sunset St., Suite N
Longmont, CO 80501
IPC-SA101A-DT Rev 3.4
7/13
© 2013 IntelliProp, Inc. All rights reserved. IntelliProp and the IntelliProp logo are trademarks of IntelliProp Inc.
Disclaimer: IntelliProp expressly disclaims any liability that might result from the use of this document or the information included herein. IntelliProp reserves the right to
Make changes without notice to any product described herein to improve reliability, function, or design. Information in this document is subject to change without notice.
IPC-SA103A-DT
www.IntelliProp.com
SATA Device App Core
SERDES
IntelliProp SATA Device Core
PHY
Layer
text
LNK
Layer
TRN
Layer
APP
Layer
SATA Core Block Diagram
Functional Description
The IPC-SA103A-DT is designed to be connected to a SATA-compliant device application to send and receive Out of
Band (OOB) signals, primitives and SATA Frame Information Structures (FIS). The SATA device core, as shown in the
block diagram, is comprised of three blocks (Phy Layer, Link Layer, and Trn Layer), the Application layer logic, and the
device specific SerDes.
Block Descriptions
2

Phy Layer and SerDes Interface
The PHY layer block includes the OOB state machine, 8b/10b encoder and decoder, speed negotiation logic,
running disparity checker and logic to check valid Dwords and align primitives.

LINK Layer
The Link layer block includes the link state machine, Cyclic Redundancy Check (CRC) generator, and scrambler.
On the transmit path, when requested by the transport layer, the Link layer converts the FIS into SATA frame by
adding Start of Frame (SOF), CRC and End of Frame (EOF). The Link layer state machine sends the frame
according to the correct sequence of primitives. The Link layer also handles an incoming frame on the receive
path as well as BIST frames. The Link layer includes logic to handle Partial and Slumber power down modes.

TRN (Transport) Layer
The Transport layer of the SATA device core includes a transport state machine, FIS Header RAM, shadow
register block, FIFO interface, interrupt mechanism and RAM for frame sequences. The TRN layer is also used to
process the received FIS.

Application Interface (Optional)
The Application Interface will handle responding to the ATA protocol such as Non-data, PIO read/write and DMA
read/write. With simple control pins, the core is capable of handling ATA commands and transferring data
through the FIFO interface.
IPC-SA103A-DT Rev 3.4
7/13
© 2013 IntelliProp, Inc. All rights reserved. IntelliProp and the IntelliProp logo are trademarks of IntelliProp Inc.
Disclaimer: IntelliProp expressly disclaims any liability that might result from the use of this document or the information included herein. IntelliProp reserves the right to
Make changes without notice to any product described herein to improve reliability, function, or design. Information in this document is subject to change without notice.
IPC-SA103A-DT
www.IntelliProp.com
SATA Device App Core

Data Interface
The FIFO interface is used to temporarily store and transfer data in and out of the SATA device core. The FIFO
size (1, 2, or 8k) is dependent on the size of the data bus width (32 bits). The FIFO size is user configurable.
Support
IntelliProp’s SATA Device Core is delivered and warranted against defects for six (6) months. Purchase of the SATA core
includes phone and email technical support for six (6) months from the delivery date.
Deliverables
The core includes everything required for successful implementation:


Encrypted RTL
Self-checking test bench in Verilog using Modelsim 10.1a (or newer). Other simulators may be supported, please
check with IntelliProp.
Simulation script, vectors, and expected results
Synthesis or place and route script
Comprehensive user documentation



Core Modifications
Modifications are generally not permitted to the SATA device core. Any modifications that are requested must be
presented to IntelliProp to determine the plausibility of integrating such changes.
Core Signals
Descriptions of all signal I/O are provided in the table below.
Table 1: Core I/O Signals.
I/O
I
Signal
CLOCK_DW
Source
Global system clock (Dword clock)
Global
I
CLOCK_BYTE
Global system clock (Byte clock)
Global
I
RESETB
Global reset (negative assertion).
Global
Encrypted key (do not touch)
Global
Reference clock used for speed negotiation circuitry if supported
Global
Global reset for power on. Used in speed negotiation circuitry if
supported
Global
I
I
CONFIG[63:0]
REFCLK
I
POWER_ON_RESETB
3
Description
I
PAR_SLUMB
I
ALLOW _POWERDOWN
Partial/Slumber is accepted if requested
Allows core to send PMACK to any power down requests from
SATA interface
IPC-SA103A-DT Rev 3.4
Power Mgmt
Power Mgmt
7/13
© 2013 IntelliProp, Inc. All rights reserved. IntelliProp and the IntelliProp logo are trademarks of IntelliProp Inc.
Disclaimer: IntelliProp expressly disclaims any liability that might result from the use of this document or the information included herein. IntelliProp reserves the right to
Make changes without notice to any product described herein to improve reliability, function, or design. Information in this document is subject to change without notice.
IPC-SA103A-DT
www.IntelliProp.com
SATA Device App Core
I/O
Signal
Description
Source
I
PARTIAL_GO
Power Mgmt
I
SLUMBER_GO
I
WAKE_UP
O
CORE_INSLEEP
To force the core to go into partial mode, set this to a 1. The core
at the next idle routine will request for power modes.
To force the core to go into slumber mode, set this to a 1. The core
at the next idle routine will request for power modes.
To wake up the core when in partial or slumber, set this bit. The
core will initiate wake up rather than be woken up by the other
SATA device or host.
When set, the core is sleeping as requested and acknowledged by
the other SATA host or device.
O
OOB_WAKE_RECOVER
I
KEEP_BUSY_OFF
O
DATATX_FIS_ERROR
O
SPEED_30
O
SPEED_15
O
SYNC-RCVD
O
FRAME_RETRYING
O
DC_RERR
O
O
CRCBAD
CRCGOOD
O
BIST_MODE
O
EVAL_WARNING
I
RELEASE_RX_FIS
I
SEND_RERR
I
O
4
Input that keeps the core busy until ready. Good way to throttle
incoming frame transfer requests (The core will not respond to
XRDY until this bit is cleared). Used with other signals below (but
for MANUAL transfer control only!).
Frame was transmitted but with errors (an RERR was received)
The Core is in speed 3.0 GHz (when = 1)
The Core is in speed 1.5GHz (when = 1)
SYNC primitive received
Frame received error and because Auto retry is on, the core is
retrying the frame. Allow retry must be on.
Primitive RERR was decoded on the RX path. Will be set while
receiving this primitive.
CRC did not match for current frame received. Use this signal if
bypassing Core CRC. The core will respond with RERR
automatically, but this signals is good for manual control.
CRC matched for current RX frame. Use this signal when using
the RELEASE_RX_FIS signal. The core does this automatically,
but this signals is good for manual control.
When = 1, the core is in BIST mode
Power Mgmt
Power Mgmt
Power Mgmt
Configuration
Configuration
Configuration
Configuration
Configuration
Configuration
Configuration
Configuration
Configuration
Configuration
When = 1, the core is within 15 minutes of locking up. Only for
evaluation mode customers. Tie to LED for visual observation.
Allows Link to respond to FIS being received (good or bad). Can
also be used to control when frames are released and how.
In manual release, when RELEASE_RX_FIS is set, and this bit is
set, the Core will be forced to send RERR even if CRC matched or
was good.
Inject a bad CRC value on the frame transmitted. The CRC is
inverted in the link and sent. Core should expect RERR response.
Configuration
Configuration
BYPASS_CRC
Bypass the Core CRC. The core will grab an additional DWord
from the Header registers and send that as the CRC. For DATA
frames, the user should set the datasize to the datapayload + 1 for
the CRC Dword. For DATA Frames, the CRC comes from the
FIFO.
DC_ROK
Core received an ROK primitive on the RX path. Will be set while
receiving this primitive.
Configuration
INJECT_CRC
I
O
Received an OOB (Comwake) on recovery from partial/slumber
Power Mgmt
XRDY_RCVD
Core received an XRDY request. Use this with KEEP BUSY OFF
IPC-SA103A-DT Rev 3.4
Configuration
Configuration
Configuration
Configuration
7/13
© 2013 IntelliProp, Inc. All rights reserved. IntelliProp and the IntelliProp logo are trademarks of IntelliProp Inc.
Disclaimer: IntelliProp expressly disclaims any liability that might result from the use of this document or the information included herein. IntelliProp reserves the right to
Make changes without notice to any product described herein to improve reliability, function, or design. Information in this document is subject to change without notice.
IPC-SA103A-DT
www.IntelliProp.com
SATA Device App Core
I/O
Signal
Description
Source
to hold the Core from responding automatically, if needed.
The CORE will send XRDY to keep the SATA bus busy or
occupied. This is not the best way to handle throughput, but does
provide another option for users to throttle transfers.
Configuration
SEND_XRDY
Use this input to control when the Core should accept XRDY. Can
be used with KEEP_BUSY_OFF, SEND_XRDY, and
XRDY_RCVD for manual control on frame transmit and receive.
Configuration
ACPT_XRDY
RRDY_RCVD
Core decoded or received a RRDY primitive. Will be set while
receiving this primitive.
Configuration
SOF_RCVD
Core decoded or received a SOF primitive. Will be set while
receiving this primitive.
Configuration
RXHEADERCOUNTER[3:0]
Number of DWords received in the non-data frame received.
Configuration
TX_CRC_VAL[31:0]
This is the 32-bit value of CRC that the core generated and sent
with the frame just transmitted.
Configuration
UNSUPPORTED FIS
Frame received is not a valid FIS type. Contents are stored in
RXHDR registers.
Configuration
I
I
O
O
O
O
O
I
APCTRL_UP[9:0]
I
INTXHDRDATAREG0[31:0]
I
INTXHDRDATAREG1[31:0]
I
INTXHDRDATAREG2[31:0]
I
INTXHDRDATAREG3[31:0]
I
INTXHDRDATAREG4[31:0]
I
INTXHDRDATAREG5[31:0]
I
INTXHDRDATAREG6[31:0]
I
ITXHDRDATAREG7[31:0]
I
IN_DATASIZE[31:0]
O
OP_RXHDR_DATAREG0[31:0
]
5
O
OPRXHDR_DATAREG1[31:0]
O
OPRXHDR_DATAREG2[31:0]
O
OPRXHDR_DATAREG3[31:0]
O
OPRXHDR_DATAREG4[31:0]
Application control register contents (9 bits)
Non-micro
32 bit register – header register
Non-micro
32 bit register – header register
Non-micro
32 bit register – header register
Non-micro
32 bit register – header register
Non-micro
32 bit register – header register
Non-micro
32 bit register – header register
Non-micro
32 bit register – header register
Non-micro
32 bit register – header register (for CRC insertion and bypass
Core CRC)
Non-micro
Application control for the size of the data transfer
Non-micro
32 bit register – header register
Non-micro
32 bit register – header register
Non-micro
32 bit register – header register
Non-micro
32 bit register – header register
Non-micro
32 bit register – header register
Non-micro
IPC-SA103A-DT Rev 3.4
7/13
© 2013 IntelliProp, Inc. All rights reserved. IntelliProp and the IntelliProp logo are trademarks of IntelliProp Inc.
Disclaimer: IntelliProp expressly disclaims any liability that might result from the use of this document or the information included herein. IntelliProp reserves the right to
Make changes without notice to any product described herein to improve reliability, function, or design. Information in this document is subject to change without notice.
IPC-SA103A-DT
www.IntelliProp.com
SATA Device App Core
I/O
Signal
O
OPRXHDR_DATAREG5[31:0]
O
OPRXHDR_DATAREG6[31:0]
O
OPRXHDR_DATAREG7[31:0]
O
DATACOUNT[15:0]
O
SYNCT_RCVD_TX
O
SYNCT_RCVD_RX
I
SEND_SYNCT_TX
I
SEND_SYNCT_RX
I
DATAFRM_TX_FIFO[31:0]
O
DATA_TO_RX_FIFO[31:0]
O
FIFO_TX_RD
O
FIFO_RX_WR
I
FIFO_FULLIN_RX
I
FIFO_EMPTY_TX
I
FIFO_WARNIN_RX
Description
Source
32 bit register – header register
Non-micro
32 bit register – header register
Non-micro
32 bit register – header register (returns the CRC of the longest
frame)
Non-micro
Size of the data frame received
Sync Terminate received during transmission of FIS
Sync Terminate received during reception of FIS
Send Sync Terminate on the frame being transmitted from Core
Send Sync Terminate on the frame being received by Core
32bit data bus for data from the FIFO to the core for transmit
32bit data bus for data received by the core to the FIFO for storage
An enable (=1) for when the core wants to read from the FIFO.
This signal may go high and low several times during a data
transfer.
An enable (=1) for when the core want to write data into the FIFO.
This signal may go high or low several times during a data transfer.
The FIFO is full and cannot accept any more dwords. This is a
fatal or data corruption condition.
FIFO is empty when this signal is a 1. This means that there is no
more data to transmit. Core will send HOLD primitives if it
expected to send more dwords. On the last Dword, this signal can
go high, but the core will know that it is okay.
FIFO is near full on data transferred from the Core to the FIFO.
When set, the core will begin sending HOLD primitives to stall data
transfers from the other SATA host or device.
Non-micro
Non-micro
Non-micro
Non-micro
Non-micro
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
Verification Methods
The SATA Device Core design is used in multiple SATA applications in which it has been tested with multiple hosts at
Gen 1, Gen 2 and Gen 3 speed. Verification done internally at IntelliProp was completed using a constrained random
testbench, Specman e and Cadence IUS tools, and a coverage driven methodology.
Recommended Design Experience
Users of the SATA Device Core are expected to have a good working knowledge of the SATA Specification and
Application layer knowledge of the SATA protocol.
FPGA Support
IntelliProp’s SATA Core is available for integration into devices offered with SoC capabilities and with capable
transceivers.
6
IPC-SA103A-DT Rev 3.4
7/13
© 2013 IntelliProp, Inc. All rights reserved. IntelliProp and the IntelliProp logo are trademarks of IntelliProp Inc.
Disclaimer: IntelliProp expressly disclaims any liability that might result from the use of this document or the information included herein. IntelliProp reserves the right to
Make changes without notice to any product described herein to improve reliability, function, or design. Information in this document is subject to change without notice.
IPC-SA103A-DT
www.IntelliProp.com
SATA Device App Core
Contact IntelliProp:
105 S. Sunset St., Ste N
Longmont CO 80501
303-774-0535
E-Mail: info@IntelliProp.com
URL: www.IntelliProp.com
7
IPC-SA103A-DT Rev 3.4
7/13
© 2013 IntelliProp, Inc. All rights reserved. IntelliProp and the IntelliProp logo are trademarks of IntelliProp Inc.
Disclaimer: IntelliProp expressly disclaims any liability that might result from the use of this document or the information included herein. IntelliProp reserves the right to
Make changes without notice to any product described herein to improve reliability, function, or design. Information in this document is subject to change without notice.