Preliminary Data Sheet
Specifications in this document are tentative and subject to change.
PS9402
R08DS0014EJ0001
Rev.0.01
May 09, 2011
2.5 A OUTPUT CURRENT, HIGH CMR, IGBT, POWER MOS FET GATE DRIVE, 16-PIN SSOP PHOTOCOUPLER
DESCRIPTION
The PS9402 is an optically coupled isolator containing a GaAlAs LED on the input side and a photo diode, a signal
processing circuit and a power output transistor on the output side on one chip.
The PS9402 is designed specifically for high common mode transient immunity (CMR), high output current and high
switching speed.
The PS9402 includes desaturation detection and active miller clamping functions.
The PS9402 is suitable for driving IGBTs and Power MOS FETs.
The PS9402 is in a 16-pin plastic SSOP (Shrink Small Outline Package). And the PS9402 is able to high-density
(surface) mounting.
FEATURES
•
•
•
•
•
•
•
•
•
•
Long creepage distance (8 mm MIN.)
Large peak output current (2.5 A MAX., 2.0 A MIN.)
High speed switching (tPLH, tPHL = 200 ns MAX.)
UVLO (Under Voltage Lock Out) protection with hysteresis
Desaturation detection
Miller clamping
High common mode transient immunity (CMH, CML = ±25 kV/μs MIN.)
Embossed tape product: PS9402-E3: 850 pcs/reel
Pb-Free product
Safety standards
• UL awaiting approval
• CSA awaiting approval
• DIN EN60747-5-2 (VDE0884 Part2) awaiting approval
PIN CONNECTION
(Top View)
1 VS
VE 16
2 VCC1
VLED 15
3 Fault
Desat 14
4 VS
5 Cathode
VCC2 13
VEE 12
6 Anode
VO 11
7 Anode
Vclamp 10
8 Cathode
VEE 9
APPLICATIONS
• IGBT, Power MOS FET Gate Driver
• Industrial inverter
• Uninterruptible Power Supply (UPS)
R08DS0014EJ0001 Rev.0.01
May 09, 2011
Page 1 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Chapter Title
PACKAGE DIMENSIONS (UNIT: mm)
10.31±0.5
1.27
0.46±0.1
0.25 M
10.36±0.4
0.2±0.15
3.5±0.2
7.49+0.5
–0.1
0.64 MIN.
0.71±0.3
PHOTOCOUPLER CONSTRUCTION
Parameter
Air Distance
Outer Creepage Distance
Isolation Distance
R08DS0014EJ0001 Rev.0.01
May 09, 2011
Unit (MIN.)
8 mm
8 mm
0.4 mm
Page 2 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Chapter Title
BLOCK DIAGRAM(UNIT: mm)
VS
VE
SHIELD
VCC1
VLED
Fault
Desat
VCC2
VS
UVLO
VEE
Cathode
Anode
VO
DESAT
Anode
Vclamp
CLAMP
Cathode
VEE
SHIELD
IF
UVLO (VCC2−VEE)
Don’t care
Don’t care
OFF
ON
Active (<VUVLO-)
Don’t care
Don’t care
Not Active (>VUVLO+)
R08DS0014EJ0001 Rev.0.01
May 09, 2011
DESAT
Don’t care
High (>VDESAT)
Don’t care
Low (<VDESAT)
FAULT
Undefined
Low
Undefined
High
VO
Low
Low
Low
High
Page 3 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Chapter Title
MARKING EXAMPLE
No. 1 pin
Mark
R
9402
NT131
Type Number
Assembly Lot
N T 1 31
Week Assembled
Year Assembled
(Last 1 Digit)
In-house Code
(T: Pb-Free)
Rank Code
ORDERING INFORMATION
Part Number
Order Number
PS9402
PS9402-E3
PS9402-AX
PS9402-E3-AX
PS9402-V
PS9402-V-E3
PS9402-V-AX
PS9402-V-E3-AX
Note:
Solder Plating
Specification
Pb-Free
(Ni/Pd/Au)
Packing Style
10 pcs (Tape 10 pcs cut)
Embossed Tape 850
pcs/reel
10 pcs (Tape 10 pcs cut)
Embossed Tape 850
pcs/reel
Safety Standard
Approval
Standard products
(UL and CSA
awaiting approval)
DIN EN60747-5-2
(VDE0884 Part2)
awaiting approval
(Option)
Application
*1
Part Number
PS9402
*1. For the application of the Safety Standard, following part number should be used.
R08DS0014EJ0001 Rev.0.01
May 09, 2011
Page 4 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Chapter Title
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise specified)
Parameter
Forward Current
Symbol
IF
Peak Transient Forward Current
(Pulse Width < 1 μs)
Reverse Voltage
Input Supply Voltage
Input IC Power Dissipation *1
High Level Peak Output Current *2
Low Level Peak Output Current *2
FAULT Output Current
FAULT Pin Voltage
Total Output Supply Voltage
Negative Output Supply Voltage
Output Voltage
Peak Clamping Sinking Current
Miller Clamping Pin Voltage
DESAT Voltage
Output IC Power Dissipation *3
Isolation Voltage *4
Operating Ambient Temperature
Storage Temperature
IF (TRAN)
Notes: *1.
*2.
*3.
*4.
VR
VCC1
PI
IOH (PEAK)
IOL (PEAK)
IFAULT
VFAULT
(VCC2−VEE)
(VE−VEE)
VO
IClamp
VClamp
VDESAT
PO
BV
TA
Tstg
Ratings
25
1.0
Unit
mA
A
5
0 to 5.5
80
2.5
2.5
8
0 to VCC1
0 to 33
0 to 15
0 to VCC2
1.7
0 to VCC2
VE to VE+10
300
5 000
−40 to +110
−55 to +125
V
V
mW
A
A
mA
V
V
V
V
A
V
V
mW
Vr.m.s.
°C
°C
Reduced to 1.6 mW/°C at TA = 75°C or more.
Maximum pulse width = 10 μs, Maximum duty cycle = 0.5%
Reduced to 5.5 mW/°C at TA = 70°C or more.
AC voltage for 1 minute at TA = 25°C, RH = 60% between input and output.
Pins 1-8 shorted together, 9-16 shorted together.
RECOMMENDED OPERATING CONDITIONS
Parameter
Total Output Supply Voltage
Negative Output Supply Voltage
Positive Output Supply Voltage
Forward Current (ON)
Forward Voltage (OFF)
Operating Ambient Temperature
R08DS0014EJ0001 Rev.0.01
May 09, 2011
Symbol
(VCC2−VEE)
(VE−VEE)
(VCC2−VE)
IF (ON)
VF (OFF)
TA
MIN.
15
0
15
8
−2
−40
MAX.
30
15
30− (VE − VEE)
12
0.8
110
Unit
V
V
V
mA
V
°C
Page 5 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Chapter Title
ELECTRICAL CHARACTERISTICS (DC) (at RECOMMENDED OPERATING CONDITIONS,
VEE = VE = GND, unless otherwise specified)
Parameter
Symbol
FAULT Logic Low Output
Voltage
VFAULTL
FAULT Logic High Output
Current
High Level Output Current
IFAULTH
Low Level Output Current
IOL
Low Level Output Current
During Fault Condition
High Level Output Voltage
IOLF
Low Level Output Voltage
Clamp Pin Threshold Voltage
Clamp Low Level Sinking
Current
High Level Supply Current
Low Level Supply Current
Blanking Capacitor Charging
Current
Blanking Capacitor Discharging
Current
DESAT Threshold
UVLO Threshold *5
UVLO Hysteresis
IOH
VOH
VOL
VtClamp
ICL
ICC2H
ICC2L
Conditions
IFAULT = 1.1 mA
VFAULT = 5.5 V, VCC1 = 5.5 V,
TA = 25°C
VO = (VCC−4 V) *2
VO = (VCC−15 V) *3
VO = (VEE+2.5 V) *2
VO = (VEE+15 V) *3
VO–VEE = 14 V
IO = 100 mA *4
IO = −650 μA *4
IO = 100 mA
VtClamp = VEE + 2.5V
MIN.
0.5
2.0
0.5
2.0
90
TYP.*1
0.1
A
140
ICHG
0.13
IDSCHG
VDESAT = 7 V
10
30
VDESAT
VUVLO+
VUVLO−
VCC1−VE > VUVLO−, VO < 5V
VO > 5 V
VO < 5 V
6.0
11.0
9.8
6.9
12.3
11.0
0.4
1.3
IO = 0 mA, VO > 5 V
Threshold Input Voltage
(H → L)
Input Forward Voltage
Input Reverse Current
Input Capacitance
VFHL
IO = 0 mA, VO < 5 V
0.8
VF
IR
CIN
IF = 10 mA, TA = 25°C
VR = 3V, TA = 25°C
f = 1 MHz, VF = 0 V
1.2
μA
1.5
2
2
0.24
IFLH
0.5
A
VCC − 2.0 VCC − 1.3
VCC − 1.5 VCC − 0.8
0.15
2.0
0.35
1.5
Threshold Input Current
(L → H)
Unit
V
1.5
IO = 0 mA
IO = 0 mA
VDESAT = 2 V
VUVLO+−
VUVLO−
MAX.
1.5
230
mA
V
0.5
V
V
A
3
3
0.33
mA
mA
mA
mA
7.5
13.5
12.3
V
V
V
5
mA
V
1.56
30
1.8
10
V
μA
pF
Notes: *1. Typical values at TA = 25°C.
*2. Maximum pulse width = 50 μs, Maximum duty cycle = 0.2%
*3. Maximum pulse width = 10 μs, Maximum duty cycle = 0.5%
*4. VOH is measured with the DC load current in this testing (Maximum pulse width = 1 ms, Maximum duty cycle =
20%).
*5. For High Level Output Voltage testing, VOH is measured with the DC load current. When driving capacitive
loads, VOH will approach VCC as IOH approaches zero units.
R08DS0014EJ0001 Rev.0.01
May 09, 2011
Page 6 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Chapter Title
SWITCHING CHARACTERISTICS (AC) (at RECOMMENDED OPERATING
CONDITIONS, VEE = VE = GND, unless otherwise specified)
Parameter
Symbol
Propagation Delay Time (L → H)
tPLH
Propagation Delay Time (H → L)
tPHL
Pulse Width Distortion (PWD)
|tPHL−tPLH|
Rise Time
tr
Fall Time
tf
CMH1
Common Mode Transient
*3
Immunity at High Level Output
Conditions
Rg = 10 Ω, Cg = 10 nF,
f = 10 kHz,
Duty Cycle = 50%*2,
IF = 10 mA,
VCC2 = 30 V
TA = 25°C, IF = 10 mA,
VCC2 = 30 V, VCM = 1.5 kV,
CDESAT = 100 pF,
RF = 2.1 kΩ, VCC1 = 5 V
Common Mode Transient
*4
Immunity at Low Level Output
CML1
TA = 25°C, VF = 0 V,
VCC2 = 30 V,
VCM = 1.5 kV, RF = 2.1 kΩ,
VCC1 = 5 V
DESAT Sense to 90% VO
*5
Delay
DESAT Sense to 10% VO Delay
tDESAT
CDESAT = 100 pF,
RF = 2.1 kΩ,
(90%)
tDESAT
(10%)
DESAT Sense to Low Level
*6
FAULT Signal Delay
DESAT Sense to DESAT Low
*5
Propagation Delay
DESAT Input Mute*7
MIN.
50
50
TYP.*1
100
100
20
50
50
MAX.
200
200
100
Unit
ns
ns
ns
ns
ns
kV/μs
−25
kV/μs
250
500
ns
2
3
μs
400
800
ns
25
Rg = 10 Ω, Cg = 10 nF
VCC2 = 30 V
tDESAT
(FAULT)
250
tDESAT
ns
(LOW)
μs
5
tDESAT
(MUTE)
RESET to High Level FAULT
Signal Delay
tRESET
(FAULT)
VCC1 = 5.5 V
VCC1 = 3.3 V
0.3
0.5
1.2
1.5
3.0
4.0
μs
μs
Notes: *1. Typical values at TA = 25°C.
*2. This load condition is equivalent to the IGBT load at 1 200 V/150 A.
*3. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode
pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF
and a 2.1kΩ pull-up resistor is needed in fault detection mode.
*4. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode
pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V).
*5. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the
FAULT output to go low. This is supply voltage dependent.
*6. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
*7. Auto Reset: This is the amount of time when VOUT will be asserted low after DESAT threshold is exceeded.
See the Description of Operation (Auto Reset) topic in the application information section.
R08DS0014EJ0001 Rev.0.01
May 09, 2011
Page 7 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Chapter Title
TEST CIRCUIT
Fig. 1 VFAULTL Test Circuit
1 VS
VFAULTL
Fig. 2 IFAULTH Test Circuit
1 VS
VE 16
2 VCC1
VLED 15
3 Fault
Desat 14
VE 16
2 VCC1
VLED 15
3 Fault
Desat 14
IFAULTH
4 VS
5 Cathode
VEE
4 VS
5 Cathode
12
VCC2 13
VEE 12
6 Anode
VO 11
6 Anode
VO 11
7 Anode
Vclamp 10
7 Anode
Vclamp 10
8 Cathode
VEE 9
8 Cathode
VEE 9
Fig. 3 IOH Test Circuit
Fig. 4 IOL Test Circuit
1 VS
1 VS
VE 16
VE 16
2 VCC1
VLED 15
2 VCC1
VLED 15
3 Fault
Desat 14
3 Fault
Desat 14
4 VS
5 Cathode
IF
VCC2 13
VCC2 13
VEE 12
6 Anode
VO
7 Anode
Vclamp 10
8 Cathode
4 VS
5 Cathode
IOH
VCC
11
VEE 9
1 VS
VEE 12
6 Anode
VO 11
7 Anode
Vclamp 10
8 Cathode
Fig. 5 VOH Test Circuit
VCC2 13
Fig. 6 VOL Test Circuit
1 VS
VE 16
VE 16
VLED 15
2 VCC1
VLED 15
3 Fault
Desat 14
3 Fault
Desat 14
5 Cathode
VCC2 13
4 VS
VEE 12
5 Cathode
VCC2 13
VEE 12
VOH
IF
6 Anode
VO 11
7 Anode
Vclamp 10
8 Cathode
R08DS0014EJ0001 Rev.0.01
May 09, 2011
VEE 9
VCC
VEE 9
2 VCC1
4 VS
IOL
VOL
VCC
6 Anode
VO 11
7 Anode
Vclamp 10
8 Cathode
VCC
VEE 9
Page 8 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Chapter Title
TEST CIRCUIT 2
Fig. 8 ICC2L Test Circuit
Fig. 7 ICC2H Test Circuit
1 VS
VE 16
2 VCC1
VLED 15
3 Fault
Desat 14
1 VS
VE 16
2 VCC1
VLED 15
3 Fault
Desat 14
ICC2H
4 VS
5 Cathode
IF
4 VS
VEE 12
6 Anode
VO 11
7 Anode
Vclamp 10
8 Cathode
ICC2L
VCC2 13
5 Cathode
VCC
VEE 9
1 VS
2 VCC1
3 Fault
4 VS
5 Cathode
IF
Desat 14
VO 11
7 Anode
Vclamp 10
8 Cathode
ICHG
VEE 9
VE 16
VLED 15
3 Fault
Desat 14
VCC2 13
VO 11
7 Anode
Vclamp 10
8 Cathode
1 VS
VE 16
VE 16
VLED 15
3 Fault
Desat 14
3 Fault
Desat 14
7 Anode
8 Cathode
R08DS0014EJ0001 Rev.0.01
May 09, 2011
4 VS
VCC2 13
5 Cathode
VEE 12
VO 11
Vclamp 10
VEE 9
VCC
Fig. 12 VDESAT Test Circuit
2 VCC1
6 Anode
IDSCHG
VEE 9
VLED 15
5 Cathode
7V
VEE 12
6 Anode
2 VCC1
4 VS
VCC
VEE 9
2 VCC1
5 Cathode
VCC
Fig. 11 ICL Test Circuit
1 VS
Vclamp 10
4 VS
VEE 12
6 Anode
7 Anode
1 VS
2V
15
VCC2 13
VO 11
Fig. 10 IDSCHG Test Circuit
VE 16
VLED
VEE 12
6 Anode
8 Cathode
Fig. 9 ICHG Test Circuit
VCC2 13
ICL
2.5 V
VCC
IF
VCC2 13
VEE 12
6 Anode
VO 11
7 Anode
Vclamp 10
8 Cathode
VDESAT
VCC
VEE 9
Page 9 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Chapter Title
TEST CIRCUIT 3
Fig. 14 IFLH Test Circuit
Fig. 13 VUVLO Test Circuit
1 VS
VE 16
1 VS
2 VCC1
VLED 15
2 VCC1
VLED 15
3 Fault
Desat 14
3 Fault
Desat 14
4 VS
5 Cathode
VCC2 13
4 VS
VEE 12
6 Anode
7 Anode
8 Cathode
VO 11
IF
Vclamp 10
VEE 9
VLED 15
3 Fault
Desat 14
5 Cathode
IF
6 Anode
VO 11
7 Anode
Vclamp 10
VCC
VEE 9
Fig. 17 tPLH/tPHL Test Wave Forms
VE 16
2 VCC1
4 VS
VEE 12
8 Cathode
Fig. 15 tPLH/tPHL Test Circuit
1 VS
VCC2 13
5 Cathode
VCC
IF
VE 16
IF
tr
tf
90%
50%
10%
VCC2 13
VOUT
VEE 12
6 Anode
VO 11
7 Anode
Vclamp 10
tPLH
10 Ω
tPHL
VCC
10 nF
8 Cathode
VEE 9
Fig. 17 tDESAT Test Circuit
1 VS
2.1 kΩ
VLED 15
3 Fault
Desat 14
5 Cathode
IF
IF
VE 16
2 VCC1
4 VS
Fig. 18 tDESAT Test Wave Forms
100 pF
7 Anode
Vclamp 10
R08DS0014EJ0001 Rev.0.01
May 09, 2011
90%
VOUT
10%
tDESET (90%)
10 Ω
10 nF
VEE 9
50%
tDESET (10%)
VEE 12
VO 11
8 Cathode
VDESET
VCC2 13
6 Anode
tDESET (LOW)
VCC
FAULT
tDESET (FAULT)
50%
tDESET (MUTE)
50%
tRESET (FAULT)
Page 10 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Chapter Title
TEST CIRCUIT 4
Fig. 20 CML Test Circuit (LED1 OFF)
Fig. 19 CMH Test Circuit (LED1 ON)
1 VS
VE 16
1 VS
VE 16
2 VCC1
VLED 15
2 VCC1
VLED 15
3 Fault
Desat 14
3 Fault
Desat 14
VCC2 13
4 VS
5 Cathode
6 Anode
VO 11
7 Anode
Vclamp 10
VCC2 13
4 VS
VEE 12
SCOPE
5 Cathode
VCC
10 Ω
VEE 12
6 Anode
VO 11
7 Anode
Vclamp 10
10 nF
1 VS
−
+
Fig. 22 CML Test Circuit (LED2 OFF)
Fig. 21 CMH Test Circuit (LED2 ON)
2.1 kΩ
VE 16
2.1 kΩ
1 VS
VE 16
2 VCC1
VLED 15
2 VCC1
VLED 15
3 Fault
Desat 14
3 Fault
Desat 14
SCOPE
SCOPE
5 Cathode
VCC2 13
4 VS
VCC2 13
4 VS
10 Ω
VEE 9
8 Cathode
−
+
5 Cathode
VEE 12
VEE 12
VCC
VCC
6 Anode
VO 11
7 Anode
Vclamp 10
10 Ω
7 Anode
Vclamp 10
90%
VCM
VO
(CMH: IF = 10 mA)
VO
(CML: IF = 0 mA)
R08DS0014EJ0001 Rev.0.01
May 09, 2011
+
Fig. 24 CMH, CML Test Wave Forms
(LED2 ON, OFF)
1 500 V
90%
VCM
10%
tr
10 Ω
VEE 9
−
+
Fig. 23 CMH, CML Test Wave Forms
(LED1 ON, OFF)
0V
VO 11
8 Cathode
VEE 9
−
6 Anode
10 nF
10 nF
8 Cathode
VCC
10 nF
VEE 9
8 Cathode
SCOPE
0V
tf
VOH
15 V
1V
VOL
VFAULT
(CMH: IF = 10 mA, DESAT)
VFAULT
(CML: IF = 0 mA, DESAT)
1 500 V
10%
tr
tf
GND
2V
OPEN
VOL
Page 11 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Chapter Title
TAPING SPECIFICATIONS (UNIT: mm)
1.75±0.1
Outline and Dimensions (Tape)
2.0±0.1
4.0±0.1
φ 1.5+0.1
–0
4.5±0.1
φ 3.5
10.8±0.1
24±0.3
11.5±0.1
3.8±0.1
0.35
φ 1.55±0.1
16±0.1
10.9±0.1
Tape Direction
PS9402-E3
Outline and Dimensions (Reel)
2.0±0.5
φ 21.0±0.8
φ 100±1.0
R 1.0
φ 330±2.0
2.0±0.5
φ13.0±0.2
25.5±1.0
29.5±1.0
Packing: 850 pcs/reel
R08DS0014EJ0001 Rev.0.01
May 09, 2011
23.9 to 27.4
Outer edge of
flange
Page 12 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Chapter Title
NOTES ON HANDLING
1. Recommended soldering conditions
(1) Infrared reflow soldering
• Peak reflow temperature
• Time of peak reflow temperature
• Time of temperature higher than 220°C
• Time to preheat temperature from 120 to 180°C
• Number of reflows
• Flux
260°C or below (package surface temperature)
10 seconds or less
60 seconds or less
120±30 s
Three
Rosin flux containing small amount of chlorine (The flux
with a maximum chlorine content of 0.2 Wt% is
recommended.)
Package Surface Temperature T (°C)
Recommended Temperature Profile of Infrared Reflow
(heating)
to 10 s
260°C MAX.
220°C
to 60 s
180°C
120°C
120±30 s
(preheating)
Time (s)
(2) Wave soldering
• Temperature
• Time
• Preheating conditions
• Number of times
• Flux
260°C or below (molten solder temperature)
10 seconds or less
120°C or below (package surface temperature)
One (Allowed to be dipped in solder including plastic mold portion.)
Rosin flux containing small amount of chlorine (The flux with a maximum chlorine
content of 0.2 Wt% is recommended.)
(3) Soldering by Soldering Iron
• Peak Temperature (lead part temperature) 350°C or below
• Time (each pins)
3 seconds or less
• Flux
Rosin flux containing small amount of chlorine (The flux with a
maximum chlorine content of 0.2 Wt% is recommended.)
(a) Soldering of leads should be made at the point 1.5 to 2.0 mm from the root of the lead
(4) Cautions
• Fluxes
Avoid removing the residual flux with freon-based and chlorine-based cleaning solvent.
R08DS0014EJ0001 Rev.0.01
May 09, 2011
Page 13 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Chapter Title
2. Cautions regarding noise
Be aware that when voltage is applied suddenly between the photocoupler’s input and output at startup, the output
transistor may enter the on state, even if the voltage is within the absolute maximum ratings.
USAGE CAUTIONS
1. This product is weak for static electricity by designed with high-speed integrated circuit so protect against static
electricity when handling.
2. Board designing
(1) By-pass capacitor of more than 0.1 μF is used between VCC and GND near device. Also, ensure that the distance
between the leads of the photocoupler and capacitor is no more than 10 mm.
(2) In older to avoid malfunctions and characteristics degradation, IGBT collector or emitter traces should not be
closed to the LED input.
3. Make sure the rise/fall time of the forward current is 0.5 μs or less.
4. In order to avoid malfunctions, make sure the rise/fall slope of the supply voltage is 3 V/μs or less.
5. Avoid storage at a high temperature and high humidity.
R08DS0014EJ0001 Rev.0.01
May 09, 2011
Page 14 of 15
Preliminary document
Specifications in this document are tentative and subject to change.
PS9402
Caution
Chapter Title
GaAs Products
This product uses gallium arsenide (GaAs).
GaAs vapor and powder are hazardous to human health if inhaled or ingested, so please observe
the following points.
• Follow related laws and ordinances when disposing of the product. If there are no applicable laws
and/or ordinances, dispose of the product as recommended below.
1. Commission a disposal company able to (with a license to) collect, transport and dispose of
materials that contain arsenic and other such industrial waste materials.
2. Exclude the product from general industrial waste and household garbage, and ensure that the
product is controlled (as industrial waste subject to special control) up until final disposal.
• Do not burn, destroy, cut, crush, or chemically dissolve the product.
• Do not lick the product or in any way allow it to enter the mouth.
R08DS0014EJ0001 Rev.0.01
May 09, 2011
Page 15 of 15
Revision History
PS9402 Preliminary Data Sheet
Rev.
Date
Page
0.01
May 09, 2011
−
Description
Summary
First edition issued
All trademarks and registered trademarks are the property of their respective owners.
C-1
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