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Cyclone V GX FPGA Development Board Reference
Manual
Cyclone V GX FPGA Development Board
Reference Manual
101 Innovation Drive
San Jose, CA 95134 www.altera.com
MNL-01072-1.2
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© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html
. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
Contents
Chapter 1. Overview
Chapter 2. Board Components
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
iv ContentsContents
Chapter 3. Board Components Reference
Additional Information
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
1. Overview
This document describes the hardware features of the Cyclone
®
V GX FPGA development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.
General Description
The Cyclone V GX FPGA development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Cyclone V GX FPGA device. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Cyclone V GX designs.
One high-speed mezzanine card (HSMC) connectors are available to add additional functionality via a variety of HSMCs available from Altera
®
and various partners.
f
To see a list of the latest HSMCs available or to download a copy of the HSMC specification, refer to the Development Board Daughtercards page of the Altera website.
Design advancements and innovations, such as the PCI Express hard IP, partial reconfiguration, and hard memory controller implementation ensure that designs implemented in the Cyclone V GXs operate faster, with lower power, and have a faster time to market than previous FPGA families.
f
For more information on the following topics, refer to the respective documents:
■
■
■
Cyclone V device family, refer to the
Cyclone V Device Handbook
.
PCI Express MegaCore function, refer to the
PCI Express Compiler User Guide
.
HSMC Specification, refer to the
High Speed Mezzanine Card (HSMC) Specification
.
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
1–2 Chapter 1: Overview
Board Component Blocks
Board Component Blocks
The development board features the following major component blocks:
■ One Cyclone V GX FPGA (5CGXFC7D6F31C7NES) in a 896-pin FineLine BGA
(FBGA) package
■
■
150,000 LEs
136,880 adaptive logic modules (ALMs)
■
■
■
■
■
7,024 Kbit (Kb) on-die block memory
Nine 3.125-Gbps high-speed transceivers
Seven fractional phase locked loops (PLLs)
■
■
312 18x18-bit multipliers
480 general purpose input/output (GPIO)
■
1.1-V core voltage
FPGA configuration circuitry
■
MAX
®
V CPLD (5M2210ZF256C4N) in a 256-pin FBGA package as the System
Controller
■
■
Flash fast passive parallel (FPP) configuration
MAX II CPLD (EPM240M100C4N) in a 100-pin FBGA package as part of the embedded USB-Blaster
TM
II for use with the Quartus
®
II Programmer
Clocking circuitry
■
■
Programmable clock generator for the FPGA reference clock input
125-MHz LVDS oscillator for the FPGA reference clock input
■
■
■
■
148.5/148.35-MHz LVDS VCXO for the FPGA reference clock input
50-MHz single-ended oscillator for the FPGA and MAX V CPLD clock input
100-MHz single-ended oscillator for the MAX V CPLD configuration clock input
■
SMA input (LVPECL)
Memory
■
DDR3 SDRAM
■
Four 128-Mbyte (MB) device with a 16-bit data bus
■
■
■
Two 128-MB device with a 8-bit data bus
One 18-MB SSRAM
One 512-MB synchronous flash
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 1: Overview
Board Component Blocks
■
■
■
General user input/output
■
LEDs and displays
■
■
■
■
Four user LEDs
One configuration load LED
One configuration done LED
One error LED
■
■
■
■
Four embedded USB-Blaster II status LEDs
Two HSMC interface link LEDs
Three PCI Express link width LEDs
Five Ethernet LEDs
■
■
■
■
One serial digital interface (SDI) carrier detect LED
One power on LED
■
One two-line character LCD display
Push buttons
■
■
■
One CPU reset push button
One MAX V reset push button
One program select push button
One program configuration push button
■
■
Three general user push buttons
DIP switches
■
■
Board settings DIP switch
JTAG chain control DIP switch
■
■
PCI Express link width DIP switch
General user DIP switch
Power supply
■
14–20-V (laptop) DC input
■
PCI Express edge connector
Mechanical
■
PCI Express card standard size (6.600" x 4.199")
1–3
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
1–4 Chapter 1: Overview
Development Board Block Diagram
Development Board Block Diagram
Figure 1–1 shows a block diagram of the Cyclone V GX FPGA development board.
Figure 1–1. Cyclone V GX FPGA Development Board Block Diagram
LVDS/Single-Ended
128-MB
DDR3
Type-B
USB 2.0
Embedded
USB-Blaster II
REFCLK SMA In
XCVR x1
Trigger SMA Out x1
Gigabit Ethernet
PHY
SDI TX/RX
XCVR x1
Debug Header
JTAG Chain
5CGXFC7D7F31C7NES x32 x11 x3 x4 x4
128-MB
DDR3
2x16 LCD
Push Buttons
DIP Switches
LEDs
Programmable
Oscillator x4 Edge
5M2210ZF256C4N
18-MB
SSRAM
512-MB
Flash
Handling the Board
When handling the board, it is important to observe the following static discharge precaution: c
Without proper anti-static handling, the board can be damaged. Therefore, use anti-static handling precautions when touching the board.
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
2. Board Components
This chapter introduces the major components on the Cyclone V GX FPGA development board.
illustrates the component locations and
provides a brief description of all component features of the board.
1
A complete set of schematics, a physical layout database, and GERBER files for the development board reside in the Cyclone V GX FPGA development kit documents directory. f
For information about powering up the board and installing the demonstration software, refer to the
Cyclone V GX FPGA Development Kit User Guide
.
■
■
■
■
■
■
■
■
■
■
This chapter consists of the following sections:
“Featured Device: Cyclone V GX FPGA” on page 2–5
“MAX V CPLD 5M2210 System Controller” on page 2–6
“FPGA Configuration” on page 2–10
“Clock Circuitry” on page 2–18
“General User Input/Output” on page 2–20
“Components and Interfaces” on page 2–24
“Statement of China-RoHS Compliance” on page 2–48
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
Program Config,
Program Select
Push Buttons
(S6, S7)
Transceiver SMA
Connectors
RX (J2, J6)
TX (J3, J7)
SDI Video
Port (J5, J10)
Gigabit Ethernet
Port (J11)
MAX V CPLD
EPM2210 System
Controller (U12)
USB Type-B
Connector (J12)
Debug Header
(J14)
Flash x16
Memory (U18)
Board Settings
DIP switch (SW3)
2–2 Chapter 2: Board Components
Board Overview
Board Overview
This section provides an overview of the Cyclone V GX FPGA development board, including an annotated board image and component descriptions.
an overview of the board features.
Figure 2–1. Overview of the Cyclone V GX FPGA Development Board Features
Max V Reset
Push Button (S1)
CPU Reset
Push Button (S2)
HSMC Port
(J1)
Program Select
LEDs (D12-D14)
Configuration Done,
Load, and Error
LEDs (D15-D17)
Clock Output
SMA Connector
(J4)
General User
Push Buttons
(S3-S5)
User LEDs
(D4-D7)
Fan Power
Header (J8)
Power
Switch
(SW1)
DC Input
Jack (J9)
Character
LCD (J18)
JTAG Chain
Header
(J13)
Cyclone V GX
FPGA (U11)
PCI Express Edge
Connector (J19)
PCI Express
Mode
DIP Switch (SW4)
JTAG Chain
Control
DIP Switch (SW5)
Clock Input SMA
Connector
(J16, J17)
DDR3A x32
+ ECC Memory
(U21, U22, U23)
DDR3B x32
+ ECC Memory
(U6, U15, U19)
Table 2–1 describes the components and lists their corresponding board references.
Table 2–1. Board Components (Part 1 of 3)
Board Reference Type Description
Featured Devices
U11
U12
FPGA
CPLD
Cyclone V GX, 5CGXFC7D6F31C7NES, 896-pin FBGA.
MAX V CPLD, 5M2210ZF256C4N, 256-pin FBGA.
Configuration, Status, and Setup Elements
J13
SW5
J12
JTAG chain header
Provides access to the JTAG chain and disables the embedded
USB-Blaster II when using an external USB-Blaster cable.
JTAG chain control DIP switch Remove or include devices in the active JTAG chain.
USB type-B connector
USB interface for FPGA programming and debugging through the embedded USB-Blaster II JTAG via a type-B USB cable.
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Board Overview
2–3
Table 2–1. Board Components (Part 2 of 3)
Board Reference
SW3
SW4
S7
S6
D15
D17
D16
D23
D12, D13, D14
D19, D20, D21,
D22, D24
D1, D2
D3
D8, D9, D10
Type
Board settings DIP switch
PCI Express DIP switch
Program select push button
Program configuration push button
Configuration done LED
Load LED
Error LED
Power LED
Program select LEDs
Ethernet LEDs
HSMC port LEDs
HSMC port present LED
PCI Express link LEDs
Description
Controls the MAX V CPLD 5M2210 System Controller functions such as clock enable, SMA clock input control, and which image to load from flash memory at power-up.
Controls the PCI Express lane width by connecting the prsnt pins together on the PCI Express edge connector.
Toggles the program select LEDs, which selects the program image that loads from flash memory to the FPGA.
Load image from flash memory to the FGPA based on the settings of the program select LEDs.
Illuminates when the FPGA is configured.
Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA.
Illuminates when the FPGA configuration from flash memory fails.
Illuminates when 5.0-V power is present.
Illuminates to show the LED sequence that determines which flash memory image loads to the FPGA when you press the program select push button. Refer to Table 2–6 for the LED settings.
Illuminates to show the connection speed as well as transmit or receive activity.
You can configure these LEDs to indicate transmit or receive activity.
Illuminates when a daughtercard is plugged into the HSMC port A.
You can configure these LEDs to indicate the PCI Express link width
(x1, x4) and Gen1 link.
Clock Circuitry
U25
X2
X4
X1
J2, J3, J6, J7
J16, J17
J4
Quad-output oscillator
148.5-MHz oscillator
50-MHz oscillator
100-MHz oscillator
Programmable oscillator with default frequencies of 125 MHz,
409.6 MHz, 156.25 MHz, and 100 MHz. The frequency is programmable using the clock control GUI running on the MAX V
CPLD 5M2210 System Controller.
148.500-MHz voltage controlled crystal oscillator for the serial digital interface (SDI) video. This oscillator is programmable to any frequency between 20–810 MHz using the clock control GUI running on the
MAX V CPLD 5M2210 System Controller.
50.000-MHz crystal oscillator for general purpose logic.
100.000-MHz crystal oscillator for the MAX V CPLD 5M2210 System
Controller.
Transceiver SMA connectors Drives serial data input/output to or from the SDI video port.
Clock input SMA connectors
Drive LVPECL-compatible clock inputs into the clock multiplexer buffer.
Clock output SMA connector Drive out 2.5-V CMOS clock output from the FPGA.
General User Input/Output
D4–D7
SW2
S2
User LEDs
User DIP switch
CPU reset push button
Four user LEDs. Illuminates when driven low.
Quad user DIP switches. When the switch is ON, a logic 0 is selected.
Reset the FPGA logic.
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–4 Chapter 2: Board Components
Board Overview
Table 2–1. Board Components (Part 3 of 3)
Board Reference
S1
S3, S4, S5
Type
MAX V reset push button
General user push buttons
Memory Devices
U6, U15, U21,
U22, U19, U23
DDR3 x32 memory
U37
J1
J11
SSRAM x16 memory
U18 Flash x16 memory
Communication Ports
J19 PCI Express edge connector
HSMC port
Gigabit Ethernet port
Description
Reset the MAX V CPLD 5M2210 System Controller.
Three user push buttons. Driven low when pressed.
Four 128-MB DDR3 SDRAM with a 16-bit data bus and two 128-MB
DDR3 SDRAM with a 8-bit data bus.
18-MB standard synchronous RAM with a 12-bit data bus and 4-bit parity.
512-MB synchronous flash devices with a 16-bit data bus for non-volatile memory.
Gold-plated edge fingers connector for up to ×8 signaling in Gen1 mode.
Provides eight transceiver channels and 84 CMOS or 17 LVDS channels per the HSMC specification.
RJ-45 connector which provides a 10/100/1000 Ethernet connection via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed
Ethernet MegaCore function in RGMII mode.
Video and Display Ports
J18 Character LCD
J5, J10 SDI video port
Connector that interfaces to a provided 16 character × 2 line LCD module along with two standoffs.
Two 75-
Ω sub-miniature version B (SMB) connectors that provide a full-duplex SDI interface through a LMH0303 cable driver and
LMH0384 cable equalizer.
Power Supply
J19
J9
SW1
PCI Express edge connector
DC input jack
Power switch
Interfaces to a PCI Express root port such as an appropriate PC motherboard.
Accepts a 14–20-V DC power supply. Do not use this input jack while the board is plugged into a PCI Express slot.
Switch to power on or off the board when power is supplied from the
DC input jack.
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Featured Device: Cyclone V GX FPGA
2–5
Featured Device: Cyclone V GX FPGA
The Cyclone V GX FPGA development board features a Cyclone V GX
5CGXFC7D6F31C7NES device (U11) in a 896-pin FBGA package.
f
For more information about Cyclone V device family, refer to the
Cyclone V Device
Handbook
.
Table 2–2 describes the features of the Cyclone V GX 5CGXFC7D6F31C7NES device.
Table 2–2. Cyclone V GX FPGA Features
ALMs
136,880
Equivalent
LEs
150,000
M10K RAM
Blocks
1,726
Total RAM
(Kbits)
7,024
18-bit × 18-bit
Multipliers
312
PLLs
7
Transceivers
9
Package Type
896-pin FBGA
I/O Resources
The Cyclone V GX 5CGXFC7D6F31C7NES device has total of 480 user I/Os and nine transceiver channels.
lists the Cyclone V GX device I/O pin count and usage by function on the board.
Table 2–3. Cyclone V GX Device I/O Pin Count
Function
DDR3A
DDR3B
Flash, SSRAM, and MAX V FSM bus
PCI Express x4 port
HSMA port
Gigabit Ethernet port
Embedded USB-Blaster II
SDI video port
Push buttons
DIP switches
Character LCD
LEDs
Clock or Oscillators
Total I/O Used:
I/O Standard
1.5-V SSTL
1.5-V SSTL
2.5-V CMOS
2.5-V CMOS + XCVR
2.5-V CMOS + LVDS + XCVR
2.5-V CMOS + LVDS
2.5-V CMOS
2.5-V CMOS + XCVR
2.5-V CMOS
2.5-V CMOS
2.5-V CMOS
2.5-V CMOS
2.5-V CMOS + LVDS + PCML
I/O Count
6
4
4
11
7
18
423
13
93
6
19
81
81
80
Special Pins
One differential x4 DQS pin
One differential x4 DQS pin
—
One reference clock
Four transceivers, 17 LVDS, I
2
C
—
—
One reference clock
One DEV_CLRn pin
—
—
—
Nine reference clock
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–6 Chapter 2: Board Components
MAX V CPLD 5M2210 System Controller
MAX V CPLD 5M2210 System Controller
■
■
The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the following purposes:
■
FPGA configuration from flash
Power measurement
Control and status registers for remote system update
Figure 2–2 illustrates the MAX V CPLD 5M2210 System Controller's functionality and
external circuit connections as a block diagram.
Figure 2–2. MAX V CPLD 5M2210 System Controller Block Diagram
MAX V CPLD System Controller
PC
FSM Bus
Embedded
USB-Blaster II
JTAG Control
SLD-HUB
Information
Register
Control
Register
FPGA
Flash
SSRAM
Encoder
Virtual-JTAG
Decoder
PFL
Power
Measurement
Results
LTC2418
Controller
Si571
Controller
Si5538
Controller
GPIO
Si571
Programmable
Oscillator
Si5338
Programmable
Oscillator
Table 2–4 lists the I/O signals present on the MAX V CPLD 5M2210 System
Controller. The signal names and functions are relative to the MAX V device.
Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 1 of 5)
Board
Reference (U12)
N4
J12
L5
K4
R7
E13
J5
N14
N15
M16
Schematic Signal Name
5M2210_JTAG_TMS
CLK50_EN
CLK_CONFIG
CLK_ENABLE
CLK_SEL
CLKIN_50_MAXV
CLOCK_SCL
CLOCK_SDA
CPU_RESETN
EXTRA_SIG0
I/O Standard
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
Description
MAX V JTAG TMS
50 MHz oscillator enable
100 MHz configuration clock input
DIP switch for clock oscillator enable
DIP switch for clock select—SMA or oscillator
50 MHz clock input
Programmable oscillator I
2
C clock
Programmable oscillator I
2
C data
FPGA reset push button
Embedded USB-Blaster II interface. Reserved for future use
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
MAX V CPLD 5M2210 System Controller
Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 2 of 5)
Board
Reference (U12)
P9
M8
P15
Schematic Signal Name
EXTRA_SIG1
EXTRA_SIG2
FACTORY_LOAD
I/O Standard
2.5-V
2.5-V
2.5-V
R14
P4
L14
P5
J14
E14
J13
F15
M13
H14
D15
G16
F16
D16
F14
E15
G13
M15
D13
F13
G15
H15
C15
E16
R6
R5
H13
H16
N12
E12
T5
P7
M6
N6
N7
FACTORY_REQUEST
FACTORY_STATUS
FAN_FORCE_ON
FLASH_ADVN
FLASH_CEN
FLASH_CLK
FLASH_OEN
FLASH_RDYBSYN
FLASH_RESETN
FLASH_WEN
FPGA_CONF_DONE
FPGA_CONFIG_D0
FPGA_CONFIG_D1
FPGA_CONFIG_D2
FPGA_CONFIG_D3
FPGA_CONFIG_D4
FPGA_CONFIG_D5
FPGA_CONFIG_D6
FPGA_CONFIG_D7
FPGA_CONFIG_D8
FPGA_CONFIG_D9
FPGA_CONFIG_D10
FPGA_CONFIG_D11
FPGA_CONFIG_D12
FPGA_CONFIG_D13
FPGA_CONFIG_D14
FPGA_CONFIG_D15
FPGA_CVP_CONFDONE
FPGA_DCLK
FPGA_NCONFIG
FPGA_NSTATUS
FPGA_PR_DONE
FPGA_PR_ERROR
FPGA_PR_READY
FPGA_PR_REQUEST
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
Description
Embedded USB-Blaster II interface. Reserved for future use
Embedded USB-Blaster II interface. Reserved for future use
DIP switch to load factory or user design at power-up
Embedded USB-Blaster II request to send FACTORY command
Embedded USB-Blaster II FACTORY command status
DIP switch to on or off the fan
FSM bus flash memory address valid
FSM bus flash memory chip enable
FSM bus flash memory clock
FSM bus flash memory output enable
FSM bus flash memory ready
FSM bus flash memory reset
FSM bus flash memory write enable
FPGA configuration done LED
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration via protocol done LED
FPGA configuration clock
FPGA configuration active
FPGA configuration ready
FPGA partial reconfiguration done
FPGA partial reconfiguration error
FPGA partial reconfiguration ready
FPGA partial reconfiguration request
2–7
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–8 Chapter 2: Board Components
MAX V CPLD 5M2210 System Controller
Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 3 of 5)
Board
Reference (U12)
T2
K1
L1
K3
C2
H2
H3
R3
C3
G4
F4
E3
J3
G1
F3
D3
K2
M2
L2
M3
M1
N1
N3
F2
G3
G2
J2
E2
E4
H4
F1
E5
D1
D2
E1
J4
G5
F5
F6
Schematic Signal Name
FSM_A0
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
FSM_A26
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
I/O Standard
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM data bus
FSM data bus
FSM data bus
FSM data bus
FSM data bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM address bus
FSM data bus
FSM data bus
FSM data bus
FSM data bus
FSM data bus
FSM data bus
FSM data bus
Description
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
MAX V CPLD 5M2210 System Controller
2–9
Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 4 of 5)
Board
Reference (U12)
L15
L6
M5
P3
N2
L3
R1
P2
Schematic Signal Name
FSM_D12
FSM_D13
FSM_D14
FSM_D15
HSMA_PRSNTN
JTAG_5M2210_TDI
JTAG_5M2210_TDO
JTAG_TCK
I/O Standard
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
P11
P12
M4
K13
L11
L4
N13
J15
M7
L12
K14
N5
P6
F11
F12
K12
M14
L13
P14
D14
M9
P8
B12
C12
A10
B10
A9
C11
C10
M570_CLOCK
M570_PCIE_JTAG_EN
MAX5_BEN0
MAX5_BEN1
MAX5_BEN2
MAX5_BEN3
MAX5_CLK
MAX5_CSN
MAX5_OEN
MAX5_WEN
MAX_CONF_DONEN
MAX_ERROR
MAX_LOAD
MAX_RESETN
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
OVERTEMP
PCIE_JTAG_EN
PGM_CONFIG
PGM_LED0
PGM_LED1
PGM_LED2
PGM_SEL
SDI_FAULT
SDI_RX_BYPASS
SDI_RX_EN
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
Description
FSM data bus
FSM data bus
FSM data bus
FSM data bus
HSMC port A present
MAX V CPLD JTAG chain data in
MAX V CPLD JTAG chain data out
JTAG chain clock
25-MHz clock to embedded USB-Blaster II for sending
FACTORY command
Low signal to disable the embedded USB-Blaster II when PCI
Express is the master to the JTAG chain
FSM bus MAX V byte enable 0
FSM bus MAX V byte enable 1
FSM bus MAX V byte enable 2
FSM bus MAX V byte enable 3
FSM bus MAX V clock
FSM bus MAX V chip select
FSM bus MAX V output enable
FSM bus MAX V write enable
Embedded USB-Blaster II configuration done LED
FPGA configuration error LED
FPGA configuration active LED
MAX V reset push button
FPGA mode select 0
FPGA mode select 1
FPGA mode select 2
FPGA mode select 3
FPGA mode select 4
Temperature monitor fan enable
DIP switch to enable the PCI Express JTAG master
Load the flash memory image identified by the PGM LEDs
Flash memory PGM select indicator 0
Flash memory PGM select indicator 1
Flash memory PGM select indicator 2
Toggles the PGM_LED[2:0] LED sequence
SDI data transmission fault
SDI equalization bypass
SDI receive enable
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–10 Chapter 2: Board Components
FPGA Configuration
Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 5 of 5)
Board
Reference (U12)
K5
L16
N16
Schematic Signal Name
SDI_SCL
SDI_SDA
SDI_TX_EN
I/O Standard
2.5-V
2.5-V
2.5-V
R12
T13
T9
T10
T4
R4
R9
T11
T15
K16
H1
G12
C14
J1
R8
T7
T8
T12
H5
SECURITY_MODE
SENSE_CS0N
SENSE_SCK
SENSE_SDI
SENSE_SDO
SI571_EN
USB_CFG0
USB_CFG1
USB_CFG2
USB_CFG3
USB_CFG4
USB_CFG5
USB_CFG6
USB_CFG7
USB_CFG8
USB_CFG9
USB_CFG10
USB_CFG11
USB_CLK
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
Description
SDI clock
SDI data
SDI transmit enable
DIP switch for the embedded USB-Blaster II to send FACTORY command at power up
Power monitor chip select
Power monitor SPI clock
Power monitor SPI data in
Power monitor SPI data out
Si571 programmable VCXO enable
Embedded USB-Blaster II interface. Reserved for future use
Embedded USB-Blaster II interface. Reserved for future use
Embedded USB-Blaster II interface. Reserved for future use
Embedded USB-Blaster II interface. Reserved for future use
Embedded USB-Blaster II interface. Reserved for future use
Embedded USB-Blaster II interface. Reserved for future use
Embedded USB-Blaster II interface. Reserved for future use
Embedded USB-Blaster II interface. Reserved for future use
Embedded USB-Blaster II interface. Reserved for future use
Embedded USB-Blaster II interface. Reserved for future use
Embedded USB-Blaster II interface. Reserved for future use
Embedded USB-Blaster II interface. Reserved for future use
Embedded USB-Blaster II interface clock
FPGA Configuration
This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System
Controller device programming methods supported by the Cyclone V GX FPGA development board.
The Cyclone V GX development board supports the following three configuration methods:
■
Embedded USB-Blaster is the default method for configuring the FPGA using the
Quartus II Programmer in JTAG mode with the supplied USB cable.
■
■
Flash memory download for configuring the FPGA using stored images from the flash memory on either power-up or pressing the program configuration push button (S6).
External USB-Blaster for configuring the FPGA using an external USB-Blaster that connects to the JTAG chain header (J13).
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
FPGA Configuration
2–11
FPGA Programming over Embedded USB-Blaster
This configuration method implements a USB type-B connector (J12), a USB 2.0 PHY device (U16), and an Altera MAX II CPLD EPM240M100C4N (U20) to allow FPGA configuration using a USB cable. This USB cable connects directly between the USB type-B connector on the board and a USB port of a PC running the Quartus II software.
The embedded USB-Blaster in the MAX II CPLD EPM570F100C5N normally masters the JTAG chain.
Figure 2–3 illustrates the JTAG chain.
Figure 2–3. JTAG Chain
Enable
GPIO
GPIO
Embedded
GPIO
USB-Blaster II
GPIO
GPIO
GPIO
JTAG Master
TCK
TMS
TDO
TDI
DIP Switch
Disable
Enable
Enable
DIP Switch
10-pin
JTAG Header
Analog
Switch
2.5 V
2.5 V
Level
Shifter
TCK
TMS
Cyclone V GX
TDI
FPGA
TDO
JTAG Slave
TCK
TMS
TDI
PCI Express
Edge
Connector
TDO
JTAG Master
PCI Express
Motherboard
Always
Enabled
(in JTAG chain)
TCK
TMS
TDI
TDO
HSMC
Port
JTAG Slave
TCK
TMS
TDI
TDO
MAX V
System
Controller
JTAG Slave
HSMC
Flash
Memory
Analog
Switch
DIP Switch
The JTAG chain control DIP switch (SW5) controls the jumpers shown in Figure 2–3 .
To connect a device or interface in the chain, their corresponding switch must be in the OFF position. Slide all the switches in the ON position to only have the FPGA in the chain.
1
The MAX V CPLD 5M2210 System Controller must be in the JTAG chain to use some of the GUI interfaces.
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2–12 Chapter 2: Board Components
FPGA Configuration
Table 2–5 lists the USB 2.0 PHY schematic signal names and their corresponding
Cyclone V GX device pin numbers.
Board Reference
(U16)
B3
A3
C3
A2
A8
A7
B6
A6
H5
G5
F5
H6
H3
F4
H4
G4
B8
F3
G3
A1
B1
F6
C8
C7
C6
H8
G6
F8
F7
C1
C2
E1
E2
H7
G7
Schematic
Signal Name
24M_XTALIN
24M_XTALOUT
FX2_D_N
FX2_D_P
FX2_FLAGA
FX2_FLAGB
FX2_FLAGC
FX2_PA1
FX2_PA2
FX2_PA3
FX2_PA4
FX2_PA5
FX2_PA6
FX2_PA7
FX2_PB0
FX2_PB1
FX2_PB2
FX2_PB3
FX2_PB4
FX2_PB5
FX2_PB6
FX2_PB7
FX2_PD0
FX2_PD1
FX2_PD2
FX2_PD3
FX2_PD4
FX2_PD5
FX2_PD6
FX2_PD7
FX2_RESETN
FX2_SCL
FX2_SDA
FX2_SLRDN
FX2_SLWRN
Table 2–5. USB 2.0 PHY Schematic Signal Names and Functions (Part 1 of 2)
Cyclone V GX
Pin Number
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V21
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I/O Standard
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
3.3-V
Description
Crystal oscillator input
Crystal oscillator output
USB 2.0 PHY data
USB 2.0 PHY data
Slave FIFO output status
Slave FIFO output status
Slave FIFO output status
USB 2.0 PHY port A interface
USB 2.0 PHY port A interface
USB 2.0 PHY port A interface
USB 2.0 PHY port A interface
USB 2.0 PHY port A interface
USB 2.0 PHY port A interface
USB 2.0 PHY port A interface
USB 2.0 PHY port B interface
USB 2.0 PHY port B interface
USB 2.0 PHY port B interface
USB 2.0 PHY port B interface
USB 2.0 PHY port B interface
USB 2.0 PHY port B interface
USB 2.0 PHY port B interface
USB 2.0 PHY port B interface
USB 2.0 PHY port D interface
USB 2.0 PHY port D interface
USB 2.0 PHY port D interface
USB 2.0 PHY port D interface
USB 2.0 PHY port D interface
USB 2.0 PHY port D interface
USB 2.0 PHY port D interface
USB 2.0 PHY port D interface
Embedded USB-Blaster hard reset
USB 2.0 PHY serial clock
USB 2.0 PHY serial data
Read strobe for slave FIFO
Write strobe for slave FIFO
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
FPGA Configuration
2–13
Table 2–5. USB 2.0 PHY Schematic Signal Names and Functions (Part 2 of 2)
Board Reference
(U16)
B7
G2
Schematic
Signal Name
FX2_WAKEUP
USB_CLK
Cyclone V GX
Pin Number
—
AA23
I/O Standard
3.3-V
3.3-V
Description
USB 2.0 PHY wake signal
USB 2.0 PHY 48-MHz interface clock
FPGA Programming from Flash Memory
Flash memory programming is possible through a variety of methods. The default method is to use the factory design—Board Update Portal. This design is an embedded webserver, which serves the Board Update Portal web page. The web page allows you to select new FPGA designs including hardware, software, or both in an industry-standard S-Record File (.flash) and write the design to the user hardware page (page 1) of the flash memory over the network.
The secondary method is to use the pre-built parallel flash loader (PFL) design included in the development kit. The development board implements the Altera PFL megafunction for flash memory programming. The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD).
The PFL functions as a utility for writing to a compatible flash memory device. This pre-built design contains the PFL megafunction that allows you to write either page 0, page 1, or other areas of flash memory over the USB interface using the Quartus II software. This method is used to restore the development board to its factory default settings.
Other methods to program the flash memory can be used as well, including the
Nios
®
II processor. f
For more information on the Nios II processor, refer to the Nios II Processor page of the Altera website.
On either power-up or by pressing the program configuration push button,
PGM_CONFIG
(S6), the MAX V CPLD 5M2210 System Controller's PFL configures the
FPGA from the flash memory. The PFL megafunction reads 16-bit data from the flash memory and converts it to fast passive parallel (FPP) format. This 16-bit data is then written to the dedicated configuration pins in the FPGA during configuration.
Pressing the PGM_CONFIG push button (S6) loads the FPGA with a hardware page based on which PGM_LED[2:0] (D11, D12, D13) illuminates. Table 2–6 defines the design that loads when you press the PGM_CONFIG push button.
Table 2–6. PGM_LED Settings
(1)
PGM_LED0 (D12)
ON
OFF
OFF
PGM_LED1 (D13)
OFF
ON
OFF
PGM_LED2 (D14)
OFF
OFF
ON
Note to Table 2–6 :
(1) ON indicates a setting of ’0’ while OFF indicates a setting of ’1’.
Design
Factory hardware
User hardware 1
User hardware 2
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Reference Manual
2–14 Chapter 2: Board Components
FPGA Configuration
Figure 2–4 shows the PFL configuration.
Figure 2–4. PFL Configuration
2.5 V 2.5 V
56.2
Ω
100
Ω
2.5 V
56.2
Ω
MAX V CPLD
5M2210 System Controller
ERROR
LOAD
CLK_SEL
CLK_EN
FACT_LOAD
SEC_MODE
FPGA_nSTATUS
FPGA_nCONFIG
FPGA_CONF_DONE
MAX_RESETn
CONF_DONE
PGM_CONFIG
FPGA_DATA [15:0]
FPGA_DCLK
PGM_SEL
PGM_LED0
PGM_LED1
PGM_LED2
FLASH_A [25:1]
FLASH_D [31:0]
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_RYBSYn0
FLASH_RYBSYn1
FLASH_CLK
FLASH_RSTn
FLASH_ADVn
CFI Flash
FLASH_A [25:1]
FLASH_D [15:0]
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_RYBSYn0
FLASH_CLK
FLASH_RESETn
FLASH_WPn
FLASH_ADVn
50 MHz
100 MHz
2.5 V
56.2
Ω
CONF_DONE_LED
2.5 V
2.5 V
10 k
Ω
10 k
Ω
Cyclone V FPGA
nSTATUS nCONFIG
CONF_DONE nCE
FPP Mode
DATA [15:0]
DCLK
Flash Interface
MSEL[4:0]
Connects to the
MAX V CPLD
10 k
Ω f
For more information on the following topics, refer to the respective documents:
■
■
Board Update Portal, PFL design, and flash memory map storage, refer to the
Cyclone V GX FPGA Development Kit User Guide
.
PFL megafunction, refer to
Parallel Flash Loader Megafunction User Guide.
FPGA Programming over External USB-Blaster
The JTAG chain header provides another method for configuring the FPGA using an external USB-Blaster device with the Quartus II Programmer running on a PC. To prevent contention between the JTAG masters, the embedded USB-Blaster is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG chain header.
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Status Elements
2–15
Status Elements
The development board includes status LEDs. This section describes the status elements.
Table 2–7 lists the LED board references, names, and functional descriptions.
Table 2–7. Board-Specific LEDs
Board
Reference
D23
Schematic Signal
Power
Name
D15
MAX_CONF_DONEn
D16
D17
MAX_ERROR
MAX_LOAD
I/O
Standard
5.0-V
2.5-V
2.5-V
2.5-V
Description
Blue LED. Illuminates when 5.0 V power is active.
Green LED. Illuminates when the FPGA is successfully configured.
Driven by the MAX V CPLD 5M2210 System Controller.
Red LED. Illuminates when the MAX V CPLD 5M2210 System
Controller fails to configure the FPGA. Driven by the MAX V CPLD
5M2210 System Controller.
Green LED. Illuminates when the MAX V CPLD 5M2210 System
Controller is actively configuring the FPGA. Driven by the MAX V
CPLD 5M2210 System Controller.
D12
D13
D14
D27, D26
D28, D25
D19
D22
D24
D20
D21
D18
D3
PGM_LED[0]
PGM_LED[1]
PGM_LED[2]
JTAG_RX, JTAG_TX
SC_RX, SC_TX
ENET_LED_TX
ENET_LED_RX
ENET_LED_LINK10
ENET_LED_LINK100
ENET_LED_LINK1000
SDI_RX_CDn
HSMA_PRSNTn
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
3.3-V
3.3-V
Green LEDs. Illuminates to indicate which hardware page loads from flash memory when you press the PGM_SEL push button.
Green LEDs. Illuminates to indicate USB-Blaster II receive and transmit activities.
Green LED. Illuminates to indicate Ethernet PHY transmit activity.
Driven by the Marvell 88E1111 PHY.
Green LED. Illuminates to indicate Ethernet PHY receive activity.
Driven by the Marvell 88E1111 PHY.
Green LED. Illuminates to indicate Ethernet linked at 10 Mbps connection speed. Driven by the Marvell 88E1111 PHY.
Green LED. Illuminates to indicate Ethernet linked at 100 Mbps connection speed. Driven by the Marvell 88E1111 PHY.
Green LED. Illuminates to indicate Ethernet linked at 1000 Mbps connection speed. Driven by the Marvell 88E1111 PHY.
Green LED. Illuminates to indicate that input signal is detected at the
SDI RX port. Driven by the SDI cable equalizer.
Green LED. Illuminates when HSMC port A has a board or cable plugged-in such that pin 160 becomes grounded. Driven by the add-in card.
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Setup Elements
Setup Elements
■
■
■
■
■
■
The development board includes several different kinds of setup elements. This section describes the following setup elements:
■
Board settings DIP switch
JTAG settings DIP switch
PCI Express control DIP switch
CPU reset push button
MAX V reset push button
Program configuration push button
Program select push button
Board Settings DIP Switch
The board settings DIP switch (SW3) controls various features specific to the board and the MAX V CPLD 5M2210 System Controller logic design.
switch controls and descriptions.
Table 2–8. Board Settings DIP Switch Controls
Switch Schematic Signal Name
1
2
3
4
CLK_SEL
CLK_EN
FACT_LOAD
SEC_MODE
Description
ON : Select SMA input clock
OFF : Select programmable oscillator clock
ON : Disable on-board oscillator
OFF : Enable on-board oscillator
ON : Load the user design from flash at power up.
OFF : Load the factory design from flash at power up.
ON : Embedded USB-Blaster II sends FACTORY command at power up.
OFF : Embedded USB-Blaster II does not send FACTORY command at power up.
Default
OFF
OFF
OFF
OFF
JTAG Chain Control DIP Switch
The JTAG chain control DIP switch (SW5) either remove or include devices in the active JTAG chain. The Cyclone V GX FPGA is always in the JTAG chain.
lists the switch controls and its descriptions.
Table 2–9. JTAG Chain Control DIP Switch
Switch Schematic Signal Name
1
2
5M2210_JTAG_EN
HSMA_JTAG_EN
Description
ON : Bypass MAX V CPLD 5M2210 System Controller
OFF : MAX V CPLD 5M2210 System Controller in-chain
ON : Bypass HSMC port A
OFF : HSMC port A in-chain
Default
OFF
ON
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Setup Elements
2–17
Table 2–9. JTAG Chain Control DIP Switch
Switch Schematic Signal Name
3
4
PCIE_JTAG_EN
NC
Description
ON : Bypass PCI Express edge connector
OFF : PCI Express edge connector in-chain
Not used
Default
ON
—
PCI Express Link Width DIP Switch
The PCI Express link width DIP switch (SW4) enable or disable different link width
lists the switch controls and descriptions.
Table 2–10. PCI Express Link Width DIP Switch Controls
Switch Schematic Signal Name
1
2
3
4
PCIE_PRSNT2n_x1
PCIE_PRSNT2n_x4
NC
FAN_FORCE_ON
Description
ON : Enable x1 presence detect
OFF : Disable x1 presence detect
ON : Enable x4 presence detect
OFF : Disable x4 presence detect
Not used
ON : Enable fan
OFF : Disable fan
Default
OFF
OFF
—
OFF
CPU Reset Push Button
The CPU reset push button, CPU_RESETn (S2), is an input to the Cyclone V GX DEV_CLRn pin and is an open-drain I/O from the MAX V CPLD System Controller. This push button is the default reset for both the FPGA and CPLD logic. The MAX V CPLD
5M2210 System Controller also drives this push button during power-on-reset (POR).
MAX V Reset Push Button
The MAX V reset push button, MAX_RESETn (S1), is an input to the MAX V CPLD
5M2210 System Controller. This push button is the default reset for the CPLD logic.
Program Configuration Push Button
The program configuration push button, PGM_CONFIG (S6), is an input to the MAX V
CPLD 5M2210 System Controller. This input forces a FPGA reconfiguration from the flash memory. The location in the flash memory is based on the settings of
PGM_LED[2:0]
, which is controlled by the program select push button, PGM_SEL. Valid settings include PGM_LED0, PGM_LED1, or PGM_LED2 on the three pages in flash memory reserved for FPGA designs.
Program Select Push Button
The program select push button, PGM_SEL (S7), is an input to the MAX V CPLD System
Controller. This push button toggles the PGM_LED[2:0]sequence that selects which location in the flash memory is used to configure the FPGA. Refer to Table 2–6 for the
PGM_LED[2:0]
sequence definitions.
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Clock Circuitry
Clock Circuitry
This section describes the board's clock inputs and outputs.
On-Board Oscillators
The development board include oscillators with a frequency of 50-MHz, 100-MHz,
148.50-MHz, and a quad-clock programmable oscillator.
Figure 2–5 shows the default frequencies of all external clocks going to the
Cyclone V GX FPGA development board.
Figure 2–5. Cyclone V GX FPGA Development Board Clocks
25 MHz Fixed
Oscillator
SMA
LVPECL
Clock Input
SMA SMA
IDT5T9306
Clock Fan-Out
IN1 x4 LVDS
CH0
CH1
IN2
CH2
CH3
To Bank 4A
IN1
Si5338 x4 LVDS Output
CH0 125 MHz
CH2 156.25 MHz
HSMC XVCR x4
FA-128
24.0 MB-W
24 MHz XTAL
FA-128
24.0 MB-W
24 MHz XTAL
CY7C68013A
USB
Microcontroller
USB Clock
48 MHz
MAX II CPLD
Embedded
USB-Blaster II
10/100/1000
Base-T
Ethernet PHY
88E1111
Bank
8A
Bank
9A
Bank
2L
Si571
LVDS VCXO
148.5 MHz and
148.35 MHz
SDI x1
Bank
1L
Bank
0L
Bank
3A
Cyclone V GX FPGA
Bank
3B
Bank
7A
Bank
6A
Bank
5B
Bank
4A
Bank
5A
MAX V CPLD
System Controller
SL18860DC
Clock Fan-Out x3 SE
CH1
CH2
CH3
Si510 SE
50 MHz Fixed
Oscillator
Si510 SE
50 MHz Fixed
Oscillator
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Clock Circuitry
2–19
Table 2–11 lists the oscillators, its I/O standard, and voltages required for the development board.
Table 2–11. On-Board Oscillators
Source Schematic Signal Name
X4
X1
J19
U25
X2
Frequency
CLKIN_50_7A
CLKIN_50_TOP
CLK_CONFIG
PCIE_REFCLK_P
PCIE_REFCLK_N
CLKIN_BANK3B_125_R_P
CLKIN_BANK3B_125_R_N
CLKIN_BANK4A_125_R_P
CLKIN_BANK4A_125_R_N
REFCLK1_Q2L_P
REFCLK1_Q2L_N
CLK_148_P
CLK_148_N
50.000 MHz
100.000 MHz
100.000 MHz
125.000 MHz
148.500 MHz
I/O Standard
Single-Ended
2.5V CMOS
LVDS
1.5V LVDS
(fanout buffer)
LVDS
Cyclone V GX
Pin Number
AA15
AC15
AB16
P8
N7
R8
R7
H17
K15
—
W8
W7
Y15
Top edge
Application
Fast FPGA configuration
PCI Express x4
Bottom edge
HSMC port A
HD-SDI video
Off-Board Clock Input/Output
The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device’s specification.
Table 2–12 lists the clock inputs for the development board.
Table 2–12. Off-Board Clock Inputs
SMA
Source
Schematic Signal
Name
CLKIN_SMA_P
CLKIN_SMA_N
Samtec HSMC
HSMA_CLK_IN0
Samtec HSMC
Samtec HSMC
PCI Express
Edge
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
PCIE_REFCLK_P
PCIE_REFCLK_N
I/O Standard
LVPECL
LVPECL
2.5-V
LVDS/2.5-V
LVDS/LVTTL
LVDS/LVTTL
LVDS/LVTTL
LVDS
HCSL
Cyclone V GX
Pin Number
—
—
Description
Input to LVDS fan-out buffer (drives one REFCLK)
L15
Single-ended input from the installed HSMC cable or board.
H19
J18
L14
L13
W8
W7
LVDS input from the installed HSMC cable or board. Can also support 2x LVTTL inputs.
LVDS input from the installed HSMC cable or board. Can also support 2x LVTTL inputs.
LVDS input from the PCI Express edge connector.
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General User Input/Output
Table 2–13 lists the clock outputs for the development board.
Table 2–13. Off-Board Clock Outputs
Source
Schematic Signal
Name
Samtec HSMC
HSMA_CLK_OUT0
Samtec HSMC
Samtec HSMC
SMA
I/O Standard
CLKOUT_SMA
2.5V CMOS
HSMA_CLK_OUT_P1
LVDS/2.5V CMOS
HSMA_CLK_OUT_N1
LVDS/2.5V CMOS
HSMA_CLK_OUT_P2
LVDS/2.5V CMOS
HSMA_CLK_OUT_N2
LVDS/2.5V CMOS
2.5V CMOS
Cyclone V GX
Pin Number
J19
Description
FPGA CMOS output (or GPIO)
B26
A26
A25
A24
F9
LVDS output. Can also support 2x CMOS outputs.
LVDS output. Can also support 2x CMOS outputs.
FPGA CMOS output (or GPIO)
General User Input/Output
This section describes the user I/O interface to the FPGA, including the push buttons,
DIP switches, LEDs, and character LCD.
User-Defined Push Buttons
The development board includes three user-defined push buttons. For information on
the system and safe reset push buttons, refer to “Setup Elements” on page 2–16
.
Board references S3, S4, and S5 are push buttons for controlling the FPGA designs that loads into the Cyclone V GX device. When you press and hold down the switch, the device pin is set to logic 0; when you release the switch, the device pin is set to logic 1.
There are no board-specific functions for these general user push buttons.
Table 2–14 lists the user-defined push button schematic signal names and their corresponding Cyclone V GX device pin numbers.
Table 2–14. User-Defined Push Button Schematic Signal Names and Functions
Board Reference
S3
S4
S5
Schematic Signal
Name
USER_PB0
USER_PB1
USER_PB2
Cyclone V GX Pin
Number
AF29
AF30
AE28
I/O Standard
1.5-V
1.5-V
1.5-V
Description
User-defined push buttons
User-Defined DIP Switch
Board reference SW2 is a four-pin DIP switch. This switch is user-defined and provides additional FPGA input control. When the switch is in the OFF position, a logic 1 is selected. When the switch is in the ON position, a logic 0 is selected. There are no board-specific functions for this switch.
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2–21
Table 2–15 lists the user-defined DIP switch schematic signal names and their corresponding Cyclone V GX device pin numbers.
Table 2–15. User-Defined DIP Switch Schematic Signal Names and Functions
Board Reference
1
2
3
4
Schematic
Signal Name
USER_DIPSW0
USER_DIPSW1
USER_DIPSW2
USER_DIPSW3
Cyclone V GX
Pin Number
AG29
AH29
AJ29
AJ28
I/O Standard
1.5-V
1.5-V
1.5-V
1.5-V
Description
User-defined DIP switch that connects to the FPGA
User-Defined LEDs
The development board includes general and HSMC user-defined LEDs. This section describes all user-defined LEDs. For information on board specific or status LEDs,
refer to “Status Elements” on page 2–15
.
General LEDs
Board references D4 through D7 are four user-defined LEDs. The status and debugging signals are driven to the LEDs from the designs loaded into the
Cyclone V GX. Driving a logic 0 on the I/O port turns the LED on while driving a logic 1 turns the LED off. There are no board-specific functions for these LEDs.
Table 2–16 lists the general LED schematic signal names and their corresponding
Cyclone V GX device pin numbers.
Table 2–16. General LED Schematic Signal Names and Functions
Board Reference
D4
D5
D6
D7
Schematic
Signal Name
USER_LED0
USER_LED1
USER_LED2
USER_LED3
Cyclone V GX
Pin Number
AF28
AG28
AH30
AJ30
I/O Standard
2.5-V
2.5-V
2.5-V
2.5-V
Description
User-defined LEDs
HSMC LEDs
Board references D1 and D2 are LEDs for the HSMC port. There are no board-specific functions for the HSMC LEDs. The LEDs are labeled TX and RX, and are intended to display data flow to and from the connected daughtercards. The LEDs are driven by the Cyclone V GX device.
Table 2–17 lists the HSMC LED schematic signal names and their corresponding
Cyclone V GX device pin numbers.
Table 2–17. HSMC LED Schematic Signal Names and Functions
Board Reference
D1
D2
Schematic
Signal Name
HSMA_RX_LED
HSMA_TX_LED
Cyclone V GX
Pin Number
T11
AB26
I/O Standard
2.5-V
2.5-V
Description
User-defined LEDs
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General User Input/Output
PCI Express LEDs
Board references D8 through D10 are PCI Express LEDs for link width indication.
There are no board-specific functions for the PCI Express LEDs. You can configure the
LEDs to display the functions as listed in
Table 2–18 . The LEDs are driven by the
Cyclone V GX device.
lists the PCI Express LED schematic signal names and their corresponding
Cyclone V GX device pin numbers.
Table 2–18. PCI Express LED Schematic Signal Names and Functions
Board
Reference
Schematic
Signal Name
Cyclone V GX
Pin Number
I/O Standard
D8
D9
D10
PCIE_LED_X1
PCIE_LED_X4
PCIE_LED_G1
AD28
AC29
AB28
2.5-V
2.5-V
2.5-V
Description
Green LED. Configure this LED to display the
PCI Express link width x1.
Green LED. Configure this LED to display the
PCI Express link width x4.
Green LED. Configure this LED to display the
PCI Express Gen1 link.
Character LCD
The development board includes a single 14-pin 0.1" pitch dual-row header that interfaces to a 2 line × 16 character Lumex character LCD. The character LCD has a
14-pin receptacle that mounts directly to the board's 14-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging or other purposes.
Table 2–19 summarizes the character LCD pin assignments. The signal names and directions are relative to the Cyclone V GX device.
Table 2–19. Character LCD Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (J18)
13
14
4
5
6
9
10
11
12
7
8
Schematic Signal Name
LCD_DATA0
LCD_DATA1
LCD_DATA2
LCD_DATA3
LCD_DATA4
LCD_DATA5
LCD_DATA6
LCD_DATA7
LCD_D_Cn
LCD_WEn
LCD_CSn
Cyclone V GX
Pin Number
AG6
R12
D17
E17
C11
T10
AH5
AH4
U8
T9
AH6
I/O Standard
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
Description
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data or command select
LCD write enable
LCD chip select
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2–23
lists the LCD pin definitions, and is an excerpt from Lumex data sheet.
Table 2–20. LCD Pin Definitions and Functions
1
2
3
Pin
Number
4
5
6
7–14
V
E
Symbol
DD
V
SS
V
0
RS
R/W
DB0–DB7
Level
—
—
—
H/L
H/L
H, H to L
H/L
Function
Power supply
5 V
GND (0 V)
For LCD drive
Register select signal
H: Data input
L: Instruction input
H: Data read (module to MPU)
L: Data write (MPU to module)
Enable
Data bus—software selectable 4-bit or 8-bit mode f
For more information such as timing, character maps, interface guidelines, and other related documentation, visit www.lumex.com
.
Debug Header
This development board includes a 2×7 debug header for debug purposes. The FPGA
I/Os route directly to the header for design testing, debugging, or quick verification.
Table 2–21 summarizes the debug header pin assignments, signal names, and functions.
Table 2–21. Debug Header Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (J14)
8
11
1
2
5
Schematic Signal
Name
DEBUG_HDR0
DEBUG_HDR6
DEBUG_HDR2
DEBUG_HDR9
SECURITY_CPLD_MRn
Cyclone V GX
Pin Number
E10
U22
L21
M21
—
I/O Standard
2.5-V
1.5-V
1.5-V
1.5-V
1.5-V
Description
Single-ended signal for debug purposes only
Single-ended signal for debug purposes only
Single-ended signal for debug purposes only
Single-ended signal for debug purposes only
Test signal
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Components and Interfaces
■
■
■
■
This section describes the development board's communication ports and interface cards relative to the Cyclone V GX device. The development board supports the following communication ports:
PCI Express
10/100/1000 Ethernet
HSMC
SDI video output/input
PCI Express
The Cyclone V GX FPGA development board is designed to fit entirely into a PC motherboard with a ×4 PCI Express slot that can accommodate a full height long form factor add-in card. This interface uses the Cyclone V GX's PCI Express hard IP block, saving logic resources for the user logic application. The PCI express edge connector has a presence detect feature to allow the motherboard to determine if a card is installed.
f
For more information on using the PCI Express hard IP block, refer to the
PCI Express
Compiler User Guide
.
The PCI Express interface supports auto-negotiating channel width from ×1 to ×4 by using Altera's PCIe MegaCore IP. You can also configure this board to a ×1 or ×4 interface through a DIP switch that connects the PRSNTn pins for each bus width.
The PCI Express interface has a connection speed of 2.5 Gbps/lane for a maximum of
20 Gbps full-duplex (Gen1).
The power for the board can be sourced entirely from the PCI Express edge connector when installed into a PC motherboard. Although the board can also be powered by a laptop power supply for use on a lab bench, Altera recommends that you do not power up from both supplies at the same time. Ideal diode power sharing devices have been designed into this board to prevent damages or back-current from one supply to the other.
The PCIE_REFCLK_P/N signal is a 100 MHz differential input that is driven from the PC motherboard on to this board through the edge connector. This signal connects directly to a Cyclone V GX REFCLK input pin pair using DC coupling. This clock is terminated on the motherboard and therefore, no on-board termination is required.
This clock can have spread-spectrum properties that change its period between
9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic (HCSL).
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Figure 2–6 shows the PCI Express reference clock levels.
Figure 2–6. PCI Express Reference Clock Levels
V
MAX
= 1.15 V
REFCLK –
V
CROSS MAX
= 550 mV
V
CROSS MIN
= 250 mV
REFCLK +
V
MIN
= –0.30 V
2–25
The JTAG and SMB are optional signals in the PCI Express specification. Both types of signals are wired to the Cyclone V GX but are not required for normal operation.
summarizes the PCI Express pin assignments. The signal names and directions are relative to the Cyclone V GX.
Table 2–22. PCI Express Pin Assignments, Schematic Signal Names, and Functions
B28
B5
B6
A16
A17
A21
A22
B20
B23
B24
B27
A14
B14
B15
B19
Board
Reference (J19)
A5
A1
B17
B31
A13
A6
A7
A8
A11
Schematic Signal Name
PCIE_JTAG_TCK
PCIE_JTAG_TDI
PCIE_JTAG_TDO
PCIE_JTAG_TMS
PCIE_PERSTN
PCIE_PRSNT1N
PCIE_PRSNT2N_X1
PCIE_PRSNT2N_X4
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_RX_P0
PCIE_RX_N0
PCIE_RX_P1
PCIE_RX_N1
PCIE_RX_P2
PCIE_RX_N2
PCIE_RX_P3
PCIE_RX_N3
PCIE_SMBCLK
PCIE_SMBDAT
PCIE_TX_P0
PCIE_TX_N0
PCIE_TX_P1
PCIE_TX_N1
AA1
R11
V22
AF4
AF3
AD4
AD3
AE1
AC2
AC1
AA2
W7
AG2
AG1
AE2
Cyclone V GX
Pin Number
—
—
—
—
W8
—
—
—
W27
I/O Standard Description
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
JTAG chain clock
JTAG chain data in
JTAG chain data out
JTAG chain mode select
Reset
LVTTL
LVTTL
LVTTL
HCSL
Link width DIP switch
Hot plug present detect
Hot plug present detect
Reference clock input
HCSL Reference clock input
1.5-V PCML Receive bus
1.5-V PCML Receive bus
1.5-V PCML Receive bus
1.5-V PCML Receive bus
1.5-V PCML Receive bus
1.5-V PCML Receive bus
1.5-V PCML Receive bus
1.5-V PCML Receive bus
2.5-V SMB clock
2.5-V SMB data
1.5-V PCML Transmit bus
1.5-V PCML Transmit bus
1.5-V PCML Transmit bus
1.5-V PCML Transmit bus
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Table 2–22. PCI Express Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (J19)
A25
A26
A29
A30
B11
Schematic Signal Name
PCIE_TX_P2
PCIE_TX_N2
PCIE_TX_P3
PCIE_TX_N3
PCIE_WAKEn
Cyclone V GX
Pin Number
AB4
AB3
Y4
Y3
Y27
I/O Standard
1.5-V PCML Transmit bus
1.5-V PCML Transmit bus
1.5-V PCML Transmit bus
1.5-V PCML Transmit bus
2.5-V Wake signal
Description
10/100/1000 Ethernet
The development board supports 10/100/1000 base-T Ethernet using an external
Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. The
PHY-to-MAC interface employs a RGMII interface. The MAC function must be provided in the FPGA for typical networking applications.
The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator. The PHY interfaces to a RJ45 model with internal magnetics that can be used for driving copper lines with Ethernet traffic.
Figure 2–7 shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111
PHY.
Figure 2–7. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
RXD[3:0]
10/100/1000 Mbps
Ethernet MAC
TXD[3:0]
Marvell 88E1111
PHY
Device
Transformer
RGMII Interface
RJ45
CAT 5 UTP:
- 10BASE-T
- 100BASE-TX
- 1000BASE-T
lists the Ethernet PHY interface pin assignments.
Table 2–23. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 1 of 2)
Board
Reference (U10)
70
76
74
73
8
23
60
58
69
68
25
Schematic Signal Name
ENET_GTX_CLK
ENET_INTN
ENET_LED_DUPLEX
ENET_LED_DUPLEX
ENET_LED_LINK10
ENET_LED_LINK100
ENET_LED_LINK1000
ENET_LED_RX
ENET_LED_RX
ENET_LED_TX
ENET_MDC
Cyclone V GX
Pin Number
U9
B17
—
—
—
—
—
—
—
—
C17
I/O Standard
2.5-V CMOS
2.5-V CMOS
2.5-V CMOS
2.5-V CMOS
2.5-V CMOS
2.5-V CMOS
Description
125-MHz RGMII transmit clock
Management bus interrupt
Duplex or collision LED. Not used
2.5-V CMOS Duplex or collision LED. Not used
2.5-V CMOS 10-Mb link LED
2.5-V CMOS 100-Mb link LED
2.5-V CMOS 1000-Mb link LED
2.5-V CMOS RX data active LED
RX data active LED
TX data active LED
Management bus data clock
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Table 2–23. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 2 of 2)
Board
Reference (U10)
9
55
29
31
11
12
14
16
92
93
91
94
24
28
2
95
33
34
39
41
42
43
Schematic Signal Name
ENET_MDIO
ENET_RESETN
ENET_RX_CLK
ENET_RX_D0
ENET_RX_D1
ENET_RX_D2
ENET_RX_D3
ENET_RX_DV
ENET_TX_D0
ENET_TX_D1
ENET_TX_D2
ENET_TX_D3
ENET_TX_EN
ENET_XTAL_25MHZ
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
Cyclone V GX
Pin Number
K20
—
—
—
AG7
AB8
AA8
AG8
AB9
AA9
AH7
D19
D18
J17
G17
AF8
—
—
—
—
—
—
I/O Standard Description
2.5-V CMOS Management bus data
2.5-V CMOS Device reset
2.5-V CMOS RGMII receive clock
2.5-V CMOS RGMII receive data bus
2.5-V CMOS RGMII receive data bus
2.5-V CMOS RGMII receive data bus
2.5-V CMOS RGMII receive data bus
2.5-V CMOS RGMII receive data valid
2.5-V CMOS RGMII transmit data bus
2.5-V CMOS RGMII transmit data bus
2.5-V CMOS RGMII transmit data bus
2.5-V CMOS RGMII transmit data bus
2.5-V CMOS RGMII transmit enable
2.5-V CMOS 25-MHz RGMII transmit clock
2.5-V CMOS Media dependent interface
2.5-V CMOS Media dependent interface
2.5-V CMOS Media dependent interface
2.5-V CMOS Media dependent interface
2.5-V CMOS Media dependent interface
2.5-V CMOS Media dependent interface
2.5-V CMOS Media dependent interface
2.5-V CMOS Media dependent interface
HSMC
The development board supports a HSMC interface. This physical interface provides four channels of 3.125 Gbps-capable transceivers. The HSMC interface also supports a full SPI4.2 interface (17 LVDS channels), three input and output clocks, as well as
JTAG and SMB signals. The LVDS channels can be used for CMOS signaling or LVDS.
1
The HSMC is an Altera-developed open specification, which allows you to expand the functionality of the development board through the addition of daughtercards
(HSMCs).
f
For more information about the HSMC specification such as signaling standards, signal integrity, compatible connectors, and mechanical information, refer to the
High
Speed Mezzanine Card (HSMC) Specification
manual.
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The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins, and 13 ground pins. The ground pins are located between the two rows of signal and power pins, acting both as a shield and a reference. The HSMC host connector is based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board connectors from Samtec. There are three banks in this connector. Bank 1 has every third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have all the pins populated as done in the QSH/QTH series.
Figure 2–8 shows the bank arrangement of signals with respect to the Samtec
connector's three banks.
Figure 2–8. HSMC Signal and Bank Diagram
Bank 3
Power
D(79.40)
-or-
LVDS
CLKIN2, CLKOUT2
Bank 2
Power
D(39:0)
-or-
D[3:0] + LVDS
CLKIN1, CLKOUT1
Bank 1
8 TX Channels CDR
8 RX Channels CDR
JTAG
SMB
CLKIN0, CLKOUT0
The HSMC interface has programmable bi-directional I/O pins that can be used as
2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as various differential I/O standards including, but not limited to, LVDS, mini-LVDS, and RSDS with up to 17 full-duplex channels.
1
As noted in the
High Speed Mezzanine Card (HSMC) Specification
manual, LVDS and single-ended I/O standards are only guaranteed to function when mixed according to either the generic single-ended pin-out or generic differential pin-out.
Table 2–24 lists the HSMC interface pin assignments, signal names, and functions.
Table 2–24. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board
Reference (J1)
20
21
22
23
17
18
19
24
Schematic Signal Name
HSMA_TX_P3
HSMA_RX_P3
HSMA_TX_N3
HSMA_RX_N3
HSMA_TX_P2
HSMA_RX_P2
HSMA_TX_N2
HSMA_RX_N2
Cyclone V GX
Pin Number
L1
M4
N2
M3
K4
L2
K3
N1
I/O Standard Description
1.5-V PCML Transceiver TX bit 3
1.5-V PCML Transceiver RX bit 3
1.5-V PCML
1.5-V PCML
Transceiver TX bit 3n
1.5-V PCML Transceiver RX bit 3n
1.5-V PCML Transceiver TX bit 2
1.5-V PCML Transceiver RX bit 2
1.5-V PCML Transceiver TX bit 2n
Transceiver RX bit 2n
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Board
Reference (J1)
59
60
61
62
53
54
55
56
47
48
49
50
41
42
43
44
71
72
73
65
66
67
68
37
38
39
40
33
34
35
36
29
30
31
32
25
26
27
28
Schematic Signal Name
HSMA_TX_P1
HSMA_RX_P1
HSMA_TX_N1
HSMA_RX_N1
HSMA_TX_P0
HSMA_RX_P0
HSMA_TX_N0
HSMA_RX_N0
HSMA_SDA
HSMA_SCL
JTAG_TCK
HSMA_JTAG_TMS
HSMA_JTAG_TDO
JTAG_FPGA_TDO_RETIMER
HSMA_CLK_OUT0
HSMA_CLK_IN0
HSMA_D0
HSMA_D1
HSMA_D2
HSMA_D3
HSMA_TX_D_P0
HSMA_RX_D_P0
HSMA_TX_D_N0
HSMA_RX_D_N0
HSMA_TX_D_P1
HSMA_RX_D_P1
HSMA_TX_D_N1
HSMA_RX_D_N1
HSMA_TX_D_P2
HSMA_RX_D_P2
HSMA_TX_D_N2
HSMA_RX_D_N2
HSMA_TX_D_P3
HSMA_RX_D_P3
HSMA_TX_D_N3
HSMA_RX_D_N3
HSMA_TX_D_P4
HSMA_RX_D_P4
HSMA_TX_D_N4
Table 2–24. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Cyclone V GX
Pin Number
B13
E12
A13
D13
D14
H12
C14
G12
D12
E11
C12
D10
K16
L18
K18
K17
B14
G14
A14
F14
A16
F15
A15
—
—
J19
L15
H14
J14
AC7
—
T4
U2
T3
U1
P4
R2
P3
R1
I/O Standard Description
1.5-V PCML Transceiver TX bit 1
1.5-V PCML Transceiver RX bit 1
1.5-V PCML Transceiver TX bit 1n
1.5-V PCML Transceiver RX bit 1n
1.5-V PCML Transceiver TX bit 0
1.5-V PCML Transceiver RX bit 0
1.5-V PCML Transceiver TX bit 0n
1.5-V PCML Transceiver RX bit 0n
2.5-V CMOS Management serial data
2.5-V CMOS Management serial clock
2.5-V CMOS JTAG clock signal
2.5-V CMOS JTAG mode select signal
2.5-V CMOS JTAG data output
2.5-V CMOS JTAG data input
2.5-V CMOS Dedicated CMOS clock out
2.5-V CMOS Dedicated CMOS clock in
2.5-V CMOS Dedicated CMOS I/O bit 0
2.5-V CMOS Dedicated CMOS I/O bit 1
2.5-V CMOS Dedicated CMOS I/O bit 2
2.5-V CMOS Dedicated CMOS I/O bit 3
LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4
LVDS or 2.5-V LVDS RX bit 0 or CMOS bit 5
LVDS or 2.5-V LVDS TX bit 0n or CMOS bit 6
LVDS or 2.5-V LVDS RX bit 0n or CMOS bit 7
LVDS or 2.5-V LVDS TX bit 1 or CMOS bit 8
LVDS or 2.5-V LVDS RX bit 1 or CMOS bit 9
LVDS or 2.5-V LVDS TX bit 1n or CMOS bit 10
LVDS or 2.5-V LVDS RX bit 1n or CMOS bit 11
LVDS or 2.5-V LVDS TX bit 2 or CMOS bit 12
LVDS or 2.5-V LVDS RX bit 2 or CMOS bit 13
LVDS or 2.5-V LVDS TX bit 2n or CMOS bit 14
LVDS or 2.5-V LVDS RX bit 2n or CMOS bit 15
LVDS or 2.5-V LVDS TX bit 3 or CMOS bit 16
LVDS or 2.5-V LVDS RX bit 3 or CMOS bit 17
LVDS or 2.5-V LVDS TX bit 3n or CMOS bit 18
LVDS or 2.5-V LVDS RX bit 3n or CMOS bit 19
LVDS or 2.5-V LVDS TX bit 4 or CMOS bit 20
LVDS or 2.5-V LVDS RX bit 4 or CMOS bit 21
LVDS or 2.5-V LVDS TX bit 4n or CMOS bit 22
2–29
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–30 Chapter 2: Board Components
Components and Interfaces
Board
Reference (J1)
116
119
120
121
110
113
114
115
104
107
108
109
98
101
102
103
122
125
126
127
128
131
132
92
95
96
97
86
89
90
91
80
83
84
85
74
77
78
79
Schematic Signal Name
HSMA_RX_D_N4
HSMA_TX_D_P5
HSMA_RX_D_P5
HSMA_TX_D_N5
HSMA_RX_D_N5
HSMA_TX_D_P6
HSMA_RX_D_P6
HSMA_TX_D_N6
HSMA_RX_D_N6
HSMA_TX_D_P7
HSMA_RX_D_P7
HSMA_TX_D_N7
HSMA_RX_D_N7
HSMA_CLK_OUT_P1
HSMA_CLK_IN_P1
HSMA_CLK_OUT_N1
HSMA_CLK_IN_N1
HSMA_TX_D_P8
HSMA_RX_D_P8
HSMA_TX_D_N8
HSMA_RX_D_N8
HSMA_TX_D_P9
HSMA_RX_D_P9
HSMA_TX_D_N9
HSMA_RX_D_N9
HSMA_TX_D_P10
HSMA_RX_D_P10
HSMA_TX_D_N10
HSMA_RX_D_N10
HSMA_TX_D_P11
HSMA_RX_D_P11
HSMA_TX_D_N11
HSMA_RX_D_N11
HSMA_TX_D_P12
HSMA_RX_D_P12
HSMA_TX_D_N12
HSMA_RX_D_N12
HSMA_TX_D_P13
HSMA_RX_D_P13
Table 2–24. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Cyclone V GX
Pin Number
C20
B23
F20
A23
C19
D23
C21
C22
E18
A21
D20
A20
J18
B22
F19
B21
E20
C24
E22
B24
E21
D25
L20
F18
B26
H19
A26
E16
B19
G18
A19
C15
B18
F16
A18
E15
E23
C16
D22
I/O Standard Description
LVDS or 2.5-V LVDS RX bit 4n or CMOS bit 23
LVDS or 2.5-V LVDS TX bit 5 or CMOS bit 24
LVDS or 2.5-V LVDS RX bit 5 or CMOS bit 25
LVDS or 2.5-V LVDS TX bit 5n or CMOS bit 26
LVDS or 2.5-V LVDS RX bit 5n or CMOS bit 27
LVDS or 2.5-V LVDS TX bit 6 or CMOS bit 28
LVDS or 2.5-V LVDS RX bit 6 or CMOS bit 29
LVDS or 2.5-V LVDS TX bit 6n or CMOS bit 30
LVDS or 2.5-V LVDS RX bit 6n or CMOS bit 31
LVDS or 2.5-V LVDS TX bit 7 or CMOS bit 32
LVDS or 2.5-V LVDS RX bit 7 or CMOS bit 33
LVDS or 2.5-V LVDS TX bit 7n or CMOS bit 34
LVDS or 2.5-V LVDS RX bit 7n or CMOS bit 35
LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 36
LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 37
LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 38
LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 39
LVDS or 2.5-V LVDS TX bit 8 or CMOS bit 40
LVDS or 2.5-V LVDS RX bit 8 or CMOS bit 41
LVDS or 2.5-V LVDS TX bit 8n or CMOS bit 42
LVDS or 2.5-V LVDS RX bit 8n or CMOS bit 43
LVDS or 2.5-V LVDS TX bit 9 or CMOS bit 44
LVDS or 2.5-V LVDS RX bit 9 or CMOS bit 45
LVDS or 2.5-V LVDS TX bit 9n or CMOS bit 46
LVDS or 2.5-V LVDS RX bit 9n or CMOS bit 47
LVDS or 2.5-V LVDS TX bit 10 or CMOS bit 48
LVDS or 2.5-V LVDS RX bit 10 or CMOS bit 49
LVDS or 2.5-V LVDS TX bit 10n or CMOS bit 50
LVDS or 2.5-V LVDS RX bit 10n or CMOS bit 51
LVDS or 2.5-V LVDS TX bit 11 or CMOS bit 52
LVDS or 2.5-V LVDS RX bit 11 or CMOS bit 53
LVDS or 2.5-V LVDS TX bit 11n or CMOS bit 54
LVDS or 2.5-V LVDS RX bit 11n or CMOS bit 55
LVDS or 2.5-V LVDS TX bit 12 or CMOS bit 56
LVDS or 2.5-V LVDS RX bit 12 or CMOS bit 57
LVDS or 2.5-V LVDS TX bit 12n or CMOS bit 58
LVDS or 2.5-V LVDS RX bit 12n or CMOS bit 59
LVDS or 2.5-V LVDS TX bit 13 or CMOS bit 60
LVDS or 2.5-V LVDS RX bit 13 or CMOS bit 61
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Components and Interfaces
2–31
Table 2–24. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board
Reference (J1)
151
152
155
156
145
146
149
150
139
140
143
144
133
134
137
138
157
158
160
Schematic Signal Name
HSMA_TX_D_N13
HSMA_RX_D_N13
HSMA_TX_D_P14
HSMA_RX_D_P14
HSMA_TX_D_N14
HSMA_RX_D_N14
HSMA_TX_D_P15
HSMA_RX_D_P15
HSMA_TX_D_N15
HSMA_RX_D_N15
HSMA_TX_D_P16
HSMA_RX_D_P16
HSMA_TX_D_N16
HSMA_RX_D_N16
HSMA_CLK_OUT_P2
HSMA_CLK_IN_P2
HSMA_CLK_OUT_N2
HSMA_CLK_IN_N2
HSMA_PRSNTn
Cyclone V GX
Pin Number
E25
H20
A25
L14
A28
G21
E26
J20
C26
G23
B27
H21
C25
L19
C27
G22
A24
L13
L16
I/O Standard Description
LVDS or 2.5-V LVDS TX bit 13n or CMOS bit 62
LVDS or 2.5-V LVDS RX bit 13n or CMOS bit 63
LVDS or 2.5-V LVDS TX bit 14 or CMOS bit 64
LVDS or 2.5-V LVDS RX bit 14 or CMOS bit 65
LVDS or 2.5-V LVDS TX bit 14n or CMOS bit 66
LVDS or 2.5-V LVDS RX bit 14n or CMOS bit 67
LVDS or 2.5-V LVDS TX bit 15 or CMOS bit 68
LVDS or 2.5-V LVDS RX bit 15 or CMOS bit 69
LVDS or 2.5-V LVDS TX bit 15n or CMOS bit 70
LVDS or 2.5-V LVDS RX bit 15n or CMOS bit 71
LVDS or 2.5-V LVDS TX bit 16 or CMOS bit 72
LVDS or 2.5-V LVDS RX bit 16 or CMOS bit 73
LVDS or 2.5-V LVDS TX bit 16n or CMOS bit 74
LVDS or 2.5-V LVDS RX bit 16n or CMOS bit 75
LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 76
LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 77
LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 78
LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 79
2.5-V CMOS HSMC port A presence detect
SDI Video Output/Input
The SDI video port consists of a LMH0303 cable driver and a LMH0384 cable equalizer. The PHY devices from National Semiconductor interface to single-ended
75-
Ω SMB connectors.
The cable driver supports operation at 270 Mbit standard definition (SD), 1.5 Gbit high definition (HD), and 2.97 Gbit dual-link HD modes. Control signals are allowed for SD and HD modes selections, as well as device enable. The reference clock of the device is 148.5 MHz and matches the incoming signals to within 50 ppm using the UP and DN voltage control lines to the voltage-controlled crystal oscillator (VCXO).
Table 2–25 lists the supported output standards for the SD and HD input.
Table 2–25. Supported Output Standards for SD and HD Input
SD_HD Input
0
1
Supported Output Standards
SMPTE 424M, SMPTE 292M
SMPTE 259M
Faster
Slower
Rise TIme
f
For more information about the application circuit of the cable driver, refer to the cable driver data sheet in www.national.com
.
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–32 Chapter 2: Board Components
Components and Interfaces
Table 2–26 summarizes the SDI video output interface pin assignments, signal names, and functions.
Table 2–26. SDI Video Output Interface Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (U1)
7
8
4
6
1
2
10
11
12
13
Schematic
Signal Name
SDI_TX_P
SDI_TX_N
SDI_TX_RSET
SDI_TX_EN
SDI_SDA
SDI_SCL
SDI_TX_SD_HDN
SDI_TXDRV_N
SDI_TXDRV_P
SDI_FAULT
Cyclone V GX
Pin Number
V4
V3
—
AJ1
R20
T21
AF7
—
—
F25
I/O Standard Description
1.5-V PCML Serial data input P
1.5-V PCML Serial data input N
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
Output swing set resistor
Output driver enable
Cable driver I
2
C bus
Cable driver I
2
C bus
High-definition select
Serial data
Serial data
Data transmission fault
The cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD, and 2.97 Gbit dual-link HD modes. Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or auto-mute signal interface.
Table 2–27 lists the cable equalizer lengths.
Table 2–27. SDI Cable Equalizer Lengths
Data Rate (Mbps)
270
1485
2970
Cable Type
Belden 1694A
Maximum Cable Length (m)
400
140
120
Figure 2–9 shows the SDI cable equalizer, which is an excerpt from the LMH0384 cable equalizer data sheet. On this development board, the output is a single-ended output, with the negative channel driving a load local to the board.
Figure 2–9. SDI Cable Equalizer
Coaxial Cable
75
Ω
1.0
μF
1.0
μF
SDI
SDI
SDI Adaptive
Cable Equalizer
SDO
SDO
To FPGA
5.6 nH
75
Ω
37.4
Ω
MUTE
MUTE
REF
BYPASS
CD
MUTE
MUTE
REF
BYPASS CD
1.0
μF
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Memory
2–33
Table 2–28 summarizes the SDI video input interface pin assignments, signal names, and functions.
Table 2–28. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (U4)
7
10
11
14
Schematic
Signal Name
SDI_RX_BYPASS
SDI_RX_N
SDI_RX_P
SDI_RX_EN
Cyclone V GX
Pin Number
AF10
W1
W2
AE10
I/O Standard
2.5-V
1.5-V PCML
1.5-V PCML
2.5-V
Description
Equalizer bypass enable
Serial data output N
Serial data output P
Device enable
Memory
■
■
■
This section describes the development board’s memory interface support and also their signal names, types, and connectivity relative to the Cyclone V GX. The development board has the following memory interfaces:
DDR3 SDRAM
Synchronous SRAM
Synchronous flash f
For more information about the memory interfaces, refer to the following documents:
■
■
Timing Analysis
section in the External Memory Interface Handbook.
DDR, DDR2, and DDR3 SDRAM Design Tutorials
section in the External Memory
Interface Handbook.
DDR3 SDRAM
The development board supports four 16Mx16x8 and two16Mx8x8 DDR3 SDRAM interfaces for very high-speed sequential memory access. The DDR3 SDRAM has two independent interfaces:
■ DDR3A x32 interface using a hard memory controller (vertical I/O banks on the bottom edge of the FPGA).
■ DDR3B x32 interface using a soft memory controller (horizontal I/O banks on the right edge of the FPGA).
Each 32-bit data bus comprises of two x16 devices and one x8 device for ECC support.
With a soft memory controller, this memory interface runs at a target frequency of
333 MHz for a maximum theoretical bandwidth of over 21.31 Gbps. The maximum frequency for this DDR3 device is 667 MHz with a CAS latency of 9.
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–34 Chapter 2: Board Components
Memory
lists the DDR3A pin assignments, signal names, and functions. The signal names and types are relative to the Cyclone V GX in terms of I/O setting and direction.
Table 2–29. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board Reference
Schematic
Signal Name
Cyclone V GX
Pin Number
I/O Standard Description
DDR3 x16 (U21)
L7
R7
N7
T3
R8
R2
T8
R3
N3
P7
P3
N2
P8
P2
M2
N8
M3
K3
K9
J7
K7
F2
G2
F8
H3
A7
E3
H8
F7
H7
L2
E7
D3
DDR3A_A0
DDR3A_A1
DDR3A_A2
DDR3A_A3
DDR3A_A4
DDR3A_A5
DDR3A_A6
DDR3A_A7
DDR3A_A8
DDR3A_A9
DDR3A_A10
DDR3A_A11
DDR3A_A12
DDR3A_A13
DDR3A_BA0
DDR3A_BA1
DDR3A_BA2
DDR3A_CASN
DDR3A_CKE
DDR3A_CLK_P
DDR3A_CLK_N
DDR3A_CSN
DDR3A_DM0
DDR3A_DM1
DDR3A_DQ0
DDR3A_DQ1
DDR3A_DQ2
DDR3A_DQ3
DDR3A_DQ4
DDR3A_DQ5
DDR3A_DQ6
DDR3A_DQ7
DDR3A_DQ8
AJ12
AK12
AH11
AH12
AG13
AG14
AK10
AK11
AF11
AG11
AJ8
AK8
AJ7
AK7
AH9
AH10
AJ10
AF9
AK18
Y13
AA14
Y12
AE15
AH19
AF15
AE16
AJ14
AH15
AE17
AD17
AJ15
AF14
AK17
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Row address select
Column address select
Differential output clock
Differential output clock
Chip select
Write mask byte lane
Write mask byte lane
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 1
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Memory
DDR3 x16 (U22)
R7
N7
T3
M2
R2
T8
R3
L7
N8
M3
K3
N2
P8
P2
R8
N3
P7
P3
Table 2–29. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board Reference
C2
B8
C8
C3
A3
D7
A2
F3
G3
C7
B7
K1
J3
T2
L3
L8
Schematic
Signal Name
DDR3A_DQ9
DDR3A_DQ10
DDR3A_DQ11
DDR3A_DQ12
DDR3A_DQ13
DDR3A_DQ14
DDR3A_DQ15
DDR3A_DQS_P0
DDR3A_DQS_N0
DDR3A_DQS_P1
DDR3A_DQS_N1
DDR3A_ODT
DDR3A_RASN
DDR3A_RESETN
DDR3A_WEN
DDR3A_ZQ01
Cyclone V GX
Pin Number
AK16
AG17
AJ18
AG16
AF16
AJ19
AH20
Y16
AA16
Y17
Y18
AH14
AG9
AK21
AK5
—
I/O Standard
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Description
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data strobe P byte lane 0
Data strobe N byte lane 0
Data strobe P byte lane 1
Data strobe N byte lane 1
On-die termination enable
Row address select
Reset
Write enable
ZQ impedance calibration
DDR3A_A0
DDR3A_A1
DDR3A_A2
DDR3A_A3
DDR3A_A4
DDR3A_A5
DDR3A_A6
DDR3A_A7
DDR3A_A8
DDR3A_A9
DDR3A_A10
DDR3A_A11
DDR3A_A12
DDR3A_A13
DDR3A_BA0
DDR3A_BA1
DDR3A_BA2
DDR3A_CASN
AJ12
AK12
AH11
AH12
AG13
AG14
AK10
AK11
AF11
AG11
AJ8
AK8
AJ7
AK7
AH9
AH10
AJ10
AF9
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Row address select
2–35
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–36 Chapter 2: Board Components
Memory
Table 2–29. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board Reference
H7
H8
A2
C2
E3
F7
H3
G2
E7
D3
F2
F8
K9
K7
J7
L2
D7
A7
A3
C3
B8
C8
F3
G3
C7
B7
K1
J3
T2
L3
L8
DDR3 x8 (U23)
K3
L7
L3
Schematic
Signal Name
DDR3A_CKE
DDR3A_CLK_P
DDR3A_CLK_N
DDR3A_CSN
DDR3A_DM2
DDR3A_DM3
DDR3A_DQ16
DDR3A_DQ17
DDR3A_DQ18
DDR3A_DQ19
DDR3A_DQ20
DDR3A_DQ21
DDR3A_DQ22
DDR3A_DQ23
DDR3A_DQ24
DDR3A_DQ25
DDR3A_DQ26
DDR3A_DQ27
DDR3A_DQ28
DDR3A_DQ29
DDR3A_DQ30
DDR3A_DQ31
DDR3A_DQS_P2
DDR3A_DQS_N2
DDR3A_DQS_P3
DDR3A_DQS_N3
DDR3A_ODT
DDR3A_RASN
DDR3A_RESETN
DDR3A_WEN
DDR3A_ZQ2
DDR3A_A0
DDR3A_A1
DDR3A_A2
Cyclone V GX
Pin Number
AJ20
AK22
AF19
AF18
AH21
AK23
AG19
AG18
AK18
Y13
AA14
Y12
AJ23
AJ27
AE18
AD18
AH24
AK25
AE20
AD19
AG24
AK26
Y20
AA20
AB19
AC19
AH14
AG9
AK21
AK5
—
AJ12
AK12
AH11
I/O Standard
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Description
Column address select
Differential output clock
Differential output clock
Chip select
Write mask byte lane
Write mask byte lane
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data strobe P byte lane 2
Data strobe N byte lane 2
Data strobe P byte lane 3
Data strobe N byte lane 3
On-die termination enable
Row address select
Reset
Write enable
ZQ impedance calibration
Address bus
Address bus
Address bus
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Memory
Table 2–29. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board Reference
E3
C8
E7
B3
G7
F7
H2
B7
D2
C7
E8
C2
K8
J3
G3
G9
M7
K7
N3
J2
M2
N8
M3
H7
K2
L8
L2
M8
D3
C3
G1
F3
N2
H3
H8
Schematic
Signal Name
DDR3A_A3
DDR3A_A4
DDR3A_A5
DDR3A_A6
DDR3A_A7
DDR3A_A8
DDR3A_A9
DDR3A_A10
DDR3A_A11
DDR3A_A12
DDR3A_A13
DDR3A_BA0
DDR3A_BA1
DDR3A_BA2
DDR3A_CASN
DDR3A_CKE
DDR3A_CLK_N
DDR3A_CLK_P
DDR3A_CSN
DDR3A_DM4
DDR3A_DQ32
DDR3A_DQ33
DDR3A_DQ34
DDR3A_DQ35
DDR3A_DQ36
DDR3A_DQ37
DDR3A_DQ38
DDR3A_DQ39
DDR3A_DQS_N4
DDR3A_DQS_P4
DDR3A_ODT
DDR3A_RASN
DDR3A_RESETN
DDR3A_WEN
DDR3A_ZQ05
Cyclone V GX
Pin Number
Y13
AA14
Y12
AG23
AG21
AF20
AK27
AH26
AG22
AF21
AE22
AH22
AK8
AJ7
AK7
AH9
AH10
AJ10
AF9
AK18
AH12
AG13
AG14
AK10
AK11
AF11
AG11
AJ8
AD20
AC21
AH14
AG9
AK21
AK5
—
I/O Standard
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Description
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Row address select
Column address select
Differential output clock
Differential output clock
Chip select
Write mask byte lane
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data strobe P byte lane 4
Data strobe N byte lane 4
On-die termination enable
Row address select
Reset
Write enable
ZQ impedance calibration
2–37
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–38 Chapter 2: Board Components
Memory
lists the DDR3B pin assignments, signal names, and functions. The signal names and types are relative to the Cyclone V GX in terms of I/O setting and direction.
Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board Reference
Schematic
Signal Name
Cyclone V GX
Pin Number
I/O Standard Description
DDR3 x16 (U6)
L7
R7
N7
T3
R8
R2
T8
R3
N3
P7
P3
N2
P8
P2
M2
N8
M3
K3
K9
J7
K7
H3
H8
G2
H7
D7
E3
F7
F2
F8
L2
E7
D3
DDR3B_A0
DDR3B_A1
DDR3B_A2
DDR3B_A3
DDR3B_A4
DDR3B_A5
DDR3B_A6
DDR3B_A7
DDR3B_A8
DDR3B_A9
DDR3B_A10
DDR3B_A11
DDR3B_A12
DDR3B_A13
DDR3B_BA0
DDR3B_BA1
DDR3B_BA2
DDR3B_CASN
DDR3B_CKE
DDR3B_CLK_P
DDR3B_CLK_N
DDR3B_CSN
DDR3B_DM0
DDR3B_DM1
DDR3B_DQ0
DDR3B_DQ1
DDR3B_DQ2
DDR3B_DQ3
DDR3B_DQ4
DDR3B_DQ5
DDR3B_DQ6
DDR3B_DQ7
DDR3B_DQ8
Y30
R28
AA29
W29
U23
AA30
R23
AC30
T23
AB29
R30
R26
T25
AD29
W30
T24
V30
T30
L28
P22
P23
U29
C29
D29
D30
C30
F29
K22
E28
K21
G29
L23
J23
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Row address select
Column address select
Differential output clock
Differential output clock
Chip select
Write mask byte lane
Write mask byte lane
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 0
Data bus byte lane 1
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Memory
DDR3 x16 (U15)
R7
N7
T3
M2
R2
T8
R3
L7
N8
M3
K3
N2
P8
P2
R8
N3
P7
P3
Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board Reference
A2
B8
A3
C3
C8
C2
A7
F3
G3
C7
B7
K1
J3
T2
L3
L8
Schematic
Signal Name
DDR3B_DQ9
DDR3B_DQ10
DDR3B_DQ11
DDR3B_DQ12
DDR3B_DQ13
DDR3B_DQ14
DDR3B_DQ15
DDR3B_DQS_P0
DDR3B_DQS_N0
DDR3B_DQS_P1
DDR3B_DQS_N1
DDR3B_ODT
DDR3B_RASN
DDR3B_RESETN
DDR3B_WEN
DDR3B_ZQ01
Cyclone V GX
Pin Number
D28
A29
H25
H24
H26
B28
D27
N21
M22
P20
N20
V29
T29
AB27
T28
—
I/O Standard
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Description
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data bus byte lane 1
Data strobe P byte lane 0
Data strobe N byte lane 0
Data strobe P byte lane 1
Data strobe N byte lane 1
On-die termination enable
Row address select
Reset
Write enable
ZQ impedance calibration
DDR3B_A0
DDR3B_A1
DDR3B_A2
DDR3B_A3
DDR3B_A4
DDR3B_A5
DDR3B_A6
DDR3B_A7
DDR3B_A8
DDR3B_A9
DDR3B_A10
DDR3B_A11
DDR3B_A12
DDR3B_A13
DDR3B_BA0
DDR3B_BA1
DDR3B_BA2
DDR3B_CASN
Y30
R28
AA29
W29
U23
AA30
R23
AC30
T23
AB29
R30
R26
T25
AD29
W30
T24
V30
T30
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Row address select
2–39
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–40 Chapter 2: Board Components
Memory
Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board Reference
G2
H7
D7
C3
F2
F8
H3
H8
E7
D3
E3
F7
K9
K7
J7
L2
C8
C2
A7
A2
B8
A3
F3
G3
C7
B7
K1
J3
T2
L3
L8
DDR3 x8 (U19)
K3
L7
L3
Schematic
Signal Name
DDR3B_CKE
DDR3B_CLK_P
DDR3B_CLK_N
DDR3B_CSN
DDR3B_DM2
DDR3B_DM3
DDR3B_DQ16
DDR3B_DQ17
DDR3B_DQ18
DDR3B_DQ19
DDR3B_DQ20
DDR3B_DQ21
DDR3B_DQ22
DDR3B_DQ23
DDR3B_DQ24
DDR3B_DQ25
DDR3B_DQ26
DDR3B_DQ27
DDR3B_DQ28
DDR3B_DQ29
DDR3B_DQ30
DDR3B_DQ31
DDR3B_DQS_P2
DDR3B_DQS_N2
DDR3B_DQS_P3
DDR3B_DQS_N3
DDR3B_ODT
DDR3B_RASN
DDR3B_RESETN
DDR3B_WEN
DDR3B_ZQ2
DDR3B_A0
DDR3B_A1
DDR3B_A2
Cyclone V GX
Pin Number
K27
F26
J30
K25
J27
H29
J28
F30
H30
L30
J29
G26
L28
P22
P23
U29
G27
L25
L29
N27
K26
L26
N22
M23
N24
N25
V29
T29
AB27
T28
—
Y30
R28
AA29
I/O Standard
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Description
Column address select
Differential output clock
Differential output clock
Chip select
Write mask byte lane
Write mask byte lane
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 2
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data strobe P byte lane 2
Data strobe N byte lane 2
Data strobe P byte lane 3
Data strobe N byte lane 3
On-die termination enable
Row address select
Reset
Write enable
ZQ impedance calibration
Address bus
Address bus
Address bus
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Memory
Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board Reference
B3
C7
C2
C8
G7
F7
H2
B7
E3
E8
D2
E7
K8
J3
G3
G9
M7
K7
N3
J2
M2
N8
M3
H7
K2
L8
L2
M8
D3
C3
G1
F3
N2
H3
H8
Schematic
Signal Name
DDR3B_A3
DDR3B_A4
DDR3B_A5
DDR3B_A6
DDR3B_A7
DDR3B_A8
DDR3B_A9
DDR3B_A10
DDR3B_A11
DDR3B_A12
DDR3B_A13
DDR3B_BA0
DDR3B_BA1
DDR3B_BA2
DDR3B_CASN
DDR3B_CKE
DDR3B_CLK_N
DDR3B_CLK_P
DDR3B_CSN
DDR3B_DM4
DDR3B_DQ32
DDR3B_DQ33
DDR3B_DQ34
DDR3B_DQ35
DDR3B_DQ36
DDR3B_DQ37
DDR3B_DQ38
DDR3B_DQ39
DDR3B_DQS_N4
DDR3B_DQS_P4
DDR3B_ODT
DDR3B_RASN
DDR3B_RESETN
DDR3B_WEN
DDR3B_ZQ05
Cyclone V GX
Pin Number
P28
K28
M27
P30
P22
P23
U29
P29
N29
M29
R27
N30
R26
T25
AD29
W30
T24
V30
T30
L28
W29
U23
AA30
R23
AC30
T23
AB29
R30
R25
P25
V29
T29
AB27
T28
—
I/O Standard
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Differential 1.5-V SSTL
Class I
Differential 1.5-V SSTL
Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
1.5-V SSTL Class I
Description
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Row address select
Column address select
Differential output clock
Differential output clock
Chip select
Write mask byte lane
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data strobe P byte lane 4
Data strobe N byte lane 4
On-die termination enable
Row address select
Reset
Write enable
ZQ impedance calibration
2–41
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–42 Chapter 2: Board Components
Memory
Synchronous SRAM
The development board supports a 18-MB standard synchronous SRAM for instruction and data storage with low-latency random access capability. The device has a 1024K x 18-bits interface. This device is part of the shared FSM bus that connects to the flash memory, SRAM, and MAX V CPLD 5M2210 System Controller.
The device speed is 200 MHz single-data-rate. There is no minimum speed for this device. The theoretical bandwidth of this interface is 3.2 Gbps for continuous bursts.
The read latency for any address is two clocks while the write latency is one clock.
lists the SSRAM pin assignments, signal names, and functions.
Table 2–31. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board
Reference (U37)
63
68
69
39
58
59
62
82
80
49
81
50
48
100
99
45
35
32
33
34
47
43
46
86
87
37
36
44
42
Schematic
Signal Name
FLASH_OEN
FLASH_WEN
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
Cyclone V GX
Pin Number
H9
E13
F13
C6
C7
A6
B6
D8
E8
F8
G9
D6
D7
A2
A3
J10
K10
E6
E7
G7
G8
F6
G6
M8
J15
N10
N9
M12
M11
I/O Standard
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
Description
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Output enable
Write enable
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Memory
2–43
Table 2–31. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Board
Reference (U37)
83
93
94
97
8
9
85
84
19
18
12
13
72
73
23
22
92
98
89
88
31
64
Schematic
Signal Name
FSM_D6
FSM_D7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
SRAM_ADSCN
SRAM_ADSPN
SRAM_ADVN
SRAM_BWAN
SRAM_BWBN
SRAM_CE2
SRAM_CE3N
SRAM_CEN
SRAM_CLK
SRAM_GWN
SRAM_MODE
SRAM_ZZ
Cyclone V GX
Pin Number
K13
P10
N11
—
A11
B11
P12
J13
A9
A10
C10
D9
A8
B7
B8
C9
—
K11
N12
—
—
—
I/O Standard
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
Description
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Address status controller
Address status processor
Adress valid
Byte write select
Byte write select
Chip enable 2
Chip enable 3
Chip enable 1
Clock
Global write enable
Burst sequence selection
Power sleep mode
Flash
The development board supports a 512-MB CFI-compatible synchronous flash device for non-volatile storage of FPGA configuration data, board information, test application data, and user code space. This device is part of the shared FSM bus that connects to the flash memory, SSRAM, and MAX V CPLD 5M2210 System Controller.
This 16-bit data memory interface can sustain burst read operations at up to 52 MHz for a throughput of 832 Mbps per device. The write performance is 270 µs for a single word buffer while the erase time is 800 ms for a 128 K array block.
lists the flash pin assignments, signal names, and functions. The signal names and types are relative to the Cyclone V GX in terms of I/O setting and direction.
Table 2–32. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)
Board
Reference (U18)
F6
B4
Schematic Signal Name
FLASH_ADVN
FLASH_CEN
Cyclone V GX
Pin Number
H15
L10
I/O Standard
2.5-V
2.5-V
Description
Address valid
Chip enable
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–44 Chapter 2: Board Components
Memory
Board
Reference (U18)
G1
H8
B6
B8
B7
C7
C8
A8
C5
D7
D8
A7
D3
C4
A5
B5
E5
G5
G6
F2
E2
G3
E4
C2
A3
B3
C3
C1
D1
D2
A2
G8
C6
A1
B1
E6
F8
F7
D4
Schematic Signal Name
FLASH_CLK
FLASH_OEN
FLASH_RDYBSYN
FLASH_RESETN
FLASH_WEN
FLASH_WPN
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
FSM_A26
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
Table 2–32. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Cyclone V GX
Pin Number
H7
J7
A4
A5
F8
G9
H9
J9
A2
A3
D8
E8
E6
E7
D6
D7
E13
F13
C6
C7
A6
B6
A8
F6
G6
J10
K10
M12
M11
G7
G8
J15
—
N10
N9
M9
M8
L11
L9
I/O Standard
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
Description
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Clock
Output enable
Ready
Reset
Write enable
Write protect
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Power Supply
2–45
Table 2–32. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)
Board
Reference (U18)
F4
F5
H5
G7
H7
E1
E3
F3
E7
Schematic Signal Name
FSM_D7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
Cyclone V GX
Pin Number
A10
C10
D9
A11
B7
B8
C9
A9
B11
I/O Standard
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Description
Power Supply
You can power up the development board either from a laptop-style DC power input or from the PCI Express edge connector. The input voltage must be in the range of
14 V to 20 V. The DC voltage is then stepped down to various power rails used by the board components and installed into the HSMC connectors.
outlines the allowable power inputs.
Table 2–33. Power Inputs
Power Source
Laptop-style DC input
25-W PCI Express edge connector
75-W PCI Express edge connector
Voltage (V)
15.0
3.3
12.0
3.3
12.0
Current (A)
4.3
3.0
2.1
3.0
5.5
Maximum Wattage (W)
65
9
16
9
66
An on-board multi-channel analog-to-digital converter (ADC) measures the current for several specific board rails.
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–46 Chapter 2: Board Components
Power Supply
Power Distribution System
Figure 2–10 shows the power distribution system on the development board.
Regulator inefficiencies and sharing are reflected in the currents shown, which are conservative absolute maximum levels.
Figure 2–10. Power Distribution System
DC INPUT
14 V - 20 V
LTC3855
3.3 V (5A) and
12 V (7A)
Dual Switcher
(5.0 A)
+/- 5%
3.3 V
2.8 A
PCI Express x8
Gold Finger
12 V
3.3 V
LTC4352 x2
3.3 V
12 V
3.2 A
12 V
LTC4352 x2
LEGEND
Board Main Power Rails
Cyclone V Power
HSMC
MAX II VCCIO
USB-Blaster II
VCC
SDI Cable Driver/Equalizer
HSMC
Fan
LTC3009
5.37 V LDO
(20 mA)
+/- 5%
5.37 V
0.3 mA
LTC3009
5.0 V LDO
(9.12 mA)
+/- 5%
5.0 V
9.12 mA
LTC3855 Channel 1
1.1 V Switcher
(6.0 A)
+/- 30 mV
1.1 V
6.0 A
Power Monitor
SPI Level Shifter
LCD
Filter
Filter
LTC3855 Channel 2
1.5 V Switcher
(6.0 A)
+/- 5%
1.5 V
6.0 A
2.5 V
3.5 A
LTC3605 Channel 2
2.5 V Switcher
(5.0 A)
+/- 5%
Filter
VCC Core
VCCE_GXB
VCCL_GXB
VCCIO
DDR3 SDRAM x6
VCCIO
VCCPD
VCCPGM
VCCAUX
VCCH_GXB
VCCA_FPLL
12 V
LTC3603
2.5 V Switcher
(2.5 A)
+/- 5%
2.5 V
2.4 A
LTC3025-1
1.8 V LDO
(115 mA)
+/- 5%
LTC3025-1
1.0 V LDO
(304 mA)
+/- 5%
TPS5110DGQ
0.75 V LDO
(739 mA)
+/- 5%
Ethernet PHY
SSRAM
Flash
MAX V VCCIO
MAX II VCCIO
MAX II VCCint
Oscillators
Flash
MAX V VCCint
Ethernet PHY
DDR3 VTT
Con Cell
SKT
3 V
FPGA VCCBAT
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Chapter 2: Board Components
Power Supply
2–47
Power Measurement
There are eight power supply rails that have on-board current sense capabilities using
24-bit differential ADC devices. Precision sense resistors split the ADC devices and rails from the primary supply plane for the ADC to measure current. A SPI bus connects these ADC devices to the MAX V CPLD 5M2210 System Controller.
shows the block diagram for the power measurement circuitry.
Figure 2–11. Power Measurement Circuit
Embedded
USB-Blaster II
USB
PHY
To User PC
Feedback
EPM570
Power Supply Load #0-7
Supply
#0-7
JTAG Chain
R
SENSE
SPI Bus
MAX V CPLD
5M2210
System
Controller
Cyclone V GX
FPGA
E
RW
14-pin
2x16
RS
D(0:7)
Character
LCD
8 Ch.
SCK
DSI
DSO
CSn
lists the targeted rails. The schematic signal name column specifies the name of the rail being measured while the device pin column specifies the devices attached to the rail.
Table 2–34. Power Measurement Rails
Channel Schematic Signal Name
1
2
3
4
5
6
C5_VCC_VCCE_GXB_VCCL_GXB
C5_VCCAUX_VCCA_FPLL
C5_VCCIO_VCCPD_PGM
C5_VCCIO_1.5V
C5_VCCBAT
C5_VCCH_GXBL
Voltage (V)
1.1
1.1
1.1
2.5
2.5
2.5
2.5
2.5
1.5
3.0
2.5
Device Pin
VCC
VCCE_GXB
VCCL_GXB
VCCA_FPLL
VCC_AUX
VCCPD
VCCPGM
VCCIO_3A,
VCCIO_5A,
VCCIO_7A,
VCCIO_8A
VCCIO_6A,
VCCIO_5B,
VCCIO_4A,
VCCIO_3B
VCCBAT
VCCH_GXB
Description
FPGA core and periphery power
XCVR analog transmit
XCVR analog clock network
PLL analog power
Auxiliary
I/O pre-drivers
Configuration I/O
VCC I/O banks 3, 7, and 8
VCCIO bank (DDR3)
Battery power
XCVR block level transmit buffers
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
2–48 Chapter 2: Board Components
Statement of China-RoHS Compliance
Statement of China-RoHS Compliance
lists hazardous substances included with the kit.
Table 2–35. Table of Hazardous Substances’ Name and Concentration
Notes
Part Name
Lead
(Pb)
Cadmium
(Cd)
Hexavalent
Chromium
(Cr6+)
Mercury
(Hg)
Polybrominated biphenyls (PBB)
Polybrominated diphenyl Ethers
(PBDE)
Cyclone V GX development board
15 V power supply
Type A-B USB cable
User guide
X*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the
SJ/T11363-2006 standard.
(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
3. Board Components Reference
This chapter lists the component reference and manufacturing information of all the components on the Cyclone V GX FPGA development board.
Table 3–1. Component Reference and Manufacturing Information
Board
Reference
Component Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U11
FPGA, Cyclone V GX F1152, 150K
LEs, leadfree
U12
MAX V CPLD 5M2210 System
Controller
High-Speed USB peripheral controller U16
D1–D7,
D12–D15,
D17–D22,
D24–D28
Green LED
D8–D10 Yellow LED
D16
D23
Red LED
Blue LED
Altera
Altera
Corporation 5CGXFC7D6F31C7NES
Corporation
Cypress
Lumex Inc.
SW2–SW5 Four-position DIP switch
Lumex Inc.
Lumex Inc.
Lumex Inc.
C&K Components/
ITT Industries
S1, S4, S6,
S7
Push button Panasonic
S3–S5
U25
X2
X1
X4
J18
U10
J11
J1
U1
Push button
Dawning Precision
Co.
Programmable LVDS quad-clock
125M, 409.6M, 156.25M, 100M defaults
148.50 MHz LVDS voltage controlled crystal oscillator
100 MHz crystal oscillator, ±50 ppm,
CMOS, 2.5 V
50 MHz crystal oscillator, ±50 ppm,
CMOS, 2.5 V
2×7 pin LCD socket strip
2×16 character LCD, 5×8 dot matrix
Silicon Labs
Silicon Labs
Silicon Labs
Silicon Labs
Ethernet PHY BASE-T device
Samtec
Lumex Inc.
Marvell
Semiconductor
RJ-45 connector, 10/100/1000 Mbps Wurth Elektronik
HSMC, custom version of QSH-DP family high-speed socket.
Samtec
3-Gbps HD/SD SDI cable driver with cable detect
National
Semiconductor
5M2210ZF256C4N
CY7C68013A
SML-LXT0805GW-TR
SML-LXT0805SYW-TR
SML-LXT0805IW-TR
SML-LX0805USBC-TR
TDA04H0SB1
EVQPAC07K
TS-A02SA-2-S100
Si5338A-A01343-GM
571FDB000159DG
510GBA100M000BAGx
510GBA50M0000BAGx
TSM-107-07-G-D
LCM-S01602DSR/C
88E1111-B2-
CAA1C000
7499111001A
ASP-122953-01
LMH0303SQx www.altera.com
www.altera.com
www.cypress.com
www.lumex.com
www.lumex.com
www.lumex.com
www.lumex.com
www.ittcannon.com
www.panasonic.com
www.dawning2.com.tw
www.silabs.com
www.silabs.com
www.silabs.com
www.silabs.com
www.samtec.com
www.lumex.com
www.marvell.com
www.we-online.com
www.samtec.com
www.national.com
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
3–2 Chapter 3: Board Components Reference
Table 3–1. Component Reference and Manufacturing Information
Board
Reference
Component
U4
3-Gbps HD/SD SDI adaptive cable equalizer
2x7 debug header J14
U6, U15,
U21, U22
16M×16×8, 128-MB DDR3 SDRAM
U19, U23 16M×8×8, 128-MB DDR3 SDRAM
U37
1024K×18 bit 18-MB synchronous
SRAM
U18
U17
512-MB synchronous flash
16-channel differential 24-bit ADC
Manufacturer
National
Semiconductor
Samtec
Micron
Micron
Integrated Silicon
Solution, Inc.
Numonyx
Linear Technology
Manufacturing
Part Number
LMH0384SQ
TSW-107-07
MT41J128M16
MT41J128M8
IS61VPS102418A-
250TQL
PC28F512P30BF
LTC2418CGN#PBF
Manufacturer
Website
www.national.com
www.samtec.com
www.micron.com
www.micron.com
www.issi.com
www.numonyx.com
www.linear.com
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
Additional Information
This chapter provides additional information about the document and Altera.
Document Revision History
The following table lists the revision history for this document.
Date
May 2013
October 2012
September 2012
Version Changes
1.2
■
Revised the device part number to 5CGXFC7D6F31C7NES.
■
Revised the default settings in Table 2–8
and
■
Updated the device pin numbers in
1.1
■
Revised the power inputs in
■
Updated
1.0
Initial release.
.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the following table.
Technical support
Technical training
Product literature
Nontechnical support (general)
(software licensing)
Contact Method
Website
Website
Website
Note to Table:
(1) You can also contact your local Altera sales office or sales representative.
Address
www.altera.com/support www.altera.com/training [email protected]
www.altera.com/literature [email protected]
Typographic Conventions
The following table shows the typographic conventions this document uses.
Visual Cue
Bold Type with Initial Capital
Letters bold type
Meaning
Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.
Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file.
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
Info–2 Additional InformationAdditional Information
Typographic Conventions
Visual Cue Meaning
Italic Type with Initial Capital Letters
Indicate document titles. For example, Stratix IV Design Guidelines.
Indicates variables. For example, n + 1.
italic type
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Initial Capital Letters
“Subheading Title”
Indicate keyboard keys and menu names. For example, the Delete key and the
Options menu.
Quotation marks indicate references to sections in a document and titles of
Quartus II Help topics. For example, “Typographic Conventions.”
Courier type
Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi
, and input. The suffix n denotes an active-low signal. For example, resetn.
Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.
Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI).
An angled arrow instructs you to press the Enter key.
r
1., 2., 3., and a., b., c., and so on
■
■ ■
1 h f m c w
Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.
Bullets indicate a list of items when the sequence of the items is not important.
The hand points to information that requires special attention.
The question mark directs you to a software help system with related information.
The feet direct you to another document or website with related information.
The multimedia icon directs you to a related multimedia presentation.
A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.
A warning calls attention to a condition or possible situation that can cause you injury.
The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.
The feedback icon allows you to submit feedback to Altera about the document.
Methods for collecting feedback vary as appropriate for each document.
Cyclone V GX FPGA Development Board
Reference Manual
May 2013 Altera Corporation
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