M6800

2.0 MHz
1.5 MHz
MC68AOO·MC68BOO
MPH
Advance Inforlll.ation
MC68A21· MC68B21
PIA
1.5 AND 2.0 MHz COMPONENTS
FOR THE M6800 MICROCOMPUTER SYSTEM
MC68A50·MC68B50
ACIA
The eight devices described in this data sheet extend the operating
frequency of the M6800 Microcomputer Family. The block diagrams
and device operation are the same as for the basic M6800-series
components.
•
Fully Hardware and Software Compatible with the
M6800 Family
•
Power Dissipation Approximately 20% Lower Than on
Standard MC6800 Series
•
Clock Specification Improved for Reduced Complexity of
Clock Generator/Driver Circuitry
•
The MC6821 and its higher-frequency versions provide drive
capability of two TTL loads on all A- and B-side buffers,
improving the drive capability of the MC6820.
MCM68AIO·MCM68BIO
RAM
MOS
(N-eHANNEL, SILICON-GATE)
MICROPROCESSOR SYSTEM
COMPONENTS
M6800 MICROCOMPUTER FAMILY
BLOCK DIAGRAM
Microprocessor
MC68AOO
MC68BOO
P SUFFIX
PLASTIC PACKAGE
CASE 711
NOT SHOWN:
L SUFFIX
CERAMIC PACKAGE
CASE 715
Address
Bus
This is advance information and specifications are subject to change without notice.
For additional information on these devicesincluding block diagrams, signal descriptions, device
operation and pin assignments-refer to the M6800
Microcomputer System Design Data brochure.
©MOTOROLA INC., 1977
ADI-429
MICROPROCESSING UNIT (MPU)
MC68AOO • MC68BOO
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, ±5%, VSS = 0, T A = 0 to 70 0 C unless otherwise noted.)
Symbol
Min
Typ
Max
Unit
Logic
ct> 1, ct>2
VII-j
VIHC
VSS +2.0
VCC - 0.6
-
VCC
VCC + 0.3
Vdc
Logic
VIL
VILC
VSS - 0.3
Vss - 0.3
-
VSS + 0.8
Vss + 0.4
Vdc
Logic*
-
1.0
ct>1, ct>2
-
Characteristic
Input High Voltage
Input Low Voltage
ct>1, ct>2
Input Leakage Current
(Vin = 0 to 5.25 V, VCC
(Vin = 0 to 5.25 V, VCC
-
-
MAdc
lin
= max)
= 0.0 V)
Three-State (Off State) Input Current
(Vin = 0.4 to 2.4 V, VCC = max)
00-07
AO-A15, R/W
ITSI
-
-
2.0
2.5
100
10
100
-
-
VSS + 2.4
VSS + 2.4
VSS + 2.4
-
-
-
VOL
-
-
VSS + 0.4
Power Dissipation
Po
-
0.5
1.0
Capacitance #
(Vin = 0, TA
Cin
Output High Voltage
(I Load = -205 MAdc, VCC
(I Load = -145 MAde, VCC
(I Load = -100 MAde, VCC
Output Low Voltage
(I Load = 1.6 mAde, VCC
Vdc
VOH
= min)
= min)
= min)
00-07
AO-A15, R/W, VMA
BA
-
Vdc
= min)
= 25 0 C, f = 1.0 MHz)
ct>1
ct>2
00-07
Logic Inputs
AO-A15, R/W, VMA
Frequency of Operation
MC68AOO
MC68BOO
Clock Timing (Figure 1)
Cycle Time
Clock Pulse Width
(Measured at VCC -0.6 V)
Total ct> 1 and ct>2 Up Time
Rise and Fall Times
(Measured between VSS + 0.4 and VCC -0.6)
Delay Time or Clock Separation
(Measured at VOV = VSS + 0.6 V)
-
-
MC68AOO
MC68BOO
t cyc
ct>1, ct>2 - MC68AOO
ct>1, ct>2 - MC68BOO
PWct>H
MC68AOO
MC68BOO
-
Cout
f
W
pF
10
6.5
35
70
12.5
10
-
-
12
pF
0.1
0.1
-
1.5
2.0
MHz
10
10
MS
9500
9500
ns
-
ns
0.666
0.50
-
-
230
180
-
600
440
-
tct>r: tct>f
5.0
-
100
ns
td
0
-
9100
ns
tut
*Except IRQ and NMI, which require a 3.0 kn pull up load resistor for wire-OR capability at optimum operation.
#Capacitances are periodically sampled rather than 100% tested.
®
MAdc
MOTOROLA SelTliconduci:or Produci:s Inc.
-
<
READIWRITE TIMING
MC68BOO
MC68AOO
Characteristic
Symbol
Address Delay
Typ
Max
Min
Typ
Max
-
-
180
165
-
-
150
135
Peripheral Read Access Time
-
250
Unit
ns
tAD
C = 90 pF
C = 30 pF
t ac = tut - (tAD
Min
t acc
-
360
-
-
40
-
ns
+ tDSR)
tDSR
60
Input Data Hold Time
tH
10
-
Output Data Hold Time
tH
10
25
Address Hold Time (Address, R/W, VMA)
tAH
10
Enable High Time for DBE Input
tEH
280
Data Setup Time (Read)
Data Delay Time (Write)
Processor Controls
Processor Control Setup Time
Processor Control Rise and Fall Time
Bus Available Delay
Three-State Enable
Three-State Delay
Data Bus Enable Down Time During (jJ 1 Up Time
Data Bus Enable Rise and Fall Times
-
ns
10
-
-
ns
10
25
-
ns
75
-
10
75
-
ns
-
-
220
-
-
ns
165
200
160
ns
tDDW
-
tpcs
tPCr, tpCf
tBA
tTSE
tTSD
tDBE
tOBEr' t DBEf
200
-
-
-
-
-
-
-
-
-
200
(jJ1
...,
§'HC
VOV
VILC
td ----
-
-
-
-
70
-
-
-
-
25
-
-
25
-
-
-
-
-
-
-
~\lV~:~
(jJ2
V I LC
tut
---t(jJf
'dJ
/
....,~
---
~~li=
I}Z'-
--rl
~I
t(jJr
--I -
PW(jJ H -
t(jJf
FIGURE 2 - READ/WRITE TIMING WAVEFORM
Measurement point for (jJ1 and (jJ2 are shown below.
Other measurements are the same as for MC6800.
~s"" of Cycle
(jJ1
VCC-0.6V
0.4 V
t r
(jJ~\-
®
-
150
-
t cyc
i---PW(jJH---j
-
100
270
40
270
FIGURE 1 - CLOCK TIMING WAVEFORM
t(jJr-
-
--J/
~C4-VO.6
1 \':
V
MOTOROLA SelT1iconduc'for Produc'fs Inc.
100
270 '
40
270
ns
ns
ns
ns
ns
ns
ns
PERIPHERAL INTERFACE ADAPTER (PIA)
MC68A21 • MC68B21
ELECTRICAL CHARACTERISTICS (Vcc = 5.0 V ±5%, vss = 0, T A = 0 to 70 0 C unless otherwise noted.)
Characteristic
Min
Typ
Max
VSS + 2.0
-
VCC
Vde
VIL
VSS -0.3
-
VSS + 0.8
Vde
lin
-
1.0
2.5
,uAde
PBO~PB7, CB2
ITSI
-
2.0
10
,uAde
Input High Current
(VIH = 2.4 Vde)
PAO-PA7, CA2
IIH
-200
-400
-
,uAde
Input Low Current
(VIL = 0.4 Vdc)
PAO-PA7, CA2
IlL
-
-1.3
-2.4
mAdc
Symbol
Input High Voltage
VIH
Input Low Voltage
Input Lea kage Current
(Vin = 0 to 5.25 Vdc)
R/W, Reset, RSO, RS1, CSO, CS2, CS1,
CA1, CB1 i Enable
Three-State (Off State) Input Current
(Vin = 0.4 to 2.4 Vde)
00-07,
Output High Voltage
(I Load = - 205 ,uAdc)
(I Load = -200 ,uAde)
00-07
Other Outputs
Output Low Voltage
(I Load = 1.6 mAde)
(I Load = 3.2 mAdc)
00-07
Other Outputs
Unit
Vde
VOH
VSS + 2.4
VSS + 2.4
-
-
-
-
Vdc
VOL
-
-
-
-
-205
-100
-1.0
-
-
-
-
-2.5
-10
,uAde
,uAdc
mAde
ILOH
-
1.0
10
,uAde
Power Dissipation
Po
-
-
550
mW
Capacitance
(Vin = 0, TA = 25 0 C, f
Cin
-
-
12.5
10
7.5
-
5.0
Output High Current (Sourcing)
(VOH = 2.4 Vde)
(VO = 1 .5 Vde, the current for driving other
than TTL, e.g., Darlington Base)
Output Leakage Current (Off State)
(VOH = 2.4 Vde)
IOH
00-07
Other Outputs
PBO-PB7, CB2
IROA,IROB
1.0 MHz)
00-07
PAO-PA7, PBO-PB7, CA2, CB2
Enable, R/W, Reset, RSO, RS1, CSO, CS1, CS2, CA1, CB1
=
IROA,IROB
pF
-
Cout
-
NOTE:
The PAO-PA7 Peripheral Data lines and the CA2 Peripheral Control line can drive two standard
TTL loads. In the input mode, the internal pullup resistor on these lines represents a maximum of
1.5 standard TTL loads.
®
VSS + 0.4
VSS + 0.4
MOTOROLA Setniconducf:or Producf:s Inc.
pF
TIMING CHARACTERISTICS (Vcc
= 5.0 V ±5%, VSS = 0, T A = 0 to 70 0 C unless otherwise noted.)
MC68A21
Characteristic
MC68B21
Symbol
Min
Max
Min
Max
Peripheral Data Setup Time
tpDSU
135
-
100
-
ns
Peripheral Data Hold Time
tPDH
0
-
0
-
ns
Delay Time, Enable negative transition to CA2 negative transition
tCA2
-
0.670
-
0.5
j.lS
Delay Time, Enable negative transistion to CA2 positive transition
tRS1
-
0.670
-
0.5
j.lS
Rise and Fall Times for CA 1 and CA2 input signals
-
1.0
j.lS
t r, tf
-
1.0
Delay Time from CA 1 active transition to CA2 positive transition
tRS2
-
1.35
Delay Time, Enable negative transition to Peripheral Data Valid
tpDW
0.670
Delay Time, Enable negative transition to Peripheral CMOS Data Valid
(VCC - 30%, VCC; Figure 6, Load C)
PAO-PA7, CA2
tCMOS
-
1.35
Delay Time, Enable positive transition to CB2 negative transition
tCB2
-
0.670
Delay Time, Peripheral Data Valid to CB2 negative transition
tDC
20
-
Delay Time, Enable positive transition to CB2 positive transition
tRS1
-
0.670
550
-
-
20
-
Unit
1.0
j.lS
0.5
j.lS
1.0
j.lS
0.5
j.lS
-
ns
0.5
j.lS
Peripheral Control Output Pulse Width, CA2/CB2
PWCT
Rise and Fall Time for CB1 and CB2 input signals
t r , tf
-
1.0
Delay Time, CB1 active transition to CB2 positive transition
tRS2
-
1.35
-
1.0
j.lS
1.1
-
0.85
j.lS
1.0
-
1.0
j.lS
-
500
-
ns
0.5
-
j.lS
Interrupt Release Time, IROA and IROB
tlR
Interrupt Resporlse Time
tRS3
-
Interrupt Input Pulse Width
PWI
500
Reset Low Time*
tRL
0.66
*The Reset line must be high a minimum of 1.0
j.lS
BUS TIMING CHARACTERISTICS (VCC
550
-
1.0
-
ns
j.lS
before addressing the PIA.
= 5.0 V ±5%, VSS = 0, T A = 0 to 70 0 C unless otherwise noted.)
READ
MC68B21
MC68A21
Characteristic
Symbol
Min
Max
Min
Max
Unit
Enable Cycle Time
tcycE
0.666
-
0.50
-
j.lS
Enable Pulse Width, High
PWEH
0.280
-
0.22
-
j.lS
Enable Pulse Width, Low
PWEL
0.280
-
0.21
-
j.lS
-
70
-
ns
180
ns
ns
~
Setup Time, Address and R/W Valid to Enable positive transition
tAS
140
Data Delay Time
tDDR
-
Data Hold Time
tH
10
-
10
-
tAH
10
-
10
-
ns
-
25
-
25
ns
Address Hold Time
Rise and Fall Time for Enable input
t Er, t Ef
220
-
WRITE
Enable Cycle Time
tcycE
0.666
-
0.50
-
j.lS
Enable Pulse Width, High
PWEH
0.280
-
0.22
-
j.lS
Enable Pulse Width, Low
PWEL
0.280
-
0.21
-
j.lS
-
70
-
ns
60
-
ns
10
-
ns
10
-
ns
-
25
ns
Setup Time, Address and R/W Valid to Enable positive transition
tAS
140
Data Setup Time
tDSW
80
Data Hold Time
tH
10
tAH
10
-
-
25
Address Hold Time
Rise and Fall Time for Enable input
1....-
®
tEr, t Ef
MOTOROLA Setniconduc'for Produc'fs Inc.
NOTES:
1. Figures shown are only those needed to define
new measurements not specified on the MC6820 data
sheet (page 39 of M6800 Microcomputer System Design
Data). Refer to that data sheet, or to the new MC6821
data sheet, for further information.
2. On all tests, measurements on the Enable pulse are
at 0.8 V and 2.0 V.
FIGURE 4 - PERIPHERAL CONTROL OUTPUT PULSE WIDTH
t 1V
pwCT
~0.4V
CA2
CB2
I
FIGURE 3 - PERIPHERAL DATA HOLD TIME
(Read Mode)
PAO-PA7
PBO-PB7
---0.-81t
2.0V
0;:;.:.;,;:;8_V;..
_
'tPDH
Enable
FIGURE 5 - INTERRUPT PULSE WIDTH and IRQ RESPONSE
V!
1)(......
CA1,2
2.0 V
CB 1, 2 _ _---'I\!I..:O~.:::.8...:V:....-
....:..
=tRS3.__
I
I
_
~V
* Assumes I nterrupt Enable Bits are set.
FIGURE 6 - BUS TIMING TEST LOADS
Load B
(IRQ Only)
Load A
(00-07)
() 5.0 V
5.0 V
:>
I-
3k
Test Point ....,o-_-_---l:IOOIIIII~I--- MMD6150
~, or Equiv.
-~
C;:,
130 p F
R
11.7 k
~,
-~
MMD 7000
~,
or Equiv.
Test Point 0---4
100 pF
-f-
Load C
(CMOS Load)
I
Load 0
(PAO-PA7, PBO-PB7, CA2, CB2)
OVCC
~~L
Test Point ....,0-__ _VI
11
-
~'10011111.....1 __ _
T""Ir"
MMD6150
or Equiv.
-~
c;:~
~,.
R
-~
MMD7000
'F
-I-
or Equiv.
~
C
= 40
pF, R
= 12
k
Adjust R L sO that II = 3.2 mA
with VI = 0.4 V and VCC = 5.25 V
@ MOTOROLA SenJiconduc'for Produc'fs Inc.
ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER (ACIA)
MC68A50 • MC68B50
ELECTRICAL CHARACTERISTICS (VCC
= 5.0 V ±5%,
vss = 0, T A = 0 to 70 0 C unless otherwise noted.)
Typ
Symbol
Min
Max
Unit
Input High Voltage
VIH
VSS + 2.0
-
VCC
Vdc
Input Low Voltage
VIL
VSS -0.3
-
VSS + 0.8
Vdc
lin
-
1.0
2.5
,uAdc
-
2.0
10
,uAdc
VSS + 2.4
VSS + 2.4
-
-
-
VSS + 0.4
Vdc
Characteristic
Input Leakage Current
(Vin = 0 to 5.25 Vdc)
R/W,CSO,CS1,CS2,Enable
Three-State (Off State) Input Current
(Vin = 0.4 to 2.4 Vdc)
DO-D7
ITSI
Output High Voltage
(I Load = -205 ,uAdc, Enable Pulse Width <25 ,us)
(I Load = -100 ,uAdc, Enable Pulse Width <25 ,us)
DO-D7
VOH
--
Tx Data, RTS
Output Low Voltage
(I Load = 1.6 mAde, Enable Pulse Width <25 ,us)
Vdc
VOL
-
ILOH
-
1.0
10
,uAdc
Power Dissipation
PD
-
300
525
mW
Capacitance
Cin
-
10
7.0
12.5
7.5
-
-
10
5.0
Output Leakage Current (Off State)
(VOH = 2.4 Vdc)
IRQ
DO-D7
(Vin = 0, TA = 25 0 C, f = 1.0 MHz)
E, Tx Clk, Rx Clk, R/W, RS, Rx Data, CSO, CS1, CS2, CTS, DCD
RTS, Tx Data
IRQ
C out
pF
-
pF
Minimum Clock Pulse Width, Low
-;-16,764 Modes
PWCL
600
-
-
ns
Minimum Clock Pulse Width, High
-;-16,764 Modes
PWCH
600
-
ns
Clock Frequency
-;-1 Mode
-;-16,764 Modes
fC
-
-
500
800
kHz
-
1.0
,us
-
ns
1.2
,us
1.0
,us
1.0*
,us
Clock-to-Data Delay for Transmitter
Receive Data Setup Time
-;-1 Mode
Receive Data Hold Time
-;-1 Mode
Interrupt Request Release Time
Request-to-Send Delay Time
Input Transition Times (Except Enable)
tTDD
-
-
tRDSU
500
-
tRDH
500
-
tlR
-
tRTS
-
tr,tf
-
-
ns
* 1.0 ,us or 10% of the pulse width, whichever is smaller.
BUS TIMING CHARACTERISTICS (VCC
=
5.0 V ±5%, VSS = 0, T A = 0 to 70 0 C unless otherwise noted.)
READ
MC68B50
MC68A50
Symbol
Min
Max
Min
Max
Enable Cycle Time
tcycE
0.666
-
0.50
-
,us
Enable Pulse Width, High
PWEH
0.28
25
0.22
25
,us
Enable Pulse Width, Low
PWEL
0.28
-
0.21
-
,us
tAS
140
-
70
-
ns
220
-
180
ns
-
10
ns
ns
Characteristic
Setup Time, Address and R/W Valid to Enable positive transition
Data Delay Time
tDDR
Data Hold Time
tH
10
-
Unit
tAH
10
-
10
-
t Er, t Ef
-
25
-
25
Enable Cycle Time
tcycE
0.666
-
0.50
-
,us
Enable Pulse Width, High
PWEH
0028
25
0.22
25
,us
Enable Pulse Width, Low
PWEL
0.28
-
0.21
-
,us
tAS
140
-
70
-
ns
Data Setup Time
tDSW
80
-
ns
tH
10
-
60
Data Hold Time
10
-
ns
tAH
10
-
10
-
ns
25
-
25
ns
Address Hold Time
Rise and Fall Time for Enable input
ns
WRITE
Setup Time, Address and R/W Valid to Enable positive transition
Address Hold Time
Rise and Fall Time for Enable input
®
tEr,tEf
-
MOTOROLA Sen1iconduc'for Produc'fs Inc.
RANDOM ACCESS MEMORY (RAM)
MCM68A10 • MCM68B10
DC CHARACTERISTICS (VCC = 5.0 V ±5%, vss = 0, T A = 0 to 70 0 C unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
lin
-
-
2.5
}.lAdc
VOH
2.4
-
-
Output Low Voltage
(I0L = 1.6 mAl
VOL
-
-
0.4
Vdc
Output Leakage Current (Three-State)
ILO
-
-
10
}.lAdc
-
-
80
Input Current (An, R/W, CS n , CS n )
(Vin = 0 to 5.25 V)
Output High Voltage
UOH
(CS
Vdc
= -205 p,A)
= 0.8 V or CS = 2.0 V, V out = 0.4 V to 2.4 V)
Supply Current
(VCC
mAdc
ICC
= 5.25 V, all other pins grounded, T A = OoC)
AC CHARACTERISTICS
= 5.0 V ±5%, VSS = 0, T A = 0 to 70 0 C unless otherwise noted.)
READ CYCLE (VCC
MCM68B10
MCM68A10
Symbol
Min
Max
Min
Max
Unit
tcyc(R)
360
-
250
-
ns
Access Time
t acc
-
-
250
ns
Address Setup Time
tAS
20
360
-
ns
ns
Characteristic
Read Cycle Time
0
-
220
-
180
0
-
0
-
ns
tDHA
10
-
10
-
ns
tH
10
-
10
-
ns
tDHW
10
60
10
60
ns
tAH
0
Data Delay Time (Read)
tDDR
-
Read to Select Delay Time
tRCS
Data Hold from Address
Address Hold Time
Output Hold Time
Data Hold from Write
WRITE CYCLE (VCC
-
20
ns
= 5.0 V ±5%,VSS = 0, TA = 0 to 70 0 C unless otherwise noted.)
MCM68B10
MCM68A10
Characteristic
Symbol
Min
Max
Min
tcyc(W)
360
-
250
-
ns
Address Setup Time
tAS
20
-
20
-
ns
Address Hold Time
tAH
0
-
0
-
ns
ns
Write Cycle Time
Chip Select Pulse Width
Max
Unit
tcs
250
-
210
-
Write to Chip Select Delay Time
twcs
0
-
0
-
ns
Data Setup Time (Write)
tDSW
80
-
60
-
ns
tH
10
-
10
-
ns
Input Hold Time
MOTOROLA Selniconduc"for Produc-ts Inc.
3501 ED BLUESTEIN BLVD., AUSTIN, TEXAS 78721 • A SUBSIDIARY OF MOTOROLA INC.
10952 PRINTED IN USA 4-77
IMPERIAL LITHO 863344
15M
ADI-429