300-W STEREO / 400-W MONO PurePath™ HD DIGITAL-INPUT POWER STAGE TAS5631B FEATURES APPLICATIONS

TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
300-W STEREO / 400-W MONO PurePath™ HD DIGITAL-INPUT POWER STAGE
Check for Samples: TAS5631B
FEATURES
APPLICATIONS
•
•
•
•
•
1
23
•
•
•
•
•
•
PurePath™ HD Enabled Integrated Feedback
Provides:
– Signal Bandwidth up to 80 kHz for HighFrequency Content From HD Sources
– Ultralow 0.03% THD at 1 W Into 4 Ω
– Flat THD at All Frequencies for Natural
Sound
– 80-dB PSRR (BTL, No Input Signal)
– >100-dB (A-weighted) SNR
– Click- and Pop-Free Start-Up
Multiple Configurations Possible on the Same
PCB With Stuffing Options:
– Mono Parallel Bridge-Tied Load (PBTL)
– Stereo Bridge-Tied Load (BTL)
– 2.1 Single-Ended Stereo Pair and BridgeTied Load Subwoofer
– Quad Single-Ended Outputs
Total Output Power at 10% THD+N
– 400 W per Channel in Mono PBTL
Configuration
– 300 W per Channel in Stereo BTL
Configuration
– 145 W per Channel in Quad Single-Ended
Configuration
High-Efficiency Power Stage (>88%) With 60mΩ Output MOSFETs
Two Thermally Enhanced Package Options:
– PHD (64-Pin QFP)
– DKD (44-Pin PSOP3)
Self-Protection Design (Including
Undervoltage, Overtemperature, Clipping, and
Short-Circuit Protection) With Error Reporting
EMI Compliant When Used With
Recommended System Design
Mini Combo System
AV Receivers
DVD Receivers
Active Speakers
DESCRIPTION
The TAS5631B is a high-performance PWM input
class-D amplifier with integrated closed-loop
feedback technology (known as PurePath HD
technology) with the ability to drive up to 300 W (1)
stereo into 4-Ω to 8-Ω speakers from a single 50-V
supply.
PurePath HD technology enables traditional ABamplifier performance (<0.03% THD) levels while
providing the power efficiency of traditional class-D
amplifiers.
Unlike traditional class-D amplifiers, the distortion
curve does not increase until the output levels move
into clipping. PurePath HD™
PurePath HD technology enables lower idle losses,
making the device even more efficient.
Note 1. Achievable output power levels are
dependent on the thermal configuration of the target
application. A high-performance thermal interface
material between the package exposed heat slug
and the heat sink should be used to achieve high
output-power levels.
♫♪
DIGITAL
AUDIO
INPUT
TAS5518C
Digital PWM
Processor
TM
PurePath HD
TAS5630
TAS5631B
♫♪
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath HD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Pin Assignment
Both package types contains a heat slug that is located on the top side of the device for convenient thermal
coupling to the heat sink.
DKD PACKAGE
(TOP VIEW)
64-pins QFP package
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
_
GND_D
OTW2
CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PSU_REF
VDD
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
SD
OTW
READY
M1
M2
M3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 pins PACKAGE
(TOP VIEW)
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
SD
OTW1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
PHD PACKAGE
(TOP VIEW)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GVDD_AB
BST_A
PVDD_A
PVDD_A
OUT_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD_CD
PIN ONE LOCATION PHD PACKAGE
Electrical Pin 1
Pin 1 Marker
White Dot
2
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
MODE SELECTION PINS
MODE PINS
PWM INPUT (1)
OUTPUT
CONFIGURATION
2N
2 × BTL
AD mode
—
—
Reserved
2N
2 × BTL
BD mode
1N
1 × BTL +2 × SE
AD mode
0
1N
4 × SE
AD mode
1
2N
IN
M3
M2
M1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
(1)
(2)
DESCRIPTION
INPUT_C (2)
INPUT_D (2)
0
0
AC mode
1
0
BD mode
1 x PBTL
Reserved
The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
INPUT_C and INPUT_D are used to select between a subset of AD and BD mode operations in PBTL mode.
THERMAL INFORMATION
THERMAL METRIC (1) (2)
TAS5631B
PHD (64 Pins)
DKD (44 Pins)
θJA
Junction-to-ambient thermal resistance
8.5
9.3
θJCtop
Junction-to-case (top) thermal resistance
0.2
0.6
θJB
Junction-to-board thermal resistance
20.6
3.7
ψJT
Junction-to-top characterization parameter
0.2
1.3
ψJB
Junction-to-board characterization parameter
0.73
3.5
θJCbot
Junction-to-case (bottom) thermal resistance
8.2
19.1
(1)
(2)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Thermal model data was performed using a 40 x 40 x 90mm heat-sink
Table 1. ORDERING INFORMATION (1)
(1)
TA
PACKAGE
DESCRIPTION
0°C–70°C
TAS5631BPHD
64-pin HTQFP
0°C–70°C
TAS5631BDKD
44-pin PSOP3
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
3
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TAS5631B
UNIT
VDD to AGND
–0.3 to 13.2
V
GVDD to AGND
–0.3 to 13.2
V
PVDD_X to GND_X (2)
–0.3 to 69
V
PVDD_X to GND_X; DC voltage
-0.3 to 57
V
OUT_X to GND_X
(2)
–0.3 to 69
V
–0.3 to 82.2
V
BST_X to GVDD_X (2)
–0.3 to 69
V
VREG to AGND
–0.3 to 4.2
V
GND_X to GND
–0.3 to 0.3
V
GND_X to AGND
–0.3 to 0.3
V
GND to AGND
–0.3 to 0.3
V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP,
PSU_REF to GND
–0.3 to 4.2
V
–0.3 to 7
V
BST_X to GND_X (2)
INPUT_X, RESET, SD, OTW1, OTW2, CLIP, READY to GND
Maximum continuous sink current (SD, OTW1, OTW2, CLIP, READY)
Maximum operating junction temperature range, TJ
Storage temperature, Tstg
Human-body model
Electrostatic discharge
(1)
(2)
(3)
(3)
(all pins)
Charged-device model (3) (all pins)
9
mA
0 to 150
°C
–40 to 125
°C
±2
kV
±500
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represents the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
Failure to follow good anti-static ESD handling during manufacture and rework contributes to device malfunction. Make sure the
operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
PVDD_x
Half-bridge supply
DC supply voltage
25
50
52.5
V
GVDD_x
Supply for logic regulators and gate-drive circuitry
DC supply voltage
10.8
12
13.2
V
VDD
Digital regulator supply voltage
DC supply voltage
10.8
12
13.2
V
3.5
4
1.8
2
2.4
3
7
10
7
15
7
10
352
384
RL(BTL)
RL(SE)
(2)
RL(PBTL)
Load impedance
Output filter according to schematics in the
application information section.
(1)
(2)
LOUTPUT(BTL)
LOUTPUT(SE)
(2)
Output filter inductance
(1)
Minimum output inductance at IOC
LOUTPUT(PBTL) (2)
fPWM
PWM frame rate
ROCP
Overcurrent-protection-programming resistor,
cycle-by-cycle mode
Overcurrent-protection-programming resistor,
latching mode
TJ
(1)
(2)
4
Ω
μH
500
64-pin QFP package (PHD)
22
33
44-Pin PSOP3 package (DKD)
24
33
PHD or DKD
47
68
0
125
Junction temperature
kHz
kΩ
°C
Values are for actual measured impedance over all combinations of tolerance, current and temperature and not simply the component
rating.
See additional details for SE and PBTL in the System Design Considerations section.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
PIN FUNCTIONS
PIN
Function (1)
DESCRIPTION
10
P
Analog ground
43
P
HS bootstrap supply (BST); external 0.033-μF capacitor to OUT_A required
41
34
P
HS bootstrap supply (BST); external 0.033-μF capacitor to OUT_B required
BST_C
40
33
P
HS bootstrap supply (BST); external 0.033-μF capacitor to OUT_C required
BST_D
27
24
P
HS bootstrap supply (BST); external 0.033-μF capacitor to OUT_D required
CLIP
18
—
O
Clipping warning; open drain; active-low
C_STARTUP
3
5
O
Start-up ramp requires a charging capacitor of 4.7 nF to AGND.
TEST
12
14
I
Connect to VREG node
GND
7, 23, 24, 57, 58
9
P
Ground
GND_A
48, 49
38
P
Power ground for half-bridge A
GND_B
46, 47
37
P
Power ground for half-bridge B
GND_C
34, 35
30
P
Power ground for half-bridge C
GND_D
32, 33
29
P
Power ground for half-bridge D
GVDD_A
55
—
P
Gate drive voltage supply requires 0.1-μF capacitor to AGND.
GVDD_B
56
—
P
Gate drive voltage supply requires 0.1-μF capacitor to AGND.
GVDD_C
25
—
P
Gate drive voltage supply requires 0.1-μF capacitor to AGND.
GVDD_D
26
—
P
Gate drive voltage supply requires 0.1-μF capacitor to AGND.
GVDD_AB
—
44
P
Gate drive voltage supply requires 0.22-μF capacitor to AGND.
GVDD_CD
—
23
P
Gate drive voltage supply requires 0.22-μF capacitor to AGND.
INPUT_A
4
6
I
Input signal for half-bridge A
INPUT_B
5
7
I
Input signal for half-bridge B
INPUT_C
10
12
I
Input signal for half-bridge C
INPUT_D
11
13
I
Input signal for half-bridge D
M1
20
20
I
Mode selection
M2
21
21
I
Mode selection
M3
22
22
I
Mode selection
NC
59–62
–
—
No connect; pins may be grounded.
NC
NAME
PHD NO.
DKD NO.
AGND
8
BST_A
54
BST_B
13, 14
15, 16
—
No connect; pins may be grounded.
OC_ADJ
1
3
O
Analog overcurrent programming pin requires resistor to ground.
OTW
—
18
O
Overtemperature warning signal, open-drain, active-low
OTW1
16
—
O
Overtemperature warning signal, open-drain, active-low
OTW2
17
—
O
Overtemperature warning signal, open-drain, active-low
OUT_A
52, 53
39, 40
O
Output, half-bridge A
OUT_B
44, 45
36
O
Output, half-bridge B
OUT_C
36, 37
31
O
Output, half-bridge C
OUT_D
28, 29
27, 28
O
Output, half-bridge D
63
1
P
PSU reference requires close decoupling of 4.7 μF to AGND.
PVDD_A
50, 51
41, 42
P
Power-supply input for half-bridge A requires close decoupling with 2.2μF capacitor to
GND_A.
PVDD_B
42, 43
35
P
Power-supply input for half-bridge B requires close decoupling with 2.2μF capacitor to
GND_B.
PVDD_C
38, 39
32
P
Power-supply input for half-bridge C requires close decoupling with 2.2µF capacitor to
GND_C.
PVDD_D
30, 31
25, 26
P
Power-supply input for half-bridge D requires close decoupling with 2.2μF capacitor to
GND_D.
READY
19
19
O
Normal operation; open-drain; active-high
RESET
2
4
I
Device reset input; active-low
SD
15
17
O
Shutdown signal; open-drain, active-low
VDD
64
2
P
Power supply for digital voltage regulator requires a 47-μF capacitor in parallel with a 0.1μF capacitor to GND for decoupling.
VI_CM
6
8
O
Analog comparator reference node requires close decoupling of 4.7 μF to AGND.
PSU_REF
(1)
I = Input, O = Output, P = Power
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
5
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
PIN FUNCTIONS (continued)
PIN
NAME
PHD NO.
DKD NO.
VREG
9
11
Function (1)
P
DESCRIPTION
Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.
TYPICAL SYSTEM BLOCK DIAGRAM
Caps for
External
Filtering
and
Startup/Stop
System
microcontroller
(2)
AMP RESET
LeftChannel
Output
PWM_A
C_STARTUP
VI_CM
PSU_REF
RESET
VALID
/CLIP
*NOTE1
READY
/SD
TAS5518/
TAS5508/
TAS5086
/OTW1, /OTW2, /OTW
I2C
BST_A
BST_B
OUT_A
INPUT_A
PWM_B
Input
H-Bridge 1
INPUT_B
Output
H-Bridge 1
2
OUT_B
2
Bootstrap
Caps
2nd Order
L-C Output
Filter for
each
H-Bridge
2-CHANNEL
H-BRIDGE
BTL MODE
PWM_C
INPUT_C
PWM_D
OUT_C
Input
H-Bridge 2
INPUT_D
Output
H-Bridge 2
2
OUT_D
8
50V
PVDD
12V
PVDD
Power Supply
Decoupling
SYSTEM
Power
Supplies
GND
8
OC_ADJ
TEST
VREG
AGND
M3
2nd Order
L-C Output
Filter for
each
H-Bridge
BST_C
VDD
M2
GND
M1
GND_A, B, C, D
Hardwire
Mode
Control
GVDD_A, B, C, D
2
PVDD_A, B, C, D
RightChannel
Output
BST_D
Bootstrap
Caps
4
GVDD, VDD,
and VREG
Power Supply
Decoupling
Hardwire
OverCurrent
Limit
GND
GVDD (12V)/VDD (12V)
VAC
(1)
6
Logic AND is inside or outside the microcontroller.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
FUNCTIONAL BLOCK DIAGRAM
CLIP
READY
OTW1
OTW2
SD
PROTECTION & I/O LOGIC
M1
M2
M3
RESET
STARTUP
CONTROL
C_STARTUP
VDD
POWER-UP
RESET
UVP
VREG
VREG
AGND
TEMP
SENSE
GVDD_A
GVDD_C
GVDD_B
OVER-LOAD
PROTECTION
PPSC
CURRENT
SENSE
CB3C
4
4
4
GND
GVDD_D
OC_ADJ
PVDD_X
OUT_X
GND_X
GVDD_A
PWM
ACTIVITY
DETECTOR
BST_A
PVDD_A
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_A
GND_A
PSU_REF
GVDD_B
VI_CM
INPUT_D
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
-
+
ANALOG COMPARATOR MUX
PVDD_X
GND
PVDD_B
PWM
RECEIVER
+
ANALOG INPUT MUX
4
AGC
BST_B
+
ANALOG
LOOP FILTER
INPUT_B
INPUT_C
-
ANALOG
LOOP FILTER
INPUT_A
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_B
GND_B
GVDD_C
BST_C
PVDD_C
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
+
OUT_C
GND_C
-
GVDD_D
BST_D
PVDD_D
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_D
GND_D
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
7
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
AUDIO CHARACTERISTICS (BTL)
Audio performance is recorded as a chipset consisting of a TAS5518 PWM processor (modulation index limited to 97.7%)
and a TAS5631B power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C;
output filter: LDEM = 10 μH, CDEM = 680 nF, MODE = 000, unless otherwise noted.
PARAMETER
PO
Power output per channel
TEST CONDITIONS
MIN
TYP MAX UNIT
RL = 4 Ω, 10% THD+N, clipped input signal
300
RL = 6 Ω, 10% THD+N, clipped input signal
210
RL = 8 Ω, 10% THD+N, clipped input signal
160
RL = 4 Ω, 1% THD+N, unclipped input signal
240
RL = 6 Ω, 1% THD+N, unclipped input signal
160
RL = 8 Ω, 1% THD+N, unclipped input signal
125
W
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, TAS5518 modulator
|VOS|
Output offset voltage
No signal
SNR
Signal-to-noise ratio (1)
A-weighted, TAS5518 modulator
103
dB
DNR
Dynamic range
A-weighted, input level –60 dBFS using TAS5518
modulator
103
dB
Pidle
Power dissipation due to idle losses
(IPVDD_X)
PO = 0, all channels switching (2)
3.9
W
(1)
(2)
0.03%
μV
180
15
40
mV
SNR is calculated relative to 1% THD-N output level.
Actual system idle losses also are affected by core losses of output inductors.
AUDIO SPECIFICATION (Single-Ended Output)
Audio performance is recorded as a chipset consisting of a TAS5086 PWM processor (modulation index limited to 97.7%)
and a TAS5631B power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 2 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C;
output filter: LDEM = 7 μH, CDEM = 470 nF, MODE = 100, unless otherwise noted.
PARAMETER
PO
TEST CONDITIONS
Power output per channel
MIN
TYP MAX
RL = 2 Ω, 10%, THD+N, clipped input signal
145
RL = 3 Ω, 10%, THD+N, clipped input signal
100
RL = 4 Ω, 10%, THD+N, clipped input signal
75
RL = 2 Ω, 1% THD+N, unclipped input signal
110
RL = 3 Ω, 1% THD+N, unclipped input signal
75
RL = 4 Ω, 1% THD+N, unclipped input signal
UNIT
W
55
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, TAS5086 modulator
140
μV
A-weighted, TAS5086 modulator
100
dB
100
dB
3
W
SNR
Signal-to-noise ratio
(1)
0.04%
DNR
Dynamic range
A-weighted, input level –60 dBFS using TAS5086
modulator
Pidle
Power dissipation due to idle losses (IPVDD_X)
PO = 0, 4 channels switching (2)
(1)
(2)
8
SNR is calculated relative to 1% THD-N output level.
Actual system idle losses are affected by core losses of output inductors.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
AUDIO SPECIFICATION (PBTL)
Audio performance is recorded as a chipset consisting of a TAS5086 PWM processor (modulation index limited to 97.7%)
and a TAS5631B power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 3 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C;
output filter: LDEM = 10 μH, CDEM = 680 nF, MODE = 100-00, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
RL = 3 Ω, 10%, THD+N, clipped input signal
400
RL = 4 Ω, 10%, THD+N, clipped input signal
300
RL = 3 Ω, 1% THD+N, unclipped input signal
310
UNIT
PO
Power output per channel
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, TAS5518 modulator
170
μV
A-weighted, TAS5518 modulator
103
dB
103
dB
3.7
W
RL = 4 Ω, 1% THD+N, unclipped input signal
SNR
Signal-to-noise ratio
(1)
230
0.03%
DNR
Dynamic range
A-weighted, input level –60 dBFS using TAS5086
modulator
Pidle
Power dissipation due to idle losses (IPVDD_X)
PO = 0, 4 channels switching (2)
(1)
(2)
W
SNR is calculated relative to 1% THD-N output level.
Actual system idle losses are affected by core losses of output inductors.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
9
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
PVDD_X = 50V, GVDD_X = 12 V, VDD = 12V, TC (case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
Voltage regulator, only used as reference
node, VREG
VI_CM
Analog comparator reference node, VI_CM
IVDD
VDD supply current
IGVDD_x
Gate-supply current per half-bridge
IPVDD_x
Half-bridge idle current
VDD = 12 V
3
3.3
3.6
V
1.5
1.75
1.9
V
Operating, 50% duty cycle
22.5
Idle, reset mode
22.5
50% duty cycle
12.5
Reset mode
mA
mA
1.5
50% duty cycle without output filter or
load
19.5
mA
Reset mode, no switching
750
μA
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
RDS(on)
Drain-to-source resistance, high side (HS)
TJ = 25°C, excludes metallization
resistance,
GVDD = 12 V
60
100
mΩ
60
100
mΩ
I/O PROTECTION
Vuvp,G
Undervoltage protection limit, GVDD_X, VDD
Vuvp,hyst
9.5
(1)
V
0.6
V
OTW1 (1)
Overtemperature warning 1
95
100
105
°C
OTW2 (1)
Overtemperature warning 2
115
125
135
°C
OTWhyst
(1)
Temperature drop needed below OTW temperature for OTW to be inactive after OTW
event
Overtemperature error
OTE (1)
25
145
OTE-OTW differential
OTEHYST
OLPC
(1)
165
30
°C
°C
A reset must occur for SD to be released following an OTE event
25
°C
Overload protection counter
fPWM = 384 kHz
2.6
ms
Nominal peak current in 1-Ω load,
64-pin QFP package (PHD)
ROCP = 22 kΩ
15
A
Nominal peak current in 1-Ω load,
44-pin PSOP3 package (DKD)
ROCP = 24 kΩ
15
A
Overcurrent latched
Nominal peak current in 1-Ω load,
ROCP = 47 kΩ
15
A
Internal pulldown resistor at output of each
half-bridge
Connected when RESET is active to
provide bootstrap charge. Not used in SE
mode.
3
mA
Overcurrent limit
IOC
IPD
155
°C
STATIC DIGITAL SPECIFICATIONS
VIH
High-level input voltage
VIL
Low-level input voltage
Ilkg
Input leakage current
INPUT_X, M1, M2, M3, RESET
1.9
V
1.45
V
100
μA
kΩ
OTW/SHUTDOWN (SD)
RINT_PU
Internal pullup resistance, OTW, OTW1,
OTW2, CLIP, READY, SD to VREG
VOH
High-level output voltage
VOL
Low-level output voltage
IO = 4 mA
FANOUT
Device fanout OTW, OTW1, OTW2, SD,
CLIP, READY
No external pullup
(1)
10
Internal pullup resistor
External pullup of 4.7 kΩ to 5 V
20
26
33
3
3.3
3.6
4.5
5
200
30
500
V
mV
devices
Specified by design
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
10
320
THD+N − Total Harmonic Distortion + Noise − %
4Ω
6Ω
8Ω
4Ω
6Ω
8Ω
300
280
260
240
PO − Output Power − W
1
0.1
220
200
180
160
140
120
100
80
60
40
0.01
0.005
0.02
0.1
1
10
100
TC = 75°C
THD+N at 10%
20
TC = 75°C
0
400
25
30
PO − Output Power − W
Figure 1.
Figure 2.
UNCLIPPED OUTPUT POWER
vs
SUPPLY VOLTAGE
SYSTEM EFFICIENCY
vs
OUTPUT POWER
280
4Ω
6Ω
8Ω
260
240
200
180
Efficiency − %
PO − Output Power − W
220
160
140
120
100
80
60
40
20
0
TC = 75°C
25
35
40
PVDD − Supply Voltage − V
30
35
40
PVDD − Supply Voltage − V
45
50
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
45
50
4Ω
6Ω
8Ω
TC = 25°C
THD+N at 10%
0
Figure 3.
100
200
300
400
500
2 Channel Output Power − W
600 650
Figure 4.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
11
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
OUTPUT POWER
vs
CASE TEMPERATURE
360
TC = 25°C
THD+N at 10%
340
320
300
280
260
PO − Output Power − W
Power Loss − W
SYSTEMS POWER LOSS
vs
OUTPUT POWER
240
220
200
180
160
140
120
100
80
60
4Ω
6Ω
8Ω
0
100
200
300
400
500
2 Channel Output Power − W
40
20
4Ω
6Ω
8Ω
THD+N at 10%
0
−50−40−30−20−10 0 10 20 30 40 50 60 70 80 90 100110
600 650
TC − Case Temperature − °C
Figure 5.
Figure 6.
NOISE AMPLITUDE
vs
FREQUENCY
+0
-10
-20
Noise Amplitude - dB
-30
-40
-50
TC = 75°C,
VREF = 31.7 V,
Sample Rate = 48 kHz,
FFT Size = 16384
-60
-70
-80
-90
-100
-110
-120
4W
-130
-140
-150
-160
0k
2k
4k
6k
8k 10k 12k 14k 16k 18k 20k 22k
f - Frequency - Hz
Figure 7.
12
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
TYPICAL CHARACTERISTICS, SE CONFIGURATION
1 Channel Driven
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
160
2Ω
3Ω
4Ω
2Ω
3Ω
4Ω
150
140
130
120
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
10
1
0.1
110
100
90
80
70
60
50
40
30
20
0.01
0.02
0.1
1
10
TC = 75°C
THD+N at 10%
10
TC = 75°C
0
100 200
25
30
PO − Output Power − W
35
40
PVDD − Supply Voltage − V
Figure 8.
45
50
Figure 9.
OUTPUT POWER
vs
CASE TEMPERATURE
170
160
150
140
PO − Output Power − W
130
120
110
100
90
80
70
60
50
40
30
2Ω
3Ω
4Ω
20
10
0
−10
0
10
THD+N at 10%
20
30
40
50
60
70
80
90 100 110
TC − Case Temperature − °C
Figure 10.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
13
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
500
3Ω
4Ω
6Ω
8Ω
3Ω
4Ω
6Ω
8Ω
450
400
1
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
10
0.1
350
300
250
200
150
100
0.01
50
TC = 75°C
THD+N at 10%
TC = 75°C
0.003
0.02
0.1
1
10
100
0
700
PO − Output Power − W
25
30
35
40
PVDD − Supply Voltage − V
G001
45
50
G001
Figure 11.
Figure 12.
OUTPUT POWER
vs
CASE TEMPERATURE
500
450
PO − Output Power − W
400
350
300
250
200
150
100
3Ω
4Ω
6Ω
8Ω
50
0
−10
0
10
THD+N at 10%
20
30
40
50
60
70
80
TC − Case Temperature − °C
90 100 110
G001
Figure 13.
14
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
APPLICATION INFORMATION
PCB MATERIAL RECOMMENDATION
FR-4 2-oz. (70 μm) glass epoxy material is recommended for use with the TAS5631B. The use of this material
can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB
trace resistance).
PVDD CAPACITOR RECOMMENDATION
The large capacitors used in conjunction with each full bridge are referred to as the PVDD capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well-designed system power supply, 1000 μF, 63 V support more applications.
The PVDD capacitors should be low-ESR type due to high ripple current.
DECOUPLING CAPACITOR RECOMMENDATION
To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio
performance, good-quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 2.2-μF capacitor that is placed on the power supply to each half-bridge. It must withstand the
voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the
ripple current created by high power output. A minimum voltage rating of 63 V is required for use with a 50-V
power supply.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
15
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
SYSTEM DESIGN RECOMMENDATIONS
The following schematics and PCB layouts illustrate best practices in the use of the TAS5631B.
GVDD/VDD (+12V)
2
10
100nF
100R
11
R_RIGHT_N
2
R13
VREG
1
12
13
100R
14
15
2
1
2
2
1
PVDD_C
TEST
OUT_C
NC
OUT_C
NC
GND_C
/SD
GND_C
/OTW1
GND_D
38
C62
2.2uF
36
1 2
2
2
1
GND
GND
GND
2
R74
3.3R
GND
C78
10nF
GND
GND
OUT_RIGHT_P
R72
3.3R
34
GND
33
C52
680nF
C72
1nF
+
1
GND_D
2
C76
10nF
C77
10nF
C53
680nF
1
READY
C73
1nF
2
L13
10uH
1
1
GND
1
GND
C69
2.2uF
GND
10uH
L12
35
2
/CLIP
C68
47uF
63V
1000uF
C66
C42
33nF
1
C63
2.2uF
/OTW2
PVDD
1
39
37
1
1
2
1000uF
C65
32
PVDD_D
PVDD_D
30
/OTW1
31
OUT_D
OUT_D
29
GVDD_D
BST_D
28
27
26
GVDD_C
GND
25
24
GND
M3
23
22
M2
21
M1
20
READY
19
/OTW2
/CLIP
18
17
/SD
1 2
1
1
1
2
49
GND_A
51
50
PVDD_A
PVDD_A
53
52
OUT_A
55
54
OUT_A
BST_A
GVDD_A
57
56
GND
GVDD_B
59
58
NC
GND
61
62
60
NC
NC
63
PVDD_C
INPUT_D
41
40
1
1
2
BST_C
INPUT_C
42
2
16
VREG
BST_B
12
9
AGND
C41
33nF
2
1
PVDD_B
U10
TAS5631BPHD
OUT_LEFT_M
C61
2.2uF
2
GND
GND
PVDD_B
GND
R71
3.3R
1
1
VREG
2
VI_CM
44
43
C71
1nF
2
1 2
2
C22
OUT_B
1
GND
-
1 2
IN_RIGHT_P
R12
OUT_B
INPUT_B
L11
10uH
GND
-
GND
R73
3.3R
2
8
INPUT_A
C51
680nF
46
1
7
4.7uF
100R
6
47
45
2
GND
1
GND_B
2
2
GND_B
C_STARTUP
1
C21
1
C75
10nF
2
IN_LEFT_N
R11
/RESET
48
1
4
GND_A
2
3
OC_ADJ
1
1
4.7nF
+
2
2
22.0k
C20
C74
10nF
1
1
2
1
R70
3.3R
C70
1nF
GND
R20
5
2
C50
680nF
1
2
NC
64
VDD
GND
GND
1
100R
OUT_LEFT_P
GND
1
R10
GND
2
C60
2.2uF
2
2
2
L10
10uH
1
1
IN_LEFT_P
GND
2
C31
100nF
2
2
100R C18
100pF
PSU_REF
1
1
C40
33nF
1
GND
2
2
1
1
4.7uF
R19
47k
1
/RESET
R18
C30
100nF
2
GND
2
2
1
1
2
C23
2
GND
GND
R31
3.3R
C26
100nF
2
C25
10uF
VREG
1
PVDD
C64
1000uF
3.3R
2
R30
1
1
2
OUT_RIGHT_R
VREG
2
C67
1000uF
2
C43
33nF
R32
1
GND
2
3.3R
R33
2
1
1
2
2
C33
100nF
PVDD
1
1
GND
1
GVDD/VDD (+12V)
3.3R
C32
100nF
GNDGND
Figure 14. Typical Differential (2N) BTL Application With BD Modulation Filters
16
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
3.3R
1
VDD (+12V)
2
GVDD (+12V)
1
1
GND
12
2
GND_A
PVDD_A
PVDD_A
OUT_A
BST_A
OUT_A
GVDD_A
GVDD_B
GND
GND
NC
NC
NC
NC
1
1
2
1uF
250V
33nF
10uH
1
2
2
2
1
+
10nF
63V
GND
-
1 2
1
1nF
63V
2
2.2uF
63V
37
36
2
1
38
GND
10nF
63V
1
1
39
1 2
1
2
1
2
40
3.3R
35
35
34
OUT_LEFT_M
GND
33
1
2
32
1000uF
63V
1
31
31
BST_D
OUT_D
30
30
29
29
28
28
27
27
17
1nF
63V
41
2
GND_D
3.3R
1uF
250V
2
GND_C
/OTW1
2
33nF
1
/SD
42
2.2uF
63V
2
GND_C
10uH
1
GND_D
NC
PVDD_D
OUT_C
PVDD_D
OUT_C
NC
OUT_D
TEST
/OTW2
16
16
PVDD_C
GVDD_D
15
PVDD_C
INPUT_D
GVDD_C
14
INPUT_C
25
13
BST_B
BST_C
26
26
12
GND
GND
45
43
43
VREG
GND
11
VREG
OUT_LEFT_P
46
44
44
TAS5631BPHD
24
24
10
10
GND
47
OUT_B
PVDD_B
AGND
GND
VREG
GND
M3
9
OUT_B
VI_CM
48
48
PVDD_B
INPUT_B
23
77
8
INPUT_A
M2
6.3V
100nF VREG
2
GND
GND_B
M1
1
6
C_STARTUP
21
GND
1
GND_B
20
4.7uF
GND_A
/RESET
22
5
100R
2
1000uF
63V
OC_ADJ
READY
4
1
PSU_REF
VDD
3
6.3V
GND
2
GND
GND
2
1
/CLIP
2
GND
1
4.7nF
GND
19
22.0k
1
1
18
2
IN_N
GND
1
49
51
50
52
53
54
56
55
57
58
60
61
59
63
62
64
2
GND
100R
2
GND
6.3V
100pF
IN_P
GND
10nF
63V
2
2
2
2
1
1
2.2uF
63V
4.7uF
GND
47k
100R
2
PVDD
3.3R
2.2uF
63V
2
1
VREG
/RESET
47uF
63V
1000uF
63V
1
GNDGND
2
1
10uH
1
1
2
1
33nF
1
2
2
2
2
GNDGND
2
2
1
100nF
100nF
100nF
2
10uF
1
1
1
3.3R
1
/OTW1
GND
1
GND
VREG
10uH
1
/OTW2
/CLIP
2
READY
33nF
3.3R
3.3R
1
2
GND
1
2
GVDD (+12V)
2
2
1
2
PVDD
1000uF
63V
2
GND
2
2.2uF
63V
/SD
100nF
1
1
100nF
GNDGND
Figure 15. Typical Differential (2N) BTL Application With BD Modulation Filters
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
17
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
3.3R
1
VDD (+12V)
2
1
1
1
1
3.3R
1
2
33nF
1
2
GVDD (+12V)
100nF
2
2
10uH
1
GNDGND
1
VREG
51
49
50
52
55
54
53
56
57
58
59
61
62
60
63
6.3V
GND
12
GND_A
PVDD_A
OUT_A
OUT_A
BST_A
GVDD_A
GVDD_B
GND
NC
GND
PVDD_A
PVDD_C
INPUT_D
PVDD_C
TEST
2
B
PVDD
1
42
42
2
47uF
63V
39
39
38
38
2.2uF
63V
37
37
36
36
3.3R
1
1
41
41
2.2uF
63V
12
40
40
10nF
63V
33nF
10uH
GND
2
1
GND
GND
C
35
35
34
34
GND
33
33
GND_D
PVDD_D
43
43
33nF
1
32
31
31
OUT_D
30
30
29
29
BST_D
28
28
26
26
27
27
25
17
PVDD_D
GND_D
OUT_D
/OTW1
GVDD_D
GND_C
GVDD_C
/SD
GND
GND_C
/OTW2
16
16
OUT_C
NC
GND
15
OUT_C
NC
M3
14
24
24
13
2.2uF
63V
2
INPUT_C
10uH
1
44
44
2
BST_C
GND
45
45
2
11
VREG
BST_B
TAS5631BPHD
VREG
10
10
GND
1
PVDD_B
AGND
9
100R
2
IN_D
NC
GND
8
GND
23
IN_C
100nF VREG
2
22
1
1
PVDD_B
46
46
1
7
7
6.3V
GND
100R
2
VI_CM
47
47
2
6
M2
1
OUT_B
M1
2
INPUT_B
21
1
OUT_B
20
2
IN_B
4.7uF
GND_B
INPUT_A
READY
100R
C_STARTUP
48
48
1
5
GND_B
1
4
GND_A
/RESET
2
6.3V
GND
OC_ADJ
1
3
/CLIP
IN_A
2
1
1
2
1
100R
NC
1
10nF
19
22.0k
2
18
2
GND
NC
VDD
2
GND
PSU_REF
100pF
2
PVDD
2
GND
64
1
1
1
2
100R
2
/RESET
A
2.2uF
63V
4.7uF
2
GND
47k
2
1
GND GND
2
100nF
100nF
2
10uF
2.2uF
63V
GND
/OTW1
PVDD
2
/SD
VREG
10uH
1
/OTW2
/CLIP
GND
2
READY
3.3R
GVDD (+12V)
2
1
1
10nF
63V
GND
2
1
2
1
1 2
2
2
1
21
2
1
2
2
3.3R
GND
1
2
2
10k
1%
OUT_C_M
10k
1%
470uF
50V
2
63V
10nF
1 2
-
GND
OUT_D_M
3.3R
1
2
2
2
2
3.3R
1
+
100nF
63V
1
470uF
50V
100nF
63V
470nF
250V
10k
2
1 2
2
GND
PVDD
2
2
1
2
100nF
63V
-
1
2
GND
R_COMP
+
1
21
12
10k
1%
470uF
50V
1
10k
1%
470uF
50V
100nF
63V
470nF
250V
10k
2
1 1
R_COMP
GND
OUT_D_P
D
1
2
3.3R
1
OUT_C_P
C
PVDD
2
1
1
1
196 kOhm
GND
10nF
63V
2
191 kOhm
10nF
63V
21
47 V
<47 V
2
63V
10nF
GND
1
191 kOhm
1
GND
1 1
48 V
63V
10nF
OUT_B_M
3.3R
2
12
169 kOhm
2
2
1
2
49 V
GND
-
GND
10k
1%
470uF
50V
3.3R
1
+
100nF
63V
1
150 kOhm
OUT_A_M
2
50 V
10k
1%
470uF
50V
100nF
63V
470nF
250V
10k
1 1
1 2
2
GND
PVDD
12
2
1
2
21
12
100nF
63V
-
1
2
R_COMP
R_COMP
+
10k
1%
470uF
50V
PVDD
1
2
1 1
10k
1%
470uF
50V
100nF
63V
470nF
250V
10k
GND
OUT_B_P
B
1
2
OUT_A_P
3.3R
1
2
R_COMP
2
1
3.3R
1
1
2
D
1
GNDGND
1
A
PVDD
2
100nF
100nF
10nF
63V
33nF
3.3R
1
2
2
1
2
GND
GND
1
2
63V
10nF
GND
Figure 16. Typical SE Application
18
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
GVDD (+12V)
1
PVDD
3.3R
1
VDD (+12V)
2
1000uF
63V
1
2
2
2
33nF
1
10uH
GNDGND
1 2
1
2
2
1
12
2
2
2
1
1
1
1
2
1
3.3R
GND
2
GND
OUT_LEFT_M
3.3R
2
1
2
-
GND
10k
1%
470uF
50V
1
+
100nF
63V
21
12
GND_D
470nF
250V
10k
10k
1%
1 2
PVDD
12
GND
33
OUT_LEFT_P
100nF
63V
1
34
2
R_COMP
2
35
35
1
2
2
GND
GND
1
63V
10nF
10nF
63V
2
GND
1
2
1
2
GND
2
2.2uF
63V
GND
1
2
1
2
2
1
2
1
GND
10uH
1
32
17
GND
470uF
50V
VREG
/SD
10nF
63V
10nF
63V
1
GND_D
PVDD_D
GND_C
/OTW1
PVDD_D
/SD
2.2uF
63V
2
GND_C
33nF
1 1
NC
2.2uF
63V
37
36
PVDD
3.3R
47uF
63V
1000uF
63V
39
1
OUT_C
OUT_CENTER_M
40
38
2
33nF
41
2
OUT_C
NC
42
-
3.3R
10uH
1
2.2uF
63V
GND
1 2
GND_A
PVDD_A
PVDD_A
OUT_A
OUT_A
BST_A
GVDD_A
GVDD_B
GND
GND
NC
NC
NC
TEST
/OTW2
16
16
PVDD_C
31
31
15
INPUT_D
30
30
14
PVDD_C
OUT_D
13
BST_C
INPUT_C
OUT_D
12
VREG
28
28
IN_RIGHT
VREG
1
43
43
BST_B
29
29
100R
2
44
44
PVDD_B
BST_D
11
GND
45
+
10nF
63V
46
OUT_B
TAS5631BPHD
AGND
GVDD_D
10
10
GND
GND
GVDD_C
9
26
26
8
25
77
27
27
IN_LEFT
6.3V
100nF VREG
2
GND
OUT_B
VI_CM
47
10nF
63V
1nF
63V
680nF
250V
48
48
PVDD_B
INPUT_B
GND
1
1
INPUT_A
24
24
GND
100R
2
6
GND
5
1
23
VREG
4.7uF
2
M3
4
GND
GND_B
22
1
GND_B
C_STARTUP
M2
IN_CENTER
6.3V
GND_A
/RESET
M1
100R
GND
OC_ADJ
READY
3
21
1
20
2
10nF
2
NC
VDD
GND
/CLIP
1
1nF
63V
GND
1
19
22.0k
18
2
PSU_REF
2
GND
2
1
2
49
50
51
53
52
55
56
54
57
58
60
59
61
64
62
6.3V
100pF
3.3R
680nF
250V
2
GND
2
1
63
1
2
2
1
/RESET
2.2uF
63V
4.7uF
2
GND
47k
OUT_CENTER_P
2
1
1
1
VREG
100R
2
1
1
1
GND GND
1
GND
2
2
2
100nF
2
10uF
1
1
1
3.3R
100nF
100nF
/OTW1
2
10uH
48 V
191 kOhm
47 V
191 kOhm
<47 V
196 kOhm
1 2
2
1
+
1 2
2
1
2
1 1
10k
1%
470uF
50V
100nF
63V
GND
-
GND
10k
1%
470uF
50V
2
GNDGND
470nF
250V
10k
12
169 kOhm
OUT_RIGHT_P
100nF
63V
OUT_RIGHT_M
3.3R
2
GND
1
2
150 kOhm
49 V
PVDD
12
50 V
2
100nF
100nF
R_COMP
1
R_COMP
1
PVDD
3.3R
1
2
2
1
3.3R
2
21
2
READY
33nF
3.3R
2
1
/CLIP
GND
1
1
/OTW2
63V
10nF
PVDD
GVDD (+12V)
Figure 17. Typical 2.1 System (2N) Input BTL and (1N) Input SE Application
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
19
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
R34
2
1
GVDD (+12V)
1
PVDD
1000uF
63V
2
GND
1
2
GND
GND
10uH
1
GND
2
1
GND
2
GND
11
100nF
12
100R
13
IN_RIGHT_N
2
R60
VREG
1
14
15
100R
16
17
18
19
20
VREG
21
22
AGND
PVDD_B
VREG
BST_B
INPUT_C
BST_C
INPUT_D
PVDD_C
TEST
OUT_C
NC
GND_C
NC
GND_D
/SD
OUT_D
/OTW
OUT_D
READY
PVDD_D
M1
PVDD_D
M2
BST_D
M3
GVDD_CD
1
2
2
1
1
2
1 2
2
37
OUT_LEFT_M
GND
PVDD
1
36
35
C41
2
34
2
33
1
1000uF 1000uF
63V
C91
2.2uF
33nF
C37
32
C90
2.2uF
33nF
1
31
63V
3.3R
47uF
63V
2.2uF
100V
10nF
100V
GND
GND
GND
GND
GND
GND
30
10uH
1
2
OUT_RIGHT_P
29
28
GND
27
C34
2.2uF
26
25
24
1
23
33nF
C88
3.3R
680nF
250V
1nF
100V
2
680nF
250V
+
1nF
100V
10nF
100V
GND
-
3.3R
2
/OTW
10nF
100V
2
1
GND
GND
/SD
1 2
1
2
1
2
OUT_B
1
1
GND_B
GND
2
IN_RIGHT_P
R53
10
VREG
VI_CM
2
9
C42
2
8
1
1
4.7uF
3.3R
10uH
2
2
38
1
GND
GND_A
680nF
250V
C83
2.2uF
39
-
GND
1 2
C85
1
100R
INPUT_B
40
1
R54
OUT_A
2
2
OUT_A
INPUT_A
2
IN_LEFT_N
PVDD_A
C_STARTUP
10nF
100V
1
7
/RESET
1nF
100V
1
6
+
1 2
5
GND
41
2
1
4.7nF
33nF
42
10nF
100V
1
2
PVDD_A
1
GND
100R
OC_ADJ
2
4
2
1
3
C33
1
43
2
1
24k
C45
GND
1
R14
BST_A
1nF
100V
44
1
2
VDD
GVDD_AB
2
GND
PSU_REF
1
R45
2
12
2
2
1
C78
100pF
100R
IN_LEFT_P
4.7uF
R44
47k
2
1
1
R13
2
2
1
/RESET
3.3R
680nF
250V
U16
TAS5631BDKD
2
1
2
2
1
GND
1
C86
VREG
OUT_LEFT_P
1
2
C35
100nF
12
1
VDD (+12V)
C44
10uF
C87
100nF
2
2
C38
100nF
1
1
1.5R
2
READY
10uH
1
2
OUT_RIGHT_M
1
PVDD
100nF
C84
2
1
1000uF
63V
GND
GVDD (+12V)
1
1
R31
2
2
2
100nF
C89
1.5R
GND
Figure 18. Typical Differential Input BTL Application With BD Modulation Filters, DKD Package
20
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5631B needs only a 12-V supply in addition to the (typical) 50-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path, including gate drive and
output stage, is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
gate-drive supply pins (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as a supply for all common circuits. Although supplied from the
same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300 kHz to 400 kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2.2-μF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5631B reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V powerstage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit. Moreover, the TAS5631B is fully protected against erroneous
power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within
the specified range (see the Recommended Operating Conditions table of this data sheet).
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The TAS5631B does not require a power-up sequence. The outputs of the H-bridges remain in a highimpedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage
protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not
specifically required, it is recommended to hold RESET in a low state while powering up the device. This allows
an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge
output.
Powering Down
The TAS5631B does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
21
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
ERROR REPORTING
The SD, OTW, OTW1, and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see the following table).
SD
OTW1
OTW2,
OTW
0
0
0
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
0
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
warning)
0
1
1
Overload (OLP) or undervoltage (UVP)
1
0
0
Junction temperature higher than 125°C (overtemperature warning)
1
0
1
Junction temperature higher than 100°C (overtemperature warning)
1
1
1
Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)
DESCRIPTION
NOTE
Aasserting RESET low forces the SD signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system microcontroller and responding
to an overtemperature warning signal by, e.g., turning down the volume to prevent further
heating of the device resulting in device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW
outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the
Electrical Characteristics table of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The TAS5631B contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5631B responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been
removed, i.e., the supply voltage has increased.
The device functions on errors, as shown in the following table.
BTL Mode
Local Error In
A
B
C
D
PBLT Mode
Turns Off
A+B
C+D
Local Error In
SE Mode
Turns Off
Local Error In
A
B
C
Turns Off
A
A+B+C+D
D
B
C
D
A+B
C+D
Bootstrap UVP does not shut down according to the table; it shuts down the respective half-bridge.
NOTE
In PBTL mode the device is protected against overload and load shorts, but shorting to
GND or PVDD during high load is not recommended
22
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
PIN-TO-PIN SHORT-CIRCUIT PROTECTION (PPSC)
The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the
demodulation filter, whereas PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup, i.e., when VDD is supplied; consequently, a short to either GND_X or PVDD_X after
system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on
the output, all half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the startup sequence and starts switching. The detection is controlled globally by a two-step sequence. The first step
ensures that there are no shorts from OUT_X to GND_X; the second step tests that there are no shorts from
OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC
filter. The typical duration is <15 ms/μF. While the PPSC detection is in progress, SD is kept low, and the device
does not react to changes applied to the RESET pin. If no shorts are present, the PPSC detection passes, and
SD is released. A device reset does not start a new PPSC detection. PPSC detection is enabled in BTL and
PBTL output configurations; the detection is not performed in SE mode. To make sure not to trip the PPSC
detection system, it is recommended not to insert resistive load between OUT_X and GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
The two different package options have individual overtemperature protection schemes.
PHD Package
The TAS5631B PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation. For highest reliability, the RESET should not be asserted until
OTW1 has cleared.
DKD Package
The TAS5631B DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. It is recommended to wait until OTW has cleared before asserting RESET.
Thereafter, the device resumes normal operation.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5631B fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach values stated in the Electrical
Characteristics table. Although GVDD_X and VDD are independently monitored, a supply-voltage drop below the
UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the highimpedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply
voltages have increased above the UVP threshold.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high-impedance state when
asserting the reset input low. Asserting the reset input low removes any fault information to be signaled on the
SD output, i.e., SD is forced high. A rising-edge transition on the reset input allows the device to resume
operation after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than
4 ms after the falling edge of SD.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
23
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
SYSTEM DESIGN CONSIDERATIONS
A rising-edge transition on the reset input allows the device to execute the startup sequence and start switching.
Apply only audio when the state of READY is high; that starts and stops the amplifier without having audible
artifacts that are heard in the output transducers. If an overcurrent protection event is introduced, the READY
signal goes low; hence, filtering is needed if the signal is intended for audio muting in non-microcontroller
systems.
The CLIP signal indicates that the output is approaching clipping. The signal can be used either to activate a
volume decrease or to signal an intelligent power supply to increase the rail voltage from low to high for optimum
efficiency.
The device inverts the audio signal from input to output.
The VREG pin is not recommended to be used as a voltage source for external circuitry.
Click and Pop in SE-Mode
The BTL startup has low click and pop due to the trimmed output dc offset, see the AUDIO CHARACTERISTICS
(BTL) table.
The startup of the BTL+2 x SE system (Figure 17) or 4xSE (Figure 16) is more difficult to get click and pop free,
than the pure BTL solution; therefore, evaluating the resulting click and pop before designing in the device is
recommended.
PBTL Overload and Short Circuit
The TAS5631B has extensive overload and short circuit protection. In BTL and SE mode, it is fully protected
against speaker terminal overloads, and terminal-to-terminal short circuit, and short circuit to GND or PVDD. The
protection works by limiting the current, by flipping the state of the output MOSFET’s; thereby, ramping currents
down in the inductor. This only works when the inductor is NOT saturated, the recommended minimum inductor
values are listed in RECOMMENDED OPERATING CONDITIONS table. In BTL mode, the short circuit currents
can reach more than 15A, so when connecting the device in PBTL mode (Mono), the currents double – that is
more than 30 A, and with these high currents, the protection system will limit PBTL speaker overloads, terminalto-terminal shorts, and terminal-to-GND shorts. PBTL mode short circuit to PVDD is not recommended.
PRINTED CIRCUIT BOARD RECOMMENDATION
Use an unbroken ground plane to have good low-impedance and -inductance return path to the power supply for
power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high, fast-switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
for the audio input should be kept short and together with the accompanying audio source ground. It is important
to keep a solid local ground area underneath the device to minimize ground bounce. It is always good practice to
follow the EVM layout as a guideline,
Netlist for this printed circuit board is generated from the schematic in Figure 15.
24
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
Note T1: PVDD decoupling bulk capacitors C60–C64 should be as close as possible to the PVDD and GND_X pins;
the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and
without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low-impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins. This is valid for C60, C61, C62, and C63.
Note T3: Heat sink must have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range, and preferably metal film types.
Figure 19. Printed Circuit Board – Top Layer
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
25
TAS5631B
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
Note B1: It is important to have a direct, low-impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low-impedance X7R ceramic capacitors placed on bottom side provide a short low-inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors
Figure 20. Printed Circuit Board – Bottom Layer
26
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
TAS5631B
www.ti.com
SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
REVISION HISTORY
Changes from Original (October 2010) to Revision A
Page
•
Changed Title From: 600-W MONO To 400-W MONO ........................................................................................................ 1
•
Changed Feature From: 600 W per Channel in Mono PBTL Configuration To: 400 W per Channel in Mono PBTL
Configuration ......................................................................................................................................................................... 1
•
Changed the DKD package to Product Preview ................................................................................................................... 2
•
Changed the Mode Selection Pins table .............................................................................................................................. 3
•
Replaced the PACKAGE HEAT DISSIPATION RATINGS table with the Thermal Information table .................................. 3
•
Changed TAS5631BDKD From: Product Preview To; Active .............................................................................................. 3
•
Added PVDD_X to GND_X; DC voltage to the Abs Max Table ........................................................................................... 4
•
Changed the Abs Max storage Temperature From: –40 to 150 To: –40 to 125 .................................................................. 4
•
Added footnotes to the ROC table ........................................................................................................................................ 4
•
Changed RL(PBLT) Min value From: 1.8 To 2.4 Ω, Typ Value From: 2 To 3 Ω ................................................................... 4
•
Added ROCP information to the ROC Table ........................................................................................................................... 4
•
Changed the description of Pins PVDD_A, PVDD_B, PVDD_C, PVDD_D ......................................................................... 5
•
AUDIO CHARACTERISTICS (BTL) table -Changed LDEM = 7 μH, to 10 µH (Conditions statement). Changed |VOS|
values From Typ = 20 Max = 50 To: Typ = 15 MAx = 40. Changed Pidle test conditions From: PO = 0 To: PO = 4 ............. 8
•
Changed AUDIO CHARACTERISTICS (BTL), |VOS| - From: Typ = 20 MAx = 50 To: Typ = 15 Max = 40 .......................... 8
•
Changed AUDIO CHARACTERISTICS (BTL), PIdle - PO = 4, four channels To: PO = 0, all channels ................................. 8
•
Changed LDEM = 7 μH To: LDEM = 10 μH in the AUDIO SPECIFICATION (Single-Ended Output) conditions
statement .............................................................................................................................................................................. 8
•
Electrical Characterics - Changed Vuvp,G Typ value From: 10 To: 9.5, changed the IOC Test Conditions, Deleted IOCT .... 10
•
Changed IOC Typical valuesFrom: 19A To: 15A ................................................................................................................. 10
•
Changed the TYPICAL CHARACTERISTICS, BTL CONFIGURATION graphs ................................................................ 11
•
Changed the TYPICAL CHARACTERISTICS, BTL CONFIGURATION graphs ................................................................ 12
•
Replaced the TYPICAL CHARACTERISTICS, PBTL CONFIGURATION graphs ............................................................. 14
•
Changed the PVDD CAPACITOR RECOMMENDATION section ...................................................................................... 15
•
DECOUPLING CAPACITOR RECOMMENDATION section - Changed From: 0.1-μF capacitor To: 2.2-μF capacitor ..... 15
•
Changed Figure 14, Figure 15, Figure 16, Figure 17, and Figure 18 ................................................................................. 16
•
Added Note to the DEVICE PROTECTION SYSTEM section ........................................................................................... 22
•
Added section - Click and Pop in SE-Mode ....................................................................................................................... 24
•
Added section - PBTL Overload and Short Circuit ............................................................................................................. 24
Changes from Revision A (November 2010) to Revision B
Page
•
ChangedRINT_PU parameters From: OTW1 to VREG, OTW2 to VREG, SD to VREG To: OTW, OTW1, OTW2, CLIP,
READY, SD to VREG ......................................................................................................................................................... 10
•
Added text to the PHD Package section ............................................................................................................................ 23
•
Added text to the DKD Package section ............................................................................................................................ 23
Changes from Revision B (November 2011) to Revision C
•
Page
Deleted - RL = 2 Ω, 10%, THD+N, clipped input signal From PO in the Audio Specification (PBTL) table .......................... 9
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TAS5631B
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TAS5631BDKD
ACTIVE
HSSOP
DKD
44
29
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
0 to 70
TAS5631B
TAS5631BDKDR
ACTIVE
HSSOP
DKD
44
500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
0 to 70
TAS5631B
TAS5631BPHD
ACTIVE
HTQFP
PHD
64
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
0 to 70
TAS5631B
TAS5631BPHDR
ACTIVE
HTQFP
PHD
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
0 to 70
TAS5631B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TAS5631BDKDR
HSSOP
DKD
44
500
330.0
24.4
TAS5631BPHDR
HTQFP
PHD
64
1000
330.0
24.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
14.7
16.4
4.0
20.0
24.0
Q1
17.0
17.0
1.5
20.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5631BDKDR
HSSOP
DKD
TAS5631BPHDR
HTQFP
PHD
44
500
367.0
367.0
45.0
64
1000
367.0
367.0
45.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated