Technical Reference Guide
HP Compaq dx7300 and dc7700 Series
Business Desktop Computers
Document Part Number: 433473-001
September 2006
This document provides information on the design, architecture, function,
and capabilities of the HP Compaq dx7300 and dc7700 Series Business
Desktop Computers. This information may be used by engineers,
technicians, administrators, or anyone needing detailed information on
the products covered.
© Copyright 2006 Hewlett-Packard Development Company, L.P.
The information contained herein is subject to change without notice.
Microsoft, MS-DOS, Windows, and Windows NT are trademarks of Microsoft Corporation in the U.S. and other
countries.
Intel, Pentium, Intel Inside, and Celeron are trademarks of Intel Corporation in the U.S. and other countries.
Adobe, Acrobat, and Acrobat Reader are trademarks or registered trademarks of Adobe Systems Incorporated.
The only warranties for HP products and services are set forth in the express warranty statements accompanying
such products and services. Nothing herein should be construed as constituting an additional warranty. HP shall
not be liable for technical or editorial errors or omissions contained herein.
This document contains proprietary information that is protected by copyright. No part of this document may be
photocopied, reproduced, or translated to another language without the prior written consent of Hewlett-Packard
Company.
!
WARNING: Text set off in this manner indicates that failure to follow directions could result in bodily
harm or loss of life.
CAUTION: Text set off in this manner indicates that failure to follow directions could result in damage to
equipment or loss of information.
✎ Text set off in this manner provides infomation that may be helpful.
Technical Reference Guide
HP Compaq dx7300 and dc7700 Series Business Desktop Computers
First Edition (September 2006)
Document Part Number: 433473-001
Contents
1 Introduction
1.1 About this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 Online Viewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 Hardcopy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Additional Information Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Model Numbering Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Notational Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.2 Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.3 Register Notation and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.4 Bit Notation and Byte Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Common Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–1
1–1
1–1
1–1
1–2
1–3
1–3
1–3
1–3
1–3
1–3
1–4
2 System Overview
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2.3 Mechanical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2.3.1 Cabinet Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
2.3.2 Chassis Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
2.3.3 Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
2.4 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
2.4.1 Intel Processor Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
2.4.2 Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
2.4.3 Support Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
2.4.4 System Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
2.4.5 Mass Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
2.4.6 Serial and Parallel Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
2.4.7 Universal Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
2.4.8 Network Interface Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
2.4.9 Graphics Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
2.4.10Audio Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
2.5 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
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3 Processor/Memory Subsystem
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Pentium 4 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Processor Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Processor Upgrading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1
3–2
3–2
3–3
3–4
4 System Support
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.2 PCI Bus Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.2.1 PCI 2.3 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4.2.2 PCI Express Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
4.2.3 Option ROM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
4.2.4 PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
4.2.5 PCI Power Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
4.2.6 PCI Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
4.3 System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4.3.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
4.3.2 Direct Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16
4.4 Real-Time Clock and Configuration Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
4.4.1 Clearing CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
4.4.2 Standard CMOS Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
4.5 System Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
4.5.1 Security Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
4.5.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
4.5.3 System Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
4.5.4 Thermal Sensing and Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
4.6 Register Map and Miscellaneous Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24
4.6.1 System I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24
4.6.2 SCH5317 I/O Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25
5 Input/Output Interfaces
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5.2 SATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5.2.1 SATA Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5.2.2 SATA Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
5.2.3 RAID Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
5.3 Diskette Drive Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
5.3.1 Diskette Drive Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
5.3.2 Diskette Drive Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
5.4 Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
5.4.1 Serial Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
5.4.2 Serial Interface Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
5.5 Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
5.5.1 Standard Parallel Port Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
5.5.2 Enhanced Parallel Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
5.5.3 Extended Capabilities Port Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
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5.6
5.7
5.8
5.9
5.5.4 Parallel Interface Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.5 Parallel Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard/Pointing Device Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.1 Keyboard Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.2 Pointing Device Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.3 Keyboard/Pointing Device Interface Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.4 Keyboard/Pointing Device Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Serial Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1 USB Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.2 USB Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.3 USB Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.4 USB Cable Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.1 HD Audio Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.2 HD Audio Link Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.3 Audio Codec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.4 Audio Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.5 Audio Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Network Interface Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.1 Wake-On-LAN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.2 Alert Standard Format Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.3 Power Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.4 NIC Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.5 NIC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.6 NIC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–12
5–14
5–15
5–15
5–17
5–17
5–21
5–22
5–23
5–24
5–25
5–26
5–27
5–28
5–28
5–29
5–30
5–32
5–33
5–34
5–34
5–34
5–35
5–35
5–36
6 Integrated Graphics Subsystem
6.1
6.2
6.3
6.4
6.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Display Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Upgrading 845G-Based Graphics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VGA Monitor Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1
6–2
6–4
6–5
6–6
7 Power and Signal Distribution
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
7.2 Power Supply Assembly/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
7.2.1 Power Supply Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2
7.2.2 Power Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
7.2.3 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7
7.3 Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8
7.4 Signal Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10
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8 BIOS ROM
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
8.2 ROM Flashing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
8.2.1 Upgrading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
8.2.2 Changeable Splash Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
8.3 Boot Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
8.3.1 Boot Device Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
8.3.2 Network Boot (F12) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4
8.3.3 Memory Detection and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4
8.3.4 Boot Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5
8.4 Setup Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
8.5 Client Management Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15
8.5.1 System ID and ROM Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15
8.5.2 Temperature Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15
8.5.3 Drive Fault Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15
8.6 SMBIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–17
8.7 USB Legacy Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–17
A Error Messages and Codes
B ASCII Character Set
C Keyboard
Index
8
www.hp.com
Technical Reference Guide
1
Introduction
1.1
About this Guide
This guide provides technical information about HP Compaq dx7300 and dc7700 series personal
computers that feature Intel Pentium processors and the Intel Q965 chipset. This document
describes in detail the system's design and operation for programmers, engineers, technicians,
and system administrators, as well as end-users wanting detailed information.
The chapters of this guide primarily describe the hardware and firmware elements and primarily
deal with the system board and the power supply assembly. The appendices contain general data
such as error codes and information about standard peripheral devices such as keyboards,
graphics cards, and communications adapters.
This guide can be used either as an online document or in hardcopy form.
1.1.1 Online Viewing
Online viewing allows for quick navigating and convenient searching through the document. A
color monitor will also allow the user to view the color shading used to highlight differential
data. A softcopy of the latest edition of this guide is available for downloading in .pdf file format
at the URL listed below: www.hp.com
Viewing the file requires a copy of Adobe Acrobat Reader available at no charge from Adobe
Systems, Inc. at the following URL: www.adobe.com
1.1.2 Hardcopy
A hardcopy of this guide may be obtained by printing from the .pdf file. The document is
designed for printing in an 8 ½ x 11-inch format. Note that printing in black and white will lose
color shading properties.
1.2
Additional Information Sources
For more information on components mentioned in this guide refer to the indicated
manufacturers' documentation, which may be available at the following online sources:
1.3
■
HP Corporation: www.hp.com
■
Intel Corporation: www.intel.com
■
Standard Microsystems Corporation: www.smsc.com
■
Serial ATA International Organization (SATA-IO) : www.serialATA.org.
■
USB user group: www.usb.org
Model Numbering Convention
The model numbering convention for HP systems is as follows:
Technical Reference Guide
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1-1
Introduction
1-2
www.hp.com
Technical Reference Guide
Introduction
1.4
Serial Number
The unit's serial number is located on a sticker placed on the exterior cabinet. The serial number
is also written into firmware and may be read with HP Diagnostics or Insight Manager utilities.
1.5
Notational Conventions
The notational guidelines used in this guide are described in the following subsections.
1.5.1 Values
Hexadecimal values are indicated by a numerical or alpha-numerical value followed by the letter
“h.” Binary values are indicated by a value of ones and zeros followed by the letter “b.”
Numerical values that have no succeeding letter can be assumed to be decimal unless otherwise
stated.
1.5.2 Ranges
Ranges or limits for a parameter are shown using the following methods:
Example A:
Bits <7..4> = bits 7, 6, 5, and 4.
Example B:
IRQ3-7, 9 = IRQ signals 3 through 7, and IRQ signal 9
1.5.3 Register Notation and Usage
This guide uses standard Intel naming conventions in discussing the microprocessor's (CPU)
internal registers. Registers that are accessed through programmable I/O using an indexing
scheme are indicated using the following format:
03C5.17h
Index port
Data port
In the example above, register 03C5.17h is accessed by writing the index port value 17h to the
index address (03C4h), followed by a write to or a read from port 03C5h.
1.5.4 Bit Notation and Byte Values
Bit designations are labeled between brackets (i.e., “bit <0 >”). Binary values are shown with the
most significant bit (MSb) on the far left, least significant bit (LSb) at the far right. Byte values in
hexadecimal are also shown with the MSB on the left, LSB on the right.
Technical Reference Guide
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1-3
Introduction
1.6
Common Acronyms and Abbreviations
Table 1-1 lists the acronyms and abbreviations used in this guide.
Table 1-1
Acronyms and Abbreviations
1-4
Acronym or
Abbreviation
Description
A
ampere
AC
alternating current
ACPI
Advanced Configuration and Power Interface
A/D
analog-to-digital
ADC
Analog-to-digital converter
ADD or ADD2
Advanced digital display (card)
AGP
Accelerated graphics port
API
application programming interface
APIC
Advanced Programmable Interrupt Controller
APM
advanced power management
AOL
Alert-On-LAN™
ASIC
application-specific integrated circuit
ASF
Alert Standard Format
AT
1. attention (modem commands) 2. 286-based PC architecture
ATA
AT attachment (IDE protocol)
ATAPI
ATA w/packet interface extensions
AVI
audio-video interleaved
AVGA
Advanced VGA
AWG
American Wire Gauge (specification)
BAT
Basic assurance test
BCD
binary-coded decimal
BIOS
basic input/output system
bis
second/new revision
BNC
Bayonet Neill-Concelman (connector type)
bps or b/s
bits per second
BSP
Bootstrap processor
BTO
Built to order
CAS
column address strobe
CD
compact disk
CD-ROM
compact disk read-only memory
CDS
compact disk system
CGA
color graphics adapter
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Technical Reference Guide
Introduction
Table 1-1
Acronyms and Abbreviations
Acronym or
Abbreviation
Description
Ch
Channel, chapter
cm
centimeter
CMC
cache/memory controller
CMOS
complimentary metal-oxide semiconductor (configuration memory)
Cntlr
controller
Cntrl
control
codec
1. coder/decoder 2. compressor/decompressor
CPQ
Compaq
CPU
central processing unit
CRIMM
Continuity (blank) RIMM
CRT
cathode ray tube
CSM
1. Compaq system management 2. Compaq server management
DAC
digital-to-analog converter
DC
direct current
DCH
DOS compatibility hole
DDC
Display Data Channel
DDR
Double data rate (memory)
DIMM
dual inline memory module
DIN
Deutche IndustriNorm (connector type)
DIP
dual inline package
DMA
direct memory access
DMI
Desktop management interface
dpi
dots per inch
DRAM
dynamic random access memory
DRQ
data request
DVI
Digital video interface
dword
Double word (32 bits)
EDID
extended display identification data
EDO
extended data out (RAM type)
EEPROM
electrically eraseable PROM
EGA
enhanced graphics adapter
EIA
Electronic Industry Association
EISA
extended ISA
EPP
enhanced parallel port
EIDE
enhanced IDE
Technical Reference Guide
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1-5
Introduction
Table 1-1
Acronyms and Abbreviations
1-6
Acronym or
Abbreviation
Description
ESCD
Extended System Configuration Data (format)
EV
Environmental Variable (data)
ExCA
Exchangeable Card Architecture
FIFO
first in/first out
FL
flag (register)
FM
frequency modulation
FPM
fast page mode (RAM type)
FPU
Floating point unit (numeric or math coprocessor)
FPS
Frames per second
ft
Foot/feet
GB
gigabyte
GMCH
Graphics/memory controller hub
GND
ground
GPIO
general purpose I/O
GPOC
general purpose open-collector
GART
Graphics address re-mapping table
GUI
graphic user interface
h
hexadecimal
HW
hardware
hex
hexadecimal
Hz
Hertz (cycles-per-second)
ICH
I/O controller hub
IDE
integrated drive element
IEEE
Institute of Electrical and Electronic Engineers
IF
interrupt flag
I/F
interface
IGC
integrated graphics controller
in
inch
INT
interrupt
I/O
input/output
IPL
initial program loader
IrDA
Infrared Data Association
IRQ
interrupt request
ISA
industry standard architecture
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Technical Reference Guide
Introduction
Table 1-1
Acronyms and Abbreviations
Acronym or
Abbreviation
Description
Kb/KB
kilobits/kilobytes (x 1024 bits/x 1024 bytes)
Kb/s
kilobits per second
kg
kilogram
KHz
kilohertz
kV
kilovolt
lb
pound
LAN
local area network
LCD
liquid crystal display
LED
light-emitting diode
LPC
Low pin count
LSI
large scale integration
LSb/LSB
least significant bit/least significant byte
LUN
logical unit (SCSI)
m
Meter
MCH
Memory controller hub
MMX
multimedia extensions
MPEG
Motion Picture Experts Group
ms
millisecond
MSb/MSB
most significant bit/most significant byte
mux
multiplex
MVA
motion video acceleration
MVW
motion video window
n
variable parameter/value
NIC
network interface card/controller
NiMH
nickel-metal hydride
NMI
non-maskable interrupt
NRZI
Non-return-to-zero inverted
ns
nanosecond
NT
nested task flag
NTSC
National Television Standards Committee
NVRAM
non-volatile random access memory
OS
operating system
PAL
1. programmable array logic 2. phase alternating line
PATA
Parallel ATA
Technical Reference Guide
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1-7
Introduction
Table 1-1
Acronyms and Abbreviations
1-8
Acronym or
Abbreviation
Description
PC
Personal computer
PCA
Printed circuit assembly
PCI
peripheral component interconnect
PCI-E
PCI Express
PCM
pulse code modulation
PCMCIA
Personal Computer Memory Card International Association
PEG
PCI express graphics
PFC
Power factor correction
PIN
personal identification number
PIO
Programmed I/O
PN
Part number
POST
power-on self test
PROM
programmable read-only memory
PTR
pointer
RAID
Redundant array of inexpensive disks (drives)
RAM
random access memory
RAS
row address strobe
rcvr
receiver
RDRAM
(Direct) Rambus DRAM
RGB
red/green/blue (monitor input)
RH
Relative humidity
RMS
root mean square
ROM
read-only memory
RPM
revolutions per minute
RTC
real time clock
R/W
Read/Write
SATA
Serial ATA
SCSI
small computer system interface
SDR
Singles data rate (memory)
SDRAM
Synchronous Dynamic RAM
SDVO
Serial digital video output
SEC
Single Edge-Connector
SECAM
sequential colour avec memoire (sequential color with memory)
SF
sign flag
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Technical Reference Guide
Introduction
Table 1-1
Acronyms and Abbreviations
Acronym or
Abbreviation
Description
SGRAM
Synchronous Graphics RAM
SIMD
Single instruction multiple data
SIMM
single in-line memory module
SMART
Self Monitor Analysis Report Technology
SMI
system management interrupt
SMM
system management mode
SMRAM
system management RAM
SPD
serial presence detect
SPDIF
Sony/Philips Digital Interface (IEC-958 specification)
SPN
Spare part number
SPP
standard parallel port
SRAM
static RAM
SSE
Streaming SIMD extensions
STN
super twist pneumatic
SVGA
super VGA
SW
software
TAD
telephone answering device
TAFI
Temperature-sensing And Fan control Integrated circuit
TCP
tape carrier package, transmission control protocol
TF
trap flag
TFT
thin-film transistor
TIA
Telecommunications Information Administration
TPE
twisted pair ethernet
TPI
track per inch
TTL
transistor-transistor logic
TV
television
TX
transmit
UART
universal asynchronous receiver/transmitter
UDMA
Ultra DMA
URL
Uniform resource locator
us/µs
microsecond
USB
Universal Serial Bus
UTP
unshielded twisted pair
V
volt
Technical Reference Guide
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1-9
Introduction
Table 1-1
Acronyms and Abbreviations
1-10
Acronym or
Abbreviation
Description
VAC
Volts alternating current
VDC
Volts direct current
VESA
Video Electronic Standards Association
VGA
video graphics adapter
VLSI
very large scale integration
VRAM
Video RAM
W
watt
WOL
Wake-On-LAN
WRAM
Windows RAM
ZF
zero flag
ZIF
zero insertion force (socket)
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Technical Reference Guide
2
System Overview
2.1
Introduction
The HP Compaq dx7300 and dc7700 Series Business Desktop Computers (Figure 2-1) deliver an
outstanding combination of manageability, serviceability, and compatibility for enterprise
environments. Based on the Intel Pentium 4 processor with the Intel Q965 Express chipset, these
systems emphasize performance along with industry compatibility. These models feature a
similar architecture incorporating both PCI 2.3 and PCIe buses. All models are easily
upgradeable and expandable to keep pace with the needs of the office enterprise.
HP Compaq dx7300 ST
HP Compaq dc7700 USDT
HP Compaq dx7300 MT
HP Compaq dc7700 SFF
HP Compaq dc7700 CMT
Figure 2-1. HP Compaq dx7300and dc7700 Series Business Desktop Computers
This chapter includes the following topics:
■
Features (2.2)
■
Mechanical design (2.3)
■
System architecture (2.4)
■
Specifications (2.5)
Technical Reference Guide
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2-1
System Overview
2.2 Features
The following standard features are included on all series unless otherwise indicated:
2-2
■
Intel Pentium processor in LGA775 (Socket T) package
■
Integrated graphics controller
■
PC2-6400 and PC2-5300 DIMM support on all models
■
Serial ATA (SATA) interfaces supporting transfer rates up to 3.0 Gbps and RAID operation
for dual drive arrays
■
PCI 2.3 and PCI Express interfaces
■
Hard drive fault prediction
■
Eight USB 2.0-compliant ports
■
High definition (HD) audio processor with one headphone output, at least one microphone
input, one line output, and one line input
■
Network interface controller providing 10/100/1000Base T support
■
Plug 'n Play compatible (with ESCD support)
■
Intelligent Manageability support
■
Energy Star compliant
■
Security features including:
❏
Flash ROM Boot Block
❏
Diskette drive disable, boot disable, write protect
❏
Power-on password
❏
Administrator password
❏
Serial/parallel port disable
❏
hood (cover) sense
❏
USB port disable
■
PS/2 enhanced keyboard
■
PS/2 scroll mouse
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Technical Reference Guide
System Overview
Table 2-1 shows the differences in features between the different PC series based on form factor:
Table 2-1
Difference Matrix by Form Factor
USDT
SFF
ST
MT
CMT
Series
dc7700
dc7700
dx7300
dx7300
dc7700
System Board Type
custom
custom
custom
µATX
µATX
Optional [1]
Standard
Standard
Standard
Standard
3
3 GB
DDR2
4
4 GB
DDR2
4
4 GB
DDR2
4
4 GB
DDR2
4
4 GB
DDR2
1
1
2
1
2
1
4
2
4
2
1 [2a]
0
1 [3] [4]
1 [4]
1 [3] [4]
1 [4]
1 [5]
1
1 [5]
1
2
full-height
2 or 4
full-height [7]
Serial and parallel ports
Memory:
# of sockets
Maximum memory
Memory type
Drive bays:
Externally accessible
Internal
PCI Express slots:
x16 graphics
x1
PCI 2.3 32-bit 5-V slots
1full-height
[2b]
Smart Cover Sensor /
Smart Cover Lock
Sensor only
Both
Both
Both
Both
200-watt
Active
Yes
240-watt
Active
Yes
240-watt
Active
Yes
365-watt
Active
Yes
365-watt
Active
Yes
Power Supply:
Power rating
PFC type
Auto-ranging
2 half-height
2 half-height
or
or
2 full-height [6] 2 full-height [6]
NOTES:
[1] Supported on system board. Requires optional cable/bracket assembly.
[2] Configuration choice of:
a) 1 low-profile PCIe x16 graphics card support: height = 3.99 in., lenght = 6.60 in. when
optional PCI Express riser card is installed.
Or
b) 1 full height PCI card support when optional PCI riser is installed.
[3] Accepts low-profile, reversed-layout ADD2/SDVO PCI-E card: height = 2.5 in., length = 6.6 in.
[4] Slot not accessible in configuration using PCI riser card.
[5] Accepts standard height, normal (non-reversed) layout ADD2/SDVO card: height = 4.2 in.,
length = 10.5 in.
[6] Full-height PCI slots require installation of PCI riser card field option.
Half-height dimensions: height = 2.5 in., length = 6.6 in.
Full-hieght dimensions: height = 4.2 in., length = 6.875 in
[7] PCI expansion board required for 4-slot support.
Full-height dimensions: height = 4.2 in., length = 6.875 in
Technical Reference Guide
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2-3
System Overview
2.3
Mechanical Design
This guide covers five form factors:
■
Ultra-slim Desktop (USDT)—Very slim design that can be used in a tradition desktop
(horizontal) orientation or as a small tower mounted in the supplied tower stand.
■
Small Form Factor (SFF)—A small footprint design that can be used in a desktop
configuration (default) or as a small tower mounted in a tower stand.
■
Slim Tower (ST)—Slim design that can be used in a tradition desktop (horizontal)
orientation or as a small tower (default) mounted in the supplied tower stand.
■
MicroTower (MT)—Compact tower design that is easily placed on a desktop or floor
■
Convertible Minitower (CMT) —an ATX-type unit providing the most expandability and
being adaptable to desktop (horizontal) or floor-standing (vertical) placement.
The following subsections describe the mechanical (physical) aspects of models.
CAUTION: Voltages are present within the system unit whenever the unit is plugged into a live AC outlet,
regardless of the system's “Power On” condition. Always disconnect the power cable from the power
outlet and/or from the system unit before handling the system unit in any way.
✎
2-4
The following information is intended primarily for identification purposes only. Before servicing these systems,
refer to the applicable Service Reference Guide. Service personnel should review training materials also
available on these products.
www.hp.com
Technical Reference Guide
System Overview
2.3.1 Cabinet Layouts
Front Views
Figure 2-2 shows the front panel components of the Ultra Slim Desktop (USDT) format factor.
1
2
3
4
5 6 7 8
Item
Description
Item
Decription
1
Slimline drive bay
5
USB ports 7, 8
2
CD-ROM eject button
6
HD activity LED
3
Microphone audio In jack
7
Power LED
4
Headphone audio Out jack
8
Power button
Figure 2-2. HP Compaq dc7700 USDT Front View
Technical Reference Guide
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2-5
System Overview
Figure 2-3 shows the front panel components of the Small Form Factor (SFF). and Slim Tower
(ST)
Item
Description
Item
Decription
1
Diskette drive activity LED
7
Microphone audio In jack
2
Diskette drive media door
8
Headphone audio Out jack
3
CD-ROM drive acitvity LED
9
USB ports 7, 8
4
Diskette drive eject button
10
Hard drive activity LED
5
CD-ROM media tray
11
Power LED
6
CD-ROM drive open/close button
12
Power button
Figure 2-3. HP Compaq dc7700 SFF (left)/dx7300 ST (right) Front View
2-6
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Technical Reference Guide
System Overview
Figure 2-4 shows the front panel components of the microtower (uT) form factor.
Item
Description
Item
Decription
1
CD-ROM drive
7
CD-ROM drive open/close button
2
CD-ROM drive activity LED
8
Power button
3
Diskette drive media door
9
Power LED
4
Diskette drive activity LED
10
Hard drive activity LED
5
Diskette drive eject button
11
Headphone audio Out jack
6
USB ports 7, 8
12
Microphone audio In jack
Figure 2-4. HP Compaq dx7300 MT Front View
Technical Reference Guide
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2-7
System Overview
Figure 2-5 shows the front panel components of the Convertable Minitower (CMT) form factor.
Item
Description
Item
Decription
1
CD-ROM drive
7
CD-ROM drive open/close button
2
CD-ROM drive activity LED
8
Power button
3
Diskette drive media door
9
Power LED
4
Diskette drive activity LED
10
USB ports 7, 8
5
Diskette drive eject button
11
Headphone audio Out jack
6
Hard drive activity LED
12
Microphone audio In jack
Figure 2-5. HP Compaq dc7700 CMT Front View
2-8
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Technical Reference Guide
System Overview
Rear Chassis Connections
Table 2-2 describes the signal connections available on the rear panels of the dx7300 and dc7700
models. Note that not all connectors listed are provided on all form factors.
Table 2-2
Rear Panel Signal Connections
Connector & Icon
Description
AC input connector.
(no icon)
PS/2 female connector (color-coded purple) for keyboard
interface.
PS/2 female connector (color-coded green) for mouse interface
Universal serial bus (USB) connector for USB interface
DB-9 male connector for RS-232 serial (COM1 or COM2)
interface.
RJ-45 jack for Local Area Network (LAN) interface.
DB-25 female connetor for parallel (LPT1) interface.
DB-15 female connector for video monitor.
1/8 inch, 3-conductor phone jack (color-coded blue) for stereo
audio line input.
1/8-inch, 3-conductor phone jack (color-coded green) for stereo
audio line output.
1/8-inch, 3-conductor phone jack (color-coded pink) for stereo
audio microphone input.
Technical Reference Guide
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2-9
System Overview
2.3.2 Chassis Layouts
This section describes the internal layouts of the chassis. For detailed information on servicing
the chassis refer to the multimedia training and/or the maintenance and service guide for these
systems.
UIltra Slim Desktop Chassis
The Ultra Slim Desktop (USDT) chassis used for the HP Compaq dc7700 models uses a
compact, space-saving form factor.
1
3
2
7
4
5
6
Item
Description
Item
Description
1
Power supply assembly
5
Chassis fan
2
DIMM sockets (3)
6
Slimline Optical Drive bay
3
PCI or PCIe riser card cage
7
Hard drive (under item 6)
4
Processor socket
--
--
Figure 2-6. USDT Chassis Layout, TopView
2-10
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Technical Reference Guide
System Overview
Small Form Factor / Slim Tower Chassis
The chassis layouts for the Small Form Factor (SFF) used for the HP Compaq dc7700 models
and the Slim Tower (ST) used for the HP Comapq dx7300 models are shown in Figure 2-8.
Features include:
■
Tilting drive cage assembly for easy access to processor and memory sockets
■
Two configurations available:
❏
Without card cage:
❏
◆
Two half-height, full length PCI 2.3 slots
◆
One PCI Express x16 graphics/SDVO reverse-layout slot
◆
One PCI Express x1 slot
With card cage:
◆
Two full-height, full-length PCI 2.3 slots
2 345
1
- 9 8
2
1
-
7
9
6
8 7
Chassis with card cage
Chassis without card cage
Item
Description
Item
Description
1
Power supply assembly
6
Card cage
2
DIMM sockets (4)
7
Processor socket
3
PCI Express x1 slot
8
Chassis fan
4
PCI Express x16
graphics/reverse-layout slot [1]
9
Optical drive bay
5
PCI 2.3 slots (2)
10
Diskette drive bay (under item 9)
NOTE:
[1] Accepts PCI-E graphics or reversed-layout ADD2 card.
Figure 2-7. SFF / ST Chassis Layout, Top / Right Side Views
Technical Reference Guide
www.hp.com
2-11
System Overview
Microtower Chassis
Figure 2-8 shows the layout for the Microtower (MT) chassis used for the HP Compaq dx7300
models. Features include:
■
Externally accessible drive bay assembly.
■
Easy access to expansion slots and all socketed system board components.
1
2 3
4
5
6
q
9
8
7
Item
Description
Item
Description
1
Power supply assembly
7
Speaker
2
Processor socket
8
PCI 2.3 slots
3
DIMM sockets (4)
9
PCI Express x1 slot
4
DriveLock
10
PCI Express x16 graphics/normal-layout
SDVO slot [1]
5
Externally accessible
drive bays
11
Chassis fan
6
Internally accessible
drive bays
--
--
NOTE:
[1] Accepts PCI-E graphics or normal-layout ADD2 card.
Figure 2-8. MT Chassis Layout, Left Side View
2-12
www.hp.com
Technical Reference Guide
System Overview
Convertible Minitower
Figure 2-9 shows the layout for the Convertible Minitower (CMT) chassis in the minitower
configuration used for HP Compaq dc7700 models. Features include:
■
Externally accessible drive bay assembly may be configured for minitower (vertical) or
desktop (horizontal) position.
■
Easy access to expansion slots and all socketed system board components.
1
2 3
4
5
6
w
q
7
9
8
Item
Description
Item
Description
1
Power supply assembly
7
Speaker (inside optional card guide
assembly, if installed)
2
Processor socket
8
Expansion board area
3
DIMM sockets (4)
9
PCI 2.3 slots
4
DriveLock
10
PCI Express x1 slot
5
Externally accessible drive bays
11
PCI Express x16 graphics/normal-layout
SDVO slot [1]
6
Internally accessible drive bays
12
Chassis fan
NOTE:
[1] Accepts PCI-E graphics or normal-layout ADD2 card.
Figure 2-9. CMT Chassis Layout, Left Side View (Minitower configuration)
Technical Reference Guide
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2-13
System Overview
2.3.3 Board Layouts
Figures 2-10 through 2-12 show the system and expansion board layouts. Figure 2-9 shows the
layout for the USDT system board.
12 345 6 7 8
p
o
i
u
y
t
r
9
e w q
Item
Description
Item
Description
1
Serial port option header
11
Power button, power LED, HD LED, temp
sensor header
2
Hood sense header
12
Chassis speaker connector
3
Parallel port option header
13
Front panel audio connector
4
CMOS clear button
14
Front panel USB port connector
5
SATA #0 (blue), 1 (white), 2 (white)
connectors
15
Chassis fan connector
6
Password clear jumper/header
16
Processor fan connctor
7
PCI Express x16 slot
17
DIMM sockets (3)
8
PCI 2.3 slot
18
IDE (PATA) connector
9
Power supply (VccP) connector
19
Battery
10
Processor socket
20
Power supply connector
Figure 2-10. USDT System Board
2-14
www.hp.com
Technical Reference Guide
System Overview
123 4 5 6 7 8
f d
s
a
p
9
o
i
u y t
r e w q
Item
Description
Item
Description
1
Serial port header
13
Power button, power LED, HD LED header
2
Hood sense header
14
Chassis speaker connector
3
Password clear jumper
15
Front panel audio header
4
CMOS clear button
16
Front panel USB port connector
5
SATA #0 (blue), 1 (white), 2 (white)
17
DIMM sockets (4)
6
PCI Express x1 slot
18
Diskette drive connector
7
PCI Express x16 graphics/reversed-layout
SDVO slot
19
IDE (PATA) connector
8
PCI 2.3 slots
20
Battery
9
Power supply (VccP) connector
21
Power supply connector
10
Processor socket
22
Hood lock header
11
Processor fan connector
12
Chassis fan conenctor
--
--
NOTE:
See SFF and ST rear chassis illustrations for externally accessible I/O connectors.
Figure 2-11. SFF/ST System Board
Technical Reference Guide
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2-15
System Overview
1 234 5 6
1
z
k
l
j
7
g
8
f
d
s
a
9
-
p
o i uyt r e w q
PCI Expansion Board [1]
System Board
Item
Description
Item
Description
1
PCI 2.3 slots
14
SATA #3 connector
2
Battery
15
CMOS clear switch
3
PCI Express x1 slot
16
SATA #0 connector
4
PCI Express x16 graphics
17
Hood lock header
5
Chassis fan header
18
Hood sense header
6
Power supply (VccP) connector
19
Password clear jumper header
7
Serial port B header
20
Power LED/button, HD LED header
8
Processor socket
21
SATA #1 connector
9
Processor fan connector
22
Front panel USB port connector
10
DIMM sockets (4)
23
Internal speaker connector
11
Diskette drive connector
24
PCI expansion board connector [2]
12
Power supply connector
25
Front panel audio connector
13
SATA #2 connector
--
--
NOTES:
See CMT rear chassis illustration for externally accessible I/O connectors.
[1] Applicable to CMT chassis only.
[2] Not included on MT system boards.
Figure 2-12. MT and CMT System Board and CMT PCI Expansion Board
2-16
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Technical Reference Guide
System Overview
2.4 System Architecture
The systems covered in this guide feature an architecture based on the Intel Q965 Express
chipset (Figure 2-13). All systems covered in this guide include the following key components:
■
Intel Pentium 4, Pentium D, or Core 2 Duo processor.
■
Intel Q965 Express chipset - Includes Q965 GMCH north bridge and 82801 ICH8-DO south
bridge
■
SMC SCH5317 super I/O controller supporting PS/2 keyboard and mouse peripherals
■
ALC262 audio controller supporting line in, line out, microphone in, and headphones out
■
Intel 82566DM 10/100/1000 network interface controller
The Q965 chipset provides a major portion of system functionality. Designed to compliment the
latest Intel processors, the Q965 GMCH intefaces with the processor through a
533/800/1066-MB Front-Side Bus (FSB) and communicates with the ICH8-DO component
through the Direct Media Interface (DMI). The integrated graphics controller of the Q965 may
be upgraded through a PCI Express x16 graphics slot. All systems include at least one PCI 2.3
slot and feature as standard a serial ATA (SATA) hard drive. The USDT model supports a
Slimline Optical Drive through a legacy parallel ATA 100 interface.
Table 2-3 lists the differences between models by form factor.
Table 2-3.
Architectural Differences By Form Factor
Model
USDT
SFF
ST
MT
CMT
Memory sockets
3
4
4
4
4
PCI Express x16
graphics slot?
Yes [1]
Yes [2]
Yes [2]
Yes
Yes
0
Yes [2]
Yes [2]
Yes
Yes
1 [3]
2 [4]
2 [4]
2
4
Optional [5]
Standard [6]
Standard [6]
Standard [6]
Standard [6]
1
3
3
4
4
# of PCI Express x1
slots
# of PCI 2.3 slots
Serial / parallel ports
SATA interfaces
Notes:
[1] Supports an ADD2 card in the reverse-layout. or a PCIe x16 graphics card (with PCIe riser card
installed)
[2] Slot not accessible if PCI riser is installed.
[3] Full-height slot (requires PCI riser)
[4] Low-profile slots without PCI riser, full-height slots with optional PCI riser
[5] Requires adapter.
[6] 2nd serial port requires adapter
Technical Reference Guide
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2-17
System Overview
Pentium
Processor
Q965 Chipset
Monitor
PCI Express
x16 slot (PEG)[1]
RGB
Integrated
Graphics
Cntlr.
Q965
GMCH SDRAM
Cntlr
PCIe
PEG I/F [1] DMI
SATA
Hard Drive
Optical
Drive
SATA-to
-PATA
Bridge [2]
HD Audio
Subsystem
DMI
SATA
I/F
82801
ICH8-DO
USB
I/F
Ch A DDR2
SDRAM
Ch B DDR2
SDRAM
USB Ports 1-8
Serial I/F [4] Parallel I/F [4]
LPC I/F
SCH5317
I/O Cntlr.
Kybd-Mouse I/F Diskette I/F
Audio I/F
PCI Cntlr.
Keyboard
PCI 2.3 slot(s) [3]
Notes:
NIC
I/F
PCI Express x1 slot
Floppy
Mouse
Power Supply
[1] USDT: reverse-layout ADD2 card or PCIe x16 graphics card (with PCIe riser card installed).
SFF/ST: reverse layout graphics, ADD2, SDVO card.
CMT: normal-layout graphics, ADD2, SDVO card.
[2] USDT only
[3] USDT requires PCI riser card
[4] Requires optional cable assembly for USDT form factor, standard on SFF, ST, MT, and CMT form factors.
Figure 2-13. System Architecture, Block diagram
2-18
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Technical Reference Guide
System Overview
2.4.1 Intel Processor Support
The models covered in this guide support the following processor types:
■
Intel Pentium Processor Extreme Edition - dual-core design with Hyper-Threading (HT)
technology
■
Intel Pentium D Processor - dual-core design
■
Intel Pentium 4 Processor - single-core design with HT technology
■
Intel Core2 Duo - (when available) energy-efficient dual-core performance
■
Intel Celeron D Processor
These processors are backward-compatible with software written for earlier x86 microprocessors
and include streaming SIMD extensions (SSE, SSE2, and SSE3) for enhancing 3D graphics and
speech processing performance.
The system board includes a zero-insertion-force (ZIF) Socket-T designed for mounting an
LGA775-type processor package (Figure 2-14).
Figure 2-14. Processor Socket and Processor Package
To remove the processor:
1. Remove the processore heat sink/fan assembly (not shown).
2. Release the locking lever (1) by first pushing down, then out and up.
3. Pull up the securing frame (2).
4. Grasp the processor (3) by the edges and lift straight up from the socket.
Technical Reference Guide
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2-19
System Overview
processor heatsink/fan assembly mounting differs between form factors. Always use the
✎ The
same assembly or one of the same type when replacing the processor. Refer to the applicable
Service Reference Guide for detailed removal and replacement procedures of the heatsink/fan
assembly and the processor.
2.4.2 Chipset
The Intel Q965 Express chipset consists of a Graphics Memory Controller Hub (GMCH) and an
enhanced I/O controller hub with Digital Office (ICH8-DO). Table 2-4 compares the functions
provided by the chipsets.
Table 2-4
Chipset Components
Components
Function
G965 GMCH
Intel Graphics Media Accelerator 950 (integrated graphics controller)
PCI Express x16 graphics interface (Q965 only)
SDRAM controller supporting unbuffered, non-ECC PC2-6400 DDR2
DIMMs
533-, 800-, or 1066-MHz FSB
82801GB ICH8-DO
PCI 2.3 bus I/F
PCI Express x1
LPC bus I/F
SMBus I/F
IDE I/F with SATA and PATA support
HD audio interface
RTC/CMOS
IRQ controller
Power management logic
USB 1.1/2.0 controllers supporting eight (8) ports
Gigabit Ethernet Controller
The I/O controller hub (ICH8-DO ) features Intel Digital Office, which includes Active
Management Technology (AMT). AMT is a hardware/firmware solution that operates on
auxiliary power to allow 24/7 support of network alerting and managment of the unit without
regard to the power state or operating system. AMT capabilities include:
2-20
■
System asset recovery (hardware and software configuration data)
■
OS-independent system wellness and healing
■
Software (virus) protection/management
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Technical Reference Guide
System Overview
2.4.3 Support Components
Input/output functions not provided by the chipset are handled by other support components.
Some of these components also provide “housekeeping” and various other functions as well.
Table 2-5 shows the functions provided by the support components.
Table 2-5
Support Component Functions
Component Name
Function
SCH5317 I/O Controller
Keyboard and pointing device I/F
Diskette I/F
Serial I/F (COM1and COM2)
Parallel I/F (LPT1, LPT2, or LPT3)
PCI reset generation
Interrupt (IRQ) serializer
Power button and front panel LED logic
GPIO ports
Processor over tempurature monitoring
Fan control and monitoring
Power supply voltage monitoring
SMBus and Low Pin Count (LPC) bus I/F
Intel 82566DM Network Interface
Controller
10/100/1000 Fast Ethernet network interface controller.
ALC262 HD Audio Codec
Audio mixer
One digital-to-analog 2-channel converter
Two analog-to-digital 2-channel converters
Analog I/O
2-channel audio support
2.4.4 System Memory
These systems implement a dual-channel Double Data Rate (DDR2) memory architecture. All
models support DDR2 800-, 667-, and 533-MHz DIMMs and ship with DDR2 800- or 667-MHz
DIMMs.
✎ DDR and DDR2 DIMMs are NOT interchangeable.
The USDT system provides three DIMM sockets supporting up to 3 GB of memory while all
other form factors provide four DIMM sockets and support a total of four gigabytes of memory.
maximum memory amounts stated above are with 1-GB memory modules using 1-Gb
✎ The
technology DIMMs.
Technical Reference Guide
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2-21
System Overview
2.4.5 Mass Storage
All models support at least two mass storage devices, with one being externally accessible for
removable media. These systems provide the following intefaces for internal storage devices:
USDT: one SATA interface, one SATA-to-PATA bridge/interface for a Slimline optical drive
SFF/ST: three SATA interfaces
MT/CMT: four SATA interfaces
These systems may be preconfigured or upgraded with a 80-, 160-, or 250-GB SATA hard drive
and one removable media drive such as a CD-ROM drive.
2.4.6 Serial and Parallel Interfaces
All models except those that use the USDT form factor include a serial port and a parallel port,
both of which are accessible at the rear of the chassis. The USDT form factor may be upgraded
with an adapter to provide serial and parallel ports. The SFF, ST, MT, and CMT form factors may
be upgraded with an optional second serial port.
The serial interface is RS-232-C/16550-compatible and supports standard baud rates up to
115,200 as well as two high-speed baud rates of 230K and 460K. The parallel interface is
Enhanced Parallel Port (EPP1.9) and Enhanced Capability Port (ECP) compatible, and supports
bi-directional data transfers.
2.4.7 Universal Serial Bus Interface
All models provide eight Universal Serial Bus (USB) ports, with two ports accessible at the front
of the unit and six ports accessible on the rear panel. The USB interface provides hot
plugging/unplugging functionality. These systems support USB 1.1 and 2.0 functionality on all
ports.
2.4.8 Network Interface Controller
All models feature a Intel 82566 Gigabit Network Interface Controller (NIC) integrated on the
system board. The controller provides automatic selection of 10BASE-T, 100BASE-TX, or
1000BASE-T operation with a local area network and includes power-down, wake-up, and
Alert-On-LAN (AOL), and Alert Standard Format (ASF) features. An RJ-45 connector with
status LEDs is provided on the rear panel.
2-22
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Technical Reference Guide
System Overview
2.4.9 Graphics Subsystem
These systems use the Q965 GMCH component that integrates an integrated graphics controller
that can drive an external VGA monitor. The integrated graphics controller (IGC) features a
333-MHz core processor and a 400-MHz RAMDAC. The controller implements Dynamic Video
Memory Technology (DVMT 3.0) for video memory. Table 2-6 lists the key features of the
integrated graphics subsystem.
Table 2-6
Integrated Graphics Subsystem Statistics
Q965 GMCH
Integrated Graphics Controller
Recommended for:
Hi 2D, Entry 3D
Bus Type
Int. PCI Express
Memory Amount
8 MB pre-allocated
Memory Type
DVMT 3.0
DAC Speed
400 MHz
Maximum 2D Res.
2048x1536 @ 85 Hz
Software Compatibility
Quick Draw,
DirectX 9.0,
Direct Draw,
Direct Show,
Open GL 1.4,
MPEG 1-2,
Indeo
Outputs
1 RGB
The IGC supports dual independent display for expanding the desktop viewing area across two
monitors. The graphics subsystem of all form factors supports upgrading through the PCI
Express x16 graphics slot.
PCI Express x16 slot of the USDT form factor supports either a reverse-layout SDVO ADD2
✎ The
card or a low-profile PCIe x16 graphics card.
2.4.10 Audio Subsystem
These systems use the integrated High Definitions audio controller of the chipset and the Realtek
ALC262 High Definition audio codec. HD audio provides improvements over AC’97 audio such
as higher sampling rates, refined signal interfaces, and higher signal-to-noise ratio audio
processors. These systems include a 1.5-watt output amplifier driving an internal speaker. All
models feature front panel-accessible stereo microphone in and headphone out audio jacks as
standard.
Technical Reference Guide
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2-23
System Overview
2.5 Specifications
This section includes the environmental, electrical, and physical specifications for the systems
covered in this guide. Where provided, metric statistics are given in parenthesis. Specifications
are subject to change without notice.
Table 2-7
Environmental Specifications (Factory Configuration)
Parameter
Operating
Non-operating
Ambient Air Temperature
50o to 95o F (10o to 35o C, max.
rate of change < 10°C/Hr)
-22o to 140o F (-30o to 60o C, max.
rate of change < 20°C/Hr )
Shock (w/o damage)
5 Gs [1]
20 Gs [1]
Vibration
0.000215 G2/Hz, 10-300 Hz
0.0005 G2/Hz, 10-500 Hz
Humidity
10-90% Rh @ 28o C max.
wet bulb temperature
5-95% Rh @ 38.7o C max.
wet bulb temperature
Maximum Altitude
10,000 ft (3048 m) [2]
30,000 ft (9144 m) [2]
NOTE:
[1]
[2]
Peak input acceleration during an 11 ms half-sine shock pulse.
Maximum rate of change: 1500 ft/min.
Table 2-8
Electrical Specifications
Parameter
Input Line Voltage:
Nominal:
Maximum:
Input Line Frequency Range:
Nominal:
Maximum:
Power Supply:
Maximum Continuous Power:
USDT
ST or SFF
MT/CMT
Maximum Line Current Draw:
USDT
SF or SFF
MT/CMT
U.S.
International
100–240 VAC
90–264 VAC
100–240 VAC
90–264 VAC
50–60 Hz
47–63 Hz
50–60 Hz
47–63 Hz
200 watts
240 watts
365 watts
200 watts
240 watts
365 watts
4 A @ 100 VAC
5 A @ 100 VAC
6 A @ 100 VAC
2 A @ 200 VAC
2.5 A @ 200 VAC
3.0 A @ 200 VAC
.
2-24
www.hp.com
Technical Reference Guide
System Overview
Table 2-9
Physical Specifications
Parameter
USDT
ST
SFF
MT
CMT [2]
Height
2.95 in
(7.49 cm)
13.3 in
(33.78 cm)
3.95 in
(10.03 cm)
14.5 in
(36.8 cm)
17.65 in
(44.8 cm)
Width
12.4 in
(31.5 cm)
3.95 in
(10.03 cm)
13.3 in
(33.78 cm)
6.88 in
17.5 cm)
6.60 in
(16.8 cm)
Depth
13.18 in
(33.48 cm)
14.9 in
(37.85 cm)
14.9 in
(37.85 cm)
16.31 in
(41.1 cm)
17.8 in
(45.21 cm)
Weight [1]
13.2 lb
(6.0 kg)
19.5 lb
(8.8 kg)
19.5 lb
(3.61 kg)
23.8 lb
(10.8 kg)
32.5 lb
(14.7 kg)
100 lb
(45.4 kg)
72.1 lb
(35 kg)
100 lb
(45.4 kg)
72.1 lb
(35 kg)
Load-bearing ability 72.1 lb
of chassis [3]
(35 kg)
NOTES:
[1] System weight may vary depending on installed drives/peripherals.
[2] Minitower configuration. For desktop configuration, swap Height and Width dimensions
[3] Applicable to unit in desktop orientation only and assumes reasonable type of load such
as a monitor .
Technical Reference Guide
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2-25
System Overview
Table 2-10
Diskette Drive Specifications
Parameter
Measurement
Media Type
3.5 in 1.44 MB/720 KB diskette
Height
1/3 bay (1 in)
Bytes per Sector
512
Sectors per Track:
High Density
Low Density
18
9
Tracks per Side:
High Density
Low Density
80
80
Read/Write Heads
2
Average Access Time:
Track-to-Track (high/low)
Average (high/low)
Settling Time
Latency Average
2-26
3 ms/6 ms
94 ms/169 ms
15 ms
100 ms
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Technical Reference Guide
System Overview
Table 2-11
Optical Drive Specifications
Parameter
48x CD-ROM
48/32/48x CD-RW Drive
Interface Type
SATA [1]
SATA [1]
Media Type (reading)
Mode 1,2, Mixed Mode, CD-DA,
Photo CD, Cdi, CD-XA
Mode 1,2, Mixed Mode, CD-DA,
Photo CD, Cdi, CD-XA
Media Type (writing)
N/a
CD-R, CD-RW
Transfer Rate (Reads)
4.8 Kb/s (max sustained)
CD-ROM, 4.8 Kb/s;
CD-ROM/CD-R, 1.5-6 Kb/s
Transfer Rate (Writes):
N/a
CD-R, 2.4 Kbps (sustained);
CD-RW, 1.5 Kbps (sustained);
550 MB
640 MB
180 MB
540 MB
650/700 MB
180 MB
15 mm
15 mm
Disc Diameter
8/12 cm
8/12 cm
Disc Thickness
1.2 mm
1.2 mm
Track Pitch
1.6 um
1.6 um
+/- 1.5 °
0.14 mW
GaAs
790 +/- 25 nm
53.5 + 1.5°
53.6 0.14 mW
GaAs
790 +/- 25 nm
Average Access Time:
Random
Full Stroke
<100 ms
<150 ms
<125 ms
<210 ms
Audio Output Level
0.7 Vrms
0.7 Vrms
128 KB
2 MB
Capacity:
Mode 1, 12 cm
Mode 2, 12 cm
8 cm
Center Hole Diameter
Laser
Beam Divergence
Output Power
Type
Wave Length
Cache Buffer
NOTE:
[1] IDE interface on USDT models (through SATA bridge)
Technical Reference Guide
www.hp.com
2-27
System Overview
Table 2-12
Hard Drive Specifications
Parameter
80 GB
160 GB
250 GB
Drive Size
3.5 in
3.5 in
3.5 in
Interface
SATA
SATA
SATA
300 Gb/s
300 Gb/s
300 Gb/s
Yes
Yes
Yes
0.8 ms
9 ms
17 ms
0.8 ms
9 ms
17 ms
1.0 ms
11 ms
18 ms
Disk Format (logical blocks)
156,301,488
320,173,056
488,397,168
Rotation Speed
5400/7200
7200 RPM
7200 RPM
SMART III
SMART III
SMART III
Transfer Rate
Drive Protection System
Support?
Typical Seek Time (w/settling)
Single Track
Average
Full Stroke
Drive Fault Prediction
2-28
www.hp.com
Technical Reference Guide
3
Processor/Memory Subsystem
3.1
Introduction
This chapter describes the processor/memory subsystem. These systems include an Intel Celeron
D, Pentium 4, Pentium D, or Core 2 Duo processor and the Q965 chipset (Figure 3-1). These
models support PC2-6400 and PC2-5300 DDR2 DIMMs.
Intel
Pentium
Processor
FSB I/F
Intel
Q965
GMCH
XMM1
XMM2
Ch A
DIMM
Ch A
DIMM
Ch B
DIMM
Ch B
DIMM
XMM3
XMM4 [1]
SDRAM
Cntrl
Note:
[1] Not present on USDT form factor.
Figure 3-1. Processor/Memory Subsystem Architecture
This chapter includes the following topics:
■
Intel Pentium processor (3.2)
■
Memory subsystem (3.3)
Technical Reference Guide
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3-1
Processor/Memory Subsystem
3.2
Intel Pentium Processors
These systems each feature an Intel processor in a FC-LGA775 package mounted with a heat
sink in a zero-insertion force socket. The mounting socket allows the processor to be easily
changed for upgrading.
3.2.1 Intel Processor Overview
These models support the latest generation of Intel Pentium processors, including those which
feature Intel's NetBurst architecture and Hyper-Threading technology. The processors are
designed for handling the intensive multimedia and internet applications of today while
maintaining compatibility with software written for earlier x86) micoprocessors.
Key features of supported Intel Pentium processors include:
■
Dual-core architecture—Featured on all Intel Pentium Processor Extreme Editions and
Pentium D processors, provides full parallel processing .
■
Hyper-Threading Technology—Featured in some Intel Pentium Processor Extreme Editions
and Pentium 4 Processors, the main processing loop has twice the depth (20 stages) of earlier
processors allowing for increased processing frequencies.
■
Execution Trace Cache— A new feature supporting the branch prediction mechanism, the
trace cache stores translated sequences of branching micro-operations ( ops) and is checked
when suspected re-occurring branches are detected in the main processing loop. This feature
allows instruction decoding to be removed from the main processing loop.
■
Rapid Execution Engine—Arithmetic Logic Units (ALUs) run at twice (2x) processing
frequency for higher throughput and reduced latency.
■
1-/2-/4-MB Advanced transfer L2 cache—Using 32-byte-wide interface at processing speed,
the large L2 cache provides a substantial increase.
■
Advanced dynamic execution—Using a larger (4K) branch target buffer and improved
prediction algorithm, branch mis-predictions are reduced by an average of 33 % over the
Pentium III.
■
Enhanced Floating Point Processor —With 128-bit integer processing and deeper pipelining
the Pentium's FPU provides a 2x performance boost over the Pentium III.
■
Additional Streaming SIMD extensions (SSE2 andSSE3)—In addition to the SSE support
provided by previous Pentium processors, the Pentium 4 processor includes an additional
144 MMX instructions, further enhancing:
■
3-2
❏
Streaming video/audio processing
❏
Photo/video editing
❏
Speech recognition
❏
3D processing
❏
Encryption processing
Quad-pumped Front Side Bus (FSB)—The FSB uses a 200-MHz clock for qualifying the
buses' control signals. However, address information is transferred using a 2x strobe while
data is transferred with a 4x strobe, providing a maximum data transfer rate that is four times
that of earlier processors.
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Technical Reference Guide
Processor/Memory Subsystem
Figure 3-2 illustrates the basic internal architecture of an Intel Pentium single-core processor.
Dual-core processors feature two cores operating in parallel. The table below provides a
representative listing of supported processors. Other models may also be supported.
Pentium 4 Processor
Intel Pentium
Single Core Processor
Branch
Prediction
16-K Execution
Trace Cache
CPU
Rapid Exe. Eng.
ALUs
ALUs
Core speed
Intel Model
No.
E6700
E6600
E6400
E6300
965
960
955
950
940
930
920
840
672
670
660
650
640
630
Out-of-Order
Core
128-bit
Integer
FPU
Core
Speed
2.66 GHz
2.40 GHz
2.13 GHz
1.86 GHz
3.73 GH
3.60 GHz
3.46 GHz
3.40 GHz
3.20 GHz
3.00 GHz
2.80 GHz
3.20 GHz
3.80 GHz
3.80 GHz
3.60 GHz
3.40 GHz
3.20 GHz
3.00 GHz
L2
Adv..
Transfer
Cache
FSB
I/F
ALU Speed (Core speed x2)
Dual
Core?
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
8-K
L1
L1
Cache
Data
Cache
FSB
Speed
1066 MHz
1066 MHz
1066 MHz
1066 MHz
1066 MHz
800 MHz
1066 MHz
800 MHz
800 MHz
800 MHz
800 MHz
800 MHz
800 MHz
800 MHz
800 MHz
800 MHz
800 MHz
800 MHz
FSB speed (max. data transfer rate)
L2 Cache
Size
4 MB
4 MB
2 MB
2 MB
2 x 2 MB
2 x 2 MB
2 x 2 MB
2 x 2 MB
2 x 2 MB
2 x 2 MB
2 x 2 MB
2 x 1 MB
2 MB
2 MB
2 MB
2 MB
2 MB
2 MB
Hyper-Threading
Technology?
No
No
No
No
Yes
No
Yes
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Figure 3-2. Supported Pentium and Core 2 Duo Processors (partial listing)
The Intel Pentium processor increases processing speed by using higher clock speeds with
hyper-pipelined technology, therefore handling significantly more instructions at a time. The
Arithmetic Logic Units (ALUs) of all processors listed above run at twice the core speed.
An improved branch prediction mechanism features an execution trace cache and a refined
prediction algorithm. The execution trace cache can store 12 kilobytes of micro-ops (decoded
instructions dealing with branching sequences) that are checked when re-occurring branches are
processed. Code that is not executed (bypassed) is no longer stored in the L1 cache as was the
case in earlier generation Pentium processors.
The Pentium processor is compatible with software written for x86 processors. These systems
also support the Intel Celeron D processors and the energy-efficient Intel CoreT M 2 Duo
processors.
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3-3
Processor/Memory Subsystem
3.2.2 Processor Upgrading
All models use the LGA775 ZIF (Socket T) mounting socket. These systems require that the
processor use an integrated heatsink/fan assembly. A replacement processor must use the same
type heatsink/fan assembly as the original to ensure proper cooling.
The processor uses a PLGA775 package consisting of the processor die mounted “upside down”
on a PC board. This arrangement allows the heat sink to come in direct contact with the processor
die. The heat sink and attachment clip are specially designed provide maximum heat transfer
from the processor component.
CAUTION: Attachment of the heatsink to the processor is critical on these systems. Improper attachment
of the heatsink will likely result in a thermal condition. Although the system is designed to detect thermal
conditions and automatically shut down, such a condition could still result in damage to the processor
component. Refer to the applicable Service Reference Guide for processor installation instructions.
ï
CAUTION: Installing a processor that is not supported by the system board may cause damage to the
system board and/or the processor. Processors rated above 95 watts are not recommended.
ï
3.3
Memory Subsystem
All models support non-ECC PC2-5300 and PC2-6400 DDR2 memory. The USDT form factor
supports up to 3 gigabytes of memory while the SFF, ST, MT, and CMT form factors support up
to 4 gigabytes of memory.
DDR SDRAM “PCxxxx” reference designates bus bandwidth (i.e., a PC2-5300 DIMM can,
✎ The
operating at a 667-MHz effective speed, provide a throughput of 5300 MBps (8 bytes ×
667MHz)). Memory speed types may be mixed within a system, although the system BIOS will
set the memory controller to work at speed of the slowest DIMM.
The system board provides three or four DIMM sockets depending on form factor:
■
XMM1, channel A
■
XMM2, channel A
■
XMM3, channel B
■
XMM4, channel B (not present inUSDT form factor)
DIMMs do not need to be installed in pairs although installation of pairs (an equal DIMM for
each channel) provides the best performance. The XMM1 socket must be populated for proper
support of Intel Advanced Management Technology (AMT). The BIOS will detect the DIMM
population and set the system accordingly as follows:
3-4
■
Single-channel mode - DIMMs installed for one channel only
■
Dual-channel asymetric mode - DIMMs installed for both channels but of unequal channel
capacities.
■
Dual-channel interleaved mode (recommended)- DIMMs installed for both channels and
offering equal channel capacities, proving the highest performance.
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Technical Reference Guide
Processor/Memory Subsystem
These systems support DIMMs with the following parameters:
■
Unbuffered, compatible with SPD rev. 1.0
■
256-Mb, 512-Mb, and 1-Gb memory technologies for x8 and x16 devices
■
CAS latency (CL) of 5 or 6 (depending on memory speed)
■
Single or double-sided
■
Non-ECC memory only
The SPD format supported by these systems complies with the JEDEC specification for 128-byte
EEPROMs. This system also provides support for 256-byte EEPROMs to include additional
HP-added features such as part number and serial number. The SPD format as supported in this
system (SPD rev. 1) is shown in Table 3-1.
If BIOS detects an unsupported DIMM, a “memory incompatible” message will be displayed
and the system will halt. These systems are shipped with non-ECC DIMMs only. Refer to
chapter 8 for a description of the BIOS procedure of interrogating DIMMs.
An installed mix of DIMM types is acceptable but operation will be constrained to the level of
the DIMM with the lowest (slowest) performance specification.
If an incompatible DIMM is detected the NUM LOCK will blink for a short period of time
during POST and an error message may or may not be displayed before the system hangs.
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3-5
Processor/Memory Subsystem
Table 3-1 shows suggested memory configurations for these systems. Note that the USDT form
factor provides only three DIMM sockets and therefore cannot match the SFF, ST, MT, and CMT
form factors in maximum memory capacity.
NOTE: Table 3-1 does not list all possible configurations. Balanced-capacity, dual-channel
loading yields best performance.
Table 3-1.
DIMM Socket Loading
Channel A
Socket 1
Socket 2 [1]
128-MB
none
128-MB
none
128-MB
128-MB
128-MB
128-MB
256-MB
none
256-MB
none
512-MB
none
512-MB
none
1-GB
none
1-GB
none
1-GB
1-GB
1-GB
1-GB
Channel B
Socket 3
Socket 4
none
none
128-MB
none
128-MB
none
128-MB
128-MB
none
none
256-MB
none
none
none
512-MB
none
none
none
1-GB
none
1-GB
none
1-GB
1-GB
Total
128-MB
256-MB (dual-channel)
384-MB (dual-channel)
512-MB (dual- channel)
256-MB
512-MB (dual-channel)
512-MB
1-GB (dual-channel)
1-GB
2-GB (dual-channel)
3-GB (dual-channel)
4-GB (dual-channel)
NOTE:
[1] Not present on USDT form factor.
3-6
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Technical Reference Guide
Processor/Memory Subsystem
The SPD address map is shown in Table 3-2.
Table 3-2
SPD Address Map (SDRAM DIMM)
Byte
Description
Notes
Byte
Description
Notes
0
No. of Bytes Written Into EEPROM
[1]
25
Min. CLK Cycle Time at CL X-2
[7]
1
Total Bytes (#) In EEPROM
[2]
26
Max. Acc. Time From CLK @ CL X-2
[7]
2
Memory Type
27
Min. Row Prechge. Time
[7]
3
No. of Row Addresses On DIMM
28
Min. Row Active to Delay
[7]
4
No. of Column Addresses On DIMM
29
Min. RAS to CAS Delay
[7]
5
No. of Module Banks On DIMM
30-31
Reserved
6, 7
Data Width of Module
32-61
Superset Data
[7]
8
Voltage Interface Standard of DIMM
62
SPD Revision
[7]
9
Cycletime @ Max CAS Latency (CL)
[4]
63
Checksum Bytes 0-62
10
Access From Clock
[4]
64-71
JEP-106E ID Code
11
Config. Type (Parity, Nonparity...)
72
DIMM OEM Location
[8]
12
Refresh Rate/Type
73-90
OEM’s Part Number
[8]
13
Width, Primary DRAM
91-92
OEM’s Rev. Code
[8]
14
Error Checking Data Width
93-94
Manufacture Date
[8]
95-98
OEM’s Assembly S/N
[8]
99125
OEM Specific Data
[8]
[3]
[4][5]
15
Min. Clock Delay
16
Burst Lengths Supported
[6]
17
No. of Banks For Each Mem. Device
[4]
126
Intel frequency check
18
CAS Latencies Supported
[4]
127
Reserved
[8]
19
CS# Latency
[4]
128 - 131
Compaq header “CPQ1”
[9]
20
Write Latency
[4]
132
Header checksum
[9]
21
DIMM Attributes
133 - 145
Unit serial number
[9][10]
22
Memory Device Attributes
146
DIMM ID
[9][11]
23
Min. CLK Cycle Time at CL X-1
[7]
147
Checksum
[9]
24
Max. Acc. Time From CLK @ CL X-1
[7]
148
Reserved
[9]
NOTES:
[1] Programmed as 128 bytes by the DIMM OEM
[2] Must be programmed to 256 bytes.
[3] High order bit defines redundant addressing: if set (1), highest order RAS# address must be re-sent as highest order CAS#
address.
[4] Refer to memory manufacturer’s datasheet
[5] MSb is Self Refresh flag. If set (1), assembly supports self refresh.
[6] Back-to-back random column addresses.
[7] Field format proposed to JEDEC but not defined as standard at publication time.
[8] Field specified as optional by JEDEC but required by this system.
[9] HP usage. This system requires that the DIMM EEPROM have this space available for reads/writes.
[10] Serial # in ASCII format (MSB is 133). Intended as backup identifier in case vender data is invalid.
Can also be used to indicate s/n mismatch and flag system adminstrator of possible system Tampering.
[11]Contains the socket # of the module (first module is “1”). Intended as backup identifier (refer to note [10]).
Technical Reference Guide
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3-7
Processor/Memory Subsystem
Figure 3-3 shows the system memory map.
FFFF FFFFh
High BIOS Area
FFE0 0000h
4 GB
DMI/APIC
Area
F000 0000h
PCI
Memory
Area
IGC (1-64 MB)
TSEG
Main
Memory
Area
Top of DRAM
Main
Memory
0100 0000h
16 MB
00FF FFFFh
Main
Memory
0010 0000h
000F FFFFh
BIOS
Extended BIOS
Expansion Area
Legacy Video
DOS
Compatibilty
Area
1 MB
640 KB
Base Memory
0000 0000h
locations in memory are cacheable. Base memory is always mapped to DRAM. The next 128
✎ All
KB fixed memory area can, through the north bridge, be mapped to DRAM or to PCI space.
Graphics RAM area is mapped to PCI or AGP locations.
Figure 3-3. System Memory Map
3-8
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Technical Reference Guide
4
System Support
4.1
Introduction
This chapter covers subjects dealing with basic system architecture and covers the following
topics:
■
PCI bus overview (4.2), page 4-1
■
System resources (4.3), page 4-11
■
Real-time clock and configuration memory (4.4), page 4-19
■
System management (4.5), page 4-20
■
Register map and miscellaneous functions (4.6), page 4-24
This chapter covers functions provided by off-the-shelf chipsets and therefore describes only
basic aspects of these functions as well as information unique to the systems covered in this
guide. For detailed information on specific components, refer to the applicable manufacturer's
documentation.
4.2 PCI Bus Overview
section describes the PCI bus in general and highlights bus implementation in this particular
✎ This
system. For detailed information regarding PCI bus operation, refer to the appropriate PCI
specification or the PCI web site: www.pcisig.com.
These systems implement the following types of PCI buses:
■
PCI 2.3 - Legacy parallel interface operating at 33-MHz
■
PCI Express - High-performance interface capable of using multiple TX/RX high-speed
lanes of serial data streams
The PCI bus handles address/data transfers through the identification of devices and functions on
the bus. A device is typically defined as a component or slot that resides on the PCI bus (although
some components such as the GMCH and ICH8 are organized as multiple devices). A function is
defined as the end source or target of the bus transaction. A device may contain one or more
functions. In the standard configuration these systems use a hierarchy of three PCI buses (Figure
4-1). The PCI bus #0 is internal to the chipset components and is not physically accessible. The
Direct Media Interface (DMI) links the GMCH and ICH8 components and operates as a subset of
the PCI bus. All PCI slots and the NIC function internal to the ICH8 reside on PCI bus #2.
Technical Reference Guide
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4-1
System Support
Q965
GMCH
Memory
Cntlr
Function
PCI Bus 0
Integrated
Graphics
Controller
RGB Monitor
Host-PCI Exp.
Bridge
PCI Express x16 graphics slot [1]
Host-DMI Bridge
DMI Link
82801 ICH8
DMI
PCI Bus 1
PCI 2.3
Bridge
Function
PCI Exp.
Port 1
Function
NIC.
Function
HD Audio
SATA USB I/F
LPC
Bridge
Cntlr
Cntlr
Cntlr
Function Function Function Function
NIC
I/F
PCI Express x1 slot
PCI 2.3 slot(s)
Notes:
Only implemented functions are shown.
[1] In USDT SFF, and ST form factors, accepts reverse-layout graphics cards.
In MT and CMT form factors, accepts nomal layout graphics card.
Figure 4-1. PCI Bus Devices and Functions
4.2.1 PCI 2.3 Bus Operation
The PCI 2.3 bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for
handling both address and data transfers. A bus transaction consists of an address cycle and one
or more data cycles, with each cycle requiring a clock (PCICLK) cycle. High performance is
realized during burst modes in which a transaction with contiguous memory locations requires
that only one address cycle be conducted and subsequent data cycles are completed using
auto-incremented addressing. Four types of address cycles can take place on the PCI bus; I/O,
memory, configuration, and special. Address decoding is distributed (left up to each device on
the PCI bus).
I/O and Memory Cycles
For I/O and memory cycles, a standard 32-bit address decode (AD31..0) for byte-level
addressing is handled by the appropriate PCI device. For memory addressing, PCI devices
decode the AD31..2 lines for dword-level addressing and check the AD1,0 lines for burst
(linear-incrementing) mode. In burst mode, subsequent data phases are conducted a dword at a
time with addressing assumed to increment accordingly (four bytes at a time).
4-2
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System Support
Configuration Cycles
Devices on the PCI bus must comply with PCI protocol that allows configuration of that device
by software. In this system, configuration mechanism #1 (as described in the PCI Local Bus
specification Rev. 2.3) is employed. This method uses two 32-bit registers for initiating a
configuration cycle for accessing the configuration space of a PCI device. The configuration
address register (CONFIG_ADDRESS) at 0CF8h holds a value that specifies the PCI bus, PCI
device, and specific register to be accessed. The configuration data register (CONFIG_DATA) at
0CFCh contains the configuration data.
PCI Configuration Data Register
I/O Port 0CFCh, R/W, (8-, 16-, 32-bit access)
Bit
Function
31
Configuration Enable
0 = Disabled
1 = Enable
PCI Configuration Address Register
I/O Port 0CF8h, R/W, (32-bit access only)
Bit
31..0
30..24
Reserved—read/write 0s
23..16
Bus Number. Selects PCI bus
15..11
PCI Device Number. Selects PCI
device for access
10..8
Function Number. Selects function of
selected PCI device.
7..2
Register Index. Specifies config. reg.
1,0
Configuration Cycle Type ID.
00 = Type 0
01 = Type 1
Function
Configuration Data.
Two types of configuration cycles are used. A Type 0 (zero) cycle is targeted to a device on the
PCI bus on which the cycle is running. A Type 1 cycle is targeted to a device on a downstream
PCI bus as identified by bus number bits <23..16>. With three or more PCI buses, a PCI bridge
may convert a Type 1 to a Type 0 if it's destined for a device being serviced by that bridge or it
may forward the Type 1 cycle unmodified if it is destined for a device being serviced by a
downstream bridge. Figure 4-2 shows the configuration cycle format and how the loading of
0CF8h results in a Type 0 configuration cycle on the PCI bus. The Device Number (bits <15..11>
determines which one of the AD31..11 lines is to be asserted high for the IDSEL signal, which
acts as a “chip select” function for the PCI device to be configured. The function number (CF8h,
bits <10..8>) is used to select a particular function within a PCI component.
3
Register 0CF8h
2 2
Reserved
1 1
1 1
8 7
2 1 0 [1]
Function
Register
Bus
Device
Number
Index
Number
Number
Results in:
AD31..0
(w/Type 00
Config. Cycle)
IDSEL (only one signal line asserted)
Function
Number
Register
Index
NOTES:
[1] Bits <1,0> : 00 = Type 0 Cycle, 01 = Type 1 cycle
Type 01 cycle only. Reserved on Type 00 cycle.
Figure 4-2. PCI Configuration Cycle
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4-3
System Support
Table 4-1 shows the standard configuration of device numbers and IDSEL connections for
components and slots residing on a PCI 2.3 bus.
Table 4-1
PCI Component Configuration Access
Function #
Device #
PCI Bus
#
Q965 GMCH:
Host/DMI Bridge
Host/PCI Expr. Bridge
Integrated Graphics Cntlr.
0
0
0
28
1
2
0
0
0
PCI Express x16 graphics slot
0
0
32
0
0
2
3
5
6
0
1
2
3 [2]
1
7
7
0
0
0
1
2
3
4
5
30
31
31
31
31
31
29
29
29
29 [2]
26
29
26
25
27
28
28
28
28
28
28
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
8
AD20
PCI Component
82801EB ICH8
PCI Bridge
LPC Bridge
Serial ATA Controller #1
SMBus Controller
Serial ATA Controller #2
Thermal System
USB 1.1 Controller #1
USB 1.1 Controller #2
USB 1.1 Controller #3
USB 1.1 Controller #4
USB 1.1 Controller #5
USB 2.0 Controller #1
USB 2.0 Controller #2
Network Interface Controller
Intel HD audio controller
PCI Express port 1
PCI Express port 2
PCI Express port 3
PCI Express port 4
PCI Express port 5
PCI Express port 6
Notes
IDSEL
Wired to:
--
---
[1]
[1]
[1]
[1]
[1]
[1]
PCI 2.3 slot 1
PCI 2.3 slot 2
[3]
0
9
8
AD25
PCI 2.3 slot 3
[4]
0
10
8
AD27
PCI 2.3 slot 4
[4]
0
11
8
AD29
NOTES:
[1] Function not used in these systems.
[2] Mapping for USB 1.1 Controller #4 if USB ports 9 and 10 and USB 2.0 Controller #2 are
disabled. Otherwise, mapping for USB 1.1 controller #4 is F0:D25.
[3] SFF, ST, & CMT form factors only.
[4] CMT form factor with PCI expansion board.
4-4
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Technical Reference Guide
System Support
The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration
space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of
configuration data (Figure 4-3), of which the first 64 bytes comprise the configuration space
header.
31
24 23
16 15
8
7
0
Index
FCh
31
24 23
Device-Specific Area
8
7
0
Min. GNT
Int. Pin
Int. Line
Reserved
Reserved
Ex pansion ROM Base Address
Subs ystem ID
Subs ystem Vendor ID
Card Bus CIS Pointer
40h
3Ch
38h
34h
30h
2Ch
28h
Base Address Registers
Brid ge Control
Int. Pin
Int. Line
Ex pansion ROM Base Address
Reserved
I/O Base U pper 16 Bits
I/O Limit Upper 16 Bits
Prefetchable Limit U pper 32 Bits
Prefetchable Base U pper 32 Bits
Prefetch. Mem. Limit
Prefetch. Mem. Base
Memory Limit
Memory Base
Secondar y Status
I/O Limit
I/O Base
2 nd Lat.Tmr Sub. Bus # Sec. Bus #
Pri. Bus #
Base Address Registers
BIST
Hdr. T ype
Class Code
Status
Device ID
Lat. Timer
Index
FCh
Device-Specific Area
Min. Lat.
Configuration
Space
Header
16 15
Line Size
Revision ID
Command
Vendor ID
10h
0Ch
08h
04h
00h
BIST
Hdr. T ype
Class Code
Status
Device ID
Lat. Timer
Line Size
Revision ID
Command
Vendor ID
40h
3Ch
38h
34h
30h
2Ch
28h
24h
20h
1Ch
18h
10h
0Ch
08h
04h
00h
PCI Configuration Space Type 1
PCI Configuration Space Type 0
Not required
Data required by PCI protocol
Figure 4-3. PCI Configuration Space Mapping
PCI 2.3 Bus Master Arbitration
The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has
been granted control of the bus for the purpose of initiating a transaction. A target is a device that
is the recipient of a transaction. The Request (REQ), Grant (GNT), and FRAME signals are used
by PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI
bus (and does not already own it), the PCI device asserts it's REQn signal to the PCI bus arbiter (a
function of the system controller component). If the bus is available, the arbiter asserts the GNTn
signal to the requesting device, which then asserts FRAME and conducts the address phase of the
transaction with a target. If the PCI device already owns the bus, a request is not needed and the
device can simply assert FRAME and conduct the transaction. Table 4-3 shows the grant and
request signals assignments for the devices on the PCI bus.
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4-5
System Support
Table 4-3.
PCI Bus Mastering Devices
Device
REQ/GNT Line
Note
PCI Connector Slot 1
REQ0/GNT0
PCI Connector Slot 2
REQ1/GNT1
[1]
PCI Connector Slot 3
REQ2/GNT2
[2]
PCI Connector Slot 4
REQ3/GNT3
[2]
NOTE:
[1] SFF, ST, MT, and CMT form factors only.
[2] CMT form factor with PCI expansion board
PCI bus arbitration is based on a round-robin scheme that complies with the fairness algorithm
specified by the PCI specification. The bus parking policy allows for the current PCI bus owner
(excepting the PCI/ISA bridge) to maintain ownership of the bus as long as no request is asserted
by another agent. Note that most CPU-to-DRAM accesses can occur concurrently with PCI
traffic, therefore reducing the need for the Host/PCI bridge to compete for PCI bus ownership.
4.2.2 PCI Express Bus Operation
The PCI Express bus is a high-performace extension of the legacy PCI bus specification. The PCI
Express bus uses the following layers:
■
Software/driver layer
■
Transaction protocol layer
■
Link layer
■
Physical layer
Software/Driver Layer
The PCI Express bus maintains software compatibility with PCI 2.3 and earlier versions so that
there is no impact on existing operating systems and drivers. During system intialization, the PCI
Express bus uses the same methods of device discovery and resource allocation that legacy
PCI-based operating systems and drivers are designed to use. The use of PCI configuration space
and the programmability of I/O devices are also used in the same way as for legacy PCI buses
(although PCI Express operation uses more configuration space). The software/driver layer
provides read and write requests to the transaction layer for handling a data transfer.
Transaction Protocol Layer
The transaction protocol layer processes read and write requests from the software/driver layer
and generates request packets for the link layer. Each packet includes an identifier allowing any
required responcse packets to be directed to the originator.
PCI Express protocol supports the three legacy PCI address spaces (memory, I/O, configuration)
as well as a new message space. The message space allows in-band processing of interrupts
through use of the Message Signal Interrupt (MSI) introduced with the PCI 2.2 specification. The
MSI method eliminates the need for hard-wired sideband signals by incorporating those
functions into packets.
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System Support
Link Layer
The link layer provides data integrity by adding a sequence information prefix and a CRC suffix
to the packet created by the transaction layer. Flow-control methods ensure that a packet will
only be transferred if the receiving device is ready to accomodate it. A corrupted packet will be
automatically re-sent.
Physical Layer
The PCI Express bus uses a point-to-point, high-speed TX/RX serial lane topology. One or more
full-duplex lanes transfer data serially, and the design allows for scalability depending on
end-point capabilities. Each lane consists of two differential pairs of signal paths; one for
transmit, one for receive (Figure 4-4).
System Board
PCI Express Card
TX
Device B
Device A
RX
Figure 4-4. PCI Express Bus Lane
Each byte is transferred using 8b/10b encoding. which embeds the clock signal with the data.
Operating at a 2.5 Gigabit transfer rate, a single lane can provide a data flow of 200 MBps. The
bandwidth is increased if additional lanes are available for use. During the initialization process,
two PCI Express devices will negotiate for the number of lanes available and the speed the link
can operate at.
In a x1 (single lane) interface, all data bytes are transferred serially over the lane. In a multi-lane
interface, data bytes are distributed across the lanes using a multiplex scheme as shown in Table
4-4:
Table 4-4.
PCI Express Byte Transfer
Byte #
0
1
2
3
4
5
6
7
x1
Transfer
Lane #
0
0
0
0
0
0
0
0
Technical Reference Guide
x4
Transfer
Lane #
0
1
2
3
0
1
2
3
x8
Transfer
Lane #
0
1
2
3
4
5
6
7
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System Support
For a PCI Express x16 transfer, a lane will be re-used for the transfer of every17th byte. The
mux-demux process provided by the physical layer is transparent to the other layers and to
software/drivers.
The SFF, ST, MT, and CMT form factors provide two PCI Express slots: a PCI Express x16
(16-lane) slot specifically designed for a graphics controller, and a general purpose PCI Express
x1 (1-lane) slot.
4.2.3 Option ROM Mapping
During POST, the PCI bus is scanned for devices that contain their own specific firmware in
ROM. Such option ROM data, if detected, is loaded into system memory's DOS compatibility
area (refer to the system memory map shown in chapter 3).
4.2.4 PCI Interrupts
Eight interrupt signals (INTA- thru INTH-) are available for use by PCI devices. These signals
may be generated by on-board PCI devices or by devices installed in the PCI slots. For more
information on interrupts including PCI interrupt mapping refer to the “System Resources”
section 4.3.
4.2.5 PCI Power Management Support
This system complies with the PCI Power Management Interface Specification (rev 1.0). The
PCI Power Management Enable (PME-) signal is supported by the chipset and allows compliant
PCI peripherals to initiate the power management routine.
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4.2.6 PCI Connectors
PCI 2.3 Connector
A1
B2
A49
A52
A62
B49
B52
B62
Figure 4-5. 32-bit, 5.0-volt PCI 2.3 Bus Connector (J20, J21 on system board)
Table 4-5.
PCI 2.3 Bus Connector Pinout
Pin
B Signal
A Signal
Pin
B Signal
A Signal
Pin
B Signal
A Signal
01
-12 VDC
TRST-
22
GND
AD28
43
+3.3 VDC
PAR
02
TCK
+12 VDC
23
AD27
AD26
44
C/BE1-
AD15
03
GND
TMS
24
AD25
GND
45
AD14
+3.3 VDC
04
TDO
TDI
25
+3.3 VDC
AD24
46
GND
AD13
05
+5 VDC
+5 VDC
26
C/BE3-
IDSEL
47
AD12
AD11
06
+5 VDC
INTA-
27
AD23
+3.3 VDC
48
AD10
GND
07
INTB-
INTC-
28
GND
AD22
49
GND
AD09
08
INTD-
+5 VDC
29
AD21
AD20
50
Key
Key
09
PRSNT1-
Reserved
30
AD19
GND
51
Key
Key
10
RSVD
+5 VDC
31
+3.3 VDC
AD18
52
AD08
C/BE0-
11
PRSNT2-
Reserved
32
AD17
AD16
53
AD07
+3.3 VDC
12
GND
GND
33
C/BE2-
+3.3 VDC
54
+3.3 VDC
AD06
13
GND
GND
34
GND
FRAME-
55
AD05
AD04
14
RSVD
+3.3 AUX
35
IRDY-
GND
56
AD03
GND
15
GND
RST-
36
+3.3 VDC
TRDY-
57
GND
AD02
16
CLK
+5 VDC
37
DEVSEL-
GND
58
AD01
AD00
17
GND
GNT-
38
GND
STOP-
59
+5 VDC
+5 VDC
18
REQ-
GND
39
LOCK-
+3.3 VDC
60
ACK64-
REQ64-
19
+5 VDC
PME-
40
PERR-
SDONE n
61
+5 VDC
+5 VDC
20
AD31
AD30
41
+3.3 VDC
SBO-
62
+5 VDC
+5 VDC
21
AD29
+3.3 VDC
42
SERR-
GND
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System Support
PCI Express Connectors
A1
A11
A12
A18
x1 Connector
A82
x16 Connector
B1
B11
B82
B12
Figure 4-6. PCI Express Bus Connectors J31 (x1) and J41(x16) on system board
Table 4-6.
PCI Express Bus Connector Pinout
4-10
Pin
B Signal
A Signal
Pin
B Signal
A Signal
Pin
B Signal
A Signal
01
+12 VDC
PRSNT1#
29
GND
PERp3
57
GND
PERn9
02
+12 VDC
+12 VDC
30
RSVD
PERn3
58
PETp10
GND
03
RSVD
+12 VDC
31
PRSNT2#
GND
59
PETn10
GND
04
GND
GND
32
GND
RSVD
60
GND
PERp10
05
SMCLK
+5 VDC
33
PETp4
RSVD
61
GND
PERn10
06
+5 VDC
JTAG2
34
PETn4
GND
62
PETp11
GND
07
GND
JTAG4
35
GND
PERp4
63
PETn11
GND
08
+3.3 VDC
JTAG5
36
GND
PERn4
64
GND
PERp11
09
JTAG1
+3.3 VDC
37
PETp5
GND
65
GND
PERn11
10
3.3 Vaux
+3.3 VDC
38
PETn5
GND
66
PETp12
GND
11
WAKE
PERST#
39
GND
PERp5
67
PETn12
GND
12
RSVD
GND
40
GND
PERn5
68
GND
PERp12
13
GND
REFCLK+
41
PETp6
GND
69
GND
PERn12
14
PETp0
REFCLK-
42
PETn6
GND
70
PETp13
GND
15
PETn0
GND
43
GND
PERp6
71
PETn13
GND
16
GND
PERp0
44
GND
PERn6
72
GND
PERp13
17
PRSNT2#
PERn0
45
PETp7
GND
73
GND
PERn13
18
GND
GND
46
PETn7
GND
74
PETp14
GND
19
PETp1
RSVD
47
GND
PERp7
75
PETn14
GND
20
PETn1
GND
48
PRSNT2#
PERn7
76
GND
PERp14
21
GND
PERp1
49
GND
GND
77
GND
PERn14
22
GND
PERn1
50
PETp8
RSVD
78
PETp15
GND
23
PETp2
GND
51
PETn8
GND
79
PETn15
GND
24
PETn2
GND
52
GND
PERp8
80
GND
PERp15
25
GND
PERp2
53
GND
PERn8
81
PRSNT2#
PERn15
82
RSVD
GND
26
GND
PERn2
54
PETp9
GND
27
PETp3
GND
55
PETn9
GND
28
PETn3
GND
56
GND
PERp9
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System Support
4.3 System Resources
This section describes the availability and basic control of major subsystems, otherwise known as
resource allocation or simply “system resources.” System resources are provided on a priority
basis through hardware interrupts and DMA requests and grants.
4.3.1 Interrupts
The microprocessor uses two types of hardware interrupts; maskable and nonmaskable. A
maskable interrupt can be enabled or disabled within the microprocessor by the use of the STI
and CLI instructions. A nonmaskable interrupt cannot be masked off within the microprocessor,
although it may be inhibited by hardware or software means external to the microprocessor.
Maskable Interrupts
The maskable interrupt is a hardware-generated signal used by peripheral functions within the
system to get the attention of the microprocessor. Peripheral functions produce a unique INTA-H
(PCI) or IRQ0-15 (ISA) signal that is routed to interrupt processing logic that asserts the
interrupt (INTR-) input to the microprocessor. The microprocessor halts execution to determine
the source of the interrupt and then services the peripheral as appropriate.
Most IRQs are routed through the I/O controller of the super I/O component, which provides the
serializing function. A serialized interrupt stream is then routed to the ICH component.
Interrupts may be processed in one of two modes (selectable through the F10 Setup utility):
■
8259 mode
■
APIC mode
These modes are described in the following subsections.
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8259 Mode
The 8259 mode handles interrupts IRQ0-IRQ15 in the legacy (AT-system) method using
8259-equivalent logic. Table 4-7 lists the standard source configuration for maskable interrupts
and their priorities in 8259 mode. If more than one interrupt is pending, the highest priority
(lowest number) is processed first.
Table 4-7.
Maskable Interrupt Priorities and Assignments
Priority
4-12
Signal Label
Source (Typical)
1
IRQ0
Interval timer 1, counter 0
2
IRQ1
Keyboard
3
IRQ8-
Real-time clock
4
IRQ9
Unused
5
IRQ10
PCI devices/slots
6
IRQ11
Audio codec
7
IRQ12
Mouse
8
IRQ13
Coprocessor (math)
9
IRQ14
Primary IDE controller
10
IRQ15
Sec. IDE I/F controller (not available on SATA units)
11
IRQ3
Serial port (COM2)
12
IRQ4
Serial port (COM1)
13
IRQ5
Network interface controller
14
IRQ6
Diskette drive controller
15
IRQ7
Parallel port (LPT1)
--
IRQ2
NOT AVAILABLE (Cascade from interrupt controller 2)
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APIC Mode
The Advanced Programmable Interrupt Controller (APIC) mode provides enhanced interrupt
processing with the following advantages:
■
Eliminates the processor's interrupt acknowledge cycle by using a separate (APIC) bus
■
Programmable interrupt priority
■
Additional interrupts (total of 24)
The APIC mode accommodates eight PCI interrupt signals (PIRQA-..PIRQH-) for use by PCI
devices. The PCI interrupts are evenly distributed to minimize latency and wired as follows:
System Interrupts
System Board
Connector
PIRQ
A
PIRQ
B
PIRQ
C
PIRQ
D
PIRQ
E
PIRQ
F
PIRQ
G
PIRQ
H
PCI slot 1
A
B
C
D
PCI slot 2 [1]
D
A
B
C
PCI Expansion
Connector (J30) [1]
D
A
B
C
PCI slot 3 [1]
C
D
A
B
PCI slot 4 [1]
A
B
C
D
NOTES:
[1] If present.
The PCI interrupts can be configured by PCI Configuration Registers 60h..63h to share the
standard ISA interrupts (IRQn).
APIC mode is supported by the Windows NT, Windows 2000, and Windows XP operating
✎ The
systems. Systems running the Windows 95 or 98 operating system will need to run in 8259 mode.
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System Support
Maskable Interrupt processing is controlled and monitored through standard AT-type
I/O-mapped registers. These registers are listed in Table 4-8.
Table 4-8.
Maskable Interrupt Control Registers
I/O Port
020h
021h
0A0h
0A1h
Register
Base Address, Int. Cntlr. 1
Initialization Command Word 2-4, Int. Cntlr. 1
Base Address, Int. Cntlr. 2
Initialization Command Word 2-4, Int. Cntlr. 2
The initialization and operation of the interrupt control registers follows standard AT-type
protocol.
Non-Maskable Interrupts
Non-maskable interrupts cannot be masked (inhibited) within the microprocessor itself but may
be maskable by software using logic external to the microprocessor. There are two non-maskable
interrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable
interrupts, with the SMI- having top priority over all interrupts including the NMI-.
NMI- Generation
The Non-Maskable Interrupt (NMI-) signal can be generated by one of the following actions:
■
Parity errors detected on a PCI bus (activating SERR- or PERR-).
■
Microprocessor internal error (activating IERRA or IERRB)
The SERR- and PERR- signals are routed through the ICH8 component, which in turn activates
the NMI to the microprocessor.
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The NMI Status Register at I/O port 061h contains NMI source and status data as follows:
NMI Status Register 61h
Bit
7
6
5
4
3
2
1
0
Function
NMI Status:
0 = No NMI from system board parity error.
1 = NMI requested, read only
IOCHK- NMI:
0 = No NMI from IOCHK1 = IOCHK- is active (low), NMI requested, read only
Interval Timer 1, Counter 2 (Speaker) Status
Refresh Indicator (toggles with every refresh)
IOCHK- NMI Enable/Disable:
0 = NMI from IOCHK- enabled
1 = NMI from IOCHK- disabled and cleared (R/W)
System Board Parity Error (PERR/SERR) NMI Enable:
0 = Parity error NMI enabled
1 = Parity error NMI disabled and cleared (R/W)
Speaker Data (R/W)
Inteval Timer 1, Counter 2 Gate Signal (R/W)
0 = Counter 2 disabled
1 = Counter 2 enabled
Functions not related to NMI activity
After the active NMI has been processed, status bits <7> or <6> are cleared by pulsing bits <2>
or <3> respectively.
The NMI Enable Register (070h, <7>) is used to enable/disable the NMI signal. Writing 80h to
this register masks generation of the NMI-. Note that the lower six bits of register at I/O port 70h
affect RTC operation and should be considered when changing NMI- generation status.
SMI- Generation
The SMI- (System Management Interrupt) is typically used for power management functions.
When power management is enabled, inactivity timers are monitored. When a timer times out,
SMI- is asserted and invokes the microprocessor's SMI handler. The SMI- handler works with the
APM BIOS to service the SMI- according to the cause of the timeout.
Although the SMI- is primarily used for power management the interrupt is also employed for
the QuickLock/QuickBlank functions as well.
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System Support
4.3.2 Direct Memory Access
Direct Memory Access (DMA) is a method by which a device accesses system memory without
involving the microprocessor. Although the DMA method has been traditionally used to transfer
blocks of data to or from an ISA I/O device, PCI devices may also use DMA operation as well.
The DMA method reduces the amount of CPU interactions with memory, freeing the CPU for
other processing tasks.
section describes DMA in general. For detailed information regarding DMA operation, refer
✎ This
to the data manual for the Intel 82801 I/O Controller Hub.
The 82801 ICH8 component includes the equivalent of two 8237 DMA controllers cascaded
together to provide eight DMA channels, each (excepting channel 4) configurable to a specific
device. Table 4-9 lists the default configuration of the DMA channels.
Table 4-9.
Default DMA Channel Assignments
DMA Channel
Controller 1 (byte transfers)
0
1
2
3
Controller 2 (word transfers)
4
5
6
7
Device ID
Spare
Audio subsystem
Diskette drive
Parallel port
Cascade for controller 1
Spare
Spare
Spare
All channels in DMA controller 1 operate at a higher priority than those in controller 2. Note
that channel 4 is not available for use other than its cascading function for controller 1. The DMA
controller 2 can transfer words only on an even address boundary. The DMA controller and page
register define a 24-bit address that allows data transfers within the address space of the CPU.
In addition to device configuration, each channel can be configured (through PCI Configuration
Registers) for one of two modes of operation:
■
LPC DMA
■
PC/PCI DMA
The LPC DMA mode uses the LPC bus to communicate DMA channel control and is
implemented for devices using DMA through the SCH5317 I/O controller such as the diskette
drive controller.
The PC/PCI DMA mode uses the REQ#/GNT# signals to communicate DMA channel control
and is used by PCI expansion devices.
The DMA logic is accessed through two types of I/O mapped registers; page registers and
controller registers.
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DMA Page Registers
The DMA page register contains the eight most significant bits of the 24-bit address and works in
conjunction with the DMA controllers to define the complete (24-bit) address for the DMA
channels. Table 4-10 lists the page register port addresses.
Table 4-10.
DMA Page Register Addresses
DMA Channel
Page Register I/O Port
Controller 1 (byte transfers)
Ch 0
087h
Ch 1
083h
Ch 2
081h
Ch 3
082h
Controller 2 (word transfers)
Ch 4
n/a
Ch 5
08Bh
Ch 6
089h
Ch 7
08Ah
Refresh
08Fh [see note]
NOTE:
The DMA memory page register for the refresh channel
must be programmed with 00h for proper operation.
The memory address is derived as follows:
24-Bit Address—Controller 1 (Byte Transfers)
8-Bit Page Register
8-Bit DMA Controller
A23..A16
A15..A00
24-Bit Address—Controller 2 (Word Transfers)
8-Bit Page Register
16-Bit DMA Controller
A23..A17
A16..A01, (A00 = 0)
Note that address line A16 from the DMA memory page register is disabled when DMA
controller 2 is selected. Address line A00 is not connected to DMA controller 2 and is always 0
when word-length transfers are selected.
By not connecting A00, the following applies:
■
The size of the the block of data that can be moved or addressed is measured in 16-bits
(words) rather than 8-bits (bytes).
■
The words must always be addressed on an even boundary.
DMA controller 1 can move up to 64 Kbytes of data per DMA transfer. DMA controller 2 can
move up to 64 Kwords (128 Kbytes) of data per DMA transfer. Word DMA operations are only
possible between 16-bit memory and 16-bit peripherals.
The RAM refresh is designed to perform a memory read cycle on each of the 512 row addresses
in the DRAM memory space. Refresh operations are used to refresh memory on the 32-bit
memory bus and the ISA bus. The refresh address is provided on lines SA00 through SA08.
Address lines LA23..17, SA18,19 are driven low.
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System Support
The remaining address lines are in an undefined state during the refresh cycle. The refresh
operations are driven by a 69.799-KHz clock generated by Interval Timer 1, Counter 1. The
refresh rate is 128 refresh cycles in 2.038 ms.
DMA Controller Registers
Table 4-11 lists the DMA Controller Registers and their I/O port addresses. Note that there is a
set of registers for each DMA controller.
Table 4-11.
DMA Controller Registers
Register
4-18
Controller 1
Controller 2
R/W
Status
008h
0D0h
R
Command
008h
0D0h
W
Mode
00Bh
0D6h
W
Write Single Mask Bit
00Ah
0D4h
W
Write All Mask Bits
00Fh
0DEh
W
Software DRQx Request
009h
0D2h
W
Base and Current Address—Ch 0
000h
0C0h
W
Current Address—Ch 0
000h
0C0h
R
Base and Current Word Count—Ch 0
001h
0C2h
W
Current Word Count—Ch 0
001h
0C2h
R
Base and Current Address—Ch 1
002h
0C4h
W
Current Address—Ch 1
002h
0C4h
R
Base and Current Word Count—Ch 1
003h
0C6h
W
Current Word Count—Ch 1
003h
0C6h
R
Base and Current Address—Ch 2
004h
0C8h
W
Current Address—Ch 2
004h
0C8h
R
Base and Current Word Count—Ch 2
005h
0CAh
W
Current Word Count—Ch 2
005h
0CAh
R
Base and Current Address—Ch 3
006h
0CCh
W
Current Address—Ch 3
006h
0CCh
R
Base and Current Word Count—Ch 3
007h
0CEh
W
Current Word Count—Ch 3
007h
0CEh
R
Temporary (Command)
00Dh
0DAh
R
Reset Pointer Flip-Flop (Command)
00Ch
0D8h
W
Master Reset (Command)
00Dh
0DAh
W
Reset Mask Register (Command)
00Eh
0DCh
W
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4.4 Real-Time Clock and Configuration Memory
The Real-time clock (RTC) and configuration memory (also referred to as “CMOS”) functions
are provided by the 82801 component and is MC146818-compatible. As shown in the following
figure, the 82801 ICH8 component provides 256 bytes of battery-backed RAM divided into two
128-byte configuration memory areas. The RTC uses the first 14 bytes (00-0Dh) of the standard
memory area. All locations of the standard memory area (00-7Fh) can be directly accessed using
conventional OUT and IN assembly language instructions through I/O ports 70h/71h, although
the suggested method is to use the INT15 AX=E823h BIOS call.
0Dh
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h
82801
Register D
Register C
Register B
Register A
Year
Month
Date of Month
Day of Week
Hours (Alarm)
Hours (Timer)
Minutes (Alarm)
Minutes (Timer)
Seconds (Alarm)
Seconds (Timer)
FFh
Extended Config.
Memory Area
(128 bytes)
80h
7Fh
Standard Config.
Memory Area
(114 bytes)
RTC Area
(14 bytes)
0Eh
0Dh
00h
CMOS
Figure 4 11. Configuration Memory Map
A lithium 3-VDC battery is used for maintaining the RTC and configuration memory while the
system is powered down. During system operation a wire-Ored circuit allows the RTC and
configuration memory to draw power from the power supply. The battery is located in a battery
holder on the system board and has a life expectancy of three or more years. When the battery
has expired it is replaced with a Renata CR2032 or equivalent 3-VDC lithium battery.
4.4.1 Clearing CMOS
The contents of configuration memory (including the Power-On Password) can be cleared by the
following procedure:
1. Turn off the unit.
2. Disconnect the AC power cord from the outlet and/or system unit.
3. Remove the chassis hood (cover) and insure that no LEDs on the system board are
illuminated.
4. On the system board, press and hold the CMOS clear button (colored yellow) for at least 5
seconds.
5. Replace the chassis hood (cover).
6. Reconnect the AC power cord to the outlet and/or system unit.
7. Turn the unit on.
To clear only the Power-On Password refer to section 4.5.1.
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4.4.2 Standard CMOS Locations
Table 4-12 describes standard configuration memory locations 0Ah-3Fh. These locations are
accessible through using OUT/IN assembly language instructions using port 70/71h or BIOS
function INT15, AX=E823h.
Table 4-12.
Configuration Memory (CMOS) Map
Location
00-0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Function
Real-time clock
Diagnostic status
System reset code
Diskette drive type
Reserved
Hard drive type
Security functions
Equipment installed
Base memory size, low byte/KB
Base memory size, high byte/KB
Extended memory, low byte/KB
Extended memory, high byte/KB
Hard drive 1, primary controller
Hard drive 2, primary controller
Hard drive 1, secondary controller
Hard drive 2, secondary controller
Enhanced hard drive support
Reserved
Power management functions
Location
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh-2Fh
30h-31h
32h
33h
34h
35h
36h
37h-3Fh
40-FFh
Function
System board ID
System architecture data
Auxiliary peripheral configuration
Speed control external drive
Expanded/base mem. size, IRQ12
Miscellaneous configuration
Hard drive timeout
System inactivity timeout
Monitor timeout, Num Lock Cntrl
Additional flags
Checksum of locations 10h-2Dh
Total extended memory tested
Century
Miscellaneous flags set by BIOS
International language
APM status flags
ECC POST test single bit
Power-on password
Feature Control/Status
NOTES:
Assume unmarked gaps are reserved.
Higher locations (>3Fh) contain information that should be accessed using the INT15, AX=E845h
BIOS function (refer to Chapter 8 for BIOS function descriptions).
4.5 System Management
This section describes functions having to do with security, power management, temperature,
and overall status. These functions are handled by hardware and firmware (BIOS) and generally
configured through the Setup utility.
4.5.1 Security Functions
These systems include various features that provide different levels of security. Note that this
subsection describes only the hardware functionality (including that supported by Setup) and
does not describe security features that may be provided by the operating system and application
software.
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Power-On / Setup Password
These systems include a power-on and setup passwords, which may be enabled or disabled
(cleared) through a jumper on the system board. The jumper controls a GPIO input to the 82801
ICH8 that is checked during POST. The password is stored in configuration memory (CMOS)
and if enabled and then forgotten by the user will require that either the password be cleared
(preferable solution and described below) or the entire CMOS be cleared (refer to section 4.4.1).
To clear the password, use the following procedure:
1. Turn off the system and disconnect the AC power cord from the outlet and/or system unit.
2. Remove the cover (hood) as described in the appropriate User Guide or Maintainance And
Service Reference Guide. Insure that all system board LEDs are off (not illuminated).
3. Locate the password clear jumper (header is colored green and labeled E49 on these systems)
and move the jumper from pins 1 and 2 and place on (just) pin 2 (for safekeeping).
4. Replace the cover.
5. Re-connect the AC power cord to the AC outlet and/or system unit.
6. Turn on the system. The POST routine will clear and disable the password.
7. To re-enable the password feature, repeat steps 1-6, replacing the jumper on pins 1 and 2 of
header E49.
Setup Password
The Setup utility may be configured to be always changeable or changeable only by entering a
password. Refer to the previous procedure (Power On / Setup Password) for clearing the Setup
password.
Cable Lock Provision
These systems include a chassis cutout (on the rear panel) for the attachment of a cable lock
mechanism.
I/O Interface Security
The serial, parallel, USB, and diskette interfaces may be disabled individually through the Setup
utility to guard against unauthorized access to a system. In addition, the ability to write to or boot
from a removable media drive (such as the diskette drive) may be enabled through the Setup
utility. The disabling of the serial, parallel, and diskette interfaces are a function of the SCH5317
I/O controller. The USB ports are controlled through the 82801.
Chassis Security
Some systems feature Smart Cover (hood) Sensor and Smart Cover (hood) Lock mechanisms to
inhibit unauthorized tampering of the system unit.
Smart Cover Sensor
Some systems include a plunger switch that, when the cover (hood) is removed, closes and
grounds an input of the 82801 component. The battery-backed logic will record this “intrusion”
event by setting a specific bit. This bit will remain set (even if the cover is replaced) until the
system is powered up and the user completes the boot sequence successfully, at which time the
bit will be cleared. Through Setup, the user can set this function to be used by Alert-On-LAN
and or one of three levels of support for a “cover removed” condition:
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4-21
System Support
Level 0—Cover removal indication is essentially disabled at this level. During POST, status bit is
cleared and no other action is taken by BIOS.
Level 1—During POST the message “The computer's cover has been removed since the last
system start up” is displayed and time stamp in CMOS is updated.
Level 2—During POST the “The computer's cover has been removed since the last system start
up” message is displayed, time stamp in CMOS is updated, and the user is prompted for the
administrator password. (A Setup password must be enabled in order to see this option).
Smart Cover Lock (Optional)
Some systems support an optional solenoid-operated locking bar that, when activated, prevents
the cover (hood) from being removed. The GPIO ports 44 and 45 of the SCH5317 I/O controller
provide the lock and unlock signals to the solenoid. A locked hood may be bypassed by removing
special screws that hold the locking mechanism in place. The special screws are removed with
the Smart Cover Lock Failsafe Key.
4.5.2 Power Management
This system provides baseline hardware support of ACPI- and APM-compliant firmware and
software. Key power-consuming components (processor, chipset, I/O controller, and fan) can be
placed into a reduced power mode either automatically or by user control. The system can then
be brought back up (“wake-up”) by events defined by the ACPI 2.0 specification. The ACPI
wake-up events supported by this system are listed as follows:
4-22
ACPI Wake-Up Event
System Wakes From
Power Button
Suspend or soft-off
RTC Alarm
Suspend or soft-off
Wake On LAN (w/NIC)
Suspend or soft-off
PME
Suspend or soft-off
Serial Port Ring
Suspend or soft-off
USB
Suspend only
Keyboard
Suspend only
Mouse
Suspend only
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Technical Reference Guide
System Support
4.5.3 System Status
These systems provide a visual indication of system boot, ROM flash, and operational status
through the power LED and internal speaker, as described in Table 13.
d
.
Table 4-13.
System Operational Status LED Indications
System Status
PowerLED
Beeps [2]
S0: System on (normal operation)
Steady green
None
Action Required
None
S1: Suspend
Blinks green @ .5 Hz
None
None
S3: Suspend to RAM
Blinks green @ .5 Hz
None
None
S4: Suspend to disk
Off – clear
None
None
S5: Soft off
Off – clear
None
None
Processor thermal shutdown
Blinks red 2 times @ I Hz [1]
2
Check air flow, fans, heatsink
Processor not seated / installed
Blinks red 3 times @ I Hz [1]
3
Check processor presence/seating
Power supply overload failure
Blinks red 4 times @ I Hz [1]
4
Check system board problem [3],
Memory error (pre-video)
Blinks red 5 times @ I Hz [1]
5
Check DIMMs, system board
Video error
Blinks red 6 times @ I Hz [1]
6
Check graphics card or system board
PCA failure detected by BIOS (pre-video)
Blinks red 7 times @ I Hz [1]
7
Replace system board
Invalid ROM checksum error
Blinks red 8 times @ I Hz [1]
8
Reflash BIOS ROM
Boot failure (after power on)
Blinks red 9 times @ I Hz [1]
9
Check power supply, processor, sys. bd
Bad option card
Blinks red 10 times @ I Hz [1]
None
Replace option card
NOTES:
Beeps are repeated for 5 cycles, after which only blinking LED indication continues.
[1] Repeated after 2 second pause.
[2] Beeps are produced by the internal chassis speaker.
[3] Check that CPU power connector P3 is plugged in.
4.5.4 Thermal Sensing and Cooling
All systems feature a variable-speed fan mounted as part of the processor heatsink assembly. All
systems also provide or support an auxiliary chassis fan. All fans are controlled through
temperature sensing logic on the system board and/or in the power supply. There are some
electrical differences between form factors and between some models, although the overall
functionally is the same. Typical cooling conditions include the following:
1. Normal—Low fan speed.
2. Hot processor—ASIC directs Speed Control logic to increase speed of fan(s).
3. Hot power supply—Power supply increases speed of fan(s).
4. Sleep state—Fan(s) turned off. Hot processor or power supply will result in starting fan(s).
The RPM (speed) of all fans is the result of the temperature of the CPU as sensed by speed
control circuitry. The fans are controlled to run at the slowest (quietest) speed that will maintain
proper cooling.
using chassis and CPU fans must have both fans connected to their corresponding headers
✎ Units
to ensure proper cooling of the system.
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4-23
System Support
4.6 Register Map and Miscellaneous Functions
This section contains the system I/O map and information on general-purpose functions of the
ICH8 and I/O controller.
4.6.1 System I/O Map
Table 4-14 lists the fixed addresses of the input/output (I/O) ports.
Table 4-14
System I/O Map
I/O Port
Function
0000..001Fh
DMA Controller 1
0020..002Dh
Interrupt Controller 1
002E, 002Fh
Index, Data Ports to SCH5317 I/O Controller (primary)
0030..003Dh
Interrupt Controller
0040..0042h
Timer 1
004E, 004Fh
Index, Data Ports to SCH5317 I/O Controller (secondary)
0050..0052h
Timer / Counter
0060..0067h
Microcontroller, NMI Controller (alternating addresses)
0070..0077h
RTC Controller
0080..0091h
DMA Controller
0092h
Port A, Fast A20/Reset Generator
0093..009Fh
DMA Controller
00A0..00B1h
Interrupt Controller 2
00B2h, 00B3h
APM Control/Status Ports
00B4..00BDh
Interrupt Controller
00C0..00DFh
DMA Controller 2
00F0h
Coprocessor error register
0170..0177h
IDE Controller 2 (active only if standard I/O space is enabled for secondary controller)
01F0..01F7h
IDE Controller 1 (active only if standard I/O space is enabled for primary controller)
0278..027Fh
Parallel Port (LPT2)
02E8..02EFh
Serial Port (COM4)
02F8..02FFh
Serial Port (COM2)
0370..0377h
Diskette Drive Controller Secondary Address
0376h
IDE Controller 2 (active only if standard I/O space is enabled for primary drive)
0378..037Fh
Parallel Port (LPT1)
03B0..03DFh
Graphics Controller
03BC..03BEh
Parallel Port (LPT3)
03E8..03EFh
Serial Port (COM3)
03F0..03F5h
Diskette Drive Controller Primary Addresses
03F6h
IDE Controller 1 (active only if standard I/O space is enabled for sec. drive)
03F8..03FFh
Serial Port (COM1)
04D0, 04D1h
Interrupt Controller
0678..067Fh
Parallel Port (LPT2)
0778..077Fh
Parallel Port (LPT1)
07BC..07BEh
Parallel Port (LPT3)
0CF8h
PCI Configuration Address (dword access only )
0CF9h
Reset Control Register
0CFCh
PCI Configuration Data (byte, word, or dword access)
NOTE:
Assume unmarked gaps are unused, reserved, or used by functions that employ variable I/O
address mapping. Some ranges may include reserved addresses.
4-24
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Technical Reference Guide
System Support
4.6.2 SCH5317 I/O Controller Functions
The SCH5317 I/O controller contains various functions such as the keyboard/mouse interfaces,
diskette interface, serial interfaces, and parallel interface. While the control of these interfaces
uses standard AT-type I/O addressing (as described in chapter 5) the configuration of these
functions uses indexed ports unique to the SCH5317. In these systems, hardware strapping
selects I/O addresses 02Eh and 02Fh at reset as the Index/Data ports for accessing the logical
devices within the SCH5317. Table 4-15 lists the PnP standard control registers for the
SCH5317.
Table 4-15.
SCH5317 I/O Controller Control Registers
Index
02h
03h
07h
20h
21h
22h
23h
24h
25h
26h
27h
28-2Fh
Function
Configuration Control
Reserved
Logical Device (Interface) Select:
00h = Diskette Drive I/F
01h = Reserved
02h = Reserved
03h = Parallel I/F
04h = Serial I/F (UART 1/Port A)
05h = Serial I/F (UART 2/Port B)
06h = Reserved
07h = Keyboard I/F
08h = Reserved
09h = Reserved
0Ah = Runtime Registers (GPIO Config.)
0Bh = SMBus Configuration
Super I/O ID Register (SID)
Revision
Logical Device Power Control
Logical Device Power Management
PLL / Oscillator Control
Reserved
Configuration Address (Low Byte)
Configuration Address (High Byte)
Reserved
Reset Value
00h
00h
56h
-00h
00h
04h
NOTE:
For a detailed description of registers refer to appropriate documentation available from SMC
Corporation.
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4-25
System Support
The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after
the configuration phase has been activated by writing 55h to I/O port 2Eh. The desired interface
(logical device) is initiated by firmware selecting logical device number of the 47B347 using the
following sequence:
1. Write 07h to I/O register 2Eh.
2. Write value of logical device to I/O register 2Fh.
3. Write 30h to I/O register 2Eh.
4. Write 01h to I/O register 2Fh (this activates the interface).
Writing AAh to 2Eh deactivates the configuration phase.
The systems covered in this guide utilize the following specialized functions built into the LPC
SCH5317 I/O Controller:
4-26
■
Power/Hard drive LED control—The I/O controller provides color and blink control for the
front panel LEDs used for indicating system events (refer to Table 4-14).
■
Intruder sensing—The battery-backed D-latch logic internal to the SCH5317 is connected to
the hood sensor switch to record hood (cover) removal.
■
Hood lock/unlock—Supported on SFF, ST, MT, and CMT form factors, logic internal to the
SCH5317 controls the lock bar mechanism.
■
I/O security—The parallel, serial, and diskette interfaces may be disabled individually by
software and the SCH5317's disabling register locked. If the disabling register is locked, a
system reset through a cold boot is required to gain access to the disabling (Device Disable)
register.
■
Processor present/speed detection—One of the battery-back general-purpose inputs (GPI26)
of the SCH5317 detects if the processor has been removed. The occurrence of this event is
passed to the ICH8 that will, during the next boot sequence, initiate the speed selection
routine for the processor.
■
Legacy/ACPI power button mode control—The SCH5317 receives the pulse signal from the
system's power button and produces the PS On signal according to the mode (legacy or
ACPI) selected. Refer to chapter 7 for more information regarding power management.
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Technical Reference Guide
5
Input/Output Interfaces
5.1
Introduction
This chapter describes the standard (i.e., system board) interfaces that provide input and output
(I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped
registers. The following I/O interfaces are covered in this chapter:
5.2
■
SATA interface (5.2)
■
Diskette drive interface (5.3)
■
Serial interfaces (5.4)
■
Parallel interface (5.5)
■
Keyboard/pointing device interface (5.6)
■
Universal serial bus interface (5.7)
■
Audio subsystem (5.8)
■
Network interface controller (5.9)
SATA Interfaces
These systems provide one, three, or four serial ATA (SATA) interfaces that support tranfer rates
up to 3.0 Gb/s and RAID data protection functionality. The SATA interface duplicates most of
the functionality of the EIDE interface through a register interface that is equivalent to that of the
legacy IDE host adapter.
5.2.1 SATA Programming
The SATA interface is configured as a PCI device during POST and controlled through
I/O-mapped registers at runtime. Non-DOS (non-Windows) operating systems may require using
Setup (F10) for drive configuration.
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5-1
Input/Output Interfaces
SATA Configuration Registers
The SATA controller is configured as a PCI device with bus mastering capability. The PCI
configuration registers for the SATA controller function (PCI device #31, function #2) are listed
in Table 5-1.
Table 5-1.
SATA PCI Configuration Registers (82801, Device 31/Function 2)
PCI Conf.
Addr.
Register
Reset
Value
PCI Conf.
Addr.
Register
Reset
Value
00-01h
Vender ID
8086h
0F..1Fh
Reserved
0’s
02-03h
Device ID
24D1h
10-17h
Pri. Cmd, Cntrl.
Addrs.
1 (both)
04-05h
PCI Command
0000h
18-1Fh
Sec. Cmd, Cntrl.
Addrs.
1 (both)
06-07h
PCI Status
02B0h
20-23h
BMstr Base Address
1
08h
Revision ID
00h
2C, 2Dh
Subsystem Vender ID
0000h
09h
Programming
8Ah
2E, 2Fh
Subsystem ID
0000h
0Ah
Sub-Class
01h
34h
Capabilities pointer
80h
0Bh
Base Class Code
01h
3Ch
Interrupt Line
00h
0Dh
Master Latency Timer
00h
3Dh
Interrupt Pin
01h
0Eh
Header Type
00h
40-57h
Timing, Control
All 0’s
SATA Bus Master Control Registers
The SATA interface can perform PCI bus master operations using the registers listed in Table
5-2. These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI
configuration register 20h in the previous table. As indicated, these registers are virtually a copy
of those used by EIDE operations discussed in the EIDE section.
Table 5-2.
IDE Bus Master Control Registers
I/O Addr.
Offset
5-2
Size
(Bytes)
Register
Default Value
00h
1
Bus Master IDE Command (Primary)
00h
02h
1
Bus Master IDE Status (Primary)
00h
04h
4
Bus Master IDE Descriptor Pointer (Primary)
08h
1
Bus Master IDE Command (Secondary)
00h
0Ah
2
Bus Master IDE Status (Secondary)
00h
0Ch
4
Bus Master IDE Descriptor Pointer (Secondary
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0000 0000h
0000 0000h
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Input/Output Interfaces
5.2.2 SATA Connector
The 7-pin SATA connector is shown in the figure below.
Pin 1
Pin 7
B
A
Figure 5-1. 7-Pin SATA Connector (P60-P63 on system board).
Table 5-3.
7-Pin SATA Connector Pinout
Pin
Description
Pin
Description
1
Ground
6
RX positive
2
TX positive
7
Ground
3
TX negative
A
Holding clip
4
Ground
B
Holding clip
5
RX negative
--
--
5.2.3 RAID Functionality
The ICH8 DO component includes Intel RAID migration technology that simplifies the
migration from a single hard to a RAID0 or RAID1 dual hard drive array without requiring OS
reinstallation. Intel Matrix RAID provides exceptional storage performance with increased data
protection for configurations using dual drive arrays. A software solution is included that
provides full management and status reporting of the RAID array, and the BIOS ROM also
supports RAID creation, naming, and deletion of RAID arrays.
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5-3
Input/Output Interfaces
5.3
Diskette Drive Interface
The MT and CMT form factors support a diskette drive through a standard 34-pin diskette drive
connector. Selected models come standard with a 3.5-inch 1.44-MB diskette drive installed as
drive A.
The diskette drive interface function is integrated into the SCH5317 super I/O component. The
internal logic of the I/O controller is software-compatible with standard 82077-type logic. The
diskette drive controller has three operational phases in the following order:
■
Command phase—The controller receives the command from the system.
■
Execution phase—The controller carries out the command.
■
Results phase—Status and results data is read back from the controller to the system.
The Command phase consists of several bytes written in series from the CPU to the data register
(3F5h/375h). The first byte identifies the command and the remaining bytes define the
parameters of the command. The Main Status register (3F4h/374h) provides data flow control
for the diskette drive controller and must be polled between each byte transfer during the
Command phase.
The Execution phase starts as soon as the last byte of the Command phase is received. An
Execution phase may involve the transfer of data to and from the diskette drive, a mechnical
control function of the drive, or an operation that remains internal to the diskette drive controller.
Data transfers (writes or reads) with the diskette drive controller are by DMA, using the DRQ2
and DACK2- signals for control.
The Results phase consists of the CPU reading a series of status bytes (from the data register
(3F5h/375h)) that indicate the results of the command. Note that some commands do not have a
Result phase, in which case the Execution phase can be followed by a Command phase.
During periods of inactivity, the diskette drive controller is in a non-operation mode known as the
Idle phase.
5.3.1 Diskette Drive Programming
Programming the diskette drive interface consists of configuration, which occurs typically during
POST, and control, which occurs at runtime.
Diskette Drive Interface Configuration
The diskette drive controller must be configured for a specific address and also must be enabled
before it can be used. Address selection and enabling of the diskette drive interface are affected
by firmware through the PnP configuration registers of the SCH5317 I/O controller during
POST.
The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after
the configuration phase has been activated by writing 55h to I/O port 2Eh. The diskette drive I/F
is initiated by firmware selecting logical device 0 of the SCH5317 using the following sequence:
1. Write 07h to I/O register 2Eh.
2. Write 00h to I/O register 2Fh (this selects the diskette drive I/F).
3. Write 30h to I/O register 2Eh.
4. Write 01h to I/O register 2Fh (this activates the interface).
Writing AAh to 2Eh deactivates the configuration phase.
5-4
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Technical Reference Guide
Input/Output Interfaces
The diskette drive I/F configuration registers are listed in the following table:
Table 5-4.
Diskette Drive Interface Configuration Registers
Index
Address
Function
R/W
Reset
Value
30h
Activate
R/W
01h
60-61h
Base Address
R/W
03F0h
70h
Interrupt Select
R/W
06h
74h
DMA Channel Select
R/W
02h
F0h
DD Mode
R/W
02h
F1h
DD Option
R/W
00h
F2h
DD Type
R/W
FFh
F4h
DD 0
R/W
00h
F5h
DD 1
R/W
00h
For detailed configuration register information refer to the SMSC data sheet for the SCH5317
I/O component.
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5-5
Input/Output Interfaces
Diskette Drive Interface Control
The BIOS function INT 13 provides basic control of the diskette drive interface. The diskette
drive interface can be controlled by software through the SCH5317's I/O-mapped registers listed
in Table 5-5. The diskette drive controller of the SCH5317 operates in the PC/AT mode in these
systems.
Table 5-5.
Diskette Drive Interface Control Registers
Primary
Address
5-6
Second.
Address Register
R/W
3F0h
370h
Status Register A:
<7> Interrupt pending
<6> Reserved (always 1)
<5> STEP pin status (active high)
<4> TRK 0 status (active high)
<3> HDSEL status (0 = side 0, 1 = side 1)
<2> INDEX status (active high)
<1> WR PRTK status (0 = disk is write protected)
<0> Direction (0 = outward, 1 = inward)
R
3F1h
371h
Status Register B:
<7,6> Reserved (always 1’s)
<5> DOR bit 0 status
<4> Write data toggle
<3> Read data toggle
<2> WGATE status (active high)
<1,0> MTR 2, 1 ON- status (active high)
R
3F2h
372h
Digital Output Register (DOR):
<7,6> Reserved
<5,4> Motor 1, 0 enable (active high)
<3> DMA enable (active high)
<2> Reset (active low)
<1,0> Drive select (00 = Drive 1, 01 = Drive 2, 10 = Reserved, 11 =
Tape drive)
R/W
3F3h
373h
Tape Drive Register (available for compatibility)
R/W
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Input/Output Interfaces
Table 5-5. (Continued)
Diskette Drive Interface Control Registers
Primary
Address
Second.
Address Register
3F4h
374h
R/W
Main Status Register (MSR):
<7> Request for master (host can transfer data) (active high)
<6> Transfer direction (0 – write, 1 = read)
<5> non-DMA execution (active high)
<4> Command busy (active high)
<3,2> Reserved
<1,0> Drive 1, 2 busy (active high)
Data Rate Select Register (DRSR):
<7> Software reset (active high)
<6> Low power mode enable (active high)
<5> Reserved (0)
<4..2> Precompensation select (default = 000)
<1,0> Data rate select (00 = 500 Kb/s, 01 = 300 Kb/s, 10 = 250
Kb/s, 11 = 2/1 Mb/s)
Data Register:
<7..0> Data
R
W
3F5h
375h
R/W
3F6h
376h
Reserved
--
3F7h
377h
Digital Input Register (DIR):
<7> DSK CHG status (records opposite value of pin)
<6..0> Reserved (0’s)
Configuration Control Register (CCR):
<7..2> Reserved
<1,0> Data rate select (00 = 500 Kb/s, 01 = 300 Kb/s, 10 = 250
Kb/s, 11 = 2/1 Mb/s)
R
W
NOTE: The most recently written data rate value to either DRSR or CCR will be in effect.
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5-7
Input/Output Interfaces
5.3.2 Diskette Drive Connector
The SFF, ST, MT, and CMT form factors use a standard 34-pin connector for diskette drives
(refer to Figure 5-2 and Table 5-6 for the pinout). Drive power is supplied through a separate
connector.
2
1
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
Figure 5-2. 34-Pin Diskette Drive Connector (P10 on system board).
Table 5-6.
34-Pin Diskette Drive Connector Pinout
5-8
Pin
Signal
Description
Pin
Signal
Description
1
GND
Ground
18
DIR-
Drive head direction control
2
LOW DEN-
Low density select
19
GND
Ground
3
---
(KEY)
20
STEP-
Drive head track step cntrl.
4
MEDIA ID-
Media identification
21
GND
Ground
5
GND
Ground
22
WR DATA-
Write data
6
DRV 4 SEL-
Drive 4 select
23
GND
Ground
7
GND
Ground
24
WR ENABLE-
Enable for WR DATA-
8
INDEX-
Media index is detected
25
GND
Ground
9
GND
Ground
26
TRK 00-
Heads at track 00 indicator
10
MTR 1 ON-
Activates drive motor
27
GND
Ground
11
GND
Ground
28
WR PRTK-
Media write protect status
12
DRV 2 SEL-
Drive 2 select
29
GND
Ground
13
GND
Ground
30
RD DATA-
Data and clock read off disk
14
DRV 1 SEL-
Drive 1 select
31
GND
Ground
15
GND
Ground
32
SIDE SEL-
Head select (side 0 or 1)
16
MTR 2 ON-
Activates drive motor
33
GND
Ground
17
GND
Ground
34
DSK CHG-
Drive door opened indicator
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Input/Output Interfaces
5.4
Serial Interface
Systems covered in this guide may include one RS-232-C type serial interface to transmit and
receive asynchronous serial data with external devices. Some systems may allow the installation
of a second serial interface through an adapter that consists of a PCI bracket and a cable that
attaches to header P52 on the system board. The serial interface function is provided by the
SCH5317 I/O controller component that includes two NS16C550-compatible UARTs.
The UART supports the standard baud rates up through 115200, and also special high speed rates
of 239400 and 460800 baud. The baud rate of the UART is typically set to match the capability
of the connected device. While most baud rates may be set at runtime, baud rates 230400 and
460800 must be set during the configuration phase.
5.4.1 Serial Connector
The serial interface uses a DB-9 connector as shown in the following figure with the pinout listed
in Table 5-7.
Figure 5-3. DB-9 Serial Interface Connector (as viewed from rear of chassis)
Table 5-7.
DB-9 Serial Connector Pinout
Pin
Signal
Description
Pin
Signal
Description
1
CD
Carrier Detect
6
DSR
Data Set Ready
2
RX Data
Receive Data
7
RTS
Request To Send
3
TX Data
Transmit Data
8
CTS
Clear To Send
4
DTR
Data Terminal Ready
9
RI
Ring Indicator
5
GND
Ground
--
--
--
The standard RS-232-C limitation of 50 feet (or less) of cable between the DTE (computer) and
DCE (modem) should be followed to minimize transmission errors. Higher baud rates may
require shorter cables.
5.4.2 Serial Interface Programming
Programming the serial interfaces consists of configuration, which occurs during POST, and
control, which occurs during runtime.
Serial Interface Configuration
The serial interface must be configured for a specific address range (COM1, COM2, etc.) and
also must be activated before it can be used. Address selection and activation of the serial
interface are affected through the PnP configuration registers of the SCH5317 I/O controller.
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5-9
Input/Output Interfaces
The serial interface configuration registers are listed in the following table:
Table 5-8.
Serial Interface Configuration Registers
Index Address
Function
R/W
30h
Activate
R/W
60h
Base Address MSB
R/W
61h
Base Address LSB
R/W
70h
Interrupt Select
R/W
F0h
Mode Register
R/W
Serial Interface Control
The BIOS function INT 14 provides basic control of the serial interface. The serial interface can
be directly controlled by software through the I/O-mapped registers listed in Table 5-17
Table 5-9.
Serial Interface Control Registers
5-10
COM1
Addr.
COM2
Addr.
3F8h
2F8h
Receive Data Buffer
Transmit Data Buffer
Baud Rate Divisor Register 0 (when bit 7 of Line Control Reg. Is set)
R
W
W
3F9h
2F9h
Baud Rate Divisor Register 1 (when bit 7 of Line Control Reg. Is set)
Interrupt Enable Register
W
R/W
3FAh
2FAh
Interrupt ID Register
FIFO Control Register
R
W
3FBh
2FBh
Line Control Register
R/W
3FCh
2FCh
Modem Control Register
R/W
3FDh
2FDh
Line Status Register
R
3FEh
2FEh
Modem Status
R
Register
R/W
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Input/Output Interfaces
5.5
Parallel Interface
Systems covered in this guide may include a parallel interface for connection to a peripheral
device with a compatible interface, the most common being a printer. The parallel interface
function is integrated into the SCH5317 I/O controller component and provides bi-directional
8-bit parallel data transfers with a peripheral device. The parallel interface supports three main
modes of operation:
■
Standard Parallel Port (SPP) mode
■
Enhanced Parallel Port (EPP) mode
■
Extended Capabilities Port (ECP) mode
These three modes (and their submodes) provide complete support as specified for an IEEE 1284
parallel port.
5.5.1 Standard Parallel Port Mode
The Standard Parallel Port (SPP) mode uses software-based protocol and includes two
sub-modes of operation, compatible and extended, both of which can provide data transfers up to
150 KB/s. In the compatible mode, CPU write data is simply presented on the eight data lines. A
CPU read of the parallel port yields the last data byte that was written.
The following steps define the standard procedure for communicating with a printing device:
1. The system checks the Printer Status register. If the Busy, Paper Out, or Printer Fault signals
are indicated as being active, the system either waits for a status change or generates an error
message.
2. The system sends a byte of data to the Printer Data register, then pulses the printer STROBE
signal (through the Printer Control register) for at least 500 ns.
3. The system then monitors the Printer Status register for acknowledgment of the data byte
before sending the next byte.
In extended mode, a direction control bit (CTR 37Ah, bit <5>) controls the latching of output
data while allowing a CPU read to fetch data present on the data lines, thereby providing
bi-directional parallel transfers to occur.
The SPP mode uses three registers for operation: the Data register (DTR), the Status register
(STR) and the Control register (CTR). Address decoding in SPP mode includes address lines A0
and A1.
5.5.2 Enhanced Parallel Port Mode
In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due
to a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7
and 1.9 are both supported. For the parallel interface to be initialized for EPP mode, a negotiation
phase is entered to detect whether or not the connected peripheral is compatible with EPP mode.
If compatible, then EPP mode can be used. In EPP mode, system timing is closely coupled to
EPP timing. A watchdog timer is used to prevent system lockup.
Five additional registers are available in EPP mode to handle 16- and 32-bit CPU accesses with
the parallel interface. Address decoding includes address lines A0, A1, and A2.
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5-11
Input/Output Interfaces
5.5.3 Extended Capabilities Port Mode
The Extended Capabilities Port (ECP) mode, like EPP, also uses a hardware protocol-based
design that supports transfers up to 2 MB/s. Automatic generation of addresses and strobes as
well as Run Length Encoding (RLE) decompression is supported by ECP mode. The ECP mode
includes a bi-directional FIFO buffer that can be accessed by the CPU using DMA or
programmed I/O. For the parallel interface to be initialized for ECP mode, a negotiation phase is
entered to detect whether or not the connected peripheral is compatible with ECP mode. If
compatible, then ECP mode can be used.
Ten control registers are available in ECP mode to handle transfer operations. In accessing the
control registers, the base address is determined by address lines A2-A9, with lines A0, A1, and
A10 defining the offset address of the control register. Registers used for FIFO operations are
accessed at their base address + 400h (i.e., if configured for LPT1, then 378h + 400h = 778h).
The ECP mode includes several sub-modes as determined by the Extended Control register. Two
submodes of ECP allow the parallel port to be controlled by software. In these modes, the FIFO
is cleared and not used, and DMA and RLE are inhibited.
5.5.4 Parallel Interface Programming
Programming the parallel interface consists of configuration, which typically occurs during
POST, and control, which occurs during runtime.
Parallel Interface Configuration
The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and
also must be enabled before it can be used. When configured for EPP or ECP mode, additional
considerations must be taken into account. Address selection, enabling, and EPP/ECP mode
parameters of the parallel interface are affected through the PnP configuration registers of the
SCH5317 I/O controller. Address selection and enabling are automatically done by the BIOS
during POST but can also be accomplished with the Setup utility and other software.
The parallel interface configuration registers are listed in the following table:
Table 5-10.
Parallel Interface Configuration Registers
Index
Address Function
5-12
R/W
Reset Value
30h
Activate
R/W
00h
60h
Base Address MSB
R/W
00h
61h
Base Address LSB
R/W
00h
70h
Interrupt Select
R/W
00h
74h
DMA Channel Select
R/W
04h
F0h
Mode Register
R/W
00h
F1h
Mode Register 2
R/W
00h
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Input/Output Interfaces
Parallel Interface Control
The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions
such as initialization, character printing, and printer status are provide by subfunctions of INT
17. The parallel interface is controllable by software through a set of I/O mapped registers. The
number and type of registers available depends on the mode used (SPP, EPP, or ECP). Table 5-11
lists the parallel registers and associated functions based on mode.
Table 5-11.
Parallel Interface Control Registers
SPP
Mode
Ports
EPP
Mode
Ports
ECP
Mode
Ports
Data
LPT1,2,3
LPT1,2
LPT1,2,3
Base + 1h
Printer Status
LPT1,2,3
LPT1,2
LPT1,2,3
Base + 2h
Control
LPT1,2,3
LPT1,2
LPT1,2,3
Base + 3h
Address
--
LPT1,2
--
Base + 4h
Data Port 0
--
LPT1,2
--
Base + 5h
Data Port 1
--
LPT1,2
--
Base + 6h
Data Port 2
--
LPT1,2
--
Base + 7h
Data Port 3
--
LPT1,2
--
Base + 400h
Parallel Data FIFO
--
--
LPT1,2,3
Base + 400h
ECP Data FIFO
--
--
LPT1,2,3
Base + 400h
Test FIFO
--
--
LPT1,2,3
Base + 400h
Configuration Register A
--
--
LPT1,2,3
Base + 401h
Configuration Register B
--
--
LPT1,2,3
Base + 402h
Extended Control Register
--
--
LPT1,2,3
I/O
Address
Register
Base
Base Address:
LPT1 = 378h
LPT2 = 278h
LPT3 = 3BCh
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5-13
Input/Output Interfaces
5.5.5 Parallel Interface Connector
Figure 5-4 and Table 5-12 show the connector and pinout of the parallel interface connector.
Note that some signals are redefined depending on the port's operational mode.
Figure 5-4. DB-25 Parallel Interface Connector (as viewed from rear of chassis)
Table 5-12.
DB-25 Parallel Connector Pinout
Pin
Signal
Function
Pin
Signal
Function
1
STB-
Strobe / Write [1]
14
LF-
Line Feed [2]
2
D0
Data 0
15
ERR-
Error [3]
3
D1
Data 1
16
INIT-
Initialize Paper [4]
4
D2
Data 2
17
SLCTIN-
Select In / Address. Strobe [1]
5
D3
Data 3
18
GND
Ground
6
D4
Data 4
19
GND
Ground
7
D5
Data 5
20
GND
Ground
8
D6
Data 6
21
GND
Ground
9
D7
Data 7
22
GND
Ground
10
ACK-
Acknowledge / Interrupt [1]
23
GND
Ground
11
BSY
Busy / Wait [1]
24
GND
Ground
12
PE
Paper End / User defined [1]
25
GND
Ground
13
SLCT
Select / User defined [1]
--
--
--
NOTES:
[1] Standard and ECP mode function / EPP mode function
[2] EPP mode function: Data Strobe
ECP modes: Auto Feed or Host Acknowledge
[3] EPP mode: user defined
ECP modes:Fault or Peripheral Req.
[4] EPP mode: Reset
ECP modes: Initialize or Reverse Req.
5-14
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Input/Output Interfaces
5.6
Keyboard/Pointing Device Interface
The keyboard/pointing device interface function is provided by the SCH5317 I/O controller
component, which integrates 8042-compatible keyboard controller logic (hereafter referred to as
simply the “8042”) to communicate with the keyboard and pointing device using bi-directional
serial data transfers. The 8042 handles scan code translation and password lock protection for the
keyboard as well as communications with the pointing device. This section describes the
interface itself. The keyboard is discussed in the Appendix C.
5.6.1 Keyboard Interface Operation
The data/clock link between the 8042 and the keyboard is uni-directional for Keyboard Mode 1
and bi-directional for Keyboard Modes 2 and 3. (These modes are discussed in detail in
Appendix C). This section describes Mode 2 (the default) mode of operation.
Communication between the keyboard and the 8042 consists of commands (originated by either
the keyboard or the 8042) and scan codes from the keyboard. A command can request an action
or indicate status. The keyboard interface uses IRQ1 to get the attention of the CPU.
The 8042 can send a command to the keyboard at any time. When the 8042 wants to send a
command, the 8042 clamps the clock signal from the keyboard for a minimum of 60 us. If the
keyboard is transmitting data at that time, the transmission is allowed to finish. When the 8042 is
ready to transmit to the keyboard, the 8042 pulls the data line low, causing the keyboard to
respond by pulling the clock line low as well, allowing the start bit to be clocked out of the 8042.
The data is then transferred serially, LSb first, to the keyboard (Figure 5-5). An odd parity bit is
sent following the eighth data bit. After the parity bit is received, the keyboard pulls the data line
low and clocks this condition to the 8042. When the keyboard receives the stop bit, the clock line
is pulled low to inhibit the keyboard and allow it to process the data.
Start
Bit
0
D0
(LSb)
1
D1
D2
D3
D4
D5
D6
0
1
1
0
1
1
Parity
D7
(MSb)
1
1
Stop
Bit
0
Data
Clock
Th
Tcy
Tcl Tch
Parameter
Minimum
Tcy (Cycle Time)
0 us
Tcl (Clock Low)
25 us
Tch (Clock High)
25 us
Th (Data Hold)
0 us
Tss (Stop Bit Setup) 8 us
Tsh (Stop Bit Hold) 15 us
Tss
Tsh
Maximum
80 us
35 us
45 us
25 us
20 us
25 us
Figure 5-5. 8042-To-Keyboard Transmission of Code EDh, Timing Diagram
Control of the data and clock signals is shared by the 8042and the keyboard depending on the
originator of the transferred data. Note that the clock signal is always generated by the keyboard.
After the keyboard receives a command from the 8042, the keyboard returns an ACK code. If a
parity error or timeout occurs, a Resend command is sent to the 8042.
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5-15
Input/Output Interfaces
Table 5-13 lists and describes commands that can be issued by the 8042 to the keyboard.
Table 5-13.
8042-To-Keyboard Commands
5-16
Command
Value
Description
Set/Reset Status Indicators
EDh
Enables LED indicators. Value EDh is followed by an option
byte that specifies the indicator as follows:
Bits <7..3> not used
Bit <2>, Caps Lock (0 = off, 1 = on)
Bit <1>, NUM Lock (0 = off, 1 = on)
Bit <0>, Scroll Lock (0 = off, 1 = on)
Echo
EEh
Keyboard returns EEh when previously enabled.
Invalid Command
EFh/F1h
These commands are not acknowledged.
Select Alternate Scan Codes
F0h
Instructs the keyboard to select another set of scan codes
and sends an option byte after ACK is received:
01h = Mode 1
02h = Mode 2
03h = Mode 3
Read ID
F2h
Instructs the keyboard to stop scanning and return two
keyboard ID bytes.
Set Typematic Rate/Display
F3h
Instructs the keyboard to change typematic rate and delay to
specified values:
Bit <7>, Reserved—0
Bits <6,5>, Delay Time
00 = 250 ms
01 = 500 ms
10 = 750 ms
11 = 1000 ms
Bits <4..0>, Transmission Rate:
00000 = 30.0 ms
00001 = 26.6 ms
00010 = 24.0 ms
00011 = 21.8 ms
:
11111 = 2.0 ms
Enable
F4h
Instructs keyboard to clear output buffer and last typematic
key and begin key scanning.
Default Disable
F5h
Resets keyboard to power-on default state and halts scanning
pending next 8042 command.
Set Default
F6h
Resets keyboard to power-on default state and enable
scanning.
Set Keys—Typematic
F7h
Clears keyboard buffer and sets default scan code set. [1]
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Input/Output Interfaces
Table 5-13. (Continued)
8042-To-Keyboard Commands
Command
Value
Description
Set Keys—Make/Brake
F8h
Clears keyboard buffer and sets default scan code set. [1]
Set Keys—Make
F9h
Clears keyboard buffer and sets default scan code set. [1]
Set Keys—
Typematic/Make/Brake
FAh
Clears keyboard buffer and sets default scan code set. [1]
Set Type Key—Typematic
FBh
Clears keyboard buffer and prepares to receive key ID. [1]
Set Type Key—Make/Brake
FCh
Clears keyboard buffer and prepares to receive key ID. [1]
Set Type Key—Make
FDh
Clears keyboard buffer and prepares to receive key ID. [1]
Resend
FEh
8042 detected error in keyboard transmission.
Reset
FFh
Resets program, runs keyboard BAT, defaults to Mode 2.
Note: [1] Used in Mode 3 only.
5.6.2 Pointing Device Interface Operation
The pointing device (typically a mouse) connects to a 6-pin DIN-type connector that is identical
to the keyboard connector both physically and electrically. The operation of the interface (clock
and data signal control) is the same as for the keyboard. The pointing device interface uses the
IRQ12 interrupt.
5.6.3 Keyboard/Pointing Device Interface Programming
Programming the keyboard interface consists of configuration, which occurs during POST, and
control, which occurs during runtime.
8042 Configuration
The keyboard/pointing device interface must be enabled and configured for a particular speed
before it can be used. Enabling and speed parameters of the 8042 logic are affected through the
PnP configuration registers of the SCH5317 I/O controller. Enabling and speed control are
automatically set by the BIOS during POST but can also be accomplished with the Setup utility
and other software.
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5-17
Input/Output Interfaces
The keyboard interface configuration registers are listed in the following table:
Table 5-14.
Keyboard Interface Configuration Registers
Index
Address Function
R/W
30h
Activate
R/W
70h
Primary Interrupt Select
R/W
72h
Secondary Interrupt Select
R/W
F0h
Reset and A20 Select
R/W
8042 Control
The BIOS function INT 16 is typically used for controlling interaction with the keyboard.
Sub-functions of INT 16 conduct the basic routines of handling keyboard data (i.e., translating
the keyboard's scan codes into ASCII codes). The keyboard/pointing device interface is accessed
by the CPU through I/O mapped ports 60h and 64h, which provide the following functions:
■
Output buffer reads
■
Input buffer writes
■
Status reads
■
Command writes
Ports 60h and 64h can be accessed using the IN instruction for a read and the OUT instruction for
a write. Prior to reading data from port 60h, the “Output Buffer Full” status bit (64h, bit <0>)
should be checked to ensure data is available. Likewise, before writing a command or data, the
“Input Buffer Empty” status bit (64h, bit <1>) should also be checked to ensure space is
available.
I/O Port 60h
I/O port 60h is used for accessing the input and output buffers. This register is used to send and
receive data from the keyboard and the pointing device. This register is also used to send the
second byte of multi-byte commands to the 8042 and to receive responses from the 8042 for
commands that require a response.
A read of 60h by the CPU yields the byte held in the output buffer. The output buffer holds data
that has been received from the keyboard and is to be transferred to the system.
A CPU write to 60h places a data byte in the input byte buffer and sets the CMD/ DATA bit of the
Status register to DATA. The input buffer is used for transferring data from the system to the
keyboard. All data written to this port by the CPU will be transferred to the keyboard except
bytes that follow a multibyte command that was written to 64h
5-18
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Input/Output Interfaces
I/O Port 64h
I/O port 64h is used for reading the status register and for writing commands. A read of 64h by
the CPU will yield the status byte defined as follows:
Bit
Function
7..4
General Purpose Flags.
3
CMD/DATA Flag (reflects the state of A2 during a CPU write).
0 = Data
1 = Command
2
General Purpose Flag.
1
Input Buffer Full. Set (to 1) upon a CPU write. Cleared by
IN A, DBB instruction.
0
Output Buffer Full (if set). Cleared by a CPU read of the buffer.
A CPU write to I/O port 64h places a command value into the input buffer and sets the
CMD/DATA bit of the status register (bit <3>) to CMD.
Table 5-15 lists the commands that can be sent tothe 8042 by the CPU. The 8042 uses IRQ1 for
gaining the attention of the CPU.
Table 5-15.
CPU Commands to the 8042
Value
Command Description
20h
Put current command byte in port 60h.
60h
Load new command byte.
A4h
Test password installed. Tests whether or not a password is installed in the 8042:
If FAh is returned, password is installed.
If F1h is returned, no password is installed.
A5h
Load password. This multi-byte operation places a password in the 8042 using the following
manner:
1. Write A5h to port 64h.
2. Write each character of the password in 9-bit scan code (translated) format to port 60h.
3. Write 00h to port 60h.
A6h
Enable security. This command places the 8042 in password lock mode following the A5h
command. The correct password must then be entered before further communication with the
8042 is allowed.
A7h
Disable pointing device. This command sets bit <5> of the 8042 command byte, pulling the clock
line of the pointing device interface low.
A8h
Enable pointing device. This command clears bit <5> of the 8042 command byte, activating the
clock line of the pointing device interface.
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5-19
Input/Output Interfaces
Table 5-15. (Continued)
CPU Commands to the 8042
5-20
Value
Command Description
A9h
Test the clock and data lines of the pointing device interface and place test results in the output
buffer.
00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high
AAh
Initialization. This command causes the 8042 to inhibit the keyboard and pointing device and
places 55h into the output buffer.
ABh
Test the clock and data lines of the keyboard interface and place test results in the output buffer.
00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high
ADh
Disable keyboard command (sets bit <4> of the 8042 command byte).
AEh
Enable keyboard command (clears bit <4> of the 8042 command byte).
C0h
Read input port of the 8042. This command directs the 8042 to transfer the contents of the input
port to the output buffer so that they can be read at port 60h.
C2h
Poll Input Port High. This command directs the 8042 to place bits <7..4> of the input port into the
upper half of the status byte on a continous basis until another command is received.
C3h
Poll Input Port Low. This command directs the 8042 to place bits <3..0> of the input port into the
lower half of the status byte on a continous basis until another command is received.
D0h
Read output port. This command directs the 8042 to transfer the contents of the output port to the
output buffer so that they can be read at port 60h.
D1h
Write output port. This command directs the 8042 to place the next byte written to port 60h into
the output port (only bit <1> can be changed).
D2h
Echo keyboard data. Directs the 8042 to send back to the CPU the next byte written to port 60h
as if it originated from the keyboard. No 11-to-9 bit translation takes place but an interrupt
(IRQ1) is generated if enabled.
D3h
Echo pointing device data. Directs the 8042 to send back to the CPU the next byte written to port
60h as if it originated from the pointing device. An interrupt (IRQ12) is generated if enabled.
D4h
Write to pointing device. Directs the 8042 to send the next byte written to 60h to the pointing
device.
E0h
Read test inputs. Directs the 8042 to transfer the test bits 1 and 0 into bits <1,0> of the output
buffer.
F0h-FFh
Pulse output port. Controls the pulsing of bits <3..0> of the output port (0 = pulse, 1 = don’t
pulse). Note that pulsing bit <0> will reset the system.
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5.6.4 Keyboard/Pointing Device Interface Connector
The legacy-light model provides separate PS/2 connectors for the keyboard and pointing device.
Both connectors are identical both physically and electrically. Figure 5-6 and Table 5-16 show
the connector and pinout of the keyboard/pointing device interface connectors.
Figure 5-6. PS/2 Keyboard or Pointing Device Interface Connector (as viewed from rear of chassis)
Table 5-16.
Keyboard/Pointing Device Connector Pinout
Pin
Signal
Description
Pin
Signal
Description
1
DATA
Data
4
+ 5 VDC
Power
2
NC
Not Connected
5
CLK
Clock
3
GND
Ground
6
NC
Not Connected
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5-21
Input/Output Interfaces
5.7
Universal Serial Bus Interface
The Universal Serial Bus (USB) interface provides asynchronous/isochronous data transfers with
compatible peripherals such as keyboards, printers, or modems. This high-speed interface
supports hot-plugging of compatible devices, making possible system configuration changes
without powering down or even rebooting systems.
These systems provide eight USB ports, two front panel USB ports (which may be disabled) and
six USB ports on the rear panel. The USB ports are dynamically configured to either a USB 1.1
controller or the USB 2.0 controller depending on the capability of the peripheral device. The
1.1 controllers provide a maximum transfer rate of 12 Mb/s while the 2.0 controller provides a
maximum transfer rate of 480 Mb/s. Table 5-17 shows the mapping of the USB ports.
USB
Table 5-17.
ICH8 USB Port Mapping
ICH8
Controller
5-22
USB Connector Location
Signals
USDT, SFF, ST Form Factors
MT & CMT Form Factors
USB 1.1 #1,
USB 2.0 #1
Data 0P, 0N
Rear panel quad USB stack
Rear panel quad USB stack
Data 1P, 1N
Rear panel quad USB stack
Rear panel quad USB stack
USB 1.1 #2
USB 2.0 #1
Data 2P, 2N
Rear panel dual USB with RJ-45
Rear panel quad USB stack
Data 3P, 3N
Rear panel dual USB with RJ-45
Rear panel quad USB stack
USB 1.1 #3
USB 2.0 #1
Data 4-5P/N
Not used
Not used
USB 1.1 #4
USB 2.0 #2
Data 6P, 6N
Rear panel quad USB stack
Rear panel dual USB with RJ-45
Data 7P, 7N
Rear panel quad USB stack
Rear panel dual USB with RJ-45
USB 1.1 #5
USB 2.0 #2
Data 8P, 8N
Front panel USB
Front panel USB
Data 9P, 9N
Front panel USB
Front panel USB
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5.7.1 USB Data Formats
The USB I/F uses non-return-to-zero inverted (NRZI) encoding for data transmissions, in which
a 1 is represented by no change (between bit times) in signal level and a 0 is represented by a
change in signal level. Bit stuffing is employed prior to NRZ1 encoding so that in the event a
string of 1's is transmitted (normally resulting in a steady signal level) a 0 is inserted after every
six consecutive 1's to ensure adequate signal transitions in the data stream. The USB
transmissions consist of packets using one of four types of formats (Figure 5-8) that include two
or more of seven field types.
■
Sync Field—8-bit field that starts every packet and is used by the receiver to align the
incoming signal with the local clock.
■
Packet Identifier (PID) Field—8-bit field sent with every packet to identify the attributes (in.
out, start-of-frame (SOF), setup, data, acknowledge, stall, preamble) and the degree of error
correction to be applied.
■
Address Field—7-bit field that provides source information required in token packets.
■
Endpoint Field—4-bit field that provides destination information required in token packets.
■
Frame Field—11-bit field sent in Start-of-Frame (SOF) packets that are incremented by the
host and sent only at the start of each frame.
■
Data Field—0-1023-byte field of data.
■
Cyclic Redundancy Check (CRC) Field—5- or 16-bit field used to check transmission
integrity.
Token Packet
Sync Field
(8 bits)
PID Field
(8 bits)
SOF Packet
Sync Field
(8 bits)
PID Field
(8 bits)
Data Packet
Sync Field
(8 bits)
PID Field
(8 bits)
Handshake Packet
Sync Field
(8 bits)
PID Field
(8 bits)
Addr. Field
(7 bits)
ENDP. Field
(4 bits)
Frame Field
(11 bits)
Data Field
(0-1023 bytes)
CRC Field
(5 bits)
CRC Field
(5 bits)
CRC Field
(16 bits)
Figure 5-8. USB Packet Formats
Data is transferred LSb first. A cyclic redundancy check (CRC) is applied to all packets (except a
handshake packet). A packet causing a CRC error is generally completely ignored by the
receiver.
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5-23
Input/Output Interfaces
5.7.2 USB Programming
Programming the USB interface consists of configuration, which typically occurs during POST,
and control, which occurs at runtime.
USB Configuration
Each USB controller functions as a PCI device within the 82801 component and is configured
using PCI Configuration Registers as listed in Table 5-18.
NOTE:
Table 5-18.
USB Interface Configuration Registers
PCI Config.
Address
Register
Reset PCI Config.
Value Address
Register
00, 01h
Vendor ID
8086h 0Eh
Header Type
00h
02, 03h
Device ID
I/O Space Base Address
1d
04, 05h
PCI Command
0000h 2C, 2Dh
Sub. Vender ID
00h
06, 07h
PCI Status
0280h 3Ch
Interrupt Line
00h
08h
Revision ID
00h
3Dh
Interrupt Pin
03h
09h
Programming I/F
00h
60h
Serial Bus Release No.
10h
0Ah
Sub Class Code
03h
C0, C1h
USB Leg. Kybd./Ms. Cntrl.
0Bh
Base Class Code
0Ch
C4h
USB Resume Enable
[1]
20-23h
Reset
Value
2000h
00h
Note:
[1] USB 1.1 #1= 24D2h
USB 1.1 #2 = 24D4h
USB 1.1 #3 = 24D7h
USB 1.1 #4 = 24DDh
USB 2.0
= 24DDh
5-24
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Technical Reference Guide
Input/Output Interfaces
USB Control
The USB is controlled through I/O registers as listed in table 5-19.
Table 5-19.
USB Control Registers
I/O Address
Register
Default Value
00, 01h
Command
0000h
02, 03h
Status
0000h
04, 05h
Interupt Enable
0000h
06, 07
Frame Number
0000h
08, 0B
Frame List Base Address
0000h
0Ch
Start of Frame Modify
40h
10, 11h
Port 1 Status/Control
0080h
12, 13h
Port 2 Status/Control
0080h
18h
Test Data
00h
5.7.3 USB Connector
These systems provide type-A USB ports as shown in Figure 5-9 below.
1
2
3
4
Figure 5-9. Universal Serial Bus Connector (as viewed from rear of chassis)
Table 5-20.
USB Connector Pinout
Pin
Signal
Description
Pin
Signal
Description
1
Vcc
+5 VDC
3
USB+
Data (plus)
2
USB-
Data (minus)
4
GND
Ground
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5-25
Input/Output Interfaces
5.7.4 USB Cable Data
The recommended cable length between the host and the USB device should be no longer than
sixteen feet for full-channel (12 MB/s) operation, depending on cable specification (see
following table).
Table 5-21.
USB Cable Length Data
Conductor Size
Resistance
Maximum Length
20 AWG
0.036 Ω
16.4 ft (5.00 m)
22 AWG
0.057 Ω
9.94 ft (3.03 m)
24 AWG
0.091 Ω
6.82 ft (2.08 m)
26 AWG
0.145 Ω
4.30 ft (1.31 m)
28 AWG
0.232 Ω
2.66 ft (0.81 m)
NOTE:
For sub-channel (1.5 MB/s) operation and/or when using sub-standard cable shorter lengths may
be allowable and/or necessary.
The shield, chassis ground, and power ground should be tied together at the host end but left
unconnected at the device end to avoid ground loops.
Color code
5-26
Signal
Insulation color
Data +
Green
Data -
White
Vcc
Red
Ground
Black
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Technical Reference Guide
Input/Output Interfaces
5.8
Audio Subsystem
These systems use the HD audio controller of the 82801 component to access and control a
Realtek ALC262 HD Audio Codec, which provides 2-channel high definition analog-to-digital
(ADC) and digital-to-analog (DAC) conversions. A block diagram of the audio subsystem is
shown in Figure 5-10. All control functions such as volume, audio source selection, and
sampling rate are controlled through software through the HD Audio Interface of the 82801 ICH
component. Control data and digital audio streams (record and playback) are transferred between
the ICH and the Audio Codec over the HD Audio Interface. The codec’s speaker output is
applied to a 1.5-watt amplifier that drives the internal speaker. A device plugged into the
Headphone jack or the line input jack is sensed by the system, which will inhibit the Speaker
Audio signal.
Theses systems provide the following analog interfaces for external audio devices:
Mic In—This input uses a three-conductor mini-jack that accepts a stereo microphone. This is
the default recording input after a system reset. On MT/CMT systems with both front and rear
microphone jacks, either jack is available for use (but not simultaneously).
Line In—This input uses a three-conductor (stereo) mini-jack that is specifically designed for
connection of a high-impedance audio source such as a tape deck.
Headphones Out—This input uses a three-conductor (stereo) mini-jack that is designed for
connecting a set of 32-ohm (nom.) stereo headphones. Plugging into the Headphones jack mutes
the signal to the internal speaker and the Line Out jack as well.
Line Out—This output uses a three-conductor (stereo) mini-jack for connecting left and right
channel line-level signals. Typical connections include a tape recorder's Line In (Record In)
jacks, an amplifier's Line In jacks, or to powered speakers that contain amplifiers.
PC Beep
82801 ICH
HD Audio
Interface
HD Audio I/F
Line Audio (L/R)
Speaker
Audio (mono)
Line In
Header
P23
Header
P6
Audio
Amp
Mic Audio (L/R)
Front Panel
Mic In
ALC262
HD Audio
Mic Audio (L/R)
Rear Panel
Mic In [1]
Header
P23
Codec
Headphones
Out
Line Audio
Out (L/R)
Header
P11 [2]
Aux Audio In
Headphone
Audio (L/R)
Line Out
Audio In (L/R)
NOTES:
L/R = Separate left and right channels (stereo). L+R = Combined left and right channels (mono).
[1] MT/CMT only
[2] SSF, ST, MT, and CMT only.
Figure 5-10. Audio Subsystem Functional Block Diagram
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5-27
Input/Output Interfaces
5.8.1 HD Audio Controller
The HD Audio Controller is a PCI Express device that is integrated into the 82801 ICH
component and supports the following functions:
■
Read/write access to audio codec registers
■
Support for greater than 48-KHz sampling
■
HD audio interface
5.8.2 HD Audio Interface
The HD audio controller and the HD audio codec communicate over a five-signal HD Audio
Interface (Figure 5-11). The HD Audio Interface includes two serial data lines; serial data out
(SDO, from the controller) and serial data in (SDI, from the audio codec) that transfer control
and PCM audio data serially to and from the audio codec using a time-division multiplexed
(TDM) protocol. The data lines are qualified by the 24-MHz BCLK signal driven by the audio
controller. Data is transferred in frames synchronized by the 48-KHz SYNC signal, which is
derived from the clock signal and driven by the audio controller. When asserted (typically during
a power cycle), the RESET- signal (not shown) will reset all audio registers to their default
values.
Frame
BCLK
Frame
Start
Tag A
Tag B
Frame
Start
SYNC
SDO
SDI
Command Stream
Stream A
Tag C
Response Stream
Stream B
Stream C
RST#
NOTE: Clock not drawn to scale.
Figure 5-11. HD Audio Interface Protocol
5-28
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Technical Reference Guide
Input/Output Interfaces
5.8.3 HD Audio Codec
The HD Audio Codec provides pulse code modulation (PCM) coding and decoding of audio
information as well as the selection and/or mixing of analog channels. As shown in Figure 5-12,
analog audio from an external microphone, tape, or internal CD can be selected and, if to be
recorded (saved) onto a disk drive, routed through an analog-to-digital converter (ADC). The
resulting left and right PCM record data are muxed into a time-division-multiplexed (TDM) data
stream (SD IN signal) that is routed to the audio controller. Playback (PB) audio takes the reverse
path from the audio controller to the audio codec as SD OUT data and is decoded and either
routed through an equalizer or applied directly to the digital-to-analog converter (DAC). The
codec supports simultaneous record and playback of stereo (left and right) audio. The sampling
rate used by the Sample Rate Controllers (SRC) may be set independently for the ADCs and the
DAC. The integrated analog mixer provides the computer control-console functionality handling
multiple audio inputs.
Audio
Format
Front Mic Audio In
Rear Mic Audio In [1]
Mux
CD Audio In
REC
Gain
ADC
w/SRC
L/R
Audio In
SDI
Line Audio In
RST#
PC Beep In
HD
Audio
Interface
Mux/Gain
Line Audio Out
HP Audio Out
BCLK
SYNC
PB
Gain
HD Audio
Link Bus
to/from
Audio
Controller
SDO
DAC
w/SRC
PB
Gain
L/R
Audio Out
NOTE:
The audio codec includes two ADCs. However, only one is
typcially used.
All audio lines represent both left and right channel information.
[1] CMT form factor only.
Figure 5-12. ALC262 HD Audio Codec Functional Block Diagram
All functions are controlled through index-addressed registers of the codec.
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5-29
Input/Output Interfaces
5.8.4 Audio Programming
Audio subsystem programming consists of configuration, typically accomplished during POST,
and control, which occurs during runtime.
Audio Configuration
The audio subsystem is configured according to PCI protocol through the HD audio controller
function of the 82801 ICH. Table 5-22 lists the PCI configuration registers of the audio
subsystem.
Table 5-22.
HD Audio Controller
PCI Configuration Registers (82801 Device 27/Function 0)
PCI Config.
Address
Register
PCI
Value on Config.
Reset
Address
Value on
Reset
Register
00-01h
Vendor ID
8086h
14-17h
HD Audio Upper
Base. Addr.
0
02-03h
Device ID
24D5h
2C-2Dh
Subsystem Vender ID
0000h
04-05h
PCI Command
0000h
2E-2Fh
Subsystem ID
0000h
06-07h
PCI Status
0280h
34h
Capability List Pointer
50h
08h
Revision ID
XXh
3Ch
Interrupt Line
00h
09h
Programming
00h
3Dh
Interrupt Pin
02h
0Ah
Sub-Class
01h
40h
HD Audio Control
0’s
0Bh
Base Class Code
04h
44h
Traffic Class Select
00h
0Eh
Header Type
00h
4C, 4Dh
Docking
Control/Status
10-13h
HD Audio Lower Base
Addr.
4
50-14Fh
-HD audio functions
0080h
[1]
NOTE:
Values without “h” suffix (denoting hexidecimal value) are decimal.
[1] Refer to Intel data sheet for more information.
5-30
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Technical Reference Guide
Input/Output Interfaces
Audio Control
The audio subsystem is controlled through a set of verb commands listed in Table 5-23.
Table 5-23.
HD Audio Codec Commands
Verb
Value
Verb
Value
Verb
Value
Get Parameter
F00h
Set Power State
705h
Get GPIO Enable Mask
F16h
Get Connection Select
F01h
Get Conv. Stream Ch.
F06h
Set GPIO Enable Mask
716h
Set Connection Select
701h
Set Conv. Stream Ch.
706h
Get GPIO Direction
F17h
Get Connection List
F02h
Get Pin Widget Cntrl.
F07h
Set GPIO Direction
717h
Get Processing State
F03h
Set Pin Widget Cntrl.
707h
Get GPIO Unsol. Resp.
En. Mask
F19h
Set Processing State
703h
Get Unsol. Resp. Cntrl.
F08h
Set GPIO Unsol. Resp. En.
Mask
719h
Get Coefficient Index
00Dh
Set Unsol. Resp. Cntrl.
708h
Function Reset
7FFh
Set Coefficient Index
005h
Get Pin Sense
F09h
Get Digital Converter
Control
F0Dh
Get Processing
Coefficient
00Ch
Execute Pin Sense
709h
Set Digital Conv. Cntrl. 1
70Dh
Set Processing
Coefficient
004h
Get Default Config.
F1Ch
Set Digital Conv. Cntrl. 2
70Eh
Get Amplifier Gain
00Bh
Set Default Config.
Set Amplifier Gain
003h
Get Beep Generator
F0Ah
Set EAPD Enable
70Ch
Get Converter Format
00Ah
Set Beep Generator
70Ah
Get Volume Knob Widget
FOFh
Set Converter Format
002h
Get GPIO Data
F15h
Set Volume Knob Widget
70Fh
Get Power State
F05h
Set GPIO Data
715h
--
71C-71F Get EAPD Enable
h
F0Ch
--
NOTE:
Refer to vendor data sheet for more information.
Get Converter Format
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5-31
Input/Output Interfaces
5.8.5 Audio Specifications
The specifications for the HD Audio subsystem are listed in Table 5-24.
Table 5-24.
HD Audio Subsystem Specifications
Parameter
Measurement
Sampling Rates:
DAC
ADC
44.1-, 48-, 96-, & 192-KHz [1]
44.1-, 48-, & 96-KHz [1]
Resolution:
DAC
ADC
24-bit
20-bit
Nominal Input Voltage:
Mic In (w/+20 db gain)
Line In
.283 Vp-p
2.83 Vp-p
Subsystem Impedance (nominal):
Mic In
Line In
Line Out
Headphones Out
64K ohms
64K ohms
200 ohms
32 0hms
Signal-to-Noise Ratio
ADC
DAC
90 db (nom)
100 db (nom)
Total Harmonic Distortion (THD)
ADC
DAC
-82
-87
Max. Subsystem Power Output to 4-ohm Internal
Speaker (with 10% THD):
Gain Step
1.5 watts
1.5 db
Master Volume Range
-94.5 db
Frequency Response:
ADC/DAC
Internal Speaker
16 – 19,200 Hz
450–4000 Hz
NOTE:
[1] Device driver limitation: 48 KHz
5-32
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Technical Reference Guide
Input/Output Interfaces
5.9
Network Interface Controller
These systems provide 10/100/1000 Mbps network support through an Intel 82566 network
interface controller (NIC), a PHY component, and a RJ-45 jack with integral status LEDs. The
82562-equivalent controller integrated into the 82801 ICH component is not used (disabled) in
these systems. (Figure 5-13). The support firmware for the BCM5752 component is contained in
the system (BIOS) ROM. The NIC can operate in half- or full-duplex modes, and provides
auto-negotiation of both mode and speed. Half-duplex operation features an Intel-proprietary
collision reduction mechanism while full-duplex operation follows the IEEE 802.3x flow control
specification.
Green LED
Intel
82566
NIC
Tx/Rx Data
LAN I/F
RJ-45
Connector
Tx/Rx Data
Yellow LED
LED
Green
Yellow
Function
Activity/Li nk. Indicates network activity and link pulse reception.
Speed. Indicates link detection 100Mb/s mode.
Figure 5-13. Network Interface Controller Block Diagram
The Network Interface Controller includes the following features:
■
VLAN tagging with Windows XP and Linux.
■
Multiple VLAN support with Windows XP.
■
Power management support for ACPI 1.1, PXE 2.0, WOL, ASF 1.0, IPMI
■
Cisco Etherchannel support
■
Link and Activity LED indicator drivers
The controller features high and low priority queues and provides priority-packet processing for
networks that can support that feature. The controller's micro-machine processes transmit and
receive frames independently and concurrently. Receive runt (under-sized) frames are not passed
on as faulty data but discarded by the controller, which also directly handles such errors as
collision detection or data under-run.
The NIC uses 3.3 VDC auxiliary power, which allows the controller to support Wake-On-LAN
(WOL) and Alert-On-LAN (AOL) functions while the main system is powered down.
the features in the following paragraphs to function as described, the system unit must be
✎ For
plugged into a live AC outlet. Controlling unit power through a switchable power strip will, with
the strip turned off, disable any wake, alert, or power mangement functionality.
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5-33
Input/Output Interfaces
5.9.1 Wake-On-LAN Support
The NIC supports the Wired-for-Management (WfM) standard of Wake-On-LAN (WOL) that
allows the system to be booted up from a powered-down or low-power condition upon the
detection of special packets received over a network. The NIC receives 3.3 VDC auxiliary power
while the system unit is powered down in order to process special packets. The detection of a
Magic Packet by the NIC results in the PME- signal on the PCI bus to be asserted, initiating
system wake-up from an ACPI S1 or S3 state.
5.9.2 Alert Standard Format Support
Alert Standard Format (ASF) support allows the NIC to communicate the occurrence of certain
events over a network to an ASF 1.0-compliant management console and, if necessary, take
action that may be required. The ASF communications can involve the following:
■
Alert messages sent by the client to the management console.
■
Maintenance requests sent by the management console to the client.
■
Description of client's ASF capabilities and characteristics.
The activation of ASF functionality requires minimal intervention of the user, typically requiring
only booting a client system that is connected to a network with an ASF-compliant management
console.
5.9.3 Power Management Support
The NIC features Wired-for-Management (WfM) support providing system wake up from
network events (WOL) as well as generating system status messages (AOL) and supports ACPI
power management environments. The controller receives 3.3 VDC (auxiliary) power as long as
the system is plugged into a live AC receptacle, allowing support of wake-up events occurring
over a network while the system is powered down or in a low-power state.
The Advanced Configuration and Power Interface (ACPI) functionality of system wake up is
implemented through an ACPI-compliant OS and is the default power management mode. The
following wakeup events may be individually enabled/disabled through the supplied software
driver:
■
Magic Packet—Packet with node address repeated 16 times in data portion
following functions are supported in NDIS5 drivers but implemented through remote
✎ The
management software applications (such as LanDesk).
■
Individual address match—Packet with matching user-defined byte mask
■
Multicast address match—Packet with matching user-defined sample frame
■
ARP (address resolution protocol) packet
■
Flexible packet filtering—Packets that match defined CRC signature
The PROSet Application software (pre-installed and accessed through the System Tray or
Windows Control Panel) allows configuration of operational parameters such as WOL and
duplex mode.
5-34
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Technical Reference Guide
Input/Output Interfaces
5.9.4 NIC Programming
Programming the NIC consists of configuration, which occurs during POST, and control, which
occurs at runtime. The Intel 82566 NIC is configured as a PCI device and controlled through
registers mapped in variable I/O space. The BIOS for theNIC is contained within the
HP/Compaq BIOS in system ROM. Refer to Intel documentation for details regarding 82566
register programming.
5.9.5 NIC Connector
Figure 5-14 shows the RJ-45 connector used for the NIC interface. This connector includes the
two status LEDs as part of the connector assembly.
Activity LED
Speed LED
Pin
1
2
3
6
Description
Transmit+
TransmitReceive+
Receive-
4, 7, 8 Not used
8 7 6 5 4 3 2 1
Figure 5 14. RJ-45 Ethernet TPE Connector (as viewed from rear of chassis)
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5-35
Input/Output Interfaces
5.9.6 NIC Specifications
Table 5-25.
NIC Specifications
Parameter
5-36
Modes Supported
10BASE-T half duplex @ 10 Mb/s
10Base-T full duplex @ 20 Mb/s
100BASE-TX half duplex @ 100 Mb/s
100Base-TX full duplex @ 200 Mb/s
1000BASE-T half duplex @ 1 Gb/s
1000BASE-TX full duplex @ 2 Gb/s
Standards Compliance
IEEE 802.1P, 802.1Q
IEEE 802.2
IEEE 802.3, 802.3ab, 802.3ad, 802.3u, 802.3x,
802.3z
OS Driver Support
MS-DOS
MS Windows 3.1
MS Windows 95 (pre-OSR2), 98, and 2000
Professional, XP Home, XP Pro
MS Windows NT 3.51 & 4.0
Novell Netware 3.x, 4.x, 5x
Novell Netware/IntraNetWare
SCO UnixWare 7
Linux 2.2, 2.4
PXE 2.0
Boot ROM Support
Intel PRO/100 Boot Agent (PXE 3.0, RPL)
F12 BIOS Support
Yes
Bus Inteface
PCI Express x1
Power Management Support
ACPI, PCI Power Management Spec.
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Technical Reference Guide
6
Integrated Graphics Subsystem
6.1
Introduction
This chapter describes graphics subsystem that is integrated into the Q965 GMCH component.
This graphics subsystem employs the use of system memory to provide efficient, economical 2D
and 3D performance.
These systems may be upgraded/modified one of two ways:
■
Installing a DVI ADD2 or graphics card into the PCI-E x16 slot and either enabling or
disabling the integrated controller
or
■
Installing a graphics card in a PCIe x1 slot, which will disable the integrated controller.
This chapter covers the following subjects:
■
Functional description (6.2), page 6-2
■
Display Modes (6.3), page 6-4
■
Upgrading graphics (6.4) , page 6-5
■
VGA Monitor connector (6.5), page 6-6
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6-1
Integrated Graphics Subsystem
6.2 Functional Description
The Intel Q965 GMCH component includes an Intel Integrated Graphics Media Accelerator
3000 controller (Figure 6-1). This integrated graphics controller (IGC) operates internally of the
PCIe x16 bus and can directly drive an external, analog multi-scan monitor at resolutions up to
and including 2048 x 1536 pixels. The IGC includes a memory management feature that
allocates portions of system memory for use as the frame buffer and for storing textures and 3D
effects.
The IGC provides two SDVO channels that are multiplexed through the PCI Express graphics
interface. These SDVO ports may be used by an Advanced Digital Display (ADD2) card
installed in the PCI-E x16 graphics slot in driving two digital displays with a 200-megapixel
clock.
Q965 GMCH
Monitor
PCI Express x16
Graphics slot [1]
RGB
PCI-E
& SDVO Data
Integrated
GMA 3000
Controller
SDRAM
Controller
DDR2
SDRAM
(System
Memory)
PCI Expr. I/F
NOTE:
[1] In USDT form factor, accepts reverse-layout SDVO ADD2 card only.
In SFF, ST, MT, and CMT form factors, accepts normal-layout cards.
Figure 6-1. Q965-Based Graphics, Block diagram
The IGC provides the following features:
6-2
■
2x performance over previous generation controllers.
■
Rapid pixel and texel rendering using four pipelines that allow 2D and 3D operations to
overlap, speeding up visual effects, reducing the amount of memory for texture storage.
■
Zone rendering for optimizing 3D drawing, eliminating the need for local graphics memory
by reducing the bandwidth.
■
Dynamic video memory allocation, where the amount of memory required by the application
is acquired (or released) by the controller.
■
Intelligent memory management allowing tiled memory addressing, deep display buffering,
and dynamic data management.
■
Provides two serial digital video out (SDVO) channels for use by an appropriate ADD2
accessory card.
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Technical Reference Guide
Integrated Graphics Subsystem
The IGC includes 2D and 3D accelerator engines working with a deeply-pipelined pre-processor.
Hardware cursor and overlay generators are also included as well as a legacy VGA processor
core. The controller supports three display devices:
■
One progressive-scan analog monitor
■
Up to two additional video displays with the installation of an optional Advanced Digital
Display (ADD2) card in the PCI Express x16 graphics slot.
✎ The controller can support LVDS, TMDS, or TV output with the proper encoder option.
Special features of the integrated graphics controller include:
■
400-MHz core engine
■
400-MHz 24-bit RAMDAC
■
2D engine supporting GDI+ and alpha stretch blithering up to 2048 x 1536 w/32-bit color @
75 Hz refresh (QVGA)
■
3D engine supporting Z-bias and up to 1600 x 1200 w/32-bit color @ 85 hz refresh
■
Video DVD support:
The IGC uses a portion of system memory for instructions, textures, and frame (display)
buffering. Using a process called Dynamic Video Memory Technology (DVMT), the controller
dynamically allocates display and texture memory amounts according to the needs of the
application running on the system.
The total memory allocation is determined by the amount of system memory installed in a
system. The video BIOS pre-allocates 8 megabytes of memory during POST. System memory
that is pre-allocated is not seen by the operating system, which will report the total amount of
memory installed less the amount of pre-allocated memory.
Example: A system with 128 MB of SDRAM with the video BIOS set to 8 MB will be reported
by MS Windows as having 120 MB.
The IGC will use, in standard VGA/SVGA modes, pre-allocated memory as a true dedicated
frame buffer. If the system boots with the OS loading the IGC Extreme Graphics drivers, the
pre-allocated memory will then be re-claimed by the drivers and may or may not be used by the
IGC in the “extended” graphic modes. However, it is important to note that pre-allocated
memory is available only to the IGC, not to the OS.
The Q965's DVMT function is an enhancement over the Unified Memory Architecture (UMA)
of earlier systems. The DVMT of the Q965 selects, during the boot process, the maximum
graphics memory allocation possible according on the amount of system memory installed:
SDRAM Installed
128 to 256 megabytes
257 to 511 megabytes
> 512megabytes
Maximum Memory Allocation
8-32 MB
8-64 MB
8-128 MB
The actual amount of system memory used by the IGC in the “extended” or “extreme” modes
will increase and decrease dynamically according to the needs of the application. The amount of
memory used solely for graphics (video) may be reported in a message on the screen, depending
on the operating system and/or applications running on the machine.
For viewing the maximum amount of available frame buffer memory MS Windows 2000 or XP,
go to Display Properties > Settings> Adapter.
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6-3
Integrated Graphics Subsystem
The Microsoft Direct diagnostic tool included in most versions of Windows may be used to
check the amount of video memory being used. The Display tab of the utility the “Approx. Total
Memory” label will indicate the amount of video memory. The value will vary according to OS
(In Windows XP, the video memory size reported by DirectX will always be 32 MB, even if the
total memory installed is over 128 MB).
applications, particularly games that require advanced 3D hardware acceleration, may not
✎ Some
install or run correectly on systems using the IGC.
6.3
Display Modes
The IGC supports the following standard display modes for 2D video displays:
Table 6-1.
IGC Standard 2D Display Modes
Resolution
640 x 480
800 x 600
1024 x 768
1280 x 1024
1600 x 1200
1920 x 1080
1920 x 1200
1920 x 1440
2048 x 1536
Maximum Refresh Rate
Analog
Digital
Monitor
Monitor
85 Hz
60 Hz
85 Hz
60 Hz
85 Hz
60 Hz
85 Hz
60 Hz
85 Hz
60 Hz
85 Hz
60 Hz
85 Hz
60 Hz
85 Hz
60 Hz
85 Hz
60 Hz
The highest resolution available will be determined by the following factors:
■
Memory speed and amount
■
Single or dual channel memory
■
Number and type of monitors
IGC is designed for optimum performance with multi-sync analog monitors.
✎ The
Digital displays may not provide an image as high in quality, depending on resolution.
6-4
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Technical Reference Guide
Integrated Graphics Subsystem
6.4 Upgrading Graphics
The PCI-E x16 slot of SFF, ST, MT, and CMT systems can accept a normal-layout Advanced
Digital Display 2 (ADD2) or a full-size PCIe x16 graphics controller card. The USDT system
with a PCIe x16 riser card installed can accept a reverse-layout Advanced Digital Display 2
(ADD2) or a low-profile PCIe x16 graphics card. Depending on accessory, upgrading through
the PCI Express x16 slot can provide digital monitor support and/or dual-monitor support
allowing display-cloning or extended desktop functionality. Software drivers may need to be
downloaded for specific cards.
SDVO channels are provided by the IGC for supporting two digital displays. Existing option
✎ Two
cards and drivers support one CRT and digital display. Dual digital display support may be
possible with future cards and drivers.
The upgrade procedure is as follows:
1. Shut down the system through the operating system.
2. Unplug the power cord from the rear of the system unit.
3. Remove the chassis cover.
4. Install the graphics or ADD2 card into the PCI Express x16 graphics slot.
5. Replace the chassis cover.
6. Reconnect the power cord to the system unit.
7. Power up the system unit and enter the ROM-based Setup utility using the F10 key.
8. Select whether to enabled or disable the IGC.
9. Reboot the system.
a PCIe x1 graphics controller card is installed, the IGC cannot be enabled. The BIOS will
✎ Ifdetect
the presence of the PCI card and disable the IGC of the Q965 GMCH.
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6-5
Integrated Graphics Subsystem
6.5 VGA Monitor Connector
These systems includes a standard VGA connector (Figure 6-3) for attaching an analog monitor:
9
Figure 6 3. DB-15 VGA Monitor Connector, (as viewed from rear of chassis).
Table 6-1.
DB-15 Monitor Connector Pinout
Pin
1
2
3
4
5
6
7
8
Signal
R
G
B
NC
GND
R GND
G GND
B GND
Description
Red Analog
Blue Analog
Green Analog
Not Connected
Ground
Red Analog Ground
Blue Analog Ground
Green Analog Ground
Pin
9
10
11
12
13
14
15
--
Signal
PWR
GND
NC
SDA
HSync
VSync
SCL
--
Description
+5 VDC (fused) [1]
Ground
Not Connected
DDC2-B Data
Horizontal Sync
Vertical Sync
DDC2-B Clock
--
NOTES:
[1] Fuse automatically resets when excessive load is removed.
6-6
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Technical Reference Guide
7
Power and Signal Distribution
7.1
Introduction
This chapter describes the power supply and method of general power and signal distribution.
Topics covered in this chapter include:
7.2
■
Power supply assembly/control (7.2) page 7-1
■
Power distribution (7.3) page 7-8
■
Signal distribution (7.4) page 7-12
Power Supply Assembly/Control
These systems feature a power supply assembly that is controlled through programmable logic
(Figure 7-1).
System Board
Front Bezel
Power Button
CPU, slots, Chipsets, Logic,
& Voltage Regulators
Power On
+3.3 VDC 5 AUX
PS On
90 - 264 VAC
+5 VDC +12 VDC +12 VccP
Fan
Spd [1]
-12 VDC
+3.3 VDC
+5 VDC
+12 VDC
Drives
Power Supply
Assembly
NOTE:
[1] Not present on CMT.
Figure 7-1. Power Distribution and Control, Block Diagram
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7-1
Power and Signal Distribution
7.2.1 Power Supply Assembly
These systems feature power supplies with power factor-correction logic. Four power supplies
are used: a 200-watt power supply for the USDT unit, a 240-watt power supply for the SFF and
ST units, a 300-watt power supply for the MT unit, and a 365-watt power supply for the CMT
unit. All power supplies feature active power factor correction (PFC). Tables 7-1 through 7-4 list
the specifications of the power supplies. Note that output load voltages are measured at the
load-side of the output connectors.
Table 7-1.
200-Watt (USDT) Power Supply Assembly Specifications
Range or
Tolerance
Input Line Voltage:
100–240 VAC (auto-ranging) 90–264 VAC
Line Frequency
47–63 Hz
Input (AC) Current
-+3.33 VDC Output
+4%
+5.08 VDC Output
+ 3.3 %
+5.08 AUX Output
+ 3.3 %
+12 VDC Output [3]
+5%
-12 VDC Output
+ 10 %
Min.
Current
Loading [1]
Max.
Current
Surge
Current [2]
Max.
Ripple
---0.1 A
0.3 A
0.0 A
0.1 A
0.0 A
--4.0 A
12.0 A
10.0 A
2.6 A
15.5 A
0.15 A
---12.0 A
10.0 A
3.1 A
17.0 A
0.15 A
---50 mV
50 mV
50 mV
120 mV
200 mV
NOTES:
Total continuous power should not exceed 200 watts. Total surge power (<10 seconds w/duty cycle < 5 %) should not exceed
230 watts.
[1] Minimum loading requirements must be met at all times to ensure normal operation and specification compliance.
[2] Surge duration no longer than 10 seconds with 12-volt tolerance at +/- 10%.
[3] +12 VDC output can be split by the system board to +12 VDC (@ 3 A) and +12 Vcpu (@ 12.5 A) power planes.
Table 7-2.
240-Watt (SFF/ST) Power Supply Assembly Specifications
Input Line Voltage:
100–240 VAC (auto-ranging)
Line Frequency
Input (AC) Current
+3.3 VDC Output
+5.08 VDC Output
+5.08 AUX Output
+12 VDC Output
+12 VDC Output (Vcpu)
--12 VDC Output
Range/
Tolerance
Min.
Current
Loading [1]
Max.
Current
Surge
Current [2]
Max.
Ripple
90–264 VAC
47–63 Hz
-+ 4%
+ 3.3 %
+ 3.3 %
+5%
+5%
+ 10 %
---0.1 A
0.3 A
0.0 A
0.1 A
0.1 A
0.0 A
--5.0 A
15.0 A
17.0 A
3.0 A
7.5 A
11.0 A
0.15 A
---15.0 A
170 A
3.5 A
9.0 A
14.5 A
0.15 A
---50 mV
50 mV
50 mV
120 mV
120 mv
200 mV
NOTES:
Total continuous power should not exceed 240 watts. Total surge power (<10 seconds w/duty cycle < 5 %) should not exceed
260 watts.
[1] The minimum current loading figures apply to a PS On start up only.
7-2
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Technical Reference Guide
Power and Signal Distribution
Table 7-3 lists the specifications for the 365-watt power supply used in the MT and CMT form
factors
Table 7-3.
365-Watt (M/T & CMT) Power Supply Assembly Specifications
Input Line Voltage:
115–230 VAC (auto-ranging)
Line Frequency
Input (AC) Current
+3.3 VDC Output
+5.08 VDC Output
+5.08 AUX Output
+12 VDC Output
+12 VDC Output (Vcpu)
-12 VDC Output
Range or
Tolerance
Min.
Current
Loading [1]
Max.
Current
Surge
Current [2]
Max.
Ripple
90–264 VAC
47–63 Hz
-+4%
+ 3.3 %
+ 3.3 %
+5%
+5%
+ 10 %
---0.10 A
0.30 A
0.00 A
0.20 A
0.00 A
0.00 A
--6.0 A
24.0 A
19.0 A
3.00 A
12.0 A
14.5 A
0.15 A
---24.0 A
19.0 A
3.00 A
14.5 A
17.5 A
0.15 A
---50 mV
50 mV
50 mV
120 mV
200 mv
200 mV
NOTES:
Total continuous output power should not exceed 365 watts. Maximum surge power should not exceed 385 watts.. Maximum
combined power of +5 and +3.3 VDC is 160 watts.
[1] Minimum loading requirements must be met at all times to ensure normal operation and specification compliance.
[2] Maximum surge duration for +12Vcpu is 1 second with 12-volt tolerance +/- 10%.
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7-3
Power and Signal Distribution
7.2.2 Power Control
The power supply assembly is controlled digitally by the PS On signal (Figure 7-1). When PS On
is asserted, the Power Supply Assembly is activated and all voltage outputs are produced. When
PS On is de-asserted, the Power Supply Assembly is off and no voltages (except +5 AUX) are
generated. Note that the +5 AUX voltages are always produced as long as the system is
connected to a live AC source.
Power Button
The PS On signal is typically controlled through the Power Button which, when pressed and
released, applies a negative (grounding) pulse to the power control logic. The resultant action of
pressing the power button depends on the state and mode of the system at that time and is
described as follows:
System State
Off
On, ACPI Disabled
On, ACPI Enabled
7-4
Pressed Power Button Results In:
Negative pulse, of which the falling edge results in power control logic
asserting PS On signal to Power Supply Assembly, which then initializes. ACPI
four-second counter is not active.
Negative pulse, of which the falling edge causes power control logic to
de-assert the PS On signal. ACPI four-second counter is not active.
Pressed and Released Under Four Seconds:
Negative pulse, of which the falling edge causes power control logic to
generate SMI-, set a bit in the SMI source register, set a bit for button status,
and start four-second counter. Software should clear the button status bit within
four seconds and the Suspend state is entered. If the status bit is not cleared by
software in four seconds PS On is de-asserted and the power supply assembly
shuts down (this operation is meant as a guard if the OS is hung).
Pressed and Held At least Four Seconds Before Release:
If the button is held in for at least four seconds and then released, PS On is
negated, de-activating the power supply.
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Power and Signal Distribution
Power LED Indications
A dual-color LED located on the front panel (bezel) is used to indicate system power status. The
front panel (bezel) power LED provides a visual indication of key system conditions listed as
follows:
Power LED
Condition
Steady green
Blinks green @ 0.5 Hz
Blinks red 2 times @ 1 Hz [1]
Normal full-on operation
Suspend state (S1) or suspend to RAM (S3)
Processor thermal shut down. Check air flow, fan
operation, and CPU heat sink.
Processor not installed. Install or reseat CPU.
Power failure (power supply is overloaded). Check storage
devices, expansion cards and/or system board (CPU
power connector P3).
Pre-video memory error. Incompatible or incorrectly seated
DIMM.
Pre-video graphics error. On system with integrated
graphics, check/replace system board. On system with
graphics card, check/replace graphics card.
PCA failure. Check/replace system board.
Invalid ROM (checksum error). Reflash ROM using CD or
replace system board.
System powers on but fails to boot. Check power supply,
CPU, system board.
Bad option card.
System dead. Press and hold power button for less than 4
seconds. If HD LED turns green then check voltage select
switch setting or expansion cards. If no LED light then check
power button/power supply cables to system board or
system board.
Blinks red 3 times @ 1 Hz [1]
Blinks red 4 times @ 1 Hz [1]
Blinks red 5 times @ 1 Hz [1]
Blinks red 6 times @ 1 Hz [1]
Blinks red 7 times @ 1 Hz [1]
Blinks red 8 times @ 1 Hz [1]
Blinks red 9 times @ 1 Hz [1]
Blinks red 10 times @ 1 Hz [1]
No light
NOTE:
[1] Will be accompanied by the same number of beeps, with 2-second pause between cycles. Beeps
stop after 5 cycles.
Wake Up Events
The PS On signal can be activated with a power “wake-up” of the system due to the occurrence
of a magic packet, serial port ring, or PCI power management event (PME). These events can be
individually enabled through the Setup utility to wake up the system from a sleep (low power)
state.
Wake-up functionality requires that certain circuits receive auxiliary power while the system is
✎ turned
off. The system unit must be plugged into a live AC outlet for wake up events to function.
Using an AC power strip to control system unit power will disable wake-up event functionality.
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7-5
Power and Signal Distribution
The wake up sequence for each event occurs as follows:
Wake-On-LAN
The network interface controller (NIC) can be configured for detection of a “Magic Packet” and
wake the system up from sleep mode through the assertion of the PME- signal on the PCI bus.
Refer to Chapter 5, “Network Support” for more information.
Modem Ring
A ring condition on a serial port can be detected by the power control logic and, if so configured,
cause the PS On signal to be asserted.
Power Management Event
A power management event that asserts the PME- signal on the PCI bus can be enabled to cause
the power control logic to generate the PS On. Note that the PCI card must be PCI ver. 2.2 (or
later) compliant to support this function.
7-6
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Technical Reference Guide
Power and Signal Distribution
7.2.3 Power Management
These systems include power management functions designed to conserve energy. These
functions are provided by a combination of hardware, firmware (BIOS) and software. The
system provides the following power management features:
■
ACPI v2.0 compliant (ACPI modes C1, S1, and S3-S5, )
■
APM 1.2 compliant
■
U.S. EPA Energy Star compliant
Table 7-5 shows the comparison in power states.
Table 7-5.
System Power States
Power
State
System Condition
G0, S0, D0
System fully on. OS and
application is running, all
components.
G1, S1, C1, D1 System on, CPU is executing and
data is held in memory. Some
peripheral subsystems may be on
low power. Monitor is blanked.
G1, S2/3, C2, System on, CPU not executing,
D2 (Standby/or cache data lost. Memory is
suspend)
holding data, display and I/O
subsystems on low power.
G1, S4, D3
System off. CPU, memory, and
(Hibernation)
most subsystems shut down.
Memory image saved to disk for
recall on power up.
G2, S5, D3cold System off. All components either
completely shut down or receiving
minimum power to perform system
wake-up.
G3
System off (mechanical). No power
to any internal components except
RTC circuit. [1]
Power
Consumption
Maximum
Transition
To S0 by [2]
N/A
OS Restart
Required
No
Low
< 2 sec after
keyboard or
pointing device
action
< 5 sec. after
keyboard, pointing
device, or power
button action
<25 sec. after
power button
action
No
Low
Low
No
Yes
Minimum
<35 sec. after
power button
action
Yes
None
—
—
NOTES:
Gn = Global state.
Sn = Sleep state.
Cn = ACPI state.
Dn = PCI state.
[1] Power cord is disconnected for this condition.
[2] Actual transition time dependent on OS and/or application software.
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7-7
Power and Signal Distribution
7.3
Power Distribution
The power supply assembly includes a multi-connector cable assembly that routes +3.3 VDC, +5
VDC, +5 VDC STB, +12 VC, and -12 VDC to the system board as well as to the individual drive
assemblies. Figure 7-2 shows the power supply cabling for the Ultra Slim Desktop form factor.
P2
P3
5 4321
4
P2
P3
1
Power Supply
403777
3
P1
P1
13
24
12
1
Conn
6
Pin 8
Pin 9
Pin
11
Pin
12
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
+5
aux
RTN
+5
+5
PS On
RTN
Pwr Gd
+3.3
+3.3
Tach
RTN
Fan
P1 [1]
+12
+5 sns
RTN
+5
+5
+3.3
RTN
+3.3 sns
+3.3
+3.3
RTN
-12
P2
+3.3
RTN
+5
RTN
+12
P3
RTN
RTN
RTN
VccP
VccP
P1
Pin 7
Pin
10
Pin 1
+12
NOTES:
Connectors not shown to scale.
All + and – values are VDC.
RTN = Return (signal ground)
sns = sense
GND = Power ground
RS = Remote sense
FO = Fan off
FSpd = Fan speed
FS = Fan Sink
FC = Fan Command
Vccp = +12 VDC for CPU
[1] This row represents pins 13 – 24 of connector P1.
Figure 7-2. USDT Power Cable Diagram
7-8
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Technical Reference Guide
Power and Signal Distribution
Figure 7-3 shows the power supply cabling for the SFF/ST systems.
P4
P5
P7
P2
P4, P5, P7
5 4321
P3
4
P3
P2
1
Power Supply
403778
3
4 3 2 1
P1
P1
13
24
12
1
Conn
6
Pin 4
Pin 5
Pin 6
P1
+5
aux
RTN
+5
+5
PS On
RTN
Pwr Gd
+3.3
+3.3
Tach
RTN
Fan
P1 [1]
+12
+5 sns
RTN
+5
+5
+3.3
RTN
+3.3 sns
+3.3
+3.3
RTN
-12
P2
+5
RTN
RTN
+12
+12
RTN
RTN
RTN
VccP
VccP
+3.3
RTN
+5
RTN
+12
Pin 9
Pin
12
Pin 3
P4, 5,
7
Pin 8
Pin
11
Pin 2
P3
Pin 7
Pin
10
Pin 1
Connectors not shown to scale.
All + and - values are VDC.
RTN = Return (signal ground)
sns = sense
GND = Power ground
RS = Remote sense
FC = Fan command
FO = Fan off
FSpd = Fan speed
FS = Fan Sink
POK = Power OK (power good)
VccP = +12 for CPU
[1] This row represents pins 13–24 of connector P1
Figure 7-3. SFF/ST Power Cable Diagram
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7-9
Power and Signal Distribution
Figure 7-4 shows the power supply cabling for the microtower and convertible minitower
systems.
P9
P10 P11
P4, P5, P9, P10, P11
P6
P8
5 4321
P8
P4
P5
P3
2 4
4 3 2 1
P3
P6
1
Power Supply
416224
3
1 2 3 4
P1
P1
13
24
12
1
Conn
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
P1
+3.3
+3.3
RTN
+5
RTN
+5
P1 [1]
+3.3
-12
RTN
PS On
RTN
RTN
P3
RTN
RTN
VccP
VccP
P4, 5, 9,
10, 11
+3.3
RTN
+5.08
RTN
P6
+12
RTN
RTN
+5
P8
+5
RTN
RTN
+12
Pin 7
Pin
10
Pin
11
Pin
12
Pin 8
Pin 9
RTN
POK
5 aux
+12
+12
+3.3
RTN
Open
+5
+5
+5
RTN
+12
NOTES:
Connectors not shown to scale.
All + and - values are VDC.
RTN = Return (signal ground)
GND = Power ground
RS = Remote sense
POK = Power ok (power good)
FC = Fan Command
[1] This row represents pins 13–24 of connector P1.
Figure 7-4. MT/CMT Power Cable Diagram
7-10
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Technical Reference Guide
Power and Signal Distribution
7.4
Signal Distribution
Figures 7-5 through 7-7 show general signal distribution between the main subassemblies of the
system units.
Chassis Fan
Speaker
Power On
Power LED
P8
HD LED
P6
P5
P3
+12 VccP
+3.3, +5, +5 Aux, +12 VDC
P1
System
Board
404233
P60
P21
PS On, POK
SATA I/F
IDE I/F.,
Diskette I/F.,
CD Audio
Power
Supply
Assembly
SATA
Hard Drive
SATAPATA
Interface
Slimline Optical Drive
Keyboard
J66
J67
P23
P24
Kybd data
Mouse data
Mouse
Mic In, HP Out
Audio
USB 8,9 Tx/Rx
Front
Panel
I/O Module
NOTES:
See Figure 7-10 for header pinout.
Figure 7-5. USDT Form Factor Signal Distribution Diagram
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7-11
Power and Signal Distribution
Chassis Fan
Speaker
Power On
Power LED
P8
HD LED
P6
P5
P3
+12 VccP
+3.3, +5, +5 Aux, +12 VDC
P1
P10
System
Board
404227-001
P60
PS On, POK
Diskette I/F
SATA I/F
SATA I/F
P61
Power
Supply
Assembly
Diskette
SATA
Hard Drive
CD-ROM
Keyboard
J66
J67
P23
P24
Kybd data
Mouse data
Mouse
Mic In, HP Out
Audio
USB 8,9 Tx/Rx
Front
Panel
I/O Module
NOTES:
See Figure 7-8 for header pinout.
Figure 7-6. SFF / ST Form Factor Signal Distribution Diagram
7-12
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Technical Reference Guide
Power and Signal Distribution
Chassis Fan
Speaker
Power On
Power LED
P8
HD LED
P6
P5
P3
+12 VccP
+3.3, +5, +5 Aux, +12 VDC
P1
P10
P60
System
Board
MT: 404276-001
CMT: 404224-001
PS On, POK
Diskette I/F
SATA I/F
Power
Supply
Assembly
Diskette
SATA
Hard Drive
CD-ROM
P61
SATA I/F.
Keyboard
Kybd data
J68
P23
P24
Mouse data
Mouse
Mic In, HP Out
Audio
USB 8,9 Tx/Rx
Front
Panel
I/O Module
J30
PCI 2.3 I/F
PCI Expansion
Daughter Board [1]
NOTE:
[1] CMT form factor only.
[2] See Figure 7-8 for header pinouts.
Figure 7-7. MT / CMT Form Factor Signal Distribution Diagram
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7-13
Power and Signal Distribution
Power Button/LED, HD LED
Header P5 (USDT, SFF, ST)
HD LED + 1
HD LED - 3
GND5
Pwr Btn 7
Chassis ID0 9
GND 11
Therm Diode A 13
Power Button/LED, HD LED
Header P5 (MT, CMT)
HD LED Cathode 1
HD LED Anode 3
2 PS LED +
4 PS LED -
GND5
M Reset 7
8 GND
10 Chassis ID1
12 NC
+5 VDC 9
2 PS LED Cathode
4 PS LED Anode
6 Pwr Btn
8 GND
10 NC
NC 11
GND 13
Chassis ID2 15
12 GND
Chassis ID0 17
18 Chassis ID1
14 Therm Diode C
16 +5 VDC
Front Panel Audio
Header P23
Mic In Left (Tip) 1
Mic In Right (Sleeve) 3
HP Out Right 5
2 Analog GND
4 Front Audio Detect#
6 Sense_1 Return
Sense Send 7
HP Out Left 9
Serial Port A
Header P54
Serial Port B
Header P52
UART1 DCD- 1
UART1 RX DATA 3
2 UART1 DSR4 UART1 RTS-
UART1 TX DATA 5
UART1 DTR 7
6 UART1 CTS8 UART1 RI10 Comm A Detect-
GND 9
10 Sense_2 Return
UART2 DTR- 1
UART2 CTS- 3
UART2 TX DATA 5
GND 7
+5.0V 9
UART2 RTS- 11
UART2 DCD- 13
+12V 15
GND 5
6 UART2 RI8 GND
10 +3.3V aux
12 Comm B Detect
14 -12V
Hood Sense
Header P125
Hood Lock
Header P124
Hood Lock 1
2 UART2 RX DATA
4 UART2 DSR-
2 Coil Conn
1 Hood SW Detect
4 +12V
6 Hood Unlock
2 GND
3 Hood Sensor
NOTE:
No polarity consideration required for connection to speaker header P6.
NC = Not connected
Figure 7-8. System Board Header Pinouts
7-14
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Technical Reference Guide
8
BIOS ROM
8.1
Introduction
The Basic Input/Output System (BIOS) of the computer is a collection of machine language
programs stored as firmware in read-only memory (ROM). The BIOS ROM includes such
functions as Power-On Self Test (POST), PCI device initialization, Plug 'n Play support, power
management activities, and the Setup utility. The firmware contained in the BIOS ROM supports
the following operating systems and specifications:
■
DOS 6.2
■
Windows 3.1, 95, 98SE, 2000, XP Professional, and XP Home
■
Windows NT 4.0 (SP6 required for PnP support)
■
OS/2 ver 2.1 and OS/2 Warp
■
SCO Unix
■
DMI 2.1
■
Intel Wired for Management (WfM) ver. 2.2
■
Alert Standard Format (ASF) 2.0
■
ACPI and OnNow
■
SMBIOS 2.4
■
Intel PXE boot ROM for the integrated LAN controller
■
BIOS Boot Specification 1.01
■
Enhanced Disk Drive Specification 3.0
■
“El Torito” Bootable CD-ROM Format Specification 1.0
■
ATAPI Removeable Media Device BIOS Specification 1.0
The BIOS firmware is contained in a 1024 x 8 (8 Mb) flash ROM part. The runtime portion of
the BIOS resides in a 128KB block from E0000h to FFFFFh.
This chapter includes the following topics:
■
ROM flashing (8.2), page 8-2
■
Boot functions (8.3), page 8-3
■
Setup utility (8.4), page 8-6
■
Client management functions (8.5), page 8-16
■
SMBIOS support (8.6), page 8-18
■
USB legacy support (8.7), page 8-18
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8-1
BIOS ROM
8.2 ROM Flashing
The system BIOS firmware is contained in a flash ROM device that can be re-written with new
BIOS code using a flash utility locally (with F10 setup), with the HPQFlash program in a
Windows environment, or with the FLASHBIN.EXE utility in a DOS or DOS-like environment.
8.2.1 Upgrading
Upgrading the BIOS is not normally required but may be necessary if changes are made to the
unit's operating system, hard drive, or processor. All BIOS ROM upgrades are available directly
from HP. Flashing is done either locally thrugh F10 setup, the HPQFlash program in a Windows
environment, or with the FLASHBIN.EXE utility in a DOS or DOS-like environment. Flashing
may also be done by deploying either HPQFlash or FLASHBIN.EXE through the network boot
function.
This system includes 64 KB of write-protected boot block ROM that provides a way to recover
from a failed flashing of the system BIOS ROM. If the BIOS ROM fails the flash check, the boot
block code provides the minimum amount of support necessary to allow booting the system from
the diskette drive and re-flashing the system ROM with a CD, USB, or diskette.
8-2
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8.2.2 Changeable Splash Screen
corrupted splash screen may be restored by reflashing the BIOS image through F10 setup,
✎ Arunning
HPQFlash, or running FLASHBIN.EXE. Depending on the system, changing
(customizing) the splash screen may only be available with asistance from HP.
The splash screen (image displayed during POST) is stored in the BIOS ROM and may be
replaced with another image of choice by using the Image Flash utility (Flashi.exe). The Image
Flash utility allows the user to browse directories for image searching and pre-viewing.
Background and foreground colors can be chosen from the selected image's palette.
The splash screen image requirements are as follows:
■
Format = Windows bitmap with 4-bit RLE encoding
■
Size = 424 (width) x 320 (height) pixels
■
Colors = 16 (4 bits per pixel)
■
File Size = < 64 KB
The Image Flash utility can be invoked at a command line for quickly flashing a known image as
follows:
>\Flashi.exe [Image_Filename] [Background_Color] [Foreground_Color]
The utility checks to insure that the specified image meets the splash screen requirements listed
above or it will not be loaded into the ROM.
8.3 Boot Functions
The BIOS supports various functions related to the boot process, including those that occur
during the Power On Self-Test (POST) routine.
8.3.1 Boot Device Order
The default boot device order is as follows:
1. CD-ROM drive (EL Torito CD images)
2. Diskette drive (A:)
3. USB device
4. Hard drive (C:)
5. Network interface controller (NIC)
✎
The above order assumes all devices are present in the initial configuration. If, for example, a diskette drive is
not initially installed but added later, then drive A would be added to the end of the order (after the NIC)
The order can be changed in the ROM-based Setup utility (accessed by pressing F10 when so
prompted during POST). The options are displayed only if the device is attached, except for USB
devices. The USB option is displayed even if no USB storage devices are present. The hot IPL
option is available through the F9 utility, which allows the user to select a hot IPL boot device.
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8-3
BIOS ROM
8.3.2 Network Boot (F12) Support
The BIOS supports booting the system to a network server. The function is accessed by pressing
the F12 key when prompted at the lower right hand corner of the display during POST. Booting
to a network server allows for such functions as:
■
Flashing a ROM on a system without a functional operating system (OS).
■
Installing an OS.
■
Installing an application.
These systems include, as standard, an integrated Intel 82562-equivalent NIC with Preboot
Execution Environment (PXE) ROM and can boot with a NetPC-compliant server.
8.3.3 Memory Detection and Configuration
This system uses the Serial Presence Detect (SPD) method of determining the installed DIMM
configuration. The BIOS communicates with an EEPROM on each DIMM through the SMBus
to obtain data on the following DIMM parameters:
■
Presence
■
Size
■
Type
■
Timing/CAS latency
■
PC133 capability
to Chapter 3, “Processor/Memory Subsystem” for the SPD format and DIMM data specific
✎ Refer
to this system.
The BIOS performs memory detection and configuration with the following steps:
1. Program the buffer strength control registers based on SPD data and the DIMM slots that are
populated.
2. Determine the common CAS latency that can be supported by the DIMMs.
3. Determine the memory size for each DIMM and program the GMCH accordingly.
4. Enable refresh
8-4
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8.3.4 Boot Error Codes
The BIOS provides visual and audible indications of a failed system boot by using the system’s
power LED and the system board speaker. The error conditions are listed in the following table.
Table 8-1
Boot Error Codes
Visual (power LED)
Audible (speaker) Meaning
Blinks red 2 times @ 1 Hz
None
Processor thermal shut down. Check air flow,
fan operation, and CPU heat sink.
Blinks red 3 times @ 1 Hz
None
Processor not installed. Install or reseat CPU.
Blinks red 4 times @ 1 Hz
None
Power failure (power supply is overloaded).
Check stroage devices, expansion cards
and/or system board (CPU power connector
P3).
Blinks red 5 times @ 1 Hz
5 beeps
Pre-video memory error. Incompatible or
incorrectly seated DIMM.
Blinks red 6 times @ 1 Hz
6 beeps
Pre-video graphics error. On system with
integrated graphics, check/replace system
board. On system with graphics card,
check/replace graphics card.
Blinks red 7 times @ 1 Hz
7 beeps
PCA failure. Check/replace system board.
Blinks red 8 times @ 1 Hz
8 beeps
Invalid ROM (checksum error). Reflash ROM
using CD or replace system board.
Blinks red 9 times @ 1 Hz
9 beeps
System powers on but fails to boot. Check
power supply, CPU, system board.
Blinks red 10 times @ 1 Hz
None
Bad option card.
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8-5
BIOS ROM
8.4 Setup Utility
The Setup utility (stored in ROM) allows the user to configure system functions involving
security, power management, and system resources. The Setup utility is ROM-based and invoked
when the F10 key is pressed and held during the computer boot cycle. Highlights of the Setup
utility are described in the following table.
pressing and releasing the computer’s power button, press and hold the F10 key until the
✎ After
Setup Utility screen is displayed.
Table 8-2
Setup Utility
Heading
File
Option
System Information
Description
Lists:
• Product name
• Processor type/speed/stepping
• Cache size (L1/L2)
• Installed memory size/speed, number of channels (single or
dual) (if applicable)
• Integrated MAC address for embedded, enabled NIC (if
applicable)
• System ROM (includes family name and version)
• Chassis serial number
• Asset tracking number
About
Displays copyright information.
Set Time and Date
Allows you to set system time and date.
Flash System ROM
Allows user to update the BIOS image from Setup. The binary file
can be obtained from a USB, diskette, or CD removable media.
Replicated Setup
Save to Removable Media
Saves system configuration, including CMOS, to a formatted
1.44-MB diskette, a USB flash media device, or a diskette-like
device (a storage device set to emulate a diskette drive).
Restore from Removable Media
Restores system configuration from a diskette, a USB flash media
device, or a diskette-like device.
Default Setup
Save Current Settings as Default
Saves the current system configuration settings as the default.
Restore Factory Settings as Default
Restores the factory system configuration settings as the default.
Apply Defaults
and Exit
✎
8-6
Applies the currently selected default settings and clears any
established passwords.
Support for specific Computer Setup options may vary depending on the hardware configuration.
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BIOS ROM
Table 8-2
Setup Utility
Heading
File
(continued)
Storage
Option
Description
Ignore Changes
and Exit
Exits Computer Setup without applying or saving any changes.
Save Changes and
Exit
Saves changes to system configuration or default settings and exits
Computer Setup.
Device
Configuration
Lists all installed BIOS-controlled storage devices.
When a device is selected, detailed information and options are
displayed. The following options may be presented.
Diskette Type
Identifies the highest capacity media type accepted by the diskette
drive.
Legacy Diskette Drives
Options are 3.5" 1.44 MB and
5.25" 1.2 MB.
Drive Emulation
Allows you to select a drive emulation type for a certain storage
device. (For example, a Zip drive can be made bootable by
selecting diskette emulation.)
Drive Type
Emulation Options
ATAPI Zip drive
None (treated as Other)
Diskette (treated as diskette drive)
ATA Hard disk
None (treated as Other)
Disk (treated as hard drive)
Legacy diskette
No emulation options available
CD-ROM drive
No emulation options available
ATAPI LS-120
None (treated as Other).
Diskette (treated as diskette drive).
Default Values IDE/SATA
Multisector Transfers (ATA disks only)
Specifies how many sectors are transferred per multi-sector PIO
operation. Options (subject to device capabilities) are Disabled, 8,
and 16.
CAUTION: Ordinarily, the translation mode selected
ï
automatically by the BIOS should not be changed. If the selected
translation mode is not compatible with the translation mode that
was active when the disk was partitioned and formatted, the data
on the disk will be inaccessible.
✎
Support for specific Computer Setup options may vary depending on the hardware configuration.
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8-7
BIOS ROM
Table 8-2
Setup Utility
Heading
Option
Description
Transfer Mode
Storage
(continued)
Specifies mode used for data transfer.. Options (subject to device
capabilities) are Max UDMA (default), PIO 0, Max PIO, Enhanced
DMA, and Ultra DMA 0.
Translation Parameters (ATA disks only)
This feature appears only when User translation mode is selected.
✎
Allows you to specify the parameters (logical cylinders, heads, and
sectors per track) used by the BIOS to translate disk I/O requests
(from the operating system or an application) into terms the hard
drive can accept. Logical cylinders may not exceed 1024. The
number of heads may not exceed 256. The number of sectors per
track may not exceed 63. These fields are only visible and
changeable when the drive translation mode is set to User.
Storage Options
Removable Media Boot
Enables/disables ability to boot the system from removable media.
Legacy Diskette Write
Enables/disables ability to write data to legacy diskettes.
✎
After saving changes to Removable Media Write, the computer
will restart. Turn the computer off, then on, manually.
BIOS DMA Data Transfers
Allows you to control how BIOS disk I/O requests are serviced.
When “Enable” is selected, the BIOS will service ATA disk read and
write requests with DMA data transfers. When “Disable” is selected,
the BIOS will service ATA disk read and write requests with PIO
data transfers.
SATA Emulation
Allows you to choose how the SATA controller and devices are
accessed by the operating system.
“Separate IDE Controller” is the default option. Up to 4 SATA and 2
PATA devices may be accessed in this mode. The SATA and PATA
controllers appear as two separate IDE controllers. Use this option
with Microsoft Windows 2000 and Windows XP.
• SATA 0 is seen as SATA Primary Device 0
• SATA 1 (if present) is seen as SATA Secondary Device 0
“Combined IDE Controller” is the other option. Up to 2 PATA and 2
SATA devices may be accessed in this mode. The SATA and PATA
controllers appear as one combined IDE controller. Use this option
with Microsoft Windows 98 and earlier operating systems.
• PATA Primary Device 0 replaces SATA 1
• PATA Primary Device 1 replaces SATA 3
✎
8-8
Support for specific Computer Setup options may vary depending on the hardware configuration.
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Table 8-2
Setup Utility
Heading
Option
Description
IDE Controller
Storage
(continued)
Allows you to enable or disable the primary IDE controller. This
feature is supported on select models only.
Primary SATA Controller
Allows you to enable or disable the Primary SATA controller.
Secondary SATA Controller
Allows you to enable or disable the Secondary SATA controller. This
feature is supported on select models only.
DPS Self-Test
Allows you to execute self-tests on ATA hard drives capable of
performing the Drive Protection System (DPS) self-tests.
✎
Boot Order
This selection will only appear when at least one drive capable of
performing the DPS self-tests is attached to the system.
Allows you to:
• Specify the order in which attached devices (such as a USB
flash media device, diskette drive, hard drive, optical drive, or
network interface card) are checked for a bootable operating
system image. Each device on the list may be individually
excluded from or included for consideration as a bootable
operating system source.
• Specify the order of attached hard drives. The first hard drive in
the order will have priority in the boot sequence and will be
recognized as drive C (if any devices are attached).
✎
MS-DOS drive lettering assignments may not apply after a
non-MS-DOS operating system has started.
Shortcut to Temporarily Override Boot Order
To boot one time from a device other than the default device
specified in Boot Order, restart the computer and press F9 when the
monitor light turns green. After POST is completed, a list of bootable
devices is displayed. Use the arrow keys to select the preferred
bootable device and press Enter. The computer then boots from the
selected non-default device for this one time.
Security
Setup Password
Allows you to set and enables setup (administrator) password.
✎
If the setup password is set, it is required to change Computer
Setup options, flash the ROM, and make changes to certain plug
and play settings under Windows.
See the Troubleshooting Guide on the Documentation CD for more
information.
Power-On
Password
✎
Allows you to set and enable power-on password.
See the Troubleshooting Guide for more information.
Support for specific Computer Setup options may vary depending on the hardware configuration.
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8-9
BIOS ROM
Table 8-2
Setup Utility
Heading
Security
(continued)
Option
Description
Password Options
(This selection will
appear only if a
power-on
password is set.)
Allows you to specify whether the password is required for warm
boot (CTRL+ALT+DEL).
Smart Cover
Allows you to:
Lock Legacy Resources - When enabled, prevents operating system
from changing legacy resources.
• Lock/unlock the Cover Lock.
• Set the Cover Removal Sensor to Disable/Notify User/Setup
Password.
✎
Notify User alerts the user that the sensor has detected that the
cover has been removed. Setup Password requires that the setup
password be entered to boot the computer if the sensor detects
that the cover has been removed.
This feature is supported on select models only. See the Desktop
Management Guide on the Documentation CD for more
information.
Embedded
Security
Allows you to:
• Enable/disable the Embedded Security device.
• Reset the device to Factory Settings.
This feature is supported on select models only. See the Desktop
Management Guide on the Documentation CD for more
information.
Device Security
Enables/disables serial ports, parallel port, front USB ports, system
audio, network controllers (some models), SMBus controller (some
models), and SCSI controllers (some models).
Network Service
Boot
Enables/disables the computer’s ability to boot from an operating
system installed on a network server. (Feature available on NIC
models only; the network controller must reside on the PCI bus or be
embedded on the system board.)
System IDs
Allows you to set:
• Asset tag (18-byte identifier) and ownership Tag (80-byte
identifier displayed during POST).
See the Desktop Management Guide on the Documentation CD
for more information.
• Chassis serial number or Universal Unique Identifier (UUID)
number. The UUID can only be updated if the current chassis
serial number is invalid. (These ID numbers are normally set in
the factory and are used to uniquely identify the system.)
• Keyboard locale setting (for example, English or German) for
System ID entry.
✎
8-10
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BIOS ROM
Table 8-2
Setup Utility
Heading
Security
Option
Description
DriveLock Security
Allows you to assign or modify a master or user password for hard
drives that support the ATA security command set. When this feature
is enabled, the user is prompted to provide one of the DriveLock
passwords during POST. If neither is successfully entered, the hard
drive will remain inaccessible until one of the passwords is
successfully provided during a subsequent cold-boot sequence.
(continued)
✎
This selection will only appear when at least one drive that
supports ATA security command set feature is attached to the
system.
See the Desktop Management Guide on the Documentation CD for
more information.
Data Execution
Prevention
Enable/Disable.
Data Execution Prevention Mode help prevent OS security breaches.
✎
Power
OS Power
Management
This selection is in effect only if the processor and operating
system being used comprehend and utilize the function.
• Runtime Power Management (selected processors only) Enable/Disable. Allows certain operating systems to reduce
processor voltage and frequency when the current software
load does not require the full capabilities of the processor.
• Idle Power Savings (selected processors only) Extended/Normal. Allows certain operating systems to
decrease the processors power consumption when the
processor is idle.
• ACPI S3 Support - Enables or disables ACPI S3 support.
• ACPI S3 Hard Disk Reset - Enabling this causes the BIOS to
ensure hard disks are ready to accept commands after
resuming from S3 before returning control to the operating
system.
• ACPI S3 PS2 Mouse Wakeup - Enables or disables waking from
S3 due to PS2 mouse activity.
• USB Wake on Device Insertion - Enables or disables system
wake from standby upon insertion of USB device.
✎
Hardware Power
Management
SATA power management enables or disables SATA bus and/or
device power management.
Thermal
Fan idle mode - This bar graph controls the minimum permitted fan
speed.
Support for specific Computer Setup options may vary depending on the hardware configuration.
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8-11
BIOS ROM
Table 8-2
Setup Utility
Heading
Advanced*
*For
advanced
users only
Option
Power-On Options
Description
Allows you to set:
• POST mode (QuickBoot, FullBoot, or FullBoot every 1-30 days).
• POST messages (enable/disable).
• F9 prompt (enable/disable). Enabling this feature will display
the text F9=Boot Menu during POST. Disabling this feature
prevents the text from being displayed but pressing F9 will still
access the Shortcut Boot (Order) Menu screen. See Storage >
Boot Order for more information.
• F10 prompt (enable/disable). Enabling this feature will display
the text F10=Setup during POST. Disabling this feature
prevents the text from being displayed but pressing F10 will still
access the Setup screen.
• F12 prompt (enable/disable). Enabling this feature will display
the text F12=Network Service Boot during POST.
Disabling this feature prevents the text from being displayed but
pressing F12 will still force the system to attempt booting from
the network.
• Option ROM* prompt (enable/disable). Enabling this feature
will cause the system to display a message before loading
options ROMs. (This feature is supported on select models only.)
• Remote wakeup boot source (remote server/local hard drive).
• After Power Loss (off/on/previous state): After power loss, if you
connect your computer to an electric power strip and would like
to turn on power to the computer using the switch on the power
strip, set this option to ON.
✎
If you turn off power to your computer using the switch on a
power strip, you will not be able to use the suspend/sleep feature
or the Remote Management features.
• POST Delay (in seconds) (enable/disable). Enabling this feature
will add a user-specified delay to the POST process. This delay
is sometimes needed for hard disks on some PCI cards that spin
up very slowly; so slowly that they are not ready to boot by the
time POST is finished. The POST delay also gives you more time
to press F10 to enter Computer (F10) Setup.
• I/O APIC Mode (enable/disable). Enabling this feature will
allow Microsoft Windows Operating Systems to run optimally.
This feature must be disabled for certain non-Microsoft
Operating Systems to work properly.
✎
8-12
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Table 8-2
Setup Utility
Heading
Advanced*
(continued)
Option
Power-On Options
(continued)
*For
advanced
users only
Description
Allows you to set: (continued)
• ACPI/USB Buffers @ Top of Memory (enable/disable).
Enabling this feature places USB memory buffers at the top
of memory. The advantage is that some amount of memory
below 1 MB is freed up for use by option ROMs. The
disadvantage is that a popular memory manager, HIMEM.SYS,
does not work properly when USB buffers are at top of memory
AND the system has 64 MB or less of RAM.
• Hyper-threading (enable/disable).
• Limit CPUID Maximum Value to 3 - Restricts the number of
CPUID functions reported by the microprocessor. Enable this
feature if booting to WinNT.
• Setup Browse Mode (enable/disable) - When enabled, allows
viewing Setup options without entering Setup password.
Execute Memory
Test
When selected, will reboot system and perform a complete memory
test.
BIOS Power-On
Allows you to set the computer to turn on automatically at a time you
specify.
Onboard Devices
Allows you to set resources for or disable onboard system devices
(diskette controller, serial port, or parallel port).
PCI Devices
• Lists currently installed PCI devices and their IRQ settings.
• Allows you to reconfigure IRQ settings for these devices or to
disable them entirely. These settings have no effect under an
APIC-based operating system.
Bus Options*
On select models, allows you to enable or disable:
• PCI SERR# Generation.
• PCI VGA palette snooping, which sets the VGA palette
snooping bit in PCI configuration space; only needed when
more than one graphics controller is installed.
✎
Support for specific Computer Setup options may vary depending on the hardware configuration.
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8-13
BIOS ROM
Table 8-2
Setup Utility
Heading
Advanced*
(continued)
Option
Device options
Description
Allows you to set:
• Printer mode (bi-directional, EPP & ECP, output only).
*For
advanced
users only
• Num Lock state at power-on (off/on).
• S5 Wake on LAN (enable/disable).
• To disable Wake on LAN during the off state (S5), use the arrow
(left and right) keys to select the Advanced > Device Options
menu and set the S5 Wake on Lan feature to “Disable.” This
obtains the lowest power consumption available on the computer
during S5. It does not affect the ability of the computer to Wake on
LAN from suspend or hibernation, but will prevent it from waking
from S5 via the network. It does not affect operation of the network
connection while the computer is on.
• If a network connection is not required, completely disable the
network controller (NIC) by using the arrow (left and right) keys to
select the Security > Device Security menu. Set the Network
Controller option to “Device Hidden.” This prevents the network
controller from being used by the operating system and reduces the
power used by the computer in S5.
• Processor cache (enable/disable).
• Unique Sleep State Blink Patterns. Allows you to choose an LED
blink pattern that uniquely identifies each sleep state.
• Integrated Video (enable/disable) Allows you to use integrated
video and PCI Up Solution video at the same time (available on
select models only).
✎
Inserting a PCI or PCI Express video card automatically disables
Integrated Video. When PCI Express video is on, Integrated
Video must remain disabled.
• Monitor Tracking (enable/disable). Allows ROM to save
monitor asset information.
Allows you to set:
• NIC PXE Option ROM Download (enable/disable). The BIOS
contains an embedded NIC option ROM to allow the unit to
boot through the network to a PXE server. This is typically used
to download a corporate image to a hard drive. The NIC
option ROM takes up memory space below 1MB commonly
referred to as DOS Compatibility Hole (DCH) space. This space
is limited. This F10 option will allow users to disable the
downloading of this embedded NIC option ROM thus giving
more DCH space for additional PCI cards which may need
option ROM space. The default will be to have the NIC option
ROM enabled.
PCI VGA
Configuration
✎
8-14
Displayed only if there are multiple PCI video adapters in the
system. Allows you to specify which VGA controller will be the
“boot” or primary VGA controller.
Support for specific Computer Setup options may vary depending on the hardware configuration.
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8.5 Client Management Functions
Table 8-3 provides a partial list of the client management BIOS functions supported by the
systems covered in this guide. These functions, designed to support intelligent manageability
applications, are Compaq-specific unless otherwise indicated.
Table 8-3.
Client Management Functions (INT15)
AX
Function
Mode
E800h
Get system ID
Real, 16-, & 32-bit Prot.
E813h
Get monitor data
Real, 16-, & 32-bit Prot.
E814h
Get system revision
Real, 16-, & 32-bit Prot.
E816h
Get temperature status
Real, 16-, & 32-bit Prot.
E817h
Get drive attribute
Real
E818h
Get drive off-line test
Real
E819h
Get chassis serial number
Real, 16-, & 32-bit Prot.
E820h [1]
Get system memory map
Real
E81Ah
Write chassis serial number
Real
E81Bh
Get hard drive threshold
Real
E81Eh
Get hard drive ID
Real
E827h
DIMM EEPROM Access
Real, 16-, & 32-bit Prot.
NOTE:
[1] Industry standard function.
All 32-bit protected-mode functions are accessed by using the industry-standard BIOS32 Service
Directory. Using the service directory involves three steps:
1. Locating the service directory.
2. Using the service directory to obtain the entry point for the client management functions.
3. Calling the client management service to perform the desired function.
The BIOS32 Service Directory is a 16-byte block that begins on a 16-byte boundary between the
physical address range of 0E0000h-0FFFFFh.
The following subsections provide a brief description of key Client Management functions.
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8-15
BIOS ROM
8.5.1 System ID and ROM Type
Diagnostic applications can use the INT 15, AX=E800h BIOS function to identify the type of
system. This function will return the system ID in the BX register. Systems have the following
IDs and ROM family types:
Table 8-4
System ID Numbers
System ID
Subsystem
Device ID
USDT
0A5Ch
2803h
SFF/ST:
0A54h
2801h
MT:
0A50h
2800h
CMT:
0A58h
2802h
System (Form Factor)
NOTE: For all systems, BIOS ROM Family = 786E1, PnP ID = CPQ0968, and Subsystem vendor ID = 103Ch.
The ROM family and version numbers can be verified with the Setup utility or the Compaq
Insight Manager or Diagnostics applications.
8.5.2 Temperature Status
The BIOS includes a function (INT15, AX=E816h) to retrieve the status of a system's interior
temperature. This function allows an application to check whether the temperature situation is at
a Normal, Caution, or Critical condition.
8.5.3 Drive Fault Prediction
The BIOS directly supports Drive Fault Prediction for IDE (ATA)-type hard drives. This feature
is provided through two Client Management BIOS calls. Function INT 15, AX=E817h is used to
retrieve a 512-byte block of drive attribute data while the INT 15, AX=E81Bh is used to retrieve
the drive's warranty threshold data. If data is returned indicating possible failure then the
following message is displayed:
1720-SMART Hard Drive detects imminent failure
8-16
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Technical Reference Guide
BIOS ROM
8.6 SMBIOS
In support of the DMI specification the PnP functions 50h and 51h are used to retrieve the
SMBIOS data. Function 50h retrieves the number of structures, size of the largest structure, and
SMBIOS version. Function 51h retrieves a specific structure. This system supports SMBIOS
version 2.4 and the following structure types:
Type
Data
0
BIOS Information
1
System Information
2
Base board information
3
System Enclosure or Chassis
4
Processor Information
7
Cache Information
8
Port Connector Information
9
System Slots
13
BIOS Language Information
15
System Event Log Information
16
Physical Memory Array
17
Memory Devices
19
Memory Array Mapped Addresses
20
Memory Device Mapped Addresses
31
Boot Integrity Service Entry Point
32
System Boot Information
✎ System information on these systems is handled exclusively through the SMBIOS.
8.7 USB Legacy Support
The BIOS ROM checks the USB port, during POST, for the presence of a USB keyboard. This
allows a system with only a USB keyboard to be used during ROM-based setup and also on a
system with an OS that does not include a USB driver.
On such a system a keystroke will generate an SMI and the SMI handler will retrieve the data
from the device and convert it to PS/2 data. The data will be passed to the keyboard controller
and processed as in the PS/2 interface. Changing the delay and/or typematic rate of a USB
keyboard though BIOS function INT 16 is not supported.
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8-17
BIOS ROM
8-18
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Technical Reference Guide
A
Error Messages and Codes
A.1 Introduction
This appendix lists the error codes and a brief description of the probable cause of the error.
✎ Errors listed in this appendix are applicable only for systems running HP/Compaq BIOS.
Not all errors listed in this appendix may be applicable to a particular system model and/or
configuration.
A.2 Beep/Power LED Codes
✎ Beep and Power LED indictions listed in Table A-1 apply only to HP-branded models.
Table A-1.
Beep/Power LED Codes
Beeps
Power LED
Probable Cause
None
Blinks red 2 times @ 1 Hz
Processor thermal shut down. Check air flow, fan
operation, and CPU heat sink
None
Blinks red 3 times @ 1 Hz
Processor not installed. Install or reseat CPU.
None
Blinks red 4 times @ 1 Hz
Power failure (power supply is overloaded). Check
storage devices, expansion cards and/or system
board (CPU power connector P3).
5 beeps
Blinks red 5 times @ 1 Hz
Pre-video memory error. Incompatible or incorrectly
seated DIMM.
6 beeps
Blinks red 6 times @ 1 Hz
Pre-video graphics error. On system with integrated
graphics, check/replace system board. On system with
graphics card, check/replace graphics card.
7 beeps
Blinks red 7 times @ 1 Hz
PCA failure. Check/replace system board.
8 beeps
Blinks red 8 times @ 1 Hz
Invalid ROM (checksum error). Reflash ROM using CD
or replace system board.
9 beeps
Blinks red 9 times @ 1 Hz
System powers on but fails to boot. Check power
supply, CPU, system board.
None
Blinks red 10 times @ 1 Hz
Bad option card.
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A-1
Error Messages and Codes
A.3 Power-On Self Test (POST) Messages
Table A-2.
Power-On Self Test (POST) Messages
A-2
Error Message
Probable Cause
Invalid Electronic Serial Number
Chassis serial number is corrupt. Use Setup to enter a valid number.
Network Server Mode Active (w/o
kybd)
System is in network mode.
101-Option ROM Checksum Error
A device’s option ROM has failed/is bad.
110-Out of Memory Space for
Option ROMs
Recently added PCI card contains and option ROM too large to
download during POST.
102-system Board Failure
Failed ESCD write, A20, timer, or DMA controller.
150-Safe POST Active
An option ROM failed to execute on a previous boot.
162-System Options Not Set
Invalid checksum, RTC lost power, or invalid configuration.
163-Time & Date Not Set
Date and time information in CMOS is not valid.
164-Memory Size Error
Memory has been added or removed.
201-Memory Error
Memory test failed.
213-Incompatible Memory Module
BIOS detected installed DIMM(s) as being not compatible.
214-DIM Configuration Warning
A specific error has occurred in a memory device installed in the
identified socket.
216-Memory Size Exceeds Max
Installed memory exceeds the maximum supported by the system.
217-DIMM Configuration Warning
Unbalanced memory configuration.
219-ECC Memory Module
Detected ECC Modules not
supported on this platform
Recently added memory module(s) support ECC memory error
correction.
301-Keyboard Error
Keyboard interface test failed (improper connection or stuck key).
303-Keyboard Controller Error
Keyboard buffer failed empty (8042 failure or stuck key).
304-Keyboard/System Unit Error
Keyboard controller failed self-test.
404-Parallel Port Address Conflict
Current parallel port address is conflicting with another device.
417-Network Interface Card Failure
NIC BIOS could not read Device ID of embedded NIC.
501-Display Adapter Failure
Graphics display controller.
510-Splash Image Corrupt
Corrupted splash screen image. Restore default image w/flash utility.
511-CPU Fan Not Detected
Processor heat sink fan is not connected.
512-Chassis Fan Not Detected
Chassis fan is not connected.
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Technical Reference Guide
Error Messages and Codes
Table A-2. (Continued)
Power-On Self Test (POST) Messages
Error Message
Probable Cause
514-CPU or Chassis Fan not
detected.
CPU fan is not connected or may have malfunctioned.
601-Diskette Controller Error
Diskette drive removed since previous boot.
605-Diskette Drive Type Error
Mismatch in drive type.
912-Computer Cover Removed
Since Last System Start Up
Cover (hood) removal has been detected by the Smart Cover Sensor.
914-Hood Lock Coil is not
Connected
Smart Cover Lock mechanism is missing or not connected.
916-Power Button Not Connected
Power button harness has been detached or unseated from the system
board.
917-Expansion Riser Not Detected
Expansion (backplane) board not seated properly.
919-Front Panel, MultiPort, and/or
MultiBay Risers not Detected
Riser card has been removed or has not been reinstalled properly in
the system.
1156-Serial Port A Cable Not
Detected
Cable from serial port header to I/O connector is missing or not
connected properly.
1157-Front Cables Not Detected
Cable from front panel USB and audio connectors is missing or not
connected properly.
1720-SMART Hard Drive Detects
Imminent Failure
SMART circuitry on an IDE drive has detected possible equipment
failure.
1721-SMART SCSI Hard Drive
Detects Imminent Failure
SMART circuitry on a SCSI drive has detected possible equipment
failure.
1785-MultiBay incorrectly installed
For integrated MultiBay/ USDT systems:
MultiBay device not properly seated.
or
MultiBay riser not properly seated.
1794--Inaccessible device attached
to SATA 1
(for systems with 2 SATA ports)
A device is attached to SATA 1. Any device attached to this connector
will be inaccessible while “SATA Emulation” is set to “Combined IDE
Controller” in Computer Setup.
1794-Inaccessible devices attached
to SATA 1 and/or SATA 3 (for
systems with 4 SATA ports)
A device is attached to SATA 1 and/or SATA 3.
Devices attached to these connectors will be inaccessible while “SATA
Emulation” is set to “Combined IDE Controller” in Computer Setup
1796-SATA Cabling Error
One or more SATA devices are improperly attached. For optimal
performance, the SATA 0 and SATA 1 connectors must be used before
SATA 2 and SATA 3.
Technical Reference Guide
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A-3
Error Messages and Codes
Table A-2. (Continued)
Power-On Self Test (POST) Messages
A-4
Error Message
Probable Cause
1801-Microcode Patch Error
A processor is installed for which the BIOS ROM has no patch. Check
for ROM update.
Invalid Electronic Serial Number
Electronic serial number has become corrupted.
Network Server Mode Active and
No Keyboard Attached
Keyboard failure while Network Server Mode enabled.
Parity Check 2
Keyboard failure while Network Server Mode enabled.
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Technical Reference Guide
Error Messages and Codes
A.4 System Error Messages (1xx-xx)
Table A-3.
System Error Messages
Message
Probable Cause
Message
Probable Cause
101
Option ROM error
109-02
CMOS clock rollover test failed
102
System board failure
109-03
CMOS not properly initialized (clk test)
103
System board failure
110-01
Programmable timer load data test failed
104-01
Master int. cntlr. test fialed
110-02
Programmable timer dynamic test failed
104-02
Slave int. cntlr. test failed
110-03
Program timer 2 load data test failed
104-03
Int. cntlr. SW RTC inoperative
111-01
Refresh detect test failed
105-01
Port 61 bit <6> not at zero
112-01
Speed test Slow mode out of range
105-02
Port 61 bit <5> not at zero
112-02
Speed test Mixed mode out of range
105-03
Port 61 bit <3> not at zero
112-03
Speed test Fast mode out of range
105-04
Port 61 bit <1> not at zero
112-04
Speed test unable to enter Slow mode
105-05
Port 61 bit <0> not at zero
112-05
Speed test unable to enter Mixed mode
105-06
Port 61 bit <5> not at one
112-06
Speed test unable to enter Fast mode
105-07
Port 61 bit <3> not at one
112-07
Speed test system error
105-08
Port 61 bit <1> not at one
112-08
Unable to enter Auto mode in speed test
105-09
Port 61 bit <0> not at one
112-09
Unable to enter High mode in speed test
105-10
Port 61 I/O test failed
112-10
Speed test High mode out of range
105-11
Port 61 bit <7> not at zero
112-11
Speed test Auto mode out of range
105-12
Port 61 bit <2> not at zero
112-12
Speed test variable speed mode inop.
105-13
No int. generated by failsafe timer
113-01
Protected mode test failed
105-14
NMI not triggered by failsafe timer
114-01
Speaker test failed
106-01
Keyboard controller test failed
116-xx
Way 0 read/write test failed
107-01
CMOS RAM test failed
162-xx
Sys. options failed (mismatch in drive type)
108-02
CMOS interrupt test failed
163-xx
Time and date not set
108-03
CMOS not properly initialized (int.test)
164-xx
Memory size
109-01
CMOS clock load data test failed
199-00
Installed devices test failed
[1]
NOTES:
[1] 102 message code may be caused by one of a variety of processor-related problems that may be solved by replacing the
processor, although system board replacement may be needed.
Technical Reference Guide
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A-5
Error Messages and Codes
A.5 Memory Error Messages (2xx-xx)
Table A-4.
Memory Error Messages
A-6
Message
Probable Cause
200-04
Real memory size changed
200-05
Extended memory size changed
200-06
Invalid memory configuration
200-07
Extended memory size changed
200-08
CLIM memory size changed
201-01
Memory machine ID test failed
202-01
Memory system ROM checksum failed
202-02
Failed RAM/ROM map test
202-03
Failed RAM/ROM protect test
203-01
Memory read/write test failed
203-02
Error while saving block in read/write test
203-03
Error while restoring block in read/write test
204-01
Memory address test failed
204-02
Error while saving block in address test
204-03
Error while restoring block in address test
204-04
A20 address test failed
204-05
Page hit address test failed
205-01
Walking I/O test failed
205-02
Error while saving block in walking I/O test
205-03
Error while restoring block in walking I/O test
206-xx
Increment pattern test failed
207-xx
ECC failure
210-01
Memory increment pattern test
210-02
Error while saving memory during increment pattern test
210-03
Error while restoring memory during increment pattern test
211-01
Memory random pattern test
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Technical Reference Guide
Error Messages and Codes
Table A-4. (Continued)
Memory Error Messages
Message
Probable Cause
211-02
Error while saving memory during random memory pattern test
211-03
Error while restoring memory during random memory pattern test
213-xx
Incompatible DIMM in slot x
214-xx
Noise test failed
215-xx
Random address test
A.6 Keyboard Error Messages (30x-xx)
Table A-5.
Keyboard Error Messages
Message
Probable Cause
Message
Probable Cause
300-xx
Failed ID test
303-05
LED test, LED command test failed
301-01
Kybd short test, 8042 self-test
failed
303-06
LED test, LED command test failed
301-02
Kybd short test, interface test
failed
303-07
LED test, LED command test failed
301-03
Kybd short test, echo test failed
303-08
LED test, command byte restore test failed
301-04
Kybd short test, kybd reset failed
303-09
LED test, LEDs failed to light
301-05
Kybd short test, kybd reset failed
304-01
Keyboard repeat key test failed
302-xx
Failed individual key test
304-02
Unable to enter mode 3
302-01
Kybd long test failed
304-03
Incorrect scan code from keyboard
303-01
LED test, 8042 self-test failed
304-04
No Make code observed
303-02
LED test, reset test failed
304-05
Cannot /disable repeat key feature
303-03
LED test, reset failed
304-06
Unable to return to Normal mode
303-04
LED test, LED command test failed
--
--
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A-7
Error Messages and Codes
A.7 Printer Error Messages (4xx-xx)
Table A-6
Printer Error Messages
Message
Probable Cause
Message
Probable Cause
401-01
Printer failed or not connected
402-11
Interrupt test, data/cntrl. reg. failed
402-01
Printer data register failed
402-12
Interrupt test and loopback test failed
402-02
Printer control register failed
402-13
Int. test, LpBk. test., and data register failed
402-03
Data and control registers failed
402-14
Int. test, LpBk. test., and cntrl. register failed
402-04
Loopback test failed
402-15
Int. test, LpBk. test., and data/cntrl. reg.
failed
402-05
Loopback test and data reg.
failed
402-16
Unexpected interrupt received
402-06
Loopback test and cntrl. reg.
failed
402-01
Printer pattern test failed
402-07
Loopback tst, data/cntrl. reg.
failed
403-xx
Printer pattern test failed
402-08
Interrupt test failed
404-xx
Parallel port address conflict
402-09
Interrupt test and data reg. failed
498-00
Printer failed or not connected
402-10
Interrupt test and control reg.
failed
--
--
A.8 Video (Graphics) Error Messages (5xx-xx)
Table A-7.
Video (Graphics) Error Messages
Message
Probable Cause
Message
Probable Cause
501-01
Video controller test failed
508-01
320x200 mode, color set 0 test failed
502-01
Video memory test failed
509-01
320x200 mode, color set 1 test failed
503-01
Video attribute test failed
510-01
640x200 mode test failed
504-01
Video character set test failed
511-01
Screen memory page test failed
505-01
80x25 mode, 9x14 cell test
failed
512-01
Gray scale test failed
506-01
80x25 mode, 8x8 cell test failed
514-01
White screen test failed
507-01
40x25 mode test failed
516-01
Noise pattern test failed
See Table A-14 for additional video (graphics) messages.
A-8
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Technical Reference Guide
Error Messages and Codes
A.9 Diskette Drive Error Messages (6xx-xx)
Table A-8.
Diskette Drive Error Messages
Message
Probable Cause
Message
Probable Cause
6xx-01
Exceeded maximum soft error limit
6xx-20
Failed to get drive type
6xx-02
Exceeded maximum hard error
limit
6xx-21
Failed to get change line status
6xx-03
Previously exceeded max soft limit
6xx-22
Failed to clear change line status
6xx-04
Previously exceeded max hard limit 6xx-23
Failed to set drive type in ID media
6xx-05
Failed to reset controller
6xx-24
Failed to read diskette media
6xx-06
Fatal error while reading
6xx-25
Failed to verify diskette media
6xx-07
Fatal error while writing
6xx-26
Failed to read media in speed test
6xx-08
Failed compare of R/W buffers
6xx-27
Failed speed limits
6xx-09
Failed to format a tract
6xx-28
Failed write-protect test
6xx-10
Failed sector wrap test
--
--
600-xx = Diskette drive ID test
609-xx = Diskette drive reset controller test
601-xx = Diskette drive format
610-xx = Diskette drive change line test
602-xx = Diskette read test
611-xx = Pri. diskette drive port addr. conflict
603-xx = Diskette drive R/W compare test
612-xx = Sec. diskette drive port addr. conflict
604-xx = Diskette drive random seek test
694-00 = Pin 34 not cut on 360-KB drive
605-xx = Diskette drive ID media
697-00 = Diskette type error
606-xx = Diskette drive speed test
698-00 = Drive speed not within limits
607-xx = Diskette drive wrap test
699-00 = Drive/media ID error (run Setup)
608-xx = Diskette drive write-protect test
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A-9
Error Messages and Codes
A.10 Serial Interface Error Messages (11xx-xx)
Table A-9.
Serial Interface Error Messages
Message
Probable Cause
Message
Probable Cause
1101-01
UART DLAB bit failure
1101-13
UART cntrl. signal interrupt failure
1101-02
Line input or UART fault
1101-14
DRVR/RCVR data failure
1101-03
Address line fault
1109-01
Clock register initialization failure
1101-04
Data line fault
1109-02
Clock register rollover failure
1101-05
UART cntrl. signal failure
1109-03
Clock reset failure
1101-06
UART THRE bit failure
1109-04
Input line or clock failure
1101-07
UART Data RDY bit failure
1109-05
Address line fault
1101-08
UART TX/RX buffer failure
1109-06
Data line fault
1101-09
Interrupt circuit failure
1150-xx
Comm port setup error (run Setup)
1101-10
COM1 set to invalid INT
1151-xx
COM1 address conflict
1101-11
COM2 set to invalid INT
1152-xx
COM2 address conflict
1101-12
DRVR/RCVR cntrl. signal failure
1155-xx
COM port address conflict
A-10
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Error Messages and Codes
A.11 Modem Communications Error Messages (12xx-xx)
Table A-10.
Modem Communications Error Messages
Message
Probable Cause
Message
Probable Cause
1201-XX
Modem internal loopback test
1204-03
Data block retry limit reached [4]
1201-01
UART DLAB bit failure
1204-04
RX exceeded carrier lost limit
1201-02
Line input or UART failure
1204-05
TX exceeded carrier lost limit
1201-03
Address line failure
1204-06
Time-out waiting for dial tone
1201-04
Data line fault
1204-07
Dial number string too long
1201-05
UART control signal failure
1204-08
Modem time-out waiting for remote
response
1201-06
UART THRE bit failure
1204-09
Modem exceeded maximum redial limit
1201-07
UART DATA READY bit failure
1204-10
Line quality prevented remote response
1201-08
UART TX/RX buffer failure
1204-11
Modem time-out waiting for remote
connection
1201-09
Interrupt circuit failure
1205-XX
Modem auto answer test
1201-10
COM1 set to invalid inturrupt
1205-01
Time-out waiting for SYNC [5]
1201-11
COM2 set to invalid
1205-02
Time-out waiting for response [5]
1201-12
DRVR/RCVR control signal failure 1205-03
Data block retry limit reached [5]
1201-13
UART control signal interrupt
failure
1205-04
RX exceeded carrier lost limit
1201-14
DRVR/RCVR data failure
1205-05
TX exceeded carrier lost limit
1201-15
Modem detection failure
1205-06
Time-out waiting for dial tone
1201-16
Modem ROM, checksum failure
1205-07
Dial number string too long
1201-17
Tone detect failure
1205-08
Modem time-out waiting for remote
response
1202-XX
Modem internal test
1205-09
Modem exceeded maximum redial limit
1202-01
Time-out waiting for SYNC [1]
1205-10
Line quality prevented remote response
1202-02
Time-out waiting for response [1]
1205-11
Modem time-out waiting for remote
connection
1202-03
Data block retry limit reached [1] 1206-XX
Dial multi-frequency tone test
1202-11
Time-out waiting for SYNC [2]
1206-17
Tone detection failure
1202-12
Time-out waiting for response [2]
1210-XX
Modem direct connect test
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A-11
Error Messages and Codes
Table A-10. (Continued)
Modem Communications Error Messages
Message
Probable Cause
Message
Probable Cause
1202-13
Data block retry limit reached [2] 1210-01
Time-out waiting for SYNC [6]
1202-21
Time-out waiting for SYNC [3]
1210-02
Time-out waiting for response [6]
1202-22
Time-out waiting for response [3]
1210-03
Data block retry limit reached [6]
1202-23
Data block retry limit reached [3] 1210-04
RX exceeded carrier lost limit
1203-XX
Modem external termination test
1210-05
TX exceeded carrier lost limit
1203-01
Modem external TIP/RING
failure
1210-06
Time-out waiting for dial tone
1203-02
Modem external data TIP/RING
fail
1210-07
Dial number string too long
1203-03
Modem line termination failure
1210-08
Modem time-out waiting for remote
response
1204-XX
Modem auto originate test
1210-09
Modem exceeded maximum redial limit
1204-01
Time-out waiting for SYNC [4]
1210-10
Line quality prevented remote response
1204-02
Time-out waiting for response [4]
1210-11
Modem time-out waiting for remote
connection
NOTES:
[1] Local loopback mode
[4] Modem auto originate test
[2] Analog loopback originate mode
[5] Modem auto answer test
[3] Analog loopback answer mode
[6] Modem direct connect test
A.12 System Status Error Messages (16xx-xx)
Table A-11
System Status Error Messages
A-12
Message
Probable Cause
1601-xx
Temperature violation
1611-xx
Fan failure
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Error Messages and Codes
A.13 Hard Drive Error Messages (17xx-xx)
Table A-12
Hard Drive Error Messages
Message
Probable Cause
Message
Probable Cause
17xx-01
Exceeded max. soft error limit
17xx-51
Failed I/O read test
17xx-02
Exceeded max. Hard error limit
17xx-52
Failed file I/O compare test
17xx-03
Previously exceeded max. soft error
limit
17xx-53
Failed drive/head register test
17xx-04
Previously exceeded max.hard error
limit
17xx-54
Failed digital input register test
17xx-05
Failed to reset controller
17xx-55
Cylinder 1 error
17xx-06
Fatal error while reading
17xx-56
Failed controller RAM diagnostics
17xx-07
Fatal error while writing
17xx-57
Failed controller-to-drive diagnostics
17xx-08
Failed compare of R/W buffers
17xx-58
Failed to write sector buffer
17xx-09
Failed to format a track
17xx-59
Failed to read sector buffer
17xx-10
Failed diskette sector wrap during
read
17xx-60
Failed uncorrectable ECC error
17xx-19
Cntlr. failed to deallocate bad sectors 17xx-62
Failed correctable ECC error
17xx-40
Cylinder 0 error
17xx-63
Failed soft error rate
17xx-41
Drive not ready
17xx-65
Exceeded max. bad sectors per track
17xx-42
Failed to recalibrate drive
17xx-66
Failed to initialize drive parameter
17xx-43
Failed to format a bad track
17xx-67
Failed to write long
17xx-44
Failed controller diagnostics
17xx-68
Failed to read long
17xx-45
Failed to get drive parameters from
ROM
17xx-69
Failed to read drive size
17xx-46
Invalid drive parameters from ROM
17xx-70
Failed translate mode
17xx-47
Failed to park heads
17xx-71
Failed non-translate mode
17xx-48
Failed to move hard drive table to
RAM
17xx-72
Bad track limit exceeded
17xx-49
Failed to read media in file write test
17xx-73
Previously exceeded bad track limit
17xx-50
Failed I/O write test
--
--
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A-13
Error Messages and Codes
NOTE:
xx = 00, Hard drive ID test
xx = 19, Hard drive power mode test
xx = 01, Hard drive format test
xx = 20, SMART drive detects imminent failure
xx = 02, Hard drive read test
xx = 21, SCSI hard drive imminent failure
xx = 03, Hard drive read/write compare test xx = 24, Net work preparation test
xx = 04, Hard drive random seek test
xx = 36, Drive monitoring test
xx = 05, Hard drive controller test
xx = 71, Pri. IDE controller address conflict
xx = 06, Hard drive ready test
xx = 72, Sec. IDE controller address conflict
xx = 07, Hard drive recalibrate test
xx = 80, Disk 0 failure
xx = 08, Hard drive format bad track test xx = 81, Disk 1 failure
A-14
xx = 09, Hard drive reset controller test
xx = 82, Pri. IDE controller failure
xx = 10, Hard drive park head test
xx = 90, Disk 0 failure
xx = 14, Hard drive file write test
xx = 91, Disk 1 failure
xx = 15, Hard drive head select test
xx = 92, Se. controller failure
xx = 16, Hard drive conditional format test
xx = 93, Sec. Controller or disk failure
xx = 17, Hard drive ECC test
xx = 99, Invalid hard drive type
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Technical Reference Guide
Error Messages and Codes
A.14 Hard Drive Error Messages (19xx-xx)
Table A-13
Hard Drive Error Messages
Message
Probable Cause
Message
Probable Cause
19xx-01
Drive not installed
19xx-21
Got servo pulses second time but not first
19xx-02
Cartridge not installed
19xx-22
Never got to EOT after servo check
19xx-03
Tape motion error
19xx-23
Change line unset
19xx-04
Drive busy erro
19xx-24
Write-protect error
19xx-05
Track seek error
19xx-25
Unable to erase cartridge
19xx-06
Tape write-protect error
19xx-26
Cannot identify drive
19xx-07
Tape already Servo Written
19xx-27
Drive not compatible with controller
19xx-08
Unable to Servo Write
19xx-28
Format gap error
19xx-09
Unable to format
19xx-30
Exception bit not set
19xx-10
Format mode error
19xx-31
Unexpected drive status
19xx-11
Drive recalibration error
19xx-32
Device fault
19xx-12
Tape not Servo Written
19xx-33
Illegal command
19xx-13
Tape not formatted
19xx-34
No data detected
19xx-14
Drive time-out error
19xx-35
Power-on reset occurred
19xx-15
Sensor error flag
19xx-36
Failed to set FLEX format mode
19xx-16
Block locate (block ID) error
19xx-37
Failed to reset FLEX format mode
19xx-17
Soft error limit exceeded
19xx-38
Data mismatch on directory track
19xx-18
Hard error limit exceeded
19xx-39
Data mismatch on track 0
19xx-19
Write (probably ID ) error
19xx-40
Failed self-test
19xx-20
NEC fatal error
19xx-91
Power lost during test
1900-xx = Tape ID test failed
1904-xx = Tape BOT/EOT test failed
1901-xx = Tape servo write failed
1905-xx = Tape read test failed
1902-xx = Tape format failed
1906-xx = Tape R/W compare test failed
1903-xx = Tape drive sensor test failed
1907-xx = Tape write-protect failed
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A-15
Error Messages and Codes
A.15 Video (Graphics) Error Messages (24xx-xx)
Table A-14
Video (Graphics) Error Messages
Message
Probable Cause
Message
Probable Cause
2402-01
Video memory test failed
2418-02
EGA shadow RAM test failed
2403-01
Video attribute test failed
2419-01
EGA ROM checksum test failed
2404-01
Video character set test failed
2420-01
EGA attribute test failed
2405-01
80x25 mode, 9x14 cell test failed
2421-01
640x200 mode test failed
2406-01
80x25 mode, 8x8 cell test failed
2422-01
640x350 16-color set test failed
2407-01
40x25 mode test failed
2423-01
640x350 64-color set test failed
2408-01
320x200 mode color set 0 test failed
2424-01
EGA Mono. text mode test failed
2409-01
320x200 mode color set 1 test failed
2425-01
EGA Mono. graphics mode test failed
2410-01
640x200 mode test failed
2431-01
640x480 graphics mode test failed
2411-01
Screen memory page test failed
2432-01
320x200 256-color set test failed
2412-01
Gray scale test failed
2448-01
Advanced VGA controller test failed
2414-01
White screen test failed
2451-01
132-column AVGA test failed
2416-01
Noise pattern test failed
2456-01
AVGA 256-color test failed
2417-01
Lightpen text test failed, no response
2458-xx
AVGA BitBLT test failed
2417-02
Lightpen text test failed, invalid
response
2468-xx
AVGA DAC test failed
2417-03
Lightpen graphics test failed, no resp.
2477-xx
AVGA data path test failed
2417-04
Lightpen graphics tst failed, invalid
resp.
2478-xx
AVGA BitBLT test failed
2418-01
EGA memory test failed
2480-xx
AVGA linedraw test failed
A.16 Audio Error Messages (3206-xx)
Table A-15
Audio Error Messages
A-16
Message
Probable Cause
3206-xx
Audio subsystem internal error
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Technical Reference Guide
Error Messages and Codes
A.17 DVD/CD-ROM Error Messages (33xx-xx)
Table A-16
DVD/CD-ROM Error Messages
Message
Probable Cause
3301-xx
Drive test failed
3305-xx
Seek test failed
A.18 Network Interface Error Messages (60xx-xx)
Table A-17
Network Interface Error Messages
Message
Probable Cause
Message
Probable Cause
6000-xx
Pointing device interface error
6054-xx
Token ring configuration test failed
6014-xx
Ethernet configuration test failed
6056-xx
Token ring reset test failed
6016-xx
Ethernet reset test failed
6068-xx
Token ring int. loopback test failed
6028-xx
Ethernet int. loopback test failed
6069-xx
Token ring ext. loopback test failed
6029-xx
Ethernet ext. loopback test failed
6089-xx
Token ring open
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A-17
Error Messages and Codes
A.19 SCSI Interface Error Messages (65xx-xx, 66xx-xx,
67xx-xx)
Table A-18
SCSI Interface Error Messages
Message
Probable Cause
Message
Probable Cause
6nyy-02
Drive not installed
6nyy-33
Illegal controller command
6nyy-03
Media not installed
6nyy-34
Invalid SCSI bus phase
6nyy-05
Seek failure
6nyy-35
Invalid SCSI bus phase
6nyy-06
Drive timed out
6nyy-36
Invalid SCSI bus phase
6nyy-07
Drive busy
6nyy-39
Error status from drive
6nyy-08
Drive already reserved
6nyy-40
Drive timed out
6nyy-09
Reserved
6nyy-41
SSI bus stayed busy
6nyy-10
Reserved
6nyy-42
ACK/REQ lines bad
6nyy-11
Media soft error
6nyy-43
ACK did not deassert
6nyy-12
Drive not ready
6nyy-44
Parity error
6nyy-13
Media error
6nyy-50
Data pins bad
6nyy-14
Drive hardware error
6nyy-51
Data line 7 bad
6nyy-15
Illegal drive command
6nyy-52
MSG, C/D, or I/O lines bad
6nyy-16
Media was changed
6nyy-53
BSY never went busy
6nyy-17
Tape write-protected
6nyy-54
BSY stayed busy
6nyy-18
No data detected
6nyy-60
Controller CONFIG-1 register fault
6nyy-21
Drive command aborted
6nyy-61
Controller CONFIG-2 register fault
6nyy-24
Media hard error
6nyy-65
Media not unloaded
6nyy-25
Reserved
6nyy-90
Fan failure
6nyy-30
Controller timed out
6nyy-91
Over temperature condition
6nyy-31
Unrecoverable error
6nyy-92
Side panel not installed
6nyy-32
Controller/drive not connected
6nyy-99
Autoloader reported tape not loaded properly
n = 5, Hard drive
= 6, CD-ROM drive
= 7, Tape drive
yy = 00, ID
= 03, Power check
= 05, Read
= 06, SA/Media
= 08, Controller
= 23, Random read
= 28, Media load/unload
A-18
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Technical Reference Guide
Error Messages and Codes
A.20 Pointing Device Interface Error Messages
(8601-xx)
Table A-19
Pointing Device Interface Error Messages
Message
Probable Cause
Message
Probable Cause
8601-01
Mouse ID fails
8601-07
Right block not selected
8601-02
Left mouse button is inoperative
8601-08
Timeout occurred
8601-03
Left mouse button is stuck closed
8601-09
Mouse loopback test failed
8601-04
Right mouse button is inoperative
8601-10
Pointing device is inoperative
8601-05
Right mouse button is stuck closed 8602-xx
I/F test failed
8601-06
Left block not selected
--
Technical Reference Guide
--
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A-19
Error Messages and Codes
A-20
www.hp.com
Technical Reference Guide
B
ASCII Character Set
B.1 Introduction
This appendix lists, in Table B-1, the 256-character ASCII code set including the decimal and
hexadecimal values. All ASCII symbols may be called while in DOS or using standard
text-mode editors by using the combination keystroke of holding the Alt key and using the
Numeric Keypad to enter the decimal value of the symbol. The extended ASCII characters
(decimals 128-255) can only be called using the Alt + Numeric Keypad keys.
keystrokes, refer to notes at the end of the table. Applications may interpret multiple
✎ Regarding
keystroke accesses differently or ignore them completely.
Table B-1.
ASCII Character Set
Dec
Hex
Symbol
Dec
Hex
Symbol
Dec
Hex
Symbol
Dec
Hex
Symbol
0
00
Blank
32
20
Space
64
40
@
96
60
‘
1
01
33
21
!
65
41
A
97
61
a
2
02
34
22
“
66
42
B
98
62
b
3
03
©
35
23
#
67
43
C
99
63
c
4
04
®
36
24
$
68
44
D
100
64
d
5
05
ß
37
25
%
69
45
E
101
65
e
6
06
™
38
26
&
70
46
F
102
66
f
7
07
l
39
27
‘
71
47
G
103
67
g
8
08
m
40
28
(
72
48
H
104
68
h
9
09
41
29
)
73
49
I
105
69
I
10
0A
42
2A
*
74
4A
J
106
6A
j
11
0B
43
2B
+
75
4B
K
107
6B
k
12
0C
44
2C
`
76
4C
L
108
6C
l
13
0D
45
2D
-
77
4D
M
109
6D
m
14
0E
46
2E
.
78
4E
N
110
6E
n
15
0F
47
2F
/
79
4F
O
111
6F
o
16
10
4
48
30
0
80
50
P
112
70
p
17
11
3
49
31
1
81
51
Q
113
71
q
Technical Reference Guide
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B-1
ASCII Character Set
Table B-1. (Continued)
ASCII Character Set
B-2
Dec
Hex
Symbol
Dec
Hex
Symbol
Dec
Hex
Symbol
Dec
Hex
Symbol
18
12
×
50
32
2
82
52
R
114
72
r
19
13
!!
51
33
3
83
53
S
115
73
s
20
14
¶
52
34
4
84
54
T
116
74
t
21
15
§
53
35
5
85
55
U
117
75
u
22
16
0
54
36
6
86
56
V
118
76
v
23
17
×
55
37
7
87
57
W
119
77
w
24
18
¦
56
38
8
88
58
X
120
78
x
25
19
Ø
57
39
9
89
59
Y
121
79
y
26
1A
Æ
58
3A
:
90
5A
Z
122
7A
z
27
1B
¨
59
3B
;
91
5B
[
123
7B
{
28
1C
60
3C
<
92
5C
\
124
7C
|
29
1D
´
61
3D
=
93
5D
]
125
7D
}
30
1E
s
62
3E
>
94
5E
^
126
7E
~
31
1F
t
63
3F
?
95
5F
_
127
7F
128
80
Ç
160
A0
á
192
C0
224
E0
129
81
ü
161
A1
í
193
C1
225
E1
130
82
é
162
A2
ó
194
C2
226
E2
131
83
â
163
A3
ú
195
C3
227
E3
132
84
ä
164
A4
ñ
196
C4
228
E4
133
85
à
165
A5
Ñ
197
C5
229
E5
134
86
å
166
A6
ª
198
C6
230
E6
135
87
ç
167
A7
º
199
C7
231
E7
136
88
ê
168
A8
¿
200
C8
232
E8
137
89
ë
169
A9
201
C9
233
E9
138
8A
è
170
AA
¬
202
CA
234
EA
139
8B
ï
171
AB
½
203
CB
235
EB
140
8C
î
172
AC
¼
204
CC
236
EC
141
8D
ì
173
AD
¡
205
CD
237
ED
142
8E
Ä
174
AE
«
206
CE
238
EE
143
8F
Å
175
AF
»
207
CF
239
EF
144
90
É
176
B0
208
D0
240
F0
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[1]
ß
µ
Technical Reference Guide
ASCII Character Set
Table B-1. (Continued)
ASCII Character Set
Dec
Hex
Symbol
Dec
Hex
145
91
æ
177
146
92
Æ
147
93
148
Dec
Hex
Dec
Hex
Symbol
B1
209
D1
241
F1
±
178
B2
210
D2
242
F2
ô
179
B3
211
D3
243
F3
94
ö
180
B4
212
D4
244
F4
149
95
ò
181
B5
213
D5
245
F5
150
96
û
182
B6
214
D6
246
F6
151
97
ù
183
B7
215
D7
247
F7
152
98
ÿ
184
B8
216
D8
248
F8
°
153
99
Ö
185
B9
217
D9
249
F9
·
154
9A
Ü
186
BA
218
DA
250
FA
·
155
9B
¢
187
BB
219
DB
251
FB
156
9C
£
188
BC
220
DC
252
FC
157
9D
¥
189
BD
221
DD
253
FD
158
9E
190
BE
222
DE
254
FE
159
9F
191
BF
223
DF
255
FF
ƒ
Symbol
Symbol
÷
²
Blank
NOTES:
[1] Symbol not displayed.
Keystroke Guide:
Keystroke(s)
Dec #
0
Ctrl 2
1-26
Ctrl A thru Z respectively
27
Ctrl [
28
Ctrl
29
Ctrl ]
30
Ctrl 6
31
Ctrl 32
Space Bar
33-43
Shift and key w/corresponding symbol
44-47
Key w/corresponding symbol
48-57
Key w/corresponding symbol, numerical keypad w/Num Lock active
58
Shift and key w/corresponding symbol
59
Key w/corresponding symbol
60
Shift and key w/corresponding symbol
61
Key w/corresponding symbol
62-64
Shift and key w/corresponding symbol
65-90
Shift and key w/corresponding symbol or key w/corresponding symbol and Caps Lock active
91-93
Key w/corresponding symbol
94, 95
Shift and key w/corresponding symbol
96
Key w/corresponding symbol
97-126
Key w/corresponding symbol or Shift and key w/corresponding symbol and Caps Lock active
127
Ctrl 128-255
Alt and decimal digit(s) of desired character
Technical Reference Guide
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B-3
ASCII Character Set
B-4
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Technical Reference Guide
C
Keyboard
C.1 Introduction
This appendix describes the HP keyboard that is included as standard with the system unit. The
keyboard complies with the industry-standard classification of an “enhanced keyboard” and
includes a separate cursor control key cluster, twelve “function” keys, and enhanced
programmability for additional functions.
This appendix covers the following keyboard types:
■
Standard enhanced keyboard.
■
Space-Saver Windows-version keyboard featuring additional keys for specific support of the
Windows operating system.
■
Easy Access keyboard with additional buttons for internet accessibility functions.
Only one type of keyboard is supplied with each system. Other types may be available as an
option.
appendix discusses only the keyboard unit. The keyboard interface is a function of the
✎ This
system unit and is discussed in Chapter 5, Input/Output Interfaces.
C.2 Keystroke Processing
A functional block diagram of the keystroke processing elements is shown in Figure C-1. Power
(+5 VDC) is obtained from the system through the PS/2-type interface. The keyboard uses a
Z86C14 (or equivalent) microprocessor. The Z86C14 scans the key matrix drivers every 10 ms
for pressed keys while at the same time monitoring communications with the keyboard interface
of the system unit. When a key is pressed, a Make code is generated. A Break code is generated
when the key is released. The Make and Break codes are collectively referred to as scan codes.
All keys generate Make and Break codes with the exception of the Pause key, which generates a
Make code only.
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C-1
Keyboard
Num
Lock
Keyswitch
Matrix
Caps
Lock
Matrix
Drivers
Matrix
Receivers
Keyboard
Processor
Scroll
Lock
Data/
CLK
Keyboard
Interface
(System Unit)
Figure C-1. Keystroke Processing Elements, Block Diagram
When the system is turned on, the keyboard processor generates a Power-On Reset (POR) signal
after a period of 150 ms to 2 seconds. The keyboard undergoes a Basic Assurance Test (BAT)
that checks for shorted keys and basic operation of the keyboard processor. The BAT takes from
300 to 500 ms to complete.
If the keyboard fails the BAT, an error code is sent to the CPU and the keyboard is disabled until
an input command is received. After successful completion of the POR and BAT, a completion
code (AAh) is sent to the CPU and the scanning process begins.
The keyboard processor includes a 16-byte FIFO buffer for holding scan codes until the system
is ready to receive them. Response and typematic codes are not buffered. If the buffer is full (16
bytes held) a 17th byte of a successive scan code results in an overrun condition and the overrun
code replaces the scan code byte and any additional scan code data (and the respective key
strokes) are lost. Multi-byte sequences must fit entirely into the buffer before the respective
keystroke can be registered.
C-2
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Technical Reference Guide
Keyboard
C.2.1 PS/2-Type Keyboard Transmissions
The PS/2-type keyboard sends two main types of data to the system; commands (or responses to
system commands) and keystroke scan codes. Before the keyboard sends data to the system
(specifically, to the 8042-type logic within the system), the keyboard verifies the clock and data
lines to the system. If the clock signal is low (0), the keyboard recognizes the inhibited state and
loads the data into a buffer. Once the inhibited state is removed, the data is sent to the system.
Keyboard-to-system transfers (in the default mode) consist of 11 bits as shown in Figure C-2.
Tcy
Tcl
Tch
Clock
Th-b-t
(LSb)
Data
Start
Bit
Data
0
(MSb)
Data
1
Data
2
Data
3
Data
4
Data
5
Data
6
Parameter
Minimum Nominal
Maximum
Tcy (clock cycle)
60 us
--
80 us
Tcl (clock low)
30 us
41 us
50 us
Tch (clock high)
30 us
--
40 us
Th-b-t (high-before-transmit)
--
20 us
--
Data
7
Parity
Bit
Stop
Bit
Figure C-2. PS/2 Keyboard-To-System Transmission, Timing Diagram
The system can halt keyboard transmission by setting the clock signal low. The keyboard checks
the clock line every 60 µs to verify the state of the signal. If a low is detected, the keyboard will
finish the current transmission if the rising edge of the clock pulse for the parity bit has not
occurred. The system uses the same timing relationships during reads (typically with slightly
reduced time periods).
The enhanced keyboard has three operating modes:
■
Mode 1—PC-XT compatible
■
Mode 2—PC-AT compatible (default)
■
Mode 3—Select mode (keys are programmable as to make-only, break-only, typematic)
Modes can be selected by the user or set by the system. Mode 2 is the default mode. Each mode
produces a different set of scan codes. When a key is pressed, the keyboard processor sends that
key's make code to the 8042 logic of the system unit. The When the key is released, a release
code is transmitted as well (except for the Pause key, which produces only a make code). The
8042-type logic of the system unit responds to scan code reception by asserting IRQ1, which is
processed by the interrupt logic and serviced by the CPU with an interrupt service routine. The
service routine takes the appropriate action based on which key was pressed.
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C-3
Keyboard
C.2.2 USB-Type Keyboard Transmissions
The USB-type keyboard sends essentially the same information to the system that the PS/2
keyboard does except that the data receives additional NRZI encoding and formatting (prior to
leaving the keyboard) to comply with the USB I/F specification (discussed in chapter 5 of this
guide).
Packets received at the system's USB I/F and decoded as originating from the keyboard result in
an SMI being generated. An SMI handler routine is invoked that decodes the data and transfers
the information to the 8042 keyboard controller where normal (legacy) keyboard processing
takes place.
C.2.3 Keyboard Layouts
Figures C-3 through C-8 show the key layouts for keyboards shipped with HPsystems. Actual
styling details including location of the HP logo as well as the numbers lock, caps lock, and
scroll lock LEDs may vary.
C.2.3.1 Standard Enhanced Keyboards
1
18
17
2
3
4
5
19
20
21
22
41
40
39
59
61
60
75
45
44
93
26
47
46
27
48
67
66
81
80
9
25
65
64
79
78
24
23
63
62
77
76
92
43
42
8
7
6
11
28
29
50
49
68
83
82
10
30
51
14
15
16
32
33
34
35
36
37
52
53
54
55
56
57
72
73
74
88
89
90
71
87
86
85
94
13
31
70
69
84
12
96
95
100
97
98
99
14
15
16
32
33
34
35
36
37
52
53
54
55
56
57
72
73
74
88
89
90
101
38
58
91
Figure C-3. U.S. English (101-Key) Keyboard Key Positions
1
17
39
59
75
92
18
2
3
4
5
19
20
21
22
40
41
61
60
104 76
43
42
77
93
62
78
24
23
45
44
63
79
64
80
8
7
6
47
46
81
94
26
25
65
9
66
82
27
48
67
11
28
29
50
49
68
83
10
84
69
12
13
31
51
70 103
85
71
87
86
95
96
97
98
99
100
101
38
58
91
Figure C-4. National (102-Key) Keyboard Key Positions
C-4
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Technical Reference Guide
Keyboard
C.2.3.2 Windows Enhanced Keyboards
1
18
17
2
3
4
5
19
20
21
22
41
40
39
59
75
92
61
60
45
44
93
110
47
46
27
48
67
66
81
80
9
26
25
65
64
79
78
24
23
63
62
77
76
43
42
8
7
6
94
11
28
29
50
49
68
83
82
10
30
51
14
15
16
32
33
34
35
36
37
52
53
54
55
56
57
72
73
74
88
89
90
71
87
86
85
95
13
31
70
69
84
12
96
111 112
97
98
99
100
101
38
58
91
Figure C-5. U.S. English Windows (101W-Key) Keyboard Key Positions
1
17
39
59
75
92
18
2
3
4
5
19
20
21
22
40
41
60
61
77
104 76
110
43
42
93
62
78
24
23
45
44
63
79
80
94
47
46
81
9
26
25
65
64
8
7
6
66
82
27
48
67
11
28
29
50
49
68
83
10
84
95
69
12
13
31
51
71
14
15
16
32
33
34
35
36
37
52
53
54
55
56
57
72
73
74
88
89
90
70 103
85
111 112
87
86
96
97
98
99
100
101
38
58
91
Figure C-6. National Windows (102W-Key) Keyboard Key Positions
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C-5
Keyboard
C.2.3.3 Easy Access Keyboard
The Easy Access keyboard is a Windows Enhanced-type keyboard that includes special buttons
allowing quick internet navigation. The Easy Access Keyboard uses the PS/2-type connection.
Btn 1
Btn 2
Btn 3
Btn 4
Btn 5 Btn 6 Btn 7
Btn 8
✎ Main key positions same as Windows Enhanced (Figures C-5 or C-6).
Figure C-7. 8-Button Easy Access Keyboard Layout
C-6
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Technical Reference Guide
Keyboard
C.2.4 Keys
All keys generate a Make code (when pressed) and a Break code (when released) with the
exception of the Pause key (pos. 16), which produces a Make code only. All keys with the
exception of the Pause and Easy Access keys are also typematic, although the typematic action
of the Shift, Ctrl, Alt, Num Lock, Scroll Lock, Caps Lock, and Ins keys is suppressed by
the BIOS. Typematic keys, when held down longer than 500 ms, send the Make code repetitively
at a 10-12 Hz rate until the key is released. If more than one key is held down, the last key
pressed will be typematic.
C.2.4.1 Special Single-Keystroke Functions
The following keys provide the intended function in most applications and environments.
Caps Lock—The Caps Lock key (pos. 59), when pressed and released, invokes a BIOS routine
that turns on the caps lock LED and shifts into upper case key positions 40-49, 60-68, and 76-82.
When pressed and released again, these keys revert to the lower case state and the LED is turned
off. Use of the Shift key will reverse which state these keys are in based on the Caps Lock key.
Num Lock—The Num Lock key (pos. 32), when pressed and released, invokes a BIOS routine
that turns on the num lock LED and shifts into upper case key positions 55-57, 72-74, 88-90,
100, and 101. When pressed and released again, these keys revert to the lower case state and the
LED is turned off.
The following keys provide special functions that require specific support by the application.
Print Scrn—The Print Scrn (pos. 14) key can, when pressed, generate an interrupt that initiates
a print routine. This function may be inhibited by the application.
Scroll Lock—The Scroll Lock key (pos. 15) when pressed and released, invokes a BIOS
routine that turns on the scroll lock LED and inhibits movement of the cursor. When pressed and
released again, the LED is turned off and the function is removed. This keystroke is always
serviced by the BIOS (as indicated by the LED) but may be inhibited or ignored by the
application.
Pause—The Pause (pos. 16) key, when pressed, can be used to cause the keyboard interrupt to
loop, i.e., wait for another key to be pressed. This can be used to momentarily suspend an
operation. The key that is pressed to resume operation is discarded. This function may be ignored
by the application.
The Esc, Fn (function), Insert, Home, Page Up/Down, Delete, and End keys operate at the
discretion of the application software.
C.2.4.2 Multi-Keystroke Functions
Shift—The Shift key (pos. 75/86), when held down, produces a shift state (upper case) for keys
in positions 17-29, 30, 39-51, 60-70, and 76-85 as long as the Caps Lock key (pos. 59) is
toggled off. If the Caps Lock key is toggled on, then a held Shift key produces the lower
(normal) case for the identified pressed keys. The Shift key also reverses the Num Lock state of
key positions 55-57, 72, 74, 88-90, 100, and 101.
Ctrl—The Ctrl keys (pos. 92/96) can be used in conjunction with keys in positions 1-13, 16,
17-34, 39-54, 60-71, and 76-84. The application determines the actual function. Both Ctrl key
positions provide identical functionality. The pressed combination of Ctrl and Break (pos. 16)
results in the generation of BIOS function INT 1Bh. This software interrupt provides a method of
exiting an application and generally halts execution of the current program.
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C-7
Keyboard
Alt—The Alt keys (pos. 93/95) can be used in conjunction with the same keys available for use
with the Ctrl keys with the exception that position 14 (SysRq) is available instead of position 16
(Break). The Alt key can also be used in conjunction with the numeric keypad keys (pos. 55-57,
72-74, and 88-90) to enter the decimal value of an ASCII character code from 1-255. The
application determines the actual function of the keystrokes. Both Alt key positions provide
identical functionality. The combination keystroke of Alt and SysRq results in software
interrupt 15h, AX=8500h being executed. It is up to the application to use or not use this BIOS
function.
The Ctrl and Alt keys can be used together in conjunction with keys in positions 1-13, 17-34,
39-54, 60-71, and 76-84. The Ctrl and Alt key positions used and the sequence in which they are
pressed make no difference as long as they are held down at the time the third key is pressed. The
Ctrl, Alt, and Delete keystroke combination (required twice if in the Windows environment)
initiates a system reset (warm boot) that is handled by the BIOS.
C.2.4.3 Windows Keystrokes
Windows-enhanced keyboards include three additional key positions. Key positions 110 and 111
(marked with the Windows logo
) have the same functionality and are used by themselves or
in combination with other keys to perform specific “hot-key” type functions for the Windows
operating system. The defined functions of the Windows logo keys are listed as follows:
Keystroke
Function
Window Logo
Open Start menu
Window Logo + F1
Display pop-up menu for the selected object
Window Logo + TAB
Activate next task bar button
Window Logo + E
Explore my computer
Window Logo + F
Find document
Window Logo + CTRL + F
Find computer
Window Logo + M
Minimize all
Shift + Window Logo + M
Undo minimize all
Window Logo + R
Display Run dialog box
Window Logo + PAUSE
Perform system function
Window Logo + 0-9
Reserved for OEM use (see following text)
The combination keystroke of the Window Logo + 1-0 keys are reserved for OEM use for
auxiliary functions (speaker volume, monitor brightness, password, etc.).
Key position 112 (marked with an application window icon
keys for invoking Windows application functions.
C-8
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) is used in combination with other
Technical Reference Guide
Keyboard
C.2.4.4 Easy Access Keystrokes
The Easy Access keyboards(Figures C-7) include additional keys (also referred to as buttons)
used to streamline internet access and navigation.
These buttons, which can be re-programmed to provide other functions, have the default
functionality described below:
8-Button Easy Access Keyboard:
Button # Description
Default Function
1
Go to favorite web site
Customer web site of choice
2
Go to AltaVista
AltaVista web site
3
Search
AltaVista search engine
4
Check Email
Launches user Email
5
Business Community
Industry specification info
6
Market Monitor
Launches Bloomberg market monitor
7
Meeting Center
Links to user’s project center
8
News/PC Lock
News retrieval service
All buttons may be re-programmed by the user through the Easy Access utility.
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C-9
Keyboard
C.2.5 Keyboard Commands
Table C-1 lists the commands that the keyboard can send to the system (specifically, to the
8042-type logic).
Table C-1.
Keyboard-to-System Commands
Command
Value
Description
Key Detection Error/Over/run
00h [1] Indicates to the system that a switch closure
FFh [2] couldn’t be identified.
BAT Completion
AAh
Indicates to the system that the BAT has been
successful.
BAT Failure
FCh
Indicates failure of the BAT by the keyboard.
Echo
EEh
Indicates that the Echo command was received by
the keyboard.
Acknowledge (ACK)
FAh
Issued by the keyboard as a response to valid
system inputs (except the Echo and Resend
commands).
Resend
FEh
Issued by the keyboard following an invalid
input.
Keyboard ID
83ABh
Upon receipt of the Read ID command from the
system, the keyboard issues the ACK command
followed by the two IDS bytes.
Note:
[1] Modes 2 and 3.
[2] Mode 1 only.
C-10
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Technical Reference Guide
Keyboard
C.2.6 Scan Codes
The scan codes generated by the keyboard processor are determined by the mode the keyboard is
operating in.
■
Mode 1: In Mode 1 operation, the keyboard generates scan codes compatible with
8088-/8086-based systems. To enter Mode 1, the scan code translation function of the
keyboard controller must be disabled. Since translation is not performed, the scan codes
generated in Mode 1 are identical to the codes required by BIOS. Mode 1 is initiated by
sending command F0h with the 01h option byte. Applications can obtain system codes and
status information by using BIOS function INT 16h with AH=00h, 01h, and 02h.
■
Mode 2: Mode 2 is the default mode for keyboard operation. In this mode, the 8042 logic
translates the make codes from the keyboard processor into the codes required by the BIOS.
This mode was made necessary with the development of the Enhanced III keyboard, which
includes additional functions over earlier standard keyboards. Applications should use BIOS
function INT 16h, with AH=10h, 11h, and 12h for obtaining codes and status data. In Mode
2, the keyboard generates the Break code, a two-byte sequence that consists of a Make code
immediately preceded by F0h (i.e., Break code for 0Eh is “F0h 0Eh”).
■
Mode 3: Mode 3 generates a different scan code set from Modes 1 and 2. Code translation
must be disabled since translation for this mode cannot be done.
NOTES:
Table C-2.
Keyboard Scan Codes
Make/Break Codes (Hex)
Key
Pos.
Legend
Mode 1
Mode 2
Mode 3
1
Esc
01/81
76/F0 76
08/na
2
F1
3B/BB
05/F0 05
07/na
3
F2
3C/BC
06/F0 06
0F/na
4
F3
3D/BD
04/F0 04
17/na
5
F4
3E/BE
0C/F0 0C
1F/na
6
F5
3F/BF
03/F0 03
27/na
7
F6
40/C0
0B/F0 0B
2F/na
8
F7
41/C1
83/F0 83
37/na
9
F8
42/C2
0A/F0 0A
3F/na
10
F9
43/C3
01/FO 01
47/na
11
F10
44/C4
09/F0 09
4F/na
12
F11
57/D7
78/F0 78
56/na
13
F12
58/D8
07/F0 07
5E/na
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C-11
Keyboard
Table C-2. (Continued)
Keyboard Scan Codes
Make/Break Codes (Hex)
Key
Pos.
Legend
Mode 1
Mode 2
Mode 3
14
Print Scrn
E0 2A E0 37/E0 B7 E0 AA
E0 37/E0 B7 [1] [2]
54/84 [3]
E0 2A E0 7C/E0 F0 7C E0 F0 12
E0 7C/E0 F0 7C [1] [2]
84/F0 84 [3]
57/na
15
Scroll Lock
46/C6
7E/F0 7E
5F/na
16
Pause
E1 1D 45 E1 9D C5/na
E0 46 E0 C6/na [3]
E1 14 77 E1 F0 14 F0 77/na
E0 7E E0 F0 7E/na [3]
62/na
17
`
29/A9
0E/F0 E0
0E/F0 0E
18
1
02/82
16/F0 16
46/F0 46
19
2
03/83
1E/F0 1E
1E/F0 1E
20
3
04/84
26/F0 26
26/F0 26
21
4
05/85
25/F0 25
25/F0 25
22
5
06/86
2E/F0 2E
2E/F0 2E
23
6
07/87
36/F0 36
36/F0 36
24
7
08/88
3D/F0 3D
3D/F0 3D
25
8
09/89
3E/F0 3E
3E/F0 3E
26
9
0A/8A
46/F0 46
46/F0 46
27
0
0B/8B
45/F0 45
45/F0 45
28
-
0C/8C
4E/F0 4E
4E/F0 4E
29
=
0D/8D
55/F0 55
55/F0 55
30
\
2B/AB
5D/F0 5D
5C/F0 5C
31
Backspace
0E/8E
66/F0 66
66/F0 66
32
Insert
E0 52/E0 D2
E0 AA E0 52/E0 D2 E0 2A [4]
E0 2A E0 52/E0 D2 E0 AA [6]
E0 70/E0 F0 70
E0 F0 12 E0 70/E0 F0 70 E0 12 [5]
E0 12 E0 70/E0 F0 70 E0 F0 12 [6]
67/na
33
Home
E0 47/E0 D2
E0 AA E0 52/E0 D2 E0 2A [4]
E0 2A E0 47/E0 C7 E0 AA [6]
E0 6C/E0 F0 6C
E0 F0 12 E0 6C/E0 F0 6C E0 12 [5]
E0 12 E0 6C/E0 F0 6C E0 F0 12 [6]
6E/na
34
Page Up
E0 49/E0 C7
E0 7D/E0 F0 7D
E0 AA E0 49/E0 C9 E0 2A [4] E0 F0 12 E0 7D/E0 F0 7D E0 12 [5]
E0 2A E0 49/E0 C9 E0 AA [6] E0 12 E0 7D/E0 F0 7D E0 F0 12 [6]
6F/na
C-12
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Technical Reference Guide
Keyboard
Table C-2. (Continued)
Keyboard Scan Codes
Make/Break Codes (Hex)
Key
Pos.
Legend
Mode 1
Mode 2
Mode 3
35
Num Lock
45/C5
77/F0 77
76/na
36
/
E0 35/E0 B5
E0 AA E0 35/E0 B5 E0 2A [1]
E0 4A/E0 F0 4A
E0 F0 12 E0 4A/E0 F0 4A E0 12 [1]
77/na
37
*
37/B7
7C/F0 7C
7E/na
38
-
4A/CA
7B/F0 7B
84/na
39
Tab
0F/8F
0D/F0 0D
0D/na
40
Q
10/90
15/F0 15
15/na
41
W
11/91
1D/F0 1D
1D/F0 1D
42
E
12/92
24/F0 24
24/F0 24
43
R
13/93
2D/F0 2D
2D/F0 2D
44
T
14/94
2C/F0 2C
2C/F0 2C
45
Y
15/95
35/F0 35
35/F0 35
46
U
16/96
3C/F0 3C
3C/F0 3C
47
I
17/97
43/F0 43
43/F0 43
48
O
18/98
44/F0 44
44/F0 44
49
P
19/99
4D/F0 4D
4D/F0 4D
50
[
1A/9A
54/F0 54
54/F0 54
51
]
1B/9B
5B/F0 5B
5B/F0 5B
52
Delete
E0 53/E0 D3
E0 AA E0 53/E0 D3 E0 2A [4]
E0 2A E0 53/E0 D3 E0 AA [6]
E0 71/E0 F0 71
E0 F0 12 E0 71/E0 F0 71 E0 12 [5]
E0 12 E0 71/E0 F0 71 E0 F0 12 [6]
64/F0 64
53
End
E0 4F/E0 CF
E0 AA E0 4F/E0 CF E0 2A [4]
E0 2A E0 4F/E0 CF E0 AA [6]
E0 69/E0 F0 69
E0 F0 12 E0 69/E0 F0 69 E0 12 [5]
E0 12 E0 69/E0 F0 69 E0 F0 12 [6]
65/F0 65
54
Page Down
E0 51/E0 D1
E0 AA E0 51/E0 D1 E0 2A [4]
E0 @a E0 51/E0 D1 E0 AA [6]
E0 7A/E0 F0 7A
E0 F0 12 E0 7A/E0 F0 7A E0 12 [5]
E0 12 E0 7A/E0 F0 7A E0 F0 12 [6]
6D/F0 6D
55
7
47/C7 [6]
6C/F0 6C [6]
6C/na [6]
56
8
48/C8 [6]
75/F0 75 [6]
75/na [6]
57
9
49/C9 [6]
7D/F0 7D [6]
7D/na [6]
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C-13
Keyboard
Table C-2. (Continued)
Keyboard Scan Codes
Make/Break Codes (Hex)
Key
Pos.
Legend
Mode 1
Mode 2
Mode 3
58
+
4E/CE [6]
79/F0 79 [6]
7C/F0 7C
59
Caps Lock
3A/BA
58/F0 58
14/F0 14
60
A
1E/9E
1C/F0 1C
1C/F0 1C
61
S
1F/9F
1B/F0 1B
1B/F0 1B
62
D
20/A0
23/F0 23
23/F0 23
63
F
21/A1
2B/F0 2B
2B/F0 2B
64
G
22/A2
34/F0 34
34/F0 34
65
H
23/A3
33/F0 33
33/F0 33
66
J
24/A4
3B/F0 3B
3B/F0 3B
67
K
25/A5
42/F0 42
42/F0 42
68
L
26/A6
4B/F0 4B
4B/F0 4B
69
;
27/A7
4C/F0 4C
4C/F0 4C
70
‘
28/A8
52/F0 52
52/F0 52
71
Enter
1C/9C
5A/F0 5A
5A/F0 5A
72
4
4B/CB [6]
6B/F0 6B [6]
6B/na [6]
73
5
4C/CC [6]
73/F0 73 [6]
73/na [6]
74
6
4D/CD [6]
74/F0 74 [6]
74/na [6]
75
Shift (left)
2A/AA
12/F0 12
12/F0 12
76
Z
2C/AC
1A/F0 1A
1A/F0 1A
77
X
2D/AD
22/F0 22
22/F0 22
78
C
2E/AE
21/F0 21
21/F0 21
79
V
2F/AF
2A/F0 2A
2A/F0 2A
80
B
30/B0
32/F0 32
32/F0 32
81
N
31/B1
31/F0 31
31/F0 31
82
M
32/B2
3A/F0 3A
3A/F0 3A
83
,
33/B3
41/F0 41
41/F0 41
84
.
34/B4
49/F0 49
49/F0 49
C-14
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Technical Reference Guide
Keyboard
Table C-2. (Continued)
Keyboard Scan Codes
Make/Break Codes (Hex)
Key
Pos.
Legend
Mode 1
Mode 2
Mode 3
85
/
35/B5
4A/F0 4A
4A/F0 4A
86
Shift (right)
36/B6
59/F0 59
59/F0 59
87
E0 48/E0 C8
E0 75/E0 F0 75
E0 AA E0 48/E0 C8 E0 2A [4] E0 F0 12 E0 75/E0 F0 75 E0 12 [5]
E0 2A E0 48/E0 C8 E0 AA [6] E0 12 E0 75/E0 F0 75 E0 F0 12 [6]
63/F0 63
88
1
4F/CF [6]
69/F0 69 [6]
69/na [6]
89
2
50/D0 [6]
72/F0 72 [6]
72/na [6]
90
3
51/D1 [6]
7A/F0 7A [6]
7A/na [6]
91
Enter
E0 1C/E0 9C
E0 5A/F0 E0 5A
79/F0
79[6]
92
Ctrl (left)
1D/9D
14/F0 14
11/F0 11
93
Alt (left)
38/B8
11/F0 11
19/F0 19
94
(Space)
39/B9
29/F0 29
29/F0 29
95
Alt (right)
E0 38/E0 B8
E0 11/F0 E0 11
39/na
96
Ctrl (right)
E0 1D/E0 9D
E0 14/F0 E0 14
58/na
97
E0 4B/E0 CB
E0 AA E0 4B/E0 CB E0 2A [4]
E0 2A E0 4B/E0 CB E0 AA [6]
E0 6B/Eo F0 6B
E0 F0 12 E0 6B/E0 F0 6B E0 12[5]
E0 12 E0 6B/E0 F0 6B E0 F0 12[6]
61/F0 61
98
E0 50/E0 D0
E0 72/E0 F0 72
E0 AA E0 50/E0 D0 E0 2A [4] E0 F0 12 E0 72/E0 F0 72 E0 12[5]
E0 2A E0 50/E0 D0 E0 AA [6] E0 12 E0 72/E0 F0 72 E0 F0 12[6]
60/F0 60
99
E0 4D/E0 CD
E0 74/E0 F0 74
E0 AA E0 4D/E0 CD E0 2A [4] E0 F0 12 E0 74/E0 F0 74 E0 12[5]
E0 2A E0 4D/E0 CD E0 AA [6] E0 12 E0 74/E0 F0 74 E0 F0 12[6]
6A/F0 6A
100
0
52/D2 [6]
70/F0 70 [6]
70/na [6]
101
.
53/D3 [6]
71/F0 71 [6]
71/na [6]
102
na
7E/FE
6D/F0 6D
7B/F0 7B
103
na
2B/AB
5D/F0 5D
53/F0 53
104
na
36/D6
61/F0 61
13/F0 13
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C-15
Keyboard
Table C-2. (Continued)
Keyboard Scan Codes
Key
Pos.
Make/Break Codes (Hex)
Legend
Mode 1
Mode 2
Mode 3
110
(Win95) [7] E0 5B/E0 DB
E0 AA E0 5B/E0 DB E0 2A [4]
E0 2A E0 5B/E0 DB E0 AA [6]
E0 1F/E0 F0 1F
E0 F0 12 E0 1F/E0 F0 1F E0 12 [5]
E0 12 E0 1F/E0 F0 1F E0 F0 12 [6]
8B/F0 8B
111
(Win95) [7] E0 5C/E0 DC
E0 2F/E0 F0 27
E0 AA E0 5C/E0 DC E0 2A [4] E0 F0 12 E0 27/E0 F0 27 E0 12 [5]
E0 2A E0 5C/E0 DC E0 AA [6] E0 12 E0 27/E0 F0 27 E0 F0 12 [6]
8C/F0 8C
112
(Win Apps)
[7]
E0 5D/E0 DD
E0 2F/E0 F0 2F
E0 AA E0 5D/E0 DD E0 2A [4] E0 F0 12 E0 2F/E0 F0 2F E0 12 [5]
E0 2A E0 5D E0 DD E0 AA [6] E0 12 E0 2F/E0 F0 2F E0 F0 12 [6
8D/F0 8D
Btn 1
[8]
E0 1E/E0 9E
E0 1C/E0 F0 1C
95/F0 95
Btn 2
[8]
E0 26/E0 A6
E0 4B/E0 F0 4B
9C/F0 9C
Btn 3
[8]
E0 25/E0 A5
E0 42/E0 F0 42
9D/F0 9D
Btn 4
[8]
E0 23/E0 A3
E0 33/E0 F0 33
9A/F0 9A
Btn 5
[8]
E0 21/E0 A1
E0 2B/E0 F0 2B
99/F0 99
Btn 6
[8]
E0 12/E0 92
E0 24/E0 F0 24
96/F0 96
Btn 7
[8]
E0 32/E0 B2
E0 3A/E0 F0 3A
97/F0 97
Btn 1
[9]
E0 23/E0 A3
E0 33/E0 F0 33
9A/F0 9A
Btn 2
[9]
E0 1F/E0 9F
E0 1B/E0 F0 1B
80/F0 80
Btn 3
[9]
E0 1A/E0 9A
E0 54/E0 F0 54
99/F0 99
Btn 4
[9]
E0 1E/E0 9E
E0 1C/E0 F0 1C
95/F0 95
Btn 5
[9]
E0 13/E0 93
E0 2D/E0 F0 2D
0C/F0 0C
Btn 6
[9]
E0 14/E0 94
E0 2C/E0 F0 2C
9D/F0 9D
Btn 7
[9]
E0 15/E0 95
E0 35/E0 F0 35
96/F0 96
Btn 8
[9]
E0 1B/E0 9B
E0 5B/E0 F0 5B
97/F0 97
All codes assume Shift, Ctrl, and Alt keys inactive unless otherwise noted.
NA = Not applicable
[1] Shift (left) key active.
[2] Ctrl key active.
[3] Alt key active.
[4] Left Shift key active. For active right Shift key, substitute AA/2A make/break codes for B6/36 codes.
[5] Left Shift key active. For active right Shift key, substitute F0 12/12 make/break codes for F0 59/59 codes.
[6] Num Lock key active.
[7] Windows keyboards only.
[8] 7-Button Easy Access keyboard.
[9] 8-Button Easy Access keyboard.
C-16
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Technical Reference Guide
Keyboard
C.3 Connectors
Two types of keyboard interfaces may be used in HP/Compaq systems: PS/2-type and USB-type.
System units that provide a PS/2 connector will ship with a PS/2-type keyboard but may also
support simultaneous connection of a USB keyboard. Systems that do not provide a PS/2
interface will ship with a USB keyboard. For a detailed description of the PS/2 and USB
interfaces refer to Chapter 5 “Input/Output” of this guide. The keyboard cable connectors and
their pinouts are described in the following figures:
5
6
3
4
1
2
Pin
Function
1
Data
2
Not connected
3
Ground
4
+5 VDC
5
Clock
6
Not connected
Figure C-9. PS/2 Keyboard Cable Connector (Male)
4
3
Pin
Function
1
+5 VDC
2
Data (-)
3
Data (+)
4
Ground
2
1
Figure C-10. USB Keyboard Cable Connector (Male)
Technical Reference Guide
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C-17
Keyboard
C-18
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Technical Reference Guide
Index
Numerics
8259 Mode 4-12
A
Advanced Digital Display (ADD2) 6-2
APIC Mode 4-13
audible (beep) indications 4-23
audio codec 5-32
Audio Specifications 5-32
B
BIOS upgrading 8-2
boot device order 8-3
Boot Error Codes 8-5
C
CMOS 4-19
CMOS, clearing 4-19
Computer Setup (Utility)8-6
configuration memory 4-19
D
Direct Memory Access (DMA) 4-16
Diskette Drive Connector 5-8
diskette drive interface 5-4
F
G
graphics subsystem 6-1
H
HD Audio Controller 5-28
header pinouts 7-14
I
I/O map 4-24
Technical Reference Guide
integrated graphics controller (IGC). 6-2
interrupts, hardware 4-11
interrupts, PCI 4-13
K
keyboard interface 5-15
L
LED indications, systemm status 4-23, 8-5
M
Memory 3-4
memory allocation (video) 6-3
memory map 3-7
model numbering 1-2
mouse (pointing device) interface 5-18
N
Network Boot 8-4
Network Interface Controller 5-15
P
parallel interface 5-11
Parallel Interface Connector 5-14
password, Setup 4-21
PCI 2.3 4-2
PCI Express 4-6
Pentium 4 processor 3-2
power states 7-7
Processor Upgrading 3-3
R
Real-time clock (RTC) 4-19
ROM flashing 8-2
S
SATA 5-1
SATA Connector 5-3
SDVO 6-2
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Index-1
Index
serial interface 5-9
Serial Interface Connector 5-9
serial number 1-3
Setup utility 8-6
Smart Cover Lock 4-22
Smart (hood) Cover Sensor 2-2, 4-21
SMBIOS 8-17
SPD address map 3-7
specifications
physical 2-26
system ID 8-16
T
Temperature Status 8-16
U
Universal Serial Bus (USB) interface 5-22
upgrading BIOS 8-2
upgrading graphics 6-5
USB 5-22
V
VGA connector 6-6
W
Web sites
Adobe Systems, Inc. 1-1
HP 1-1
Intel Corporation 1-1
Standard Microsystems Corporation 1-1
USB user group 1-1
Index-2
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Technical Reference Guide