Differences between M16C/62P and M32C/84

APPLICATION NOTE
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
1.
Abstract
The following document describes differences between M16C/62P 128-pin version and M32C/84 144-pin
version. Refer to each device’s hardware manual or software manual for details.
2.
Introduction
The explanation of this issue is applied to the following condition:
Applicable MCU: M16C/62P 128-pin version, M32C/84 144-pin version
REJ05B1104-0110/Rev.1.10
Dec 2007
Page 1 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
3.
Differences Outline
3.1 Differences Outline of Functions
Table 3.1.1 lists the differences of functions.
Table 3.1.1 Differences of Functions (1)
Item
M16C/62P
M32C/84
Basic Instructions
91 instructions
108 instructions
Minimum Instruction
41.7ns(f(BCLK) = 24MHz, VCC1 = 3.0 V to 5.5 V)
31.3ns(f(BCLK) = 32MHz, VCC1 = 4.2 V to 5.5 V)
Execution Time
100ns(f(BCLK) = 10MHz, VCC1 = 2.7 V to 5.5 V)
41.7ns(f(BCLK) = 24MHz, VCC1 = 3.0 V to 5.5 V)
Address Space
1-Mbyte (Available to 4 Mbytes by memory space
16-Mbyte
expansion function)
I/O Port
I/O Port: 113, Input Port: 1
I/O Port: 123, Input Port: 1
Intelligent I/O
N/A
Time measurement function: 16 bits x 8 channels
Waveform generating function: 16 bits x 8 channels
Communication function (Clock synchronous serial I/O,
Clock asynchronous serial I/O, HDLC data processing)
Serial Interface
3 channels
Clock synchronous serial I/O
Clock asynchronous serial I/O
2
I C bus, IEBus
5 channels
Clock synchronous serial I/O
Clock asynchronous serial I/O
2
I C bus
(2)
IEBus (optional)
2 channels
(2) (3)
Clock synchronous serial I/O
CAN Module
N/A
1 channels
A/D Converter
10-bit A/D converter: 1 circuit, 26 channels
10-bit A/D converter: 1 circuit, 34 channels
DMAC
2 channels
4 channels
DMAC II
N/A
Available
X/Y Converter
N/A
16 bits x 16 bits
Interrupt
29 internal and 8 external sources, 4 software sources 38 internal and 8 external sources, 5 software sources
Oscillation Stop Detect
Stop detection of main clock oscillation, re-oscillation
Stop detection of main clock oscillation
Function
detection function
Supply Voltage
VCC1 = 3.0 V to 5.5 V, VCC2 = 2.7 V toVCC1
VCC1 = 4.2 V to 5.5 V, VCC2 = 3.0 V to VCC1
(f(BCLK) = 24MHz)
(f(BCLK) = 32MHz)
VCC1 = 2.7 V to 5.5 V, VCC2 = 2.7 V to VCC1
VCC1 = 3.0 V to 5.5 V, VCC2 = 3.0 V to VCC1
(f(BCLK) = 10MHz)
(f(BCLK) = 24MHz)
14mA(VCC1 = VCC2 = 5 V, f(BCLK) = 24MHz)
28mA(VCC1 = VCC2 = 5 V, f(BCLK) = 32MHz)
8mA(VCC1 = VCC2 = 3 V, f(BCLK) = 10MHz)
22mA(VCC1 = VCC2 = 3.3 V, f(BCLK) = 24MHz)
2.0μA(VCC1 = VCC2 = 5 V, f(XCIN) = 32kHz, wait mode)
10μA(VCC1 = VCC2 = 5 V, f(BCLK) = 32kHz, wait mode)
0.8μA(VCC1 = VCC2 = 5 V, stop mode)
0.8μA(VCC1 = VCC2 = 5 V, stop mode)
Program and Erase
100 times (all area)
100 times (all area)
Endurance
or 1,000 times (user ROM area without block A and
Power Consumption
block 1) / 10,000 times (block A, block 1)
NOTES:
1. Refer to hardware manual for Electrical Characteristics and details.
2. IEBus is a trademark of NEC Electronics Corporation.
3. Please contact a Renesas sales office for optional features.
REJ05B1104-0110/Rev.1.10
December 2007
Page 2 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
3.2 Differences of Pin Characteristics
Tables 3.2.1 and 3.2.2 list the differences of pin characteristics.
Table 3.2.1 Differences of Pin Characteristics (1/2)
M16C/62P
______________
M32C/84
______________
Differences from M16C/62P
Add RXD4/SCL4/STXD4
Delete SIN4
Add TXD4/SDA4/SRXD4
Delete SOUT4
P9_7/SIN4/ADTRG
P9_7/RXD4/SCL4/STXD4/ADTRG
P9_6/SOUT4/ANEX1
P9_6/TXD4/SDA4/SRXD4/ ANEX1
P9_4/TB4IN/DA1
P9_4/TB4IN/CTS4 /RTS4 /S S 4 /DA1
P9_3/TB3IN/DA0
P9_2/TB2IN/SOUT3
P9_3/TB3IN/CTS3 /RTS3 /S S 3 /DA0
P9_2/TB2IN/TXD3/SDA3/SRXD3
P9_1/TB1IN/SIN3
P9_1/TB1IN/RXD3/SCL3/STXD3
P14_1
P14_1/INPC1_5/OUTC1_5
Add CTS3 /RTS3 /S S 3
Add TXD3/SDA3/SRXD3
Delete SOUT3
Add RXD3/SCL3/STXD3
Delete SIN3
Add INPC1_5/OUTC1_5
P14_0
P14_0/INPC1_4/OUTC1_4
Add INPC1_4/OUTC1_4
________
P8_4/INT2/ZP
________
__________ __________ ________
__________ __________ ________
________
ZP is shared with INT2
Add CAN0IN
P8_3/INT1/CAN0IN
________
________
P8_2/INT0
P8_2/INT0/CAN0OUT
___
__________ __________ ________
________
P8_4/INT2
________
P8_3/INT1
__________ __________ ________
Add CTS4 /RTS4 /S S 4
___
Add CAN0OUT
P8_1/TA4IN/U
P8_0/TA4OUT/U
P8_1/TA4IN/U /INPC1_5/OUTC1_5
P8_0/TA4OUT/U/ISRXD0
Add INPC1_5/OUTC1_5
P7_7/TA3IN
P7_7/TA3IN/CAN0IN/INPC1_4/OUTC1_4/ISCLK0
Add CAN0IN/INPC1_4/OUTC1_4/ISCLK0
P7_6/TA3OUT
P7_6/TA3OUT/ CAN0OUT/INPC1_3/
OUTC1_3/ISTXD0
Add CAN0OUT/INPC1_3/OUTC1_3/ISTXD0
____
Add ISRXD0
P7_5/TA2IN/W
____
P7_5/TA2IN/W /INPC1_2/OUTC1_2/ISRXD1/BE1IN Add INPC1_2/OUTC1_2/ISRXD1/BE1IN
P7_4/TA2OUT/W
P7_4/TA2OUT/W/ INPC1_1/OUTC1_1/ISCLK1
___ __________ __________
P7_3/TA1IN/V /CTS2 /RTS2
P7_1/TA0IN/TB5IN/RXD2/SCL2
P7_0/TA0OUT/TXD2/SDA2
P6_7/TXD1/SDA1
P6_6/RXD1/SCL1
__________ __________ __________
P6_4/CTS1 /RTS1 /CTS0 /CLKS1
___ __________ __________ ________
P7_3/TA1IN/V /CTS2 /RTS2 /S S 2 /INPC1_0/
OUTC1_0/ISTXD1/BE1OUT
P7_1/TB5IN/TA0IN/RXD2/SCL2/STXD2/
INPC1_7/OUTC1_7
P7_0/TA0OUT/TXD2/SDA2/SRXD2/
INPC1_6/OUTC1_6
P6_7/TXD1/SDA1/SRXD1
P6_6/RXD1/SCL1/STXD1
__________ __________ ________
Add INPC1_1/OUTC1_1/ISCLK1
________
Add S S 2 /INPC1_0/OUTC1_0/ISTXD1/BE1OUT
Add STXD2/INPC1_7/OUTC1_7/
Add SRXD2/INPC1_6/OUTC1_6
Add SRXD1
Add STXD1
________
P6_4/CTS1 /RTS1 /S S 1
Add S S 1
P6_3/TXD0/SDA0/SRXD0
P6_2/RXD0/SCL0/STXD0
Delete CTS0 /CLKS1
Add SRXD0
Add STXD0
__________
P6_3/TXD0/SDA0
P6_2/RXD0/SCL0
__________ __________
P6_0/CTS0 /RTS0
________
P5_7/RDY/CLKOUT
___________
P5_4/HLDA
P5_3/BCLK
_______
P4_7/CS3
__________ __________ ________
P6_0//CTS0 /RTS0 /S S 0
________
P5_7/RDY
___________
P5_4/HLDA /ALE
P5_3/CLKOUT/BCLK/ALE
_______ _______
________
Add S S 0
Delete CLKOUT
Add ALE
Add CLKOUT/ALE
_______ _______
P4_7/CS0/A23
Add CS0/A23
_______
Delete CS3
_______
P4_6/CS2
_______
_______
P4_6/CS1/A22
Add CS1/A22
_______
Delete CS2
_______
P4_5/CS1
_______
_______
P4_5/CS2/A21
Add CS2/A21
_______
Delete CS1
_______
P4_4/CS0
_______
_______
P4_4/CS3/A20
Add CS3/A20
P3_7/A15(/D15)
P3_6/A14(/D14)
P3_5/A13(/D13)
P3_4/A12(/D12)
P3_3/A11(/D11)
P3_2/A10(/D10)
P3_1/A9(/D9)
Delete CS0
Add /D15
Add /D14
Add /D13
Add /D12
Add /D11
Add /D10
Add /D9
_______
P3_7/A15
P3_6/A14
P3_5/A13
P3_4/A12
P3_3/A11
P3_2/A10
P3_1/A9
REJ05B1104-0110/Rev.1.10
December 2007
Page 3 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
Table 3.2.2 Differences of Pin Characteristics (2/2)
M16C/62P
P3_0/A8(/-/D7)
P2_7/AN2_7/A7(/D7/D6)
P2_6/AN2_6/A6(/D6/D5)
P2_5/AN2_5/A5(/D5/D4)
P2_4/AN2_4/A4(/D4/D3)
P2_3/AN2_3/A3(/D3/D2)
P2_2/AN2_2/A2(/D2/D1)
P2_1/AN2_1/A1(/D1/D0)
P2_0/AN2_0/A0(/D0/-)
P11_7
P11_6
P11_5
P11_3
P11_2
P11_1
P11_0
-
REJ05B1104-0110/Rev.1.10
M32C/84
P3_0/A8(/D8)
P2_7/AN2_7/A7(/D7)
P2_6/AN2_6/A6(/D6)
P2_5/AN2_5/A5(/D5)
P2_4/AN2_4/A4(/D4)
P2_3/AN2_3/A3(/D3)
P2_2/AN2_2/A2(/D2)
P2_1/AN2_1/A1(/D1)
P2_0/AN2_0/A0(/D0)
-
P11_3/INPC1_3/OUTC1_3
P11_2/INPC1_2/OUTC1_2/ISRXD1/BE1IN
P11_1/INPC1_1/OUTC1_1/ISCLK1
P11_0/INPC1_0/OUTC1_0/ISTXD1/BE1OUT
P14_6
P14_5
P14_4
P14_3/INPC1_7/OUTC1_7
P14_2/INPC1_6/OUTC1_6
P15_7/AN15_7
P15_6/AN15_6
P15_5/AN15_5
P15_4/AN15_4
P15_3/AN15_3
P15_2/ISRXD0/AN15_2
P15_1/ISCLK0/AN15_1
P15_0/ISTXD0/AN15_0
December 2007
Differences from M16C/62P
Add /D8
Delete /-/D7
Delete /D6
Delete /D5
Delete /D4
Delete /D3
Delete /D2
Delete /D1
Delete /D0
Delete /Only M16C/62P
Add INPC1_3/OUTC1_3
Add INPC1_2/OUTC1_2/ISRXD1/BE1IN
Add INPC1_1/OUTC1_1/ISCLK1
Add INPC1_0/OUTC1_0/ISTXD1/BE1OUT
Only M32C/84
Page 4 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
4.
Detailed Differences
4.1 Differences of CPU Functions
Table 4.1.1 lists the differences of Instructions, Table 4.1.2 lists the differences of CPU registers, and Table
4.1.3 lists the differences of register banks.
Table 4.1.1 Differences of Instructions
Item
Additional Instructions
-
M16C/62P
Deleted Instructions
-
Bit Operation
Register bit 0 to 15 can be operated
BSET bit, R0 (bit 0 to 15)
M32C/84
ADDX, BITINDEX, BRK2,
CLIP, CMPX, EXTZ, FREIT,
INDEXcnd, MAX, MIN,
MOVX, MULEX, SCcnd,
SCMPU, SHANC, SHLNC, SIN,
SMOVU, SOUT, SUBX
LDE (use MOV instruction)
STE (use MOV instruction)
LDINTB (use LDC #IMM, INTB)
Register bit 0 to 7 can be operated
BSET bit, R0L (bit 0 to 7)
BSET bit, R0H (bit 0 to 7)
Table 4.1.2 Differences of Bit Length
Internal register
Address register
M16C/62P
A0, A1
Static base register
SB
Frame base register
FB
User stack pointer
USP
M32C/84
16 bit
24 bit
Interrupt stack pointer
ISP
Interrupt table register
INTB
20 bit
24 bit
INTBL
16 bit
-
INTBH
4 bit
-
Program counter
PC
20 bit
24 bit
High-speed interrupt register
SVF
-
16 bit
SVP
-
16 bit
VCT
-
24 bit
DMD0, DMD1
-
8 bit
(When using three or more DMAC channels, DCT0, DCT1,
-
16 bit
-
16 bit
-
24 bit
-
24 bit
-
24 bit
DMAC associated register
Register bank 1 and high-speed interrupt
DCT2(R0), DCT3(R1)
register are extended for use as DMAC
DRC0, DRC1,
register)
DRC2(R2), DRC3(R3)
DMA0, DMA1,
DMA2(A0), DMA3(A1)
DRA0, DRA1,
DRA2(SVP), DRA3(VCT)
DSA0, DSA1,
DSA2(SB), DSA3(FB)
Table 4.1.3 Differences of Register Banks
Internal register
Static base register
M16C/62P
SB
Register bank 0
M32C/84
Register bank 0
Register bank 1
REJ05B1104-0110/Rev.1.10
December 2007
Page 5 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
4.2 Differences of Reset
There are five kinds of reset which are hardware reset 1, low voltage detection reset (hardware reset 2),
software reset, watchdog timer reset, and oscillation stop detection reset (only M16C/62P). Some of SFR
maintain values set before reset, even after each reset has been performed. Table 4.2.1 lists details.
Table 4.2.1 Register Maintaining Values Even after Reset
Kind of reset
Register
Hardware reset 1
PUR1
WDC
PUR1
Low voltage detection reset
(Hardware reset 2)
WDC
PM0
VCR1
VCR2
PUR1
Software reset
TCSPR
WDC
PM0
VCR1
VCR2
PUR1
Watchdog timer reset
TCSPR
WDC
PM0
Oscillation stop detection reset
CM2
VCR1
VCR2
PUR1
WDC
Value after reset
M16C/62P
M32C/84
Initialized regardless of the
Varies according to CNVSS level
CNVSS level
00h (CNVSS pin "L")
02h (CNVSS pin "H")
WDC5 bit is not initialized
Varies according to CNVSS level
Initialized regardless of the
00h (CNVSS pin "L")
CNVSS level
02h (CNVSS pin "H")
WDC5 bit is not initialized
Bits PM01 and PM00 are not initialized
Not initialized
Initialized
Not initialized
Initialized
Initialized regardless of the
Varies according to the value of
CNVSS level
registers PM01 and PM00
00h (PM01, PM00 = 00b)
02h (PM01, PM00 = 01b)
02h (PM01, PM00 = 11b)
Not initialized
WDC5 bit is not initialized
Bits PM01 and PM00 are not initialized
Not initialized
Initialized
Not initialized
Initialized
Initialized regardless of the
Varies according to the value of
CNVSS level
registers PM01 and PM00
00h (PM01, PM00 = 00b)
02h (PM01, PM00 = 01b)
02h (PM01, PM00 = 11b)
Not initialized
WDC5 bit is not initialized
Bits PM01 and PM00 are not
initialized
Bits CM20, CM21 and CM27 are not initialized
Not initialized
Not initialized
Varies according to the value of
registers PM01 and PM00
00h (PM01, PM00 = 00b)
02h (PM01, PM00 = 01b)
02h (PM01, PM00 = 11b)
WDC5 bit is not initialized
-
4.3 Differences of Low Voltage Detection Circuit
Table 4.3.1 lists the differences of low voltage detection circuit associated SFR.
Table 4.3.1 Differences of Low Voltage Detection Circuit associated SFR
Symbol
Address
M16C/62P
M32C/84
VCR1
0019h
001Bh
VCR2
001Ah
0017h
D4INT
001Fh
002Fh
REJ05B1104-0110/Rev.1.10
bit
Differences
M16C/62P
-
Different address
-
Different address
1
STOP Mode Deactivation Control
6-7 Nothing is assigned.
December 2007
M32C/84
STOP/WAIT Mode Deactivation Control
Reserved bit
Page 6 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
4.4 Differences of Processor Mode
Table 4.4.1 lists the differences of processor mode associated SFR.
Table 4.4.1 Differences of Processor Mode associated SFR
Symbol
PM0
Address
M16C/62P
M32C/84
0004h
0004h
PM1
0005h
0005h
Differences
bit
M16C/62P
6 Ports P4_0 to P4_3 Function Select
7 BCLK Output Disable
0 CS2 Area Switch
1 Ports P3_7 to P3_4 Function Select
2 Watchdog Timer Function Select
3 Internal Reserved Area Expansion
4-5 Memory Area Expansion
7 Wait Bit
M32C/84
Reserved bit
BCLK Output Disable
External Memory Space Mode
Internal Memory Wait
SFR Area Wait
ALE Pin Select
Reserved bit
4.5 Differences of Bus
Table 4.5.1 lists the Differences of bus, Table 4.5.2 lists the Differences of bus setting, Table 4.5.3 lists the
Differences of bus control pin, and Table 4.5.4 lists the Differences of bus associated SFR.
Table 4.5.1 Differences of Bus
Item
Address space
Address bus width
M16C/62P
1-Mbyte / 4-Mbyte (refer to memory space
expansion function)
12 bit / 16bit / 20bit
M32C/84
16-Mbyte
24 bit fixed
External Area wait
1 to 3 waits
1 to 7 waits
Recovery Cycle Addition
N/A
Available
Page Mode
N/A
Available (Only ROMless version)
SFR Area wait number
1 wait / 2 waits (at PLL operation)
1 wait / 2 waits
Table 4.5.2 Differences of Bus Setting
Item
Address bus width
M16C/62P
M32C/84
PM06 bit in the PM0 register
-
PM11 bit in the PM1 register
Data bus width
Set bus width in all area
Set bus width per external space
BYTE pin
Bits DS0 to DS3 in the DS register
"H" : 8 bit bus width
0 : 8 bit bus width
"L" : 16 bit bus width
1 : 16 bit bus width
Set bus width after reset
Only the external space 3 is set by BYTE pin.
BYTE pin
"H" : 8 bit bus width
"L" : 16 bit bus width
Chip select signal
Csi bit (i = 0 to 3) in the CSR register
Bits PM10 and PM11 in the PM1 register
SFR Area wait number
PM20 bit in the PM2 register
PM13 bit in the PM1 register
External Area wait
CsiW bit in the CSR register
Bits EWCRi00 to EWCRi04 in the EWCRi register
Bits CSEi0 and CSEi1 in the CSE register
(i = 0 to 3)
Recovery Cycle Addition
-
EWCRi06 bit in the EWCRi register
BCLK output
PM07 bit in the PM0 register
PM07 bit in the PM0 register
Bits CM00 and CM01 in the CM0 register
REJ05B1104-0110/Rev.1.10
December 2007
Page 7 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
Table 4.5.3 Differences of Bus associated Pin
Pin name
M16C/62P
ALE
M32C/84
P5_6
P5_6
__________
P5_4/HLDA
P5_3/CLKOUT/BCLK
_______
_______
P4_4
P4_7/A23
_______
P4_5
P4_6/A22
_______
P4_6
P4_5/A21
_______
P4_7
P4_4/A20
Multiplexed bus associated
P3_7/A15
P3_7/A15(/D15)
P3_6/A14
P3_6/A14(/D14)
P3_5/A13
P3_5/A13(/D13)
P3_4/A12
P3_4/A12(/D12)
P3_3/A11
P3_3/A11(/D11)
P3_2/A10
P3_2/A10(/D10)
P3_1/A9
P3_1/A9(/D9)
P3_0/A8(/-/D7)
P3_0/A8(/D8)
P2_7/A7(/D7/D6)
P2_7/A7(/D7)
P2_6/A6(/D6/D5)
P2_6/A6(/D6)
P2_5/A5(/D5/D4)
P2_5/A5(/D5)
P2_4/A4(/D4/D3)
P2_4/A4(/D4)
P2_3/A3(/D3/D2)
P2_3/A3(/D3)
P2_2/A2(/D2/D1)
P2_2/A2(/D2)
P2_1/A1(/D1/D0)
P2_1/A1(/D1)
P2_0/A0(/D0/-)
P2_0/A0(/D0)
CS0
CS1
CS2
CS3
Table 4.5.4 Differences of Bus associated SFR
Address
Symbol
M16C/62P
M32C/84
Differences
bit
M16C/62P
M32C/84
CSR
0008h
-
-
Only M16C/62P
-
CSE
001Bh
-
-
Only M16C/62P
-
DBR
000Bh
-
-
Only M16C/62P
-
DS
-
000Bh
-
-
Only M32C/84
EWCR0
-
0048h
-
-
Only M32C/84
EWCR1
-
0049h
-
-
Only M32C/84
EWCR2
-
004Ah
-
-
Only M32C/84
EWCR3
-
004Bh
-
-
Only M32C/84
PWCR0
-
004Ch
-
-
Only M32C/84
PWCR1
-
004Dh
-
-
Only M32C/84
REJ05B1104-0110/Rev.1.10
December 2007
Page 8 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
4.6 Differences of Clock
Table 4.6.1 lists the Differences of clock, Table 4.6.2 lists the Differences of clock associated setting, Table
4.6.3 lists the Differences of clock associated pin, and Table 4.6.4 lists the Differences of clock associated SFR.
Table 4.6.1 Differences of Clock
Item
M16C/62P
M32C/84
XIN-XOUT Drive Capacity
Enable to switch
Unable to switch
Main Clock Division
Select from no division, 2, 4, 8, 16 division
Select from no division, 2, 3, 4, 6, 8, 10, 12, 14, 16
Peripheral Function Clock
f1, f2 , f8, f32,
f1, f8, f32 , f2n
f1SIO, f2SIO, f8SIO, f32SIO
fAD,
fAD,
fc32,
division
(1)
(2)
(3)
fc32
fCAN
PLL Multiplying Factor
Multiply-by-2/ Multiply-by-4/ Multiply-by-6/
Divide-by-2 or Divide-by-3 after Multiply-by-6,
Multiply-by-8
Multiply-by-8
Operations when Oscillation Stop
Oscillation Stop Detection Reset/
Oscillation Stop Detection Interrupt
Oscillation Stop, Re-oscillation Stop Interrupt
Oscillation Stop Detect Function
Detect Oscillation Stop, Re-oscillation
Detect Oscillation Stop
Wait mode, Stop mode
Exiting procedure is different between M16C/62P and M32C/84.
Transition from low-speed mode or
Enable
Disable
low-power mode to stop mode
Transition from on-chip oscillator mode
to stop mode
The underlined items represent the differences between the two MCUs.
NOTES:
1. f1 or f2 is selected as a count source of the timers A and B and as an operating clock of the serial I/O by setting PCLKR register.
2. f32 is not selected as a count source of the timers but is selected for the CLKOUT pin output.
3. f2 is not used in M32C/84 and f2n is used as the clock (n = 0 to 15, (n = 0 : no division)).
Table 4.6.2 Differences of Clock associated Setting
Item
M16C/62P
M32C/84
XIN-XOUT Drive Capacity
CM15 bit in the CM1 register
-
Main Clock Division
CM06 bit in the CM0 register
Bits MCD0 to MCD4 in MCD register
PLL Multiplying Factor
PLC0 register
PLC0 register
Operation Select (when an oscillation
CM27 bit in the CM2 register
-
Bits CM16 and CM17 in the CM1 register
PLC1 register
stop)
Table 4.6.3 Differences of Clock associated Pin
Pin name
CLKOUT
REJ05B1104-0110/Rev.1.10
M16C/62P
P5_7
M32C/84
P5_3
December 2007
Page 9 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
Table 4.6.4 Differences of Clock associated SFR
Symbol
Address
M16C/62P
bit
Differences
M32C/84
M16C/62P
M32C/84
CM0
0006h
0006h
6
Main Clock Division Select 0
Watchdog Timer Function Select
CM1
0007h
0007h
1
System Clock Select 1
Reserved bit
5
XIN-XOUT Drive Capacity Select Bit
Reserved bit
6
Main Clock Division Select
Reserved bit
7
CM2
000Ch
000Dh
0
CPU Clock Select Bit 1
Oscillation Stop, Re-Oscillation Detection
Oscillation Stop Detection Enable
Enable
1
System Clock Select 2
CPU Clock Select Bit 2
2
Oscillation Stop, Re-Oscillation Detection Flag Oscillation Stop Detection Flag
6
Nothing is assigned.
Reserved bit
Operation Select (when an oscillation stop,
Reserved bit
7
re-oscillation is detected)
MCD
-
000Ch
-
-
Only M32C/84
PCLKR
025Eh
-
-
Only M16C/62P
-
PLC0
001Ch
0026h
0-2 PLL Multiplying Factor Select
PLL Multiplying Factor Select
(Multiply-by-2, 4, 6, 8)
(Multiply-by-6, 8)
PLC1
-
0027h
-
-
Only M32C/84
PM2
001Eh
0013h
0
Specifying Wait when Accessing SFR at PLL
Reserved bit
Operation
4
Reserved bit
CPU Clock Select 3
5
Nothing is assigned.
CAN Clock Select
6-7 Nothing is assigned.
TCSPR
-
035Fh
REJ05B1104-0110/Rev.1.10
-
-
f2n Count source Select
Only M32C/84
December 2007
Page 10 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
4.7 Differences of Protection
Table 4.7.1 lists the differences of protection associated SFR.
Table 4.7.1 Differences of Protection associated SFR
Symbol
Address
M16C/62P
PRCR
000Ah
bit
Differences
M32C/84
000Ah
M16C/62P
0
1
2
Protect 0
Enables writing to registers CM0,
CM1, CM2, PLC0, and PCLKR
Protect 1
Enables writing to registers PM0,
PM1, PM2, TB2SC, INVC0, and
INVC1
Protect 2
Enables writing to registers PD9,
S3C, and S4C
M32C/84
Protect 0
Enables writing to registers CM0,
CM1, CM2, MCD, PLC0, and PLC1
Protect 1
Enables writing to registers PM0,
PM1, PM2, INVC0, and INVC1
Protect 2
Enables writing to registers PD9 and
PS3
The underlined items represent the differences between the two MCUs.
4.8 Differences of Interrupt
Table 4.8.1 lists the differences of interrupt and Tables 4.8.2 and 4.8.3 list the differences of interrupt
associated SFR. The re-locatable vector tables and the interrupt priority level select circuits are different.
Table 4.8.1 Differences of Interrupt
Item
M16C/62P
M32C/84
High-speed interrupt
N/A
Available
Address match interrupt
Can be set in 4 addresses
Can be set in 8 addresses
Table 4.8.2 Differences of Interrupt associated SFR (1/2)
Symbol
Address
M16C/62P
bit
Differences
M32C/84
M16C/62P
M32C/84
AD0IC
-
0073h
-
-
Only M32C/84
ADIC
004Eh
-
-
Only M16C/62P
-
AIER
0009h
0009h
2
Nothing is assigned.
Enables Address Match Interrupt 2
3
Nothing is assigned.
Enables Address Match Interrupt 3
4
Nothing is assigned.
Enables Address Match Interrupt 4
5
Nothing is assigned.
Enables Address Match Interrupt 5
6
Nothing is assigned.
Enables Address Match Interrupt 6
7
Nothing is assigned.
Enables Address Match Interrupt 7
AIER2
01BBh
-
-
Only M16C/62P
-
BCN0IC/
-
0071h
-
-
Only M32C/84
-
0091h
-
-
Only M32C/84
BCN2IC
-
008Fh
-
-
Only M32C/84
BCNIC
004Ah
-
-
Only M16C/62P
-
DM0IC
004Bh
0068h
-
Different address
BCN3IC
BCN1IC/
BCN4IC
DM1IC
004Ch
0088h
-
Different address
DM2IC
-
006Ah
-
-
Only M32C/84
DM3IC
-
008Ah
-
-
Only M32C/84
REJ05B1104-0110/Rev.1.10
December 2007
Page 11 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
Table 4.8.3 Differences of Interrupt associated SFR (1/2)
Symbol
Address
M16C/62P
IFSR
IFSR2A
035Fh
035Eh
bit
Differences
M32C/84
031Fh
-
M16C/62P
M32C/84
__________
6
Interrupt Source Select (SI/O3 / I N T 4 ) Interrupt Source Select (UART0 / UART3)
7
Interrupt Source Select (SI/O4 / I N T 5 ) Interrupt Source Select (UART1 / UART4)
-
Only M16C/62P
__________
-
INT0IC
005Dh
009Eh
5
Reserved bit
Level / Edge Sensitive Switch Bit
INT1IC
005Eh
007Eh
5
Reserved bit
Level / Edge Sensitive Switch Bit
INT2IC
005Fh
009Ch
5
Reserved bit
Level / Edge Sensitive Switch Bit
INT3IC
0044h
007Ch
5
Reserved bit
Level / Edge Sensitive Switch Bit
INT4IC
0049h
009Ah
5
Reserved bit
Level / Edge Sensitive Switch Bit
INT5IC
0048h
007Ah
5
Reserved bit
Level / Edge Sensitive Switch Bit
KUPIC
004Dh
0093h
-
Different address
RLVL
-
009Fh
-
-
Only M32C/84
RMAD0
0010h-0012h 0010h-0012h
-
Setting Range : 20 bit
Setting Range : 24 bit
RMAD1
0014h-0016h 0014h-0016h
-
Setting Range : 20 bit
Setting Range : 24 bit
RMAD2
01B8h-01BAh 0018h-001Ah
-
Setting Range : 20 bit
Setting Range : 24 bit
RMAD3
01BCh-01BEh 001Ch-001Eh
-
Setting Range : 20 bit
Setting Range : 24 bit
RMAD4
-
0028h-002Ah
-
-
Only M32C/84, Setting Range : 24 bit
RMAD5
-
002Ch-002Eh
-
-
Only M32C/84, Setting Range : 24 bit
RMAD6
-
0038h-003Ah
-
-
Only M32C/84, Setting Range : 24 bit
RMAD7
-
003Ch-003Eh
-
-
Only M32C/84, Setting Range : 24 bit
S0RIC
0052h
0072h
-
Different address
S0TIC
0051h
0090h
-
Different address
S1RIC
0054h
0074h
-
Different address
S1TIC
0053h
0092h
-
Different address
S2RIC
0050h
006Bh
-
Different address
S2TIC
004Fh
0089h
-
Different address
S3IC
0049h
-
-
Only M16C/62P
-
S3RIC
-
006Dh
-
-
Only M32C/84
S3TIC
-
008Bh
-
-
Only M32C/84
S4RIC
-
006Fh
-
-
Only M32C/84
S4TIC
-
008Dh
-
-
Only M32C/84
S4IC
0048h
-
-
Only M16C/62P
-
TA0IC
0055h
006Ch
-
Different address
TA1IC
0056h
008Ch
-
Different address
TA2IC
0057h
006Eh
-
Different address
TA3IC
0058h
008Eh
-
Different address
TA4IC
0059h
0070h
-
Different address
TB0IC
005Ah
0094h
-
Different address
TB1IC
005Bh
0076h
-
Different address
TB2IC
005Ch
0096h
-
Different address
TB3IC
0047h
0078h
-
Different address
TB4IC
0046h
0098h
-
Different address
TB5IC
0045h
0069h
-
Different address
REJ05B1104-0110/Rev.1.10
December 2007
Page 12 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
4.9 Differences of Watchdog Timer
Table 4.9.1 lists the differences of Watchdog Timer.
Table 4.9.1 Differences of Watchdog Timer
Item
M16C/62P
Watchdog Timer Function Select
PM12 bit in the PM1 register
M32C/84
CM06 bit in the CM0 register
(selects interrupt or reset)
4.10 Differences of DMAC
Table 4.10.1 lists the Differences of DMAC, Table 4.10.2 lists the differences of DMAC settings, and Table
4.10.3 lists the differences of DMAC associated SFR. DMAC associated registers are assigned to SFR in
M16C/62P and are assigned to internal register and SFR in M32C/84. Therefore, DMAC settings procedures
are different between M16C/62P and M32C/84.
Table 4.10.1 Differences of DMAC
Item
M16C/62P
M32C/84
DMAC-Associated register
Assigned to SFR
Assigned to internal register and SFR
Number of Channels
2 channels
4 channels
Transfer Memory Space
- From a given address in a 1-Mbyte space to a
- From a given address in a 16-Mbyte space to a
fixed address
fixed address
- From a fixed address to a given address in a
- From a fixed address to a given address in a
1-Mbyte space
16-Mbyte space
- From a fixed address to a fixed address
Number of Transfer Time
Number set in DMAi transfer counter (i = 0 to 1) +1
Number set in DMAi transfer counter (i = 0 to 3)
Interrupt Request
When the DMAi transfer counter underflows
When the DMAi transfer counter changes ”0001h”
Generation Timing
to ”0000h”
Table 4.10.2 Differences of DMAC Settings
Item
M16C/62P
M32C/84
DMA Transfer Factor
Set bits DSEL0 to DSEL3 and DMS bit in the
Set DSEL0 to DSEL4 bit in the DMiSL register
Select
DMiSL register
Transfer Mode
DMiCON register
Set DMDi register
Source Address
SARi register
When the Source Address is fixed: DSAi register
Destination Address
DARi register
When the Source Address is in memory: DMAi register
(Re-loaded value in repeat transfer mode is set to DRAi
register)
Transfer Count
Set (the number of transfers - 1) to TCRi register.
Set the number of transfers to DCTi register
(Re-loaded value in repeat transfer mode is set to DRCi
register)
REJ05B1104-0110/Rev.1.10
December 2007
Page 13 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
Table 4.10.3 Differences of DMAC associated SFR
Symbol
Address
M16C/62P
bit
Differences
M32C/84
M16C/62P
M32C/84
DAR0
0024h-0026h -
-
Only M16C/62P
-
DAR1
0034h-0036h -
-
Only M16C/62P
-
-
-
-
DCT0
to
DCT3
CPU internal
Only M32C/84
(1)
(1)
(2)
(2)
DCT0 , DCT1
register
DCT2 , DCT3
DM0CON
002Ch
-
DM0SL
03B8h
0378h
DM1CON
003Ch
-
DM1SL
03BAh
0379h
-
Only M16C/62P
0-3 DMA Request Factor Select
DMA Request Factor Select
4
Nothing is assigned.
5
Nothing is assigned.
Software DMA Request
6
DMA Request Factor Expansion Select
Reserved bit
7
Software DMA Request
DMA Request
-
Only M16C/62P
-
0-3 DMA Request Factor Select
DMA Request Factor Select
4
Nothing is assigned.
5
Nothing is assigned.
Software DMA Request
6
DMA Request Factor Expansion Select
Reserved bit
7
Software DMA Request
DMA Request
DM2SL
-
037Ah
-
-
Only M32C/84
DM3SL
-
037Bh
-
-
Only M32C/84
DMA0
-
CPU internal
-
-
Only M32C/84
to
-
DMD1
DRA0
CPU internal
-
-
-
-
Only M32C/84
-
CPU internal
Only M32C/84
(1)
DRA2
DRA3
-
to
CPU internal
-
-
(1)(2)
(1)
, DRA3
(1)
(1)
(2)
(2)
DRC0 , DRC1
DRC3
DRC2 , DRC3
-
CPU internal
-
(1)(2)
Only M32C/84
register
to
(1)
DRA0 , DRA1
register
DSA0
(2)
register
to
DRC0
(1)
(2)
DMA2 , DMA3
DMA3
DMD0
(1)
DMA0 , DMA1
register
-
Only M32C/84
(1)
(1)
DSA0 , DSA1
register
(1)(2)
DSA3
DSA2
SAR0
0020h-0022h -
-
Only M16C/62P
-
SAR1
0030h-0032h -
-
Only M16C/62P
-
TCR0
0028h-0029h -
-
Only M16C/62P
-
TCR1
0038h-0039h -
-
Only M16C/62P
-
(1)(2)
, DSA3
NOTES:
1.
Use the LDC instruction to set the registers.
2.
Use the register bank 1 or the high-speed interrupt registers when DMA2 and/or DMA3 is used.
REJ05B1104-0110/Rev.1.10
December 2007
Page 14 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
4.11 Differences of Timer
Table 4.11.1 lists the differences of timer and Table 4.11.2 lists the differences of timer associated SFR.
Table 4.11.1 Differences of Timer
Item
M16C/62P
M32C/84
Count Source
f1/f2, f8, f32, fc32
f1, f8, f2n, fc32
Pulse output function
MR0 bit (i = 0 to 4) in the TAiMR register
Function select register
select
The underlined items represent the differences between the two MCUs.
Table 4.11.1 Differences of Timer associated SFR
Symbol
Address
M16C/62P
bit
M32C/84
ONSF
0382h
TA0
0386h-0387h 0346h-0347h
0342h
to
to
TA4
038Eh-038Fh 034Eh-034Fh
TA0MR
0396h
0356h
TA1MR
0397h
0357h
Differences
M16C/62P
-
Different address
-
Different address
2
Pulse output function select
to
6-7 Count Source select (f1/f2, f32)
2
Pulse output function select
6-7 Count Source select (f1/f2, f32)
TA2MR
0398h
0358h
2
Pulse output function select
6-7 Count Source select (f1/f2, f32)
TA3MR
0399h
0359h
2
Pulse output function select
6-7 Count Source select (f1/f2, f32)
TA4MR
039Ah
M32C/84
035Ah
2
Pulse output function select
6-7 Count Source select (f1/f2, f32)
0340h
-
Different address
-
Different address
Reserved bit
Count Source select (f1, f2n)
Reserved bit
Count Source select (f1, f2n)
Reserved bit
Count Source select (f1, f2n)
Reserved bit
Count Source select (f1, f2n)
Reserved bit
Count Source select (f1, f2n)
TABSR
0380h
TB0
0390h-0391h 0350h-0351h
to
to
TB2
0394h-0395h 0354h-0355h
TB0MR
039Bh
035Bh
6-7 Count Source select (f1/f2,f32)
Count Source select (f1,f2n)
TB1MR
039Ch
035Ch
6-7 Count Source select (f1/f2,f32)
Count Source select (f1,f2n)
TB2MR
039Dh
035Dh
6-7 Count Source select (f1/f2,f32)
Count Source select (f1,f2n)
TB3
0350h-0351h 0310h-0311h
to
to
TB5
0354h-0355h 0314h-0315h
TB3MR
035Bh
031Bh
6-7 Count Source select (f1/f2,f32)
Count Source select (f1,f2n)
TB4MR
035Ch
031Ch
6-7 Count Source select (f1/f2,f32)
Count Source select (f1,f2n)
TB5MR
035Dh
031Dh
6-7 Count Source select (f1/f2,f32)
Count Source select (f1,f2n)
TBSR
0340h
0300h
to
-
Different address
to
-
Different address
TRGSR
0383h
0343h
-
Different address
UDF
0384h
0344h
-
Different address
TCSPR
-
035Fh
-
REJ05B1104-0110/Rev.1.10
Only M32C/84
December 2007
Page 15 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
4.12 Three-Phase Motor Control Timer Functions
Table 4.12.1 lists the differences of three-phase motor control timer functions associated SFR.
Table 4.12.1 Differences of Three-Phase Motor Control Timer Functions associated SFR
Symbol
Address
M16C/62P
bit
Differences
M32C/84
M16C/62P
DTT
034Ch
030Ch
-
Different address
ICTB2
034Dh
030Dh
-
Different address
IDB0
034Ah
030Ah
-
Different address
IDB1
034Bh
030Bh
-
Different address
INVC0
0348h
0308h
-
Different address
INVC1
0349h
0309h
2
Dead Time Timer Count Source
Dead Time Timer Count Source
(f1/f2 or f1 divided-by-2 / f2 divided-by-2)
(f1 / f1 divided-by-2)
TA11
0342h-0343h 0302h-0303h
-
Different address
TA21
0344h-0345h 0304h-0305h
-
Different address
TA41
0346h-0347h 0306h-0307h
-
Different address
TB2SC
039Eh
1
Three Phase Output Port N M I Control
035Eh
M32C/84
________
Reserved bit (Set to 0.)
4.13 Differences of Serial Interface
Table 4.13.1 lists the differences of serial interface, Table 4.13.2 lists the differences of serial interface
associated pin, and Tables 4.13.3 and 4.13.4 list the differences of serial interface associated SFR. To output
from each serial interface associated pin in M32C/84, set using the function select registers.
Table 4.13.1 Differences of Serial Interface
Item
Configuration
M16C/62P
3 channels (UART0 to UART2)
M32C/84
5 channels (UART0 to UART4)
Clock Synchronous
Clock Synchronous
Clock Asynchronous
Clock Asynchronous
2
2
I C Mode
I C Mode
Special Mode2
Special Mode 2
IE Mode
GCI Mode
SIM Mode
IE Mode
2 channels (SI/O3, SI/O4)
SIM Mode
Clock Synchronous
Count Source
f1/f2, f8, f32
f1, f8, f2n
Transfer Clock Output from multiple
Selectable using UART1
N/A
_______ _______
Selectable using UART0
N/A
Pin Output Settings
When using UART associated registers
When using Function Select Registers
pins Function
CTS /RTS Separate Function
The underlined items represent the differences between the two MCUs.
REJ05B1104-0110/Rev.1.10
December 2007
Page 16 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
Table 4.13.2 Differences of Serial Interface associated Pin
Channel
UART0
UART1
UART2
Pin
P6_0
UART4 / SI/O4
M32C/84
________ ________ ______
P6_1
CTS0/RTS0
CLK0
CTS0/RTS0/SS0
CLK0
P6_2
RXD0/SCL0
RXD0/SCL0/STXD0
P6_3
TXD0/SDA0
TXD0/SDA0/SRXD0
________ ________ ________
________ ________ ______
P6_4
CTS1/RTS1/CTS0/CLKS1
CTS1/RTS1/SS1
P6_5
CLK1
CLK1
P6_6
RXD1/SCL1
RXD1/SCL1/STXD1
P6_7
TXD1/SDA1
TXD1/SDA1/SRXD1
P7_0
TXD2/SDA2
TXD2/SDA2/SRXD2
P7_1
RXD2/SCL2
RXD2/SCL2/STXD2
P7_2
CLK2
CLK2
_________ _________
_________ _________ ______
P7_3
UART3 / SI/O3
M16C/62P
________ ________
P9_0
CTS2/RTS2
CLK3
CTS2/RTS2 /SS2
CLK3
P9_1
SIN3
RXD3/SCL3/STXD3
P9_2
P9_3
SOUT3
-
P9_4
-
P9_5
CLK4
P9_6
SOUT4
TXD4/SDA4/SRXD4
P9_7
SIN4
RXD4/SCL4/STXD4
REJ05B1104-0110/Rev.1.10
TXD3/SDA3/SRXD3
_________ _________ ______
CTS3/RTS3 /SS3
_________ _________ ______
CTS4/RTS4 /SS4
CLK4
December 2007
Page 17 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
Table 4.13.3 Differences of Serial Interface associated SFR (1/2)
Symbol
Address
M16C/62P
bit
Differences
M32C/84
U0BRG
03A1h
0369h
U0C0
03A4h
036Ch
U0C1
03A5h
036Dh
M16C/62P
-
M32C/84
Different address
0-1 UiBRG Count Source Select (f1/f2, f32)
UiBRG Count Source Select (f1, f2n)
4
Nothing is assigned.
UARTi Transmit Interrupt Cause Select
5
Nothing is assigned.
UARTi Continuous Receive Mode Enable
7
Error Signal Output Enable
Clock-Divided Synchronous Stop/
Error Signal Output Enable
U0MR
03A0h
U0RB
03A6h-03A7h 036Eh-036Fh
0368h
U0SMR
036Fh
0367h
-
Different address
-
Different address
3
Reserved bit
SCLL Sync Output Enable
7
Nothing is assigned.
Clock Divide Synchronous
External Clock Synchronous Enable
U0SMR2
036Eh
0366h
7
Nothing is assigned.
U0SMR3
036Dh
0365h
0
Nothing is assigned.
2
Nothing is assigned.
S S Pin Function Enable
Serial Input Port Set
4
Nothing is assigned.
Fault Error Flag
U0SMR4
U0TB
036Ch
0364h
03A2h-03A3h 036Ah-036Bh
U1BRG
03A9h
02E9h
U1C0
03ACh
02ECh
U1C1
03ADh
02EDh
3
______
SCL, SDA Output Select
SCL, SDA Output Select
(Start and Stop Condition output/
(Selects the serial I/O / Selects the
not output)
start/stop condition)
-
Different address
-
Different address
0-1 UiBRG Count Source Select (f1/f2, f32)
UiBRG Count Source Select (f1, f2n)
4
Nothing is assigned.
UARTi Transmit Interrupt Cause Select
5
Nothing is assigned.
UARTi Continuous Receive Mode Enable
7
Error Signal Output Enable
Clock-Divided Synchronous Stop/
Error Signal Output Enable
U1MR
03A8h
U1RB
03AEh-03AFh 02EEh-02EFh
02E8h
U1SMR
0373h
02E7h
-
Different address
-
Different address
3
Reserved bit
SCLL Sync Output Enable
7
Nothing is assigned.
Clock Divide Synchronous
External Clock Synchronous Enable
U1SMR2
0372h
02E6h
7
Nothing is assigned.
U1SMR3
0371h
02E5h
0
Nothing is assigned.
2
Nothing is assigned.
S S Pin Function Enable
Serial Input Port Set
4
Nothing is assigned.
Fault Error Flag
3
SCL, SDA Output Select
SCL, SDA Output Select
(Start and Stop Condition output/
(Selects the serial I/O / Selects the
not output)
start/stop condition)
U1SMR4
U1TB
0370h
02E4h
03AAh-03ABh 02EAh-02EBh
U2BRG
0379h
0339h
U2C0
037Ch
033Ch
U2C1
037Dh
033Dh
-
Different address
-
Different address
0-1 UiBRG Count Source Select (f1/f2, f32)
7
Error Signal Output Enable
______
UiBRG Count Source Select (f1, f2n)
Clock-Divided Synchronous Stop/
Error Signal Output Enable
U2MR
0378h
U2RB
037Eh-037Fh 033Eh-033Fh
U2SMR
0377h
U2SMR2
0376h
0338h
0337h
0336h
REJ05B1104-0110/Rev.1.10
-
Different address
-
Different address
3
Reserved bit
SCLL Sync Output Enable
7
Nothing is assigned.
Clock Divide Synchronous
7
Nothing is assigned.
External Clock Synchronous Enable
December 2007
Page 18 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
Table 4.13.4 Differences of Serial Interface associated SFR (2/2)
Symbol
Address
M16C/62P
U2SMR3
U2SMR4
0375h
0374h
bit
Differences
M32C/84
0335h
0334h
M16C/62P
M32C/84
______
0
Nothing is assigned.
2
Nothing is assigned.
S S Pin Function Enable
Serial Input Port Set
4
Nothing is assigned.
Fault Error Flag
3
SCL, SDA Output Select
SCL, SDA Output Select
(Start and Stop Condition output/ (Selects the serial I/O / Selects the start/stop condition)
not output)
U2TB
037Ah-03ABh 033Ah-033Bh
-
Different address
UCON
03B0h
-
-
Only M16C/62P
-
S3BRG
0363h
-
-
Only M16C/62P
-
S3C
0362h
-
-
Only M16C/62P
-
S3TRR
0360h
-
-
Only M16C/62P
-
S4BRG
0367h
-
-
Only M16C/62P
-
S4C
0366h
-
-
Only M16C/62P
-
S4TRR
0364h
-
-
Only M16C/62P
-
U3BRG
-
0329h
-
-
Only M32C/84
U3C0
-
032Ch
-
-
Only M32C/84
U3C1
-
032Dh
-
-
Only M32C/84
U3MR
-
0328h
-
-
Only M32C/84
U3RB
-
032Eh-032Fh
-
-
Only M32C/84
U3SMR
-
0327h
-
-
Only M32C/84
U3SMR2
-
0326h
-
-
Only M32C/84
U3SMR3
-
0325h
-
-
Only M32C/84
U3SMR4
-
0324h
-
-
Only M32C/84
U3TB
-
032Ah-032Bh
-
-
Only M32C/84
U4BRG
-
02F9h
-
-
Only M32C/84
U4C0
-
02FCh
-
-
Only M32C/84
U4C1
-
02FDh
-
-
Only M32C/84
U4MR
-
02F8h
-
-
Only M32C/84
U4RB
-
02FEh-02FFh
-
-
Only M32C/84
U4SMR
-
02F7h
-
-
Only M32C/84
U4SMR2
-
02F6h
-
-
Only M32C/84
U4SMR3
-
02F5h
-
-
Only M32C/84
U4SMR4
-
02F4h
-
-
Only M32C/84
U4TB
-
02FAh-02FBh
-
-
Only M32C/84
REJ05B1104-0110/Rev.1.10
December 2007
Page 19 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
4.14 Differences of A/D Converter
4.14.1 Differences of A/D Converter
Table 4.14.1 lists the differences of A/D converter and Table 4.14.2 lists the differences of A/D converter
associated SFR.
Table 4.14.1 Differences of A/D Converter
Item
Operating Clock (φAD)
A/D Converter maximum operating clock
A/D Conversion Start
Condition
Mode
Analog Input Pins
DMAC operating mode
(1)
M16C/62P
Selectable from among:
fAD, fAD/2, fAD/3, fAD/4, fAD/6,
fAD/12
(Registers ADCON0, ADCON1, and
ADCON2 determine)
VCC1 ≥ 4V : φAD = 12MHz
VCC1 < 4V : φAD = 10MHz
Software trigger/ External trigger
M32C/84
Selectable from among:
fAD, fAD/2, fAD/3, fAD/4, fAD/6, fAD/8
(Registers AD0CON0, AD0CON1, and AD0CON3
determine)
One-shot mode
Repeat mode
Single sweep mode
Repeat sweep mode 0
Repeat sweep mode 1
One-shot mode
Repeat mode
Single sweep mode
Repeat sweep mode 0
Repeat sweep mode 1
Multi-port single sweep mode
Multi-port repeat sweep mode 0
34 pins
AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7,
AN15_0 to AN15_7, ANEX0, ANEX1
Available
26 pins
AN0 to AN7, AN0_0 to AN0_7, AN2_0 to
AN2_7, ANEX0, ANEX1
N/A
VCC1 = 5.0 V : φAD = 16MHz
VCC1 = 3.3 V : φAD = 10MHz
Software trigger/ External trigger /Hardware trigger
NOTE:
(1) The A/D conversion result is stored in the AD00 register after the A/D conversion is completed. DMAC transfers the conversion result to a
given memory space every time a pin is converted.
Table 4.14.2 Differences of A/D Converter associated SFR
Symbol
Address
M16C/62P
AD0CON0 /
03D6h
bit
M32C/84
0396h
ADCON0
AD0CON1 /
0-2 Analog Input Pin
Analog Input Pin
Trigger Select
7 Frequency Select
Frequency Select
0397h
0-1 A/D Sweep Pin Select
03D4h
0394h
1-2 A/D Input Group Select
4 Frequency Select 1
ADCON2
M32C/84
5 Trigger Select
03D7h
ADCON1
AD0CON2 /
Differences
M16C/62P
A/D Sweep Pin Select
Frequency Select
Analog Input Port Select
3 Reserved bit
Nothing is assigned.
4 Frequency Select 2
Nothing is assigned.
5 Nothing is assigned.
External Trigger Request Cause Select
6-7 Nothing is assigned.
Reserved bit
AD0CON3
-
0395h
- -
Only M32C/84
AD0CON4
-
0392h
- -
Only M32C/84
AD00 to AD07 03C0h-03C1h to
0380h-0381h to - Different address
/ AD0 to AD7
038Eh-038Fh
03CEh-03CFh
4.14.2 Notice of A/D Converter
In M32C/84, to separate A/D input/output pins (ANEX0, ANEX1, AN4 to AN7, and AN15_0 to AN15_7) from
the other peripheral function inputs, set bits PSL3_5 and PSL3_6 in the PSL3 register, the PSC_7 bit in the
PSC register and the IPS2 bit in the IPS register. Setting 1 (A/D input/output) to corresponding bits with pins
which are used as A/D input/output prevents applying intermediate electric potential to the other peripheral
function inputs. (Applying intermediate electric potential may bring increase of power supply current.)
REJ05B1104-0110/Rev.1.10
December 2007
Page 20 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
4.15 Differences of D/A Converter
4.15.1 Differences of D/A Converter
Table 4.15.1 lists the Differences of D/A converter associated SFR.
Table 4.15.1 Differences of D/A Converter associated SFR
Symbol
Address
M16C/62P
bit
Differences
M32C/84
M16C/62P
DACON
03DCh
039Ch
-
Different address
DA0
03D8h
0398h
-
Different address
DA1
03DAh
039Ah
-
Different address
M32C/84
4.15.2 Notice of D/A Converter
In M32C/84, to separate D/A output pins (DA0, DA1) from the other peripheral function inputs, set bits
PSL3_3 and PSL3_4 in the PSL3 register. Setting 1 (D/A output) to corresponding bits with pins which are
used as D/A output prevents applying intermediate electric potential to the other peripheral function inputs.
(Applying intermediate electric potential may bring increase of power supply current.)
4.16 Differences of CRC Calculation
Table 4.16.1 lists the Differences of CRC calculation associated SFR.
Table 4.16.1 Differences of CRC Calculation associated SFR
Symbol
Address
M16C/62P
M32C/84
CRCIN
03BEh
037Eh
CRCD
03BCh-03BDh 037Ch-037Dh
REJ05B1104-0110/Rev.1.10
bit
Differences
M16C/62P
-
Different address
-
Different address
December 2007
M32C/84
Page 21 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
4.17 Differences of Ports
4.17.1 Differences of Port Pi Direction Register, Port Pi Register
Table 4.17.1 lists the differences of port Pi direction register and port Pi register.
Table 4.17.1 Differences of Port Pi Direction Register, Port Pi Register
Symbol
Address
M16C/62P
bit
Differences
M32C/84
M16C/62P
P6
03ECh
03C0h
-
Different address
P7
03EDh
03C1h
-
Different address
P8
03F0h
03C4h
-
Different address
P9
03F1h
03C5h
-
Different address
P10
03F4h
03C8h
-
Different address
P11
03F5h
03C9h
-
Different address
P12
03F8h
03CCh
-
Different address
P13
03F9h
03CDh
-
Different address
P14
-
03D0h
-
-
M32C/84
Only M32C/84
P15
-
03D1h
-
-
Only M32C/84
PC14
03DEh
-
-
Only M16C/62P
-
PD6
03EEh
03C2h
-
Different address
PD7
03EFh
03C3h
-
Different address
PD8
03F2h
03C6h
-
Different address
PD9
03F3h
03C7h
-
Different address
PD10
03F6h
03CAh
-
Different address
PD11
03F7h
03CBh
-
Different address
PD12
03FAh
03CEh
-
Different address
PD13
03FBh
03CFh
-
Different address
PD14
-
03D2h
-
-
Only M32C/84
PD15
-
03D3h
-
-
Only M32C/84
4.17.2 Differences of Port Control Register
Table 4.17.2 lists the differences of port control register.
Table 4.17.2 Differences of Port Control Register
Symbol
Address
M16C/62P
PCR
03FFh
bit
M32C/84
03FFh
Differences
M16C/62P
0
Port P1 Control
M32C/84
Port P1 Control
(Determines either the input level is read (Determines either CMOS output or
or the port latch is read)
REJ05B1104-0110/Rev.1.10
December 2007
N-channel open drain output)
Page 22 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
4.17.3 Differences of Pull-Up Control Register
Table 4.17.3 lists the differences of pull-up control register.
Table 4.17.3 Differences of Pull-Up Control Register
Symbol
Address
M16C/62P
PUR1
PUR2
PUR3
PUR4
03FDh
03FEh
03DFh
-
bit
Differences
M32C/84
03F1h
03DAh
03DBh
03DCh
M16C/62P
M32C/84
4
P6_0 to P6_3 Pull-Up
Nothing is assigned.
5
P6_4 to P6_7 Pull-Up
Nothing is assigned.
6
P7_2 to P7_3 Pull-Up
Nothing is assigned.
7
P7_4 to P7_7 Pull-Up
Nothing is assigned.
0
P8_0 to P8_3 Pull-Up
P6_0 to P6_3 Pull-Up
1
P8_4 to P8_7 Pull-Up
P6_4 to P6_7 Pull-Up
2
P9_0 to P9_3 Pull-Up
P7_2 to P7_3 Pull-Up
3
P9_4 to P9_7 Pull-Up
P7_4 to P7_7 Pull-Up
4
P10_0 to P10_3 Pull-Up
P8_0 to P8_3 Pull-Up
5
P10_4 to P10_7 Pull-Up
P8_4 to P8_7 Pull-Up
6
Nothing is assigned.
P9_0 to P9_3 Pull-Up
7
Nothing is assigned.
P9_4 to P9_7 Pull-Up
0
P11_0 to P11_3 Pull-Up
P10_0 to P10_3 Pull-Up
1
P11_4 to P11_7 Pull-Up
P10_4 to P10_7 Pull-Up
2
P12_0 to P12_3 Pull-Up
P11_0 to P11_3 Pull-Up
3
P12_4 to P12_7 Pull-Up
P11_4 Pull-Up
4
P13_0 to P13_3 Pull-Up
P12_0 to P12_3 Pull-Up
5
P13_4 to P13_7 Pull-Up
P12_4 to P12_7 Pull-Up
6
P14_0 and P14_1 Pull-Up
P13_0 to P13_3 Pull-Up
7
P11 to P14 Enabling
P13_4 to P13_7 Pull-Up
-
-
Only M32C/84
4.17.4 Function Select Register
M32C/84 has the Function Select Registers (PSC, PSC2, PSC3, PSD1, PSL0 to PSL3, PS0 to PS3, PS5, PS8,
and PS9). When multiple peripheral function outputs are assigned to a pin, set these function select registers
to select which function is used.
4.17.5 Input Function Select Register
M32C/84 has the input function select registers (IPS and IPSA) which select input function.
REJ05B1104-0110/Rev.1.10
December 2007
Page 23 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
4.18 Differences of Flash Memory
4.18.1 Differences of Flash Memory
Table 4.18.1 lists the differences of flash memory. Addresses of flash memory associated SFR are different in
M16C/62P and M32C/84.
Table 4.18.1 Differences of Flash Memory
bit
Address
Symbol
M16C/62P
Differences
M32C/84
M16C/62P
FIDR
01B4h
-
-
Only M16C/62P
FMR0
01B7h
0057h
-
Different address
FMR1
01B5h
0055h
-
Different address
M32C/84
-
4.19 Peripheral Functions added in M32C/84
Peripheral Functions added in M32C/84 are as below.
- Intelligent I/O
- CAN
- DMACII
- X/Y Conversion
4.20 Differences of Development Tool
Table 4.20.1 lists the differences of development tool.
Table 4.20.1 Differences of Development Tool.
Tool
C Compiler
For M16C/62P
For M32C/84
M3T-NC30WA
M3T-NC308WA
Real-time OS
M3T-MR30/4
M3T-MR308/4
Emulator Debugger
M16C R8C PC7501
M32C PC7501
(including Simulator Debugger)
M16C PC4701
Emulation Probe
M3062PT2-EPB (for PC7501)
M30850T2-EPB
Emulation Pod
M3062PT3-RPD-E (for PC4701)
Compact Emulator
M3062PT3-CPE
M30850T3-CPE
Renesas Starter Kits
R0K33062PS000BE
R0K330879S000BE
REJ05B1104-0110/Rev.1.10
December 2007
Page 24 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
5.
Reference Documents
Hardware manual
M16C/62P Group Hardware Manual
M32C/84 Group Hardware Manual
(Use the latest information on the home page: http://www.renesas.com)
TECHNICAL UPDATE/TECHNICAL NEWS
(Use the latest information on the home page: http://www.renesas.com)
REJ05B1104-0110/Rev.1.10
December 2007
Page 25 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
Web site and Contact for Support
Renesas Technology Web site
http://www.renesas.com/
Inquiries
http://www.renesas.com/inquiry
csc@renesas.com
REVISION HISTORY
Rev.
Date
1.10
Dec 20, 2007
REJ05B1104-0110/Rev.1.10
Page
-
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
Description
Summary
First edition issued
December 2007
Page 26 of 27
M16C/62P, M32C/84 Group
Differences between M16C/62P and M32C/84
© 2007. Renesas Technology Corp., All rights reserved.
REJ05B1104-0110/Rev.1.10
December 2007
Page 27 of 27