Differences between M16C/62P and M16C/62M

APPLICATION NOTE
M16C/62P, M16C/62M Group
Differences between M16C/62P and M16C/62M
1.
Abstract
This issue is the reference matelials ot function differences between M16C/62P and M16C/62M.
2.
Introduction
The explanation of this issue is applied to the following condition:
Applicable MCU: M16C/62P, M16C/62M
3.
Contents
3.1 Function differences
Table 3.1.1 and table 3.1.2 show the function differences (mask ROM version and flash memory version). Table 3.1.3 shows
the function differences (flash memory version).
Table 3.1.1 Function differences (mask ROM version and flash memory version)-1(Note1)
Item
M16C/62P
M16C/62M
Shortest instruction
execution time
41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Supply voltage
I/O power supply
VCC1=3.0 to 5.5V, VCC2=3.0V to VCC1
(f(BCLK)=24MHz)
VCC1=VCC2=2.7 to 5.5V (f(BCLK)=10MHz)
Double (VCC1, VCC2)
Package
80-pin, 100-pin, 128-pinplastic mold QFP
80-pin, 100-pinplastic mold QFP
Clock generating circuit
PLL, XIN, XCIN, on-chip oscillator
When placed in low power mode a divided-8
value is used for these clocks. The XIN drive
capability is set to HIGH.
Built-in
XIN, XCIN
When placed in low power mode, the divided-n
value for the main clock does not change. Nor
does the XIN drive capability change.
None
(protected by protect register)
None
System clock protective
function
Oscillation stop,
re-oscillation detecton
function
Low power consumption
Memory area
External
area
device
connect
Built-in
18mA(VCC1=VCC2=5V, f(BCLK)=24MHz)
8mA(VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8uA(VCC1=VCC2=3V, f(XCIN)=32kHz, wait
mode)
Memory area expandable (4M bytes)
04000h to 07FFFh (PM13=0)
08000h to 0FFFFh(PM10=0)
10000h to 26FFFh
28000h to 7FFFFh
80000h to CFFFFh (PM13=0)
D0000h to FFFFFh (Microprocessor mode)
100ns(f(XIN)=10MHz, VCC=2.7 to 3.6V)
142.9ns(f(XIN)=7MHz, VCC=2.2 to 3.6V,
with software one-wait)
2.7 to 3.6V(f(XIN)=10MHz)
2.4 to 3.6V(f(XIN)=7MHz)
2.2 to 3.6V(f(XIN)=7MHz, with software one-wait)
Single (VCC)
9.5mA(VCC=3V, f(XIN)=10MHz)
0.9uA(VCC=3V, f(XCIN)=32kHz, wait mode)
1 M bytes fixed
04000h to 05FFFh (PM13=0)
06000h to CFFFFh
D0000h to FFFFFh (Microprocessor mode)
Note 1: About the details and the characteristics, refer to hardware manual.
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August 2004
Page 1 of 11
M16C/62P, M16C/62M Group
Differences between M16C/62P and M16C/62M
Table 3.1.2 Function differences (mask ROM version and flash memory version)-2(Note1)
Item
M16C/62P
M16C/62M
Upper address memory
expansion
mode
and
microprocessor mode
Access to SFR
P4_0 to P4_3(A16 to A19),
P3_4 to P3_7(A12 to A15)
: Switchable between address bus and I/O port
Variable (1 to 2 waits)
P4_0 to P4_3(A16 to A19)
: Switchable between address bus and I/O port
A12 to A15: No Switchable
1 wait fixed
Software wait to external
area
Protect
Variable (0 to 3 waits)
Variable (0 to 1 wait)
Can be set for PM0, PM1, PM2, CM0, CM1,
CM2, PLC0, INVC0, INVC1, PD9, S3C, S4C,
TB2SC, PCLKR, VCR2, D4INT registers
Watchdog timer interrupt or watchdog timer reset
is selected
Count source protective mode is available
4
Can be set for PM0, PM1, CM0, CM1, PD9, S3C,
S4C registers
2
Selectable: f1, f2, f8, f32, fC32
Selectable: f1, f8, f32, fC32
Function Z-phase (counter reset) input
No function Z-phase (counter reset) input
Function protect by protect register
Count source is selected f1, f2, f8, f32, fC32
Dead time timer count source is selected: f1, f1
divided by 2, f2, f2 divided by 2
Three-phase output forcible shutoff function
based on NMI input is available, output polarity
change, carrier wave phase detection
2
TM
(UART, Clock synchronous, I C-bus (Note 2),
TM
IEBus (Note 3)) x 3
No function protected by protect register
Count source is selected :f1, f8, f32, fC32
Dead time timer count source is fixed at f1
divided by 2
Watchdog timer
Address match interrupt
Timers A, timer B
Count source
Timer A two-phase pulse
signal processing
Timer
functions
for
three-phase motor control
Serial I/O
(UART0 to UART2)
UART0 to UART2,
SI/O3, SI/O4
Count source
Serial I/O
RTS timing
UART0 to UART2
Overrun error occur timing
Serial I/O
CTS/RTS separate function
UART2 data transmit timing
Serial I/O
Sleep function
Serial I/O
2
I C mode
Serial I/O
2
I C mode
SDA delay
SI/O3, SI/O4
Clock polarity
A/D converter
A/D converter
operation clock
A/D converter input pin
Watchdog timer interrupt
No count source protective mode
Select from f1SIO, f2SIO, f8SIO, f32SIO
(UART, Clock synchronous) x 2
2
TM
(UART, Clock synchronous, I C-bus (Note 2),
TM
IEBus (Note 3)) x 1
Select from f1, f8, f32
Assert low when receive buffer is read
Assert low when reception is completed
This error occurs if the serial I/O started receiving
the next data before reading the UiRB register
(i=0 to 2) and received the 7th bit of the next data
(Clock synchronous).
This error occurs if the serial I/O started receiving
the next data before reading the UiRB register
and received the bit one before the last stop bit of
the next data (UART).
Have
This error occurs when the next data is ready
before contents of UiRB register (i=0 to 2) are
read out
None
After data was written, transfer starts at the 2nd
BRG overflow timing (same as UART0 and
UART1)
None
After data was written, transfer starts at the 1st
BRG overflow timing (Output starts one cycle of
BRG overflow earlier than UART0 and UART1)
Have
Start condition, stop condition: Auto-generation
Only digital delay is selected as SDA delay
SDA digital delay count source: BRG
Start condition, stop condition:
Not auto-generation
Analog or digital delay is selected as SDA delay.
SDA digital delay count source: 1/f(XIN)
Selectable
Fixed
10 bits x 8 channels
Expandable up to 26 channels
Selectable: fAD, fAD divided by 2, 3, 4, 6, 12
10 bits x 8 channels
Expandable up to 10 channels
Selectable: fAD, fAD/2, fAD/4
Select from ports P0, P2, P10
Fixed at port P10
Note 1: About the details and the characteristics, refer to hardware manual.
Note 2: I2C is a trademark of Philips Semiconductors Corporation.
Note 3: IEBus is a trademark of NEC Electronics Corporation.
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August 2004
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M16C/62P, M16C/62M Group
Differences between M16C/62P and M16C/62M
Table 3.1.2 Function differences (flash memory version)(Note1)
Item
User ROM blocks
Program manner
Program command
(Software command)
Block status after program
function
CPU rewrite mode
M16C/62P
M16C/62M
14 blocks: 4 Kbytes X 3, 8 Kbytes X 3,
32 Kbytes X 1, 64 Kbytes X 7
(Flash memory: max. 512 Kbytes)
Word
7 blocks: 8Kbytes X 2, 16 Kbytes X 1,
32 Kbytes X 1, 64 Kbytes X 3
(Flash memory: max. 256 Kbytes)
Page
Page program command: none
Program command: have
(Program method: in units of word, in units of
byte)
None
Page program command: have
Program command: none
(Program method: in units of page)
EW1 mode is available
No EW1 mode
Have
Note 1: About the details and the characteristics, refer to hardware manual.
REJ05B0398-0102Z/Rev.1.02
August 2004
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M16C/62P, M16C/62M Group
Differences between M16C/62P and M16C/62M
3.2 Pin function differences
Table 3.2.1 shows the pin function differences.
Table 3.2.1 Pin function differences
M16C/62P
M16C/62M
VCC1
P8_4/INT2/ZP
P6_7/TxD1/SDA1
P6_6/RxD1/SCL1
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_3/TxD0/SDA0
VCC
P8_4/INT2
P6_7/TxD1
P6_6/RxD1
P6_4/CTS1/RTS1/CLKS1
P6_3/TxD0
P6_2/RxD0/SCL0
VCC2
P2_7/AN2_7/A7(/D7/D6)
P2_6/AN2_6/A6(/D6/D5)
P2_5/AN2_5/A5(/D5/D4)
P2_4/AN2_4/A4(/D4/D3)
P2_3/AN2_3/A3(/D3/D2)
P2_2/AN2_2/A2 (/D2/D1)
P2_1/AN2_1/A1(/D1/D0)
P2_0/AN2_0/A0(/D0/-)
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P6_2/RxD0
VCC
P2_7/A7(/D7/D6)
P2_6/A6(/D6/D5)
P2_5/A5(/D5/D4)
P2_4/A4(/D4/D3)
P2_3/A3(/D3/D2)
P2_2/A2 (/D2/D1)
P2_1/A1(/D1/D0)
P2_0/A0(/D0/-)
P0_7/D7
P0_6/D6
P0_5/D5
P0_4/D4
P0_3/D3
P0_2/D2
P0_1/D1
P0_0/D0
REJ05B0398-0102Z/Rev.1.02
August 2004
Remarks
Add ZP
Add SDA1
Add SCL1
Add CTS0
Add SDA0
Add SCL0
Add AN2_7
Add AN2_6
Add AN2_5
Add AN2_4
Add AN2_3
Add AN2_2
Add AN2_1
Add AN2_0
Add AN0_7
Add AN0_6
Add AN0_5
Add AN0_4
Add AN0_3
Add AN0_2
Add AN0_1
Add AN0_0
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M16C/62P, M16C/62M Group
Differences between M16C/62P and M16C/62M
3.3 SFR differences
Table 3.3.1 show the SFR differences.
Table 3.3.1 SFR differences-1
M16C/62P
M16C/62M
Remarks
PM1
PM1
Change function
CM0
CM0
Change function
CM1
CM1
Add bit1
PRCR
PRCR
Change function
DBR
-
CM2
-
WDC
WDC
VCR1
-
VCR2
-
CSE
-
PLC0
-
PM2
-
D4INT
-
TB4IC,U1BCNIC
TB4IC
Shard with U1BCNIC register
TB3IC,U0BCNIC
TB3IC
Shard with U0BCNIC register
FIDR
-
RMAD2
-
AIER2
-
RMAD3
-
PCLKR
-
Add bit5
INVC1
INVC1
IFSR2A
-
Change function
S3C
S3C
Add bit4
S4C
S4C
Add bit4
U0SMR4
-
U0SMR3
-
U0SMR2
-
U0SMR
-
U1SMR4
-
U1SMR3
-
U1SMR2
-
U1SMR
-
U2SMR4
-
U2SMR3
U2SMR3
Change function
U2SMR2
U2SMR2
Change function
U2SMR
U2SMR
Change function
ONSF
ONSF
Add bit5
TB2SC
-
U0MR
U0MR
Change function
U0C0
U0C0
Change function
U0C1
U0C1
Add Bits6, 7
U1MR
U1MR
Change function
U1C0
U1C0
Change function
REJ05B0398-0102Z/Rev.1.02
August 2004
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M16C/62P, M16C/62M Group
Differences between M16C/62P and M16C/62M
Table 3.3.2 SFR differences-2
M16C/62P
M16C/62M
Remarks
U1C1
U1C1
Add bits6, 7
UCON
UCON
Add bit6
FMR1
FMR1
Address change from 03B6h to 01B5h. Change function.
FMR0
FMR0
Address change from 03B7h to 01B7h. Change function.
ADCON2
ADCON2
Change function
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August 2004
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M16C/62P, M16C/62M Group
Differences between M16C/62P and M16C/62M
3.4 Interrupt vector differences
Table 3.4.1 shows the fixed vector table differences. Table 3.4.2 shows the relocatable vector table differences.
Table 3.4.1 Fixed vector table differences
M16C/62P interrupt source
Watchdog timer
Oscillation stop and re-oscillation detection
Voltage down detection
M16C/62M interrupt source
Watchdog timer
Table 3.4.2 Relocatable vector table differences
M16C/62P interrupt source
M16C/62M interrupt source
Software interrupt
number
Timer B4, UART1 bus collision detect
Timer B3, UART0 bus collision detect
UART0 transmit, NACK0
UART0 receive, ACK0
UART1 transmit, NACK1
UART1 receive, ACK1
REJ05B0398-0102Z/Rev.1.02
Timer B4
Timer B3
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
August 2004
6
7
17
18
19
20
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M16C/62P, M16C/62M Group
Differences between M16C/62P and M16C/62M
3.5 Support tool differences
Table 3.5.1 shows the support tool differences.
Table 3.5.1 support tool differences
Tool information
M16C/62P tool product
M16C/62P tool product
M16C/62M tool product
Change
(Max.24MHz)
(Max.16MHz)
C Compiler
M3T-NC30WA
M3T-NC30WA
M3T-NC30WA
Real-time OS
M3T-MR30
M3T-MR30
M3T-MR30
Simulator Debugger
M3T-PD30SIM
M3T-PD30SIM
M3T-PD30SIM
Emulator Debugger
M3T-PD30F
M3T-PD30
M3T-PD30
√
Emulator
PC7501
PC4701U
PC4701U
√
Emulation Pod,
M3062PT-EPB
M3062PT3-RPD-E
M30620TL-RPD-E
√
Emulation Probe
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August 2004
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M16C/62P, M16C/62M Group
Differences between M16C/62P and M16C/62M
4.
Reference
DATA SHEET
M16C/62M Group data sheet Rev.B1
(Acquire the most current version from Renesas web-site)
HARDWARE MANUAL
M16C/62P Group Hardware manual Rev.2.30
(Acquire the most current version from Renesas web-site)
5.
Web-site and contact for support
Renesas Web-site
http://www.renesas.com
Contact for Renesas technical support
Mail to : support_apl@renesas.com
REJ05B0398-0102Z/Rev.1.02
August 2004
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M16C/62P, M16C/62M Group
Differences between M16C/62P and M16C/62M
REVISION HISTORY
Rev.
Date
Description
Page
Summary
1.00
Jan 16, 2004
-
First edition issued
1.01
Feb 02, 2004
6
Address is revised (FMR0 register, FMR1 register)
1.02
Aug 02,2004
-
Words standardized: On-chip oscillator, and A/D converter
REJ05B0398-0102Z/Rev.1.02
August 2004
Page 10 of 11
M16C/62P, M16C/62M Group
Differences between M16C/62P and M16C/62M
6.
Keep safety first in your circuit designs!
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products
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with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
7.
Notes regarding these materials!
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REJ05B0398-0102Z/Rev.1.02
August 2004
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