CY8C20x36/46/66, CY8C20396 CapSense(TM) Applications

CY8C20X36A/46A/66A/96A
®
CapSense Applications
CapSense Applications
Features
■
Operating Range: 1.71 V to 5.5 V
®
■ Low power CapSense block
❐ Configurable capacitive sensing elements
❐ Supports SmartSense
❐ Supports a combination of CapSense buttons, sliders,
touchpads, touchscreens, and proximity sensors
■ Powerful Harvard-architecture processor
❐ M8C CPU speed can be up to 24 MHz or sourced by an
external crystal, resonator, or clock signal
❐ Low power at high speed
❐ Interrupt controller
❐ Temperature range: –40 °C to +85 °C
■ Flexible on-chip memory
❐ Three program/data storage size options:
• CY8C20x36A: 8 KB flash / 1 KB SRAM
• CY8C20x46A, CY8C20x96A: 16 KB flash/2 KB SRAM
• CY8C20x66A: 32 KB flash/2 KB SRAM
❐ 50,000 flash erase/write cycles
❐ Partial flash updates
❐ Flexible protection modes
❐ In-system serial programming (ISSP)
■ Full-speed USB
❐ Available on CY8C20646A, CY8C20666A, CY8C20x96A
only
❐ 12 Mbps USB 2.0 compliant
❐ Eight unidirectional endpoints
❐ One bidirectional control endpoint
❐ Dedicated 512 byte buffer
❐ Internally regulated at 3.3 V
■ Precision, programmable clocking
❐ Internal main oscillator (IMO): 6/12/24 MHz ± 5%
❐ Internal low speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐ Precision 32 kHz oscillator for optional external crystal
❐ 0.25% accuracy for USB with no external components
(CY8C20646A, CY8C20666A, CY8C20x96A only)
■ Programmable pin configurations
❐ Up to 36 general-purpose I/Os (GPIOs) (depending on
package)
❐ Dual mode GPIO: All GPIOs support digital I/O and analog
inputs
❐ 25-mA sink current on each GPIO
• 120 mA total sink current on all GPIOs
❐ Pull-up, high Z, open-drain modes on all GPIOs
❐ CMOS drive mode – 5 mA source current on ports 0 and 1
and 1 mA on ports 2, 3, and 4
• 20 mA total source current on all GPIOs
❐ Selectable, regulated digital I/O on port 1
❐ Configurable input threshold on port 1
❐ Hot-swap capability on all Port 1 GPIO
Cypress Semiconductor Corporation
Document Number: 001-54459 Rev. *E
•
■
Versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O
❐ High power supply rejection ratio (PSRR) comparator
❐ Low-dropout voltage regulator for all analog resources
■
Additional system resources
2
❐ I C Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• No clock stretching (under most conditions)
• Implementation during sleep modes with less than 100 µA
• Hardware address validation
❐ SPI master and slave: Configurable 46.9 kHz to 12 MHz
❐ Three 16-bit timers
❐ Watchdog and sleep timers
❐ Internal voltage reference
❐ Integrated supervisory circuit
❐ 8 to 10-bit incremental analog-to-digital converter (ADC)
• Not available on CY8x20xx6AN versions
❐ Two general-purpose high speed, low power analog
comparators
■
Complete development tools
❐ Free development tool (PSoC Designer™)
❐ Full-featured, in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■
Package options
❐ CY8C20x36A:
• 16-Pin 3 × 3 × 0.6 mm QFN
• 24-Pin 4 × 4 × 0.6 mm QFN
• 32-Pin 5 × 5 × 0.6 mm QFN
• 48-Pin SSOP
• 48-Pin 7 × 7 × 1.0 mm QFN
❐ CY8C20x46A:
• 16-Pin 3 × 3 × 0.6 mm QFN
• 24-Pin 4 × 4 × 0.6 mm QFN
• 30-Ball WLCSP
• 32-Pin 5 × 5 × 0.6 mm QFN
• 48-Pin SSOP
• 48-Pin 7 × 7 × 1.0 mm QFN (with USB)
❐ CY8C20x96A:
• 24-Pin 4 × 4 × 0.6 mm QFN (with USB)
• 32-Pin 5 × 5 × 0.6 mm QFN (with USB)
❐ CY8C20x66A:
• 32-Pin 5 × 5 × 0.6 mm QFN
• 48-Pin 7 × 7 × 1.0 mm QFN (with USB)
• 48-Pin SSOP
• 30-Ball WLCSP
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 30, 2010
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CY8C20X36A/46A/66A/96A
Logic Block Diagram
Port 4
Port 3
Port 2
Port 1
Port 0
1.8/2.5/3V
LDO
PWRSYS [1]
(Regulator)
PSoC CORE
SYSTEM BUS
Global Analog Interconnect
1K/2K
SRAM
Supervisory ROM (SROM)
Interrupt
Controller
8K/16K/32K Flash
Nonvolatile Memory
Sleep and
Watchdog
CPU Core (M8C)
6/12/24 MHz Internal Main Oscillator
(IMO)
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
CAPSENSE
SYSTEM
Analog
Reference
CapSense
Module
Two
Comparators
Analog
Mux
SYSTEM BUS
USB
I2C
Slave
Internal
Voltage
References
System
Resets
POR
and
LVD
SPI
Master/
Slave
Three 16-Bit
Programmable
Timers
Digital
Clocks
SYSTEM RESOURCES
Note
1. Internal voltage regulator for internal circuitry
Document Number: 001-54459 Rev. *E
Page 2 of 43
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CY8C20X36A/46A/66A/96A
Contents
CapSense Applications .................................................... 1
Features ............................................................................. 1
Logic Block Diagram ........................................................ 2
PSoC® Functional Overview ............................................ 4
PSoC Core .................................................................. 4
CapSense System ....................................................... 4
Additional System Resources ..................................... 5
Getting Started .................................................................. 5
Application Notes ........................................................ 5
Development Kits ........................................................ 5
Training ....................................................................... 5
CYPros Consultants .................................................... 5
Solutions Library .......................................................... 5
Technical Support ....................................................... 5
Designing with PSoC Designer ....................................... 6
Select Components ..................................................... 6
Configure Components ............................................... 6
Organize and Connect ................................................ 6
Generate, Verify, and Debug ....................................... 6
Pinouts .............................................................................. 7
16-Pin QFN (No E-Pad) ............................................ 7
24-Pin QFN .............................................................. 8
24-Pin QFN with USB ................................................. 9
30-Ball Part Pinout .................................................... 10
32-Pin QFN ............................................................. 11
32-Pin QFN (with USB) ............................................ 12
48-Pin SSOP ............................................................ 13
48-Pin QFN ............................................................. 14
48-Pin QFN with USB .............................................. 15
48-Pin QFN OCD ...................................................... 16
Electrical Specifications ................................................ 17
Absolute Maximum Ratings ....................................... 17
Operating Temperature ............................................. 17
DC Chip-Level Specifications .................................... 18
DC GPIO Specifications ............................................ 19
DC Analog Mux Bus Specifications ........................... 21
DC Low Power Comparator Specifications ............... 21
Document Number: 001-54459 Rev. *E
Comparator User Module Electrical Specifications ... 22
ADC Electrical Specifications ................................... 22
DC POR and LVD Specifications .............................. 23
DC Programming Specifications ............................... 23
AC Chip-Level Specifications .................................... 24
AC General Purpose I/O Specifications .................... 25
AC Comparator Specifications .................................. 26
AC External Clock Specifications .............................. 26
AC Programming Specifications ................................ 27
AC I2C Specifications ................................................ 28
Packaging Information ................................................... 31
Thermal Impedances ................................................ 34
Capacitance on Crystal Pins .................................... 34
Solder Reflow Peak Temperature ............................. 34
Development Tool Selection ......................................... 35
Software .................................................................... 35
Development Kits ...................................................... 35
Evaluation Tools ............................................................. 36
Device Programmers ................................................. 36
Accessories (Emulation and Programming) .............. 37
Third Party Tools ....................................................... 37
Build a PSoC Emulator into Your Board .................... 37
Ordering Information ...................................................... 38
Ordering Code Definitions ............................................ 39
Acronymns ...................................................................... 40
Acronyms Used ......................................................... 40
Reference Documents .................................................... 40
Document Conventions ............................................. 40
Units of Measure ....................................................... 40
Numeric Naming ........................................................ 41
Glossary .......................................................................... 41
Document History Page ................................................. 42
Sales, Solutions, and Legal Information ...................... 43
Worldwide Sales and Design Support ....................... 43
Products .................................................................... 43
PSoC Solutions ......................................................... 43
Page 3 of 43
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CY8C20X36A/46A/66A/96A
PSoC® Functional Overview
Figure 1. CapSense System Block Diagram
The PSoC family consists of on-chip controller devices, which
are designed to replace multiple traditional microcontroller unit
(MCU)-based components with one, low cost single-chip
programmable component. A PSoC device includes
configurable analog and digital blocks, and programmable
interconnect. This architecture allows the user to create
customized peripheral configurations, to match the requirements
of each individual application. Additionally, a fast CPU, Flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
CS1
IDAC
The Core
■
CapSense Analog System
■
System Resources (including a full-speed USB port).
Analog Global Bus
CSN
Vr
The architecture for this device family, as shown in the Logic
Block Diagram on page 2, consists of three main areas:
■
CS2
Reference
Buffer
Cinternal
Cexternal (P0[1]
or P0[3])
Comparator
Mux
A common, versatile bus allows connection between I/O and the
analog system.
Mux
Each CY8C20x36A/46A/66A/96A PSoC device includes a
dedicated CapSense block that provides sensing and scanning
control circuitry for capacitive sensing applications. Depending
on the PSoC package, up to 36 GPIO are also included. The
GPIO provides access to the MCU and analog mux.
Refs
Cap Sense Counters
CSCLK
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO and
ILO. The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-MIPS,
8-bit Harvard-architecture microprocessor.
CapSense System
The analog system contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. The analog system is composed of the
CapSense PSoC block and an internal 1 V or 1.2 V analog
reference, which together support capacitive sensing of up to
33 inputs[2]. Capacitive sensing is configurable on each GPIO
pin. Scanning of enabled CapSense pins are completed quickly
and easily across multiple ports.
SmartSense™
SmartSense is an innovative solution from Cypress that removes
manual tuning of CapSense applications. This solution is easy to
use and provides a robust noise immunity. It is the only autotuning solution that establishes, monitors, and maintains all
required tuning parameters. SmartSense allows engineers to go
from prototyping to mass production without re-tuning for
manufacturing variations in PCB and/or overlay material
properties.
IMO
CapSense
Clock Select
Oscillator
Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
Complex capacitive sensing interfaces, such as sliders and
touchpads.
■
Chip-wide mux that allows analog input from any I/O pin.
■
Crosspoint connection between any I/O pin combinations.
Note
2. 36 GPIOs = 33 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
Document Number: 001-54459 Rev. *E
Page 4 of 43
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CY8C20X36A/46A/66A/96A
Additional System Resources
System resources provide additional capability, such as
configurable USB and I2C slave, SPI master/slave
communication interface, three 16-bit programmable timers, and
various system resets supported by the M8C.
These system resources provide additional capability useful to
complete systems. Additional resources include low voltage
detection and power on reset. The merits of each system
resource are listed here:
■
The I2C slave/SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
■
The I2C hardware address recognition feature reduces the
already low power consumption by eliminating the need for
CPU intervention until a packet addressed to the target device
is received.
■
■
The I2C enhanced slave interface appears as a 32-byte RAM
buffer to the external I2C master. Using a simple predefined
protocol, the master controls the read and write pointers into
the RAM. When this method is enabled, the slave does not stall
the bus when receiving data bytes in active mode. For usage
details, refer to the application note I2C Enhanced Slave
Operation - AN56007.
Low-voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced poweron-reset (POR) circuit eliminates the need for a system
supervisor.
■
An internal reference provides an absolute reference for
capacitive sensing.
■
A register-controlled bypass mode allows the user to disable
the LDO regulator.
Getting Started
The quickest way to understand PSoC silicon is to read this
datasheet and then use the PSoC Designer Integrated
Development Environment (IDE). This datasheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications.
For in depth information, along with detailed programming
details, see the Technical Reference Manual for the
CY8C20x36A/46A/66A/96A PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at www.cypress.com/psoc.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located at
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet, DigiKey, Farnell, Future Electronics, and Newark. Refer to
Development Kits on page 35.
Training
Free PSoC and CapSense technical training (on demand,
webinars, and workshops) is available online at
www.cypress.com/training. The training covers a wide variety of
topics and skill levels to assist you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, create a technical support case
or call technical support at 1-800-541-4736.
Document Number: 001-54459 Rev. *E
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CY8C20X36A/46A/66A/96A
Designing with PSoC Designer
Organize and Connect
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
You build signal chains by interconnecting user modules to each
other and the I/O pins. You perform the selection, configuration,
and routing so that you have complete control over the use of all
on-chip resources.
These configurable resources, called PSoC blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process is summarized in the following
four steps:
1. Select components
2. Configure components
3. Organize and connect
4. Generate, verify, and debug
When you are ready to test the hardware configuration or move
to developing code for the project, you perform the ‘Generate
Configuration Files’ step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system.
Based on your design, software is generated. Application
programming interfaces (APIs) are provided with high level
functions to control and respond to hardware events at run time
and interrupt service routines that you can adapt as needed.
Select Components
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both. The last step in the development process
takes place inside PSoC Designer’s Debugger (access by
clicking the Connect icon). PSoC Designer downloads the HEX
image to the ICE where it runs at full speed. PSoC Designer
debugging capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the debug interface provides a large
trace buffer and allows you to define complex breakpoint events
that include monitoring address and data bus values, memory
locations and external signals.
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components. These components are called user
modules. User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
programmable system-on-chip varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Timer
User Module configures one digital PSoC block. The user
module parameters permit you to establish the period, mode,
and timer clock. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
Generate, Verify, and Debug
User modules are documented in datasheets that are viewed
directly in PSoC Designer. These datasheets explain the internal
operation of the component and provide performance
specifications. Each datasheet describes the use of each user
module parameter and other information you may need to
successfully implement your design.
Document Number: 001-54459 Rev. *E
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CY8C20X36A/46A/66A/96A
Pinouts
The CY8C20x36A/46A/66A/96A PSoC device is available in a variety of packages, which are listed and illustrated in the following
tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, and
XRES are not capable of Digital I/O.
16-Pin QFN (No E-Pad)
Table 1. Pin Definitions – CY8C20236A, CY8C20246A PSoC Device
I/O
I
P2[3] Crystal input (XIn)
3
IOHR
I
P1[7] I2C SCL, SPI SS
2
4
IOHR
I
P1[5] I C SDA, SPI MISO
5
IOHR
I
P1[3] SPI CLK
6
IOHR
I
P1[1] ISSP CLK[3], I2C SCL, SPI
MOSI
7
Power
VSS
IOHR
I
P1[0] ISSP DATA[3], I2C SDA, SPI
CLK[4]
9
IOHR
I
P1[2]
10
IOHR
I
P1[4] Optional external clock
(EXTCLK)
12
13
Input
IOH
AI , XIn, P2[3]
AI , I2 C SCL, SPI SS, P1[7]
AI , I2 C SDA, SPI MISO, P1[5]
Ground connection
8
11
AI, XOut, P2[5]
XRES Active high external reset with
internal pull-down
I
Power
P0[4]
VDD
Supply voltage
14
IOH
I
P0[7]
15
IOH
I
P0[3] Integrating input
16
IOH
I
P0[1] Integrating input
1
2
3
4
14
13
2
P0[1], AI
P0[3], AI
P0[7], AI
Vdd
P2[5] Crystal output (XOut)
16
15
I
Figure 2. CY8C20236A, CY8C20246A PSoC Device
12
QFN
( Top View) 11
10
9
5
6
7
8
Analog
I/O
Description
P0[4] , AI
XRES
P1[4] , EXTCLK, AI
P1[2] , AI
AI, SPI CLK , P1[3]
AI, ISSP CLK, SPI MOSI, P1[1]
Vss
[3,4]
AI, ISSP DATA , I2C SDA, SPI CLK , P1[0]
Digital
1
Name
[3]
Type
Pin
No.
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
3. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
4. Alternate SPI clock.
Document Number: 001-54459 Rev. *E
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CY8C20X36A/46A/66A/96A
24-Pin QFN
Table 2. Pin Definitions š CY8C20336A, CY8C20346A [5]
7
IOHR
I
P1[1]
ISSP CLK[6], I2C SCL, SPI
MOSI
NC
No connection
VSS
Ground connection
ISSP DATA[6], I2C SDA, SPI
CLK[7]
9
Power
10
IOHR
I
P1[0]
11
IOHR
I
P1[2]
12
IOHR
I
P1[4]
13
IOHR
I
P1[6]
14
Input
XRES
15
I/O
I
P2[0]
16
IOH
I
P0[0]
17
IOH
I
P0[2]
18
IOH
I
P0[4]
19
IOH
I
P0[6]
20
VDD
Power
Active high external reset with
internal pull-down
QFN
(T o p V ie w )
16
15
5
14
6
13
Supply voltage
IOH
I
P0[7]
22
IOH
I
P0[5]
23
IOH
I
P0[3]
Integrating input
24
IOH
I
P0[1]
Integrating input
VSS
Center pad must be connected
to ground
Power
3
4
Optional external clock input
(EXTCLK)
21
CP
P 2 [1 ]
P 1 [7 ]
P 1 [5 ]
P 1 [3 ]
P 0 [4 ], A I
P 0 [2 ], A I
P 0 [0 ], A I
P 2 [0 ], A I
XRES
P 1 [6 ], A I
[6, 7]
8
A I,
A I, I2 C S C L , S P I S S ,
A I, I2 C S D A , S P I M IS O ,
A I, S P I C L K ,
Vdd
SPI CLK
P0[6], AI
P1[3]
19
I
18
17
2
12
IOHR
1
AI, EXTCLK, P1[4]
6
A I, X O u t, P 2 [5]
A I, X In , P 2 [3 ]
P0[7], AI
I2C SDA, SPI MISO
20
P1[5]
11
I
AI, P1[2]
IOHR
P0[5], AI
5
21
I2C SCL, SPI SS
22
P1[7]
9
I
10
IOHR
Vss
4
2
Crystal input (XIn)
P2[1]
AI, ISSP DATA , I2C SDA, SPI CLK, P1[0]
P2[3]
I
P0[1], AI
I
I/O
P0[3], AI
I/O
3
24
2
23
Crystal output (XOut)
8
P2[5]
7
I
NC
I/O
2
1
Figure 3. CY8C20336A, CY8C20346A PSoC Device
SPI MOSI, P1[1]
Description
AI, ISSP CLK , I2C SCL
Type
Pin
No. Digital Analog Name
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
5. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
6. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
7. Alternate SPI clock.
Document Number: 001-54459 Rev. *E
Page 8 of 43
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CY8C20X36A/46A/66A/96A
24-Pin QFN with USB
Table 3. Pin Definitions – CY8C20396A PSoC Device [8]
Name
Description
1
I/O
I
P2[5]
2
I/O
I
P2[3]
3
I/O
I
P2[1]
4
IOHR
I
P1[7]
I2C SCL, SPI SS
5
IOHR
I
P1[5]
I2C SDA, SPI MISO
6
IOHR
I
P1[3]
SPI CLK
VSS
Ground
9
I/O
I
D+
USB D+
10
I/O
I
D-
USB D-
VDD
Supply
12
IOHR
Power
I
P1[0]
ISSP DATA[9], I2C SDA, SPI
CLK[10]
13
IOHR
I
P1[2]
14
IOHR
I
P1[4]
15
IOHR
I
16
RESET INPUT
IOH
I
P0[0]
IOH
I
P0[2]
19
IOH
I
P0[4]
20
IOH
I
P0[6]
21
IOH
I
P0[7]
22
IOH
I
P0[5]
23
IOH
I
P0[3]
Integrating input
24
IOH
I
P0[1]
Integrating input
VSS
19
21
20
22
24
23
13
Active high external reset with
internal pull-down
18
Power
14
6
Optional external clock input
(EXTCLK)
17
CP
5
P1[6]
XRES
16
(Top View) 15
[9]
11
QFN
3
4
P0[2], AI
P0[0], AI
XRES
P1[6], AI
P1[4] , AI, EXTCLK
P1[2 ], AI
AI, ISSP DATA, I2C SDA, SPI CLK, P1[0]
ISSP CLK , I C SCL, SPI
MOSI
17
[9, 10]
Power
P1[1]
P2[1], AI
AI, I 2 C SCL, SPI SS,P1[7]
AI, I2C SDA , SPI MISO,P1[5]
AI, SPI CLK ,P1[3]
18
2
11
12
I
2
1
9
10
8
IOHR
[9]
P2[5], AI
P2[3], AI
8
7
Figure 4. CY8C20396A PSoC Device
P0[1], AI
P0[3], AI
P0[5], AI
P0[7], AI
P0[6], AI
P0[4], AI
Analog
7
Type
Digital
AI, ISSP CLK, I2C SCL, SPI MOSI, P1[1]
Vss
D+
DVDD
Pin No.
Thermal pad must be
connected to Ground
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Notes
8. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
9. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
10. Alternate SPI clock.
Document Number: 001-54459 Rev. *E
Page 9 of 43
[+] Feedback
CY8C20X36A/46A/66A/96A
30-Ball Part Pinout
Table 4. Pin Definitions – CY8C20766A, CY8C20746A 30-Ball Part Pinout (WLCSP)
Pin No.
Type
Name
Digital
Analog
A1
IOH
I
P0[2]
A2
IOH
I
P0[6]
A3
Description
Figure 5. CY8C20766A 30-Ball WLCSP
Power
Bottom View
5
VDD
Supply voltage
Integrating Input
A4
IOH
I
P0[1]
A5
I/O
I
P2[7]
B1
I/O
I
P2[6]
B2
IOH
I
P0[0]
B3
IOH
I
P0[4]
B4
IOH
I
P0[3]
Integrating Input
B5
I/O
I
P2[5]
Crystal Output (Xout)
C1
I/O
I
P2[2]
C2
I/O
I
P2[4]
C3
IOH
I
P0[7]
C4
IOH
I
P0[5]
C5
I/O
I
P2[3]
D1
I/O
I
P2[0]
D2
I/O
I
P3[0]
D3
I/O
I
P3[1]
D4
I/O
I
P3[3]
D5
I/O
I
P2[1]
E1
Input
XRES
1
A
D
E
F
Top View
1
Crystal Input (Xin)
2
3
4
5
A
B
C
Active high external reset with
internal pull-down
I
P1[6]
E3
IOHR
I
P1[4]
Optional external clock input
(EXT CLK)
E4
IOHR
I
P1[7]
I2C SCL, SPI SS
E5
IOHR
I
P1[5]
I2C SDA, SPI MISO
F1
IOHR
I
P1[2]
F2
IOHR
I
P1[0]
VSS
2
C
IOHR
Power
3
B
E2
F3
4
D
E
F
ISSP DATA[11], I2C SDA, SPI
CLK[12]
Supply ground
F4
IOHR
I
P1[1]
ISSP CLK[11], I2C SCL, SPI
MOSI
F5
IOHR
I
P1[3]
SPI CLK
Notes
11. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
12. Alternate SPI clock.
Document Number: 001-54459 Rev. *E
Page 10 of 43
[+] Feedback
CY8C20X36A/46A/66A/96A
32-Pin QFN
Table 5. Pin Definitions – CY8C20436A, CY8C20446A, CY8C20466A PSoC Device [13]
P2[5]
Crystal output (XOut)
4
I/O
I
P2[3]
Crystal input (XIn)
5
I/O
I
P2[1]
6
I/O
I
P3[3]
7
I/O
I
P3[1]
8
IOHR
I
P1[7]
I C SCL, SPI SS
9
IOHR
I
P1[5]
I2C SDA, SPI MISO
10
IOHR
I
P1[3]
SPI CLK.
11
IOHR
I
P1[1]
ISSP CLK[14], I2C SCL, SPI MOSI.
12
VSS
Ground connection.
13
IOHR
Power
I
P1[0]
ISSP DATA[14], I2C SDA,
SPI CLK[15]
14
IOHR
I
P1[2]
15
IOHR
I
P1[4]
16
IOHR
I
P1[6]
17
Input
XRES
I/O
I
P3[0]
19
I/O
I
P3[2]
20
I/O
I
P2[0]
21
I/O
I
P2[2]
22
I/O
I
P2[4]
23
I/O
I
P2[6]
24
IOH
I
P0[0]
25
IOH
I
P0[2]
26
IOH
I
P0[4]
27
IOH
I
P0[6]
Vss
P0 [3 ], AI
P0 [5 ], AI
32
31
Active high external reset with
internal pull-down
QFN
( Top View)
[14]
18
Optional external clock input
(EXTCLK)
1
2
3
4
5
6
7
8
9
2
AI, P0[1]
AI, P2[7]
AI , XOut, P2[5]
AI, XIn, P2[3]
AI, P2[1]
AI, P3[3]
AI, P3[1]
AI, I2 C SCL, SPI SS, P1[7]
28
Power
VDD
P0 [4 ], AI
P0 [2 ], AI
P2[7]
I
26
25
I
I/O
24
23
22
21
20
19
18
17
15
16
I/O
3
Integrating input
AI, E XTCLK, P 1[4]
AI, P 1[6]
2
P0[1]
P0 [7 ], AI
Vd d
P0 [6 ], AI
I
28
27
IOH
PSoC Device
13
14
1
Figure 6. CY8C20436A, CY8C20446A, CY8C20466A
30
29
Description
A I,ISSP CLK , I2C SCL, SPI MOSI, P1[1]
Vss
[14]
AI , ISSP DATA , I2C SDA, SPI CLK, P1[0]
AI, P 1[2]
Name
Analog
10
11
12
Type
Digital
AI, I2C SDA, SPI MISO, P 1[5]
AI, SPI CLK, P 1[3]
Pin
No.
P0[0] , AI
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[2] , AI
P3[0] , AI
XRES
Supply voltage
29
IOH
I
P0[7]
30
IOH
I
P0[5]
31
IOH
I
P0[3]
Integrating input
32
Power
VSS
Ground connection
CP
Power
VSS
Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
13. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
14. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
15. Alternate SPI clock.
Document Number: 001-54459 Rev. *E
Page 11 of 43
[+] Feedback
CY8C20X36A/46A/66A/96A
32-Pin QFN (with USB)
Table 6. Pin Definitions – CY8C20496A PSoC Device [16]
XTAL In
4
I/O
I
P2[1]
5
IOHR
I
P1[7]
I2C SCL, SPI SS
QFN
6
IOHR
I
P1[5]
I C SDA, SPI MISO
7
IOHR
I
P1[3]
SPI CLK
8
IOHR
I
P1[1]
ISSP CLK[17], I2C SCL, SPI MOSI
Ground Pin
9
XTAL IN , P2[ 3]
AI , P2[ 1]
I2C SCL, SPI SS , P 1[ 7]
I2C SDA, SPI MISO , P 1[ 5]
1
2
3
4
5
6
7
8
Vss
USB PHY, D+
2
AI , P 0[ 1]
XTAL OUT, P 2 [ 5]
Power
VSS
10
I
I
D+
USB D+
D-
USB D-
11
12
VDD
Power pin
13
IOHR
Power
I
P1[0]
ISSP DATA[17], I2C SDA, SPI
CLKI[18]
14
IOHR
I
P1[2]
15
IOHR
I
P1[4]
16
IOHR
I
P1[6]
17
Input
XRES
18
I/O
I
P3[0]
19
I/O
I
P3[2]
20
I/O
I
P2[0]
21
I/O
I
P2[2]
22
I/O
I
P2[4]
23
I/O
I
P2[6]
24
IOH
I
P0[0]
25
IOH
I
P0[2]
26
IOH
I
P0[4]
27
IOH
I
P0[6]
28
Power
VDD
Optional external clock input
(EXTCLK)
Active high external reset with
internal pull-down
IOH
I
P0[7]
30
IOH
I
P0[5]
31
IOH
I
P0[3]
Integrating Input
VSS
Ground Pin
Power
24
23
22
21
20
19
18
17
P0[0] , AI
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[2] , AI
P3[0] , AI
XRES
Power Pin
29
32
( Top View)
10
11
12
9
SPI CLK , P1[3]
[17]
ISSP CLK, I2C SCL, SPI MOSI,P1[ 1 ]
P0 [4], AI
P0 [2], AI
XTAL Out
P2[3]
26
25
P2[5]
I
15
16
I
I/O
AI, P 1[2]
I/O
3
AI, E XTCLK, P 1[4]
AI, P 1[6]
2
28
27
Integrating Input
13
14
P0[1]
30
29
I
Vdd
ISSP
, DATA, I2C SDA, SPI CLK, P1[0]
IOH
USB D-
1
P0 [7], AI
Vd d
P0 [6], AI
Figure 7. CY8C20496A PSoC Device
Description
[17, 18]
Name
Analog
Vss
P0 [3], AI
P0 [5], AI
Type
Digital
32
31
Pin
No.
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
16. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
17. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
18. Alternate SPI clock.
Document Number: 001-54459 Rev. *E
Page 12 of 43
[+] Feedback
CY8C20X36A/46A/66A/96A
48-Pin SSOP
I
I
I
I
I
I
I
I
IOHR
IOHR
IOHR
I
I
I
IOHR
I
P1[6]
NC
NC
NC
NC
No connection
No connection
No connection
33
34
35
SSOP
VDD
P0[6] , AI
P0[4] , AI
P0[2] , AI
P0[0] , AI
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[6] , AI
P3[4] , AI
P3[2] , AI
P3[0] , AI
XRES
NC
NC
NC
NC
NC
NC
P1[6] , AI
P1[4] , EXT CLK
P1[2] , AI
[19, 20]
P1[0] , ISSP DATA, I2C SDA, SPI CLK
No connection
No connection
I2C SCL, SPI SS
I2C SDA, SPI MISO
SPI CLK
ISSP CLK[19], I2C SCL, SPI MOSI
Ground Pin
ISSP DATA[19], I2C SDA, SPI CLK[20]
Optional external clock input
(EXT CLK)
No connection
No connection
No connection
No connection
Pin No.
IOHR
IOHR
IOHR
IOHR
XTAL Out
XTAL In
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Description
I/O
I/O
I/O
I/O
Integrating Input
Integrating Input
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
I
I
AI, P0[7]
AI, P0[5]
AI, P0[3]
AI P0[1]
AI, P2[7]
XTALOUT, P2[5]
XTALIN, P2[3]
AI , P2[1]
NC
NC
AI, P4[3]
AI, P4[1]
NC
AI, P3[7]
AI, P3[5]
AI, P3[3]
AI, P3[1]
NC
NC
I2 C SCL, SPI SS, P1[7]
I2 C SDA, SPI MISO, P1[5 ]
SPI CLK, P1[3]
[19]
ISSP CLK, I2 C SCL, SPI MOSI, P1[1 ]
VSS
Analog
I/O
I/O
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
NC
NC
P4[3]
P4[1]
NC
P3[7]
P3[5]
P3[3]
P3[1]
NC
NC
P1[7]
P1[5]
P1[3]
P1[1]
VSS
P1[0]
P1[2]
P1[4]
Digital
28
29
30
31
32
I
I
I
I
I
I
I
I
Figure 8. CY8C20536A, CY8C20546A, and CY8C20566A
PSoC Device
Description
IOH
IOH
IOH
IOH
I/O
I/O
I/O
I/O
Name
Digital
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Analog
Pin No.
Table 7. Pin Definitions – CY8C20536A, CY8C20546A, and CY8C20566A PSoC Device[19]
NC
NC
XRES
No connection
41
I/O
I
P2[2]
No connection
42
I/O
I
P2[4]
Active high external reset with internal pull- 43
I/O
I
P2[6]
down
36 I/O
I
P3[0]
44
IOH I
P0[0]
37 I/O
I
P3[2]
45
IOH I
P0[2]
38 I/O
I
P3[4]
46
IOH I
P0[4]
39 I/O
I
P3[6]
47
IOH I
P0[6]
40 I/O
I
P2[0]
48
Power
VDD
Power Pin
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
Notes
19. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
20. Alternate SPI clock.
Document Number: 001-54459 Rev. *E
Page 13 of 43
[+] Feedback
CY8C20X36A/46A/66A/96A
48-Pin QFN
I/O
I/O
I/O
I
I
I
P3[0]
P3[2]
P3[4]
30
31
32
33
34
35
36
37
38
39
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOH
IOH
IOH
I
I
I
I
I
I
I
I
I
I
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P0[1], AI
Vss
P0[3], AI
P0[5], AI
P0[7], AI
NC
NC
Supply voltage
ISSP DATA[21], I2C SDA, SPI
CLK[23]
P2[6] ,AI
P2[4] AI
,
P2[2] ,AI
P2[0] AI
,
P4[2] ,AI
P4[0] ,AI
P3[6] ,AI
P3[4] , AI
P3[2] ,AI
P3[0] , AI
XRES
P1[6] , AI
Optional external clock input
(EXTCLK)
Active high external reset with
internal pull-down
Pin No.
27
28
29
36
35
34
33
32
31
30
29
28
27
26
25
40
41
42
43
44
45
46
47
48
CP
IOH
I
Power
IOH
I
IOH
I
IOH
I
Power
IOH
I
Power
Description
P1[6]
XRES
42
41
40
39
38
37
IOHR
I
Input
48
47
46
45
44
43
25
26
SCL, SPI SS
I2C SDA, SPI MISO
No connection
No connection
SPI CLK
ISSP CLK[21], I2C SCL, SPI MOSI
Ground connection
QFN
( Top View
)
13
14
15
16
17
18
19
20
21
22
23
24
P1[2]
P1[4]
I
I
I2C
1
2
3
4
5
6
7
8
9
10
11
12
I2C SDA, SPI MISO, A I, P1[5]
NC
NC
SPI CLK, AI, P1[3]
[21]
AI, ISSP CLK, I2C SCL, SPI MOSI, P1[1]
Vss
DNU
DNU
[21, 23]
Vdd
AI, ISSP DATA1 , I2C SDA, SPI CLK, P1[0]
AI, P1[2]
AI, EXTCLK, P1[4]
IOHR
IOHR
NC
AI ,P2[7]
AI , XOut,P2[5]
AI , XIn ,P2[3]
AI ,P2[1]
AI ,P4[3]
AI ,P4[1]
AI ,P3[7]
AI ,P3[5]
AI ,P3[3]
AI P3[1]
AI ,I2 C SCL, SPI SS,P1[7]
Crystal output (XOut)
Crystal input (XIn)
Name
23
24
IOHR
I
IOHR
I
Power
No connection
Analog
Power
IOHR
I
NC
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
NC
NC
P1[3]
P1[1]
VSS
DNU
DNU
VDD
P1[0]
Digital
I
I
I
I
I
I
I
I
I
I
I
I
Figure 9. CY8C20636A PSoC Device
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOHR
IOHR
Name
Analog
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Digital
Pin No.
Table 8. Pin Definitions – CY8C20636A PSoC Device [21, 22]
P0[6]
VDD
NC
NC
P0[7]
P0[5]
P0[3]
VSS
P0[1]
VSS
Supply voltage
No connection
No connection
Integrating input
Ground connection
Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Notes
21. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
22. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal
23. Alternate SPI clock.
Document Number: 001-54459 Rev. *E
Page 14 of 43
[+] Feedback
CY8C20X36A/46A/66A/96A
48-Pin QFN with USB
42
41
40
39
38
37
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
NC
NC
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P0[1], AI
48
47
46
45
44
43
QFN
( Top View)
13
14
15
16
17
18
19
20
21
22
23
24
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
P2[6] , AI
P2[4] ,AI
P2[2] ,AI
P2[0] ,AI
P4[2] ,AI
P4[0] ,AI
P3[6] ,AI
P3[4] , AI
P3[2] ,AI
P3[0] , AI
XRES
P1[6] , AI
I2C SDA, SPI MISO, A I, P1[5]
NC
NC
SPI CLK, A I, P1[3]
[24]
AI,ISSP CLK , I2C SCL, SPI MOSI, P1[1]
Vss
D+
DVdd
[24, 26]
AI ,ISSP DATA, I2C SDA, SPI CLK, P1[0]
AI, P 1[2]
AI, EXTCLK, P1[4]
I2C SCL, SPI SS
I2C SDA, SPI MISO
No connection
No connection
SPI CLK
ISSP CLK[24], I2C SCL, SPI MOSI
Ground connection
USB D+
USB DSupply voltage
ISSP DATA[24], I2C SDA, SPI CLK[26]
1
2
3
4
5
6
Optional external clock input (EXTCLK)
Active high external reset with internal
pull-down
P3[0]
P3[2]
P3[4]
Description
I
I
I
NC
AI , P2[7]
AI, XOut, P2[5]
AI, XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI , P3[5]
AI , P3[3]
AI , P3[1]
AI, I2 C SCL, SPI SS, P1[7]
Crystal output (XOut)
Crystal input (XIn)
Name
I/O
I/O
I/O
I
I
I
I
No connection
Analog
I
I
NC
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
NC
NC
P1[3]
P1[1]
VSS
D+
DVDD
P1[0]
P1[2]
P1[4]
P1[6]
XRES
Digital
IOHR
IOHR
Power
I/O
I/O
Power
IOHR
IOHR
IOHR
IOHR
Input
Description
I
I
I
I
I
I
I
I
I
I
I
I
Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOHR
IOHR
Pin No.
27
28
29
Analog
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Digital
Pin No.
Table 9. Pin Definitions – CY8C20646A, CY8C20666A PSoC Device [24, 25]
Figure 10. CY8C20646A, CY8C20666A PSoC Device
30
I/O
I
P3[6]
40
IOH
I
P0[6]
31
I/O
I
P4[0]
41
Power
VDD
Supply voltage
32
I/O
I
P4[2]
42
NC
No connection
33
I/O
I
P2[0]
43
NC
No connection
34
I/O
I
P2[2]
44
IOH
I
P0[7]
35
I/O
I
P2[4]
45
IOH
I
P0[5]
36
I/O
I
P2[6]
46
IOH
I
P0[3]
Integrating input
37
IOH
I
P0[0]
47
Power
VSS
Ground connection
38
IOH
I
P0[2]
48
IOH
I
P0[1]
39
IOH
I
P0[4]
CP
Power
VSS
Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Notes
24. On Power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
resistive low for 512 sleep clock cycles and both the pins transition to High impedance state . On reset, after XRES de- asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance
(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
25. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
26. Alternate SPI clock.
Document Number: 001-54459 Rev. *E
Page 15 of 43
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CY8C20X36A/46A/66A/96A
48-Pin QFN OCD
The 48-pin QFN part is for the CY8C20066A On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit
debugging.
P1[2]
24
IOHR
I
P1[4]
25
26
IOHR
I
Input
P3[0]
P3[2]
P3[4]
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P2[6]
Name
I
I
I
I
I
I
I
I
I
I
Analog
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Active high external reset with
internal pull-down
Digital
27
28
29
30
31
32
33
34
35
36
P1[6]
XRES
OCDO
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
42
41
40
39
38
37
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
OCDE
48
47
46
45
44
43
P0[1], AI
I2C SCL, SPI SS
I2C SDA, SPI MISO
OCD CPU clock output
OCD high speed clock output
SPI CLK.
ISSP CLK[29], I2C SCL, SPI MOSI
Ground connection
USB D+
USB DSupply voltage
ISSP DATA[29], I2C SDA, SPI
CLK[30]
Optional external clock input
(EXTCLK)
QFN
7
8
9
10
11
12
( Top View)
36
35
34
33
32
31
30
29
28
27
26
25
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P4[2] , AI
P4[0] , AI
P3[6] , AI
P3[4] , AI
P3[2] , AI
P3[0] , AI
XRES
P1[6] , AI
37
IOH
I
P0[0]
38
39
IOH
IOH
I
I
P0[2]
P0[4]
40
41
42
43
44
45
46
47
48
CP
IOH
I
Power
IOH
IOH
IOH
Power
IOH
Power
I
I
I
I
P0[6]
VDD
OCDO
OCDE
P0[7]
P0[5]
P0[3]
VSS
P0[1]
VSS
Description
I
Crystal output (XOut)
Crystal input (XIn)
1
2
3
4
5
6
13
14
15
16
17
18
19
20
21
22
23
24
IOHR
I
I
I
I
I
I
I
I
I
I
I
I
OCDO
A E
, P2[7]
I
AI, XOut, P2[5]
AI, XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI, P3[5]
AI, P3[3]
AI, P3[1]
AI, I2 C SCL, SPI SS, P1[7]
OCD mode direction pin
I2C SDA, SPI MISO, AI, P1[5]
CCLK
HCLK
SPI CLK, A I, P1[3]
[29]
AI,ISSP CLK6, I2C SCL, SPI MOSI, P1[1]
Vss
D+
D[29, 30]
Vdd
AI,ISSP DATA1, I2C SDA, SPI CLK, P1[0]
AI, P 1[2]
AI, EXTCLK, P1[4]
23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOHR
IOHR
Description
Name
Analog
IOHR
I
IOHR
I
Power
I/O
I/O
Power
IOHR
I
OCDOE
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
CCLK
HCLK
P1[3]
P1[1]
VSS
D+
DVDD
P1[0]
Figure 11. CY8C20066A PSoC Device
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Digital
Pin No.
Table 10. Pin Definitions – CY8C20066A PSoC Device [27, 28]
Supply voltage
OCD even data I/O
OCD odd data output
Integrating input
Ground connection
Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Notes
27. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.
28. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
29. On Power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
resistive low for 512 sleep clock cycles and both the pins transition to High impedance state . On reset, after XRES de- asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance
(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
30. Alternate SPI clock.
Document Number: 001-54459 Rev. *E
Page 16 of 43
[+] Feedback
CY8C20X36A/46A/66A/96A
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20x36A/46A/66A/96A PSoC devices. For the latest electrical
specifications, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc.
Figure 12. Voltage versus CPU Frequency
5.5V
Vdd Voltage
li d ng
Va rati n
e io
Op Reg
1.71V
750 kHz
3 MHz
CPU
24 MHz
Frequency
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 11. Absolute Maximum Ratings
Symbol
Description
Conditions
Min
Typ
Max
Units
TSTG
Storage temperature
Higher storage temperatures reduce data
retention time. Recommended Storage
Temperature is +25 °C ± 25 °C. Extended
duration storage temperatures above 85 °C
degrades reliability.
–55
+25
+125
°C
VDD
Supply voltage relative to VSS
–
–0.5
–
+6.0
V
VIO
DC input voltage
–
VSS – 0.5
–
VDD + 0.5
V
VIOZ
DC voltage applied to tristate
–
VSS – 0.5
–
VDD + 0.5
V
IMIO
Maximum current into any port pin
–
–25
–
+50
mA
ESD
Electro static discharge voltage
Human body model ESD
2000
–
–
V
LU
Latch-up current
In accordance with JESD78 standard
–
–
200
mA
Min
Typ
Max
Units
–
+85
°C
70
°C
+100
°C
Operating Temperature
Table 12. Operating Temperature
Symbol
Description
Conditions
TA
Ambient temperature
–
–40
TC
Commercial temperature range
–
0
TJ
Operational die temperature
The temperature rise from ambient to junction
is package specific. Refer the table Thermal
Impedances per Package on page 34. The
user must limit the power consumption to
comply with this requirement.
Document Number: 001-54459 Rev. *E
–40
–
Page 17 of 43
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CY8C20X36A/46A/66A/96A
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 13. DC Chip-Level Specifications
Symbol
VDD
[31, 32, 33, 34]
Description
Supply voltage
Conditions
Refer the table DC POR and LVD
Specifications on page 23
Min
Typ
Max
Units
1.71
–
5.50
V
IDD24
Supply current, IMO = 24 MHz Conditions are VDD ≤ 3.0 V, TA = 25 °C,
CPU = 24 MHz. CapSense running at 12 MHz,
no I/O sourcing current
–
3.32
4.00
mA
IDD12
Supply current, IMO = 12 MHz Conditions are VDD ≤ 3.0 V, TA = 25 °C,
CPU = 12 MHz. CapSense running at
12 MHz, no I/O sourcing current
–
1.86
2.60
mA
IDD6
Supply current, IMO = 6 MHz
Conditions are VDD ≤ 3.0 V, TA = 25 °C,
CPU = 6 MHz. CapSense running at 6 MHz,
no I/O sourcing current
–
1.13
1.80
mA
ISB0
Deep sleep current
VDD ≤ 3.0 V, TA = 25 °C, I/O regulator turned off
–
0.10
0.50
μA
ISB1
Standby current with POR, LVD VDD ≤ 3.0 V, TA = 25 °C, I/O regulator turned off
and sleep timer
–
1.07
1.50
μA
Notes
31. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µsec, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be
slower than 1 V/500 usec to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter.
32. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken:
a. Bring the device out of sleep before powering down.
b. Assure that VDD falls below 100 mV before powering back up.
c. Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.
d. Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register.
For the referenced registers, refer to the CY8C20x36 Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows
VDD brown out conditions to be detected for edge rates slower than 1V/ms.
33. AFor USB mode, the VDD supply for bus-powered application should be limited to 4.35V-5.35V. For self-powered application, VDD should be 3.15 V-3.45 V.
34. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD , the rate at which VDD drops should not exceed 200 mV/s. Base VDD can
be between 1.8 V and 5.5 V
Document Number: 001-54459 Rev. *E
Page 18 of 43
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CY8C20X36A/46A/66A/96A
DC GPIO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C ≤ TA ≤ 85 °C, 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, or 1.71 V to 2.4 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical
parameters apply to 5V and 3.3 V at 25 C and are for design guidance only.
Table 14. 3.0-V to 5.5-V DC GPIO Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
RPU
Pull-up resistor
–
4
5.60
8
kΩ
VOH1
High output voltage
Port 2 or 3 pins
IOH < 10 μA, maximum of 10 mA source
current in all I/Os
VDD – 0.20
–
–
V
VOH2
High output voltage
Port 2 or 3 Pins
IOH = 1 mA, maximum of 20 mA source
current in all I/Os
VDD – 0.90
–
–
V
VOH3
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH < 10 μA, maximum of 10 mA source
current in all I/Os
VDD – 0.20
–
–
V
VOH4
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH = 5 mA, maximum of 20 mA source
current in all I/Os
VDD – 0.90
–
–
V
VOH5
High output voltage
Port 1 Pins with LDO Regulator
Enabled for 3 V out
IOH < 10 μA, VDD > 3.1 V, maximum of
4 I/Os all sourcing 5 mA
2.85
3.00
3.30
V
VOH6
High output voltage
IOH = 5 mA, VDD > 3.1V, maximum of
Port 1 pins with LDO regulator enabled 20 mA source current in all I/Os
for 3 V out
2.20
–
–
V
VOH7
High output voltage
IOH < 10 μA, VDD > 2.7 V, maximum of
Port 1 pins with LDO enabled for 2.5 V 20 mA source current in all I/Os
out
2.35
2.50
2.75
V
VOH8
IOH = 2 mA, VDD > 2.7 V, maximum of
High output voltage
Port 1 pins with LDO enabled for 2.5 V 20 mA source current in all I/Os
out
1.90
–
–
V
VOH9
High output voltage
IOH < 10 μA, VDD > 2.7 V, maximum of
Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os
out
1.60
1.80
2.10
V
VOH10
High output voltage
IOH = 1 mA, VDD > 2.7 V, maximum of
Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os
out
1.20
–
–
V
VOL
Low output voltage
IOL = 25 mA, VDD > 3.3 V, maximum of
60 mA sink current on even port pins (for
example, P0[2] and P1[4]) and 60 mA sink
current on odd port pins (for example, P0[3]
and P1[5])
–
–
0.75
V
VIL
Input low voltage
–
–
–
0.80
V
VIH
Input high voltage
–
2.00
–
–
V
VH
Input hysteresis voltage
–
–
80
–
mV
IIL
Input leakage (Absolute Value)
–
–
0.001
1
μA
CPIN
Pin capacitance
Package and pin dependent
Temp = 25 °C
0.50
1.70
7
pF
Document Number: 001-54459 Rev. *E
Page 19 of 43
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CY8C20X36A/46A/66A/96A
Table 15. 2.4V to 3.0V DC GPIO Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
4
5.60
8
kΩ
IOH < 10 μA, maximum of 10 mA
source current in all I/Os
VDD - 0.20
–
–
V
High output voltage
Port 2 or 3 Pins
IOH = 0.2 mA, maximum of 10 mA
source current in all I/Os
VDD - 0.40
–
–
V
VOH3
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH < 10 μA, maximum of 10 mA
source current in all I/Os
VDD - 0.20
–
–
V
VOH4
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source VDD - 0.50
current in all I/Os
–
–
V
VOH5A
High output voltage
IOH < 10 μA, VDD > 2.4 V, maximum of
Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os
out
1.50
1.80
2.10
V
VOH6A
High output voltage
IOH = 1 mA, VDD > 2.4 V, maximum of
Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os
out
1.20
–
–
V
VOL
Low output voltage
IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
–
–
0.75
V
VIL
Input low voltage
–
–
–
0.72
V
VIH
Input high voltage
–
1.40
–
VH
Input hysteresis voltage
–
–
80
–
mV
IIL
Input leakage (absolute value)
–
CPIN
Capacitive load on pins
Package and pin dependent
Temp = 25 °C
RPU
Pull-up resistor
–
VOH1
High output voltage
Port 2 or 3 pins
VOH2
V
–
1
1000
nA
0.50
1.70
7
pF
Min
Typ
Max
Units
Table 16. 1.71-V to 2.4-V DC GPIO Specifications
Symbol
Description
Conditions
RPU
Pull-up resistor
–
4
5.60
8
kΩ
VOH1
High output voltage
Port 2 or 3 pins
IOH = 10 μA, maximum of 10 mA
source current in all I/Os
VDD – 0.20
–
–
V
VOH2
High output voltage
Port 2 or 3 pins
IOH = 0.5 mA, maximum of 10 mA
source current in all I/Os
VDD – 0.50
–
–
V
VOH3
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
IOH = 100 μA, maximum of 10 mA
source current in all I/Os
VDD – 0.20
–
–
V
VOH4
High output voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source VDD – 0.50
current in all I/Os
–
–
V
VOL
Low output voltage
IOL = 5 mA, maximum of 20 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
–
–
0.40
V
VIL
Input low voltage
–
–
–
0.30 × VDD
V
VIH
Input high voltage
–
0.65 × VDD
–
–
V
Document Number: 001-54459 Rev. *E
Page 20 of 43
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CY8C20X36A/46A/66A/96A
Table 16. 1.71-V to 2.4-V DC GPIO Specifications (continued)
Symbol
Description
Conditions
Min
Typ
Max
Units
VH
Input hysteresis voltage
–
–
80
–
mV
IIL
Input leakage (absolute value)
–
–
1
1000
nA
CPIN
Capacitive load on pins
Package and pin dependent
temp = 25 oC
0.50
1.70
7
pF
Table 17. DC Characteristics – USB Interface
Min
Typ
Max
Units
RUSBI
Symbol
USB D+ pull-up resistance
Description
With idle bus
Conditions
900
–
1575
Ω
RUSBA
USB D+ pull-up resistance
While receiving traffic
1425
–
3090
Ω
VOHUSB
Static output high
–
2.8
–
3.6
V
VOLUSB
Static output low
–
–
–
0.3
V
VDI
Differential input sensitivity
–
0.2
–
VCM
Differential input common mode range –
0.8
–
2.5
V
VSE
Single ended receiver threshold
–
0.8
–
2.0
V
CIN
Transceiver capacitance
–
IIO
High Z state data line leakage
On D+ or D- line
RPS2
PS/2 pull-up resistance
REXT
External USB series resistor
V
–
–
50
pF
–10
–
+10
μA
–
3000
5000
7000
Ω
In series with each USB pin
21.78
22.0
22.22
Ω
DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 18. DC Analog Mux Bus Specifications
Min
Typ
Max
Units
RSW
Symbol
Switch resistance to common analog
bus
Description
–
Conditions
–
–
800
Ω
RGND
Resistance of initialization switch to
VSS
–
–
–
800
Ω
The maximum pin voltage for measuring RSW and RGND is 1.8 V
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 19. DC Comparator Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
0.0
–
1.8
V
–
–
10
40
μA
–
–
2.5
30
mV
VLPC
Low power comparator (LPC) common Maximum voltage limited to VDD
mode
ILPC
LPC supply current
VOSLPC
LPC voltage offset
Document Number: 001-54459 Rev. *E
Page 21 of 43
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CY8C20X36A/46A/66A/96A
Comparator User Module Electrical Specifications
The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the
entire device voltage and temperature operating range: –40°C <= TA <= 85°C, 1.71V <= VDD <= 5.5V.
Table 20. Comparator User Module Electrical Specifications
Symbol
Min
Typ
Max
Units
50 mV overdrive
–
70
100
ns
Offset
Valid from 0.2 V to VDD – 0.2 V
–
2.5
30
mV
Current
Average DC current, 50 mV
overdrive
–
20
80
µA
Supply voltage > 2 V
Power supply rejection ratio
–
80
–
dB
Supply voltage < 2 V
Power supply rejection ratio
–
40
–
0
TCOMP
PSRR
Description
Comparator response time
Input range
Conditions
–
dB
1.5
V
ADC Electrical Specifications
Table 21.ADC User Module Electrical Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
0
–
VREFADC
V
Input
VIN
Input voltage range
CIIN
Input capacitance
–
RIN
Input resistance
Equivalent switched cap input
resistance for 8-, 9-, or 10-bit
resolution
ADC reference voltage
FCLK
–
–
–
5
pF
1/(500fF ×
data clock)
1/(400fF ×
data clock)
1/(300fF ×
data clock)
Ω
–
1.14
–
1.26
V
Data clock
Source is chip’s internal main
oscillator. See AC Chip-Level
Specifications for accuracy
2.25
–
6
MHz
S8
8-bit sample rate
Data clock set to 6 MHz.
sample rate = 0.001/
(2^Resolution/Data Clock)
–
23.43
–
ksps
S10
10-bit sample rate
Data clock set to 6 MHz.
sample rate = 0.001/
(2^resolution/data clock)
–
5.85
–
ksps
RES
Resolution
Can be set to 8-, 9-, or 10-bit
8
–
10
bits
DNL
Differential nonlinearity
–
–1
–
+2
LSB
INL
Integral nonlinearity
–
–2
–
+2
LSB
EOFFSET
Offset error
8-bit resolution
0
3.20
19.20
LSB
10-bit resolution
0
12.80
76.80
LSB
Gain error
For any resolution
–5
–
+5
%FSR
IADC
Operating current
–
–
2.10
2.60
mA
PSRR
Power supply rejection ratio
PSRR (VDD > 3.0 V)
–
24
–
dB
PSRR (VDD < 3.0 V)
–
30
–
dB
Reference
VREFADC
Conversion Rate
DC Accuracy
EGAIN
Power
Document Number: 001-54459 Rev. *E
Page 22 of 43
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CY8C20X36A/46A/66A/96A
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 22. DC POR and LVD Specifications
Symbol
VPOR0
Description
Conditions
Min
Typ
Max
Units
1.61
–
1.66
1.71
V
2.36
2.41
–
2.60
2.66
–
2.82
2.95
VPOR2
1.66 V selected in PSoC Designer VDD must be greater than or equal to 1.71 V
2.36 V selected in PSoC Designer during startup, reset from the XRES pin, or
reset from watchdog.
2.60 V selected in PSoC Designer
VPOR3
2.82 V selected in PSoC Designer
VLVD0
2.45 V selected in PSoC Designer –
2.40
2.45
2.51
VLVD1
2.71 V selected in PSoC Designer
2.64[35]
2.71
2.78
VLVD2
2.92 V selected in PSoC Designer
2.85[36]
2.92
2.99
VLVD3
3.02 V selected in PSoC Designer
2.95[37]
3.02
3.09
VLVD4
3.13 V selected in PSoC Designer
3.06
3.13
3.20
VLVD5
1.90 V selected in PSoC Designer
1.84
1.90
2.32
VLVD6
1.80 V selected in PSoC Designer
1.75[38]
1.80
1.84
VLVD7
4.73 V selected in PSoC Designer
4.62
4.73
4.83
VPOR1
V
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 23. DC Programming Specifications
Symbol
Description
VDDIWRITE Supply voltage for flash write
operations
IDDP
Supply current during
programming or verify
VILP
Input low voltage during
programming or verify
VIHP
Input high voltage during
programming or verify
IILP
Input current when Applying VILP
to P1[0] or P1[1] during
programming or verify
IIHP
Input current when applying VIHP
to P1[0] or P1[1] during
programming or verify
VOLP
Output low voltage during
programming or verify
VOHP
Output high voltage during
programming or verify
FlashENPB Flash write endurance
FlashDR
Flash data retention
–
Conditions
Min
1.71
Typ
–
Max
5.25
Units
V
–
–
5
25
mA
See the appropriate DC GPIO Specifications on page 19
See appropriate DC GPIO Specifications
on page 19 table on pages 15 or 16
Driving internal pull-down resistor
–
–
VIL
V
VIH
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
VSS + 0.75
V
VOH
–
VDD
V
50,000
20
–
–
–
–
–
Years
Driving internal pull-down resistor
See appropriate DC GPIO Specifications
on page 19 table on page 16. For VDD >
3V use VOH4 in Table 12 on page 17.
Erase/write cycles per block
Following maximum Flash write cycles;
ambient temperature of 55 °C
Notes
35. Always greater than 50 mV above VPPOR1 voltage for falling supply.
36. Always greater than 50 mV above VPPOR2 voltage for falling supply.
37. Always greater than 50 mV above VPPOR3 voltage for falling supply.
38. Always greater than 50 mV above VPPOR0 voltage for falling supply.
Document Number: 001-54459 Rev. *E
Page 23 of 43
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CY8C20X36A/46A/66A/96A
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 24. AC Chip-Level Specifications
Min
Typ
Max
Units
FIMO24
Symbol
Internal main oscillator frequency at 24 MHz
Setting
Description
–
Conditions
22.8
24
25.2
MHz
FIMO12
Internal main oscillator frequency at 12 MHz
setting
–
11.4
12
12.6
MHz
FIMO6
Internal main oscillator frequency at 6 MHz
setting
–
5.7
6.0
6.3
MHz
FCPU
CPU frequency
–
0.75
–
25.20
MHz
F32K1
Internal low speed oscillator frequency
–
19
32
50
kHz
F32K_U
Internal low speed oscillator (ILO) untrimmed –
frequency)
13
32
82
kHz
DCIMO
Duty cycle of IMO
–
40
50
60
%
DCILO
Internal low speed oscillator duty cycle
–
40
50
60
%
VDD slew rate during power-up
–
–
250
V/ms
After supply voltage is valid
1
–
–
ms
Applies after part has booted
10
–
–
μs
SRPOWER_UP Power supply slew rate
tXRST
tXRST2
External reset pulse width at power-up
External reset pulse width after
power-up[39]
Note
39. The minimum required XRES pulse length is longer when programming the device (see Table 30 on page 27).
Document Number: 001-54459 Rev. *E
Page 24 of 43
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CY8C20X36A/46A/66A/96A
AC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 25. AC GPIO Specifications
Symbol
FGPIO
Description
GPIO operating frequency
Conditions
Normal strong mode Port 0, 1
Min
0
0
tRISE23
tRISE23L
tRISE01
tRISE01L
tFALL
tFALLL
Rise time, strong mode, Cload = 50 pF
Ports 2 or 3
Rise time, strong mode low supply,
Cload = 50 pF, Ports 2 or 3
Rise time, strong mode, Cload = 50 pF
Ports 0 or 1
Rise time, strong mode low supply,
Cload = 50 pF, Ports 0 or 1
Fall time, strong mode, Cload = 50 pF
all ports
Fall time, strong mode low supply,
Cload = 50 pF, all ports
Typ
Max
Units
– 6 MHz for
MHz
1.71 V <VDD < 2 .40 V
– 12 MHz for
MHz
2.40 V < VDD< 5.50 V
–
80
ns
VDD = 3.0 to 3.6 V, 10% to 90%
15
VDD = 1.71 to 3.0 V, 10% to 90%
15
–
80
ns
VDD = 3.0 to 3.6 V, 10% to 90%
LDO enabled or disabled
VDD = 1.71 to 3.0 V, 10% to 90%
LDO enabled or disabled
VDD = 3.0 to 3.6 V, 10% to 90%
10
–
50
ns
10
–
80
ns
10
–
50
ns
VDD = 1.71 to 3.0 V, 10% to 90%
10
–
70
ns
Figure 13. GPIO Timing Diagram
90%
GPIO Pin
Output
Voltage
10%
TRise23
TRise01
TRise23L
TRise01L
Document Number: 001-54459 Rev. *E
TFall
TFallL
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Table 26. AC Characteristics – USB Data Timings
Min
Typ
Max
Units
tDRATE
Symbol
Full speed data rate
Description
Average bit rate
Conditions
12 – 0.25%
12
12 + 0.25%
MHz
tJR1
Receiver jitter tolerance
To next transition
–18.5
–
18.5
ns
tJR2
Receiver jitter tolerance
To pair transition
–9.0
–
9
ns
tDJ1
FS Driver jitter
To next transition
–3.5
–
3.5
ns
tDJ2
FS Driver jitter
To pair transition
–4.0
–
4.0
ns
tFDEOP
Source jitter for differential
transition
To SE0 transition
–2.0
–
5
ns
tFEOPT
Source SE0 interval of EOP
–
160.0
–
175
ns
tFEOPR
Receiver SE0 interval of EOP
–
82.0
–
–
ns
tFST
Width of SE0 interval during
differential transition
–
–
–
14
ns
Min
Typ
Max
Units
4
–
20
ns
Table 27. AC Characteristics – USB Driver
Symbol
Description
Conditions
tFR
Transition rise time
50 pF
tFF
Transition fall time
50 pF
4
–
20
ns
tFRFM[40]
Rise/fall time matching
–
90
–
111
%
VCRS
Output signal crossover voltage
–
1.30
–
2.00
V
AC Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 28. AC Low Power Comparator Specifications
Symbol
tLPC
Description
Comparator response time,
50 mV overdrive
Conditions
50 mV overdrive does not include
offset voltage.
Min
Typ
Max
Units
–
–
100
ns
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 29. AC External Clock Specifications
Symbol
FOSCEXT
Min
Typ
Max
Units
Frequency (external oscillator
frequency)
Description
–
Conditions
0.75
–
25.20
MHz
High period
–
20.60
–
5300
ns
Low period
–
20.60
–
–
ns
Power-up IMO to switch
–
150
–
–
μs
Note
40. TFRFM is not met under all conditions. There is a corner case at lower supply voltages, such as those under 3.3V. This condition does not affect USB communications.
Signal integrity tests show an excellent eye diagram at 3.15V.
Document Number: 001-54459 Rev. *E
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CY8C20X36A/46A/66A/96A
AC Programming Specifications
Figure 14. AC Waveform
SCLK (P1[1])
T FSCLK
T RSCLK
SDATA (P1[0])
TSSCLK
T HSCLK
TDSCLK
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 30. AC Programming Specifications
Symbol
tRSCLK
tFSCLK
tSSCLK
tHSCLK
FSCLK
tERASEB
tWRITE
tDSCLK
tDSCLK3
tDSCLK2
tXRST3
Description
Rise time of SCLK
Fall time of SCLK
Data setup time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
Flash erase time (block)
Flash block write time
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
External reset pulse width after power-up
tXRES
tVDDWAIT
tVDDXRES
tPOLL
tACQ
XRES pulse length
VDD stable to wait-and-poll hold off
VDD stable to XRES assertion delay
SDATA high pulse time
“Key window” time after a VDD ramp
acquire event, based on 256 ILO clocks.
“Key window” time after an XRES event,
based on 8 ILO clocks
tXRESINI
Document Number: 001-54459 Rev. *E
Conditions
–
–
–
–
–
–
–
3.6 < VDD
3.0 ≤ VDD ≤ 3.6
1.71 ≤ VDD ≤ 3.0
Required to enter programming mode
when coming out of sleep
–
–
–
–
–
–
Min
1
1
40
40
0
–
–
–
–
–
300
Typ
–
–
–
–
–
–
–
–
–
–
–
Max
20
20
–
–
8
18
25
60
85
130
–
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ns
μs
300
0.1
14.27
0.01
3.20
–
–
–
–
–
–
1
–
200
19.60
μs
ms
ms
ms
ms
98
–
615
μs
Page 27 of 43
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CY8C20X36A/46A/66A/96A
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 31. AC Characteristics of the I2C SDA and SCL Pins
Symbol
fSCL
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
tSP
Description
SCL clock frequency
Hold time (repeated) START condition. After this period, the first clock pulse is
generated
LOW period of the SCL clock
HIGH Period of the SCL clock
Setup time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START condition
Pulse width of spikes are suppressed by the input filter
Standard
Mode
Min
Max
0
100
4.0
–
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
3.45
–
–
–
–
Fast Mode
Min
0
0.6
Max
400
–
1.3
–
0.6
–
0.6
–
0
0.90
100[41]
–
0.6
–
1.3
–
0
50
Units
kHz
µs
µs
µs
µs
µs
ns
µs
µs
ns
Figure 15. Definition for Timing for Fast/Standard Mode on the I2C Bus
Note
41. A Fast-Mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-54459 Rev. *E
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CY8C20X36A/46A/66A/96A
Table 32. SPI Master AC Specifications
Min
Typ
Max
Units
FSCLK
Symbol
SCLK clock frequency
Description
VDD ≥ 2.4 V
VDD < 2.4 V
Conditions
–
–
–
–
6
3
MHz
MHz
DC
SCLK duty cycle
–
–
50
–
%
tSETUP
MISO to SCLK setup time
VDD ≥ 2.4 V
VDD < 2.4 V
60
100
–
–
–
–
ns
ns
tHOLD
SCLK to MISO hold time
–
40
–
–
ns
tOUT_VAL
SCLK to MOSI valid time
–
–
–
40
ns
tOUT_HIGH
MOSI high time
–
40
–
–
ns
Figure 16. SPI Master Mode 0 and 2
SPI Master, modes 0 and 2
1/FSCLK
THIGH
TLOW
SCLK
(mode 0)
SCLK
(mode 2)
TSETUP
MISO
(input)
THOLD
LSB
MSB
TOUT_SU
TOUT_H
MOSI
(output)
Figure 17. SPI Master Mode 1 and 3
SPI Master, modes 1 and 3
1/FSCLK
THIGH
TLOW
SCLK
(mode 1)
SCLK
(mode 3)
TSETUP
MISO
(input)
THOLD
TOUT_SU
MOSI
(output)
Document Number: 001-54459 Rev. *E
LSB
MSB
TOUT_H
MSB
LSB
Page 29 of 43
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CY8C20X36A/46A/66A/96A
Table 33. SPI Slave AC Specifications
Symbol
FSCLK
Description
SCLK clock frequency
tLOW
tHIGH
tSETUP
tHOLD
tSS_MISO
tSCLK_MISO
tSS_HIGH
tSS_CLK
tCLK_SS
SCLK low time
SCLK high time
MOSI to SCLK setup time
SCLK to MOSI hold time
SS high to MISO valid
SCLK to MISO valid
SS high time
Time from SS low to first SCLK
Time from last SCLK to SS high
Conditions
VDD ≥ 2.4 V
VDD < 2.4 V
–
–
–
–
–
–
–
–
–
Min
–
–
41.67
41.67
30
50
–
–
–
2/SCLK
2/SCLK
Typ
–
–
–
–
–
–
–
–
–
–
–
Max
12
6
–
–
–
–
153
125
50
–
–
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 18. SPI Slave Mode 0 and 2
SPI Slave, modes 0 and 2
TSS_HIGH
TCLK_SS
TSS_CLK
/SS
1/FSCLK
THIGH
TLOW
SCLK
(mode 0)
SCLK
(mode 2)
TOUT_H
TSS_MISO
MISO
(output)
TSETUP
MOSI
(input)
THOLD
LSB
MSB
Figure 19. SPI Slave Mode 1 and 3
SPI Slave, modes 1 and 3
TSS_CLK
TCLK_SS
/SS
1/FSCLK
THIGH
TLOW
SCLK
(mode 1)
SCLK
(mode 3)
TOUT_H
TSCLK_MISO
TSS_MISO
MISO
(output)
MSB
TSETUP
MOSI
(input)
Document Number: 001-54459 Rev. *E
LSB
THOLD
MSB
LSB
Page 30 of 43
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CY8C20X36A/46A/66A/96A
Packaging Information
This section illustrates the packaging specifications for the CY8C20x36A/46A/66A/96A PSoC device, along with the thermal impedances for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 20. 16-pin QFN No E-pad 3x3x0.6 mm Package Outline (Sawn)
2.9
3.1
0.20 min
1
1
2
2.9
3.1
0.20 DIA TYP.
2
1.5 (NOM)
0.45
0.55
PIN #1 ID
0.152 REF.
0.30
0.18
0.05 MAX
0.50
0.60 MAX
1.5
SEATING PLANE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTES:
PART NO.
DESCRIPTION
LG16A
LEAD-FREE
LD16A
STANDARD
1. JEDEC # MO-220
2. Package Weight: 0.014g
3. DIMENSIONS IN MM, MIN
MAX
001-09116 *E
Figure 21. 24-Pin (4 × 4 × 0.6 mm) QFN
001-13937 *C
Document Number: 001-54459 Rev. *E
Page 31 of 43
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CY8C20X36A/46A/66A/96A
Figure 22. 32-Pin (5 × 5 × 0.6 mm) QFN
001-42168 *D
Figure 23. 48-Pin (300-Mil) SSOP
.020
24
1
0.395
0.420
0.292
0.299
25
DIMENSIONS IN INCHES MIN.
MAX.
48
0.620
0.630
0.088
0.092
0.095
0.110
0.025
BSC
SEATING PLANE
0.005
0.010
.010
GAUGE PLANE
0.004
0.008
0.0135
0.008
0.016
0°-8°
0.024
0.040
51-85061 *D
Document Number: 001-54459 Rev. *E
Page 32 of 43
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CY8C20X36A/46A/66A/96A
Figure 24. 48-Pin (7 × 7 × 1.0 mm) QFN
001-13191 *E
Figure 25. 30-Ball (2.2 × 2.32 × 0.40 mm) WLCSP
001-50669 *B
Important Notes
For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
■ Pinned vias for thermal conduction are not required for the low power PSoC device.
■
Document Number: 001-54459 Rev. *E
Page 33 of 43
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CY8C20X36A/46A/66A/96A
Thermal Impedances
Table 34. Thermal Impedances per Package
Package
Typical θJA [42]
16 Pin QFN
33 °C/W
[43]
21 °C/W
[43]
20 °C/W
24 Pin QFN
32 Pin QFN
69 °C/W
48 Pin SSOP
[43]
48 Pin QFN
18 °C/W
30 Ball WLCSP
54 °C/W
Capacitance on Crystal Pins
Table 35. Typical Package Capacitance on Crystal Pins
Package
Package Capacitance
32 Pin QFN
3.2 pF
48 Pin QFN
3.3 pF
Solder Reflow Peak Temperature
This table lists the minimum solder reflow peak temperature to achieve good solderability.
Table 36. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature[44]
Maximum Peak Temperature
16 Pin QFN
240 °C
260 °C
24 Pin QFN
240 °C
260 °C
32 Pin QFN
240 °C
260 °C
48 Pin SSOP
220 °C
260 °C
48 Pin QFN
240 °C
260 °C
30 Ball WLCSP
240 °C
260 °C
Note
42. TJ = TA + Power × θJA.
43. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
44. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 oC with Sn-Pb or 245 ± 5 oC with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications
Document Number: 001-54459 Rev. *E
Page 34 of 43
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CY8C20X36A/46A/66A/96A
Development Tool Selection
Software
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip
(PSoC) devices. The PSoC Designer IDE and application runs
on Windows XP and Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language
compilers developed specifically for the devices in the PSoC
family. PSoC Designer is available free of charge at
http://www.cypress.com/psocdesigner and includes a free C
compiler.
PSoC Designer Software Subsystems
You choose a base device to work with and then select different
onboard analog and digital components called user modules that
use the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters. You configure the user modules
for your chosen application and connect them to each other and
to the proper pins. Then you generate your project. This prepopulates your project with APIs and libraries that you can use to
program your application.
The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time. Code Generation
Tools PSoC Designer supports multiple third-party C compilers
and assemblers. The code generation tools work seamlessly
within the PSoC Designer interface and have been tested with a
full range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all the features of C tailored to
the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write I/O
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Document Number: 001-54459 Rev. *E
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices. The emulator consists of a
base unit that connects to the PC by way of a USB port. The base
unit is universal and operates with all PSoC devices. Emulation
pods for each device family are available separately. The
emulation pod takes the place of the PSoC device in the target
board and performs full speed (24MHz) operation.
Standard Cypress PSoC IDE tools are available for debugging
the CY8C20x36A/46A/66A/96A family of parts. However, the
additional trace length and a minimal ground plane in the FlexPod can create noise problems that make it difficult to debug the
design. A custom bonded On-Chip Debug (OCD) device is
available in a 48-pin QFN package. The OCD device is recommended for debugging designs that have high current and/or
high analog accuracy requirements. The QFN package is
compact and is connected to the ICE through a high density
connector.
PSoC Programmer
PSoC Programmer is flexible enough and is used on the bench
in development and is also suitable for factory programming.
PSoC Programmer works either as a standalone programming
application or operates directly from PSoC Designer. PSoC
Programmer software is compatible with both PSoC ICE Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free of cost at
http://www.cypress.com/psocprogrammer..
Development Kits
All development kits are sold at the Cypress Online Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
PSoC Designer supports the advance emulation features also.
The kit includes:
■
PSoC Designer Software CD
■
ICE-Cube In-Circuit Emulator
■
ICE Flex-Pod for CY8C29x66A Family
■
Cat-5 Adapter
■
Mini-Eval Programming Board
■
110 ~ 240 V Power Supply, Euro-Plug Adapter
■
iMAGEcraft C Compiler (Registration Required)
■
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
■
2 CY8C29466A-24PXI 28-PDIP Chip Samples
Page 35 of 43
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CY8C20X36A/46A/66A/96A
Evaluation Tools
All evaluation tools are sold at the Cypress Online Store.
Device Programmers
CY3210-MiniProg1
All device programmers are purchased from the Cypress Online
Store.
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample
■
28-Pin CY8C27443A-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
Modular Programmer Base
■
Three Programming Module Cards
■
MiniProg Programming Unit
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
110 ~ 240 V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
CY3280-20x66 Universal CapSense Controller
The CY3280-20X66 CapSense Controller Kit is designed for
easy prototyping and debug of CY8C20xx6A CapSense Family
designs with pre-defined control circuitry and plug-in hardware.
Programming hardware and an I2C-to-USB bridge are included
for tuning and data acquisition.
The kit includes:
■
CY3280-20x66 CapSense Controller Board
■
CY3240-I2USB Bridge
■
CY3210 MiniProg1 Programmer
■
USB 2.0 Retractable Cable
■
CY3280-20x66 Kit CD
Document Number: 001-54459 Rev. *E
Page 36 of 43
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CY8C20X36A/46A/66A/96A
Accessories (Emulation and Programming)
Table 37. Emulation and Programming Accessories
Part Number
Pin Package
Flex-Pod Kit[45]
Foot Kit[46]
Adapter[47]
CY8C20236A-24LKXI
16 QFN
CY3250-20246QFN
CY3250-20246QFN-POD
See note 43
CY8C20246A-24LKXI
16 QFN
CY3250-20246QFN
CY3250-20246QFN-POD
See note 47
CY8C20336A-24LQXI
24 QFN
CY3250-20346QFN
CY3250-20346QFN-POD
See note 43
CY8C20346A-24LQXI
24 QFN
CY3250-20346QFN
CY3250-20346QFN-POD
See note 47
CY8C20396A-24LQXI
24 QFN
CY8C20436A-24LQXI
32 QFN
CY3250-20466QFN
CY3250-20466QFN-POD
See note 43
CY8C20446A-24LQXI
32 QFN
CY3250-20466QFN
CY3250-20466QFN-POD
See note 47
CY8C20466A-24LQXI
32 QFN
CY3250-20466QFN
CY3250-20466QFN-POD
See note 47
CY8C20496A-24LQXI
32 QFN
CY8C20536A-24PVXI
48 SSOP
CY3250-20566
CY3250-20566-POD
See note 47
CY8C20546A-24PVXI
48 SSOP
CY3250-20566
CY3250-20566-POD
See note 47
Not Supported
Not Supported
CY8C20566A-24PVXI
48 SSOP
CY3250-20566
CY3250-20566-POD
See note 47
CY8C20636A-24LTXI
48 QFN
CY3250-20666QFN
CY3250-20666QFN-POD
See note 47
CY8C20646A-24LTXI
48 QFN
CY3250-20666QFN
CY3250-20666QFN-POD
See note 47
CY8C20666A-24LTXI
48 QFN
CY3250-20666QFN
CY3250-20666QFN-POD
See note 47
Third Party Tools
Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and
production. Specific details for each of these tools can be found at http://www.cypress.com under Documentation > Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC
device, refer Application Note Debugging - Build a PSoC Emulator into Your Board – AN2323.
Note
45. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
46. Foot kit includes surface mount feet that can be soldered to the target PCB.
47. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-54459 Rev. *E
Page 37 of 43
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CY8C20X36A/46A/66A/96A
Ordering Information
The following table lists the CY8C20x36A/46A/66A/96A PSoC devices' key package features and ordering codes..
Table 38. PSoC Device Key Features and Ordering Information
Flash
(Bytes)
SRAM
(Bytes)
CapSense
Blocks
16-Pin (3 × 3 × 0.6 mm) QFN CY8C20236A-24LKXI
8K
1K
1
13
13
Yes
No
Yes
16-Pin (3 × 3 × 0.6 mm) QFN CY8C20236A-24LKXIT
(Tape and Reel)
8K
1K
1
13
13
Yes
No
Yes
16-Pin (3 × 3 × 0.6 mm) QFN CY8C20246A-24LKXI
16 K
2K
1
13
13
Yes
No
Yes
16-Pin (3 × 3 × 0.6 mm) QFN CY8C20246A-24LKXIT
(Tape and Reel)
16 K
2K
1
13
13
Yes
No
Yes
24-Pin (4 × 4 × 0.6 mm) QFN CY8C20336A-24LQXI
8K
1K
1
20
20
Yes
No
Yes
24-Pin (4 × 4 × 0.6 mm) QFN CY8C20336A-24LQXIT
(Tape and Reel)
8K
1K
1
20
20
Yes
No
Yes
24-Pin (4 × 4 × 0.6 mm) QFN CY8C20346A-24LQXI
16 K
2K
1
20
20
Yes
No
Yes
24-Pin (4 × 4 × 0.6 mm) QFN CY8C20346A-24LQXIT
(Tape and Reel)
16 K
2K
1
20
20
Yes
No
Yes
24-Pin (4 × 4 × 0.6 mm) QFN CY8C20396A-24LQXI
16 K
2K
1
19
19
Yes
Yes
Yes
24-Pin (4 × 4 × 0.6 mm) QFN CY8C20396A-24LQXIT
(Tape and Reel)
16 K
2K
1
19
19
Yes
Yes
Yes
32-Pin (5 × 5 × 0.6 mm) QFN CY8C20436A-24LQXI
8K
1K
1
28
28
Yes
No
Yes
32-Pin (5 × 5 × 0.6 mm) QFN CY8C20436A-24LQXIT
(Tape and Reel)
8K
1K
1
28
28
Yes
No
Yes
32-Pin (5 × 5 × 0.6 mm) QFN CY8C20446A-24LQXI
16 K
2K
1
28
28
Yes
No
Yes
32-Pin (5 × 5 × 0.6 mm) QFN CY8C20446A-24LQXIT
(Tape and Reel)
16 K
2K
1
28
28
Yes
No
Yes
32-Pin (5 × 5 × 0.6 mm) QFN CY8C20466A-24LQXI
32 K
2K
1
28
28
Yes
No
Yes
32-Pin (5 × 5 × 0.6 mm) QFN CY8C20466A-24LQXIT
(Tape and Reel)
32 K
2K
1
28
28
Yes
No
Yes
32-Pin (5 × 5 × 0.6 mm) QFN CY8C20496A-24LQXI
16 K
2K
1
25
25
Yes
Yes
Yes
32-Pin (5 × 5 × 0.6 mm) QFN CY8C20496A-24LQXIT
(Tape and Reel)
16 K
2K
1
25
25
Yes
Yes
Yes
48-Pin SSOP
8K
1K
1
34
34
Yes
No
Yes
48-Pin SSOP (Tape and Reel) CY8C20536A-24PVXIT
8K
1K
1
34
34
Yes
No
Yes
48-Pin SSOP
16 K
2K
1
34
34
Yes
No
Yes
48-Pin SSOP (Tape and Reel) CY8C20546A-24PVXIT
16 K
2K
1
34
34
Yes
No
Yes
48-Pin SSOP
32 K
2K
1
34
34
Yes
No
Yes
48-Pin SSOP (Tape and Reel) CY8C20566A-24PVXIT
32 K
2K
1
34
34
Yes
No
Yes
48-Pin (7 × 7 mm) QFN
CY8C20636A-24LTXI
8K
1K
1
36
36
Yes
No
Yes
48-Pin (7 × 7 mm) QFN
(Tape and Reel)
CY8C20636A-24LTXIT
8K
1K
1
36
36
Yes
No
Yes
48-Pin (7 × 7 mm) QFN
CY8C20646A-24LTXI
16 K
2K
1
36
36
Yes
Yes
Yes
48-Pin (7 × 7 mm) QFN
(Tape and Reel)
CY8C20646A-24LTXIT
16 K
2K
1
36
36
Yes
Yes
Yes
48-Pin (7 × 7 mm) QFN
CY8C20666A-24LTXI
32 K
2K
1
36
36
Yes
Yes
Yes
Package
Ordering Code
CY8C20536A-24PVXI
CY8C20546A-24PVXI
CY8C20566A-24PVXI
Document Number: 001-54459 Rev. *E
Digital I/O Analog XRES
Pins
Inputs[48] Pin
USB ADC
Page 38 of 43
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CY8C20X36A/46A/66A/96A
Table 38. PSoC Device Key Features and Ordering Information
Package
Ordering Code
Flash
(Bytes)
SRAM
(Bytes)
CapSense
Blocks
Digital I/O Analog XRES
Pins
Inputs[48] Pin
USB ADC
48-Pin (7 × 7 mm) QFN
(Tape and Reel)
CY8C20666A-24LTXIT
32 K
2K
1
36
36
Yes
Yes
Yes
48-Pin (7 × 7 mm) QFN
(OCD)[48]
CY8C20066A-24LTXI
32 K
2K
1
36
36
Yes
Yes
Yes
30-Pin WLCSP
CY8C20746A-24FDXC
16 K
1K
1
27
27
Yes
No
Yes
30-Pin WLCSP
(Tape and Reel)
CY8C20746A-24FDXCT
16 K
1K
1
27
27
Yes
No
Yes
30-Pin WLCSP
CY8C20766A-24FDXC
32 K
2K
1
27
27
Yes
No
Yes
30-Pin WLCSP
(Tape and Reel)
CY8C20766A-24FDXCT
32 K
2K
1
27
27
Yes
No
Yes
24-Pin (4 × 4 × 0.6 mm) QFN CY8C20336AN-24LQXI
8K
1K
1
20
20
Yes
No
No
24-Pin (4 × 4 × 0.6 mm) QFN CY8C20336AN(Tape and Reel)
24LQXIT
8K
1K
1
20
20
Yes
No
No
32-Pin (5 × 5 × 0.6 mm) QFN CY8C20436AN-24LQXI
8K
1K
1
28
28
Yes
No
No
32-Pin (5 × 5 × 0.6 mm) QFN CY8C20436AN(Tape and Reel)
24LQXIT
8K
1K
1
28
28
Yes
No
No
48-Pin (7 × 7 mm) QFN
CY8C20636AN-24LTXI
8K
1K
1
36
36
Yes
No
No
48-Pin (7 × 7 mm) QFN
(Tape and Reel)
CY8C20636AN-24LTXIT
8K
1K
1
36
36
Yes
No
No
Ordering Code Definitions
Note
48. Dual-function
Digital I/O Pins also connect to the common analog mux.
Document Number: 001-54459 Rev. *E
Page 39 of 43
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CY8C20X36A/46A/66A/96A
Acronymns
Reference Documents
Acronyms Used
■
Technical reference manual for CY8C20xx6 devices
The following table lists the acronyms that are used in this
document.
■
In-system Serial Programming (ISSP) protocol for 20xx6
(AN2026C)
■
Host Sourced Serial Programming for 20xx6 devices
(AN59389)
Table 39. Acronyms Used in this Document
Acronym
AC
ADC
API
CMOS
CPU
DAC
DC
EOP
FSR
GPIO
GUI
I 2C
ICE
IDAC
ILO
IMO
I/O
ISSP
LCD
LDO
LSB
LVD
MCU
MIPS
MISO
MOSI
MSB
OCD
POR
PPOR
PSRR
PWRSYS
PSoC®
SLIMO
SRAM
SNR
QFN
SCL
SDA
SDATA
SPI
SS
SSOP
TC
USB
USB D+
USB DWLCSP
XTAL
Description
alternating current
analog-to-digital converter
application programming interface
complementary metal oxide semiconductor
central processing unit
digital-to-analog converter
direct current
end of packet
full scale range
general purpose input/output
graphical user interface
inter-integrated circuit
in-circuit emulator
digital analog converter current
internal low speed oscillator
internal main oscillator
input/output
in-system serial programming
liquid crystal display
low dropout (regulator)
least-significant bit
low voltage detect
micro-controller unit
mega instructions per second
master in slave out
master out slave in
most-significant bit
on-chip debugger
power on reset
precision power on reset
power supply rejection ratio
power system
Programmable System-on-Chip
slow internal main oscillator
static random access memory
signal to noise ratio
quad flat no-lead
serial I2C clock
serial I2C data
serial ISSP data
serial peripheral interface
slave select
shrink small outline package
test controller
universal serial bus
USB Data +
USB Datawafer level chip scale package
crystal
Document Number: 001-54459 Rev. *E
Document Conventions
Units of Measure
Table 40 lists all the abbreviations used to measure the PSoC
devices.
Table 40. Units of Measure
Symbol
°C
dB
fF
g
Hz
KB
Kbit
KHz
Ksps
kΩ
MHz
MΩ
μA
μF
μH
μs
μW
mA
ms
mV
nA
ns
nV
W
pA
pF
pp
ppm
ps
sps
s
V
W
Unit of Measure
degree Celsius
decibels
femto farad
gram
hertz
1024 bytes
1024 bits
kilohertz
kilo samples per second
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microwatts
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
watt
Page 40 of 43
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CY8C20X36A/46A/66A/96A
Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
Glossary
Crosspoint connection
Connection between any GPIO combination via analog multiplexer bus.
Differential non-linearity
Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly
one LSB apart. Differential non-linearity is a measure of the worst case deviation from the
ideal 1 LSB step.
Hold time
Hold time is the time following a clock event during which the data input to a latch or flipflop must remain stable in order to guarantee that the latched data is correct.
I2C
It is a serial multi-master bus used to connect low speed peripherals to MCU.
Integral nonlinearity
It is a term describing the maximum deviation between the ideal output of a DAC/ADC and
the actual output level.
Latch-up current
Current at which the latch-up test is conducted according to JESD78 standard ( at 125
degree celsius)
Power supply rejection ratio (PSRR)
The PSRR is defined as the ratio of the change in supply voltage to the corresponding
change in output voltage of the device.
Scan
The conversion of all sensor capacitances to digital values.
Setup time
Period required to prepare a device, machine, process, or system for it to be ready to
function.
Signal-to-noise ratio
The ratio between a capacitive finger signal and system noise.
SPI
Serial peripheral interface is a synchronous serial data link standard.
Document Number: 001-54459 Rev. *E
Page 41 of 43
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CY8C20X36A/46A/66A/96A
Document History Page
Document Title: CY8C20X36A/46A/66A/96A CapSense® Applications
Document Number: 001-54459
Revision
ECN
Origin of Change Submission Date
Description of Change
**
2737924
SNV
07/14/09
New silicon and document
*A
2764528
MATT
09/16/2009
Updated AC Chip Level Specifications
Updated ADC User Module Electrical Specifications table
Added Note 5.
Added SRPOWER_UP parameter.
Updated Ordering information.
Updated Capacitance on Crystal Pins
*B
2803229
VZD
11/10/09
Added Contents on page 3. Added Note 6 on page 20. Edited
Features section to include reference to Incremental ADC.
*C
2846083
DST/KEJO
01/12/2010
Updated AC Programming Specifications on page 27 per CDT
56531
Updated Idd typical values in DC Chip-Level Specifications on
page 18.
Added 30-pin WLCSP pin and package details
Added Contents on page 2.
*D
2935141 KEJO/ISW/SSHH
03/05/2010
Updated Features on page 1.
Added SmartSense™ on page 4.
Updated PSoC® Functional Overview on page 4.
Removed SNR statement regarding on page 4 (Analog Multiplexer section).
Updated on page 5 with the I2C enhanced slave interface point.
Removed references to “system level” in Designing with PSoC
Designer on page 6.
Changed TC CLK and TC DATA to ISSP CLK and ISSP DATA
respectively in all the pinouts.
Modified notes in Pinouts.
Updated 30-ball pin diagram.
Removed IMO frequency trim options diagram in Electrical
Specifications on page 17.
Updated and formatted values in DC and AC specifications.
Updated Ordering information table.
Updated 48-pin SSOP package diagram. Added 30-Ball
WLCSP package spec 001-50669.
Removed AC Analog Mux Bus Specifications section.
Added SPI Master and Slave mode diagrams.
Modified Definition for Timing for Fast/Standard Mode on the
I2C Bus on page 28.
Updated Thermal Impedances on page 34.
Combined Development Tools with Development Tool
Selection on page 35. Removed references to “system level”.
Updated Evaluation Tools on page 36.
Added Ordering Code Definitions on page 39.
Updated Acronyms Used on page 40.
Added Glossary and Reference Documents on page 40
Changed datasheet status from Preliminary to Final
*E
3043291
SAAC
09/30/10
1) Change: Added the line “Supports SmartSense” under the
“Low power CapSense® block” bullet in the Features section.
Areas affected: Features section.
Impact: Helps to know that this part has the feature of Auto
Tuning.
2) Change: Replaced pod MPNs.
Areas affected: Foot kit column of table 37.
3) Change: Template and Styles update.
Areas affected: Entire datasheet.
Impact: Datasheet adheres to Cypress standards.
Document Number: 001-54459 Rev. *E
Page 42 of 43
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© Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54459 Rev. *E
Revised September 30, 2010
Page 43 of 43
2
PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I C components from Cypress or one of its sublicensed
Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of
their respective holders.
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