Renesas 70 Technical information

To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
When exporting the products or technology described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas
Electronics products or the technology described in this document for any purpose relating to military applications or use by
the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and
technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and
“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as
indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior
written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way
liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an
application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written
consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”:
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with
applicable laws and regulations.
This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD70F3003A, 70F3025A, 70F3003A(A)
V853
32-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD70F3003A, µPD70F3025A, and µPD70F3003A(A) have a flash memory instead of the internal mask ROM
of the µPD703003A/703004A, µPD703025A, and µPD703003A(A), respectively. This model is useful for small-scale
production of a variety of application sets or early start of production since the program can be written and erased
by the user even with the µPD70F3003 mounted on the board.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V853 Hardware User’s Manual:
U10913E
V850 Series Architecture User’s Manual: U10243E
FEATURES
• Compatible with µPD703003A, 703004A, 703025A, and 703003A(A)
• Can be replaced with mask ROM model for mass production of application set
µPD70F3003A → µPD703003A, 703004A
µPD70F3025A → µPD703025A
µPD70F3003A(A) → µPD703003A(A)
• Internal memory
Flash memory: 128KB (µPD70F3003A, 70F3003A(A))
256KB (µPD70F3025A)
Remark For differences among the products, refer to 1. DIFFERENCES BETWEEN PRODUCT.
ORDERING INFORMATION
Part Number
Package
Quality Grade
µPD70F3003AGC-33-8EU
100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
µPD70F3003AGC-33-8EU-A
100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
µPD70F3025AGC-33-8EU
100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
µPD70F3025AGC-33-8EU-A
100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
µPD70F3003AGC(A)-33-8EU
100-pin plastic LQFP (fine pitch) (14 × 14)
Special
Remarks 1. The µPD70F3003A and µPD70F3003A(A) differ in the quality grade only.
2. Products with -A at the end of the part number are lead-free products.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the devices and its
recommended applications.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U13189EJ5V1DS00 (5th edition)
Date Published August 2005 N CP(K)
Printed in Japan
The mark
shows major revised points.
1998
µPD70F3003A, 70F3025A, 70F3003A(A)
APPLICATIONS
µ PD70F3003A, 70F3025A:
Camcorders, VCRs, PPCs, LBPs, printers, motor controllers, NC machine
tools, mobile telephones, etc.
µ PD70F3003A(A):
Medical equipment, automotive appliances, etc.
PIN CONFIGURATION (Top View)
• 100-Pin Plastic LQFP (fine pitch) (14 × 14)
µ PD70F3003AGC-33-8EU
µ PD70F3025AGC-33-8EU
µ PD70F3003AGC-33-8EU-A
µ PD70F3025AGC-33-8EU-A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
ANO0
ANO1
AVREF2
AVREF3
P07/INTP113/ADTRG
P06/INTP112
P05/INTP111
P04/INTP110
P03/TI11
P02/TCLR11
P01/TO111
P00/TO110
P117/INTP143
P116/INTP142
P115/INTP141
P114/INTP140
P113/TI14
P112/TCLR14
P111/TO141
P43/AD3
P42/AD2
VSS
VDD
P41/AD1
P40/AD0
P90/LBEN
P91/UBEN
P92/R/W
P93/DSTB
P94/ASTB
P95/HLDAK
P96/HLDRO
WAIT
VPP
MODE
RESET
CVDD/CKSEL
X2
X1
CVSS
CLKOUT
VSS
VDD
P110/TO140
P31/TO131
P32/TCLR13
P33/TI13
P34/INTP130
P35/INTP131/SO3
P36/INTP132/SI3
P37/INTP133/SCK3
P63/A19
P62/A18
P61/A17
P60/A16
VSS
VDD
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P30/TO130
P27/SCK1
P26/RXD1/SI1
P25/TXD1/SO1
P24/SCK0
P23/RXD0/SI0
P22/TXD0/SO0
P21/PWM1
P20/PWM0
NMI
VDD
VSS
P17/INTP123/SCK2
P16/INTP122/SI2
P15/INTP121/SO2
P14/INTP120
P13/TI12
P12/TCLR12
P11/TO121
P10/TO120
AVDD
AVSS
AVREF1
P77/ANI7
P76/ANI6
µ PD70F3003AGC(A)-33-8EU
Caution Connect VPP pin to VSS pin except the case that µPD70F3003A, 70F3003A(A) or 70F3025A
is used in flash memory programming mode.
2
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
PIN NAMES
A16 to A19:
Address bus
P40 to P47:
Port 4
AD0 to AD15:
Address/data bus
P50 to P57:
Port 5
ADTRG:
A/D Trigger input
P60 to P63:
Port 6
ANI0 to ANI7:
Analog input
P70 to P77:
Port 7
ANO0, ANO1:
Analog output
P90 to P96:
Port 9
ASTB:
Address strobe
P110 to P117:
Port 11
AV DD :
Analog V DD
PWM0, PWM1:
Pulse width modulation
AV REF1 to AV REF3:
Analog reference voltage
RESET:
Reset
AV SS :
Analog V SS
R/W:
Read/write status
CV DD :
Power supply for clock generator
RXD0, PXD1:
Receive data
CV SS :
Ground for clock generator
SCK0 to SCK3:
Serial clock
CKSEL:
Clock select
SI0 to SI3:
Serial input
CLKOUT :
Clock output
SO0 to SO3:
Serial output
DSTB:
Data strobe
TO110, TO111,
HLDAK:
Hold acknowledge
TO120, TO121,
HLDRQ:
Hold request
TO130, TO131,
INTP110 to INTP113,
TO140, TO141:
Timer output
INTP120 to INTP123,
TCLR11 to TCLR14: Timer clear
INTP130 to INTP133,
TI11 to TI14:
Timer input
INTP140 to INTP143: Interrupt request from peripherals
TXD0, TXD1:
Transmit data
LBEN:
Lower byte enable
UBEN:
Upper byte enable
MODE:
Mode
WAIT:
Wait
NMI:
Non-maskable interrupt request
X1, X2:
Crystal
P00 to P07:
Port 0
V DD :
Power supply
P10 to P17:
Port 1
V PP:
Programming power supply
P20 to P27:
Port 2
V SS:
Ground
P30 to P37:
Port 3
Data Sheet U13189EJ5V1DS
3
µPD70F3003A, 70F3025A, 70F3003A(A)
INTERNAL BLOCK DIAGRAM
Flash memory
CPU
NMI
INTP110 to INTP113
INTP120 to INTP123
INTP130 to INTP133
INTP140 to INTP143
Note 1
TO110, TO111
TO120, TO121
TO130, TO131
TO140, TO141
Instruction
queue
PC
INTC
32-bit
barrel shifter
Multiplier
16 × 16 → 32
System
register
RPU
RAM
TCLR11 to TCLR14
TI11 to TI14
Note 2
BCU
ASTB
DSTB
R/W
UBEN
LBEN
WAIT
A16 to A19
AD0 to AD15
HLDRQ
HLDAK
Generalpurpose
register
32 bits × 32
ALU
SIO
SO0/TXD0
SI0/RXD0
SCK0
UART0/CSI0
BRG0
CSI2
Ports
P110 to P117
P90 to P96
P70 to P77
P60 to P63
P50 to P57
P40 to P47
P30 to P37
P20 to P27
P10 to P17
P00 to P07
SO2
SI2
SCK2
D/A
converter
AVREF2, AVREF3
BRG1
A/D
converter
ANO0, ANO1
UART1/CSI1
ANI0 to ANI7
AVREF1
AVSS
AVDD
ADTRG
SO1/TXD1
SI1/RXD1
SCK1
CG
CKSEL
CLKOUT
X1
X2
MODE
RESET
VDD
VSS
BRG2
CVDD
SO3
SI3
SCK3
CSI3
PWM0, PWM1
PWM
CVSS
VPP
Notes 1. µPD70F3003A, 70F3003A(A): 128 KB
µPD70F3025A:
256 KB
2. µPD70F3003A, 70F3003A(A): 4 KB
µPD70F3025A:
4
8 KB
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
CONTENTS
1. DIFFERENCES BETWEEN PRODUCTS ·························································································· 6
2. PIN FUNCTIONS ································································································································ 7
2.1 Port Pins ·····················································································································································
7
2.2 Non-Port Pins ·············································································································································
9
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ························································· 11
3. ELECTRICAL SPECIFICATIONS ······································································································· 14
3.1 Normal Operation Mode ···························································································································· 14
3.2 Flash Memory Programming Mode ·········································································································· 37
4. PACKAGE DRAWING ······················································································································· 40
5. RECOMMENDED SOLDERING CONDITIONS ················································································· 41
APPENDIX NOTES ON TARGET SYSTEM DESIGN ············································································· 43
Data Sheet U13189EJ5V1DS
5
µPD70F3003A, 70F3025A, 70F3003A(A)
1. DIFFERENCES BETWEEN PRODUCTS
Item
Internal ROM
µ PD703003A µ PD703004A µ PD703025A µ PD703003A(A) µ PD703025A(A) µ PD70F3003A µ PD70F3025A µ PD70F3003A(A)
Mask ROM
128 KB
Flash memory
96 KB
256 KB
128 KB
256 KB
8 KB
4 KB
8 KB
128 KB
Internal RAM
4 KB
Flash memory
programming mode
None
Provided
V PP pin
None
Provided
Quality grade
Standard
Special
4 KB
256 KB
128 KB
8 KB
Standard
4 KB
Special
Electrical specifications Current consumption, etc. differs. (Refer to each product data sheets).
Others
Noise immunity and noise radiation differ because circuit scale and mask layout differ.
Caution There are differences in noise immunity and noise radiation between the flash memory version
and mask ROM version. When pre-producing an application set with the flash memory version
and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluation
for commercial samples (not engineering samples) of the mask ROM version.
6
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
2. PIN FUNCTIONS
2.1 Port Pins
(1/2)
Pin Name
P00
I/O
I/O
Function
Alternate Function
Port 0
TO110
P01
8-bit I/O port.
TO111
P02
Input/output can be specified in 1-bit units.
TCLR11
P03
TI11
P04
INTP110
P05
INTP111
P06
INTP112
P07
INTP113/ADTRG
P10
I/O
Port 1
TO120
P11
8-bit I/O port.
TO121
P12
Input/output can be specified in 1-bit units.
TCLR12
P13
TI12
P14
INTP120
P15
INTP121/SO2
P16
INTP122/SI2
P17
INTP123/SCK2
P20
I/O
Port 2
PWM0
P21
8-bit I/O port.
PWM1
P22
Input/output can be specified in 1-bit units.
TXD0/SO0
P23
RXD0/SI0
P24
SCK0
P25
TXD1/SO1
P26
RXD1/SI1
P27
SCK1
P30
I/O
Port 3
TO130
P31
8-bit I/O port.
TO131
P32
Input/output can be specified in 1-bit units.
TCLR13
P33
TI13
P34
INTP130
P35
INTP131/SO3
P36
INTP132/SI3
P37
INTP133/SCK3
P40 to P47
I/O
Port 4
AD0 to AD7
8-bit I/O port.
Input/output can be specified in 1-bit units.
P50 to P57
I/O
Port 5
AD8 to AD15
8-bit I/O port.
Input/output can be specified in 1-bit units.
Data Sheet U13189EJ5V1DS
7
µPD70F3003A, 70F3025A, 70F3003A(A)
(2/2)
Pin Name
P60 to P63
I/O
I/O
Function
Port 6
Alternate Function
A16 to A19
4-bit I/O port.
Input/output can be specified in 1-bit units.
P70 to P77
Input
Port 7
ANI0 to ANI7
8-bit input port.
P90
Port 9
LBEN
P91
7-bit I/O port.
UBEN
P92
Input/output can be specified in 1-bit units.
R/W
P93
DSTB
P94
ASTB
P95
HLDAK
P96
HLDRQ
P110
8
I/O
I/O
Port 11
TO140
P111
8-bit I/O port.
TO141
P112
Input/output can be specified in 1-bit units.
TCLR14
P113
TI14
P114
INTP140
P115
INTP141
P116
INTP142
P117
INTP143
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
2.2 Non-Port Pins
(1/2)
Pin Name
TO110
I/O
Output
Function
Pulse signal output from timers 11 to 14
Alternate Function
P00
TO111
P01
TO120
P10
TO121
P11
TO130
P30
TO131
P31
TO140
P110
TO141
P111
TCLR11
Input
External clear signal input for timers 11 to 14
P02
TCLR12
P12
TCLR13
P32
TCLR14
P112
TI11
Input
External count clock input for timers 11 to 14
P03
TI12
P13
TI13
P33
TI14
P113
INTP110
Input
INTP111
External maskable interrupt request input and external capture
P04
trigger input for timer 11
P05
INTP112
P06
INTP113
P07/ADTRG
INTP120
Input
INTP121
External maskable interrupt request input and external capture
P14
trigger input for timer 12
P15/SO2
INTP122
P16/S12
INTP123
P17/SCK2
INTP130
Input
INTP131
External maskable interrupt request input and external capture
P34
trigger input for timer 13
P35/SO3
INTP132
P36/SI3
INTP133
P37/SCK3
INTP140
Input
INTP141
External maskable interrupt request input and external capture
P114
trigger input for timer 14
P115
INTP142
P116
INTP143
P117
SO0
Output
Serial transmit data output for CSI0 to CSI3 (3-wire)
P22/TXD0
SO1
P25/TXD1
SO2
P15/INTP121
SO3
P35/INTP131
SI0
Input
Serial receive data output for CSI0 to CSI3 (3-wire)
P23/RXD0
SI1
P26/RXD1
SI2
P16/INTP122
SI3
P36/INTP132
Data Sheet U13189EJ5V1DS
9
µPD70F3003A, 70F3025A, 70F3003A(A)
(2/2)
Pin Name
SCK0
I/O
I/O
Function
Serial clock I/O for CSI0 to CSI3 (3-wire)
Alternate Function
P24
SCK1
P27
SCK2
P17/INTP123
SCK3
P37/INTP133
TXD0
Output
Serial transmit data output of UART0 to UART1
TXD1
RXD0
P25/SO1
Input
Serial receive data input of UART0 to UART1
RXD1
PWM0
P23/SI0
P26/SI1
Output
Pulse signal output of PWM
PWM1
AD0 to AD7
P22/SO0
P20
P21
I/O
16-bit multiplexed address/data bus when external memory is connected
AD8 to AD15
P40 to P47
P50 to P57
A16 to A19
Output
Higher address bus when external memory is connected
P60 to P63
LBEN
Output
Lower byte enable signal output of external data bus
P90
Higher byte enable signal output of external data bus
P91
External read/write status output
P92
DSTB
External data strobe signal output
P93
ASTB
External address strobe signal output
P94
Bus hold acknowledge output
P95
UBEN
R/W
Output
HLDAK
Output
HLDRQ
Input
Bus hold request input
P96
ANI0 to ANI7
Input
Analog input to A/D converter
P70 to P77
ANO0, ANO1
Output
NMI
CLKOUT
Input
Output
Analog output of D/A converter
—
Non-maskable interrupt request input
—
System clock output
—
CKSEL
Input
Input specifying operation mode of clock generator
CVDD
WAIT
Input
Control signal input inserting wait state in bus cycle
—
MODE
Input
Operation mode specification
—
RESET
Input
System reset input
—
X1
Input
System clock resonator connection. Input external clock to X1 to
—
X2
—
supply external clock.
—
ADTRG
Input
A/D converter external trigger input
P07/INTP113
AVREF1
Input
Reference voltage input for A/D converter
—
AVREF2
Input
Reference voltage input for D/A converter
—
—
AVREF3
AVDD
—
Positive power supply for A/D converter
—
AVSS
—
Ground potential for A/D converter
—
CVDD
—
Positive power supply for internal clock generator
CVSS
—
Ground potential for internal clock generator
—
VDD
—
Positive power supply
—
VSS
—
Ground potential
—
VPP
—
High voltage application pin when program is written/verified
—
10
Data Sheet U13189EJ5V1DS
CKSEL
µPD70F3003A, 70F3025A, 70F3003A(A)
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the I/O circuit type of each pin, and the recommended connections of the unused pins. Figure
2-1 shows a partially simplified diagram of each circuit.
It is recommended that 1 to 10 kΩ resistors be used when connecting to V DD or V SS via a resistor.
Table 2-1. Types of Pin I/O Circuits and Recommended Connections of Unused Pins (1/2)
Pin Name
I/O Circuit Type
Recommended Connection of Unused Pins
P00/TO110, P01/TO111
5
Input:
Independently connect to VDD or VSS via a resistor.
P02/TCLR11, P03/TI11,
8
Output:
Leave open.
P04/INTP110 to P07/INTP113/ADTRG
P10 to TO120, P11/TO121
5
P12/TCLR12, P13/TI12
8
P14/INTP120
P15/INTP121/SO2
P16/INTP122/SI2
P17/INTP123/SCK2
P20/PWM0, P21/PWM1
5
P22/TXD0/SO0
P23/RXD0/SI0, P24/SCK0
8
P25/TXD1/SO1
5
P26/RXD1/SI1, P27/SCK1
8
P30/TO130, P31/TO131
5
P32/TCLR13, P33/TI13
8
P34/INTP130
P35/INTP131/SO3
10-A
P36/INTP132/SI3
P37/INTP133/SCK3
P40/AD0 to P47/AD7
5
P50/AD8 to P57/AD15
P60/A16 to P63/A19
P70/ANI0 to P77/ANI7
9
Directly connect to VSS.
P90/LBEN
5
Input:
Independently connect to VDD or VSS via a resistor.
Output:
Leave open.
P91/UBEN
P92/R/W
P93/DSTB
P94/ASTB
P95/HLDAK
P96/HLDRQ
P110/TO140, P111/TO141
P112/TCLR14, P113/TI14
8
P114/INTP140 to P117/INTP143
Data Sheet U13189EJ5V1DS
11
µPD70F3003A, 70F3025A, 70F3003A(A)
Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)
Pin Name
I/O Circuit Type
Recommended Connection of Unused Pins
ANO0, ANO1
12
Leave open.
NMI
2
Directly connect to VSS.
CLKOUT
3
Leave open.
WAIT
1
Directly connect to VDD.
MODE
2
—
RESET
CVDD/CKSEL
—
AVREF1 to AVREF3, AVSS
—
Directly connect to VSS.
AVDD
—
Directly connect to VDD.
VPP
—
Connect to VSS.
12
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
Figure 2-1. Pins I/O Circuits
Type 1
Type 8
VDD
Data
VDD
P-ch
IN/OUT
P-ch
Output
disable
IN
N-ch
N-ch
Type 2
Type 9
P-ch
N-ch
IN
Comparator
+
–
IN
VREF (Threshold voltage)
Input enable
Schmitt trigger input with hysteresis characteristics
Type 3
Type 10-A
VDD
Pull-up
enable
VDD
P-ch
VDD
Data
P-ch
P-ch
OUT
IN/OUT
Open drain
Output disable
N-ch
N-ch
Type 12
Type 5
VDD
Data
P-ch
P-ch
IN/OUT
Analog output voltage
Output
disable
OUT
N-ch
N-ch
Input
enable
Data Sheet U13189EJ5V1DS
13
µPD70F3003A, 70F3025A, 70F3003A(A)
3. ELECTRICAL SPECIFICATIONS
3.1 Normal Operation Mode
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD
Input voltage
Conditions
VDD pin
Ratings
Unit
–0.5 to +7.0
CVDD
CVDD pin
–0.5 to VDD + 0.3
CVSS
CVSS pin
–0.5 to +0.5
V
Note 1
V
AVDD
AVDD pin
–0.5 to VDD + 0.3
AVSS
AVSS pin
–0.5 to +0.5
VI1
Note 2, VDD = 5.0 V ±10%
VI2
VPP pin in flash memory programming mode,
–0.5 to VDD + 0.3
V
Note 1
V
V
Note 1
V
–0.5 to +11.0
V
–0.5 to VDD + 1.0Note 1
V
VDD = 5.0 V ±10%
Clock input voltage
VK
X1 pin, VDD = 5.0 V ±10%
Output current, low
ICL
1 pin
4.0
mA
Total of all pins
100
mA
1 pin
–4.0
mA
Total of all pins
–100
Output current, high
Output voltage
ICH
VO
Analog input voltage
VIAN
VDD = 5.0 V ±10%
P70/ANI0 to P77/ANI7
–0.5 to VDD + 0.3
AVDD > VDD
VDD ≥ AVDD
Analog reference input voltage
AVREF
AVREF1 to AVREF3
AVDD > VDD
VDD ≥ AVDD
mA
Note 1
V
Note 1
V
–0.5 to VDD + 0.3
–0.5 to AVDD + 0.3
–0.5 to VDD + 0.3
Note 1
Note 1
–0.5 to AVDD + 0.3
Note 1
V
V
V
Operating ambient temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +125
°C
Notes 1. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
2. X1, P70 to P77, AVREF1 to AVREF3, and their alternate-function pins are excluded.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC
and GND. However, direct connections among open-drain and open-collector pins are
possible, as are direct connections to external circuits that have timing designed to prevent
output conflict with pins that become high-impedance.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The normal operating ranges of ratings and conditions in which the quality of the product
is guaranteed are specified in the following DC Characteristics and AC Characteristics.
14
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CI
fc = 1 MHz
15
pF
I/O capacitance
CIO
Pins other than tested pin: 0 V
15
pF
Output capacitance
CO
15
pF
Operating Conditions
Operation Mode
Internal System Clock Frequency (φ)
Direct mode,
PLL mode
Operating Temperature (TA)
Supply Voltage (VDD)
2 to 33 MHz
Note 1
–40 to +85°C
5.0 V ±10%
5 to 33 MHz
Note 2
–40 to +85°C
5.0 V ±10%
Notes 1. When A/D converter not used.
2. When A/D converter used.
Recommended Oscillator
Caution For the resonator selection and oscillator constant of the µ PD70F3003A(A), customers are
requested to apply to the resonator manufacturer for evaluation.
(1) Ceramic resonator connection (TA = –40 to +85°C)
(a) µPD70F3003A
X1
X2
Rd
C1
Manufacturer
Kyocera
Corporation
TDK
Murata Mfg.
Co., Ltd
Part Number
PBRC4.00HR
PBRC5.00HR
PBRC6.00HR
PBRC6.60HR
FCR4.0MC5
FCR5.0MC5
FCR6.0MC5
CSTS0400MG06
CSTCR4M00G05
CSTS0600MG06
CSTCR6M00G55-R0
C2
Oscillation
Recommended
Frequency
fXX (MHz)
Circuit Constant
C1 (pF) C2 (pF)
Rd (W)
On-chip On-chip
—
On-chip On-chip
—
On-chip On-chip
—
On-chip On-chip
—
On-chip On-chip
—
On-chip On-chip
—
On-chip On-chip
—
On-chip On-chip
—
On-chip On-chip
—
On-chip On-chip
—
On-chip On-chip
—
4.0
5.0
6.0
6.6
4.0
5.0
6.0
4.0
4.0
6.0
6.0
Oscillation
Oscillation
Voltage Range
Stabilization Time
MIN. (V) MAX. (V) (MAX.) TOST (ms)
4.5
5.5
0.10
4.5
5.5
0.08
4.5
5.5
0.08
4.5
5.5
0.08
4.5
5.5
0.14
4.5
5.5
0.14
4.5
5.5
0.11
4.5
5.5
0.12
4.5
5.5
0.14
4.5
5.5
0.14
4.5
5.5
0.18
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken lines.
3. Thoroughly evaluate the matching between the µPD70F3003A and the resonator.
Data Sheet U13189EJ5V1DS
15
µPD70F3003A, 70F3025A, 70F3003A(A)
(b) µPD70F3025A
X1
X2
Rd
C1
Manufacturer
Part Number
C2
Oscillation
Recommended
Frequency
fXX (MHz)
Circuit Constant
Oscillation
C1 (pF)
C2 (pF)
Rd (W)
Oscillation
Voltage Range
Stabilization Time
MIN. (V) MAX. (V) (MAX.) TOST (ms)
Kyocera
PBRC4.00HR
4.0
On-chip
On-chip
—
4.5
5.5
0.12
Corporation
PBRC5.00HR
5.0
On-chip
On-chip
—
4.5
5.5
0.04
PBRC6.00HR
6.0
On-chip
On-chip
—
4.5
5.5
0.04
PBRC6.60HR
6.6
On-chip
On-chip
—
4.5
5.5
0.04
FCR4.0MC5
4.0
On-chip
On-chip
—
4.5
5.5
0.14
FCR5.0MC5
5.0
On-chip
On-chip
—
4.5
5.5
0.13
TDK
Murata Mfg.
Co., Ltd
FCR6.0MC5
6.0
On-chip
On-chip
—
4.5
5.5
0.13
CSTS0400MG06
4.0
On-chip
On-chip
—
4.5
5.5
0.12
CSTCR4M00G55-R0
4.0
On-chip
On-chip
—
4.5
5.5
0.14
CSTS0600MG06
6.0
On-chip
On-chip
—
4.5
5.5
0.16
CSTCR6M00G55-R0
6.0
On-chip
On-chip
—
4.5
5.5
0.19
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken lines.
3. Thoroughly evaluate the matching between the µ PD70F3025A and the resonator.
(2) External clock input
X1
X2
Open
High-speed CMOS inverter
External clock
Cautions 1. Put the high-speed CMOS inverter as close to the X1 pins as possible.
2. Sufficiently evaluate the matching between the µ PD70F3003A, 70F3025A, or 70F3003A(A),
and the high-speed CMOS inverter.
16
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)
(1/2)
Parameter
Input voltage, high
Symbol
VIH
Conditions
MIN.
Except X1 and Note
MAX.
Unit
2.2
VDD + 0.3
V
0.8VDD
VDD + 0.3
V
Except X1 and Note
–0.5
+0.8
V
Note
–0.5
0.2VDD
V
Note
Input voltage, low
VIL
TYP.
Clock input voltage, high
VXH
X1
0.8VDD
VDD + 0.5
V
Clock input voltage, low
VXL
X1
–0.5
0.6
V
Schmitt trigger input threshold voltage
VT
VT
+
–
+
Schmitt trigger input hysteresis width
VT – VT
Output voltage, high
VOH
–
Note, rising
3.0
V
Note, falling
2.0
V
Note
0.5
V
IOH = –2.5 mA
0.7VDD
V
IOH = –100 µA
VDD – 0.4
V
Output voltage, low
VOL
IOC = 2.5 mA
0.45
V
Input leakage current, high
ILIH
VI = VDD
10
µA
Input leakage current, low
ILIL
VI = 0 V
–10
µA
Output leakage current, high
ILOH
VO = VDD
10
µA
Output leakage current, low
ILOL
VO = 0 V
–10
µA
Software pull-up resistor
R
P35/INTP131/SO3,
P36/INTP132/SI3,
P37/INTP133/SCK3
90
kΩ
15
40
Note P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, and their
alternate-function pins.
Remark TYP. values are reference values for when TA = 25°C and VDD = 5.0 V.
Data Sheet U13189EJ5V1DS
17
µPD70F3003A, 70F3025A, 70F3003A(A)
(2/2)
Parameter
Symbol
Supply µPD70F3003A, Operating
IDD1
current 70F3003A(A)
In HALT mode
In IDLE mode
IDD2
IDD3
In STOP mode IDD4
Conditions
MIN.
TYP.
MAX.
Unit
Direct mode
2.2 × φ + 7.5
2.5 × φ + 22
mA
PLL mode
2.3 × φ + 9.5
2.6 × φ + 25
mA
Direct mode
1.2 × φ + 7.5
1.3 × φ + 15
mA
PLL mode
1.3 × φ + 9.5
1.4 × φ + 17
mA
Direct mode
8 × φ + 300
10 × φ + 500
µA
PLL mode
0.1 × φ + 2
0.2 × φ + 3
mA
CESEL = 0, Note 1
2
50
µA
CESEL = 0, Note 2
2
200
µA
CESEL = 1, Note 1
30
200
µA
30
500
µA
Direct mode
2.5 × φ + 8
2.8 × φ + 22.5
mA
PLL mode
2.6 × φ + 10 2.9 × φ + 25.5
mA
Direct mode
1.3 × φ + 7.5
1.4 × φ + 15
mA
PLL mode
1.3 × φ + 12.5 1.4 × φ + 20
mA
CESEL = 1, Note 2
µPD70F3025A Operating
In HALT mode
In IDLE mode
IDD1
IDD2
IDD3
In STOP mode IDD4
Direct mode
8 × φ + 300
10 × φ + 500
µA
PLL mode
0.1 × φ + 2
0.2 × φ + 3
mA
CESEL = 0, Note 1
2
50
µA
CESEL = 0, Note 2
2
200
µA
CESEL = 1, Note 1
60
300
µA
CESEL = 1, Note 2
60
500
µA
Notes 1. –40°C ≤ TA ≤ +50°C
2. 50°C < TA ≤ 85°C
Remarks 1. TYP. values are reference values for when TA = 25°C (except for the conditions in Note 2) and VDD
= 5.0 V. The power supply current does not include AVREF1 to AVREF3 or the current that flows through
software pull-up resistors.
2. φ: Internal system clock frequency
18
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
Data Retention Characteristics (TA = –40 to +85°C, VDD = VDDDR)
Parameter
Symbol
Conditions
MIN.
TYP.
1.5
MAX.
Unit
5.5
V
Data hold voltage
VDDDR
STOP mode
Data hold current
IDDDR
µPD70F3003A, CESEL = 0, Note 1
0.4VDDDR
50
µA
70F3003A(A)
CESEL = 0, Note 2
0.4VDDDR
200
µA
CESEL = 1, Note 1
6VDDDR
200
µA
CESEL = 1, Note 2
6VDDDR
500
µA
µPD70F3025A CESEL = 0, Note 1
0.4VDDDR
50
µA
CESEL = 0, Note 2
0.4VDDDR
200
µA
CESEL = 1, Note 1
12VDDDR
300
µA
CESEL = 1, Note 2
12VDDDR
500
µA
Supply voltage rise time
tRVD
200
µs
Supply voltage fall time
tFVD
200
µs
Supply voltage hold time
(vs. STOP mode setting)
tHVD
0
ms
STOP mode release signal input time
tDREL
0
ns
Data hold input voltage, high
VIHDR
Note 3
0.9VDDDR
VDDDR
V
Data hold input voltage, low
VILDR
Note 3
0
0.1VDDDR
V
Notes 1. –40°C ≤ TA ≤ +50°C
2. 50°C <TA ≤ 85°C
3. P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, X1, and
their alternate-function pins.
Remark TYP. values are reference values for when TA = 25°C (except for the conditions in Note 2) and VDD =
5.0 V.
Data Sheet U13189EJ5V1DS
19
µPD70F3003A, 70F3025A, 70F3003A(A)
STOP mode is set (at fifth clock after PSC register has been set).
VDD
VDD
VDD
VDDDR
tHVD
RESET (input)
NMI (input)
(Release by falling edge)
tFVD
tRVD
VIHDR
VIHDR
NMI (input)
(Release by rising edge)
VILDR
20
Data Sheet U13189EJ5V1DS
tDREL
µPD70F3003A, 70F3025A, 70F3003A(A)
AC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)
AC test input test points
(a) P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, X1, and
their alternate-function pins
VDD
0.8VDD
0.8VDD
Test points
0V
0.2VDD
0.2VDD
(b) Other than (a)
2.4 V
2.2 V
2.2 V
Test points
0.4 V
0.8 V
0.8 V
AC test output test points
2.2 V
2.2 V
Test points
0.8 V
0.8 V
Load condition
DUT
(tested device)
CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration,
decrease the load capacitance of this device to less then 50 pF by using a buffer.
Data Sheet U13189EJ5V1DS
21
µPD70F3003A, 70F3025A, 70F3003A(A)
(1) Clock timing
Parameter
X1 input cycle
Symbol
<1>
Conditions
tCYX
Direct mode
PLL mode
(PLL lock status)
X1 input width, high
X1 input width, low
X1 input rise time
<2>
<3>
<4>
tWXH
tWXL
tXR
MIN.
MAX.
Unit
15
Note 1
ns
Note 3
ns
151
Note 2
Direct mode
6
ns
PLL mode
60
ns
Direct mode
6
ns
PLL mode
60
ns
Direct mode
PLL mode
X1 input fall time
<5>
tXF
Direct mode
—
φ
ns
10
ns
7
ns
10
ns
Note 4
33
MHz
30
Note 5
ns
PLL mode
CPU operating frequency
7
CLKOUT output cycle
<6>
tCYK
CLKOUT width, high
<7>
tWKH
0.5 T – 5
ns
CLKOUT width, low
<8>
tWKL
0.5 T – 5
ns
CLKOUT rise time
<9>
tXR
5
ns
CLKOUT fall time
<10>
tXF
5
ns
X1 ↓→ CLKOUT delay time
<11>
tDXK
17
ns
Direct mode
3
Notes 1. When A/D converter used: 100 ns
When A/D converter not used: 250 ns
2. When using A/D converter: The value when φ = 5 × fXX and φ = fXX are set. Setting φ = 1/2 × fXX is
prohibited.
When not using A/D converter: The value when φ = 5 × fXX, φ = fXX, and φ = 1/2 × fXX are set.
3. When using A/D converter: 250 ns (when φ = 5 × fXX is set) and 200 ns (when φ = fXX is set). Setting
φ = 1/2 × fXX is prohibited.
When not using A/D converter: 250 ns (when φ = 5 × fXX, φ = fXX, and φ = 1/2 × fXX are set).
4. When A/D converter used: 5 MHz
When A/D converter not used: 2 MHz
5. When A/D converter used: 200 ns
When A/D converter not used: 500 ns
Remark
T = tCYK
<1>
<2>
<3>
X1 (input)
<4>
<11>
<5>
<6>
<11>
<7>
<8>
CLKOUT (output)
<9>
22
Data Sheet U13189EJ5V1DS
<10>
µPD70F3003A, 70F3025A, 70F3003A(A)
(2) Input wave
(a) P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, and their
alternate-function pins
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Input rise time
<12>
tIR2
20
ns
Input fall time
<13>
tIF2
20
ns
VDD
0.8VDD
0.8VDD
Input signal
0.2VDD
0V
0.2VDD
< 13 >
< 12 >
(b) Other than (a)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Input rise time
<14>
tIR1
10
ns
Input fall time
<15>
tIF1
10
ns
2.4 V
2.2 V
2.2 V
Input signal
0.4 V
0.8 V
< 15 >
Data Sheet U13189EJ5V1DS
0.8 V
< 14 >
23
µPD70F3003A, 70F3025A, 70F3003A(A)
(3) Output wave (other than CLKOUT)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Output rise time
<16>
tOR
10
ns
Output fall time
<17>
tOF
10
ns
2.2 V
2.2 V
Output signal
0.8 V
0.8 V
< 16 >
< 17 >
(4) Reset timing
Parameter
Symbol
Conditions
RESET width, high
<18>
tWRSH
RESET width, low
<19>
tWRSL
On power application, or on
releasing STOP
mode
Except on power
application, or
except on releasing STOP mode
MIN.
RESET (input)
24
Data Sheet U13189EJ5V1DS
Unit
500
ns
500 + TOST
ns
500
ns
Remark TOST: Oscillation stabilization time
< 18 >
MAX.
< 19 >
µPD70F3003A, 70F3025A, 70F3003A(A)
(5) Read timing (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT↑ to address
<20>
tDKA
3
20
ns
Delay time from CLKOUT↑ to R/W, UBEN, LBEN
<78>
tDKA2
–2
+13
ns
Delay time from CLKOUT↑ to address float <21>
tFKA
3
15
ns
Delay time from CLKOUT↓ to ASTB
<22>
tDKST
3
15
ns
Delay time from CLKOUT↓ to DSTB
15
ns
<23>
tDKD
3
Data input setup time (to CLKOUT↑) <24>
tSIDK
5
ns
Data input hold time (from CLKOUT↑)
<25>
tHKID
5
ns
WAIT setup time (to CLKOUT↓)
<26>
tSWTK
5
ns
WAIT hold time (from CLKOUT↓)
<27>
tHKWT
5
ns
Address hold time (from CLKOUT↑)
<28>
tHKA
Address setup time (to ASTB↓)
<29>
tSAST
Address hold time (from ASTB↓)
<30>
tHSTA
Delay time from DSTB↓ to address float
<31>
tFDA
Data input setup time (to address)
<32>
tSAID
0
ns
–40°C ≤ TA ≤ +70°C
0.5 T – 10
ns
70°C < TA ≤ 85°C
0.5 T – 12
ns
0.5 T – 10
Data input setup time (to DSTB↓)
<33>
tSDID
Delay time from ASTB↓ to DSTB↓
<34>
tDSTD
Data input hold time (from DSTB↑) <35>
tHDID
Delay time from DSTB↑ to address output
<36>
tDDA
Delay time from DSTB↑ to ASTB↑
<37>
tDDSTH
Delay time from DSTB↑ to ASTB↓
<38>
tDDSTL
DSTB low-level width
<39>
tWDL
ns
–40°C ≤ TA ≤ +70°C
(2 + n) T – 22
ns
70°C < TA ≤ 85°C
(2 + n) T – 25
ns
–40°C ≤ TA ≤ +70°C
(1 + n) T – 20
ns
70°C < TA ≤ 85°C
ASTB high-level width
<40>
tWSTH
<41>
tSAWT1
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
(1 + n) T – 24
0.5 T – 10
WAIT setup time (to address)
<42>
ns
0
0
ns
(1 + i) T
ns
0.5 T – 10
ns
(1.5 + i) T – 10
ns
–40°C ≤ TA ≤ +70°C
(1 + n) T – 10
ns
70°C < TA ≤ 85°C
(1 + n) T – 13
ns
T – 10
tSAWT2
ns
n ≥ 1, –40°C ≤ TA ≤ +70°C
1.5 T – 20
ns
n ≥ 1, 70°C < TA ≤ 85°C
1.5 T – 24
ns
n ≥ 1, –40°C ≤ TA ≤ +70°C
(1.5 + n) T – 20
ns
n ≥ 1, 70°C < TA ≤ 85°C
(1.5 + n) T – 24
ns
<43>
tHAWT1
n≥1
(0.5 + n) T
ns
<44>
tHAWT2
n≥1
(1.5 + n) T
ns
<45>
tSSTWT1
n ≥ 1, –40°C ≤ TA ≤ +70°C
<46>
tSSTWT2
n≥1
<47>
tHSTWT1
n≥1
nT
ns
<48>
tHSTWT2
n≥1
(1 + n) T
ns
T – 18
ns
T – 20
ns
(1 + n) T – 15
ns
n ≥ 1, 70°C < TA ≤ 85°C
WAIT hold time (from ASTB↓)
ns
ns
Remarks 1. T = tCYK
2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when
the programmable wait state is inserted.
3. i indicates the number of idle states (0 or 1) t be inserted in the read cycle.
4. Be sure to observe at least one of data input hold times tHKID (<25>) and tHDID (<35>).
Data Sheet U13189EJ5V1DS
25
µPD70F3003A, 70F3025A, 70F3003A(A)
(5) Read Timing (2/2): 1 wait
T1
T2
TW
T3
CLKOUT (output)
< 20 >
< 28 >
A16 to A19 (output)
< 78 >
R/W (output)
UBEN (output)
LBEN (output)
< 32 >
< 21 >
AD0-AD15 (I/O)
< 24 >
A0 to A15 (output)
D0 to D15 (input)
< 22 >
< 29 >
< 25 >
< 35 >
< 30 >
< 22 >
ASTB (output)
< 40>
< 37 >
< 23 >< 31 >
< 34 >
< 23 >
< 33 >
< 36 >
DSTB (output)
< 38 >
< 39 >
< 45 > < 26 >
< 27 >
< 26 >
< 47 >
< 46 >
< 48 >
WAIT (input)
< 41 >
< 43 >
< 42 >
< 44 >
Remark Broken line indicates high-impedance.
26
Data Sheet U13189EJ5V1DS
< 27 >
µPD70F3003A, 70F3025A, 70F3003A(A)
(6) Write timing (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
Delay time from CLKOUT↑ to address
<20>
tDKA
3
20
Delay time from CLKOUT↑ to R/W, UBEN, LBEN
<78>
tDKA2
–2
+13
ns
Delay time from CLKOUT↓ to ASTB
<22>
tDKST
3
15
ns
Delay time from CLKOUT↑ to DSTB
<23>
tDKD
3
15
ns
WAIT setup time (to CLKOUT↓)
<26>
tSWTK
5
ns
WAIT hold time (from CLKOUT↓)
<27>
tHKWT
5
ns
Address hold time (from CLKOUT↑)
<28>
tHKA
Address setup time (to ASTB↓)
<29>
tSAST
0
ns
–40°C ≤ TA ≤ +70°C
0.5 T – 10
ns
70°C < TA ≤ 85°C
0.5 T – 12
ns
Address hold time (from ASTB↓)
<30>
tHSTA
0.5 T – 10
ns
Delay time from ASTB↓ to DSTB↓
<34>
tDSTD
0.5 T – 10
ns
Delay time from DSTB↑ to ASTB↑
<37>
tDDSTH
0.5 T – 10
ns
DSTB low-level width
<39>
tWDL
ASTB high-level width
<40>
tWSTH
WAIT setup time (to address)
<41>
tSAWT1
<42>
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
–40°C ≤ TA ≤ +70°C
(1 + n) T – 10
ns
70°C < TA ≤ 85°C
(1 + n) T – 13
ns
T – 10
tSAWT2
1.5 T – 20
ns
n ≥ 1, 70°C < TA ≤ 85°C
1.5 T – 24
ns
n ≥ 1, –40°C ≤ TA ≤ +70°C
(1.5 + n) T – 20
ns
n ≥ 1, 70°C < TA ≤ 85°C
(1.5 + n) T – 24
ns
<43>
tHAWT1
n≥1
(0.5 + n) T
<44>
tHAWT2
n≥1
(1.5 + n) T
<45>
tSSTWT1
n ≥ 1, –40°C ≤ TA ≤ +70°C
<46>
tSSTWT2
n≥1
<47>
tHSTWT1
n≥1
nT
<48>
tHSTWT2
n≥1
(1 + n) T
<49>
tDKOD
–40°C ≤ TA ≤ +70°C
20
ns
70°C < TA ≤ 85°C
23
ns
10
ns
n ≥ 1, 70°C < TA ≤ 85°C
WAIT hold time (from ASTB↓)
Address hold time (from CLKOUT↑)
ns
n ≥ 1, –40°C ≤ TA ≤ +70°C
ns
ns
T – 18
ns
T – 20
ns
(1 + n) T – 15
ns
ns
ns
Delay time from DSTB↓ to data output <50>
tDDOD
Data output hold time (from CLKOUT↑)
<51>
tHKOD
0
Data output setup time (to DSTB↑) <52>
tSODD
(1 + n) T – 15
ns
Data output hold time (from DSTB↑)
tHDOD
T – 10
ns
<53>
ns
Remarks 1. T = tCYK
2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when
the programmable wait state is inserted.
Data Sheet U13189EJ5V1DS
27
µPD70F3003A, 70F3025A, 70F3003A(A)
(6) Write timing (2/2): 1 wait
T1
T2
TW
T3
CLKOUT (output)
< 20 >
< 28 >
A16 to A19 (output)
< 78 >
R/W (output)
UBEN (output)
LBEN (output)
< 49 >
AD0-AD15 (I/O)
< 51 >
A0 to A15 (output)
D0 to D15 (output)
< 22 >
< 29 >
< 30 >
< 22 >
ASTB (output)
< 23 >
< 23 >
< 40 >
< 34 >
< 53 >
< 52 >
< 50 >
DSTB (output)
< 39 >
< 45 > < 26 >
< 27 >
< 26 >
< 47 >
< 46 >
< 48 >
WAIT (input)
< 41 >
< 43 >
< 42 >
< 44 >
Remark Broken line indicates high-impedance.
28
Data Sheet U13189EJ5V1DS
< 37 >
< 27 >
µPD70F3003A, 70F3025A, 70F3003A(A)
(7) Bus hold timing (1/2)
Parameter
HLDRQ setup time (to CLKOUT↓)
Symbol
Conditions
MIN.
MAX.
Unit
<54>
tSHOK
5
ns
HLDRQ hold time (from CLKOUT↓) <55>
tHKHQ
5
ns
Delay time from HLDAK to CLKOUT↑ <56>
tDKHA
HLDRQ high-level width
<57>
tWHQH
HLDAK low-level width
<58>
tWHAL
20
Delay time from CLKOUT↑ to bus float <59>
tDKF
Delay time from HLDAK↑ to bus output <60>
tDHAC
Delay time from HLDRQ↓ to HLDAK↓
<61>
tDHQHA1
Delay time from HLDRQ↑ to HLDAK↑
<62>
tDHQHA2
ns
T + 10
ns
–40°C ≤ TA ≤ +70°C
T – 10
ns
70°C < TA ≤ 85°C
T – 12
ns
20
–3
0.5 T
ns
ns
(2 n + 7.5) T + 20
ns
1.5 T + 20
ns
Remarks 1. T = tCYK
2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when
the programmable wait state is inserted.
Data Sheet U13189EJ5V1DS
29
µPD70F3003A, 70F3025A, 70F3003A(A)
(7) Bus hold timing (2/2)
TH
TH
TH
TH
TI
CLKOUT (output)
< 54 >
< 54 > < 55 >
< 57 >
HLDRQ (input)
< 56 >
< 56 >
< 61 >
< 62 >
HLDAK (output)
< 58 >
< 60 >
< 59 >
A16 to A19 (output)
Note
AD0 to AD15 (I/O)
D0 to D15
(input or output)
ASTB (output)
DSTB (output)
R/W (output)
Note UBEN (output), LBEN (output)
Remark Broken line indicates high-impedance.
30
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
(8) Interrupt timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
NMI width, high
<63>
tWNIH
500
ns
NMI width, low
<64>
tWNIL
500
ns
INTPn width, high
<65>
tWITH
n = 110 to 113,
120 to 123, 130
to 133, 140 to 143
3 T + 10
ns
INTPn width, low
<66>
tWITL
n = 110 to 113,
120 to 123, 130
to 133, 140 to 143
3 T + 10
ns
Remark T = tCYK
< 63 >
< 64 >
< 65 >
< 66>
NMI (input)
INTPn (input)
Remark n = 110 to 113, 120 to 123, 130 to 133, 140 to 143
Data Sheet U13189EJ5V1DS
31
µPD70F3003A, 70F3025A, 70F3003A(A)
(9) CSI timing (1/2)
(a) Master mode
(i)
CSI0 to CSI2 timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle
<67>
tCYSK1
Output
120
ns
SCKn high-level width
<68>
tWSKH1
Output
0.5 tCYSK1 – 20
ns
SCKn low-level width
<69>
tWSKL1
Output
0.5 tCYSK1 – 20
ns
SIn setup time (to SCKn↑)
<70>
tSSISK1
30
ns
SIn hold time (from SCKn↑)
<71>
tHSKSI1
0
ns
SOn output delay time (from SCKn↓)
<72>
tDSKSO1
SOn output hold time (from SCKn↑)
<73>
tHSKSO1
18
0.5 tCYSK1 – 5
ns
ns
Remark n = 0 to 2
(ii) CSI3 timing
Parameter
SCK3 cycle
Symbol
<67>
SCK3 high-level width
<68>
SCK3 low-level width
SI3 setup time (to SCK3↑)
Conditions
tCYSK3
Output
RL = 1.5
kΩ
CL = 50
pF
MIN.
MAX.
Unit
500
ns
0.5 tCYSK3 – 70
ns
tWSKH3
Output
<69>
tWSKL3
Output
0.5 tCYSK3 – 70
ns
<70>
tSSISK3
100
ns
SI3 hold time (from SCK3↑)
<71>
tHSKSI3
50
ns
SO3 output delay time (from SCK3↓)
<72>
tDSKSO3
SO3 output hold time (from SCK3↑)
<73>
tHSKSO3
RL = 1.5 KΩ
CL = 50 pF
150
0.5 tCYSK3 – 5
ns
ns
Remark R L and C L are the load resistance and load capacitance respectively of the SCK3 and SO3 output
lines.
(b) Slave mode
(i)
CSI0 to CSI2 timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle
<67>
tCYSK2
Input
120
ns
SCKn high-level width
<68>
tWSKH2
Input
30
ns
SCKn low-level width
<69>
tWSKL2
Input
30
ns
SIn setup time (to SCKn↑)
<70>
tSSISK2
10
ns
SIn hold time (from SCKn↑)
<71>
tHSKSI2
10
ns
SOn output delay time (from SCKn↓)
<72>
tDSKSO2
SOn output hold time (from SCKn↑)
<73>
tHSKSO2
Remark n = 0 to 2
32
Data Sheet U13189EJ5V1DS
30
tWSKH2
ns
ns
µPD70F3003A, 70F3025A, 70F3003A(A)
(9) CSI timing (2/2)
(ii) CSI3 timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCK3 cycle
<67>
tCYSK4
Input
500
ns
SCK3 high-level width
<68>
tWSKH4
Input
180
ns
SCK3 low-level width
<69>
tWSKL4
Input
180
ns
SI3 setup time (to SCK3↑)
<70>
tSSISK4
100
ns
SI3 hold time (from SCK3↑)
<71>
tHSKSI4
50
ns
SO3 output delay time (from SCK3↓) <72>
tDSKSO4
RL = 1.5 kΩ
<73>
tHSKSO4
CL = 50 pF
SO3 output hold time (from SCK3↑)
150
tWSKH4
ns
ns
Remark R L and C L are the load resistance and load capacitance respectively of the SCK3 and SO3 output
lines.
< 67 >
< 69 >
< 68 >
SCKn (I/O)
< 70 >
SIn (input)
< 71 >
Input data
< 72 >
< 73 >
SOn (output)
Output data
Remark 1. The broken line indicates the high-impedance state.
2. n = 0 to 3
Data Sheet U13189EJ5V1DS
33
µPD70F3003A, 70F3025A, 70F3003A(A)
(10) RPU timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
TI1n high-level width
<74>
tWTIH
3 T + 10
ns
TI1n low-level width
<75>
tWTIL
3 T + 10
ns
TCLR1n high-level width
<76>
tWTCH
3 T + 10
ns
TCLR1n low-level width
<77>
tWTCL
3 T + 10
ns
Remark T = tCYK
<74>
<75>
<76>
<77>
TI1n (input)
TCLR1n (input)
Remark n = 1 to 4
34
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)
Parameter
Symbol
Resolution
Overall error
Conditions
MIN.
TYP.
MAX.
Unit
10
10
10
bit
—
Note 1
Quantization error
4.5 V ≤ AVREF1 ≤ AVDD
±0.4
%FSR
—
3.5 V ≤ AVREF1 ≤ AVDD
±0.7
%FSR
±1/2
LSB
—
Conversion time
tCONV
Sampling time
tSAMP
Zero-scale error
Full-scale error
—
Note 1
Note 1
Non-linearity error
Note 1
4.5 V ≤ AVREF1 ≤ AVDD
60
tCYK
3.5 V ≤ AVREF1 ≤ AVDD
60
tCYK
4.5 V ≤ AVREF1 ≤ AVDD
10
tCYK
3.5 V ≤ AVREF1 ≤ AVDD
10
tCYK
—
4.5 V ≤ AVREF1 ≤ AVDD
±1.5
±3.5
LSB
—
3.5 V ≤ AVREF1 ≤ AVDD
±1.5
±4.5
LSB
—
4.5 V ≤ AVREF1 ≤ AVDD
±1.5
±2.5
LSB
—
3.5 V ≤ AVREF1 ≤ AVDD
±1.5
±4.5
LSB
—
4.5 V ≤ AVREF1 ≤ AVDD
±1.5
±2.5
LSB
—
3.5 V ≤ AVREF1 ≤ AVDD
±1.5
±4.5
LSB
Analog input
voltageNote 2
VIAN
–0.3
AVDD + 0.3
V
Reference voltage
AVREF1
3.5
AVDD
V
AVREF1 current
AIREF1
1.2
3.0
mA
AVDD supply current
AIDD
2.3
6.0
mA
Notes 1. Except quantization error.
2. The conversion result is 000H when VIAN = 0.
Converted with 10-bit resolution when 0 < VIAN < AVREF1.
The conversion result is 3FFH when AVREF1 ≤ VIAN ≤ AVDD.
Data Sheet U13189EJ5V1DS
35
µPD70F3003A, 70F3025A, 70F3003A(A)
D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
8
8
bit
Resolution
—
Overall error
—
Load conditions: 2 MΩ, 30 pF
AVREF2 = VDD
AVREF3 = 0
0.8
%
—
Load conditions: 2 MΩ, 30 pF
AVREF2 = 0.75 VDD
AVREF3 = 0.25 VDD
1.0
%
—
Load conditions: 4 MΩ, 30 pF
AVREF2 = VDD
AVREF3 = 0
0.6
%
—
Load conditions: 4 MΩ, 30 pF
AVREF2 = 0.75 VDD
AVREF3 = 0.25 VDD
0.8
%
—
Load conditions: 2 MΩ, 30 pF
10
µs
Settling time
Output resistance
RO
AVREF2 input voltage
AVREF2
0.75VDD
VDD
V
AVREF3 input voltage
AVREF3
0
0.25VDD
V
Resistance between
AVREF2 and AVREF3
RAIREF
36
8
DACS0, DACS1 = 55H
Data Sheet U13189EJ5V1DS
2
4
kΩ
kΩ
µPD70F3003A, 70F3025A, 70F3003A(A)
3.2 Flash Memory Programming Mode
Basic Characteristics (TA = 10 to 40°C (when rewriting), TA = –40 to +85°C (when not rewriting), VDD = AVDD
= 5 V ±10%, VSS = AVSS = 0 V))
(1) µPD70F3003A (all ranks), 70F3025A (except K, E, P, X rank)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
33
MHz
10.6
V
Operating frequency
φ
VPP supply voltage
VPP1
During flash memory programming
9.7
VPPL
VPP low-level detection
–0.5
0.2VDD
V
VPPM
VPP, VDD level detection
0.8VDD
1.2VDD
V
VPPH
VPP high-voltage level detection
10.6
V
VDD supply current
IDO
VPP = VPP1
3.0 × φ + 25
mA
VPP supply current
IPP
VPP = 10.3 V
200
mA
Step erase time
tER
Note 1
Overall erase time per area
tERA
When the step erase time = 0.2 s, Note 2
Write-back time
tWB
Note 3
Number of write-backs per
CWB
write-back command
10
9.7
10.3
10.3
0.2
s
40
5
When the write-back time
ms
50
= 5 ms, Note 4
Number of erase/write-backs
CERWB
Step writing time
tWT
Overall writing time per word
tWTW
When the step writing time = 50
µs (1 word = 4 bytes), Note 6
Number of rewrites per area
CERWR
1 erase + 1 write after erase
= 1 rewrite, Note 7
s/area
Count/writeback command
16
Note 5
Count
µs
50
50
500
20
µs/word
Count/area
Notes 1. The recommended setting value of the step erase time is 0.2 s.
2. The prewrite time prior to erasure and the erase verify time (write-back time) are not included.
3. The recommended setting value of the step erase time is 5 ms.
4. Write-back is executed once by the issuance of the write-back command. Therefore, the retry count
must be the maximum value minus the number of commands issued.
5. The recommended setting value of the step writing time is 50 µs.
6. 100 µs is added to the actual writing time per word. The internal verify time during and after the writing
is not included.
7. When writing initially to shipped products, it is counted as one rewrite for both “erase to write” and “write
only”.
Example (P: Write, E: Erase)
Shipped product
→ P→ E → P → E → P: 3 rewrites
Shipped product → E → P → E → P → E → P: 3 rewrites
Data Sheet U13189EJ5V1DS
37
µPD70F3003A, 70F3025A, 70F3003A(A)
Cautions 1. V PP pull-down resistance value (RV PP ) is recommended to be in the range 5 kΩ to 15 kΩ.
2. Set the transfer rate between programmer and device as follows.
CSI0:
0.2 to 1 MHz
UART0: 4,800 to 76,800 bps
Remarks 1. When the PG-FP3 is used, a time parameter required for writing/erasing by downloading parameter
files is automatically set. Do not change the settings unless otherwise specified.
2. Area 0 = 00000H to 1FFFFH, area 1 = 20000H to 3FFFFH (area 1 is provided in the µPD70F3025A
only)
3. The rank is indicated by the 5th character from the left in the lot number.
4. The I rank applies to engineering samples (ES) only. The operation of an ES is not guaranteed.
5. φ: Internal system clock frequency
38
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
(2) µPD70F3025A (X rank)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
33
MHz
10.6
V
Operating frequency
φ
Note 1
10
VPP supply voltage
VPP1
During flash memory programming
9.7
VPPL
VPP low-level detection
–0.5
0.2VDD
V
VPPM
VPP, VDD level detection
0.8VDD
1.2VDD
V
VPPH
VPP high-voltage level detection
10.6
V
VDD supply current
IDD
VPP= VPP1
3.0 × φ + 25
mA
VPP supply current
IPP
200
mA
Step erase time
tER
Note 1
Overall erase time per area
tERA
When the step erase time = 2 s, Note 2
Step writing time
tWT
Note 3
Overall writing time per word
tWTW
When the step writing time = 200
µs (1 word = 4 bytes), Note 4
Number of rewrites per area
CERWR
1 erase + 1 write after erase
9.7
10.3
10.3
VPP= 10.3 V
2
s
40
µs
200
200
s/area
2000
20
µs/word
Count/area
= 1 rewrite, Note 5
Notes 1. The recommended setting value of the step erase time is 2 s.
2. The prewrite time prior to erasure and the erase verify time (write-back time) are not included.
3. The recommended setting value of the step writing time is 200 µs.
4. 100 µs is added to the actual writing time per word. The internal verify time during and after the writing
is not included.
5. When writing initially to shipped products, it is counted as one rewrite for both “erase to write” and “write
only”.
Example (P: Write, E: Erase)
→ P → E → P → E → P: 3 rewrites
Shipped product
Shipped product → E → P → E → P → E → P: 3 rewrites
Cautions 1. V PP pull-down resistance value (RV PP) is recommended to be in the range 5 kΩ to 15 kΩ.
2. Set the transfer rate between programmer and device as follows.
CSI0:
0.2 to 1 MHz
UART0: 4,800 to 76,800 bps
Remarks 1. When the PG-FP3 is used, a time parameter required for writing/erasing by downloading parameter
files is automatically set. Do not change the settings unless otherwise specified.
2. Area 0 = 00000H to 1FFFFH, area 1 = 20000H to 3FFFFH
3. The rank is indicated by the 5th character from the left in the lot number.
4. The K, E, P, and X rank products do not support handshake mode. The I rank applies to engineering
samples (ES) only. The operation of an ES is not guaranteed.
5. φ: Internal system clock frequency
Data Sheet U13189EJ5V1DS
39
µPD70F3003A, 70F3025A, 70F3003A(A)
4. PACKAGE DRAWING
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A
B
75
76
51
50
detail of lead end
S
C D
Q
R
26
25
100
1
F
G
H
I
J
M
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
16.00±0.20
B
14.00±0.20
C
14.00±0.20
D
16.00±0.20
F
1.00
G
1.00
H
0.22 +0.05
−0.04
I
J
0.08
0.50 (T.P.)
K
1.00±0.20
L
0.50±0.20
M
0.17 +0.03
−0.07
N
0.08
P
1.40±0.05
Q
0.10±0.05
R
+7°
3° −3°
S
1.60 MAX.
S100GC-50-8EU, 8EA-2
40
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
5. RECOMMENDED SOLDERING CONDITIONS
The µ PD70F3003A, 70F3025A, and 70F3003A(A) should be soldered and mounted under the following
recommended conditions.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 5-1. Surface Mounting Type Soldering Conditions
(1) µPD70F3003AGC-33-8EU:
100-pin plastic LQFP (fine pitch) (14 × 14)
µPD70F3025AGC-33-8EU:
100-pin plastic LQFP (fine pitch) (14 × 14)
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds max.
Recommended
Condition Symbol
IR35-103-3
(at 210°C or higher), Count: Three times or less, Exposure
limit: 3 daysNote (after that, prebake at 125°C for 10 to 72 hours)
VPS
Package peak temperature: 215°C, Time: 25 to 40 seconds
(at 200°C or higher), Count: Three times or less, Exposure
limit: 3 daysNote (after that, prebake at 125°C for 10 to 72 hours)
Partial heating
Pin temperature: 300°C max., Time 3 seconds max.
(per pin row)
Note
VP15-103-3
—
After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark For soldering methods and conditions other than those recommended above, consult an NEC Electronics
sales representative.
(2) µPD70F3003AGC-33-8EU-A: 100-pin plastic LQFP (fine pitch) (14 × 14)
µPD70F3025AGC-33-8EU-A: 100-pin plastic LQFP (fine pitch) (14 × 14)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 260°C, Time: 60 seconds max.
(at 220°C or higher), Count: Three times or less, Exposure
limit: 7 daysNote (after that, prebake at 125°C for 20 to 72 hours)
Wave soldering
For details,consult an NEC Electronics sales representative.
—
Partial heating
Pin temperature: 350°C max., Time: 3 seconds max.
(per pin row)
—
Note
IR60-207-3
After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remarks 1. Products with -A at the end of the part number are lead-free products.
2. For soldering methods and conditions other than those recommended above, consult an NEC
Electronics sales representative.
Data Sheet U13189EJ5V1DS
41
µPD70F3003A, 70F3025A, 70F3003A(A)
(3) µPD70F3003AGC(A)-33-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14)
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds max.
(at 210°C or higher), Count: Two times or less, Exposure
limit: 3 daysNote (after that, prebake at 125°C for 10 to 72
Recommended
Condition Symbol
IR35-103-2
hours)
VPS
Package peak temperature: 215°C, Time: 25 to 40 seconds
(at 200°C or higher), Count: Two times or less, Exposure
limit: 3 daysNote (after that, prebake at 125°C for 10 to 72
hours)
Partial heating
Pin temperature: 300°C max., Time 3 seconds max.
(per pin row)
Note
VP15-103-2
—
After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark For soldering methods and conditions other than those recommended above, consult an NEC Electronics
sales representative.
42
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
APPENDIX NOTES ON TARGET SYSTEM DESIGN
The following shows a diagram of the connection conditions between the in-circuit emulator option board
and conversion connector. Design your system making allowances for conditions such as the form of parts
mounted on the target system as shown below.
Side view
In-circuit emulator
IE-703002-MC
In-circuit emulator option board
IE-703003-MC-EM1
132.24 mm
Note
Conversion connector
YQGUIDE
YQPACK100SD
NQPACK100SD
Target system
Note YQSOCKET100SDN (included with IE-703002-MC) can be inserted here to adjust the height (height: 3.2 mm).
Top view
IE-703002-MC
Target system
Pin 1 position
IE-703003-MC-EM1
YQPACK100SD, NQPACK100SD,
YQGUIDE
Connection
condition diagram
IE-703003-MC-EM1
Connect to
IE-703002-MC.
Pin 1 position
75 mm
YQGUIDE
YQPACK100SD
NQPACK100SD
13.3 mm
31.84 mm
15.24 mm
24 mm
21.58 mm
Data Sheet U13189EJ5V1DS
Target system
43
µPD70F3003A, 70F3025A, 70F3003A(A)
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
44
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
Related document:
µ PD703003A, 703004A, 703025A, 703003A(A), 703025A(A) Data Sheet (U13188E)
Reference Materials Electrical Characteristics for Microcomputer (U15170JNote)
Note This document number is that of Japanese version.
The related documents indicated in this publication may include preliminary versions.
However,
preliminary versions are not marked as such.
Data Sheet U13189EJ5V1DS
45
µPD70F3003A, 70F3025A, 70F3003A(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
NEC Electronics (Europe) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Duesseldorf, Germany
Tel: 0211-65030
Hong Kong
Tel: 2886-9318
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-265 40 10
• Tyskland Filial
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-558-3737
NEC Electronics Shanghai Ltd.
Shanghai, P.R. China
Tel: 021-5888-5400
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
Taeby, Sweden
Tel: 08-63 87 200
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J05.6
46
Data Sheet U13189EJ5V1DS
µPD70F3003A, 70F3025A, 70F3003A(A)
• The information in this document is current as of July, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
• NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1