To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
When exporting the products or technology described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas
Electronics products or the technology described in this document for any purpose relating to military applications or use by
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Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and
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consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”:
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
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damages arising out of the use of Renesas Electronics products beyond such specified ranges.
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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
R8C/24 Group, R8C/25 Group
SINGLE-CHIP 16-BIT CMOS MCU
1.
REJ03B0117-0300
Rev.3.00
Feb 29, 2008
Overview
These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C/Tiny Series
CPU core, and are packaged in a 52-pin molded-plastic LQFP or a 64-pin molded-plastic FLGA. It implements
sophisticated instructions for a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of
executing instructions at high speed.
Furthermore, the R8C/25 Group has on-chip data flash (1 KB x 2 blocks).
The difference between the R8C/24 Group and R8C/25 Group is only the presence or absence of data flash. Their
peripheral functions are the same.
1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer products, etc.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 1 of 51
R8C/24 Group, R8C/25 Group
1.2
1. Overview
Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/24 Group and Table 1.2 outlines the Functions and
Specifications for R8C/25 Group.
Table 1.1
Functions and Specifications for R8C/24 Group
Item
Specification
CPU
Number of fundamental
89 instructions
instructions
Minimum instruction execution
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
time
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
Operating mode
Single-chip
Address space
1 Mbyte
Memory capacity
Refer to Table 1.3 Product Information for R8C/24 Group
Peripheral
Ports
I/O ports: 41 pins, Input port: 3 pins
Functions
LED drive ports
I/O ports: 8 pins
Timers
Timer RA: 8 bits × 1 channel
Timer RB: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RD: 16 bits × 2 channels
(Input capture and output compare circuits)
Timer RE: With real-time clock and compare match function
Serial interfaces
2 channels (UART0, UART1)
Clock synchronous serial I/O, UART
Clock synchronous serial
1 channel
interface
I2C bus Interface(1)
Clock synchronous serial I/O with chip select
LIN module
Hardware LIN: 1 channel (timer RA, UART0)
A/D converter
10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer
15 bits × 1 channel (with prescaler)
Reset start selectable
Interrupts
Internal: 11 sources, External: 5 sources, Software: 4
sources, Priority levels: 7 levels
Clock
Clock generation 3 circuits
circuits
• XIN clock generation circuit (with on-chip feedback resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has a frequency
adjustment function
• XCIN clock generation circuit (32 kHz)
Real-time clock (timer RE)
Oscillation stop detection function XIN clock oscillation stop detection function
Voltage detection circuit
On-chip
Power-on reset circuit
On-chip
Electrical
Supply voltage
VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)
Characteristics
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz)
Current consumption
Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Programming and erasure endurance 100 times
Operating Ambient Temperature
-20 to 85°C (N version)
-40 to 85°C (D version)(2)
-20 to 105°C (Y version)(3)
Package
52-pin molded-plastic LQFP
64-pin molded-plastic FLGA
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version if D version functions are to be used.
3. Please contact Renesas Technology sales offices for the Y version.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 2 of 51
R8C/24 Group, R8C/25 Group
Table 1.2
1. Overview
Functions and Specifications for R8C/25 Group
Item
Specification
Number of fundamental
89 instructions
instructions
Minimum instruction execution 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
time
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
Operating mode
Single-chip
Address space
1 Mbyte
Memory capacity
Refer to Table 1.4 Product Information for R8C/25 Group
Peripheral
Ports
I/O ports: 41 pins, Input port: 3 pins
Functions
LED drive ports
I/O ports: 8 pins
Timers
Timer RA: 8 bits × 1 channel
Timer RB: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RD: 16 bits × 2 channels
(Input capture and output compare circuits)
Timer RE: With real-time clock and compare match function
Serial interface
2 channels (UART0, UART1)
Clock synchronous serial I/O, UART
Clock synchronous serial
1 channel
interface
I2C bus Interface(1)
Clock synchronous serial I/O with chip select
LIN module
Hardware LIN: 1 channel (timer RA, UART0)
A/D converter
10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer
15 bits × 1 channel (with prescaler)
Reset start selectable
Interrupts
Internal: 11 sources, External: 5 sources, Software: 4
sources, Priority levels: 7 levels
Clock
Clock generation 3 circuits
circuits
• XIN clock generation circuit (with on-chip feedback
resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has a frequency
adjustment function
• XCIN clock generation circuit (32 kHz)
Real-time clock (timer RE)
Oscillation stop detection function XIN clock oscillation stop detection function
Voltage detection circuit
On-chip
Power-on reset circuit
On-chip
Electrical
Supply voltage
VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)
Characteristics
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz)
Current consumption
Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Flash memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Programming and erasure
1,0000 times (data flash)
endurance
1,000 times (program ROM)
Operating Ambient Temperature
-20 to 85°C (N version)
-40 to 85°C (D version)(2)
-20 to 105°C (Y version)(3)
Package
52-pin molded-plastic LQFP
64-pin molded-plastic FLGA
CPU
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version if D version functions are to be used.
3. Please contact Renesas Technology sales offices for the Y version.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 3 of 51
R8C/24 Group, R8C/25 Group
1.3
1. Overview
Block Diagram
Figure 1.1 shows a Block Diagram.
I/O ports
8
8
8
6
Port P0
Port P1
Port P2
Port P3
3
3
8
Port P4
Port P6
Peripheral functions
System clock
generation circuit
A/D converter
(10 bits × 12 channels)
Timers
Timer RA (8 bits)
Timer RB (8 bits)
Timer RD
(16 bits × 2 channels)
Timer RE (8 bits)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
UART or
clock synchronous serial I/O
(8 bits × 2 channels)
I2C bus interface or clock synchronous
serial I/O with chip select
(8 bits × 1 channel)
LIN module
(1 channel)
Watchdog timer
(15 bits)
R8C/Tiny Series CPU core
R0H
R1H
R0L
R1L
R2
R3
SB
ROM(1)
USP
ISP
INTB
A0
A1
FB
Memory
RAM(2)
PC
FLG
Multiplier
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.1
Block Diagram
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 4 of 51
R8C/24 Group, R8C/25 Group
1.4
1. Overview
Product Information
Table 1.3 lists the Product Information for R8C/24 Group and Table 1.4 lists the Product Information for R8C/25
Group.
Table 1.3
Product Information for R8C/24 Group
Type No.
R5F21244SNFP
R5F21245SNFP
R5F21246SNFP
R5F21247SNFP
R5F21248SNFP
R5F21244SNLG
R5F21246SNLG
R5F21244SDFP
R5F21245SDFP
R5F21246SDFP
R5F21247SDFP
R5F21248SDFP
R5F21244SNXXXFP
R5F21245SNXXXFP
R5F21246SNXXXFP
R5F21247SNXXXFP
R5F21248SNXXXFP
R5F21244SNXXXLG
R5F21246SNXXXLG
R5F21244SDXXXFP
R5F21245SDXXXFP
R5F21246SDXXXFP
R5F21247SDXXXFP
R5F21248SDXXXFP
ROM Capacity
16 Kbytes
24 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
16 Kbytes
32 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
16 Kbytes
32 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
RAM Capacity
1 Kbyte
2 Kbytes
2 Kbytes
2.5 Kbytes
3 Kbytes
1 Kbyte
2 Kbytes
1 Kbyte
2 Kbytes
2 Kbytes
2.5 Kbytes
3 Kbytes
1 Kbyte
2 Kbytes
2 Kbytes
2.5 Kbytes
3 Kbytes
1 Kbyte
2 Kbytes
1 Kbyte
2 Kbytes
2 Kbytes
2.5 Kbytes
3 Kbytes
NOTE:
1. The user ROM is programmed before shipment.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 5 of 51
Current of Feb. 2008
Package Type
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PTLG0064JA-A
PTLG0064JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PTLG0064JA-A
PTLG0064JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
Remarks
N version
Blank product
D version
Blank product
N version
Factory
programming
product(1)
D version
Factory
programming
product(1)
R8C/24 Group, R8C/25 Group
Type No.
1. Overview
R 5 F 21 24 6 S N XXX FP
Package type:
FP: PLQP0052JA-A (0.65 mm pin-pitch, 10 mm square body)
LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
Y: Operating ambient temperature -20°C to 105°C(1)
S: Low-voltage version
ROM capacity
4: 16 KB
5: 24 KB
6: 32 KB
7: 48 KB
8: 64 KB
R8C/24 Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
NOTE:
1. Please contact Renesas Technology sales offices for the Y version.
Figure 1.2
Type Number, Memory Size, and Package of R8C/24 Group
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 6 of 51
R8C/24 Group, R8C/25 Group
Table 1.4
1. Overview
Product Information for R8C/25 Group
Type No.
R5F21254SNFP
R5F21255SNFP
R5F21256SNFP
R5F21257SNFP
R5F21258SNFP
R5F21254SNLG
R5F21256SNLG
R5F21254SDFP
R5F21255SDFP
R5F21256SDFP
R5F21257SDFP
R5F21258SDFP
R5F21254SNXXXFP
R5F21255SNXXXFP
R5F21256SNXXXFP
R5F21257SNXXXFP
R5F21258SNXXXFP
R5F21254SNXXXLG
R5F21256SNXXXLG
R5F21254SDXXXFP
R5F21255SDXXXFP
R5F21256SDXXXFP
R5F21257SDXXXFP
R5F21258SDXXXFP
ROM Capacity
Program ROM
Data flash
16 Kbytes
1 Kbyte × 2
24 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
24 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
24 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
24 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
NOTE:
1. The user ROM is programmed before shipment.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 7 of 51
Current of Feb. 2008
RAM
Capacity
1 Kbyte
2 Kbytes
2 Kbytes
2.5 Kbytes
3 Kbytes
1 Kbyte
2 Kbytes
1 Kbyte
2 Kbytes
2 Kbytes
2.5 Kbytes
3 Kbytes
1 Kbyte
2 Kbytes
2 Kbytes
2.5 Kbytes
3 Kbytes
1 Kbyte
2 Kbytes
1 Kbyte
2 Kbytes
2 Kbytes
2.5 Kbytes
3 Kbytes
Package Type
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PTLG0064JA-A
PTLG0064JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PTLG0064JA-A
PTLG0064JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
Remarks
N version
Blank product
D version
Blank product
N version
Factory
programming
product(1)
D version
Factory
programming
product(1)
R8C/24 Group, R8C/25 Group
Type No.
1. Overview
R 5 F 21 25 6 S N XXX FP
Package type:
FP: PLQP0052JA-A (0.65 mm pin-pitch, 10 mm square body)
LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
Y: Operating ambient temperature -20°C to 105°C(1)
S: Low-voltage version
ROM capacity
4: 16 KB
5: 24 KB
6: 32 KB
7: 48 KB
8: 64 KB
R8C/25 Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
NOTE:
1. Please contact Renesas Technology sales offices for the Y version.
Figure 1.3
Type Number, Memory Size, and Package of R8C/25 Group
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 8 of 51
R8C/24 Group, R8C/25 Group
1.5
1. Overview
Pin Assignments
NC
P0_7/AN0
P6_3
P6_4
P6_5/CLK1
P3_0/TRAO
P3_1/TRBO
P1_0/KI0/AN8
P1_1/KI1/AN9
P1_2/KI2/AN10
P6_7/INT3/RXD1
P6_6/INT2/TXD1
P4_5/INT0
39
38
37
36
35
34
33
32
31
30
29
28
27
Figure 1.4 shows PLQP0052JA-A Package Pin Assignments (Top View). Figure 1.5 shows PTLG0064JA-A
Package Pin Assignments.
Pin assignments (top view)
NC
40
26
NC
P0_6/AN1
41
25
P1_3/KI3/AN11
P0_5/AN2
42
24
P1_4/TXD0
P0_4/AN3
43
23
P1_5/RXD0/(TRAIO)/(INT1)(2)
P4_2/VREF
44
22
P1_6/CLK0
P6_0/TREO
45
21
P1_7/TRAIO/INT1
P6_2
46
20
P2_0/TRDIOA0/TRDCLK
R8C/24 Group
R8C/25 Group
12
13
VCC/AVCC
11
P4_6/XIN
P2_7/TRDIOD1
9
10
(1)
VSS/AVSS
P2_6/TRDIOC1
XOUT/P4_7
14
8
52
RESET
P3_7/SSO
7
P2_5/TRDIOB1
6
P2_4/TRDIOA1
15
P4_3/XCIN
16
51
P4_4/XCOUT
50
P0_0/AN7
5
P0_1/AN6
MODE
P2_3/TRDIOD0
4
17
P3_4/SDA/SCS
49
3
P0_2/AN5
2
P2_2/TRDIOC0
P3_3/SSI
P2_1/TRDIOB0
18
P3_5/SCL/SSCK
19
48
1
47
NC
P6_1
P0_3/AN4
Package: PLQP0052JA-A(52P6A-A)
0.65 mm pin pitch, 10 mm square body
NOTES:
1. P4_7 is an input-only port.
2. Can be assigned to the pin in parentheses by a program.
NC: Non-Connection
Figure 1.4
PLQP0052JA-A Package Pin Assignments (Top View)
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 9 of 51
R8C/24 Group, R8C/25 Group
1. Overview
Pin assignments (top perspective view)
8
7
A
B
C
D
E
F
G
H
3
50
48
46
45
NC
36
NC
P3_3/SSI
P0_1/AN6
P6_2
P6_0/TREO
4
51
49
NC
44
P3_4/SDA/
SCS
P0_0/AN7
P0_2/AN5
NC
5
52
47
43
42
MODE
P3_7/SSO
P6_1
P0_4/AN3
P0_5/AN2
NC
6
2
37
NC
P4_3/XCIN
P3_5/SCL/
SSCK
P6_3
NC
9
8
RESET
6
5
4
7
P4_4/XCOUT
13
12
P2_7/
TRDIOD1
VCC/AVCC
NC
10
16
VSS/AVSS
P2_4/
TRDIOA1
11
17
3
NC
2
1
P0_3/AN4
XIN/P4_6
14
15
P2_6/
TRDIOC1
P2_5/
TRDIOB1
A
B
19
35
NC
NC
38
P0_6/AN1
P0_7/AN0
32
31
NC
P1_0/KI0/
AN8
P1_1/KI1/
AN9
NC
NC
P1_5/RXD0/
P2_1/
TRDIOB0 (TRAIO)/(INT1)(2)
20
NC
21
P2_2/
P1_7/TRAIO/ P1_6/CLK0
TRDIOC0 INT1
D
30
P1_2/KI2/
AN10
24
P1_4/TXD0
22
33
P3_1/TRBO
41
23
P2_3/
P2_0/TRDIOA0/
TRDIOD0 TRDCLK
C
34
P4_2/VREF P3_0/TRAO P6_5/CLK1
XOUT/
P4_7(1)
18
P6_4
28
NC
P6_6/INT2/
TXD1
25
27
P1_3/KI3/
AN11
P4_5/INT0
P6_7/INT3/
RXD1
F
G
H
E
29
Package: PTLG0064JA-A(64F0G)
0.65 mm pin pitch, 6 mm square body
NOTES:
1. P4_7 is an input-only port.
2. Can be assigned to the pin in parentheses by a program.
3. In the figure, the numbers in circles are the pin numbers
of the 52-pin LQFP package (PLQP0052JA-A).
NC: Non-Connection
R5F21244S
NLG
JAPAN
Pin assignments (top view)
Figure 1.5
PTLG0064JA-A Package Pin Assignments
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 10 of 51
8
7
6
5
4
3
2
1
R8C/24 Group, R8C/25 Group
1.6
1. Overview
Pin Functions
Table 1.5 lists Pin Functions.
Table 1.5
Pin Functions
Type
Symbol
I/O Type
Description
Power supply input
VCC, VSS
I
Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
I
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
RESET
I
Input “L” on this pin resets the MCU.
MODE
MODE
I
Connect this pin to VCC via a resistor.
XIN clock input
XIN
I
XIN clock output
XOUT
O
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins. To use an external clock, input it to
the XIN pin and leave the XOUT pin open.
XCIN clock input
XCIN
I
XCIN clock output
XCOUT
O
INT interrupt input
INT0 to INT3
I
INT interrupt input pins.
INT0 is timer RD input pin. INT1 is timer RA input pin.
Key input interrupt
KI0 to KI3
I
Key input interrupt input pins
Timer RA
TRAIO
I/O
Timer RA I/O pin
TRAO
O
Timer RA output pin
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins. To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
Timer RB
TRBO
O
Timer RB output pin
Timer RD
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
I/O
Timer RD I/O ports
TRDCLK
I
External clock input pin
Timer RE
TREO
O
Divided clock output pin
CLK0, CLK1
I/O
Transfer clock I/O pin
RXD0, RXD1
I
Serial data input pins
Serial interface
I2C
bus interface
Clock synchronous
serial I/O with chip
select
TXD0, TXD1
O
Serial data output pins
SCL
I/O
Clock I/O pin
SDA
I/O
Data I/O pin
SSI
I/O
Data I/O pin
SCS
I/O
Chip-select signal I/O pin
SSCK
I/O
Clock I/O pin
SSO
I/O
Data I/O pin
Reference voltage
input
VREF
I
Reference voltage input pin to A/D converter
A/D converter
AN0 to AN11
I
Analog input pins to A/D converter
I/O port
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0, P3_1,
P3_3 to P3_5, P3_7,
P4_3 to P4_5,
P6_0 to P6_7
Input port
P4_2, P4_6, P4_7
I: Input
O: Output
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
I/O
I
I/O: Input and output
Page 11 of 51
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
P2_0 to P2_7 also function as LED drive ports.
Input-only ports
R8C/24 Group, R8C/25 Group
Table 1.6
Pin Name Information by Pin Number
Pin
Control Pin
Number
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
28
29
30
31
32
33
34
35
36
37
38
41
42
43
44
45
46
47
48
49
50
51
52
1. Overview
Port
Interrupt
P3_5
P3_3
P3_4
MODE
XCIN
XCOUT
RESET
XOUT
VSS/AVSS
XIN
VCC/AVCC
VREF
I/O Pin Functions for of Peripheral Modules
Clock
Serial
Synchronous I2C bus
Timer
Interface Serial I/O with Interface
Chip Select
SSCK
SCL
SSI
SCS
SDA
P4_3
P4_4
P4_7
P4_6
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P1_4
P1_3
P4_5
P6_6
P6_7
P1_2
P1_1
P1_0
P3_1
P3_0
P6_5
P6_4
P6_3
P0_7
P0_6
P0_5
P0_4
P4_2
P6_0
P6_2
P6_1
P0_3
P0_2
P0_1
P0_0
P3_7
INT1
TRDIOD1
TRDIOC1
TRDIOB1
TRDIOA1
TRDIOD0
TRDIOC0
TRDIOB0
TRDIOA0/TRDCLK
TRAIO
(INT1)(1)
(TRAIO)(1)
KI3
INT0
INT2
INT3
KI2
KI1
KI0
Page 12 of 51
CLK0
RXD0
TXD0
AN11
INT0
TXD1
RXD1
AN10
AN9
AN8
TRBO
TRAO
CLK1
AN0
AN1
AN2
AN3
TREO
NOTE:
1. Can be assigned to the pin in parentheses by a program.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
A/D
Converter
AN4
AN5
AN6
AN7
SSO
R8C/24 Group, R8C/25 Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
Data registers(1)
R2
R3
A0
A1
FB
b19
b15
Address registers(1)
Frame base register(1)
b0
Interrupt table register
INTBL
INTBH
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 13 of 51
R8C/24 Group, R8C/25 Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 14 of 51
R8C/24 Group, R8C/25 Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 15 of 51
R8C/24 Group, R8C/25 Group
3.
3. Memory
Memory
3.1
R8C/24 Group
Figure 3.1 is a Memory Map of R8C/24 Group. The R8C/24 group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal
ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2-Kbyte internal
RAM area is allocated addresses 00400h to 00BFFh. The internal RAM is used not only for storing data but also
for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
002FFh
SFR
(Refer to 4. Special
Function Registers
(SFRs))
00400h
Internal RAM
0XXXh
0FFDCh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer/oscillation stop detection/voltage monitor
0YYYYh
(Reserved)
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
1ZZZZh
0FFFFh
Internal ROM
(program ROM)
FFFFFh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Part Number
R5F21244SNFP, R5F21244SNXXXFP,
R5F21244SDFP, R5F21244SDXXXFP,
R5F21244SNLG, R5F21244SNXXXLG
R5F21245SNFP, R5F21245SNXXXFP,
R5F21245SDFP, R5F21245SDXXXFP
R5F21246SNFP, R5F21246SNXXXFP,
R5F21246SDFP, R5F21246SDXXXFP,
R5F21246SNLG, R5F21246SNXXXLG
R5F21247SNFP, R5F21247SNXXXFP,
R5F21247SDFP, R5F21247SDXXXFP
R5F21248SNFP, R5F21248SNXXXFP,
R5F21248SDFP, R5F21248SDXXXFP
Figure 3.1
Address 0YYYYh
Address 1ZZZZh
Size
Address 0XXXXh
16 Kbytes
0C000h
−
1 Kbyte
007FFh
24 Kbytes
0A000h
−
2 Kbytes
00BFFh
32 Kbytes
08000h
−
2 Kbytes
00BFFh
48 Kbytes
04000h
−
2.5 Kbytes
00DFFh
64 Kbytes
04000h
13FFFh
3 Kbytes
00FFFh
Memory Map of R8C/24 Group
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Internal RAM
Size
Page 16 of 51
R8C/24 Group, R8C/25 Group
3.2
3. Memory
R8C/25 Group
Figure 3.2 is a Memory Map of R8C/25 Group. The R8C/25 group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 2-Kbyte
internal RAM is allocated addresses 00400h to 00BFFh. The internal RAM is used not only for storing data but
also for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
002FFh
SFR
(Refer to 4. Special
Function Registers
(SFRs))
00400h
Internal RAM
0XXXXh
02400h
0FFDCh
Internal ROM
(data flash)(1)
Undefined instruction
Overflow
BRK instruction
Address match
Single step
02BFFh
Watchdog timer/oscillation stop detection/voltage monitor
0YYYYh
(Reserved)
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
1ZZZZh
0FFFFh
Internal ROM
(program ROM)
FFFFFh
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Part Number
R5F21254SNFP, R5F21254SNXXXFP,
R5F21254SDFP, R5F21254SDXXXFP,
R5F21254SNLG, R5F21254SNXXXLG
R5F21255SNFP, R5F21255SNXXXFP,
R5F21255SDFP, R5F21255SDXXXFP
R5F21256SNFP, R5F21256SNXXXFP,
R5F21256SDFP, R5F21256SDXXXFP,
R5F21256SNLG, R5F21256SNXXXLG
R5F21257SNFP, R5F21257SNXXXFP,
R5F21257SDFP, R5F21257SDXXXFP
R5F21258SNFP, R5F21258SNXXXFP,
R5F21258SDFP, R5F21258SDXXXFP
Figure 3.2
Size
Address 0YYYYh
Address 1ZZZZh
Size
Address 0XXXXh
16 Kbytes
0C000h
−
1 Kbyte
007FFh
24 Kbytes
0A000h
−
2 Kbytes
00BFFh
32 Kbytes
08000h
−
2 Kbytes
00BFFh
48 Kbytes
04000h
−
2.5 Kbytes
00DFFh
64 Kbytes
04000h
13FFFh
3 Kbytes
00FFFh
Memory Map of R8C/25 Group
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Internal RAM
Page 17 of 51
R8C/24 Group, R8C/25 Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special
function registers.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
SFR Information (1)(1)
Register
Symbol
After reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
PM0
PM1
CM0
CM1
00h
00h
01101000b
00100000b
Protect Register
PRCR
00h
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
OCD
WDTR
WDTS
WDC
RMAD0
Address Match Interrupt Enable Register
Address Match Interrupt Register 1
AIER
RMAD1
00000100b
XXh
XXh
00X11111b
00h
00h
00h
00h
00h
00h
00h
Count Source Protection Mode Register
CSPR
00h
10000000b(6)
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
FRA0
FRA1
FRA2
00h
When shipping
00h
Clock Prescaler Reset Flag
High-Speed On-Chip Oscillator Control Register 4
CPSRF
FRA4
00h
When shipping
High-Speed On-Chip Oscillator Control Register 6
High-Speed On-Chip Oscillator Control Register 7
FRA6
FRA7
When shipping
When shipping
0030h
0031h
0032h
Voltage Detection Register 1(2)
Voltage Detection Register 2(2)
VCA1
VCA2
00001000b
00h(3)
00100000b(4)
0033h
0034h
0035h
0036h
0037h
0038h
Voltage Monitor 1 Circuit Control Register(5)
Voltage Monitor 2 Circuit Control Register(5)
Voltage Monitor 0 Circuit Control Register(2)
VW1C
VW2C
VW0C
00001000b
00h
0000X000b(3)
0100X001b(4)
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
0039h
003Ah
003Eh
003Fh
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect this register.
3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.
4. Power-on reset, voltage monitor 0 reset or the LVD0ON bit in the OFS register is set to 0, and hardware reset.
5. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect b2 and b3.
6. The CSPROINI bit in the OFS register is set to 0.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 18 of 51
R8C/24 Group, R8C/25 Group
Table 4.2
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
4. Special Function Registers (SFRs)
SFR Information (2)(1)
Register
Symbol
After reset
Timer RD0 Interrupt Control Register
Timer RD1 Interrupt Control Register
Timer RE Interrupt Control Register
TRD0IC
TRD1IC
TREIC
XXXXX000b
XXXXX000b
XXXXX000b
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
SSU/IIC Interrupt Control Register(2)
KUPIC
ADIC
SSUIC / IICIC
XXXXX000b
XXXXX000b
XXXXX000b
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
INT2 Interrupt Control Register
Timer RA Interrupt Control Register
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TRAIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
INT0 Interrupt Control Register
INT0IC
XX00X000b
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 19 of 51
R8C/24 Group, R8C/25 Group
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
4. Special Function Registers (SFRs)
SFR Information (3)(1)
Register
Symbol
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
SS Control Register H / IIC bus Control Register 1(2)
SS Control Register L / IIC bus Control Register 2(2)
SS Mode Register / IIC bus Mode Register(2)
SS Enable Register / IIC bus Interrupt Enable Register(2)
SS Status Register / IIC bus Status Register(2)
SS Mode Register 2 / Slave Address Register(2)
SS Transmit Data Register / IIC bus Transmit Data Register(2)
SS Receive Data Register / IIC bus Receive Data Register(2)
SSCRH / ICCR1
SSCRL / ICCR2
SSMR / ICMR
SSER / ICIER
SSSR / ICSR
SSMR2 / SAR
SSTDR / ICDRT
SSRDR / ICDRR
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 20 of 51
After reset
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
01111101b
00011000b
00h
00h / 0000X000b
00h
FFh
FFh
R8C/24 Group, R8C/25 Group
Table 4.4
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
4. Special Function Registers (SFRs)
SFR Information (4)(1)
Register
Symbol
After reset
A/D Register
AD
XXh
XXh
A/D Control Register 2
ADCON2
00h
A/D Control Register 0
A/D Control Register 1
ADCON0
ADCON1
00h
00h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
Port P4 Direction Register
PD4
00h
Port P6 Register
P6
XXh
Port P6 Direction Register
PD6
00h
Port P2 Drive Capacity Control Register
UART1 Function Select Register
P2DRR
U1SR
00h
XXh
Port Mode Register
External Input Enable Register
INT Input Filter Select Register
Key Input Enable Register
Pull-Up Control Register 0
Pull-Up Control Register 1
PMR
INTEN
INTF
KIEN
PUR0
PUR1
00h
00h
00h
00h
00h
XX00XX00b
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 21 of 51
R8C/24 Group, R8C/25 Group
Table 4.5
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
4. Special Function Registers (SFRs)
SFR Information (5)(1)
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
00h
00h
00h
FFh
FFh
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
Timer RE Second Data Register / Counter Data Register
Timer RE Minute Data Register / Compare Data Register
Timer RE Hour Data Register
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Count Source Select Register
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
00h
00h
00h
00h
00h
00h
00001000b
Timer RD Start Register
Timer RD Mode Register
Timer RD PWM Mode Register
Timer RD Function Control Register
Timer RD Output Master Enable Register 1
Timer RD Output Master Enable Register 2
Timer RD Output Control Register
Timer RD Digital Filter Function Select Register 0
Timer RD Digital Filter Function Select Register 1
TRDSTR
TRDMR
TRDPMR
TRDFCR
TRDOER1
TRDOER2
TRDOCR
TRDDF0
TRDDF1
11111100b
00001110b
10001000b
10000000b
FFh
01111111b
00h
00h
00h
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 22 of 51
After reset
R8C/24 Group, R8C/25 Group
Table 4.6
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
4. Special Function Registers (SFRs)
SFR Information (6)(1)
Register
Timer RD Control Register 0
Timer RD I/O Control Register A0
Timer RD I/O Control Register C0
Timer RD Status Register 0
Timer RD Interrupt Enable Register 0
Timer RD PWM Mode Output Level Control Register 0
Timer RD Counter 0
Symbol
TRDCR0
TRDIORA0
TRDIORC0
TRDSR0
TRDIER0
TRDPOCR0
TRD0
Timer RD General Register A0
TRDGRA0
Timer RD General Register B0
TRDGRB0
Timer RD General Register C0
TRDGRC0
Timer RD General Register D0
TRDGRD0
Timer RD Control Register 1
Timer RD I/O Control Register A1
Timer RD I/O Control Register C1
Timer RD Status Register 1
Timer RD Interrupt Enable Register 1
Timer RD PWM Mode Output Level Control Register 1
Timer RD Counter 1
TRDCR1
TRDIORA1
TRDIORC1
TRDSR1
TRDIER1
TRDPOCR1
TRD1
Timer RD General Register A1
TRDGRA1
Timer RD General Register B1
TRDGRB1
Timer RD General Register C1
TRDGRC1
Timer RD General Register D1
TRDGRD1
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 23 of 51
After reset
00h
10001000b
10001000b
11100000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
10001000b
10001000b
11000000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
R8C/24 Group, R8C/25 Group
Table 4.7
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
FFFFh
4. Special Function Registers (SFRs)
SFR Information (7)(1)
Register
Symbol
After reset
Flash Memory Control Register 4
FMR4
01000000b
Flash Memory Control Register 1
FMR1
1000000Xb
Flash Memory Control Register 0
FMR0
00000001b
Option Function Select Register
OFS
(Note 2)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 24 of 51
R8C/24 Group, R8C/25 Group
5.
5. Electrical Characteristics
Electrical Characteristics
The electrical characteristics of N version (Topr = -20 to 85°C) and D version (Topr = -40 to 85°C) are listed
below.
Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr = -20 to
105°C).
Table 5.1
Absolute Maximum Ratings
Symbol
Parameter
Rated Value
Unit
-0.3 to 6.5
V
Input voltage
-0.3 to VCC + 0.3
V
VO
Output voltage
-0.3 to VCC + 0.3
V
Pd
Power dissipation
500(1)
mW
Topr
Operating ambient temperature
-20 to 85 (N version) /
-40 to 85 (D version)
°C
Tstg
Storage temperature
-65 to 150
°C
VCC/AVCC
Supply voltage
VI
NOTE:
1. 300 mW for the PTLG0064JA-A package.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 25 of 51
Condition
Topr = 25°C
R8C/24 Group, R8C/25 Group
Table 5.2
5. Electrical Characteristics
Recommended Operating Conditions
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
VCC/AVCC
Supply voltage
2.2
−
5.5
V
VSS/AVSS
Supply voltage
−
0
−
V
VIH
Input “H” voltage
0.8 VCC
−
VCC
V
VIL
Input “L” voltage
0
−
0.2 VCC
V
IOH(sum)
Peak sum output
“H” current
Sum of all pins IOH(peak)
−
−
-160
mA
IOH(sum)
Average sum
output “H” current
Sum of all pins IOH(avg)
−
−
-80
mA
IOH(peak)
Peak output “H”
current
Except P2_0 to P2_7
−
−
-10
mA
P2_0 to P2_7
−
−
-40
mA
Average output
“H” current
Except P2_0 to P2_7
−
−
-5
mA
P2_0 to P2_7
−
−
-20
mA
IOL(sum)
Peak sum output
“L” current
Sum of all pins IOL(peak)
−
−
160
mA
IOL(sum)
Average sum
output “L” current
Sum of all pins IOL(avg)
−
−
80
mA
IOL(peak)
Peak output “L”
current
Except P2_0 to P2_7
−
−
10
mA
P2_0 to P2_7
−
−
40
mA
IOL(avg)
Average output
“L” current
Except P2_0 to P2_7
−
−
5
mA
f(XIN)
XIN clock input oscillation frequency
IOH(avg)
−
−
20
mA
3.0 V ≤ VCC ≤ 5.5 V
0
−
20
MHz
P2_0 to P2_7
2.7 V ≤ VCC < 3.0 V
0
−
10
MHz
2.2 V ≤ VCC < 2.7 V
0
−
5
MHz
f(XCIN)
XCIN clock input oscillation frequency
2.2 V ≤ VCC ≤ 5.5 V
0
−
70
kHz
−
System clock
3.0 V ≤ VCC ≤ 5.5 V
0
−
20
MHz
2.7 V ≤ VCC < 3.0 V
0
−
10
MHz
2.2 V ≤ VCC < 2.7 V
0
−
5
MHz
FRA01 = 0
Low-speed on-chip
oscillator clock selected
−
125
−
kHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
3.0 V ≤ VCC ≤ 5.5 V
−
−
20
MHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.7 V ≤ VCC ≤ 5.5 V
−
−
10
MHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.2 V ≤ VCC ≤ 5.5 V
−
−
5
MHz
OCD2 = 0
XlN clock selected
OCD2 = 1
On-chip oscillator clock
selected
NOTES:
1. VCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 26 of 51
R8C/24 Group, R8C/25 Group
Table 5.3
5. Electrical Characteristics
A/D Converter Characteristics
Symbol
Parameter
−
Resolution
−
Absolute
accuracy
Conditions
Standard
Min.
Typ.
Max.
Unit
Vref = AVCC
−
−
10
Bit
10-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
−
−
±3
LSB
8-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
−
−
±2
LSB
10-bit mode
φAD = 10 MHz, Vref = AVCC = 3.3 V
−
−
±5
LSB
8-bit mode
φAD = 10 MHz, Vref = AVCC = 3.3 V
−
−
±2
LSB
10-bit mode
φAD = 5 MHz, Vref = AVCC = 2.2 V
−
−
±5
LSB
8-bit mode
φAD = 5 MHz, Vref = AVCC = 2.2 V
−
−
±2
LSB
Rladder
Resistor ladder
Vref = AVCC
10
−
40
kΩ
tconv
Conversion time 10-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
3.3
−
−
µs
φAD = 10 MHz, Vref = AVCC = 5.0 V
2.8
−
−
µs
2.2
−
AVCC
V
0
−
AVCC
V
0.25
−
10
MHz
8-bit mode
Vref
Reference voltage
VIA
Analog input voltage(2)
−
A/D operating
clock frequency
Without sample and hold
Vref = AVCC = 2.7 to 5.5 V
With sample and hold
Vref = AVCC = 2.7 to 5.5 V
1
−
10
MHz
Without sample and hold
Vref = AVCC = 2.2 to 5.5 V
0.25
−
5
MHz
With sample and hold
Vref = AVCC = 2.2 to 5.5 V
1
−
5
MHz
NOTES:
1. AVCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
P0
P1
P2
P3
P4
P6
Figure 5.1
30pF
Ports P0 to P4, P6 Timing Measurement Circuit
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 27 of 51
R8C/24 Group, R8C/25 Group
Table 5.4
Flash Memory (Program ROM) Electrical Characteristics
Symbol
−
5. Electrical Characteristics
Parameter
Program/erase endurance(2)
Conditions
Standard
Unit
Min.
Typ.
Max.
R8C/24 Group
100(3)
−
−
times
R8C/25 Group
1,000(3)
−
−
times
µs
−
Byte program time
−
50
400
−
Block erase time
−
0.4
9
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
97+CPU clock
× 6 cycles
µs
−
Interval from erase start/restart until
following suspend request
650
−
−
µs
−
Interval from program start/restart until
following suspend request
0
−
−
ns
−
Time from suspend until program/erase
restart
−
−
3+CPU clock
× 4 cycles
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
2.2
−
5.5
V
−
Program, erase temperature
0
−
60
°C
−
Data hold time(7)
20
−
−
year
Ambient temperature = 55°C
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 28 of 51
R8C/24 Group, R8C/25 Group
Table 5.5
5. Electrical Characteristics
Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
10,000(3)
−
−
times
Byte program time
(program/erase endurance ≤ 1,000 times)
−
50
400
µs
−
Byte program time
(program/erase endurance > 1,000 times)
−
65
−
µs
−
Block erase time
(program/erase endurance ≤ 1,000 times)
−
0.2
9
s
−
Block erase time
(program/erase endurance > 1,000 times)
−
0.3
−
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
97+CPU clock
× 6 cycles
µs
−
Interval from erase start/restart until
following suspend request
650
−
−
µs
−
Interval from program start/restart until
following suspend request
0
−
−
ns
−
Time from suspend until program/erase
restart
−
−
3+CPU clock
× 4 cycles
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
2.2
−
5.5
V
−
Program, erase temperature
-20(8)
−
85
°C
−
Data hold time(9)
20
−
−
year
−
Program/erase endurance(2)
−
Ambient temperature = 55 °C
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. -40°C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 29 of 51
R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Suspend request
(maskable interrupt request)
FMR46
Clock-dependent
time
Fixed time
Access restart
td(SR-SUS)
Figure 5.2
Table 5.6
Time delay until Suspend
Voltage Detection 0 Circuit Electrical Characteristics
Symbol
Parameter
Condition
Vdet0
Voltage detection level
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(2)
Vccmin
MCU operating voltage minimum value
VCA25 = 1, VCC = 5.0 V
Standard
Unit
Min.
Typ.
Max.
2.2
2.3
2.4
V
−
0.9
−
µA
−
−
300
µs
2.2
−
−
V
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
Table 5.7
Voltage Detection 1 Circuit Electrical Characteristics
Symbol
Vdet1
−
Parameter
Condition
Voltage detection level
Voltage monitor 1 interrupt request generation
time(2)
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(3)
VCA26 = 1, VCC = 5.0 V
Standard
Unit
Min.
Typ.
Max.
2.70
2.85
3.00
V
−
40
−
µs
−
0.6
−
µA
−
−
100
µs
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
Table 5.8
Voltage Detection 2 Circuit Electrical Characteristics
Symbol
Parameter
Vdet2
Voltage detection level
−
Voltage monitor 2 interrupt request generation time(2)
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(3)
Condition
VCA27 = 1, VCC = 5.0 V
Standard
Unit
Min.
Typ.
Max.
3.3
3.6
3.9
V
−
40
−
µs
−
0.6
−
µA
−
−
100
µs
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 30 of 51
R8C/24 Group, R8C/25 Group
Table 5.9
5. Electrical Characteristics
Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Unit
Max.
Vpor1
Power-on reset valid voltage(4)
−
−
0.1
V
Vpor2
Power-on reset or voltage monitor 0 reset valid
voltage
0
−
Vdet0
V
trth
External power VCC rise gradient(2)
20
−
−
mV/msec
NOTES:
1. The measurement condition is Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if -40°C ≤ Topr < -20°C.
Vdet0(3)
Vdet0(3)
2.2 V
trth
trth
External
Power VCC
Vpor2
Vpor1
Sampling time(1, 2)
tw(por1)
Internal
reset signal
(“L” valid)
1
× 32
fOCO-S
1
× 32
fOCO-S
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit of Hardware Manual for details.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 31 of 51
R8C/24 Group, R8C/25 Group
Table 5.10
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
fOCO40M
5. Electrical Characteristics
Parameter
High-speed on-chip oscillator frequency
temperature • supply voltage dependence
High-speed on-chip oscillator frequency when
correction value in FRA7 register is written to
FRA1 register(4)
−
Value in FRA1 register after reset
−
Oscillation frequency adjustment unit of highspeed on-chip oscillator
−
Oscillation stability time
−
Self power consumption at oscillation
Condition
Standard
Unit
Min.
Typ.
Max.
VCC = 4.75 to 5.25 V
0°C ≤ Topr ≤ 60°C(2)
39.2
40
40.8
MHz
VCC = 4.5 to 5.5 V
-20°C ≤ Topr ≤ 85°C
38.8
40
40.8
MHz
VCC = 4.5 to 5.5 V
-40°C ≤ Topr ≤ 85°C
38.4
40
40.8
MHz
VCC = 3.0 to 5.5 V
-20°C ≤ Topr ≤ 85°C(2)
38.8
40
41.2
MHz
VCC = 3.0 to 5.5 V
-40°C ≤ Topr ≤ 85°C(2)
38.4
40
41.6
MHz
VCC = 2.7 to 5.5 V
-20°C ≤ Topr ≤ 85°C(2)
38
40
42
MHz
VCC = 2.7 to 5.5 V
-40°C ≤ Topr ≤ 85°C(2)
37.6
40
42.4
MHz
VCC = 2.2 to 5.5 V
-20°C ≤ Topr ≤ 85°C(3)
35.2
40
44.8
MHz
VCC = 2.2 to 5.5 V
-40°C ≤ Topr ≤ 85°C(3)
34
40
46
MHz
−
36.864
-3%
−
3%
VCC = 5.0 V, Topr = 25°C
VCC = 3.0 to 5.5 V
-20°C ≤ Topr ≤ 85°C
MHz
%
08h
−
F7h
−
Adjust FRA1 register
(value after reset) to -1
−
+0.3
−
MHz
−
10
100
µs
VCC = 5.0 V, Topr = 25°C
−
400
−
µA
NOTES:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. Standard values when the FRA1 register value after reset is assumed.
3. Standard values when the corrected value of the FRA6 register has been written to the FRA1 register.
4. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Table 5.11
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
fOCO-S
Low-speed on-chip oscillator frequency
30
125
250
−
Oscillation stability time
−
10
100
µs
−
Self power consumption at oscillation
−
15
−
µA
VCC = 5.0 V, Topr = 25°C
kHz
NOTE:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
Table 5.12
Power Supply Circuit Timing Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
td(P-R)
Time for internal power supply stabilization during
power-on(2)
1
−
2000
µs
td(R-S)
STOP exit time(3)
−
−
150
µs
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 32 of 51
R8C/24 Group, R8C/25 Group
Table 5.13
5. Electrical Characteristics
Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Unit
Max.
tSUCYC
SSCK clock cycle time
4
−
−
tCYC(2)
tHI
SSCK clock “H” width
0.4
−
0.6
tSUCYC
tLO
SSCK clock “L” width
0.4
−
0.6
tSUCYC
tRISE
SSCK clock rising
time
Master
−
−
1
tCYC(2)
Slave
−
−
1
µs
tFALL
SSCK clock falling
time
Master
−
−
1
tCYC(2)
−
−
1
µs
tSU
SSO, SSI data input setup time
100
−
−
ns
tH
SSO, SSI data input hold time
1
−
−
tCYC(2)
tLEAD
Slave
SCS setup time
Slave
1tCYC + 50
−
−
ns
tLAG
SCS hold time
Slave
1tCYC + 50
−
−
ns
tOD
SSO, SSI data output delay time
tSA
SSI slave access time
tOR
SSI slave out open time
−
−
1
tCYC(2)
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
2.2 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
2.2 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 33 of 51
R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIH or VOH
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIH or VOH
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 34 of 51
R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIH or VOH
tHI
tLEAD
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 35 of 51
R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIH or VOH
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
Figure 5.6
tH
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous
Communication Mode)
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 36 of 51
R8C/24 Group, R8C/25 Group
Table 5.14
5. Electrical Characteristics
Timing Requirements of I2C bus Interface(1)
tSCL
SCL input cycle time
tSCLH
SCL input “H” width
Standard
Typ.
−
12tCYC + 600(2)
−
3tCYC + 300(2)
tSCLL
SCL input “L” width
500(2)
tsf
tSP
SCL, SDA input fall time
SCL, SDA input spike pulse rejection time
tBUF
SDA input bus-free time
5tCYC(2)
−
1tCYC(2)
−
tSTAH
Start condition input hold time
3tCYC(2)
−
−
ns
tSTAS
Retransmit start condition input setup time
3tCYC(2)
−
−
ns
tSTOP
Stop condition input setup time
3tCYC(2)
−
−
ns
tSDAS
Data input setup time
−
−
ns
tSDAH
Data input hold time
1tCYC + 20(2)
0
−
−
ns
Symbol
Parameter
Condition
Min.
5tCYC +
−
−
Unit
Max.
−
ns
−
ns
−
ns
−
300
−
ns
ns
−
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOP
SCL
P(2)
S(1)
tsf
Sr(3)
tSCLL
tsr
tSCL
NOTES:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 5.7
I/O Timing of I2C bus Interface
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 37 of 51
P(2)
tSDAS
tSDAH
ns
R8C/24 Group, R8C/25 Group
Table 5.15
Electrical Characteristics (1) [VCC = 5 V]
Symbol
VOH
Parameter
Output “H” voltage
Except P2_0 to P2_7,
XOUT
P2_0 to P2_7
XOUT
VOL
Output “L” voltage
Except P2_0 to P2_7,
XOUT
P2_0 to P2_7
XOUT
VT+-VT-
5. Electrical Characteristics
Hysteresis
Condition
IOH = -5 mA
IOH = -200 µA
Drive capacity HIGH
Drive capacity LOW
Drive capacity HIGH
Drive capacity LOW
IOL = 5 mA
IOL = 200 µA
Drive capacity HIGH
Drive capacity LOW
Drive capacity HIGH
Drive capacity LOW
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, RXD0,
RXD1, CLK0, CLK1,
SSI, SCL, SDA, SSO
RfXCIN
VRAM
Input “H” current
Input “L” current
Pull-up resistance
Feedback
resistance
Feedback
resistance
RAM hold voltage
IOL = 20 mA
IOL = 5 mA
IOL = 1 mA
IOL = 500 µA
Max.
VCC
VCC
VCC
VCC
VCC
VCC
2.0
0.45
2.0
2.0
2.0
2.0
−
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
0.1
1.0
−
V
−
−
−
XIN
30
−
50
1.0
5.0
-5.0
167
−
µA
−
µA
kΩ
MΩ
XCIN
−
18
−
MΩ
1.8
−
−
V
RESET
IIH
IIL
RPULLUP
RfXIN
IOH = -20 mA
IOH = -5 mA
IOH = -1 mA
IOH = -500 µA
Standard
Min.
Typ.
VCC − 2.0
−
VCC − 0.5
−
VCC − 2.0
−
VCC − 2.0
−
VCC − 2.0
−
VCC − 2.0
−
−
−
−
−
−
−
−
−
−
−
−
−
0.1
0.5
VI = 5 V, Vcc = 5V
VI = 0 V, Vcc = 5V
VI = 0 V, Vcc = 5V
During stop mode
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 38 of 51
R8C/24 Group, R8C/25 Group
Table 5.16
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (2) [Vcc = 5 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply
High-speed
current
clock mode
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are
open, other pins
are VSS
High-speed
on-chip
oscillator mode
Low-speed
on-chip
oscillator mode
Low-speed
clock mode
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 39 of 51
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
Min.
−
Standard
Typ.
Max.
10
17
Unit
mA
−
9
15
mA
−
6
−
mA
−
5
−
mA
−
4
−
mA
−
2.5
−
mA
−
10
15
mA
−
4
−
mA
−
5.5
10
mA
−
2.5
−
mA
−
130
300
µA
−
130
300
µA
−
30
−
µA
R8C/24 Group, R8C/25 Group
Table 5.17
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (3) [Vcc = 5 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply
Wait mode
current
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are
open, other pins
are VSS
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Increase during Without sample & hold
A/D converter
With sample & hold
operation
Stop mode
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Page 40 of 51
Min.
−
Standard
Typ.
Max.
25
75
Unit
µA
−
23
60
µA
−
4.0
−
µA
−
2.2
−
µA
−
2.6
1.6
−
−
−
mA
mA
−
0.8
3.0
µA
−
1.2
−
µA
R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Table 5.18
XIN Input, XCIN Input
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
50
−
25
−
25
−
14
−
7
−
7
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
tC(XIN)
Unit
ns
ns
ns
µs
µs
µs
VCC = 5 V
tWH(XIN)
XIN input
tWL(XIN)
tC(XCIN)
tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 5.8
Table 5.19
XIN Input and XCIN Input Timing Diagram when VCC = 5 V
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
100
−
40
−
40
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.9
TRAIO Input Timing Diagram when VCC = 5 V
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 41 of 51
Unit
ns
ns
ns
VCC = 5 V
R8C/24 Group, R8C/25 Group
Table 5.20
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
200
−
100
−
100
−
−
50
0
−
50
−
90
−
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 or 1
VCC = 5 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 or 1
Figure 5.10
Table 5.21
Serial Interface Timing Diagram when VCC = 5 V
External Interrupt INTi (i = 0 to 3) Input
INT0 input “H” width
Standard
Min.
Max.
−
250(1)
INT0 input “L” width
250(2)
Symbol
tW(INH)
tW(INL)
Parameter
−
Unit
ns
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 5.11
External Interrupt INTi Input Timing Diagram when VCC = 5 V
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 42 of 51
R8C/24 Group, R8C/25 Group
Table 5.22
Electrical Characteristics (3) [VCC = 3 V]
Symbol
VOH
5. Electrical Characteristics
Parameter
Output “H” voltage
Except P2_0 to P2_7,
XOUT
P2_0 to P2_7
Output “L” voltage
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
Input “H” current
Input “L” current
Pull-up resistance
Feedback resistance
Feedback resistance
RAM hold voltage
Max.
VCC
Unit
V
VCC - 0.5
−
VCC
V
IOH = -1 mA
VCC - 0.5
−
VCC
V
IOH = -0.1 mA
VCC - 0.5
−
VCC
V
IOH = -50 µA
VCC - 0.5
−
VCC
V
−
−
0.5
V
Drive capacity
HIGH
Drive capacity
LOW
Drive capacity
HIGH
Drive capacity
LOW
IOL = 5 mA
−
−
0.5
V
IOL = 1 mA
−
−
0.5
V
IOL = 0.1 mA
−
−
0.5
V
IOL = 50 µA
−
−
0.5
V
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, RXD0,
RXD1, CLK0, CLK1,
SSI, SCL, SDA, SSO
0.1
0.3
−
V
RESET
0.1
0.4
−
V
−
−
−
66
−
−
1.8
160
3.0
18
−
4.0
-4.0
500
−
−
−
µA
−
Except P2_0 to P2_7,
XOUT
P2_0 to P2_7
Hysteresis
Standard
Typ.
−
IOH = -5 mA
XOUT
VT+-VT-
IOH = -1 mA
Min.
VCC - 0.5
Drive capacity
HIGH
Drive capacity
LOW
Drive capacity
HIGH
Drive capacity
LOW
IOL = 1 mA
XOUT
VOL
Condition
VI = 3 V, Vcc = 3V
VI = 0 V, Vcc = 3V
VI = 0 V, Vcc = 3V
XIN
XCIN
During stop mode
µA
kΩ
MΩ
MΩ
V
NOTE:
1. VCC =2.7 to 3.3 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 43 of 51
R8C/24 Group, R8C/25 Group
Table 5.23
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (4) [Vcc = 3 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 2.7 to 3.3 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed onchip oscillator
mode
Low-speed onchip oscillator
mode
Low-speed
clock mode
Wait mode
Increase during
A/D converter
operation
Stop mode
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 44 of 51
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Without sample & hold
With sample & hold
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Min.
−
Standard
Typ. Max.
6
−
Unit
mA
−
2
−
mA
−
5
9
mA
−
2
−
mA
−
130
300
µA
−
130
300
µA
−
30
−
µA
−
25
70
µA
−
23
55
µA
−
3.8
−
µA
−
2.0
−
µA
−
−
0.9
0.5
−
−
mA
mA
−
0.7
3.0
µA
−
1.1
−
µA
R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
XIN Input, XCIN Input
Table 5.24
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
100
−
40
−
40
−
14
−
7
−
7
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
tC(XIN)
Unit
ns
ns
ns
µs
µs
µs
VCC = 3 V
tWH(XIN)
XIN input
tWL(XIN)
tC(XCIN)
tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 5.12
XIN Input and XCIN Input Timing Diagram when VCC = 3 V
Table 5.25
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
300
−
120
−
120
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.13
TRAIO Input Timing Diagram when VCC = 3 V
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 45 of 51
Unit
ns
ns
ns
VCC = 3 V
R8C/24 Group, R8C/25 Group
Table 5.26
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
300
−
150
−
150
−
−
80
0
−
70
−
90
−
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi Input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 or 1
VCC = 3 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 or 1
Figure 5.14
Table 5.27
Serial Interface Timing Diagram when VCC = 3 V
External Interrupt INTi (i = 0 to 3) Input
INT0 input “H” width
Standard
Min.
Max.
−
380(1)
INT0 input “L” width
380(2)
Symbol
tW(INH)
tW(INL)
Parameter
Unit
−
ns
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 5.15
External Interrupt INTi Input Timing Diagram when VCC = 3 V
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 46 of 51
R8C/24 Group, R8C/25 Group
Table 5.28
Electrical Characteristics (5) [VCC = 2.2 V]
Symbol
VOH
5. Electrical Characteristics
Parameter
Output “H” voltage
Except P2_0 to P2_7,
XOUT
P2_0 to P2_7
Output “L” voltage
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
Input “H” current
Input “L” current
Pull-up resistance
Feedback resistance
Feedback resistance
RAM hold voltage
Max.
VCC
V
−
VCC
V
IOH = -1 mA
VCC - 0.5
−
VCC
V
IOH = -0.1 mA
VCC - 0.5
−
VCC
V
IOH = -50 µA
VCC - 0.5
−
VCC
V
−
−
0.5
V
Drive capacity
HIGH
Drive capacity
LOW
Drive capacity
HIGH
Drive capacity
LOW
IOL = 2 mA
−
−
0.5
V
IOL = 1 mA
−
−
0.5
V
IOL = 0.1 mA
−
−
0.5
V
IOL = 50 µA
−
−
0.5
V
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, RXD0,
RXD1, CLK0, CLK1,
SSI, SCL, SDA, SSO
0.05
0.3
−
V
RESET
0.05
0.15
−
V
−
−
−
100
−
−
1.8
200
5
35
−
4.0
-4.0
600
−
−
−
µA
−
VI = 2.2 V
VI = 0 V
VI = 0 V
XIN
XCIN
During stop mode
NOTE:
1. VCC = 2.2 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Unit
VCC - 0.5
Except P2_0 to P2_7,
XOUT
P2_0 to P2_7
Hysteresis
Standard
Typ.
−
IOH = -2 mA
XOUT
VT+-VT-
IOH = -1 mA
Min.
VCC - 0.5
Drive capacity
HIGH
Drive capacity
LOW
Drive capacity
HIGH
Drive capacity
LOW
IOL = 1 mA
XOUT
VOL
Condition
Page 47 of 51
µA
kΩ
MΩ
MΩ
V
R8C/24 Group, R8C/25 Group
Table 5.29
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (6) [Vcc = 2.2 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed clock
(VCC = 2.2 to 2.7 V)
mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed onchip oscillator
mode
Low-speed onchip oscillator
mode
Low-speed clock
mode
Wait mode
Increase during
A/D converter
operation
Stop mode
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 48 of 51
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Without sample & hold
With sample & hold
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Min.
−
Standard
Typ. Max.
3.5
−
Unit
mA
−
1.5
−
mA
−
3.5
−
mA
−
1.5
−
mA
−
100
230
µA
−
100
230
µA
−
25
−
µA
−
22
60
µA
−
20
55
µA
−
3.0
−
µA
−
1.8
−
µA
−
−
0.4
0.3
−
−
mA
mA
−
0.7
3.0
µA
−
1.1
−
µA
R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]
XIN Input, XCIN Input
Table 5.30
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
200
−
90
−
90
−
14
−
7
−
7
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
tC(XIN)
Unit
ns
ns
ns
µs
µs
µs
VCC = 2.2 V
tWH(XIN)
XIN input
tWL(XIN)
tC(XCIN)
tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 5.16
XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V
Table 5.31
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
500
−
200
−
200
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.17
TRAIO Input Timing Diagram when VCC = 2.2 V
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 49 of 51
Unit
ns
ns
ns
VCC = 2.2 V
R8C/24 Group, R8C/25 Group
Table 5.32
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
800
−
400
−
400
−
−
200
0
−
150
−
90
−
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 or 1
VCC = 2.2 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 or 1
Figure 5.18
Table 5.33
Serial Interface Timing Diagram when VCC = 2.2 V
External Interrupt INTi (i = 0 to 3) Input
tW(INH)
INT0 input “H” width
Standard
Min.
Max.
(1)
−
1000
tW(INL)
INT0 input “L” width
1000(2)
Symbol
Parameter
−
Unit
ns
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 5.19
External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 50 of 51
R8C/24 Group, R8C/25 Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
JEITA Package Code
P-LQFP52-10x10-0.65
RENESAS Code
PLQP0052JA-A
Previous Code
52P6A-A
MASS[Typ.]
0.3g
Under development
HD
*1
D
39
27
40
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
26
bp
c1
c
E
*2
HE
b1
Reference
Symbol
14
1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
Terminal cross section
ZE
52
13
ZD
Index mark
A
A1
A2
c
F
*3
y
e
L
bp
e
x
y
ZD
ZE
L
L1
Detail F
JEITA Package Code
P-TFLGA64-6x6-0.65
RENESAS Code
PTLG0064JA-A
Previous Code
64F0G
w S B
Nom
10.0
10.0
1.4
11.8 12.0
11.8 12.0
0.05
0.27
0.09
0.35
Max
10.1
10.1
12.2
12.2
1.7
0.1 0.15
0.32 0.37
0.30
0.145 0.20
0.125
8°
0.65
0.13
0.10
1.1
1.1
0.5 0.65
1.0
MASS[Typ.]
0.07g
b1
S
AB
b
D
Min
9.9
9.9
0°
L1
x
Dimension in Millimeters
S
w S A
AB
e
A
e
H
G
F
E
E
D
C
B
A
y S
x4
v
Index mark
(Laser mark)
Rev.3.00 Feb 29, 2008
REJ03B0117-0300
Page 51 of 51
1
2
3
Index mark
4
5
6
7
8
Reference
Symbol
D
E
v
w
A
e
b
b1
x
y
Dimension in Millimeters
Min
Nom Max
6.0
6.0
0.15
0.20
1.05
0.65
0.31 0.35 0.39
0.39 0.43 0.47
0.08
0.10
REVISION HISTORY
REVISION HISTORY
Rev.
Date
0.01
Sep 17, 2004
0.02
Dec 10, 2004
R8C/24 Group, R8C/25 Group Datasheet
R8C/24 Group, R8C/25 Group Datasheet
Description
Page
-
Summary
First Edition issued
All pages Part Number revised. R8C/26 → R8C/24, R8C/27 → R8C/25
2, 3
4
5, 6
Table 1.1 R8C/24 Group Performance, Table 1.2 R8C/25 Group
Performance
- Serial Interface: I2C Bus Interface and Chip-select clock synchronous
(SSU) added.
- LIN Module added.
- Interrupt: Internal factors revised; 10 → 11
- Note on Operating Ambient Temperature added.
Figure 1.1 Block Diagram
- LIN Module added.
- Chip-select clock synchronous (SSU) is added to I2C Bus Interface.
Table 1.3 Product Information of R8C/24 Group, Table 1.4 Product
Information of R8C/25 Group
Date and Development state revised.
7
Figure 1.4 Pin Assignment
P3_5/SCL → P3_5/SCL/SSCK, P3_3 → P3_3/SSI,
P3_4/SDA → P3_4/SDA/SCS, P3_7 → P3_7/SSO, VSS/AVSS → VSS,
XIN/P4_6 → P4_6/XIN, VCC/AVSS → VCC
12pin P1_7/TRAIO/INT1 to 22pin P1_0/KI0/AN8
→ 20pin P1_7/TRAIO/INT1 to 30pin P1_0/KI0/AN8
8
Table 1.5 Pin Description
- Analog Power Supply Input eliminated.
- SSU added.
9
Table 1.6 Pin Name Information by Pin Number added.
15
Table 4.1 SFR Information (1)
- 0031h: Voltage Detection Register 1 → Voltage Detection A Register 1
- 0032h: Voltage Detection Register 1 → Voltage Detection A Register 2
01000001b → 00100001b (Note 4)
- 0036h: “(3), 01000001b (4)” eliminated.
- 0038h: Voltage Monitor 0 Control Register (2), VW0C,
00001000b (3), 01000001b (4) added.
16
Table 4.2 SFR Information (2)
- 0048h: Timer RD0 Interrupt Control Register, RD0IC, XXXXX000b added.
- 0049h: Timer RD Interrupt Control Register, RDIC
→ Timer RD1 Interrupt Control Register, RD1IC
- 004Fh: IIC Interrupt Control Register, IIC
→ IIC/SSU Interrupt Control Register, IIC2IC
19
Table 4.5 SFR Information (3)
- 0106h: LIN Control Register, LINCR, 00h added.
-0107h: LIN Status Register, LINST, 00h added.
A-1
REVISION HISTORY
Rev.
Date
0.10
Feb 24, 2005
Description
Page
0.30
Mar 8, 2005
Sep 01, 2005
Summary
1 to 3
5, 6
Pin type changed: 48-pin(under consideration) → 52-pin.
5 to 7
Package type revised: 48-pin LQFP(under consideration) →
PLQP0052JA-A
8
Table 1.5 TCLK added, VREF revised.
9
Table 1.6 revised.
13, 14
0.20
R8C/24 Group, R8C/25 Group Datasheet
Figures 3.1 and 3.2 part number revised.
15
Tabel 4.1 revised:
- 000Fh: 000XXXXXb → 00011111b
- 0023h: FR0 → FRA0
- 0024h: FR1 → FRA1
- 0025h: FR2 → FRA2
- 0031h: Voltage Detection A Register 1, VC1
→ Voltage Detection Register 1, VCA1
- 0032h: Voltage Detection A Register 2, VC2
→ Voltage Detection Register 2, VCA2
17
Tabel 4.3 Register name and the value after reset at 00B8h to 00BFh
revised; NOTE2 added.
19
Tabel 4.5 revised:
- 0107h: LINSR → LINST
- 0137h to 013Fh: Register symbol revised
20
Tabel 4.6 revised:
- 0140h to 015Fh: Register symbol revised
- 0158h, 0159h: Timer RD General Register → Timer RD General Register
A1
2, 3
8
Tables 1.1, 1.2 and 1.5 revised: “main clock” → “XIN clock”; “sub clock”
→ “XCIN clock”
15
- 0023h to 0025h: 40MHz On-Chip Oscillator Control Register
→ High-Speed On-Chip Oscillator Control Register
2, 3
Table 1.1 R8C/24 Group Performance, Table 1.2 R8C/25 Group
Performance
• Serial Interface revised:
- Serial Interface: 2 channels Clock synchronous serial I/O, UART
- Clock Synchronous Serial Interface: 1 channel
I2C bus Interface(1), Clock synchronous serial I/O with chip select
4
5, 6
Figure 1.1 Block Diagram
• UART or Clock Synchronous Serial Interface: “(8 bits × 1 channel)” →
“(8 bits × 2 channels)” revised
• UART (8 bits × 1 channel) deleted
Table 1.3 Product Information of R8C/24 Group, Table 1.4 Product
Information of R8C/25 Group
“Flash Memory Version” → “N Version” revised
A-2
REVISION HISTORY
Rev.
Date
0.30
Sep 01, 2005
R8C/24 Group, R8C/25 Group Datasheet
Description
Page
Summary
7
Figure 1.4 Pin Assignment
• Pin name revised;
VSS → VSS/AVSS,
VCC → VCC/AVCC,
P1_5/RXD0/(TRAIO)/(INT1) → P1_5/RXD0/(TRAIO)/(INT1)(2),
P6_6/INT2/(TXD1) → P6_6/INT2/TXD1,
P6_7/INT3/(RXD1) → P6_7/INT3/RXD1,
P6_5 → P6_5/CLK1
• NOTE2 added
8
Table 1.5 Pin Description
• Analog Power Supply Input: line added
• INT Interrupt Input: “INT0 Timer RD input pins. INT1 Timer RA input
pins.” added
• Serial Interface: “CLK1” added
• “I2C Bus Interface (IIC)” → “I2C Bus Interface”
• “SSU” → “Clock Synchronous Serial I/O with Chip Select”
9
Table 1.6 Pin Name Information by Pin Number revised
• Pin Number 10: “VSS” → “VSS/AVSS”
• Pin Number 12: “VCC” → “VCC/AVCC”
• Pin Number 27: “INT0” added
• Pin Number 28: “(TXD1)” → “TXD1”
• Pin Number 29: “(RXD1)” → “RXD1”
• Pin Number 35: “CLK1” added
15
Tabel 4.1 SFR Information(1) revised:
• 0012h: X0h → 00h
• 0013h: XXXXXX00b → 00h
• 0016h: X0h → 00h
• 0036h: Voltage Monitor 1 Control Register(2) → Voltage Monitor 1
Control Register(5)
• 0038h: 00001000b(3), 01000001b(4) → 0000X000b(3), 0100X001b(4)
• NOTES2, 5: “the voltage monitor 1 reset” added
• NOTE3: “voltage monitor 1 reset” → “voltage monitor 0 reset”
16
Tabel 4.2 SFR Information(2) revised:
• 0048h: RD0IC → TRD0IC
• 0049h: RD1IC → TRD1IC
• 004Ah: REIC → TREIC
• 004Fh: SSU/IIC Interrupt Control Register, IIC2AIC →
SSU/IIC Interrupt Control Register(2), SSUAIC/IIC2AIC
• 0056h: RAIC → TRAIC
• 0058h: RBIC → TRBIC
• NOTE2 added
17
Tabel 4.3 SFR Information(3) revised:
• 00BCh: 00h → 00h/0000X000b
18
Tabel 4.4 SFR Information(4) revised:
• 00D6h: 00000XXXb → 00h
• 00F5h: UART1 Function Select Register, U1SR, XXh added
A-3
REVISION HISTORY
Rev.
Date
0.30
Sep 01, 2005
R8C/24 Group, R8C/25 Group Datasheet
Description
Page
Summary
19
Tabel 4.5 SFR Information(5) revised:
• 0118h : Timer RE Second Data Register/Counter Register →
Timer RE Second Data Register/Counter Data Register
20
Tabel 4.6 SFR Information(6) revised:
• 0145h
POCR0
→ TRDPOCR0
• 0146h, 0147h TRDCNT0 → TRD0
• 0148h, 0149h GRA0
→ TRDGRA0
• 014Ah, 014Bh GRB0
→ TRDGRB0
• 014Ch, 014Dh GRC0
→ TRDGRC0
• 014Eh, 014Fh GRD0
→ TRDGRD0
• 0155h
POCR1
→ TRDPOCR1
• 0156h, 0157h TRDCNT1 → TRD1
• 0158h, 0159h GRA1
→ TRDGRA1
• 015Ah, 015Bh GRB1
→ TRDGRB1
• 015Ch, 015Dh GRC1
→ TRDGRC1
• 015Eh, 015Fh GRD1
→ TRDGRD1
21
Tabel 4.7 SFR Information(7) revised:
• 01B5h: 01000101b → 1000000Xb
• 01B7h: XX000001b → 00000001b
• FFFFh: (Note 2) added
22 to 44 5. Electrical Characteristics added
0.40
Jan 24, 2006
all pages • “Preliminary” deleted
• Symbol name “TRDMDR” → “TRDMR”, “SSUAIC” → “SSUIC”, and
“IIC2AIC” → “IICIC” revised
• Pin name “TCLK” → “TRDCLK” revised
2
Table 1.1 Functions and Specifications for R8C/24 Group revised
3
Table 1.2 Functions and Specifications for R8C/25 Group revised
4
Figure 1.1 Block Diagram;
“Peripheral Functions” added,
“System Clock Generation” → “System Clock Generator” revised
5
Table 1.3 Product Information for R8C/24 Group revised
6
Table 1.4 Product Information for R8C/25 Group revised
7
Figure 1.4 Pin Assignments (Top View) “TCLK” → “TRDCLK” revised
8
Table 1.5 Pin Functions “TCLK” → “TRDCLK” revised
9
Table 1.6 Pin Name Information by Pin Number;
“TCLK” → “TRDCLK” revised
10
Figure 2.1 CPU Registers;
“Reserved Area” → “Reserved Bit” revised
12
2.8.10 Reserved Area;
“Reserved Area” → “Reserved bit” revised
13
Figure 3.1 Memory Map of R8C/24 Group;
“Program area” → “program ROM” revised
14
3.2 R8C/25 Group, Figure 3.2 Memory Map of R8C/25 Group;
“Data area” → “data flash”, “Program area” → “program ROM” revised
A-4
REVISION HISTORY
Rev.
Date
0.40
Jan 24, 2006
R8C/24 Group, R8C/25 Group Datasheet
Description
Page
Summary
15
Table 4.1 SFR Information(1);
0024h:
“TBD” → “When shipping”
NOTES 3 and 4 revised
19
Table 4.5 SFR Information (5);
0118h:
“Timer RE Second Data Register” → “Timer RE Second
Data Register / Counter Data Register”
0119h:
“Timer RE Minute Data Register” → “Timer RE Minute Data
Register / Compare Data Register”
0138h:
“TRDMDR” → “TRDMR”
013Bh:
“Timer RD Output Master Enable Register” → “Timer RD
Output Master Enable Register 1”
22
Table 5.1 Absolute Maximum Ratings;
“VCC” → ”VCC/AVCC” revised
Table 5.2 Recommended Operating Conditions revised
23
Table 5.3 A/D Converter Characteristics revised
24
Table 5.4 Flash Memory (Program ROM) Electrical Characteristics
revised
25
Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical revised
26
Table 5.6 Voltage Detection 0 Circuit Electrical Characteristics revised
Table 5.7 Voltage Detection 1 Circuit Electrical Characteristics revised
Table 5.8 Voltage Detection 2 Circuit Electrical Characteristics revised
28
Table 5.11 High-speed On-Chip Oscillator Circuit Electrical
Characteristics revised
Table 5.12 Low-speed On-Chip Oscillator Circuit Electrical
Characteristics revised
Table 5.13 Power Supply Circuit Timing Characteristics revised
29
Table 5.14 Timing Requirements of Clock Synchronous Serial I/O with
Chip Select revised
33
Table 5.15 Timing Requirements of I2C bus Interface NOTE1 revised
34
Table 5.16 Electrical Characteristics (1) [VCC = 5 V] revised
35
Table 5.17 Electrical Characteristics (2) [VCC = 5 V] revised
36
Table 5.18 XIN Input, XCIN Input revised
37
Table 5.20 Serial Interface revised
38
Table 5.22 Electrical Characteristics (3) [VCC = 3 V] revised
39
Table 5.23 Electrical Characteristics (4) [Vcc = 3 V] revised
40
Table 5.24 XIN Input, XCIN Input revised
41
Table 5.26 Serial Interface revised
42
Table 5.28 Electrical Characteristics (5) [VCC = 2.2 V] revised
43
Table 5.29 Electrical Characteristics (6) [Vcc = 2.2 V] revised
44
Table 5.30 XIN Input, XCIN Input revised
Table 5.31 TRAIO Input, INT1 Input revised
45
Table 5.32 Serial Interface revised
Table 5.33 External Interrupt INTi (i = 0, 2, 3) Input
A-5
REVISION HISTORY
Rev.
Date
0.40
Jan 24, 2006
1.00
May 31, 2006
R8C/24 Group, R8C/25 Group Datasheet
Description
Page
46
Summary
Package Dimensions;
“TBD” → “PLQP0052JA-A (52P6A-A)” added
all pages “Under development” deleted
1
1. Overview; “data flash ROM” → “data flash” revised
3
Table 1.2 Functions and Specifications for R8C/25 Group revised
4
Figure 1.1 Block Diagram;
“System clock generator” → “System clock generation circuit” revised
5 to 6
Table 1.3 Product Information for R8C/24 Group and Table 1.4 Product
Information for R8C/25 Group; A part of (D) mark is deleted.
9
Table 1.6 Pin Name Information by Pin Number NOTE1 added
15
Table 4.1 SFR Information(1);
001Ch: “00h” → “00h, 10000000b” revised
0029h: High-Speed On-Chip Oscillator Control Register 4 FRA4 When shipping added
002Bh: High-Speed On-Chip Oscillator Control Register 6 FRA6 When shipping added
NOTE6 added
19
Table 4.5 SFR Information(5);
0118h: Timer RE Second Data Register / Counter Data Register,
0119h: Timer RE Minute Data Register / Compare Data Register
register name revised
20
Table 4.6 SFR Information(6);
0143h: “11000000b” → “11100000b” revised
22
Table 5.2 Recommended Operating Conditions revised
24
Table 5.4 Flash Memory (Program ROM) Electrical Characteristics revised
25
Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical
Characteristics revised
26
Figure 5.2 Time delay until Suspend title revised
27
Table 5.9 Voltage Monitor 0 Reset Electrical Characteristics → Table 5.9
Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics
revised
Table 5.10 Power-on Reset Circuit Electrical Characteristics (When Not
Using Voltage Monitor 0 Reset) deleted
Figure 5.3 Power-on Reset Circuit Electrical Characteristics revised
28
Table 5.10 High-speed On-Chip Oscillator Circuit Electrical
Characteristics revised
Table 5.11 Low-speed On-Chip Oscillator Circuit Electrical
Characteristics revised
35
Table 5.16 Electrical Characteristics (2) [Vcc = 5 V] revised
39
Table 5.22 Electrical Characteristics (4) [Vcc = 3 V] revised
43
Table 5.28 Electrical Characteristics (6) [Vcc = 2.2 V] revised
46
Package Dimensions;
“The latest package ... Renesas Technology website.” added
A-6
REVISION HISTORY
Rev.
Date
2.00
Jul 14, 2006
Description
Page
2, 3
Feb 29, 2008
Summary
all pages “PTLG0064JA-A (64F0G)” package added
1
3.00
R8C/24 Group, R8C/25 Group Datasheet
1. Overview; “... or a 64-pin molded-plastic FLGA.“ added
Table 1.1 Functions and Specifications for R8C/24 Group, Table 1.2
Functions and Specifications for R8C/25 Group;
Package: “64-pin molded-plastic FLGA” added
5
Table 1.3 Product Information for R8C/24 Group, Figure 1.2 Type
Number, Memory Size, and Package of R8C/24 Group revised
6
Table 1.4 Product Information for R8C/25 Group, Figure 1.3 Type
Number, Memory Size, and Package of R8C/25 Group revised
7
Figure 1.4 PLQP0052JA-A Package Pin Assignments (Top View);
NOTE3 revised
8
Figure 1.5 PTLG0064JA-A Package Pin Assignments added
14
Figure 3.1 Memory Map of R8C/24 Group revised
15
Figure 3.2 Memory Map of R8C/25 Group revised
23
Table 5.1 Absolute Maximum Ratings; NOTE1 added
47
Package Dimensions; “PTLG0064JA-A (64F0G)” added
all pages Y version added
Factory programming product added
2, 3
Table 1.1, Table 1.2 Clock; “Real-time clock (timer RE)” added
5, 7
Table 1.3, Table 1.4 revised
6, 8
Figure 1.2, Figure 1.3; ROM number “XXX” added
16, 17
Figure 3.1, Figure 3.2; “Expanded area” deleted
18
Table 4.1 revised
26
Table 5.2 NOTE2 revised
32
Table 5.10; revised, NOTE4 added
Table 5.11; Oscillation stability time: Condition “VCC = 5.0 V, Topr =
25°C” deleted
38
Table 5.15; IIH, IIL, RPULLUP Condition: “Vcc = 5V” added
39
Table 5.16; Condition: High-speed on-chip oscillator mode revised
40
Table 5.17 added
41
Figure 5.8 revised
43
Table 5.22; IIH, IIL, RPULLUP Condition: “Vcc = 3V” added
44
Table 5.23; Condition “Increase during A/D converter operation” added
45
Figure 5.12 revised
48
Table 5.29; Condition “Increase during A/D converter operation” added
49
Figure 5.16 revised
A-7
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
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destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
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(3) healthcare intervention (e.g., excision, administration of medication, etc.)
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Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
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