APPLICATION NOTE
V850E2/MN4
CSIH Control
R01AN0924EJ0100
Rev.1.00
Feb 10, 2012
Introduction
This application note explains how to set up the CSIH (clocked three-wire serial interface) and also gives an outline of
the operation and describes the procedures for using a sample program. The sample program transmits and receives data
between the CSIH0 and CSIH3. The CSIH0 transmits data in master mode, while the CSIH3 receives data in slave
mode. The sample program uses two memory modes: direct access modes and dual buffer mode.
Target Device
V850E2/MN4 Microcontrollers
Contents
1.
Overview ........................................................................................................................................... 2
2.
Usage Environment........................................................................................................................... 8
3.
Software ............................................................................................................................................ 9
4.
Sample Application.......................................................................................................................... 10
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1.
CSIH Control
Overview
This application note explains the following four operation modes of the CSIH as usage examples:
• Master dual-buffer transmit-only mode
• Slave dual-buffer receive-only mode
• Master direct-access transmit-only mode
• Slave direct-access receive-only mode
In master mode, the serial communication clock is generated by the internal baudrate generator (BRG) and supplied by
signal CSIHnTSCK. In slave mode, another device is the communication master. The communication clock is supplied.
See section 4.1 “Flow Charts” for the details of the sample program.
The main points in master dual-buffer transmit-only mode are illustrated below.
Transmit data generation
processing
: Flow of processing
: Interrupt
.........
First, an user-supplied
array is defined.
Transmit buffer
Main loop
processing
Start of transmission
Transmit status interrupt
processing
Transmission is started when the
CSIHnMCTL2.CSIHnBTST bit set.
No
End of
transmission
?
Yes
Interrupt
Transmit status interrupt
Transmission is ended and
then the user flag is set to 1.
End of processing
Figure 1.1 Master Dual-Buffer Transmit-Only Mode
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CSIH Control
The main points in slave dual-buffer receive-only mode are illustrated below.
: Flow of processing
Main loop
processing
: Interrupt
Receive status interrupt
processing
Start of transmission
Interrupt
Receive status interrupt
No
End of
transmission
?
Yes
End of processing
The receive data is stored in the user
receive array and then set the user
receive end flag is set to 1.
Communication error
interrupt processing
Interrupt
Communication error
interrupt
The communicatin is stopped, the
SFR error flag is cleared, and then,
the CSIHn is reset.
Figure 1.2 Slave Dual-Buffer Receive-Only Mode
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CSIH Control
The main points in master direct-access transmit-only mode (Job mode is enabled) are illustrated below.
: Flow of processing
Transmit data generation
processing
JOB1
JOB2
: Interrupt
First, an user-supplied array is
defined and the transmit data is
divided into two jobs.
Main loop
processing
Transmit status interrupt
processing
Start of transmission
Transmission is started when data
is stored in CSIH0TX0W.
No
Is transmission
enabled?
Yes
Write next transmit data
No
End of
transmission
?
Interrupt
Transmit status interrupt
The next data transmission
is enabled.
Job completion interrupt
processing
Interrupt
Job completion interrupt
Yes
End of processing
All the jobs are transmitted and
then the user transmit end flag is
set to 1.
Figure 1.3 Master Direct-Access Transmit-Only Mode (Job Mode Is Enabled)
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CSIH Control
The main points in slave direct-access receive-only mode are illustrated below.
: Flow of processing
: Interrupt
Main loop
processing
Receive status interrupt
processing
Interrupt
Start of reception
Receive status interrupt
No
End of
reception
?
The receive data is stored in the user
receive array. When all data have been
transmitted, the user flag is set to 1.
......
Yes
Receive buffer
End of processing
Communication error
interrupt processing
Interrupt
Transmit error interrupt
The communicatin is stopped, the
SFR error flag is cleared, and then,
the CSIHn is reset.
Figure 1.4 Slave Direct-Access Receive-Only Mode
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CSIH Control
The basic communication specifications are shown below.
Memory mode
Receive I/F
Transmit I/F
Transfer direction
Parity bits during
transmission/reception
Data length
Baud rate
FIFO size
Direct access mode
Communication data length
JOB (jobs)
EDL (extended data length)
LBM (loop-back mode)
SS (slave select)
1.1
Dual buffer mode
CSIH3
CSIH0
MSB first
No parity bit
None
6 bytes
2 jobs
8 bits
64 kbps
64 bytes (each of transmit FIFO
and receive FIFO
9 bytes
None
None
None
None
Initialization
The general registers and functional pins are initialized.
<Port setup>
•
•
•
•
Port n function control expansion registers (PFCEn)
Port n function control registers (PFCn)
Port n mode control registers (PMCn)
Port n mode registers (PMn)
1.2
CSIH Setup
The registers listed below are set up to control the operation of the CSIH. See section 4.2 for the details.
<CSIH control setup>
•
•
•
•
•
•
•
CSIHn control register 0 (CSIHnCTL0)
CSIHn control register 1 (CSIHnCTL1)
CSIHn control register 2 (CSIHnCTL2)
CSIHn memory control register 0 (CSIHnMCTL0)
CSIHn memory control register 1 (CSIHnMCTL1)
CSIHn memory control register 2 (CSIHnMCTL2)
CSIHn configuration register x (CSIHnCFGx)
1.3
Interrupt Enabling
Interrupts are enabled by the EI instruction.
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1.4
CSIH Control
Main Loop Processing
• The operation of data transfer via the CSIH depends on the memory mode.
In dual buffer mode, the transmitting CSIH0 transmits nine bytes of data and the receiving CSIH3 receives the nine
bytes of data from the CSIH0. The internal RAM has nine bytes (one byte (one block data) × nine) of an area for
each of the user transmit array to store transmit data and the user receive array to store receive data.
In direct access mode, the transmitting CSIH0 prepares six-byte data, divides the data into three bytes as a job, and
transmits the two jobs. The receiving CSIH3 receives six bytes of data and stores the data in the internal RAM. The
internal RAM has the six-byte (one byte (one block data) × six) user transmit array to store transmit data and the sixbyte user receive array to store receive data.
• The conditions under which data transfer via the CSIH starts depend on the memory mode.
<1> Transmission in CSIH master mode:
In direct access mode, data transmission is started by writing data to the CSIHnTX0W register after the setup
of the CSIH ends.
In dual buffer mode, data transmission is started by setting the CSIHnMCTL2.CSIHnBTST bit to 1.
<2> Reception in CSIH slave mode:
In direct access mode, data reception is started by detecting external clock CSIHnTSCK.
In dual buffer mode, data reception is started by setting the CSIHnMCTL2.CSIHnBTST bit to 1.
• Interrupts occur at the timings described below.
In direct access transmit mode, a transmit status interrupt (CSIHnTIC) occurs after each unit of data is transmitted.
In job mode, a job completion interrupt (CSIHnTIJC) occurs after the transfer of the job that is enabled by setting
the CSIH0CTL0.JOBE bit to 1 is completed.
In direct access receive mode, a receive status interrupt (CSIHnTIR) occurs each time data is received.
In dual buffer mode, a transmit status interrupt (CSIHnTIC) and a receive status interrupt (CSIHnTIR) occur after
the specified amount of data is transferred.
A communication status interrupt (CSIHnTIRE) is generated whenever a communication error occurs.
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2.
CSIH Control
Usage Environment
This section provides the circuit diagram and operating environment of the hardware on which this sample program is
to run.
2.1
Circuit Diagram
See “V850E2/MN4 Target Board User Manual: QB-V850E2MN4DUAL-TB (R20UT0683XJ)” for the details of the
circuit diagram.
This sample program performs CSI communication between the CSIH0 and the CSIH3. The CSIH0 transmits data in
master mode and the CSIH3 receives the data in slave mode. The P4_12 pin, the P4_13 pin, and the P4_11 pin are used
for the SO0F pin, the SI0F pin, and the SCK0F pin for the CSIH0, respectively. The P4_3 pin, the P4_6 pin, and the
P4_7 pin are used for the SO3F pin, the SI3F pin, and the SCK3F pin for the CSIH3, respectively. The SO0F pin is
connected to the SI3F pin and the SCK0F pin is connected to the SCK3F pin.
LED1 and LED2 are connected to port 13. The P13_7 pin is used for LED1. The P13_6 pin is used for LED2.
2.2
Development Environment
It is necessary to install the tools that are listed below to run the sample program.
• CubeSuite+
The integrated development environment CubeSuite+ from Renesas Electronics provides various software
development tools that are necessary for the user to develop applications. The user can use these tools seamlessly
and easily in various development stages including coding, assembly, compilation, debugging using an emulator or
simulator, and flash programming.
• MINICUBE
MINICUBE is a general-purpose in-circuit emulator from Renesas Electronics which adopts the JTAG interface
system. It allows the user to debug an onboard real processor and provides highly transparent and stable emulation
functionalities. An adapter is required to connect a TB board to MINICUBE.
• Multi
Green Hills software, Inc. integrated development tool suit.
IAR Embedded Workbench
IAR Systems integrated development tool suit.
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3.
CSIH Control
Software
This section describes the organization of the compressed files to be downloaded.
3.1
File Organization
The compressed files to be downloaded is summarized below.
File Name
(Tool Structure)
crtE.s
startup.s
V850E2MN4.dir
V850E2_MN4 CSIH.ld
vector.s
csih.h
main.c
initial.c
csih_transmit.c
csih_receive.c
interrupt.c
Description
Common
Source File
Hardware initialization processing
Link/directive file
Vector table
Variable and function declarations
Main processing
Software initialization processing
Transmit processing
Receive processing
Interrupt processing
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CubeSuite+
File
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Multi File
●
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4.
CSIH Control
Sample Application
This section explains how to set up the CSIH functions.
4.1
Flow Charts
The flow charts of this sample program are given below. The pertinent subroutines are entered according to the
operating mode that is set up by the user.
4.1.1
Main Processing
The main processing disables maskable interrupts first. After each setup ends, the maskable interrupts and
transmit/receive status interrupts are enabled. The main loop processing repeatedly controls communication and awaits
the end of communication.
START
DI
Disable maskable interrupts
PORT_INITIAL
APPLICATION_INITIAL
RECEIVE_INITIAL
TRANSMIT_INITIAL
Initialize system
Initialize ports
Initialize variables
Initialize CSIH3 for reception
and enable receive interrupts
n
o
i
t
a
z
i
l
a
i
t
i
n
I
SYSTEM_INITIAL
Initialize CSIH0 for transmission
and enable transmit interrupts
Enable maskable interrupts
TRANSMIT_START
RECEIVE_START
OVER ?
Start communication
Start reception
Await end of transmission /
reception
p
o
o
l
n
i
a
M
EI
NO
Start program
YES
FLAGS_CLEAR
Clear user transmit / receive end flag
Figure 4.1 Main Processing Flowchart
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4.1.2
CSIH Control
Master Direct-Access Transmit-Only Mode
Master direct-access transmit-only mode is started by writing transmit data to the CSIHnTX0W register. Forty-eight
bits (six bytes) of transmit data are divided into two jobs before transmission. The communication data length is eight
bits.
Start
Initialize CSIHn
Write transmit data to
CSIHnTX0W register
Start transmission
Last job?
NO
YES
Set JOBE bit to 1
Write next transmit data
Have CSIHnTIC
interrupt occurred?
NO
YES
Have CSIHnTIJC
interrupt occurred?
NO
YES
Set user transmit end flag
End
Remark 1. The broken lines indicate hardware processing.
Figure 4.2 Flowchart of Master Direct-Access Transmit-Only Mode
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4.1.3
CSIH Control
Slave Direct-Access Receive-Only Mode
Slave direct-access receive-only mode is started by detecting external clock CSIHTSCK.
Start
Initialize CSIHn
Has communication
clock CSIHnTSCK been
detected?
NO
YES
Start of reception
Has CSIHnTIR
interrupt occurred?
NO
YES
Read data from CSIHnRX0W register
by receive data read processing
NO
End of reception?
YES
Set user receive end flag
End
Remark 1. The broken lines indicate hardware processing.
Figure 4.3 Flowchart of Slave Direct-Access Receive-Only Mode
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4.1.4
CSIH Control
Master Dual-Buffer Transmit-Only Mode
Master dual-buffer transmit-only mode is started by setting the CSIHnMCTL2.CSIHnBTST bit to 1.
Start
Initialize CSIHn
Write transmit data to
CSIHnTX0W register
Have all data been
written?
NO
YES
Set BTST bit to 1
Start transmission
Have CSIHnTIC
interrupt occurred?
NO
YES
Set user transmit end flag
End
Remark 1. The broken lines indicate hardware processing
Figure 4.4 Flowchart of Master Dual-Buffer Transmit-Only Mode
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4.1.5
CSIH Control
Slave Dual-Buffer Receive-Only Mode
Slave dual-buffer receive-only mode is started by setting the CSIHnMCTL2.CSIHnBTST bit to 1 and then detecting
external clock CSIHTSCK.
Start
Initialize CSIHn
Set BIST bit to 1
Has communication
clock CSIHnTSCK been
detected?
NO
YES
Start of reception
Has CSIHnTIR
interrupt occurred?
NO
YES
Read data from CSIHnRX0W register
by receive data read processing
Have all data
been read?
NO
YES
Set user receive end flag
END
Remark 1. The broken lines indicate hardware processing
te
Figure 4.5 Flowchart of Slave Dual-Buffer Receive-Only Mode
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4.1.6
CSIH Control
Communication Error Interrupt Processing
If a communication error occurs, a communication error interrupt is generated. Then, the communication error interrupt
processing is executed. The communication is stopped and the SFR error flag is cleared. The CSIHn is reset at the same
time.
Status interrupt
INT_CSIHTIRE
Clear error flag
Reset CSIHn
End of processing
Figure 4.6 Communication Error Interrupt Processing
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4.2
CSIH Control
Register Setup
This section explains how to set up the relevant registers according to the flow charts shown in section 4.1. The
registers described below must be configured to control the CSIH.
4.2.1
Port Setup
The program described in this application note executes serial transmission/reception by using two macros, the CSIH0
and the CSIH3. The relevant ports must be set up so that the pins for the CSIH0 and the CSIH3 are enabled.
The LEDs are connected to port 13. The P13_7 pin is used for LED1. The P13_6 pin is used for LED2.
Macro
CSIH0
CSIH3
PORT
Pin
SO0F
SI0F
SCK0F
SO3F
SI3F
SCK3F
P13_6
P13_7
PMC
1
1
1
1
1
1
0
0
PFCE
1
1
1
1
1
1
0
0
PFC
1
1
1
1
1
1
0
0
PM
0
1
0
0
1
1
0
0
Corresponding Function
Alternative mode 4, output
Alternative mode 4, input
Alternative mode 4, output
Alternative mode 4, output
Alternative mode 4, input
Alternative mode 4, input
Port mode, output
Port mode, output
Setting examples
/* alternative mode 4 in that csih
CSIH0:Master Mode,transmission
P4_12: CSIHTA0SO
P4_13: CSIHTA0SI
P4_11: CSIHTA0SCO
CSIH3:Slave Mode,receptiom
P4_3: CSIHTA3SO
P4_6: CSIHTA3SI
P4_7: CSIHTA3SCI */
PFCE4 = 0x38c8;
PFC4 = 0x38c8;
PMC4 = 0x38c8;
PM4 = 0x20c0;
/* P13_6,7: LEDs,IO,OUTPUT */
PFCE13 = 0x0000;
PFC13 = 0x0000;
PMC13 = 0x0000;
PM13 = 0x0000;
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4.2.2
CSIH Control
CSIH Control Register 2 (CSIHnCTL2)
The CSIHnCTL2 register selects the communication clock.
In master mode, the transmission baud rate can be selected by the CSIHnPRS[2:0] bits and the CSIHnBRS[11:0] bits in
the CSIHnCTL2 register. The maximum available baud rate is Pclk/4 in master mode and Pclk/6 in slave mode. The
minimum available baud rate is Pclk/524160 in both modes.
In this sample program, the communication clock is set to 64 kbps, and the CSIHnPRS[2:0] bits are set to 1, and the
CSIHnBRS[11:0] bits are set to 260.
Figure 4.7 CSIHnCTL2 Register Format
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CSIH Control
Setting example
CSIHnCTL2 = 0x2104;
CSIHnCTL2 = 0xE000;
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/* master mode;Pclk/2^1*260*2 */
/* slave mode */
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4.2.3
CSIH Control
CSIH Control Register 0 (CSIHnCTL0)
The CSIHnCTL0 register controls the operation clock, enables or disables transmission and reception, and specifies the
use for the CSIH memory. It forces the stop of communication at the end of the current job.
Figure 4.8 CSIHnCTL0 Register Format (1/2)
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CSIH Control
Figure 4.9 CSIHnCTL0 Register Format (2/2)
CSIHnCTL0 = 0x00;
CSIHnPWR = 1;
CSIHnTXE = 1;
CSIHnRXE = 1;
CSIHnMBS = 0;
CSIHnMBS = 1;
CSIHnJOBE = 1;
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/* stop CSIH0 */
/* permit CSIHn */
/* permit transmission */
/* permit reception */
/* memory mode */
/* direct access mode */
/* stop communication after this JOB */
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4.2.4
CSIH Control
CSIH Control Register 1 (CSIHnCTL1)
The CSIHnCTL1 register controls the communication. It mainly specifies the interrupt timing and interrupt delay mode
and selects the active output level of each chip select signal and the chip select signal operation to perform after the last
data is transferred.
Figure 4.10 CSIHnCTL1 Register Format (1/3)
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CSIH Control
Figure 4.11 CSIHnCTL1 Register Format (2/3)
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CSIH Control
Figure 4.12 CSIHnCTL1 Register Format (3/3)
CSIHnCTL1 = 0x00010040;
CSIHnCTL1 = 0x00000000;
CSIHnCTL1 = 0x00000000;
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/* TIC at start;CS0 inactive;JOB mode enable */
/* Output initial CSIHTSCO value at high level */
/* Transmit status interrupt request is generated at beginning of
transmission */
/* Set chip select signal CS0 to active low*/
/* Disable extended data length mode */
/* Enable job mode */
/* Disable data consistency check */
/* Chip select signals retain active level */
/* Set loopback mode inactive */
/* No interrupt delay mode */
/* Disable handshake function */
/* Disable slave selection (SS) */
/* Normal interrupt timing */
/* CS0 inactive */
/* Disable job mode */
/* Set chip select signals to active low */
/* hand shaking disable */
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4.2.5
CSIH Control
CSIH Configuration Register x (CSIHnCFGx)
The CSIHnCFGx registers specify the prescaler, the parity, the data length, the recessive configuration for broadcasting,
the serial data direction, the clock phase and the data phase, the idle enforcement configuration, the idle timing, the hold
timing, the inter-data timing, and the setup timing for each chip select signal CSIHCSSx.
In master mode, one or more chip select signals can be used. If several slaves are connected to the master, the chip
select signals can be used to address one or more of the slaves. Only a selected slave is then enabled for communication.
A value must be set in the bit for each chip select signal according to the baud rate. In this sample program, these bits
are set to initial values.
Figure 4.13 CSIHnCFGx Register Format (1/5)
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CSIH Control
Figure 4.14 CSIHnCFGx Register Format (2/5)
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CSIH Control
Figure 4.15 CSIHnCFGx Register Format (3/5)
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CSIH Control
Figure 4.16 CSIHnCFGx Register Format (4/5)
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CSIH Control
Figure 4.17 CSIHnCFGx Register Format (5/5)
CSIHnCFG0 = 0x08000000;
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/* No parity */
/* data length 8 bits */
/* Recessive configuration: Dominant (higher priority) */
/* MSB first */
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4.2.6
CSIH Control
CSIH Memory Control Register 0 (CSIHnMCTL0)
The CSIHnMCTL0 register selects the memory mode and timeout setting.
FIFO mode, dual buffer mode, transmit-only buffer mode, and direct access mode can be set in the CSIH as memory
modes.
The sample program uses only dual buffer mode. It does not detect timeout time.
Figure 4.18 CSIHnMCTL0 Register Format
CSIH0MCTL0 = 0x0100;
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/* dual buffer mode; no timeout detection */
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4.2.7
CSIH Control
CSIH Status Clear Register 0 (CSIHnSTCR0)
The CSIH can detect five errors: data consistency error, parity error, overrun error, timeout error, and overflow error.
The parity error, data consistency error, and timeout error can be individually enabled or disabled by the CSIHnSTCR0
register. When any of these errors is detected, receive error interrupt CSIHTIRE is generated.
In this sample program, when receive error interrupt CSIHTIRE is detected, the relevant error flags are cleared by
setting each bit in the status clear register to 1.
Figure 4.19 CSIHnSTCR0 Register Format
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/* Clear status flags to 0 */
CSIHnTMOEC = 1;
CSIHnOFEC = 1;
CSIHnPEC = 1;
CSIHnOVEC = 1;
CSIHnPCT = 1;
CSIHnDCEC = 1;
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CSIH Control
/* Clear timeout error flag */
/* Clear overflow error flag */
/* Clear parity error flag */
/* Clear overrun error flag */
/* Clear FIFO buffer pointer */
/* Clear data consistency error flag */
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4.3
CSIH Control
Memory Modes
The CSIH supports FIFO mode, dual buffer mode, transmit-only buffer mode, and direct access mode as memory
modes. The memory mode can be changed by resetting CSIHnMCTL0.CSIHnMMS[1:0]. The conditions for starting
CSIH data transfer and the interrupt timing depends on the memory mode, the operation mode, and the transfer mode.
Table 4.1 Start of Data Transfer
Memory Mode and
Operating Mode
FIFO mode
Direct access mode
Master
Slave
Transmit-only
buffer mode
Master
Slave
Dual buffer mode
Master
Slave
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Transfer Mode
Receive
Transmit-Only and
Transmit/Receive
Writes to the CSIHnTX0 register
Writes to the CSIHnTX0 register
Receives a clock from the master
Writes to the CSIHnTX0 register
and starts the master clock
Sets CSIHnMCTL2.BTST to 1
Sets CSIHnMCTL2.BTST to 1
Receives a clock from the master
Sets CSIHnMCTL2.BTST to 1
and starts the master clock
Sets CSIHnMCTL2.BTST to 1
Sets CSIHnMCTL2.BTST to 1
Receives a clock from the master
Sets CSIHnMCTL2.BTST to 1
and starts the master clock
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4.4
CSIH Control
Function Specifications
This section describes the specifications for the functions that are used by the sample program.
4.4.1
Main Processing (main.c)
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
4.4.2
main ()
Calls necessary initialization functions before entering an infinite loop.
None
None
Enters the main function after hardware initialization.
None
None
flag_mode, flag_transmit_over, flag_receive_over, flag_error
main.c
None
Software Initialization Processing (initial.c)
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
port_initial()
Sets up ports and their mode.
None
None
Call
PFCE4, PFC4, PMC4, PM4, PFCE13, PFC13, PMC13, PM13
main()
None
initial.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
cg_initial()
Initializes the special clock frequency control register.
None
None
Call
SFRCTL3
main()
None
initial.c
None
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V850E2/MN4
CSIH Control
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
hbus_initial()
Initializes the AHB bus.
None
None
Call
ETARCFG0, ETARADRS0, ETARMASK0
main()
None
initial.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
board_initial()
Sets up the initial state of the LEDs.
None
None
Call
P13
main()
None
initial.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
ram_initial()
Sets up the initial states of the receive buffer and flags.
None
None
Call
None
main()
buf_receive[], flag_transmit_over, flag_receive_over, flag_job_transmit, flag_error,
flag_fifo_error, count, LED, point_receive, point_transmit
initial.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
wait()
Waits for a certain number of steps.
int number
None
Call according to the an argument setting.
None
main(), csih_transmit_1_start()
None
initial.c
None
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V850E2/MN4
CSIH Control
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
display()
Controls the LEDs according to the state of the relevant flags.
None
None
Call
P13
main()
flag_transmit_over, flag_receive_over, flag_error
initial.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
clear_receive_buffer ()
Clears receive buffer to 0.
None
None
Call
None
csih_receive_start ()
point_receive, buf_receive
initial.c
None
4.4.3
Receive Processing (csih_receive.c)
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
csih_receive_initial()
Selects the subroutine according to the communication mode flags.
None
None
Call
None
main()
flag_mode
csih_receive.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
csih_receive_1_initial()
The CSIH3 macro performs initialization in direct-access receive-only mode.
None
None
Call
CSIH3CTL0, CSIH3CTL1, CSIH3CTL2, CSIH3CFG0, ICCSIH3IR
csih_receive_initial()
None
csih_receive.c
None
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V850E2/MN4
CSIH Control
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
csih_receive_2_initial()
The CSIH3 macro performs initialization in dual-buffer receive-only mode.
None
None
Call
CSIH3CTL0, CSIH3CTL1, CSIH3CTL2, CSIH3CFG0, ICCSIH3IR
csih_receive_initial()
None
csih_receive.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
csih_receive_start ()
The CSIH3 macro performs reception in dual-buffer receive-only mode.
None
None
Call
CSIH3PWR, CSIH3MCTL2
main()
None
csih_receive.c
None
4.4.4
Transmit Processing (csih_transmit.c)
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
csih_transmit_initial()
Selects the subroutine according to the communication mode flags.
None
None
Call
None
main()
flag_mode
csih_transmit.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
csih_transmit_1_initial()
The CSIH0 macro performs initialization in direct-access transmit-only mode.
None
None
Call
CSIH0CTL0, CSIH0CTL1, CSIH0CTL2, CSIH0CFG0, ICCSIH0IC, ICCSIH0IJC
csih_transmit_initial()
None
csih_transmit.c
None
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V850E2/MN4
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
CSIH Control
[Calling Function]
[Variables]
[File Name]
[Notes]
csih_transmit_2_initial()
The CSIH0 macro performs initialization in dual-buffer transmit-only mode.
None
None
Call
CSIH0CTL0, CSIH0CTL1, CSIH0CTL2, CSIH0CFG0, ICCSIH0IC, CSIH0MCTL0,
CSIH0MCTL2
csih_transmit_initial()
None
csih_transmit.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
csih_transmit_start()
Selects the subroutine according to the communication mode flags.
None
None
Call
None
main()
flag_mode
csih_transmit.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
csih_transmit_1_start()
The CSIH0 macro performs transmission in direct-access transmit-only mode.
None
None
Call
CSIH0CTL0, CSIH3CTL0, CSIH0TX0W
csih_transmit_start()
flag_job_transmit
csih_transmit.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
csih_transmit_2_start()
The CSIH0 macro performs transmission in dual-buffer transmit-only mode.
None
None
Call
CSIH0CTL0, CSIH3CTL0, CSIH0TX0W, CSIH0TX0W, CSIH0MCTL2
csih_transmit_start()
point_transmit
csih_transmit.c
None
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Page 37 of 40
V850E2/MN4
4.4.5
CSIH Control
Interrupt Processing (interrupt.c)
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
int_csih0ic()
Processes CSIH0 macro transmit status interrupt.
None
None
Request CSIH0TIC is present in an unmasked state.
CSIH0CTL0
None
flag_mode, flag_job_transmit, flag_transmit_over
interrupt.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
I int_csih0ijc()
Processes CSIH0 macro job completion interrupt.
None
None
Request CSIH0TIJC is present in an unmasked state.
CSIH0CTL0
None
flag_mode, flag_transmit_over
interrupt.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
int_csih0ire()
Processes CSIH0 macro communication error interrupt.
None
None
Request CSIH0TIRE is present in an unmasked state.
CSIH0STCR0, CSIH0CTL0
None
flag_error, point_receive, point_transmit
interrupt.c
None
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
int_csih3ir()
Processes CSIH3 macro receive status interrupt.
None
None
Request CSIH3TIR is present in an unmasked state.
CSIH3RX0W, CSIH3CTL0
None
flag_mode, point_receive, count, flag_receive_over
interrupt.c
None
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Feb 10, 2012
Page 38 of 40
V850E2/MN4
[Function Name]
[Function]
[Arguments]
[Return Value]
[Startup Method]
[SFRs Used]
[Calling Function]
[Variables]
[File Name]
[Notes]
CSIH Control
int_csih3ire()
Processes CSIH3 macro communication error interrupt.
None
None
Request CSIH3TIRE is present in an unmasked state.
CSIH3STCR0, CSIH3CTL0
None
flag_error, point_receive, point_transmit, count
interrupt.c
None
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Feb 10, 2012
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V850E2/MN4
CSIH Control
Website and Support
Renesas Electronics Website
http://www.renesas.com/
Inquiries
http://www.renesas.com/inquiry
All trademarks and registered trademarks are the property of their respective owners.
R01AN0924EJ0100 Rev.1.00
Feb 10, 2012
Page 40 of 40
Revision Record
Rev.
1.00
Date
Feb 10, 2012
Description
Page
Summary
—
First edition issued
A-1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the
products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General
Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the
description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and
pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins
are not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
⎯ When the clock signal is generated with an external resonator (or from an external oscillator)
during a reset, ensure that the reset line is only released after full stabilization of the clock signal.
Moreover, when switching to a clock signal produced with an external resonator (or by an external
oscillator) while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm that the
change will not lead to problems.
⎯ The characteristics of MPU/MCU in the same group but having different type numbers may differ
because of the differences in internal memory capacity and layout pattern. When changing to
products of different type numbers, implement a system-evaluation test for each of the products.
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5.
When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to
the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations.
6.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
7.
Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
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Refer to "http://www.renesas.com/" for the latest and detailed information.
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Colophon 1.1