Si5367 - Octopart

Si5367
P R E L I M I N A R Y D A TA S H E E T
µ P - P ROGRAMMABLE P RECISION C L O C K M ULTIPLIER
Description
Features
The Si5367 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5367 accepts four clock inputs ranging
from 10 to 707 MHz and generates five frequency-multiplied
clock outputs ranging from 10 to 945 MHz and select
frequencies to 1.4 GHz. The device provides virtually any
frequency translation combination across this operating
range. The outputs are divided down separately from a
common source. The Si5367 input clock frequency and clock
multiplication ratio are programmable through an I2C or SPI
interface. The Si5367 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides any-rate
frequency synthesis in a highly integrated PLL solution that
eliminates the need for external VCXO and loop filter
components. The DSPLL loop bandwidth is digitally
programmable, providing jitter performance optimization at
the application level. Operating from a single 1.8 or 2.5 V
supply, the Si5367 is ideal for providing clock multiplication in
high performance timing applications.
Applications
SONET/SDH OC-48/OC-192 STM-16/STM-64 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Wireless basestations
Data converter clocking
xDSL
SONET/SDH + PDH clock synthesis
Test and measurement
CKIN1
÷ N31
CKIN2
÷ N32
®
CKIN3
÷ N33
CKIN4
÷ N34
DSPLL
Generates any frequency from 10 to 945 MHz and
select frequencies to 1.4 GHz from an input
frequency of 10 to 710 MHz
Low jitter clock outputs w/jitter generation as low as
0.6 ps rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth
(30 kHz to 1.3 MHz)
Four clock inputs with manual or automatically
controlled switching
Five clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 FEC ratios (255/238,
255/237, 255/236)
LOS alarm outputs
Digitally-controlled output phase adjust
I2C or SPI programmable settings
On-chip voltage regulator for 1.8 ±5% or 2.5 V
±10% operation
Small size: 14 x 14 mm 100-pin TQFP
Pb-free, RoHS compliant
÷ NC1_LS
CKOUT1
÷ NC2_LS
CKOUT2
÷ NC3_LS
CKOUT3
÷ NC4_LS
CKOUT4
÷ NC5_LS
CKOUT5
N1_HS
÷ N2
2
I C/SPI Port
Clock Select
Control
Device Interrupt
VDD (1.8 or 2.5 V)
LOS Alarms
GND
Preliminary Rev. 0.4 2/08
Copyright © 2008 by Silicon Laboratories
Si5367
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5367
Table 1. Performance Specifications
(VDD = 1.8 ±5% or 2.5 V ±10%, TA = –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Supply Current
Input Clock Frequency
(CKIN1, CKIN2, CKIN3,
CKIN4)
Output Clock Frequency
(CKOUT1, CKOUT2,
CKOUT3, CKOUT4,
CKOUT5)
Symbol
TA
VDD
Test Condition
IDD
fOUT = 622.08 MHz
All CKOUTs enabled
LVPECL format output
Only CKOUT1 enabled
fOUT = 19.44 MHz
All CKOUTs enabled
CMOS format output
Only CKOUT1 enabled
Tristate/Sleep Mode
Input frequency and clock multiplication ratio determined by programming device PLL dividers. Consult
Silicon Laboratories configuration
software DSPLLsim or Any-Rate
Precision Clock Family Reference
Manual at www.silabs.com/timing
(click on Documentation) to determine PLL divider settings for a
given input frequency/clock multiplication ratio combination.
CKF
CKOF
Min
–40
2.25
1.71
—
Typ
25
2.5
1.8
394
Max
85
2.75
1.89
435
Unit
ºC
V
V
mA
—
—
253
278
284
321
mA
mA
—
—
10
229
TBD
—
261
TBD
707.35
mA
mA
MHz
10
970
1213
—
—
—
945
1134
1417
MHz
See Note 2.
–2
—
2
µA
1.8 V ±5%
2.5 V ±10%
20–80%
Whichever is smaller
0.25
0.9
1.0
—
40
2
—
—
—
—
—
—
1.9
1.4
1.7
11
60
VPP
V
V
ns
%
ns
VDD – 1.42
1.1
0.5
—
—
—
VDD – 1.25
1.9
0.93
V
V
V
230
350
ps
3-Level Input Pins
Input Mid Current
IIMM
Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4)
Differential Voltage Swing CKNDPP
Common Mode Voltage
CKNVCM
Rise/Fall Time
Duty Cycle
(Minimum Pulse Width)
CKNTRF
CKNDC
Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5)
Common Mode
VOCM
LVPECL
100 Ω load
Differential Output Swing
VOD
line-to-line
Single Ended Output
VSE
Swing
20–80%
Rise/Fall Time
CKOTRF
Notes:
1. For a more comprehensive listing of device specifications, consult the Silicon Laboratories Any-Rate Precision Clock
Family Reference Manual. This document can be downloaded from www.silabs.com/timing (click on
Documentation).
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
Manual. In most designs an external resistor voltage divider is recommended.
2
Preliminary Rev. 0.4
Si5367
Table 1. Performance Specifications (Continued)
(VDD = 1.8 ±5% or 2.5 V ±10%, TA = –40 to 85 ºC)
Parameter
Duty Cycle Uncertainty
Symbol
CKODC
Test Condition
LVPECL
Differential 100 Ω Line-to-Line Measured at 50% point
Min
–40
Typ
—
Max
40
Unit
ps
JGEN
fIN = fOUT = 622.08 MHz,
LVPECL output format
50 kHz–80 MHz
12 kHz–20 MHz
800 Hz–80 MHz
—
0.6
TBD
ps rms
—
—
—
—
0.6
TBD
0.05
TBD
TBD
TBD
0.1
TBD
ps rms
ps rms
dB
dBc/Hz
—
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
dBc
—
40
—
ºC/W
PLL Performance
Jitter Generation
Jitter Transfer
Phase Noise
JPK
CKOPN
Subharmonic Noise
Spurious Noise
SPSUBH
SPSPUR
Package
Thermal Resistance
Junction to Ambient
θJA
fIN = fOUT = 622.08 MHz
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
Phase Noise @ 100 kHz Offset
Max spur @ n x F3
(n > 1, n x F3 < 100 MHz)
Still Air
Notes:
1. For a more comprehensive listing of device specifications, consult the Silicon Laboratories Any-Rate Precision Clock
Family Reference Manual. This document can be downloaded from www.silabs.com/timing (click on
Documentation).
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
Manual. In most designs an external resistor voltage divider is recommended.
Table 2. Absolute Maximum Ratings
Symbol
Value
Unit
DC Supply Voltage
Parameter
VDD
–0.5 to 3.6
V
LVCMOS Input Voltage
VDIG
–0.3 to (VDD + 0.3)
V
Operating Junction Temperature
TJCT
–55 to 150
ºC
Storage Temperature Range
TSTG
–55 to 150
ºC
2
kV
ESD HBM Tolerance (100 pF, 1.5 kΩ), CKIN Pins
700
V
ESD MM Tolerance, Except CKIN Pins
200
V
ESD MM Tolernace, CKIN Pins
150
V
ESD HBM Tolerance (100 pF, 1.5 kΩ), Except CKIN Pins
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.4
3
Si5367
Phase Noise (dBc/Hz)
622 MHz In, 622 MHz Out BW=877 kHz
-50
-70
-90
-110
-130
-150
-170
1000
10000
100000
1000000
10000000 100000000
Offset Frequency (Hz)
Figure 1. Typical Phase Noise Plot
4
Jitter Bandwidth
RMS Jitter (fs)
OC-48, 12 kHz to 20 MHz
374
OC-192, 20 kHz to 80 MHz
388
OC-192, 4 MHz to 80 MHz
181
OC-192, 50 kHz to 80 MHz
377
Broadband, 800 Hz to 80 MHz
420
Preliminary Rev. 0.4
Si5367
System
Power
Supply
C10
Ferrite
Bead
1 µF
VDD = 3.3 V
0.1 µF
VDD
130 Ω
GND
130 Ω
C1–9
CKIN1+
CKOUT1+
CKIN1–
82 Ω
+
100 Ω
82 Ω
CKOUT1–
Input
Clock
Sources*
0.1 µF
CKOUT5+
VDD = 3.3 V
–
0.1 µF
Clock
Outputs
0.1 µF
+
100 Ω
130 Ω
130 Ω
CKIN4+
Si5367
Interrupt/Alarm Output
Indicator
CKINn Invalid Indicator
(n = 1 to 3)
CnB
82 Ω
Control Mode (L)
Reset
–
0.1 µF
INT_ALM
CKIN4–
82 Ω
CKOUT5–
A[2:0]
Serial Port
Address
CMODE
SDA
Serial Data
RST
SCL
Serial Clock
I2C
Interface
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 2. Si5367 Typical Application Circuit (I2C Control Mode)
System
Power
Supply
C10
Ferrite
Bead
1 µF
VDD = 3.3 V
CKIN1+
GND
0.1 µF
130 Ω
VDD
130 Ω
C1–9
CKOUT1+
CKIN1–
82 Ω
Input
Clock
Sources*
0.1 µF
+
100 Ω
82 Ω
CKOUT1–
CKOUT5+
VDD = 3.3 V
0.1 µF
0.1 µF
–
Clock
Outputs
+
100 Ω
130 Ω
CKOUT5–
130 Ω
CKIN4+
Si5367
INT_ALM
CKIN4–
82 Ω
CnB
82 Ω
SS
Control Mode (H)
Reset
CMODE
RST
0.1 µF
–
Interrupt/Alarm Output
Indicator
CKIN_n Invalid
Indicator (n = 1 to 3)
Slave Select
SDO
Serial Data
Out
SDI
Serial Data
In
SCL
Serial Clock
SPI
Interface
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 3. Si5367 Typical Application Circuit (SPI Control Mode)
Preliminary Rev. 0.4
5
Si5367
1. Functional Description
1.1. Further Documentation
The Si5367 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5367 accepts four clock inputs
ranging from 10 to 707 MHz and generates five
frequency-multiplied clock outputs ranging from 10 to
945 MHz and select frequencies to 1.4 GHz. The device
provides virtually any frequency translation combination
across this operating range. Independent dividers are
available for every input clock and output clock, so the
Si5367 can accept input clocks at different frequencies
and it can generate output clocks at different
frequencies. The Si5367 input clock frequency and
clock multiplication ratio are programmable through an
I2C or SPI interface. Silicon Laboratories offers a PCbased software utility, DSPLLsim, that can be used to
determine the optimum PLL divider settings for a given
input frequency/clock multiplication ratio combination
that minimizes phase noise and power consumption.
This
utility
can
be
downloaded
from
http://www.silabs.com/timing (click on Documentation).
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for detailed
information about the Si5367. Additional design support
is available from Silicon Laboratories through your
distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
The Si5367 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis in a highly integrated PLL
solution that eliminates the need for external VCXO and
loop filter components. The Si5367 PLL loop bandwidth
is digitally programmable and supports a range from
30 kHz to 1.3 MHz. The DSPLLsim software utility can
be used to calculate valid loop bandwidth settings for a
given input clock frequency/clock multiplication ratio.
The Si5367 monitors all input clocks for loss-of-signal
and provides a LOS alarm when it detects missing
pulses on its inputs.
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to the last valid operating state.
The Si5367 has five differential clock outputs. The
signal format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize power consumption. In addition, the phase of
each output clock may be adjusted in relation to the
other output clocks. The resolution varies from 800 ps to
2.2 ns depending on the PLL divider settings. Consult
the DSPLLsim configuration software to determine the
phase offset resolution for a given input clock/clock
multiplication ratio combination. For system-level
debugging, a bypass mode is available which drives the
output clock directly from the input clock, bypassing the
internal DSPLL. The device is powered by a single 1.8
or 2.5 V supply.
6
Preliminary Rev. 0.4
Si5367
VDD
CKOUT3+
CKOUT3–
VDD
NC
VDD
CKOUT1–
CKOUT1+
VDD
NC
CKOUT5–
VDD
CKOUT5+
VDD
CMODE
VDD
CKOUT2+
CKOUT2–
NC
VDD
VDD
CKOUT4–
VDD
CKOUT4+
VDD
2. Pin Descriptions: Si5367
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
1
NC
NC
2
74
NC
RST
3
73
NC
NC
4
72
NC
VDD
5
71
SDI
VDD
6
70
A2_SS
GND
GND
7
69
A1
8
68
A0
C1B
9
67
NC
C2B
10
66
NC
C3B
11
65
INT_ALM
12
64
GND
GND
CS0_C3A
13
63
VDD
GND
14
62
VDD
VDD
15
61
SDA_SDO
GND
60
SCL
NC
16
17
59
C2A
GND
18
58
C1A
GND
19
57
CS1_C4A
NC
20
56
NC
GND
21
55
GND
NC
22
GND
NC
23
54
53
NC
24
25
GND PAD
NC
NC
NC
NC
NC
CKIN1–
GND
CKIN1+
GND
VDD
GND
CKIN3–
CKIN3+
GND
NC
GND
CKIN2–
GND
CKIN2+
VDD
GND
CKIN4–
CKIN4+
NC
GND
NC
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VDD
52
GND
NC
Si5367
Table 3. Si5367 Pin Descriptions
Pin #
Pin Name
1, 2, 4, 17, 20,
22, 23, 24, 25,
37, 47, 48, 49,
50, 51, 52, 53,
56, 66, 67, 72,
73, 74, 75, 80,
85, 95
NC
3
RST
I/O
Signal Level
Description
No Connect.
These pins must be left unconnected for normal operation.
I
LVCMOS
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state and
forces the device registers to their default value. Clock
outputs are disabled during reset. The part must be programmed after a reset or power-on to get a clock output.
See Family Reference Manual for details.
This pin has a weak pull-up.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Preliminary Rev. 0.4
7
Si5367
Table 3. Si5367 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
5, 6, 15, 27, 32,
42, 62, 63, 76,
79, 81, 84, 86,
89, 91, 94, 96,
99, 100
VDD
Vdd
Supply
VDD.
The device operates from a 1.8 or 2.5 V supply. Bypass
capacitors should be associated with the following VDD
pins:
Pins
Bypass Cap
5, 6
0.1 µF
15
0.1 µF
27
0.1 µF
62, 63
0.1 µF
76, 79
1.0 µF
81, 84
0.1 µF
86, 89
0.1 µF
91, 94
0.1 µF
96, 99, 100
0.1 µF
7, 8, 14, 16, 18,
19, 21, 26, 28,
31, 33, 36, 38,
41, 43, 46, 54,
55, 64, 65
GND
GND
Supply
Ground.
This pin must be connected to system ground. Minimize
the ground path impedance for optimal performance.
9
C1B
O
LVCMOS
CKIN1 Invalid Indicator.
This pin performs the CK1_BAD function if
CK1_BAD_PIN = 1 and is tristated if CK1_BAD_PIN = 0.
Active polarity is controlled by CK_BAD_POL.
0 = No alarm on CKIN1.
1 = Alarm on CKIN1.
10
C2B
O
LVCMOS
CKIN2 Invalid Indicator.
This pin performs the CK2_BAD function if
CK2_BAD_PIN = 1 and is tristated if CK2_BAD_PIN = 0.
Active polarity is controlled by CK_BAD_POL.
0 = No alarm on CKIN2.
1 = Alarm on CKIN2.
11
C3B
O
LVCMOS
CKIN3 Invalid Indicator.
This pin performs the CK3_BAD function if
CK3_BAD_PIN = 1 and is tristated if CK3_BAD_PIN = 0.
Active polarity is controlled by CK_BAD_POL.
0 = No alarm on CKIN3.
1 = Alarm on CKIN3.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
8
Preliminary Rev. 0.4
Si5367
Table 3. Si5367 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
12
INT_ALM
O
LVCMOS
Interrupt/Alarm Output Indicator.
This pin functions as a maskable interrupt output with
active polarity controlled by the INT_POL register bit.
The INT output function can be turned off by setting
INT_PIN = 0. If the ALRMOUT function is desired
instead on this pin, set ALRMOUT_PIN = 1 and
INT_PIN = 0.
0 = ALRMOUT not active.
1 = ALRMOUT active.
The active polarity is controlled by CK_BAD_POL. If no
function is selected, the pin tristates.
13
57
CS0_C3A
CS1_C4A
I/O
LVCMOS
Input Clock Select/CKIN3 or CKIN4 Active Clock
Indicator.
Input: If manual clock selection is chosen, and if
CKSEL_PIN = 1, the CKSEL pins control clock
selection and the CKSEL_REG bits are ignored.
CS[1:0]
Active Input Clock
00
CKIN1
01
CKIN2
10
CKIN3
11
CKIN4
If configured as inputs, these pins must not
float.
Output: If CKSEL_PIN = 0, the CKSEL_REG register
bits control this function.
If auto clock selection is enabled, then they
serve as the CKIN_n active clock indicator.
0 = CKIN3 (CKIN4) is not the active input clock
1 = CKIN3 (CKIN4) is currently the active input
to the PLL
The CKn_ACTV_REG bit always reflects the
active clock status for CKIN_n. If
CKn_ACTV_PIN = 1, this status will also be
reflected on the CnA pin with active polarity controlled by the CK_ACTV_POL bit. If
CKn_ACTV_PIN = 0, this output tristates.
29
30
CKIN4+
CKIN4–
I
MULTI
Clock Input 4.
Differential clock input. This input can also be driven with
a single-ended signal. CKIN4 serves as the frame sync
input associated with the CKIN2 clock when
CK_CONFIG_REG = 1.
34
35
CKIN2+
CKIN2–
I
MULTI
Clock Input 2.
Differential input clock. This input can also be driven with
a single-ended signal.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Preliminary Rev. 0.4
9
Si5367
Table 3. Si5367 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
39
40
CKIN3+
CKIN3–
I
MULTI
Clock Input 3.
Differential clock input. This input can also be driven with
a single-ended signal. CKIN3 serves as the frame sync
input associated with the CKIN1 clock when
CK_CONFIG_REG = 1.
44
45
CKIN1+
CKIN1–
I
MULTI
Clock Input 1.
Differential clock input. This input can also be driven with
a single-ended signal.
58
C1A
O
LVCMOS
CKIN1 Active Clock Indicator.
This pin serves as the CKIN1 active clock indicator. The
CK1_ACTV_REG bit always reflects the active clock status for CKIN1. If CK1_ACTV_PIN = 1, this status will
also be reflected on the C1A pin with active polarity controlled by the CK_ACTV_POL bit. If
CK1_ACTV_PIN = 0, this output tristates.
59
C2A
O
LVCMOS
CKIN2 Active Clock Indicator.
This pin serves as the CKIN2 active clock indicator. The
CK2_ACTV_REG bit always reflects the active clock status for CKIN_2. If CK2_ACTV_PIN = 1, this status will
also be reflected on the C2A pin with active polarity controlled by the CK_ACTV_POL bit. If
CK2_ACTV_PIN = 0, this output tristates.
60
SCL
I
LVCMOS
Serial Clock.
This pin functions as the serial port clock input for both
SPI and I2C modes.
This pin has a weak pull-down.
61
SDA_SDO
I/O
LVCMOS
Serial Data.
In I2C microprocessor control mode (CMODE = 0), this
pin functions as the bidirectional serial data port.In SPI
microprocessor control mode (CMODE = 1), this pin
functions as the serial data output.
68
69
A0
A1
I
LVCMOS
Serial Port Address.
In I2C control mode (CMODE = 0), these pins function as
hardware controlled address bits. The I2C address is
1101 [A2][A1][A0.]
In SPI control mode (CMODE = 1), these pins are
ignored.
This pin has a weak pull-down.
70
A2_SS
I
LVCMOS
Serial Port Address/Slave Select.
In I2C microprocessor control mode (CMODE = 0), this
pin functions as a hardware controlled address bit. The
I2C address is 1101 [A2][A1][A0.]
In SPI microprocessor control mode (CMODE = 1), this
pin functions as the slave select input.
This pin has a weak pull-down.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
10
Preliminary Rev. 0.4
Si5367
Table 3. Si5367 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
71
SDI
I
LVCMOS
Serial Data In.
In SPI microprocessor control mode (CMODE = 1), this
pin functions as the serial data input.
In I2C microprocessor control mode (CMODE = 0), this
pin is ignored.
This pin has a weak pull-down.
77
78
CKOUT3+
CKOUT3–
O
MULTI
Clock Output 3.
Differential clock output. Output signal format is selected
by SFOUT3_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
82
83
CKOUT1–
CKOUT1+
O
MULTI
Clock Output 1.
Differential clock output. Output signal format is selected
by SFOUT1_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
87
88
CKOUT5–
CKOUT5+
O
MULTI
Clock Output 5.
Differential clock output. Output signal format is selected
by SFOUT5_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
90
CMODE
I
LVCMOS
92
93
CKOUT2+
CKOUT2–
O
MULTI
Clock Output 2.
Differential clock output. Output signal format is selected
by SFOUT2_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
97
98
CKOUT4–
CKOUT4+
O
MULTI
Clock Output 4.
Differential clock output. Output signal format is selected
by SFOUT4_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
GND PAD
GND PAD
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical impedance to a ground plane.
Control Mode.
Selects I2C or SPI control mode for the device.
0 = I2C Control Mode.
1 = SPI Control Mode.
This pin must be tied high or low.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Preliminary Rev. 0.4
11
Si5367
3. Ordering Guide
12
Ordering Part
Number
Output Clock
Frequency Range
Package
ROHS6,
Pb-Free
Temperature Range
Si5367A-C-GQ
10–945 MHz
970–1134 MHz
1.213–1.417 GHz
100-Pin 14 x 14 mm TQFP
Yes
–40 to 85 °C
Si5367B-C-GQ
10–808 MHz
100-Pin 14 x 14 mm TQFP
Yes
–40 to 85 °C
Si5367C-C-GQ
10–346 MHz
100-Pin 14 x 14 mm TQFP
Yes
–40 to 85 °C
Preliminary Rev. 0.4
Si5367
4. Package Outline: 100-Pin TQFP
Figure 4 illustrates the package details for the Si5366. Table 4 lists the values for the dimensions shown in the
illustration.
Figure 4. 100-Pin Thin Quad Flat Package (TQFP)
Table 4. 100-Pin Package Diagram Dimensions
Dimension
Min
Nom
Max
Dimension
Min
Nom
Max
A
—
—
1.20
E
16.00 BSC
A1
0.05
—
0.15
E1
14.00 BSC
A2
0.95
1.00
1.05
E2
3.85
4.00
4.15
b
0.17
0.22
0.27
L
0.45
0.60
0.75
c
0.09
—
0.20
aaa
—
—
0.20
D
16.00 BSC
bbb
—
—
0.20
D1
14.00 BSC
ccc
—
—
0.08
ddd
—
—
0.08
θ
0º
3.5º
7º
D2
e
3.85
4.00
0.50 BSC
4.15
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MS-026, variant AED-HD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
Preliminary Rev. 0.4
13
Si5367
5. Recommended PCB Layout
Figure 5. PCB Land Pattern Diagram
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Preliminary Rev. 0.4
Si5367
Table 5. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
0.50 BSC.
E
15.40 REF.
D
15.40 REF.
E2
3.90
4.10
D2
3.90
4.10
GE
13.90
—
GD
13.90
—
X
—
0.30
Y
1.50 REF.
ZE
—
16.90
ZD
—
16.90
R1
R2
0.15 REF
—
1.00
Notes (General):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes (Stencil Design):
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center
ground pad.
Notes (Card Assembly):
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
Preliminary Rev. 0.4
15
Si5367
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Changed LVTTL to LVCMOS in Table 2, “Absolute
Maximum Ratings,” on page 3.
Updated “2. Pin Descriptions: Si5367”.
Changed FSOUT (pins 87 and 88) to CLKOUT5.
Changed FS_ALIGN (pin 21) control pin to GND.
Changed pin 16 to ground.
Revision 0.2 to Revision 0.3
Removed references to latency control, INC, and
DEC pins.
Updated block diagram on page 1.
Added Figure 1, “Typical Phase Noise Plot,” on page
4.
Updated “2. Pin Descriptions: Si5367”.
Changed font of register names to underlined italics.
Updated "3. Ordering Guide" on page 12.
Added “5. Recommended PCB Layout”.
Revision 0.3 to Revision 0.5
Changed 1.8 V operating range to ±5%.
Clarified "2. Pin Descriptions: Si5367" on page 7.
Updated "4. Package Outline: 100-Pin TQFP" on
page 13.
16
Preliminary Rev. 0.4
Si5367
NOTES:
Preliminary Rev. 0.4
17
Si5367
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: Clockinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
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the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
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18
Preliminary Rev. 0.4