STK14D88 32Kx8 AutoStore nvSRAM

STK14D88
32Kx8 AutoStore nvSRAM
Features
Description
■
25, 35, 45 ns Read Access and R/W Cycle Time
■
Unlimited Read/Write Endurance
The Cypress STK14D88 is a 256Kb fast static RAM with a
nonvolatile Quantum Trap storage element included with each
memory cell.
■
Automatic Nonvolatile STORE on Power Loss
■
Nonvolatile STORE Under Hardware or Software Control
■
Automatic RECALL to SRAM on Power Up
■
Unlimited RECALL Cycles
■
200K STORE Cycles
■
20-Year Nonvolatile Data Retention
■
Single 3.0V +20%, -10% Power Supply
■
Commercial, Industrial Temperatures
■
Small Footprint SOIC and SSOP Packages (RoHS-Compliant)
ig
ns
The SRAM provides fast access and cycle times, ease of use,
and unlimited read and write endurance of a normal SRAM.
es
Data transfers automatically to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
rN
ew
D
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performance,
most reliable nonvolatile memory available.
fo
Logic Block Diagram
d
VCCX
POWER
CONTROL
en
STORE
RECALL
STORE/
RECALL
CONTROL
om
m
STATIC RAM
ARRAY
512 x 512
SOFTWARE
DETECT
ec
R
INPUT BUFFERS
ot
N
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
ROW DECODER
A5
A6
A7
A8
A9
A11
A12
A13
A14
de
Quantum Trap
512 x 512
VCAP
COLUMN I/O
HSB
A0 - A13
COLUMN DEC
A0 A1 A2 A3 A4 A10
G
E
W
Cypress Semiconductor Corporation
Document Number: 001-52037 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 01, 2009
[+] Feedback
STK14D88
Contents
Features................................................................................ 1
Description........................................................................... 1
Logic Block Diagram........................................................... 1
Contents ............................................................................... 2
Pin Configurations .............................................................. 3
Pin Descriptions .................................................................. 3
Absolute Maximum Ratings ............................................... 4
DC Characteristics .............................................................. 4
AC Test Conditions ............................................................. 5
Capacitance ......................................................................... 5
SRAM READ Cycles #1 and #2 ..................................... 6
SRAM WRITE Cycle #1 and #2 ..................................... 7
AutoStore/POWER UP RECALL ......................................... 8
Software-Controlled STORE/RECALL Cycle..................... 9
Hardware STORE Cycle ..................................................... 10
Soft Sequence Commands ............................................... 10
Mode Selection ................................................................... 11
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
ns
nvSRAM Operation............................................................ 12
nvSRAM ....................................................................... 12
SRAM READ ................................................................ 12
SRAM WRITE .............................................................. 12
AutoStore Operation...................................................... 12
Hardware STORE (HSB) Operation............................. 12
Software STORE.......................................................... 12
Software RECALL ........................................................ 13
Data Protection............................................................. 13
Best Practices .............................................................. 13
Low Average Active Power .......................................... 13
Noise Considerations ................................................... 14
Preventing AutoStore ................................................... 14
Part Numbering Nomenclature......................................... 16
Package Diagrams............................................................. 17
Document History Page ..................................................... 19
Sales, Solutions, and Legal Information ......................... 19
Worldwide Sales and Design Support.......................... 19
Products ....................................................................... 19
Document Number: 001-52037 Rev. *A
Page 2 of 18
[+] Feedback
STK14D88
Pin Configurations
Figure 1. Pin Diagram 48-Pin SSOP/32-SOIC
32-SOIC
48-Pin SSOP
48
2
47
VCC
NC
3
46
HSB
A12
A7
4
5
45
44
A6
A5
6
43
7
42
W
A13
A8
A9
NC
A4
8
41
NC
9
40
A11
NC
10
39
NC
NC
NC
VSS
11
38
NC
37
13
36
NC
NC
DQ0
14
35
NC
VSS
NC
15
34
16
33
A3
A2
17
32
18
31
G
A10
A1
19
30
E
A0
DQ1
DQ2
20
29
21
28
22
23
27
24
25
DQ7
DQ5
DQ4
DQ3
VCC
I/O
E
Input
W
Input
VCC
HSB
30
4
A6
A5
5
29
28
6
27
W
A13
A8
A9
A4
A3
7
26
A11
25
NC
A2
9
24
G
NC
8
TOP
23
A10
11
22
12
21
E
DQ7
DQ0
DQ1
13
20
DQ6
14
19
DQ5
DQ2
VSS
15
18
16
17
DQ4
DQ3
10
D
ew
rN
fo
d
Description
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
ot
Input
N
G
3
Relative PCB Area Usage[1]
om
Input
A12
A7
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Write Enable: The active low W enables data on the DQ pins to be written to the address location
latched by the falling edge of E
R
A14-A0
DQ7-DQ0
HSB
ec
I/O
NC
DQ6
m
Pin Descriptions
Pin Name
VCC
31
SSOP
26
32
2
A1
A0
de
TOP
1
A14
en
NC
NC
12
VCAP
ig
ns
1
NC
A14
es
VCAP
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
Power Supply Power: 3.0V, +20%, -10%
I/O
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this pin
high if not connected. (Connection Optional).
VCAP
Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
VSS
Power Supply Ground
NC
No Connect
Unlabeled pins have no internal connections.
Note
1. See “Package Diagrams” on page 16 for detailed package size specifications.
Document Number: 001-52037 Rev. *A
Page 3 of 18
[+] Feedback
STK14D88
Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Note: Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Voltage on Input Relative to VSS ...........–0.6V to (VCC + 0.5V)
Voltage on DQ0-7 or HSB ......................–0.5V to (VCC + 0.5V)
Temperature under Bias ............................... –55°C to 125°C
Storage Temperature .................................... –65°C to 140°C
Power Dissipation............................................................. 1W
ig
ns
DC Output Current (1 output at a time, 1s duration).... 15 mA
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS
es
θjc 5.4 C/W; θja 44.3 [0 fpm], 37.9 [200 fpm], 35.1 C/W [500 fpm].
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS
D
θjc 6.2 C/W; θja 51.1 [0 fpm], 44.7 [200 fpm], 41.8 C/W [500 fpm].
ew
DC Characteristics
(VCC = 2.7V-3.6V)
Commercial
Parameter[2]
Min
Industrial
rN
Symbol
Max
Min
Max
Unit
Notes
mA
mA
mA
tAVAV = 25 ns
tAVAV = 35 ns
tAVAV = 45 ns
Dependent on output loading and
cycle rate. Values obtained without
output loads.
3
mA
All Inputs Don’t Care, VCC = max
Average current for duration of
STORE cycle (tSTORE)
10
10
mA
W ≥ (V CC – 0.2V)
All Others Cycling, CMOS Levels
Dependent on output loading and
cycle rate. Values obtained without
output loads.
3
3
mA
All Inputs Don’t Care
Average current for duration of
STORE cycle (tSTORE)
VCC Standby Current
(Standby, Stable CMOS Input
Levels)
3
3
mA
E ≥ (V CC – 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
Standby current level after nonvolatile
cycle complete
IILK
Input Leakage Current
±1
±1
μA
VCC = max
VIN = VSS to VCC
IOLK
Off State Output Leakage Current
±1
±1
μA
VCC = max
VIN = VSS to VCC, E or G ≥ VIH
VIH
Input Logic “1” Voltage
2.0
VCC + .5
2.0
VCC + .5
V
All Inputs
VSS – .5
0.8
VSS – .5
0.8
65
55
50
ICC2
Average VCC Current during
STORE
ICC3
Average VCC Current at tAVAV =
200ns
3V, 25°C, Typical
ICC4
Average VCAP Current during
AutoStore Cycle
ISB
de
d
Average VCC Current
fo
70
60
55
ICC1
N
ot
R
ec
om
m
en
3
VIL
Input Logic “0” Voltage
VOH
Output Logic “1” Voltage
VOL
Output Logic “0” Voltage
2.4
2.4
0.4
0.4
V
All Inputs
V
IOUT = – 2 mA
V
IOUT = 4 mA
Note:
2. The HSB pin has IOUT=-10uA for VOH of 2.4V, this parameter is characterized but not tested
Document Number: 001-52037 Rev. *A
Page 4 of 18
[+] Feedback
STK14D88
DC Characteristics (continued)
(VCC = 2.7V-3.6V)
Commercial
Parameter[2]
Symbol
TA
Operating Temperature
Industrial
Min
Max
Min
Max
0
70
- 40
85
Unit
Notes
°C
VCC
Operating Voltage
2.7
3.6
2.7
3.6
V
3.3V +20%, -10%
VCAP
Storage Capacitance
17
120
17
120
μF
Between VCAP pin and VSS, 5V Rated
DATAR
Data Retention
20
20
NVC
Nonvolatile STORE Operations
200
200
K
ig
ns
Years At 55°C
es
AC Test Conditions
ew
D
Input Pulse Levels .................................................... 0V to 3V
Input Rise and Fall Times ............................................ <5 ns
Input and Output Timing Reference Levels .................... 1.5V
Output Load.................................. See Figure 2 and Figure 3
Figure 2. AC Output Loading
rN
3.0V
fo
577Ω
d
OUTPUT
30 pF
INCLUDING
SCOPE AND
FIXTURE
m
en
de
789Ω
om
Figure 3. AC Output Loading for Tri-state Specs (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ
577Ω
OUTPUT
789Ω
N
ot
R
ec
3.0V
5 pF
INCLUDING
SCOPE AND
FIXTURE
Capacitance
Parameter[3]
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Max
Unit
Conditions
7
pF
ΔV = 0 to 3V
7
pF
ΔV = 0 to 3V
Note
3. These parameters are guaranteed but not tested.
Document Number: 001-52037 Rev. *A
Page 5 of 18
[+] Feedback
STK14D88
SRAM READ Cycles #1 and #2
NO.
Symbols
#1
#2
1
tELQV
STK14D88-25 STK14D88-35 STK14D88-45
Parameter
Alt.
Min
Max
Min
tACS
Chip Enable Access Time
[4]
tRC
Read Cycle Time
tAVQV[5]
tAA
Address Access Time
25
tGLQV
tOE
Output Enable to Data Valid
12
tAXQX[5]
tOH
Output Hold after Address Change
3
3
6
tELQX
tLZ
Address Change or Chip Enable to
Output Active
3
3
7
tEHQZ[6]
tHZ
Address Change or Chip Disable to
Output Inactive
8
tGLQX
tOLZ
Output Enable to Output Active
9
tGHQZ[6]
tELICCH[3]
tEHICCL[3]
tOHZ
Output Disable to Output Inactive
tPA
Chip Enable to Power Active
tPS
Chip Disable to Power Standby
10
0
35
45
ns
15
20
ns
45
ns
ig
ns
3
ns
3
13
0
10
0
ns
35
10
0
ns
15
0
13
35
ns
ns
15
ns
45
ns
0
25
Unit
ns
rN
11
25
Max
45
es
5
tAXQX[5]
Min
35
D
4
tELEH
25
ew
2
3
tAVAV[4]
tAVQV[5]
Max
fo
Figure 4. SRAM READ Cycle 1: Address Controlled [4, 5, 6]
2
tAVAV
d
ADDRESS
DATA VALID
m
en
DQ (DATA OUT)
3
tAVQV
de
5
tAXQX
2
29
1
11
6
R
ec
om
Figure 5. SRAM READ Cycle 2: E Controlled [4, 7]
ot
7
N
3
9
4
8
10
Notes
4. W must be high during SRAM READ cycles.
5. Device is continuously selected with E and G both low.
6. Measured ± 200 mV from steady state output voltage.
7. HSB must remain high during READ and WRITE cycles.
Document Number: 001-52037 Rev. *A
Page 6 of 18
[+] Feedback
STK14D88
SRAM WRITE Cycle #1 and #2
tWLQZ[6, 8]
tWHQX
Alt.
tWC
tWP
tCW
tDW
tDH
tAW
tAS
tWR
tWZ
tOW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ig
ns
#1
tAVAV
tWLWH
tELWH
tDVWH
tWHDX
tAVWH
tAVWL
tWHAX
STK14D88-25 STK14D88-35 STK14D88-45
Unit
Min
Max
Min
Max
Min
Max
25
35
45
ns
20
25
30
ns
20
25
30
ns
10
12
15
ns
0
0
0
ns
20
25
30
ns
0
0
0
ns
0
0
0
ns
10
13
15
ns
3
3
3
ns
Parameter
D
12
13
14
15
16
17
18
19
20
21
Symbols
#2
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
es
NO.
ew
Figure 6. SRAM WRITE Cycle 1: W Controlled [8, 9]
12
tAVAV
rN
ADDRESS
14
tELWH
fo
E
tAVWL
de
13
tWLWH
d
17
tAVWH
18
en
W
DATA IN
15
tDVWH
13
tWHDX
DATA VALID
m
20
tWLQZ
DATA OUT
19
tWHAX
21
tWHQX
HIGH IMPEDANCE
ec
om
PREVIOUS DATA
Figure 7. SRAM WRITE Cycle 2: E Controlled [8, 9]
R
ot
ADDRESS
12
tAVAV
18
tAVEL
14
tELEH
19
tEHAX
N
E
17
tAVEH
13
tWLEH
W
15
tDVEH
DATA IN
DATA OUT
16
tEHDX
DATA VALID
HIGH IMPEDANCE
Notes
8. If W is low when E goes low, the outputs remain in the high-impedance state.
9. E or W must be ≥ VIH during address transitions.
Document Number: 001-52037 Rev. *A
Page 7 of 18
[+] Feedback
STK14D88
AutoStore/POWER UP RECALL
Symbols
Alt.
22 tRECALL
23 tSTORE
STK14D88
Parameter
Unit
Notes
20
ms
10
STORE Cycle Duration
12.5
ms
11, 12
Low Voltage Trigger Level
2.65
V
Min
Max
Power up RECALL Duration
tHLHZ
24 VSWITCH
25 VCCRISE
Vcc Rise Time
μs
150
ig
ns
No.
d
fo
rN
ew
D
es
Figure 8. AutoStore /POWER UP RECALL
23
23
22
N
ot
R
ec
om
22
m
en
de
22
Note: Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH
Notes
10. tHRECALL starts from the time VCC rises above VSWITCH.
11. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
12. Industrial Grade Devices require 15 ms Max.
Document Number: 001-52037 Rev. *A
Page 8 of 18
[+] Feedback
STK14D88
Software-Controlled STORE/RECALL Cycle[13, 14]
Symbols
No.
E Cont
STK14D88-25 STK14D88-35 STK14D88-45
Parameter
Alternate
Min
Max
Min
Max
Min
Max
Unit Notes
26 tAVAV
27 tAVEL
tRC
STORE/RECALL Initiation Cycle Time
25
35
45
ns
tAS
Address Setup Time
0
0
0
ns
28 tELEH
29 tEHAX
tCW
Clock Pulse Width
20
25
30
ns
Address Hold Time
1
1
1
ns
RECALL Duration
50
50
50
ig
ns
30 tRECALL
14
μs
26
tAVAV
ADDRESS
tAVAV
27
tAVEL
ADDRESS #6
ew
ADDRESS #1
D
26
es
Figure 9. E and G Controlled Software STORE/RECALL Cycle[14]
28
tELEH
fo
rN
E
29
DQ (DATA
23
tSTORE
DATA VALID
30
/ tRECALL
HIGH IMPEDANCE
N
ot
R
ec
om
m
en
DATA VALID
de
d
tELAX
Notes
13. The software sequence is clocked on the falling edge of E controlled READs.
14. The six consecutive addresses must be read in the order listed in the software STORE/RECALL Mode Selection Table. W must be high during all six consecutive cycles
Document Number: 001-52037 Rev. *A
Page 9 of 18
[+] Feedback
STK14D88
Hardware STORE Cycle
NO.
Symbols
Standard
31
tDELAY
32
tHLHX
tHLQZ
STK14D88
Parameter
Alternate
Min
Max
Hardware STORE to SRAM Disabled
1
70
Hardware STORE Pulse Width
15
Unit
Notes
µs
15
ns
Figure 10. Hardware STORE Cycle
es
ig
ns
32
ew
D
23
de
d
fo
rN
31
Symbols
Parameter
Standard
tSS
m
NO.
STK14D88
Min
Soft Sequence Processing Time
Max
70
Unit
Notes
µs
16, 17
om
33
en
Soft Sequence Commands
33
33
N
ot
R
ec
Figure 11. Software Sequence Commands
Notes
15. Read and Write cycles in progress before HSB is asserted are given this minimum amount of time to complete.
16. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
17. Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
Document Number: 001-52037 Rev. *A
Page 10 of 18
[+] Feedback
STK14D88
Mode Selection
W
G
A14–A0
Mode
IO
Power
X
X
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x03F8
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x07F0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
0x0FC0
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
18, 19, 20
18, 19, 20
es
ICC2
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
fo
Notes
D
ew
Output High Z
rN
Nonvolatile Store
d
L
Active
de
H
Active
Output Data
Output Data
Output Data
Output Data
Output Data
18, 19, 20
18, 19, 20
N
ot
R
ec
om
m
en
L
ig
ns
E
H
Notes
18. The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
19. While there are 15 addresses on the STK14D88, only the lower 14 are used to control software modes
20. I/O state depends on the state of G. The I/O table shown assumes G low.
Document Number: 001-52037 Rev. *A
Page 11 of 18
[+] Feedback
STK14D88
nvSRAM Operation
VCAP pin is driven to 5V by a charge pump internal to the chip. A
pull up should be placed on W to hold it inactive during power up.
nvSRAM
To reduce unneeded nonvolatile stores, AutoStore and
Hardware Store operations will be ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. The HSB signal can be monitored by the system to detect
an AutoStore cycle is in progress.
The STK14D88 nvSRAM is made up of two functional components paired in the same physical cell. These are the SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates like a standard fast static RAM. Data in the
SRAM can be transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture allows all cells to be stored
and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The
STK14D88 supports unlimited read and writes like a typical
SRAM. In addition, it provides unlimited RECALL operations
from the nonvolatile cells and up to 200K STORE operations.
0.1µF
10k Ohm
fo
rN
ew
W
VCC
d
The STK14D88 performs a READ cycle whenever E and G are
low while W and HSB are high. The address specified on pins
A0-16 determine which of the 32,768 data bytes will be accessed.
When the READ is initiated by an address transition, the outputs
will be valid after a delay of tAVQV (READ cycle #1). If the READ
is initiated by E and G, the outputs will be valid at tELQV or at
tGLQV, whichever is later (READ cycle #2). The data outputs
repeatedly respond to address changes within the tAVQV access
time without the need for transitions on any control input pins,
and remain valid until another address change or until either E
or G is brought high, or W or HSB is brought low.
D
SRAM READ
VCC
es
VCAP
VCAP
ig
ns
Figure 12. AutoStore Mode
Hardware STORE (HSB) Operation
de
SRAM WRITE
om
m
en
A WRITE cycle is performed whenever E and W are low and HSB
is high. The address inputs must be stable prior to entering the
WRITE cycle and must remain stable until either E or W goes
high at the end of the cycle. The data on the common I/O pins
DQ0-7 will be written into memory if it is valid tDVWH before the
end of a W controlled WRITE or tDVEH before the end of an E
controlled WRITE.
R
ec
It is recommended that G be kept high during the entire WRITE
cycle to avoid data bus contention on common I/O lines. If G is
left low, internal circuitry will turn off the output buffers tWLQZ after
W goes low.
AutoStore Operation
N
ot
The STK14D88 stores data to nvSRAM using one of three
storage operations. These three operations are Hardware Store
(activated by HSB), Software Store (activated by an address
sequence), and AutoStore (on power down).
AutoStore operation is a unique feature of Cypress Quantum
Trap technology is enabled by default on the STK14D88.
During normal operation, the device will draw current from VCC
to charge a capacitor connected to the VCAP pin. This stored
charge will be used by the chip to perform a single STORE
operation. If the voltage on the VCC pin drops below VSWITCH,
the part will automatically disconnect the VCAP pin from VCC. A
STORE operation will be initiated with power provided by the
VCAP capacitor.
Figure 12 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to the DC CHARACTERISTICS table for the size of the capacitor. The voltage on the
Document Number: 001-52037 Rev. *A
The STK14D88 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin can be
used to request a hardware STORE cycle. When the HSB pin is
driven low, the STK14D88 will conditionally initiate a STORE
operation after tDELAY. An actual STORE cycle will only begin if
a WRITE to the SRAM took place since the last STORE or
RECALL cycle. The HSB pin has a very resistive pull up and is
internally driven low to indicate a busy condition while the
STORE (initiated by any means) is in progress. This pin should
be externally pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations that are in progress when
HSB is driven low by any means are given time to complete
before the STORE operation is initiated. After HSB goes low, the
STK14D88 continues SRAM operations for tDELAY. During
tDELAY, multiple SRAM READ operations may take place. If a
WRITE is in progress when HSB is pulled low, it will be allowed
a time, tDELAY, to complete. However, any SRAM WRITE cycles
requested after HSB goes low will be inhibited until HSB returns
high.
If HSB is not used, it should be left unconnected.
Software STORE
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The STK14D88
software STORE cycle is initiated by executing sequential E
controlled READ cycles from six specific address locations in
exact order. During the STORE cycle, previous data is erased
and then the new data is programmed into the nonvolatile
elements. Once a STORE cycle is initiated, further memory
inputs and outputs are disabled until the cycle is completed.
Page 12 of 18
[+] Feedback
STK14D88
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on, should always program a unique
NV pattern (for example, a complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state (such as AutoStore enabled). While the
nvSRAM is shipped in a preset state, best practice is to rewrite
the nvSRAM into the desired state as a safeguard against
events that might flip the bit inadvertently (such as program
bugs, incoming inspection routines, and others).
■
If AutoStore has been firmware disabled, it will not reset to
“autostore enabled” on every power down event captured by
the nvSRAM. The application firmware should re-enable or
re-disable AutoStore on each reset sequence based on the
behavior desired.
es
After the sixth address in the sequence has been entered, the
STORE cycle begins and the chip is disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence.
After the tSTORE cycle time has been fulfilled, the SRAM is again
activated for READ and WRITE operation.
■
rN
d
de
m
om
Data Protection
R
ec
The STK14D88 protects data from corruption during low-voltage
conditions by inhibiting all externally initiated STORE and
WRITE operations. The low-voltage condition is detected when
VCC<VSWITCH.
ot
If the STK14D88 is in a WRITE mode (both E and W low) at
power up, after a RECALL, or after a STORE, the WRITE will be
inhibited until a negative transition on E or W is detected. This
protects against inadvertent writes during power up or brown out
conditions.
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the max VCAP value because the
nvSRAM internal algorithm calculates VCAP charge time based
on this max VCAP value. Customers who want to use a larger
VCAP value to make sure there is extra store charge and store
time should discuss their VCAP size selection with Cypress to
understand any impact on the VCAP voltage level at the end of
a tRECALL period.
fo
■
en
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the
SRAM will once again be ready for READ or WRITE operations.
The RECALL operation in no way alters the data in the nonvolatile storage elements.
ew
D
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of E controlled READ
operations must be performed:
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x0C63, Initiate RECALL Cycle
ig
ns
To initiate the software STORE cycle, the following READ
sequence must be performed:
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x0FC0, Initiate STORE Cycle
Low Average Active Power
CMOS technology provides the STK14D88 with the benefit of
power supply current that scales with cycle time. Less current will
be drawn as the memory cycle time becomes longer than 50 ns.
Figure 13 shows the relationship between ICC and
READ/WRITE cycle time. Worst-case current consumption is
shown for commercial temperature range, VCC = 3.6V, and chip
enable at maximum frequency. Only standby current is drawn
when the chip is disabled. The overall average current drawn by
the STK14D88 depends on the following items:
The duty cycle of chip enable
■
The overall cycle rate for operations
Best Practices
■
The ratio of READs to WRITEs
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The operating temperature
■
The VCC level
■
I/O loading
N
■
Document Number: 001-52037 Rev. *A
Page 13 of 18
[+] Feedback
STK14D88
Preventing AutoStore
The AutoStore function can be disabled by initiating an
AutoStore Disable sequence. A sequence of READ operations
is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following
sequence of E controlled or G controlled READ operations must
be performed:
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x03F8, AutoStore Disable
50
40
20
Writes
10
Reads
ig
ns
30
100 150 200 300
Cycle Time (ns)
The AutoStore can be re-enabled by initiating an AutoStore
Enable sequence. A sequence of READ operations is performed
in a manner similar to the software RECALL initiation. To initiate
the AutoStore Enable sequence, the following sequence of E
controlled or G controlled READ operations must be performed:
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x07F0, AutoStore Enable
D
50
es
0
ew
Average Active Current (mA)
Figure 13. Current versus Cycle Time
fo
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) needs to be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore enabled.
In all cases, make sure the READ sequence is uninterrupted. For
example, an interrupt that occurs in the sequence that reads the
nvSRAM would abort this sequence, resulting in an error.
N
ot
R
ec
om
m
en
de
d
The STK14D88 is a high speed memory and so must have a high
frequency bypass capacitor of 0.1 µF connected between both
VCC pins and VSS ground plane with no plane break to chip VSS.
Use leads and traces that are as short as possible. As with all
high speed CMOS ICs, careful routing of power, ground, and
signals will reduce circuit noise.
rN
Noise Considerations
Document Number: 001-52037 Rev. *A
Page 14 of 18
[+] Feedback
STK14D88
Part Numbering Nomenclature
STK14D88 - R F 45 I TR
Packaging Option:
TR = Tape and Reel
Blank = Tube
ig
ns
Temperature Range:
Blank - Commercial (0 to 70°C)
I - Industrial (-40 to 85°C)
es
Lead Finish
Speed:
25 - 25 ns
35 - 35 ns
45 - 45 ns
D
F = 100% Sn (Matte Tin) ROHS Compliant
rN
ew
Package:
N = Plastic 32-pin 300 mil SOIC (50 mil pitch)
R = Plastic 48-pin 300 mil SSOP(25 mil pitch)
Ordering Codes
Description
d
Part Number
fo
These parts are not recommended for new designs.
3V 32Kx8 AutoStore nvSRAM SOP32-300
STK14D88-NF35
STK14D88-NF45
STK14D88-NF25TR
STK14D88-NF35TR
Access Times
Temperature
25 ns
Commercial
3V 32Kx8 AutoStore nvSRAM SOP32-300
35 ns
Commercial
3V 32Kx8 AutoStore nvSRAM SOP32-300
45 ns
Commercial
3V 32Kx8 AutoStore nvSRAM SOP32-300
25 ns
Commercial
3V 32Kx8 AutoStore nvSRAM SOP32-300
35 ns
Commercial
m
en
de
STK14D88-NF25
3V 32Kx8 AutoStore nvSRAM SOP32-300
45 ns
Commercial
STK14D88-RF25
3V 32Kx8 AutoStore nvSRAM SSOP48-300
25 ns
Commercial
STK14D88-RF35
3V 32Kx8 AutoStore nvSRAM SSOP48-300
35 ns
Commercial
STK14D88-RF45
3V 32Kx8 AutoStore nvSRAM SSOP48-300
45 ns
Commercial
3V 32Kx8 AutoStore nvSRAM SSOP48-300
25 ns
Commercial
35 ns
Commercial
ec
om
STK14D88-NF45TR
STK14D88-RF35TR
R
STK14D88-RF25TR
3V 32Kx8 AutoStore nvSRAM SSOP48-300
3V 32Kx8 AutoStore nvSRAM SSOP48-300
45 ns
Commercial
STK14D88-NF25I
3V 32Kx8 AutoStore nvSRAM SOP32-300
25 ns
Industrial
STK14D88-NF35I
3V 32Kx8 AutoStore nvSRAM SOP32-300
35 ns
Industrial
STK14D88-NF45I
3V 32Kx8 AutoStore nvSRAM SOP32-300
45 ns
Industrial
STK14D88-NF25ITR
3V 32Kx8 AutoStore nvSRAM SOP32-300
25 ns
Industrial
STK14D88-NF35ITR
3V 32Kx8 AutoStore nvSRAM SOP32-300
35 ns
Industrial
STK14D88-NF45ITR
3V 32Kx8 AutoStore nvSRAM SOP32-300
45 ns
Industrial
STK14D88-RF25I
3V 32Kx8 AutoStore nvSRAM SSOP48-300
25 ns
Industrial
STK14D88-RF35I
3V 32Kx8 AutoStore nvSRAM SSOP48-300
35 ns
Industrial
STK14D88-RF45I
3V 32Kx8 AutoStore nvSRAM SSOP48-300
45 ns
Industrial
STK14D88-RF25ITR
3V 32Kx8 AutoStore nvSRAM SSOP48-300
25 ns
Industrial
STK14D88-RF35ITR
3V 32Kx8 AutoStore nvSRAM SSOP48-300
35 ns
Industrial
STK14D88-RF45ITR
3V 32Kx8 AutoStore nvSRAM SSOP48-300
45 ns
Industrial
N
ot
STK14D88-RF45TR
Document Number: 001-52037 Rev. *A
Page 15 of 18
[+] Feedback
STK14D88
Package Diagrams
Figure 14. 32-Pin (300 Mil) SOIC (51-85127)
PIN 1 ID
16
1
ig
ns
REFERENCE JEDEC MO-119
es
0.405[10.287]
0.419[10.642]
32
D
17
MIN.
MAX.
DIMENSIONS IN INCHES[MM]
0.292[7.416]
0.299[7.594]
PART #
S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.
ew
SEATING PLANE
fo
0.090[2.286]
0.100[2.540]
rN
0.810[20.574]
0.822[20.878]
0.004[0.101]
0.050[1.270]
TYP.
0.026[0.660]
0.032[0.812]
d
0.004[0.101]
0.0100[0.254]
0.006[0.152]
0.012[0.304]
51-85127 *B
N
ot
R
ec
om
m
en
de
0.014[0.355]
0.020[0.508]
0.021[0.533]
0.041[1.041]
Document Number: 001-52037 Rev. *A
Page 16 of 18
[+] Feedback
STK14D88
Package Diagrams (continued)
51-85061-*C
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
ns
Figure 15. 48-Pin (300 Mil) SSOP (51-85061)
Document Number: 001-52037 Rev. *A
Page 17 of 18
[+] Feedback
STK14D88
Document History Page
Document Title: STK14D88 32Kx8 AutoStore nvSRAM
Document Number: 001-52037
Orig. of Submission
Change
Date
ECN
Description of Change
**
2668632
GVCH
03/04/2009 New data sheet
*A
2821358
GVCH
12/04/2009 Added Note in Ordering Information mentioning that these parts are not recommended for new designs.
Added “Not recommended for New Designs” watermark in the PDF.
Added Contents on page 2.
ig
ns
Revision
Sales, Solutions, and Legal Information
es
Worldwide Sales and Design Support
D
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
PSoC
ew
Products
psoc.cypress.com
Wireless
wireless.cypress.com
Memories
memory.cypress.com
image.cypress.com
ot
R
ec
om
m
en
de
d
Image Sensors
rN
clocks.cypress.com
fo
Clocks & Buffers
N
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-52037 Rev. *A
Revised December 01, 2009
Page 18 of 18
All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback