Agilent Technologies DisplayPort Technical data

Agilent U7232A
DisplayPort Electrical
Performance
Compliance Test
Application
Method of Implementation
s
Agilent Technologies
Notices
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U7232-97004
Edition
Fifth edition, March 2009
Printed in USA
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DisplayPort Automated Testing—At A Glance
The Agilent U7232A DisplayPort Electrical Performance Compliance Test
Application helps you verify DisplayPort Source device under test (DUT)
compliance to DisplayPort specifications using an Agilent 8 GHz or greater
Infiniium digital storage oscilloscope. The DisplayPort Electrical
Performance Compliance Test Application:
• Lets you select individual or multiple tests to run.
• Lets you identify the device being tested and its configuration.
• Shows you how to make oscilloscope connections to the device under
test.
• Automatically checks for proper oscilloscope configuration.
• Automatically sets up the oscilloscope for each test.
• Provides detailed information for each test that has been run and lets
you specify the thresholds at which marginal or critical warnings
appear.
• Creates a printable HTML report of the tests that have been run.
NOTE
The tests performed by the DisplayPort Electrical Performance Compliance Test Application
are intended to provide a quick check of the electrical health of the DUT. This testing is not
a replacement for an exhaustive test validation plan.
Compliance testing measurements are described in Section 3, Source
Compliance Tests, in the DisplayPort- Compliance Test Specification
Version 1.1 document, which complies to the DisplayPort Standard 1.1a.
For more information, see the VESA web site at www.vesa.org.
Required Equipment and Software
In order to run the DisplayPort automated tests, you need the following
equipment and software:
• Version 05.60 or later of Infiniium software (54854A, 54855A and 80000
series Infiniium Digital Storage Oscilloscope) OR
• Version 1.31 or greater of baseline software (90000A series Infiniium
Digital Storage Oscilloscope).
• 8 GHz or greater Infiniium Oscilloscope. Option 001 (1 M/ch memory
upgrade) is required.
• U7232A DisplayPort Electrical Performance Compliance Test Application
version 2.01.
• W2641A DisplayPort Test Point Adapter fixture. Includes four SMA to
SMP cables.
• Keyboard, qty = 1, (provided with the Agilent Infiniium oscilloscope).
• Mouse, qty = 1, (provided with the Agilent Infiniium oscilloscope).
U7232A DisplayPort Electrical Performance Compliance Test Application
3
• Precision 3.5 mm BNC to SMA male adapter, Agilent p/n 54855- 67604,
qty = 2 (provided with the Agilent Infiniium oscilloscope).
• Calibration cable (provided with the Infiniium oscilloscopes). Use a
good quality 50 Ω BNC cable for calibrating the oscilloscope.
• E2655A/B probe de- skew fixture.
• 1168A or 1169A probes and N5380A SMA probe head.
• U7232A DisplayPort Electrical Performance Compliance Test Application
license.
• N5400A EZJIT Plus Jitter Analysis software license.
In order to run the DisplayPort source automated tests, you need the
following additional hardware:
• W2642A DisplayPort Test Controller (DPTC).
• Quantum Data DisplayPort Adapter.
4
U7232A DisplayPort Electrical Performance Compliance Test Application
In This Book
This manual describes the tests that are performed by the DisplayPort
Electrical Performance Compliance Test Application in more detail; it
contains information from (and refers to) the DisplayPort Specification
Version 1.1, and it describes how the tests are performed.
• Chapter 1, “Installing the DisplayPort Electrical Performance
Compliance Test Application shows how to install and license the
automated test application (if it was purchased separately).
• Chapter 2, “Preparing to Take Measurements shows how to start the
DisplayPort Electrical Performance Compliance Test Application and
gives a brief overview of how it is used.
• Chapter 3, “Source Eye Diagram Differential Tests shows the probing
and test procedure of the source data eye diagram differential tests.
• Chapter 4, “Source Total Jitter Differential Tests shows the probing and
test procedure of the source total jitter differential tests.
• Chapter 5, “Source Non- ISI Jitter Differential Tests shows the probing
and test procedure of the source non- isi jitter differential tests.
• Chapter 6, “Source Transition Time Differential Tests (Informative)
describes the source rise time and fall time differential tests. These are
informative tests.
• Chapter 7, “Source Non Pre- Emphasis Level Differential Tests describes
the source non Pre- Emphasis level differential tests.
• Chapter 8, “Source Overshoot Differential Tests (Informative) shows the
probing and test procedure of the source overshoot differential tests.
These are informative tests.
• Chapter 9, “Source Pre- Emphasis Level Differential Tests (Normative &
Informative) shows the probing and test procedure of the source
pre- Emphasis differential tests. The Pre- Emphasis Level tests are
normative tests whereas Non- Transition Voltage Range Measurements
are informative tests.
• Chapter 10, “Source Inter Pair Skew Differential Tests shows the
probing and test procedure of the source inter pair skew differential
tests.
• Chapter 11, “Source Unit Interval Differential Tests (Informative)
describes the source unit interval differential tests. These are
informative tests.
• Chapter 12, “Source Main Link Frequency Compliance Differential Tests
shows the probing and test procedure of the source main link frequency
compliance differential tests.
• Chapter 13, “Source Spread Spectrum Clocking (SSC) Differential Tests
(Normative & Informative) describes the source spread spectrum
clocking (SSC) differential tests. In this SSC test, the Modulation
U7232A DisplayPort Electrical Performance Compliance Test Application
5
Frequency and Modulation Deviation tests are normative tests whereas
Deviation HF Variation tests are informative tests.
• Chapter 14, “Source Rise- Fall Mismatch Single- Ended Tests
(Informative) shows the probing and test procedure of the source rise
and fall mismatch single- ended tests.
• Chapter 15, “Source Intra Pair Skew Single- Ended Tests shows the
probing and test procedure of the source intra pair skew single- ended
tests.
• Chapter 16, “Source AC Common Mode Noise Single- Ended Tests shows
the probing and test procedure of the source AC common mode noise
single- ended tests.
• Chapter 17, “Link Layer Protocol Tests describes the link layer protocol
tests.
• Chapter 18, “Sink Eye Diagram Tests shows the probing and test
procedure of the sink eye diagram tests.
• Chapter 19, “Sink Total Jitter Tests contains more information on the
sink total jitter tests.
• Chapter 20, “Sink Non- ISI Jitter Tests shows the probing and test
procedure of the sink non- isi jitter tests.
• Chapter 21, “Cable Eye Diagram Tests shows the probing and test
procedure of the cable eye diagram tests.
• Chapter 22, “Cable Total Jitter Tests contains more information on the
cable total jitter tests.
• Chapter 23, “Cable Non- ISI Jitter Tests contains more information on
the cable non- isi jitter tests.
• Chapter 24, “Calibrating the Infiniium Oscilloscope and Probe describes
how to calibrate the oscilloscope in preparation for running the
DisplayPort automated tests.
• Chapter 25, “InfiniiMax Probing describes the 1168A/1169A probe
amplifier and probe head recommendations for DisplayPort testing.
• Appendix A, “DisplayPort Source Automated Test with W2642A DPTC
describes the implementation of test automation features architect in
the DisplayPort Standard Version 1.1a using Agilent W2642A
DisplayPort Test Controller (DPTC).
6
U7232A DisplayPort Electrical Performance Compliance Test Application
See Also
• The DisplayPort Electrical Performance Compliance Test Application’s
online help, which describes:
• Starting the tests.
• Creating or opening a test project.
• Setting up the DisplayPort test environment.
• Setting up the source automated tests with W2642A DPTC.
• Selecting tests.
• Configuring selected tests.
• Connecting the oscilloscope to the DUT.
• Running the tests.
• Viewing the test results.
• Viewing/printing the HTML test report.
• Saving test projects.
• Understanding the HTML report.
U7232A DisplayPort Electrical Performance Compliance Test Application
7
8
U7232A DisplayPort Electrical Performance Compliance Test Application
Contents
DisplayPort Automated Testing—At A Glance
Required Equipment and Software 3
In This Book
See Also
3
5
7
1 Installing the DisplayPort Electrical Performance Compliance Test Application
Installing the Software
16
Installing the License Key
17
2 Preparing to Take Measurements
W2641A DisplayPort Test Point Adapter Fixture
Acquiring the Test Fixture 20
W2641A Test Fixture Description 20
Calibrating the Oscilloscope
20
21
Starting the DisplayPort Electrical Performance Compliance Test Application
Online Help Topics
22
24
3 Source Eye Diagram Differential Tests
Probing for Source Data Eye Diagram Differential Tests
Source Eye Diagram Differential Tests
Test Procedure 28
Test Condition 33
PASS Condition 34
Test References 35
26
28
4 Source Total Jitter Differential Tests
Probing for Source Total Jitter Differential Tests
Source Total Jitter Differential Tests
Test Procedure 40
Test Condition 43
PASS Condition 44
Test References 44
38
40
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
9
5 Source Non-ISI Jitter Differential Tests
Probing for Source Non-ISI Jitter Differential Tests
Source Non-ISI Jitter Differential Tests
Test Procedure 48
Test Condition 51
PASS Condition 52
Test References 52
46
48
6 Source Transition Time Differential Tests (Informative)
Probing for Source Transition Time Differential Tests
Source Transition Time Differential Tests
Test Procedure 56
Test Condition 59
PASS Condition 59
Test References 60
54
56
7 Source Non Pre-Emphasis Level Differential Tests
Probing for Source Non Pre-Emphasis Level Differential Tests
Source Non Pre-Emphasis Level Test
Test Procedure 64
Test Condition 67
PASS Condition 67
Test References 68
62
64
8 Source Overshoot Differential Tests (Informative)
Probing for Source Overshoot Differential Tests
Source Overshoot Differential Tests
Test Procedure 72
Test Condition 75
PASS Condition 75
Test References 75
70
72
9 Source Pre-Emphasis Level Differential Tests (Normative & Informative)
Probing for Source Pre-Emphasis Level Differential Tests
10
78
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Pre-Emphasis Level Differential Tests
Test Procedure 80
Test Condition 84
PASS Condition 85
Test References 85
80
10 Source Inter Pair Skew Differential Tests
Probing for Source Inter Pair Skew Differential Tests
Source Inter Pair Skew Differential Test
Test Procedure 90
Test Condition 93
PASS Condition 93
Test References 94
88
90
11 Source Unit Interval Differential Tests (Informative)
Probing for Source Unit Interval Differential Tests
Source Unit Interval Differential Tests
Test Procedure 98
Test Condition 101
PASS Condition 101
Test References 102
96
98
12 Source Main Link Frequency Compliance Differential Tests
Probing for Source Main Link Frequency Compliance Differential Tests
Source Main Link Frequency Compliance Differential Tests
Test Procedure 106
Test Condition 109
PASS Condition 109
Test References 109
104
106
13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative)
Probing for Source Spread Spectrum Clocking (SSC) Differential Tests
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
112
11
Source Spread Spectrum Clocking (SSC) Differential Test 114
Spread Spectrum Modulation Frequency (Normative) 114
Spread Spectrum Modulation Deviation (Normative) 114
Deviation HF Variation (Informative) 114
Test Procedure 115
SSC Modulation Frequency Test Condition 118
SSC Modulation Deviation Test Condition 118
SSC Deviation HF Variation Test Condition 119
SSC Modulation Frequency PASS Condition 119
SSC Modulation Deviation PASS Condition 119
SSC Deviation HF Variation PASS Condition 119
Test References 120
14 Source Rise-Fall Mismatch Single-Ended Tests (Informative)
Probing for Source Rise-Fall Mismatch Single-Ended Tests
Source Rise-Fall Mismatch Single-Ended Tests
Test Procedure 123
Test Condition 126
PASS Condition 126
Test References 127
122
123
15 Source Intra Pair Skew Single-Ended Tests
Probing for Source Intra Pair Skew Single-Ended Tests
Source Intra Pair Skew Single-Ended Tests
Test Procedure 131
Test Condition 134
PASS Condition 134
Test References 134
130
131
16 Source AC Common Mode Noise Single-Ended Tests
Probing for Source AC Common Mode Noise Single-Ended Tests
Source AC Common Mode Noise Single-Ended Test
Test Procedure 139
Test Condition 142
PASS Condition 143
Test References 143
138
139
17 Link Layer Protocol Tests
Probing for Link Layer Protocol Tests
12
146
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Link Layer Protocol Tests 147
Link Layer Protocol - Pre-Emphasis 147
Link Layer Protocol - Level 147
Link Layer Protocol - Bit Rate 147
Test Procedure 148
Pre-Emphasis Test Condition 151
Level Test Condition 151
Bit Rate Test Condition 151
Pre-Emphasis PASS Condition 152
Level PASS Condition 152
Bit Rate PASS Condition 152
Test References 152
18 Sink Eye Diagram Tests
Probing for Sink Eye Diagram Tests
154
Sink Eye Diagram Tests 156
Test Procedure 156
PASS Condition 161
Test References 162
19 Sink Total Jitter Tests
Probing for Sink Total Jitter Tests
164
Sink Total Jitter Tests 166
Test Procedure 166
PASS Condition 171
Test References 171
20 Sink Non-ISI Jitter Tests
Probing for Sink Non-ISI Jitter Tests
174
Sink Non-ISI Jitter Tests 176
Test Procedure 176
PASS Condition 181
Test References 182
21 Cable Eye Diagram Tests
Probing for Cable Eye Diagram Tests
184
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
13
Cable Eye Diagram Tests 186
Test Procedure 186
PASS Condition 191
Test References 192
22 Cable Total Jitter Tests
Probing for Cable Total Jitter Tests
194
Cable Total Jitter Tests 196
Test Procedure 196
PASS Condition 201
Test References 201
23 Cable Non-ISI Jitter Tests
Probing for Cable Non-ISI Jitter Tests
Cable Non-ISI Jitter Tests
Test Procedure 206
PASS Condition 211
Test References 212
204
206
24 Calibrating the Infiniium Oscilloscope and Probe
Required Equipment for Calibration
Internal Calibration
214
215
Probe Calibration and De-skew 219
SMA probe head Atten/Offset Calibration 219
Differential Probe Head Skew Calibration 223
SMA Probe Head Atten/Offset Calibration 224
SMA Probe Head Skew Calibration 229
25 InfiniiMax Probing
A DisplayPort Source Automated Test with W2642A DPTC
Aux Channel and Hot Plug Detect (HPD)
DPTC Controller
234
235
Automated Test Sequence
OPTION 1 236
OPTION 2 241
236
Index
14
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
1
Installing the DisplayPort Electrical
Performance Compliance Test
Application
Installing the Software 16
Installing the License Key 17
If you purchased the U7232A DisplayPort Electrical Performance
Compliance Test Application version 2.01, you need to install the software
and license key.
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Agilent Technologies
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1
Installing the DisplayPort Electrical Performance Compliance Test Application
Installing the Software
1 Make sure you have version 05.60 or higher of the Infiniium
oscilloscope software or Version 1.31 or greater of baseline software by
choosing Help>About Infiniium... from the main menu.
2 To obtain the DisplayPort Electrical Performance Compliance Test
Application, go to Agilent website:
http://www.agilent.com/find/scope- apps- sw.
Figure 1
Agilent website for software Downloads
3 Search the list on this web page for the link to the U7232A DisplayPort
Electrical Performance Compliance Test Application. Click on it and
follow the instructions to download and install the application.
16
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Installing the DisplayPort Electrical Performance Compliance Test Application
1
Installing the License Key
1 Request a license code from Agilent by following the instructions on the
Entitlement Certificate.
You will need the oscilloscope’s “Option ID Number”, which you can
find in the Help>About Infiniium... dialog box.
2 After you receive your license code from Agilent, choose
Utilities>Install Option License....
3 In the Install Option License dialog, enter your license code and click
Install License.
4 Click OK in the dialog that tells you to restart the Infiniium
oscilloscope application software to complete the license installation.
5 Click Close to close the Install Option License dialog.
6 Choose File>Exit.
7 Restart the Infiniium oscilloscope application to complete the license
installation.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
17
1
18
Installing the DisplayPort Electrical Performance Compliance Test Application
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
2
Preparing to Take Measurements
W2641A DisplayPort Test Point Adapter Fixture 20
Calibrating the Oscilloscope 21
Starting the DisplayPort Electrical Performance Compliance Test
Application 22
Online Help Topics 24
Before running the DisplayPort automated tests, you need to acquire the
appropriate test fixtures, and you should calibrate the oscilloscope and
probe. After the oscilloscope and probe have been calibrated, you are
ready to start the DisplayPort Electrical Performance Compliance Test
Application and perform the measurements.
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2
Preparing to Take Measurements
W2641A DisplayPort Test Point Adapter Fixture
The W2641A test fixture is the Agilent DisplayPort test point adapter
fixture that is used for all of the DisplayPort compliance tests.
Acquiring the Test Fixture
The W2641A DisplayPort test point adapter fixture can be acquired from
Agilent Technologies.
W2641A Test Fixture Description
Figure 2 shows the top view of the W2641A test fixture.
Figure 2
20
W2641A DisplayPort Test Point Adapter Fixture (Top View)
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Preparing to Take Measurements
2
Calibrating the Oscilloscope
If you haven’t already calibrated the oscilloscope and probe, see
Chapter 24, “Calibrating the Infiniium Oscilloscope and Probe.
NOTE
If the ambient temperature changes more than 5 degrees Celsius from the calibration
temperature, internal calibration should be performed again. The delta between the
calibration temperature and the present operating temperature is shown in the
Utilities>Calibration menu.
NOTE
If you switch cables between channels or other oscilloscopes, it is necessary to perform
cable and probe calibration again. Agilent recommends that, once calibration is performed,
you label the cables with the channel on which they were calibrated.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
21
2
Preparing to Take Measurements
Starting the DisplayPort Electrical Performance Compliance Test
Application
1 From the Infiniium oscilloscope’s main menu, choose
Analyze>Automated Test Apps>DisplayPort Test.
Figure 3
22
The DisplayPort Electrical Performance Compliance Test Application
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
2
Preparing to Take Measurements
NOTE
If DisplayPort Test does not appear in the Automated Test Apps menu, the DisplayPort
Electrical Performance Compliance Test Application has not been installed (see Chapter 1,
“Installing the DisplayPort Electrical Performance Compliance Test Application).
Figure 3 shows the DisplayPort Electrical Performance Compliance Test
Application main window. The task flow pane, and the tabs in the main
pane, show the steps you take in running the automated tests:
NOTE
Set Up
Lets you select your setup options. Allows you to
setup by connection type, device identifier, jitter
separation measurements and test fixture type.
Select Tests
Lets you select the tests you want to run. The tests
are organized hierarchically, so you can select all
tests in a group. After tests are run, status indicators
show which tests have passed, failed, or not been
run, and there are indicators for the test groups.
Configure
Lets you enter information about the device being
tested and configure test parameters (like memory
depth). This information appears in the HTML report.
Connect
Shows you how to connect the oscilloscope to the
device under test for the tests to be run.
Run Tests
Starts the automated tests. If the connections to the
device under test need to be changed while multiple
tests are running, the tests pause, show you how to
change the connection, and wait for you to confirm
that the connections have been changed before
continuing.
Results
Contains more detailed information about the tests
that have been run. You can change the thresholds at
which marginal or critical warnings appear.
HTML Report
Shows a compliance test report that can be printed.
When you close the DisplayPort application, each channel’s probe is configured as
single-ended or differential depending on the last DisplayPort test that was run.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
23
2
Preparing to Take Measurements
Online Help Topics
For information on using the DisplayPort Electrical Performance
Compliance Test Application, see the online help (which you can access by
choosing Help>Contents... from the application’s main menu).
The DisplayPort Electrical Performance Compliance Test Application’s
online help describes:
• Running the Compliance Test Application on a second monitor.
• Starting the DisplayPort Electrical Performance Compliance Test
Application.
• To view or minimize the task flow pane.
• To view or hide the toolbar.
• Creating or opening a test project.
• Setting up DisplayPort test environment.
• Setting up DisplayPort automated tests with W2642A DPTC.
• Selecting the tests.
• Configuring selected tests.
• Connecting the oscilloscope to the Device Under Test (DUT).
• Running the tests.
• Viewing test results.
• To show reference images and flash mask hits.
• To change the display settings.
• To change the margin thresholds and report trial display.
• To change the auto- recovery option.
• Viewing or printing the HTML test report.
• Saving the test projects.
• Understanding the DisplayPort HTML report.
24
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
3
Source Eye Diagram Differential Tests
Probing for Source Data Eye Diagram Differential Tests 26
Source Eye Diagram Differential Tests 28
This section provides the guidelines for source eye diagram differential
tests using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or
1169A probes, and the DisplayPort Electrical Performance Compliance Test
Application.
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3
Source Eye Diagram Differential Tests
Probing for Source Data Eye Diagram Differential Tests
When performing the data eye diagram test, the DisplayPort Electrical
Performance Compliance Test Application will prompt you to make the
proper connections. Your DisplayPort test environment setup on the Set
Up tab must match the physical connection.
Figure 4 and Figure 5 show a physical connection for making differential
and single- ended connections.
.
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of the
probe to the plus side of the
SMA probe head and the
negative side of the probe to
the negative side of the SMA
probe head.
DUT
SMA to SMP cables
1168A or 1169A
Probe Amplifier
Lane on the W2641A test fixture
Figure 4 Probing for Differential Tests - Data Eye Diagram Tests (Single Connection with
W2641A DisplayPort Test Fixture)
26
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Eye Diagram Differential Tests
3
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 5 Differential Measurement Setup Using Two Single Ended Connections - Data
Eye Diagram Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
For more information on the 1168A or 1169A probe amplifiers and
differential probe heads, see Chapter 25, “InfiniiMax Probing,” starting on
page 231.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
27
3
Source Eye Diagram Differential Tests
Source Eye Diagram Differential Tests
The eye diagram test provides a visual evaluation of the amplitude and
timing variations of the waveform with the overall objective of obtaining a
specified bit error rate in transmitted data. The test must use a PRBS 7
test pattern at all voltage levels. The test should be performed without
pre- Emphasis.
The source eye diagram performance provides the best visual assessment
of interoperability potential by showing amplitude and timing minimum
and maximum values.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
28
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Eye Diagram Differential Tests
3
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
Figure 6
Set Up for Data Eye Pattern Differential Tests
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
29
3
Source Eye Diagram Differential Tests
Figure 7
Test Type Set Up for Data Eye Pattern Differential Tests
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted
Characterization Testing.
30
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Eye Diagram Differential Tests
3
Navigate to the Eye Diagram - Lane # - Eye Diagram Test where # is the
lane number to be tested.
Figure 8
Selecting Data Eye Pattern Differential Tests
8 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 1),
run the test and view the test results. Options may vary depending on
selected mode: Compliance Mode or Debug Mode.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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3
Source Eye Diagram Differential Tests
Table 1
Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
32
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Eye Diagram Differential Tests
Table 1
3
Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Source Differential Tests
Eye Diagram
Eye Diagram Edge
Sets the number of edges measured for the eye test.
Mask Scaling Option
Sets the type of scaling performed on the mask for the eye test.
Mask Type
Selects the type of mask to use for the eye test.
Eye Diagram Mask
Movement
This field contains 3 options. (1) Find Passing Mode will automatically
search +/-0.5UI horizontally until no violation occurs, (2) Fixed Mask
will not be moving, it only report Pass or Fail upon test, (3) Find Margin
will search +/-0.5UI horizontally to find the maximum margin of
non-violation mask.
CTS Version for Eye Mask Set the mask file to CTS version 1.0 or 1.1
Test Condition
Bit Rate: all bit rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then the device is tested for both conditions. If the device is
always SSC Enabled or always SSC Disabled then the device is tested in
its normal state.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
33
3
Source Eye Diagram Differential Tests
PASS Condition
The following table and figure define the mask for the eye measurements.
There can be no signal trajectories entering into the mask. Table 2 shows
the voltage and time coordinates for the mask used in the eye diagram.
The specification states that either 400mV, 600mV, or 800mV setting must
pass.
Table 2
Eye Diagram Mask Coordinates
Bit Rate
Mask Point
Reduced (1.62 Gb/s)
High (2.7 Gb/s)
1
0.127, 0.000
0.210, 0.000
2
0.291, 0.160
0.355, 0.140
3
0.500, 0.200
0.500, 0.175
4
0.709, 0.200
0.645, 0.175
5
0.875, 0.000
0.790, 0.000
6
0.709,-0.200
0.645,-0.175
7
0.500,-0.200
0.500,-0.175
8
0.291,-0.160
0.355,-0.140
3
4
2
1
5
8
7
Figure 9
6
The Source Eye Pattern Mask
Mask Test: Zero mask failures.
34
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Eye Diagram Differential Tests
3
Test References
See Test 3.1: Eye Diagram Testing, in the DisplayPort- Compliance Test
Specification Version 1.1.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
35
3
36
Source Eye Diagram Differential Tests
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
4
Source Total Jitter Differential Tests
Probing for Source Total Jitter Differential Tests 38
Source Total Jitter Differential Tests 40
This section provides the guidelines for source total jitter differential tests
using an Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax
probes, and the DisplayPort Electrical Performance Compliance Test
Application.
s
Agilent Technologies
37
4
Source Total Jitter Differential Tests
Probing for Source Total Jitter Differential Tests
When performing the source total jitter test, the DisplayPort Electrical
Performance Compliance Test Application will prompt you to make the
proper connections. Your DisplayPort test environment setup on the Set
Up tab must match the physical connection.
Figure 10 and Figure 11 show a physical connection for making
differential and single- ended connections.
.
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of the
probe to the plus side of the
SMA probe head and the
negative side of the probe to
the negative side of the SMA
probe head.
DUT
SMA to SMP cables
1168A or 1169A
Probe Amplifier
Lane on the W2641A test fixture
Figure 10 Probing for Differential Tests - Total Jitter Tests (Single Connection with
W2641A DisplayPort Test Fixture)
38
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Total Jitter Differential Tests
4
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 11 Differential Measurement Setup Using Two Single Ended Connections - Total
Jitter Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
39
4
Source Total Jitter Differential Tests
Source Total Jitter Differential Tests
To evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10- 9 or through an approved estimation
technique. This measurement is a data time interval error (Data- TIE) jitter
measurement. (Reference: Table 3.13 VESA DisplayPort Standard).
The overall system jitter budget allocates different amounts of jitter which
each component of the system is allowed to contribute. To exceed any of
these limits is to violate the component level jitter budget. (Reference:
Jitter model in base DisplayPort Specification (Section 3.5.3.9: The Dual
Dirac Jitter Model)).
The test must use a PRBS 7 test pattern at all voltage levels. The test can
be performed with pre- Emphasis for best performance results.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted
Characterization Testing.
40
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Total Jitter Differential Tests
4
Navigate to the Total Jitter - Lane # - where # is the lane number to be
tested.
Figure 12 Selecting Source Total Jitter Differential Tests
8 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 3),
run the test and view the test results. Options may vary depending on
selected mode: Compliance Mode or Debug Mode.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
41
4
Source Total Jitter Differential Tests
Table 3
Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
42
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Total Jitter Differential Tests
Table 3
4
Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Source Differential Tests
Jitter Separation Settings
Jitter Separation Edges
Sets the number of edges measured for the jitter separation test.
Bit Error rate
Sets the bit error rate for the RJ/DJ measurements.
Test Condition
Bit Rate: all bit rates are supported.
Output Level: all output levels are supported.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then the device is tested for both conditions. If the device is
always SSC Enabled or always SSC Disabled then the device is tested in
its normal state.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
43
4
Source Total Jitter Differential Tests
PASS Condition
Table 4
Total Jitter at Internal and Compliance Points.
Transmitter package pin
Transmitter Connector (TP2)
High-bit Rate (2.7 Gb/s per lane)
Ap-p
0.294 UI
0.420 UI
Reduced-bit Rate (1.62 Gb/s per lane)
Ap-p
0.180 UI
0.254 UI
UI is Unit Interval.
Test References
See Test 3.12: Total Jitter (TJ) Measurements in the
DisplayPort- Compliance Test Specification Version 1.1.
44
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
5
Source Non-ISI Jitter Differential Tests
Probing for Source Non-ISI Jitter Differential Tests 46
Source Non-ISI Jitter Differential Tests 48
This section provides the guidelines for source non- ISI jitter differential
tests using an Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax
probes, and the DisplayPort Electrical Performance Compliance Test
Application.
Agilent Technologies
45
5
Source Non-ISI Jitter Differential Tests
Probing for Source Non-ISI Jitter Differential Tests
When performing the non- ISI jitter test, the DisplayPort Electrical
Performance Compliance Test Application will prompt you to make the
proper connections. Your DisplayPort test environment setup on the Set
Up tab must match the physical connection.
Figure 13 and Figure 14 show a physical connection for making
differential and single- ended connections.
.
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of the
probe to the plus side of the
SMA probe head and the
negative side of the probe to
the negative side of the SMA
probe head.
DUT
SMA to SMP cables
1168A or 1169A
Probe Amplifier
Lane on the W2641A test fixture
Figure 13 Probing for Differential Tests - Non-ISI Jitter Tests (Single Connection with
W2641A DisplayPort Test Fixture)
46
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Non-ISI Jitter Differential Tests
5
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 14 Differential Measurement Setup Using Two Single Ended Connections - Non-ISI
Jitter Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
47
5
Source Non-ISI Jitter Differential Tests
Source Non-ISI Jitter Differential Tests
To evaluate the Non- ISI jitter accompanying the data transmission at
either an explicit bit error rate of 10- 9 or through an approved estimation
technique. (Reference: Table 3.13 VESA DisplayPort Standard).
The overall system jitter budget allocates different amounts of jitter which
each component of the system is allowed to contribute. To exceed any of
these limits is to violate the component level jitter budget. (Reference:
Jitter model in base DisplayPort Specification (Section 3.5.3.9: The Dual
Dirac Jitter Model)).
The test must use a PRBS 7 test pattern at all voltage levels. The test can
be performed with pre- Emphasis for best performance results.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted
Characterization Testing.
48
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Non-ISI Jitter Differential Tests
5
Navigate to the Non- ISI Jitter - Lane # - Non- ISI Jitter Test where # is
the lane number to be tested.
Figure 15 Selecting Source Non-Jitter Differential Tests
8 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 5),
run the test and view the test results. Options may vary depending on
selected mode: Compliance Mode or Debug Mode.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
49
5
Source Non-ISI Jitter Differential Tests
Table 5
Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
50
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Non-ISI Jitter Differential Tests
Table 5
5
Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Source Differential Tests
Jitter Separation Settings
Jitter Separation Edges
Sets the number of edges measured for the jitter separation test.
Bit Error rate
Sets the bit error rate for the RJ/DJ measurements.
Test Condition
Bit Rate: all bit rates are supported.
Output Level: all output levels are supported.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then the device is tested for both conditions. If the device is
always SSC Enabled or always SSC Disabled then the device is tested in
its normal state.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
51
5
Source Non-ISI Jitter Differential Tests
PASS Condition
Table 6
Non-ISI Jitter at Internal and Compliance Points.
Transmitter package pin
Transmitter Connector (TP2)
High-bit Rate (2.7 Gb/s per lane)
Ap-p
0.260 UI
0.276 UI
Reduced-bit Rate (1.62 Gb/s per lane)
Ap-p
0.160 UI
0.170 UI
UI is Unit Interval.
Test References
See Test 3.12: Non- ISI Jitter (TJ) Measurements in the
DisplayPort- Compliance Test Specification Version 1.1.
52
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
6
Source Transition Time Differential
Tests (Informative)
Probing for Source Transition Time Differential Tests 54
Source Transition Time Differential Tests 56
This section provides the guidelines for source transition time differential
tests using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or
1169A probes, and the DisplayPort Electrical Performance Compliance Test
Application.
Agilent Technologies
53
6
Source Transition Time Differential Tests (Informative)
Probing for Source Transition Time Differential Tests
When performing the transition time test, the DisplayPort Electrical
Performance Compliance Test Application will prompt you to make the
proper connections. Your DisplayPort test environment setup on the Set
Up tab must match the physical connection.
Figure 16 and Figure 17 below show the differential and the single- ended
connections for Transition Time Diffential Tests.
.
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of the
probe to the plus side of the
SMA probe head and the
negative side of the probe to
the negative side of the SMA
probe head.
DUT
SMA to SMP cables
1168A or 1169A
Probe Amplifier
Lane on the W2641A test fixture
Figure 16 Probing for Differential Tests - Transition Time Tests (Single Connection with
W2641A DisplayPort Test Fixture)
54
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Transition Time Differential Tests (Informative)
6
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 17 Differential Measurement Setup Using Two Single Ended Connections Transition Time Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
55
6
Source Transition Time Differential Tests (Informative)
Source Transition Time Differential Tests
Transition time testing measures the rise time and fall time across the
outputs of a differential data lane. The transition is defined as the time
interval between the normalized 20% and 80% amplitude levels.
The transition time test should be performed at all bit rates supported
without pre- Emphasis for 400 mV differential voltage swing. The source
pattern should be a PRBS 7 waveform. This applies to one, two, and four
lane operation with all functional lanes being tested. (Reference: Table 3.10
VESA DisplayPort Standard).
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted
Characterization Testing.
8 This is an Informative test, therefore, the Hide Informative Tests
checkbox must be un- checked.
56
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Transition Time Differential Tests (Informative)
6
Navigate to the Transition Time group, and check the rise time and fall
time tests that you want to perform.
Figure 18 Selecting Transition Time Differential Tests
9 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 7),
make oscilloscope connections, run the tests, and view the tests results.
Options may vary depending on the selected mode: Compliance Mode or
Debug Mode.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
57
6
Source Transition Time Differential Tests (Informative)
Table 7
Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
58
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Transition Time Differential Tests (Informative)
Table 7
6
Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Source Differential Tests
Transition Time
Transition Edges
Sets the number of edges measured for the transition tests.
Transition VH Pattern
Sets the pattern for rise time measurement to either 01111, 0111 or
011. The default setting is 0111.
Transition VL Pattern
Sets the pattern for fall time measurement to either 10000, 1000 or
100. The default setting is 1000.
Threshold
Specifies the threshold in percentage.
Test Condition
Bit Rate: all bit rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then the device is tested for both conditions. If the device is
always SSC Enabled or always SSC Disabled then the device is tested in
its normal state.
PASS Condition
50 ps ≤ Transition Time ≤ 160 ps
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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6
Source Transition Time Differential Tests (Informative)
Test References
See section 3.6, in the DisplayPort- Compliance Test Specification Version
1.1.
60
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
7
Source Non Pre-Emphasis Level
Differential Tests
Probing for Source Non Pre-Emphasis Level Differential Tests 62
Source Non Pre-Emphasis Level Test 64
This section provides the guidelines for source non pre- Emphasis level
differential tests using an Agilent 8 GHz or greater Infiniium oscilloscope,
1168A or 1169A probes, and the DisplayPort Electrical Performance
Compliance Test Application.
Agilent Technologies
61
7
Source Non Pre-Emphasis Level Differential Tests
Probing for Source Non Pre-Emphasis Level Differential Tests
When performing the non pre- Emphasis level differential test, the
DisplayPort Electrical Performance Compliance Test Application will
prompt you to make the proper connections. Your DisplayPort test
environment setup on the Set Up tab must match the physical connection.
Figure 19 and Figure 20 below show the differential and the single- ended
connections for Non Pre- Emphasis Level Differential Tests..
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of the
probe to the plus side of the
SMA probe head and the
negative side of the probe to
the negative side of the SMA
probe head.
DUT
SMA to SMP cables
1168A or 1169A
Probe Amplifier
Lane on the W2641A test fixture
Figure 19 Probing for Differential Tests - Non Pre-Emphasis Level Tests (Single
Connection with W2641A DisplayPort Test Fixture)
62
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Non Pre-Emphasis Level Differential Tests
7
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 20 Differential Measurement Setup Using Two Single Ended Connections - Non
Pre-Emphasis Level Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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7
Source Non Pre-Emphasis Level Differential Tests
Source Non Pre-Emphasis Level Test
To evaluate the waveform peak differential amplitude to ensure signal is
neither over, nor under driven. (Reference: Table 3.10 VESA DisplayPort
Standard).
The source is given a range of expected output for each level setting that
correlates with the system budget elements such as cable loss and receiver
eye minimum and max values. This test ensures that the system budget is
obeyed.
The amplitude measurement is performed using the following equation at
all bit rates without pre- Emphasis and a PRBS 7 waveform:
Peak- to- peak Voltage = VH - VL
where:
VH is the high voltage level
VL is the low voltage level
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted
Characterization Testing.
8 Navigate to the Non- Pre- Emphasis Level - Lane # - Non Pre- Emphasis
Level Test where # is the lane number to be tested.
64
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Non Pre-Emphasis Level Differential Tests
7
.
Figure 21 Selecting Non Pre-Emphasis Level Tests
9 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 8),
make oscilloscope connections, run the tests, and view the test results.
Options may vary depending on the selected mode: Compliance Mode or
Debug Mode.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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7
Source Non Pre-Emphasis Level Differential Tests
Table 8
Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
66
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Non Pre-Emphasis Level Differential Tests
Table 8
7
Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Source Differential Tests
Non Pre-Emphasis
Level Edges
Sets the number of edges measured for the level test.
Test Condition
Bit Rate: all bit rates are supported.
Output Level: all output levels are supported.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then the device is tested for both conditions. If the device is
always SSC Enabled or always SSC Disabled then the device is tested in
its normal state.
PASS Condition
For each level setting testes, the following equation should be used:
Resultant = 20 * Log10[VoltagePeak- Peak_Level A /
VoltagePeak- Peak_Level B]
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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7
Source Non Pre-Emphasis Level Differential Tests
Table 9
Compared Levels
Measurement
VoltagePeak-Peak_LevelA
VoltagePeak-Peak_LevelB
1
600mV nominal (0 dB)
400mV nominal (0 dB)
2
800mV nominal (0 dB)
600mV nominal (0 dB)
3*
1200mV nominal (0 dB)*
800mV nominal (0 dB).
* if device optionally capable
The resultants specifications are as identified below:
Measurement 1: 0.8 dB ≤ Resultant ≤ 6.0 dB
Measurement 2: 0.1 dB ≤ Resultant ≤ 5.1 dB
Measurement 3: 0.8 dB ≤ Resultant ≤ 6.0 dB
Test References
See Test 3- 2: Non Pre- Emphasis Level Verification Testing, in the
DisplayPort- Compliance Test Specification Version 1.1.
68
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
8
Source Overshoot Differential Tests
(Informative)
Probing for Source Overshoot Differential Tests 70
Source Overshoot Differential Tests 72
This section provides the guidelines for source overshoot differential tests
using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or 1169A
probes, and the DisplayPort Electrical Performance Compliance Test
Application.
Agilent Technologies
69
8
Source Overshoot Differential Tests (Informative)
Probing for Source Overshoot Differential Tests
When performing the overshoot test, the DisplayPort Electrical
Performance Compliance Test Application will prompt you to make the
proper connections. Your DisplayPort test environment setup on the Set
Up tab must match the physical connection.
Figure 22 and Figure 23 below show the differential and the single- ended
connections for Overshoot Differential Tests.
.
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of the
probe to the plus side of the
SMA probe head and the
negative side of the probe to
the negative side of the SMA
probe head.
DUT
SMA to SMP cables
1168A or 1169A
Probe Amplifier
Lane on the W2641A test fixture
Figure 22 Probing for Differential Tests - Overshoot Tests (Single Connection with
W2641A DisplayPort Test Fixture)
70
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Overshoot Differential Tests (Informative)
8
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 23 Differential Measurement Setup Using Two Single Ended Connections Overshoot Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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8
Source Overshoot Differential Tests (Informative)
Source Overshoot Differential Tests
Overshoot is a differential measurement across the outputs of a differential
pair. The overshoot test should be performed at the lowest pixel rate.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted
Characterization Testing.
8 This is an Informative test, therefore, the Hide Informative Tests
checkbox must be un- checked.
72
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
8
Source Overshoot Differential Tests (Informative)
Navigate to the Overshoot Test - Lane # - Overshoot Test where # is the
lane number to be tested.
Figure 24 Selecting Overshoot Differential Tests
9 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 10),
make oscilloscope connections, run the tests, and view the tests results.
Options may vary depending on the selected mode: Compliance Mode or
Debug Mode.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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8
Source Overshoot Differential Tests (Informative)
Table 10 Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
74
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Overshoot Differential Tests (Informative)
8
Table 10 Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Test Condition
Bit Rate: all bit rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then the device is tested for both conditions. If the device is
always SSC Enabled or always SSC Disabled then the device is tested in
its normal state.
PASS Condition
Overshoot ≤ 25% of the differential swing.
Test References
See section 3.8, in the DisplayPort- Compliance Test Specification Version
1.1.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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8
76
Source Overshoot Differential Tests (Informative)
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
9
Source Pre-Emphasis Level Differential
Tests (Normative & Informative)
Probing for Source Pre-Emphasis Level Differential Tests 78
Source Pre-Emphasis Level Differential Tests 80
This section provides the guidelines for source pre- Emphasis level
differential tests using an Agilent 8 GHz or greater Infiniium oscilloscope,
1168A or 1169A probes, and the DisplayPort Electrical Performance
Compliance Test Application. In this source test, the Pre- Emphasis Level
tests are normative tests whereas Non- Transition Voltage Range
Measurements are informative tests.
Agilent Technologies
77
9
Source Pre-Emphasis Level Differential Tests (Normative & Informative)
Probing for Source Pre-Emphasis Level Differential Tests
When performing the pre- Emphasis level differential test, the DisplayPort
Electrical Performance Compliance Test Application will prompt you to
make the proper connections. Your DisplayPort test environment setup on
the Set Up tab must match the physical connection.
Figure 25 and Figure 26 below show the differential and the single- ended
connections for Pre- Emphasis Level Differential Tests.
.
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of the
probe to the plus side of the
SMA probe head and the
negative side of the probe to
the negative side of the SMA
probe head.
DUT
SMA to SMP cables
1168A or 1169A
Probe Amplifier
Lane on the W2641A test fixture
Figure 25 Probing for Differential Tests - Pre-Emphasis Level Tests (Single Connection
with W2641A DisplayPort Test Fixture)
78
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Pre-Emphasis Level Differential Tests (Normative & Informative)
9
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 26 Differential Measurement Setup Using Two Single Ended Connections Pre-Emphasis Level Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
79
9
Source Pre-Emphasis Level Differential Tests (Normative & Informative)
Source Pre-Emphasis Level Differential Tests
This test evaluates the effect of pre- Emphasis on the source waveform by
measuring the peak differential amplitude and assuring the accuracy of the
pre- Emphasis setting. (Reference: Table 3.10 VESA DisplayPort Standard).
The source can apply pre- Emphasis to the waveform in order to overcome
the harmful effects caused by such things as system losses through pc
boards, connectors, and cables. The standard stipulates the relative
magnitude to overcome specific losses. Because pre- Emphasis is
negotiated, two units with substantially different degrees of pre- Emphasis
may be seen as non- interoperable under certain conditions. This test
ensures that the system loss or pre- Emphasis budget is obeyed.
Tests must be made on all bit rates supported with pre- Emphasis for all
differential voltage swings supported using a test pattern of PRBS 7. The
following equation is used to calculate the pre- Emphasis result:
⎛ V Swingpe ⎞
Pre-emphasis Result = 20 log ⎜ ---------------------------⎟
⎝ V Swingnope⎠
V Swingpe = ( V Hpe – V Lpe )
V Swingnope = ( V Hnope – V Lnope )
where:
VHpe = the high voltage value is measured using the histogram modes
at the top for transition eyes.
VLpe = the low voltage value is measured using the histogram modes
at the top for transition eyes.
VHnope = the high voltage value is measured using the histogram modes
at the top for non- transition eyes.
VLnope = the high voltage value is measured using the histogram modes
at the top for non- transition eyes.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
80
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
9
Source Pre-Emphasis Level Differential Tests (Normative & Informative)
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted
Characterization Testing.
8 The Non- Transition Voltage Range Measurement test is an Informative
test, therefore, the Hide Informative Tests checkbox must be
un- checked.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
81
9
Source Pre-Emphasis Level Differential Tests (Normative & Informative)
Navigate to the Pre- Emphasis Level - Lane # - Pre- Emphasis Level Test or
Lane # - Non- Transition Voltage Range Measurement where # is the lane
number to be tested.
Figure 27 Selecting Pre-Emphasis Level Differential Tests
9 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 11),
make oscilloscope connections, run the tests, and view the test results.
Options may vary depending on the selected mode: Compliance Mode or
Debug Mode.
82
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Pre-Emphasis Level Differential Tests (Normative & Informative)
9
Table 11 Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
83
9
Source Pre-Emphasis Level Differential Tests (Normative & Informative)
Table 11 Test Configuration Options
Configuration Option
Description
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Source Differential Tests
PreEmphasis Level
PreEmphasis Edge
Sets the number of edges measured for the Pre-Emphasis Level test.
Test Condition
Bit Rate: all bit rates are supported.
Output Level: all output levels are supported.
Pre- Emphasis: all the pre- Emphasis supported settings are subject to the
constraints listed in Table 3- 12 of the DisplayPort Standard.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then the device is tested for both conditions. If the device is
always SSC Enabled or always SSC Disabled then the device is tested in
its normal state.
84
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Pre-Emphasis Level Differential Tests (Normative & Informative)
9
PASS Condition
The pre- Emphasis calculation must fall within the following ranges for
each pre- Emphasis level:
0 dB setting: Resultant > - 8.4 dB
3.5 dB setting: Resultant3.5dB > 2.0 dB
6.0 dB setting: Resultant6.0dB > Resultant3.5dB + 1.6
9.5 dB setting: Resultant9.5dB > Resultant6.0dB + 1.6
The non- transition voltage range measurement calculation must fall within
the following ranges:
Resultant < 0.30 * (Nominal Voltage)
400 mV: Resultant < 120mV
600 mV: Resultant < 180mV
800 mV: Resultant < 240mV
Test References
See Test 3- 3: Pre- Emphasis Level Verification Testing, in the
DisplayPort- Compliance Test Specification Version 1.1.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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9
86
Source Pre-Emphasis Level Differential Tests (Normative & Informative)
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
10
Source Inter Pair Skew Differential
Tests
Probing for Source Inter Pair Skew Differential Tests 88
Source Inter Pair Skew Differential Test 90
This section provides the guidelines for source inter pair skew differential
tests using an Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax
probes, and the DisplayPort Electrical Performance Compliance Test
Application.
Agilent Technologies
87
10 Source Inter Pair Skew Differential Tests
Probing for Source Inter Pair Skew Differential Tests
When performing the inter pair skew test, the DisplayPort Electrical
Performance Compliance Test Application will prompt you to make the
proper connections. Your DisplayPort test environment setup on the Set
Up tab must match the physical connection.
Figure 28 and Figure 29 below show the differential and the single- ended
connections for Inter Pair Skew Differential Tests..
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of the
probe to the plus side of the
SMA probe head and the
negative side of the probe to
the negative side of the SMA
probe head.
DUT
SMA to SMP cables
1168A or 1169A
Probe Amplifier
Lane on the W2641A test fixture
Figure 28 Probing for Differential Tests - Inter Pair Skew Tests (Single Connection with
W2641A DisplayPort Test Fixture)
88
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Inter Pair Skew Differential Tests
10
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 29 Differential Measurement Setup Using Two Single Ended Connections - Inter
Pair Skew Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
89
10 Source Inter Pair Skew Differential Tests
Source Inter Pair Skew Differential Test
The inter pair skew test evaluates the skew, or time delay, between
respective differential data lanes in the DisplayPort interface. (Reference
Table 3.10 VESA DisplayPort Standard).
The DisplayPort interface has the ability to skew, or deskew lanes by
20 UI (Unit Intervals) which is as much as 12ns (1.62Gb/s) and is
intended to eliminate simultaneous degradation of concurrent bytes of
transmitted data. The specification at 150 ps at the package pins (TP1),
likely to be degraded another 50 ps through the connector, is less than 0.5
UI at the highest bit rate. Therefore, it is unlikely to be a significant
reason for non- interoperability.
Channel- to- channel de- skew must be performed on the two oscilloscope
channels used for this measurement (see “Differential Probe Head Skew
Calibration" on page 223 and “SMA Probe Head Skew Calibration" on
page 229).
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted
Characterization Testing.
90
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Inter Pair Skew Differential Tests
10
Navigate to the Inter Pair Skew - Lane # - Inter Pair Skew Test where #
is the lane number to be tested.
Figure 30 Selecting Inter Pair Skew Differential Tests
8 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 12),
make oscilloscope connections, run the tests, and view the tests results.
Options may vary depending on the selected mode: Compliance Mode or
Debug Mode.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
91
10 Source Inter Pair Skew Differential Tests
Table 12 Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
92
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Inter Pair Skew Differential Tests
10
Table 12 Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Source Differential Tests
Inter Pair Skew
Inter Pair Skew Edges
Sets the number of edges measured for the inter pair skew test.
Maximum Retries
Sets the number of re-tries for the inter pair skew test.
Trigger Patterns
Define trigger pattern other than the default pattern.
Test Condition
Bit Rate: highest bit rate is supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then the device is tested for both conditions. If the device is
always SSC Enabled or always SSC Disabled then the device is tested in
its normal state.
PASS Condition
- 2 UI ≤ Inter Pair Skew ≤ 2 UI
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
93
10 Source Inter Pair Skew Differential Tests
Test References
See Test 3.4: Inter- Pair Skew Measurement, in the DisplayPort- Compliance
Test Specification Version 1.1.
94
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
11
Source Unit Interval Differential Tests
(Informative)
Probing for Source Unit Interval Differential Tests 96
Source Unit Interval Differential Tests 98
This section provides the guidelines for source unit interval differential
tests using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or
1169A probes, and the DisplayPort Electrical Performance Compliance Test
Application.
Agilent Technologies
95
11 Source Unit Interval Differential Tests (Informative)
Probing for Source Unit Interval Differential Tests
When performing the unit interval test, the DisplayPort Electrical
Performance Compliance Test Application will prompt you to make the
proper connections. Your DisplayPort test environment setup on the Set
Up tab must match the physical connection.
Figure 31 and Figure 32 below show the differential and the single- ended
connections for Unit Interval Differential Tests.
.
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of the
probe to the plus side of the
SMA probe head and the
negative side of the probe to
the negative side of the SMA
probe head.
DUT
SMA to SMP cables
1168A or 1169A
Probe Amplifier
Lane on the W2641A test fixture
Figure 31 Probing for Differential Tests - Unit Interval Tests (Single Connection with
W2641A DisplayPort Test Fixture)
96
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Unit Interval Differential Tests (Informative)
11
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 32 Differential Measurement Setup Using Two Single Ended Connections - Unit
Interval Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
97
11 Source Unit Interval Differential Tests (Informative)
Source Unit Interval Differential Tests
Unit interval test evaluates the overall variation in the UI width over at
least one full typical SSC cycle to ensure it stays within the specification
limit.
This test calculates the average unit interval with and without the spread
spectrum clocking which will have very little to do with interoperability
unless the unit interval is at the extremes.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted
Characterization Testing.
8 This is an Informative test, therefore, the Hide Informative Tests
checkbox must be un- checked.
98
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Unit Interval Differential Tests (Informative)
11
Navigate to the Unit Interval - Lane # - SSC Unit Interval Test where # is
the lane number to be tested.
Figure 33 Selecting Unit Interval Differential Tests
9 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 13),
make oscilloscope connections, run the tests, and view the tests results.
Options may vary depending on the selected mode: Compliance Mode or
Debug Mode.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
99
11 Source Unit Interval Differential Tests (Informative)
Table 13 Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
100
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
11
Source Unit Interval Differential Tests (Informative)
Table 13 Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Test Condition
Bit Rate: all bit rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then the device is tested for both conditions. If the device is
always SSC Enabled or always SSC Disabled then the device is tested in
its normal state.
An evaluation of at least 100K Unit Intervals or 1 full SSC cycle is
required to ensure that any SSC modulation on the signal does not violate
the timebase accuracy specifications.
PASS Condition
For Reduced Bit Rate:
[1/1.62e9]*[1- 0.0003] ≤ Mean Unit Interval ≤ [1/1.62e9]*[1+.0053]
For High Bit Rate:
[1/2.7 e9]*[1- 0.0003] ≤ Mean Unit Interval ≤ [1/2.7e9]*[1+.0053]
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
101
11 Source Unit Interval Differential Tests (Informative)
Test References
See section 3.6, in the DisplayPort- Compliance Test Specification Version
1.1.
102
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
12
Source Main Link Frequency
Compliance Differential Tests
Probing for Source Main Link Frequency Compliance Differential
Tests 104
Source Main Link Frequency Compliance Differential Tests 106
This section provides the guidelines for the source main link frequency
compliance tests using an Agilent 8 GHz or greater Infiniium oscilloscope,
InfiniiMax probes, and the DisplayPort Electrical Performance Compliance
Test Application.
Agilent Technologies
103
12 Source Main Link Frequency Compliance Differential Tests
Probing for Source Main Link Frequency Compliance Differential Tests
When performing the source main link frequency compliance tests, the
DisplayPort Electrical Performance Compliance Test Application will
prompt you to make the proper connections. Your DisplayPort test
environment setup on the Set Up tab must match the physical connection.
Figure 34 and Figure 35 below show the differential and the single- ended
connections for Main Link Frequency Compliance Tests.
.
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of the
probe to the plus side of the
SMA probe head and the
negative side of the probe to
the negative side of the SMA
probe head.
DUT
SMA to SMP cables
1168A or 1169A
Probe Amplifier
Lane on the W2641A test fixture
Figure 34 Probing for Differential Tests - Main Link Frequency Compliance Tests (Single
Connection with W2641A DisplayPort Test Fixture)
104
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Main Link Frequency Compliance Differential Tests
12
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 35 Differential Measurement Setup Using Two Single Ended Connections - Main
Link Frequency Compliance Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
105
12 Source Main Link Frequency Compliance Differential Tests
Source Main Link Frequency Compliance Differential Tests
The main link frequency compliance test evaluates the overall variation in
source time base accuracy, ensuring the device stays within the required
+- 300 PPM limit. Tests shall be performed on a PRBS 7 signal with SSC
disabled. An evaluation of at least 10 acquisitions is required.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted
Characterization Testing.
106
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
12
Source Main Link Frequency Compliance Differential Tests
Navigate to the Main Link Frequency Compliance - Lane # - Main Link
Frequency Compliance where # is the lane number to be tested.
Figure 36 Selecting Main Link Frequency Compliance Tests
8 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 14),
make oscilloscope connections, run the tests, and view the tests results.
Options may vary depending on the selected mode: Compliance Mode or
Debug Mode.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
107
12 Source Main Link Frequency Compliance Differential Tests
Table 14 Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
108
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
12
Source Main Link Frequency Compliance Differential Tests
Table 14 Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Test Condition
Bit Rate: all bit rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: D10.2.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then the device is tested for both conditions. If the device is
always SSC Enabled or always SSC Disabled then the device is tested in
its normal state.
An evaluation of at least 10 full SSC cycles are required.
PASS Condition
The Main Link Frequency Compliance Test result must satisfy the
following criteria:
SSC frequencyppm ≤ 300.
Test References
See Test 3.14: Main Link Frequency Compliance Tests, in the
DisplayPort- Compliance Test Specification Version 1.1.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
109
12 Source Main Link Frequency Compliance Differential Tests
110
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
13
Source Spread Spectrum Clocking
(SSC) Differential Tests (Normative &
Informative)
Probing for Source Spread Spectrum Clocking (SSC) Differential
Tests 112
Source Spread Spectrum Clocking (SSC) Differential Test 114
This section provides the guidelines for the source spread spectrum
clocking (SSC) differential tests using an Agilent 8 GHz or greater
Infiniium oscilloscope, 1168A or 1169A probes, and the DisplayPort
Electrical Performance Compliance Test Application. In this SSC test, the
Modulation Frequency and Modulation Deviation tests are normative tests
whereas Deviation HF Variation tests are informative tests.
s
Agilent Technologies
111
13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative)
Probing for Source Spread Spectrum Clocking (SSC) Differential Tests
When performing the spread spectrum clocking (SSC) test, the DisplayPort
Electrical Performance Compliance Test Application will prompt you to
make the proper connections. Your DisplayPort test environment setup on
the Set Up tab must match the physical connection.
Figure 37 and Figure 38 below show the differential and the single- ended
connections for Spread Spectrum Clocking (SSC) Differential Tests.
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of the
probe to the plus side of the
SMA probe head and the
negative side of the probe to
the negative side of the SMA
probe head.
DUT
SMA to SMP cables
1168A or 1169A
Probe Amplifier
Lane on the W2641A test fixture
Figure 37 Probing for Differential Tests - SSC Tests (Single Connection with W2641A
DisplayPort Test Fixture)
112
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative)
13
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 38 Differential Measurement Setup Using Two Single Ended Connections - SSC
Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
For more information on the 1168A or 1169A probe amplifiers and
differential probe heads, see Chapter 25, “InfiniiMax Probing,” starting on
page 231.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
113
13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative)
Source Spread Spectrum Clocking (SSC) Differential Test
Spread Spectrum Modulation Frequency (Normative)
The spread spectrum modulation frequency evaluates the frequency of the
SSC modulation and validates if it falls with specification limits.
The SSC frequency will be evaluated at the highest bit rate the transmitter
supports. Tests shall be performed on a PRBS 7 signal, with SSC enabled.
An evaluation of at least 10 full SSC cycles is required (Mean value
reported). As SSC is mandatory, the reported result must be the mean of
ten measured with maximum values from the range of SSC modulation
deviation.
Spread Spectrum Modulation Deviation (Normative)
The spread spectrum modulation deviation evaluates the range of SSC
down- spreading of the transmitter signal in PPM. This requires the device
[the device must] operate in the region of 0 to - 5000 PPM. The SSC
Modulation Deviation will be evaluated at the highest bit rate the
transmitter supports. Tests shall be performed on a PRBS 7 signal, with
SSC enabled.
An evaluation of at least 10 full SSC cycles is required (Mean value
reported). As SSC is mandatory, the reported result must be the mean of
ten measured with maximum values from the range of SSC modulation
deviation.
The value reported as the result must be the single total range value
relative to nominal of the SSC modulation deviation, using the equation
below, where "Min" is the mean of 10 recorded values of the minimum
peaks.
Calculate deviation = (Measured Min - Nominal)/Nominal * 1e6 ppm
Deviation HF Variation (Informative)
The deviation HF variation verifies SSC profile that does not include any
frequency deviations which would exceed 1250 ppm/µSec.
Spread spectrum clocking demands that the sink receiver tracks the
modulated frequency of the source link rate while maintaining clock/data
phase tracking. This test measures the range of frequency deviation with
the source SSC enabled. If this range exceeds specification, the ability of
the sink to frequency and phase track may be impaired, possibly causing
data recovery errors and non- interoperability with a compliant receiver.
114
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
13
Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative)
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. SSC tests are available in the 2 test modes onlyUser Defined Conditions and Targeted Characterization Testing.
8 The Deviation HF Variation test is an Informative test, therefore, the
Hide Informative Tests checkbox must be un- checked for this test.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
115
13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative)
Navigate to the Spread Spectrum Clocking (SSC) group and select the
appropriate test and the lane number to be tested.
Figure 39 Selecting the Spread Spectrum Clocking (SSC) Tests
9 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 15),
run the test and view the test results. Options may vary depending on
selected mode: Compliance Mode or Debug Mode.
116
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative)
13
Table 15 Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative)
Table 15 Test Configuration Options
Configuration Option
Description
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
SSC Modulation Frequency Test Condition
Bit Rate: highest rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: D10.2.
SSC: Enabled. The devices that do not have SSC Enabled will not be
tested.
An evaluation of at least 10 full SSC cycle is required.
SSC Modulation Deviation Test Condition
Bit Rate: highest rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
118
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative)
13
Test Pattern: D10.2.
SSC: Enabled. The devices that do not have SSC Enabled will not be
tested.
An evaluation of at least 10 full SSC cycle is required.
SSC Deviation HF Variation Test Condition
Bit Rate: highest rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: D10.2.
SSC: Enabled. The devices that do not have SSC Enabled will not be
tested.
An evaluation of at least 10 full SSC cycle is required.
SSC Modulation Frequency PASS Condition
The SSC Modulation Frequency result must satisfy the following criteria:
• fSSC measures between 30 kHz and 33 kHz
The value above shall be based on a mean of at least 10 complete SSC
cycles.
SSC Modulation Deviation PASS Condition
The SSC Modulation Deviation result must satisfy the following criteria:
• SSCtol measures between 5000 ppm and 0 ppm
The value above shall be based on a mean of at least 10 complete SSC
cycles.
SSC Deviation HF Variation PASS Condition
The SSC Deviation HF Variation result must satisfy the following criteria:
• SSCt dF/dt ≤ 1250 ppm/µSec variations
The value above shall be based on a mean of at least 10 complete SSC
cycles.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative)
Test References
See Test 3.15: Spread Spectrum Modulation Frequency, Test 3.16: Spread
Spectrum Modulation Deviation and Test 3.17: Deviation HF Variation in
the DisplayPort- Compliance Test Specification Version 1.1.
120
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
14
Source Rise-Fall Mismatch
Single-Ended Tests (Informative)
Probing for Source Rise-Fall Mismatch Single-Ended Tests 122
Source Rise-Fall Mismatch Single-Ended Tests 123
This section provides the guidelines for source rise- fall mismatch
single- ended tests using an Agilent 8 GHz or greater Infiniium
oscilloscope, 1168A or 1169A probes, and the DisplayPort Electrical
Performance Compliance Test Application.
Agilent Technologies
121
14 Source Rise-Fall Mismatch Single-Ended Tests (Informative)
Probing for Source Rise-Fall Mismatch Single-Ended Tests
When performing the rise- fall mismatch test, the DisplayPort Electrical
Performance Compliance Test Application will prompt you to make the
proper connections. Your DisplayPort test environment setup on the Set
Up tab must match the physical connection.
Figure 40 below shows the single- ended connections for the Rise- Fall
Mismatch Single- Ended Tests.
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 40 Differential Measurement Setup Using Two Single Ended Connections Rise-Fall Mismatch Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figure are just
examples. You can choose any desired data lane and channel that you
want.
122
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14
Source Rise-Fall Mismatch Single-Ended Tests (Informative)
Source Rise-Fall Mismatch Single-Ended Tests
The rise and fall time mismatch tests evaluate the differences in rise and
fall times of the two single- ended waveform in a given differential data
lane of a DisplayPort interface. (Reference Table 3.10 VESA DisplayPort
Standard specification).
The mismatch in time of the rising and falling time of the single- ended
signals composing a differential lane will create common mode noise and
will radiate.
The rise and fall times are measured between the 80% and 20% levels of
the waveform.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted
Characterization Testing.
8 This is an Informative test, therefore, the Hide Informative Tests
checkbox must be un- checked.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
123
14 Source Rise-Fall Mismatch Single-Ended Tests (Informative)
Navigate to the Rise- Fall Mismatch group, and check the Rising Mismatch
or Falling Mismatch tests that you want to perform and the lane number
to be tested.
Figure 41 Selecting Rise-Fall Mismatch Tests
9 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 16),
make oscilloscope connections, run the tests, and view the tests results.
Options may vary depending on the selected mode: Compliance Mode or
Debug Mode.
124
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14
Source Rise-Fall Mismatch Single-Ended Tests (Informative)
Table 16 Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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14 Source Rise-Fall Mismatch Single-Ended Tests (Informative)
Table 16 Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Single-ended Tests
Rise-Fall Mismatch
Rise-Fall Mismatch Edge
Sets the number of edges measured for the rise-fall mismatch test.
Threshold
Sets the threshold used to make a rise time or fall time measurement.
Test Condition
Bit Rate: all bit rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then SSC Disabled will be selected. If the device is always
SSC Enabled or always SSC Disabled then the device is tested in its
normal state.
Two single- ended signals are probed independently, acquired
simultaneously and compared.
PASS Condition
Falling Mismatch ≤ 15% of the single- ended rise time
Rising Mismatch ≥ 15% of the single- ended fall time
126
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Rise-Fall Mismatch Single-Ended Tests (Informative)
14
Test References
See section 3.7, in the DisplayPort- Compliance Test Specification Version
1.1.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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14 Source Rise-Fall Mismatch Single-Ended Tests (Informative)
128
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
15
Source Intra Pair Skew Single-Ended
Tests
Probing for Source Intra Pair Skew Single-Ended Tests 130
Source Intra Pair Skew Single-Ended Tests 131
This section provides the guidelines for source intra pair skew
sing le- ended tests using an A gilent 8 GHz or g reater Inf iniium
oscilloscope, InfiniiMax probes, and the DisplayPort Electrical Performance
Compliance Test Application.
s
Agilent Technologies
129
15 Source Intra Pair Skew Single-Ended Tests
Probing for Source Intra Pair Skew Single-Ended Tests
When performing the intra pair skew test, the DisplayPort Electrical
Performance Compliance Test Application will prompt you to make the
proper connections. Your DisplayPort test environment setup on the Set
Up tab must match the physical connection.
Figure 42 below shows the single- ended connections for Intra Pair Skew
Single- Ended Tests.
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 42 Differential Measurement Setup Using Two Single Ended Connections - Intra
Pair Skew Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figure are just
examples. You can choose any desired data lane and channel that you
want.
130
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
15
Source Intra Pair Skew Single-Ended Tests
Source Intra Pair Skew Single-Ended Tests
The intra pair skew test evaluates the skew, or time delay, between the
respective sides of a differential data lane in a DisplayPort interface.
(Reference Table 3.10 VESA DisplayPort Standard).
Intra pair skew has deleterious effects on signal rise time and manner of
crossing through the transition point. The DisplayPort specification at
package pins (TP1) is 20 ps. It can clearly double or triple to and through
the connector. These are secondar y contributors to source jitter
performance.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted
Characterization Testing.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
131
15 Source Intra Pair Skew Single-Ended Tests
Navigate to the Intra Pair Skew - Lane # - Intra Pair Skew Test where #
is the lane number to be tested.
Figure 43 Selecting Intra Pair Skew Tests
8 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 17),
make oscilloscope connections, run the tests, and view the tests results.
Options may vary depending on the selected mode: Compliance Mode or
Debug Mode.
132
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
15
Source Intra Pair Skew Single-Ended Tests
Table 17 Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
133
15 Source Intra Pair Skew Single-Ended Tests
Table 17 Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Single-ended Tests
Intra-pair Skew
Intra Pair Skew Edges
Sets the number of edges measured for the intra pair skew test.
Skew Trigger Patterns
Define trigger pattern for intra pair skew test.
Test Condition
Bit Rate: highest bit rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then both will be selected. If the device is always SSC
Enabled or always SSC Disabled then the device is tested in its normal
state.
PASS Condition
Intra pair skew ≤ 30 ps
Test References
See Test 3.5: in the DisplayPort- Compliance Test Specification Version
1.1.
134
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Source Intra Pair Skew Single-Ended Tests
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
15
135
15 Source Intra Pair Skew Single-Ended Tests
136
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
16
Source AC Common Mode Noise
Single-Ended Tests
Probing for Source AC Common Mode Noise Single-Ended Tests 138
Source AC Common Mode Noise Single-Ended Test 139
This section provides the guidelines for source AC common mode noise
single- ended tests using an Agilent 8 GHz or greater Infiniium
oscilloscope, InfiniiMax probes, and the DisplayPort Electrical Performance
Compliance Test Application.
s
Agilent Technologies
137
16 Source AC Common Mode Noise Single-Ended Tests
Probing for Source AC Common Mode Noise Single-Ended Tests
When performing the AC common mode noise test, the DisplayPort
Electrical Performance Compliance Test Application will prompt you to
make the proper connections. Your DisplayPort test environment setup on
the Set Up tab must match the physical connection.
Figure 44 below shows the single- ended connections for AC Common
Mode Noise Single- Ended Tests.
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 44 Differential Measurement Setup Using Two Single Ended Connections - AC
Common Mode Noise Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figure are just
examples. You can choose any desired data lane and channel that you
want.
138
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
16
Source AC Common Mode Noise Single-Ended Tests
Source AC Common Mode Noise Single-Ended Test
The AC common mode noise measurement of the distributed clock network
verifies that the nominal operating clock frequency is within the
acceptable tolerance range. In order for the sink devices to properly
recover the data, the source clock must operate within the acceptable
tolerance range.
The test must be made at all bit rates supported by the device under test
without pre- Emphasis and a voltage swing of 1.2 volts. A test pattern of
D10.2 should be used.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type,
Connection Type and Number of Channels according to the type of
testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted
Characterization Testing.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
139
16 Source AC Common Mode Noise Single-Ended Tests
Navigate to the AC Common Mode - Lane # - Common Mode AC Test
where # is the lane number to be tested.
Figure 45 Selecting AC Common Mode Tests
8 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 18),
make oscilloscope connections, run the tests, and view the tests results.
Options may vary depending on the selected mode: Compliance Mode or
Debug Mode.
140
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
16
Source AC Common Mode Noise Single-Ended Tests
Table 18 Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
141
16 Source AC Common Mode Noise Single-Ended Tests
Table 18 Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Single-ended Tests
AC Common Mode
AC Common Edge
Sets the number of edges measured for the AC common mode test.
Interpolation
Specifies whether to turn on or off the Sin(x)/x interpolation. Turning
On interpolation may cause more peak-to-peak jitter.
Filter
Specifies whether a high pass filter, low pass filter or no filter is
applied before the measurement. Interpolation is turned off if any filter
is chosen.
Cut Off Frequency
Sets the Cut Off Frequency if a Filter is applied.Specify in correct
format; xMHz, xkHz or xHz.
Test Condition
Bit Rate: all bit rates are supported.
Output Level: all output levels are supported.
Pre- Emphasis: all the pre- Emphasis settings are supported.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then SSC Disabled will be selected. If the device is always
SSC Enabled or always SSC Disabled then the device is tested in its
normal state.
Two single- ended signals are probed independently, acquired
simultaneously and compared.
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Source AC Common Mode Noise Single-Ended Tests
16
PASS Condition
AC Common Mode Noise < 20 mVrms.
Test References
See Test 3.10: AC Common Mode Noise, in the DisplayPort- Compliance
Test Specification Version 1.1.
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16 Source AC Common Mode Noise Single-Ended Tests
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U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
17
Link Layer Protocol Tests
Probing for Link Layer Protocol Tests 146
Link Layer Protocol Tests 147
This section provides the guidelines for link layer protocol tests using an
Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax probes, and the
DisplayPort Electrical Performance Compliance Test Application. Link layer
protocol tests are not compliance tests. The purpose of these tests is to
verify if the link layer protocol is operating properly prior to any tests.
These tests verify if the DUT is able to respond well when the
configuration of the link layer is changed.
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17 Link Layer Protocol Tests
Probing for Link Layer Protocol Tests
When performing the link layer protocol test, the DisplayPort Electrical
Performance Compliance Test Application will prompt you to make the
proper connections. Your DisplayPort test environment setup on the Set
Up tab must match the physical connection.
Figure 46 below shows the single- ended connections for Link Layer
Protocol Tests.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 46 Differential Measurement Setup Using Two Single Ended Connections - Link
Layer Protocol Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figure are just
examples. You can choose any desired data lane and channel that you
want.
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Link Layer Protocol Tests
17
Link Layer Protocol Tests
The link layer protocol tests consists of Pre- Emphasis, Level and Bit Rate
tests.
Link Layer Protocol - Pre-Emphasis
The link layer - pre- Emphasis test verifies if the pre- Emphasis of the DUT
can change accordingly from the lowest pre- Emphasis to the highest
pre- Emphasis setting.
The test must be made on the highest bit rate supported by the
differential voltage swings of 400 mV using a test pattern of PRBS 7. The
following equation is used to calculate the pre- Emphasis result:
Pre- Emphasis Result = 20log(VSwingPE/ VSwingNoPE)
VSwingPE = VHpe- VLpe
VSingNoPE = VHnope- VLnope
where:
VHpe = the high voltage value is measured using the histogram modes
at the top for transition eyes.
VLpe = the low voltage value is measured using the histogram modes at
the top for transition eyes.
VHnope = the high voltage value is measured using the histogram modes
at the top for non- transition eyes.
VLnope = the high voltage value is measured using the histogram modes
at the top for non- transition eyes.
Link Layer Protocol - Level
The link layer - level tests verifies if the amplitude level of the DUT can
change accordingly from the lowest to the highest setting.
The amplitude measurement is performed using the following equation at
all bit rates without pre- Emphasis and a PRBS 7 waveform:
Peak- to- peak Voltage = VH - VL where:
VH is the high voltage levelVL is the low voltage level
Link Layer Protocol - Bit Rate
The link layer - bit rate tests verifies if the bit rate of the DUT can change
accordingly from the lowest to the highest setting.
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17 Link Layer Protocol Tests
The test must be made at all bit rates supported by the DUT without
pre- Emphasis and a voltage swing of 400 mV. A test pattern of PRBS 7
should be used.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the DUT Definition Settings, Fixture Type and Number of Channels
according to the type of testing being done.
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Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Link Layer Protocol Tests
17
Navigate to the Link Layer (Protocol Test) group, and check the test and
lane you want to test.
Figure 47 Selecting Link Layer Protocol Tests
8 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 19),
make oscilloscope connections, run the tests, and view the tests results.
Options may vary depending on the selected mode: Compliance Mode or
Debug Mode.
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17 Link Layer Protocol Tests
Table 19 Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
150
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
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17
Link Layer Protocol Tests
Table 19 Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Pre-Emphasis Test Condition
Bit Rate: highest bit rates are supported.
Output Level: 400 mVolts.
Pre- Emphasis: All.
Test Pattern: PRBS 7.
Level Test Condition
Bit Rate: highest bit rates are supported.
Output Level: All.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
Bit Rate Test Condition
Bit Rate: all bit rates are supported.
Output Level: 400 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
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17 Link Layer Protocol Tests
Pre-Emphasis PASS Condition
Link Layer Protocol - Pre- Emphasis Test
For 3.5 dB setting: Resultant3.5dB > 2.0 dB
For 6.0 dB setting: Resultant6.0dB results > Resultant3.5dB + 1.6
For 9.5 dB setting: Resultant9.5dB results > Resultant6.0dB + 1.6
Level PASS Condition
Link Layer Protocol - Level Test
Output Level 1: 340 mV < Voltage Peak- Peak < 460 mV
Output Level 2: 510 mV < Voltage Peak- Peak < 680 mV
Output Level 3: 690 mV < Voltage Peak- Peak < 920 mV
Output Level 4: 1020 mV < Voltage Peak- Peak < 1380 mV
Bit Rate PASS Condition
Link Layer Protocol - Bit Rate Test
0.9 * Nominal Bit Rate < Measured Data Rate < 1.1 * Nominal Bit Rate
Test References
-
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U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
18
Sink Eye Diagram Tests
Probing for Sink Eye Diagram Tests 154
Sink Eye Diagram Tests 156
This section provides the guidelines for sink eye diagram tests using an
Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or 1169A probes,
and the DisplayPort Electrical Performance Compliance Test Application.
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18 Sink Eye Diagram Tests
Probing for Sink Eye Diagram Tests
When performing the sink eye diagram test, the DisplayPort Electrical
Performance Compliance Test Application will prompt you to make the
proper connections. Your DisplayPort test environment setup on the Set
Up tab must match the physical connection.
Figure 48 and Figure 49 show a physical connection for making
differential and single- ended connections.
.
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of
the probe to the plus side
of the SMA probe head
and the negative side of
the probe to the negative
side of the SMA probe head.
DUT
SMA to SMP cables
1168A or 1169A Probe
Amplifier
Lane on the test fixture
Figure 48 Probing for Differential Tests - Sink Eye Diagram Tests (Single Connection with
DisplayPort Test Fixture)
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Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
18
Sink Eye Diagram Tests
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 49 Differential Measurement Setup Using Two Single Ended Connections - Sink
Eye Diagram Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
For more information on the 1168A or 1169A probe amplifiers and
differential probe heads, see Chapter 25, “InfiniiMax Probing,” starting on
page 231.
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18 Sink Eye Diagram Tests
Sink Eye Diagram Tests
The eye diagram test provides a visual evaluation of the amplitude and
timing variations of the waveform with the overall objective of obtaining a
specified bit error rate in the transmitted data. The test must use a PRBS
7 test pattern at all voltage levels. The test should be performed without
pre- Emphasis.
The sink eye diagram performance provides the best visual assessment of
interoperability potential by showing amplitude and timing minimum and
maximum values.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the DUT Definition Settings, Connection Type and Number of
Channels according to the type of testing being done.
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Sink Eye Diagram Tests
18
Navigate to the Eye Diagram Test - Lane # - Sink Eye Diagram Test where
# is the lane number to be tested.
Figure 50 Selecting Sink Eye Diagram Tests
8 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 20),
run the test and view the test results. Options may vary depending on
selected mode: Compliance Mode or Debug Mode.
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18 Sink Eye Diagram Tests
Table 20 Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
158
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
18
Sink Eye Diagram Tests
Table 20 Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
Sink Test
Sink Mask
Selects the type of mask to use for the eye test.
Sink Mask Movement
This field contains 3 options. (1) Find Passing Mode will automatically
search +/-0.5UI horizontally until no violation occurs, (2) Fixed Mask
will not be moving, it only reports Pass or Fail upon test, (3) Find
Biggest Margin will search +/-0.5UI horizontally to find the maximum
margin of non-violation mask.
Sink Equalizer
Selects the type of equalization to use for the Sink test. Select Manual
if you would like to provide own Equalization Coefficient file.
Sink Data Rate
Measurement
Specify the method to measure data rate on waveform. User can
specifically enter the data rate by themselves.
Jitter Separation Edges
Sets the number of edges measured for the jitter separation test.
Bit Error Rate
Sets the bit error rate for the RJ/DJ measurements.
9 In order to perform the equalization, you have the option to use your
own coefficient file. To do so, at the Configure page, under the Sink
Equalizer option, Select “User Defined File” from the drop down menu.
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18 Sink Eye Diagram Tests
Figure 51 Selecting User Defined File for the Sink Equalizer
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Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Sink Eye Diagram Tests
18
Figure 52 Selecting User Defined File
10 The following select file dialog box appears. Select your coefficient file
(*.equ) and click Open. The test will run based on the your user
defined coefficient file.
PASS Condition
The following table and figure define the mask for the eye measurements.
There can be no signal trajectories entering into the mask. Table 21 shows
the voltage and time coordinates for the mask used for the eye diagram.
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18 Sink Eye Diagram Tests
Table 21 Sink Eye Vertices for TP3
Bit Rate
Mask Point
Reduced (1.6 Gb/s)
High (2.7 Gb/s)
1
0.375, 0.000
0.246, 0.000
2
0.500, 0.023
0.500, 0.075
3
0.625, 0.000
0.755, 0.000
4
0.500, -0.023
0.500, -0.075
Figure 53 The Sink Eye Mask at TP3
Mask Test: Zero mask failures.
Test References
See Test 3.1: Eye Diagram Testing, in the DisplayPort- Compliance Test
Specification Version 1.1.
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U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
19
Sink Total Jitter Tests
Probing for Sink Total Jitter Tests 164
Sink Total Jitter Tests 166
This section provides the guidelines for sink total jitter tests using an
Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax probes, and the
DisplayPort Electrical Performance Compliance Test Application.
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19 Sink Total Jitter Tests
Probing for Sink Total Jitter Tests
When performing the sink total jitter test, the DisplayPort Electrical
Performance Compliance Test Application will prompt you to make the
proper connections. Your DisplayPort test environment setup on the Set
Up tab must match the physical connection.
Figure 54 and Figure 55 show a physical connection for making
differential and single- ended connections.
.
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of
the probe to the plus side
of the SMA probe head
and the negative side of
the probe to the negative
side of the SMA probe head.
DUT
SMA to SMP cables
1168A or 1169A
Probe Amplifier
Lane on the test fixture
Figure 54 Probing for Differential Tests - Sink Total Jitter Tests (Single Connection with
DisplayPort Test Fixture)
164
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
19
Sink Total Jitter Tests
.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 55 Differential Measurement Setup Using Two Single Ended Connections - Sink
Total Jitter Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
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19 Sink Total Jitter Tests
Sink Total Jitter Tests
To evaluate the total jitter accompanying the data transmission at either
an explicit bit error rate of 10- 9 or through an approved estimation
technique. This measurement is a data time interval error (Data- TIE) jitter
measurement. (Reference: Table 3.13 VESA DisplayPort Standard).
The overall system jitter budget allocates different amounts of jitter which
each component of the system is allowed to contribute. To exceed any of
these limits is to violate the component level jitter budget. (Reference:
Jitter model in base DisplayPort Specification (Section 3.5.3.9: The Dual
Dirac Jitter Model)).
The test must use a PRBS 7 test pattern at all voltage levels. The test can
be performed with pre- Emphasis for best performance results.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the DUT Definition Settings, Connection Type and Number of
Channels according to the type of testing being done.
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Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Sink Total Jitter Tests
19
Navigate to the Total Jitter Test - Lane # - Sink Total Jitter Test where #
is the lane number to be tested.
Figure 56 Selecting Sink Total Jitter Tests
8 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 22),
run the test and view the test results. Options may vary depending on
selected mode: Compliance Mode or Debug Mode.
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19 Sink Total Jitter Tests
Table 22 Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
168
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
19
Sink Total Jitter Tests
Table 22 Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
Sink Test
Sink Mask
Selects the type of mask to use for the eye test.
Sink Mask Movement
This field contains 3 options. (1) Find Passing Mode will automatically
search +/-0.5UI horizontally until no violation occurs, (2) Fixed Mask
will not be moving, it only reports Pass or Fail upon test, (3) Find
Biggest Margin will search +/-0.5UI horizontally to find the maximum
margin of non-violation mask.
Sink Equalizer
Selects the type of equalization to use for the Sink test. Select Manual
if you would like to provide own Equalization Coefficient file.
Sink Data Rate
Measurement
Specify the method to measure data rate on waveform. User can
specifically enter the data rate by themselves.
Jitter Separation Edges
Sets the number of edges measured for the jitter separation test.
Bit Error Rate
Sets the bit error rate for the RJ/DJ measurements.
9 In order to perform the equalization, you have the option to use your
own coefficient file. To do so, at the Configure page, under the Sink
Equalizer option, Select “User Defined File” from the drop down menu.
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
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19 Sink Total Jitter Tests
Figure 57 Selecting User Defined File for the Sink Equalizer
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Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Sink Total Jitter Tests
19
Figure 58 Selecting User Defined File
10 The following select file dialog box appears. Select your coefficient file
(*.equ) and click Open. The test will run based on the your user
defined coefficient file.
PASS Condition
-
Test References
See Test 3.12: Total Jitter (TJ) Measurements in the
DisplayPort- Compliance Test Specification Version 1.1.
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U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
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Sink Non-ISI Jitter Tests
Probing for Sink Non-ISI Jitter Tests 174
Sink Non-ISI Jitter Tests 176
This section provides the guidelines for sink non- ISI jitter tests using an
Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax probes, and the
DisplayPort Electrical Performance Compliance Test Application.
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20 Sink Non-ISI Jitter Tests
Probing for Sink Non-ISI Jitter Tests
When performing the sink non- ISI jitter test, the DisplayPort Electrical
Performance Compliance Test Application will prompt you to make the
proper connections. Your DisplayPort test environment setup on the Set
Up tab must match the physical connection.
Figure 59 and Figure 60 show a physical connection for making
differential and single- ended connections.
.
Infiniium Oscilloscope
N5380A SMA probe head.
Connect the plus side of the
probe to the plus side of the
SMA probe head and the
negative side of the probe to
the negative side of the SMA
probe head.
DUT
SMA to SMP cables
1168A or 1169A
Probe Amplifier
Lane on the W2641A test fixture
Figure 59 Probing for Differential Tests - Sink Non-ISI Jitter Tests (Single Connection with
W2641A DisplayPort Test Fixture)
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.
Infiniium Oscilloscope
DUT
SMA to SMP cables
Data Channel
Lane on the W2641A test fixture
Figure 60 Differential Measurement Setup Using Two Single Ended Connections - Sink
Non-ISI Jitter Tests (A Minus B Configuration)
You can use any oscilloscope channel and connect it to any lane test point.
You select the channels used for testing lanes in the Set Up tab of the
DisplayPort Electrical Performance Compliance Test Application.
The data lanes and channels shown in the previous figures are just
examples. You can choose any desired data lane and channel that you
want.
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Sink Non-ISI Jitter Tests
To evaluate the Non- ISI jitter accompanying the data transmission at
either an explicit bit error rate of 10- 9 or through an approved estimation
technique. (Reference: Table 3.13 VESA DisplayPort Standard).
The overall system jitter budget allocates different amounts of jitter which
each component of the system is allowed to contribute. To exceed any of
these limits is to violate the component level jitter budget. (Reference:
Jitter model in base DisplayPort Specification (Section 3.5.3.9: The Dual
Dirac Jitter Model)).
The test must use a PRBS 7 test pattern at all voltage levels. The test can
be performed with pre- Emphasis for best performance results.
Test Procedure
1 Start the automated testing application as described in “Starting the
DisplayPort Electrical Performance Compliance Test Application" on
page 22.
2 Connect the W2641A test fixture or other appropriate fixture to the
device under test (DUT).
3 If you are using one connection, connect the probe to one channel. If
you are using two connections, connect the two probes to two channels
of the oscilloscope. If you are using four connections, connect the four
probes to four channels of the oscilloscope.
4 Connect the SMA to SMP cable to the SMA probe head of one of the
probes and to the data lane connector on the W2641A fixture that you
want to test.
5 Connect the other SMA to SMP cable to the other SMA probe head and
to the data lane on the W2641A test fixture that you want to test.
6 In the DisplayPort Compliance Test Application, click the Set Up tab.
7 Set the DUT Definition Settings, Connection Type and Number of
Channels according to the type of testing being done.
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Navigate to the Non- ISI Jitter Test - Lane # - Non- ISI Jitter Test where #
is the lane number to be tested.
Figure 61 Selecting Sink Non-Jitter Tests
8 Follow the DisplayPort Electrical Performance Compliance Test
Application’s task flow to set up configuration options (see Table 23),
run the test and view the test results. Options may vary depending on
selected mode: Compliance Mode or Debug Mode.
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Table 23 Test Configuration Options
Configuration Option
Description
Clock Recovery Settings
Clock Recovery Order
Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) 1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
2πF t
ω n = ------------------------------------------------------------------2ζ 2 – 1 + ( 2ζ 2 – 1 ) 2 + 1
where:
ω n = the natural frequency of the PLL
ζ = the dampling factor of the PLL
F t = the 3 dB bandwidth of the PLL
Configurable Parameter Settings
178
Bandwidth Reduction
Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge
Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge
Sets the number of edges required when making the VTop and VBase
measurements.
Expert Mode
Turn on the expert mode for looser pre-requisite checker.
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Table 23 Test Configuration Options
Configuration Option
Description
Test Plan Check Mode
Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions
Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth
Sets the memory depth for acquisition
Sink Test
Sink Mask
Selects the type of mask to use for the eye test.
Sink Mask Movement
This field contains 3 options. (1) Find Passing Mode will automatically
search +/-0.5UI horizontally until no violation occurs, (2) Fixed Mask
will not be moving, it only reports Pass or Fail upon test, (3) Find
Biggest Margin will search +/-0.5UI horizontally to find the maximum
margin of non-violation mask.
Sink Equalizer
Selects the type of equalization to use for the Sink test. Select Manual
if you would like to provide own Equalization Coefficient file.
Sink Data Rate
Measurement
Specify the method to measure data rate on waveform. User can
specifically enter the data rate by themselves.
Jitter Separation Edges
Sets the number of edges measured for the jitter separation test.
Bit Error Rate
Sets the bit error rate for the RJ/DJ measurements.
9 In order to perform the equalization, you have the option to use your
own coefficient file. To do so, at the Configure page, under the Sink
Equalizer option, Select “User Defined File” from the drop down menu.
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Figure 62 Selecting User Defined File for the Sink Equalizer
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Figure 63 Selecting User Defined File
10 The following select file dialog box appears. Select your coefficient file
(*.equ) and click Open. The test will run based on the your user
defined coefficient file.
PASS Condition
Table 24 Non-ISI Jitter at Internal and Compliance Points.
Receiver package pin
Transmitter Connector (TP2)
High-bit Rate (2.7 Gb/s per lane)
Ap-p
0.339 UI
0.330 UI
Reduced-bit Rate (1.62 Gb/s per lane)
Ap-p
0.465 UI
0.442 UI
UI is Unit Interval.
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Test References
See Test 3.12: Non- ISI Jitter (TJ) Measurements in the
DisplayPort- Compliance Test Specification Version 1.1.
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U7232A DisplayPort Electrical Performance Compliance Test Application
Method of Implementation
21
Cable Eye Diagram Tests
Probing for Cable Eye Diagram Tests 184
Cable Eye Diagram Tests 186
This section provides the guidelines for cable eye diagram tests using an
Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or 1169A probes,
and the DisplayPort Electrical Performance Compliance Test Application.
s
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