WM8742 Product Datasheet

w

WM8742

24-bit 192kHz DAC with Advanced Digital Filtering

DESCRIPTION

The WM8742 is a very high performance stereo DAC designed for audio applications such as professional recording systems, A/V receivers and high specification CD,

DVD and home theatre systems. The device supports PCM data input word lengths from 16 to 32-bits and sampling rates up to 192kHz. The WM8742 also supports DSD bitstream data format, in both direct DSD and PCM-converted

DSD modes.

The WM8742 includes fine resolution volume and soft mute control, digital de-emphasis and a range of advanced digital filter responses, followed by a digital interpolation filter, multi-bit sigma delta modulator and stereo DAC. Wolfson’s patented architecture optimises the linearity of the DAC and provides maximum insensitivity to clock jitter.

The digital filters include several selectable roll-off and performance characteristics. The user can select between standard sharp or slow roll-off responses. In addition, the

WM8742 includes a selection of advanced digital filter characteristics including non-half band filters and minimum phase filters.

This flexibility provides a range of benefits, such as significantly reduced pre-ringing and minimal group delay.

The internal digital filters can also be by-passed and the

WM8742 used with an external digital filter.

The WM8742 supports two connection schemes for audio

DAC control. The 2/3 wire serial control interface provides access to all features. A range of features can also be accessed by hardware control interface.

The WM8742 is available in a convenient 28-SSOP package, and is pin compatible with the WM8740 and

WM8741.

FEATURES



Advanced Ultra High Performance Multi-bit Sigma-Delta

Architecture

 126dB SNR (‘A’-weighted mono @ 48kHz)

 123dB SNR (‘A’-weighted stereo @ 48kHz)

 121dB SNR (non-weighted stereo @ 48kHz)

 -100dB THD @ 48kHz

 Differential analogue voltage outputs

 High tolerance to clock jitter

Mode

 Sampling frequency: 32kHz to 192kHz

 Input data word length support: 16 to 32-bit

 Supports all standard audio interface formats

 Selectable advanced digital filter responses



Includes linear/minimum phase and range of tailored characteristics



Enables low pre-ringing, minimal latency

 Optional interface to industry standard external filters

 Digital volume control in 0.125dB steps with soft ramp and soft mute

 Anti-clipping mode to prevent distortion even with input signals recorded up to 0dB

 Selectable de-emphasis support

 Zero Flag output

 DSD

 DSD bit-stream support for SACD applications

 Support for normal or phase modulated bit-streams

 Direct or PCM converted DSD paths (DSD Plus)

 DSD



Hardware or software control modes:

 2 and 3 wire serial control interface support



Pin compatible with WM8740 and WM8741



4.5V to 5.5V analogue, 3.15V to 3.6V digital supply operation



28-lead SSOP Package

APPLICATIONS



Professional audio systems



CD, DVD, SACD audio



Home theatre systems receivers

WOLFSON MICROELECTRONICS plc

Production Data, February 2013, Rev 4.3

Copyright

2013 Wolfson Microelectronics plc

WM8742

BLOCK DIAGRAM

Production Data w

PD, Rev 4.3, February 2013

2

Production Data

WM8742

TABLE OF CONTENTS

DESCRIPTION ....................................................................................................... 1

FEATURES ............................................................................................................ 1

APPLICATIONS ..................................................................................................... 1

BLOCK DIAGRAM ................................................................................................ 2

TABLE OF CONTENTS ......................................................................................... 3

PIN CONFIGURATION .......................................................................................... 4

ORDERING INFORMATION .................................................................................. 4

PIN DESCRIPTION (SOFTWARE CONTROL MODE) .......................................... 5

PIN DESCRIPTION (HARDWARE CONTROL MODE) ......................................... 7

ABSOLUTE MAXIMUM RATINGS ........................................................................ 9

THERMAL PERFORMANCE ................................................................................. 9

RECOMMENDED OPERATING CONDITIONS ................................................... 10

ELECTRICAL CHARACTERISTICS ................................................................... 10

MASTER CLOCK TIMING ............................................................................................. 12

PCM DIGITAL AUDIO INTERFACE TIMINGS .............................................................. 12

DSD AUDIO INTERFACE TIMINGS.............................................................................. 13

CONTROL INTERFACE TIMING – 3-WIRE MODE ...................................................... 14

CONTROL INTERFACE TIMING – 2-WIRE MODE ...................................................... 15

INTERNAL POWER ON RESET CIRCUIT .................................................................... 16

DEVICE DESCRIPTION ...................................................................................... 18

INTRODUCTION ........................................................................................................... 18

CLOCKING SCHEMES ................................................................................................. 18

CONTROL INTERFACE ................................................................................................ 18

SOFTWARE CONTROL INTERFACE........................................................................... 19

DIGITAL AUDIO INTERFACE ....................................................................................... 21

DSD MODE ................................................................................................................... 27

SOFTWARE CONTROL MODE .................................................................................... 28

HARDWARE CONTROL MODE.................................................................................... 39

OVERVIEW OF FUNCTIONS .............................................................................. 43

REGISTER MAP .................................................................................................. 44

DIGITAL FILTER CHARACTERISTICS .............................................................. 49

PCM MODE FILTER CHARACTERISTICS ................................................................... 49

8FS MODE FILTER CHARACTERISTICS .................................................................... 51

DSD PLUS MODE FILTER CHARACTERISTICS ......................................................... 52

PCM MODE FILTER RESPONSES .............................................................................. 53

8FS MODE FILTER RESPONSES ................................................................................ 58

DSD PLUS MODE FILTER RESPONSES .................................................................... 58

DSD DIRECT MODE FILTER RESPONSES ................................................................ 59

DEEMPHASIS FILTER RESPONSES........................................................................... 61

APPLICATIONS INFORMATION ........................................................................ 62

PACKAGE DIMENSIONS .................................................................................... 63

IMPORTANT NOTICE ......................................................................................... 64

ADDRESS: .................................................................................................................... 64

REVISION HISTORY ........................................................................................... 65

w


3

WM8742

PIN CONFIGURATION

Production Data

ORDERING INFORMATION

DEVICE

TEMPERATURE

RANGE

WM8742GEDS/V -0

 to +70C

WM8742GEDS/RV -0

 to +70C

PACKAGE

28-lead SSOP

(Pb-free)

28-lead SSOP

(Pb-free, tape and reel)

Note:

Reel Quantity = 2,000

MOISTURE SENSITIVITY

LEVEL

PEAK SOLDERING

TEMPERATURE

MSL2 260˚C

MSL2 260˚C


4 w

Production Data

PIN DESCRIPTION (SOFTWARE CONTROL MODE)

PIN NAME TYPE

PCM MODE

DESCRIPTION

8FS PCM MODE

WM8742

DSD MODES

1

2

LRCLK /

DSDL

DIN /

DINL

Digital input

Digital input

Audio interface left/right clock input

Audio interface data input Audio interface left data

3 BCLK /

DSD64CLK

Digital input Audio interface bit clock input

4 FSEL /

DINR

Digital input

Tri-level

Unused

5 MCLK Digital

Master clock input

Audio interface left/right clock input input

Audio interface bit clock input

Audio interface right data input

Master clock input

DSD left audio data in

Unused

64fs system clock input

Unused

Unused

Internal pulldown selection

0 = normal operation

1 = differential mono mode

Differential mono mode selection



Digital ground




Digital ground reference

Analogue Right analogue negative reference

Output

Output

Output decoupling pin output output

14 AGND Supply

Right analogue positive reference

Right analogue negative reference

Right analogue midrail decoupling pin

Right DAC positive output

Right DAC negative output

Analogue ground






Analogue ground

15 AVDD Supply

16 VOUTLN Analogue Left DAC negative output Left DAC negative output

Output

17 VOUTLP Analogue Left DAC positive output Left DAC positive output

Output

Output decoupling pin

Left analogue midrail decoupling pin

Left analogue midrail decoupling pin reference reference

Left analogue negative reference

Left analogue positive reference

Zero flag output



Zero flag output

22 OSR/DSDR Unused DSD right audio data in

23 IWO /

DOUT

Digital input

Tri-level

Digital input/output

Unused

Buffered audio interface data output

Unused Unused w


5

WM8742

PIN NAME TYPE

PCM MODE

DESCRIPTION

8FS PCM MODE

Production Data

DSD MODES

24

25

MODE /

LRSEL

MUTEB /

SDOUT

Digital input,

tri-level

Digital input or output:

Internal pull-up

When DIFFHW=0:

0 = hardware mode

1 = 3-wire software mode

Z = 2-wire software mode

When DIFFHW=1:

0 = left channel mono

1 = right channel mono

Softmute Control

0 = mute active


NOTE: In 3-wire mode only, this pin may be used as a buffered control interface data output

Serial control interface data input

27

DEEMPH

SCLK /

DSD

/ Digital input

Tri-level

Digital input

SADDR /

I

2

S

Digital input

Serial control interface clock input

3-wire mode: serial control interface latch

2-wire mode: device address select

Notes:

1. Undefined inputs should be connected to DVDD or DGND

When DIFFHW=0:

0 = hardware mode



When DIFFHW=1:



Softmute Control

0 = mute active





2-wire mode: device address select

2. Tri-level pins which require the ‘Z’ state to be selected should be left floating (open)

When DIFFHW=0:

0 = hardware mode



When DIFFHW=1:



Softute Control

0 = mute active


NOTE: In DSD Direct mode this is an analogue mute




2-wire mode: device address select w


6

Production Data

WM8742

PIN DESCRIPTION (HARDWARE CONTROL MODE)

PIN NAME TYPE

PCM MODE

DESCRIPTION

DSD DIRECT MODE

1

2

LRCLK /

DSDL

DIN /

DINL

Digital input

Digital input

Audio interface left/right clock input

Audio interface data input

3 BCLK /

DSD64CLK

Digital input Audio interface bit clock input

4 FSEL /

DINR

Digital input

Tri-level

Selects between one of three digital filters – see Table 50

5 MCLK Digital

Master clock input

DSD left audio data in

Unused

64fs system clock input

Unused

Internal pulldown



Analogue Right analogue negative reference

Unused




Digital ground

Digital supply




Output


Output


Output

14 AGND Supply

15 AVDD Supply

Analogue ground

Analogue supply

Left DAC negative output

Output

Left DAC positive output

Output

Left analogue midrail decoupling pin

Output

22 OSR/DSDR



Unused

DSD right audio data in

23 IWO /

DOUT

Digital input

Tri-level

Digital input/output

Controls internal oversampling rate:

0 = low rate

Z = medium rate

1 = high rate

Controls audio interface wordlength – see Table 46

Unused w


7

WM8742

PIN NAME TYPE

PCM MODE

Production Data

DESCRIPTION

DSD DIRECT MODE

24

25

MODE /

LRSEL

MUTEB /

SDOUT

Digital input,

tri-level

Digital input or output:

Internal pull-up

When DIFFHW=0:

0 = hardware mode



When DIFFHW=1:



Softmute Control

0 = mute active


27

DSD

/

DEEMPH

SCLK /

SADDR /

I

2

S

Digital input

Tri-level

Digital input

Digital input

De-emphasis Control


1 = de-emphasis applied

Z = anti-clipping digital filter mode

HW Mode Select:

0 = PCM

1 = DSD Direct

Controls audio interface format – see

Table 46

Notes:

1. Undefined inputs should be connected to DVDD or DGND

2. Tri-level pins who require the ‘Z’ state to be selected should be left floating (open)

When DIFFHW=0:

0 = hardware mode



When DIFFHW=1:



Analogue Mute Control

0 = mute active


Unused

HW Mode Select:

0 = PCM

1 = DSD Direct

Unused w


8

Production Data

WM8742

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.

Wolfson Microelectronics tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30

C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30

C / 60% Relative Humidity. Supplied in moisture barrier bag.

MSL3 = out of bag storage for 168 hours at <30

C / 60% Relative Humidity. Supplied in moisture barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

CONDITION

Digital supply voltage, DVDD

Analogue supply voltage, AVDD

Voltage range digital inputs

Voltage range analogue inputs

Master Clock Frequency

Operating temperature range, T

A

Storage temperature

Ambient temperature (supplies applied)

Pb free package body temperature (soldering 10 seconds)

Pb free package body temperature (soldering 2 minutes)

Notes:

1. Analogue and digital grounds must always be within 0.3V of each other.

MIN MAX

-0.3V +4.5V

-0.3V +7V

DGND - 0.3V

AGND - 0.3V

DVDD + 0.3V

AVDD + 0.3V

38.462MHz

-0°C +70°C

-65°C +150°C

-55°C +125°C

+260°C

+183°C

THERMAL PERFORMANCE

PARAMETER SYMBOL CONDITIONS

Thermal resistance – junction to case

Thermal resistance – junction to ambient

θ

JC

θ

JA

°C/W

°C/W w


9

WM8742

Production Data

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL CONDITIONS

Digital supply range

Analogue supply range

Ground

Difference DGND to AGND

Analogue operating current

Digital operating current

Analogue standby current

Digital standby current I

I

I

I

AVDD

DVDD

AVDD (Standby)

DVDD (Standby)

AVDD = 5V

DVDD = 3.3V

AVDD = 5V

Clocks stopped

DVDD = 3.3V

Clocks stopped

0 V

55

40 mA mA

45 mA

1.5 mA

ELECTRICAL CHARACTERISTICS

TEST CONDITIONS

AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, T

A stated.

= +25 o

C, 1kHz test signal, fs = 48kHz, MCLK = 512fs unless otherwise

Digital Logic Levels

Input LOW level

Input HIGH level

Output LOW level

Output HIGH level

DSD Input Characteristics

DSD reference level

DAC Performance

Signal to Noise Ratio

(Note 1)

Dynamic Range

(Note 2)

Total Harmonic Distortion

(Note 2)

Channel Separation

Channel Level Matching

Channel Phase Deviation

Power Supply Rejection

Ratio

V

IL

V

IH

V

OL

V

OH

I

OL

= 2mA

I

OH

= 2mA

0.7 x DVDD

0.9 x DVDD

0.3 x DVDD

0.1 x DVDD

V

V

V

V

DSD Direct or DSD Plus Mode

SNR A-weighted mono

@ fs = 48kHz

A-weighted stereo

@ fs = 48kHz

A-weighted stereo

@ fs = 96kHz

A-weighted stereo

@ fs = 192kHz

Non-weighted stereo

@ fs = 48kHz

DNR A=weighted,

-60dB full scale input

THD Mono 0dB @ fs = 48kHz

Stereo 0dB @ fs = 48kHz



0

50

118 123 dB

-100

-100

-100

-100

dB

DSD

% dB dB dB dB dB

PSRR 100mVpp at 1kHz

20Hz to 20kHz 100mVpp

-80

-67 dB dB w


10

Production Data

WM8742

TEST CONDITIONS

AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, T

A

= +25 o

C, 1kHz test signal, fs = 48kHz, MCLK = 512fs unless otherwise stated.

Internal Analogue Filter

Bandwidth

Passband edge response

Analogue Output Levels

PCM full scale differential output level

DSD Direct differential output level

DSD Plus differential output level

Minimum resistance load

DSD

DSD

input

input

474

2

0.948

0.991 kHz

V

V

V

RMS

RMS

RMS

To midrail or AC coupled 2 kΩ

Maximum capacitance load

Output DC level

Reference Levels

Potential divider resistance

AVDD to VMIDL/VMIDR and

VMIDL/VMIDR to AGND

Voltage at VMIDL/VMIDR

AVDD/2 V

Notes:

1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth.

2. All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher THD and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. w


11

WM8742

MASTER CLOCK TIMING

Production Data

Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T

A

= +25 o

C

Master Clock Timing Information

MCLK Master clock pulse width high

MCLK Master clock pulse width low

MCLK Master clock cycle time

MCLK Duty cycle

Table 1 MCLK Timing Requirements

t

MCLKH t

MCLKL t

MCLKY

PCM DIGITAL AUDIO INTERFACE TIMINGS

10

10 ns ns

27 ns

40:60 60:40

Figure 2 Digital Audio Data Timing

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T

A

= +25 o

C, fs = 48kHz, MCLK = 256fs unless otherwise stated.

Audio Data Input Timing Information

BCLK cycle time

BCLK pulse width high

BCLK pulse width low

LRCLK set-up time to BCLK rising edge t

BCY t

BCH t

BCL t

LRSU t

LRH

LRCLK hold time from

BCLK rising edge

DIN set-up time to BCLK rising edge

DIN hold time from BCLK rising edge t t

DS

DH

Table 2 Digital Audio Interface Timing Requirements

w

40

16

16

8

8

8

8 ns ns ns ns ns ns ns


12

Production Data

DSD AUDIO INTERFACE TIMINGS

D[n-1]

DSD[0:1]

DSDCLK64

t

DC t

DS

D[n] t

64CY t

64L

Figure 3 DSD Audio Timing - Normal Mode

t

DH

D[n+1]

WM8742

t

64H

Figure 4 DSD Audio Timing - Phase Modulated Mode

Test Conditions

DVDD = 3.3V, GND = 0V, T

A

= +25 o

C, fs = 44.1kHz, DSDCLK64 = 64fs unless otherwise stated.

Audio Data Input Timing Information

DSDCLK64 cycle time

DSDCLK64 pulse width high t

64CY t

64H t

64L

DSDCLK64 pulse width low

DSD[0:1] set-up time to

DSDCLK64 rising edge t

DSN t

DHN

DSD[0:1] hold time from

DSDCLK64 rising edge

Difference in edge timing of

DSD[0:1] to DSDCLK64 t

DC

Table 3 DSD Audio Interface Timing Requirements

20

20

354.3 ns

140 ns

140 ns ns ns ns w


13

WM8742

CONTROL INTERFACE TIMING – 3-WIRE MODE

Production Data

Figure 5 Control Interface Timing - 3-Wire Serial Control Mode

Test Conditions

DVDD = 3.3V, GND = 0V, T

A

= +25 o

C, fs = 48kHz, MCLK = 256fs unless otherwise stated.

SCLK rising edge to LATCH rising edge

SCLK pulse cycle time

SCLK pulse width low

SCLK pulse width high

SDIN to SCLK set-up time

SCLK to SDIN hold time

LATCH pulse width low

LATCH pulse width high

LATCH rising to SCLK rising t

SCS

40 t

SCY t

CSS

80 t

SCL t

SCH

32

32 t

DSU t

DHO

20 t

CSL t

CSH

20

20

20

20

Table 4 Control Interface Timing – 3-Wire Serial Control Mode

ns ns ns ns ns ns ns ns ns w


14

Production Data

CONTROL INTERFACE TIMING – 2-WIRE MODE

WM8742

Figure 6 Control Interface Timing - 2-Wire Serial Control Mode

Test Conditions

DVDD = 3.3V, DGND = 0V, T

A

= +25 o

C, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated.

SCLK Frequency

SCLK Low Pulse-Width

SCLK High Pulse-Width

Hold Time (Start Condition)

Setup Time (Start Condition)

Data Setup Time

SDIN, SCLK Rise Time

SDIN, SCLK Fall Time

Setup Time (Stop Condition)

0 t

SCL

80 t

SCH

80 t

HOL

600 t

CSE

600 t

DSU

100 t

RIS t

FAL t

CSS

600

Data Hold Time

Max Pulse width of spikes that will be suppressed

Table 5 Control Interface Timing – 2-wire Serial Control Mode

t

DHO t

PS

4 ns us ns ns ns ns w


15

WM8742

Production Data

INTERNAL POWER ON RESET CIRCUIT

The WM8742 includes two internal Power On Reset (POR) circuits which are used to reset the digital logic into a default state after power up and to allow the analogue circuits to power-up silently.

The digital POR circuit is powered from DVDD. This circuit monitors DVDD and asserts the internal digital reset if DVDD are below the minimum DVDD threshold which will allow the digital logic to function.

The analogue POR circuit is powered from AVDD. The circuit monitors AVDD, tri-stating the DAC outputs and isolating the internal reference resistor strings from AVDDL and AVDDR until there is sufficient AVDD voltage to allow the analogue DAC stages to function correctly.

Figure 7 AVDD Power up Sequence

Test Conditions

AVDD = 5V, AGND = 0V, T

A

= +25 o

C, T

A_max

= +125 o

C, T

A_min

= -25 o

C, AVDD max

= 5.5V, AVDD min

= 4.5V

Power Supply Input Timing Information

AVDD level to POR rising edge (AVDD rising)

V por_hi

AVDD level to POR falling edge (AVDD falling)

V por_lo

Table 6 Analogue POR Timing

Measured from AGND

Measured from AGND

2.00

1.84

V

V w


16

Production Data

WM8742

Figure 8 DVDD Power up Sequence

Test Conditions

DVDD = 3.3V, DGND = 0V, T

A

= +25 o

C, T

A_max

= +125 o

C, T

A_min

= -25 o

C, DVDD max

= 3.6V, DVDD min

= 3.0V

Power Supply Input Timing Information

DVDD level to POR rising edge (DVDD rising)

V por_hi

DVDD level to POR falling edge (DVDD falling)

V por_lo

Table 7 Digital POR Timing

Measured from DGND

Measured from DGND

1.86

1.83

V

V

In a real application the designer is unlikely to have control of the relative power up sequence of

AVDD and DVDD. The POR circuit ensures a reasonable delay between applying power to the device and Device Ready.

Figure 7 and Figure 8 show typical power up scenarios in a real system. DVDD must be established before the device can be written to. Any writes to the device before device ready will be ignored.

Note: DVDD must be established before the MCLK is started. This will ensure all synchronisation circuitry within the device is fully initialised and ready.

AVDD must be established before the device will output any signal. Whilst the device will output signal as soon as the Internal Analogue PORB indicates device ready, normal operation is not possible until the VMID pin has reached the midrail voltage. w


17

WM8742

Production Data

DEVICE DESCRIPTION

INTRODUCTION

The WM8742 is an ultra high performance DAC designed for digital audio applications. Its range of features makes it ideally suited for use in professional recording environments, CD/DVD players, AV receivers and other high-end consumer audio equipment.

The WM8742 is a complete differential stereo audio digital-to-analogue converter. The system includes a dithered digital interpolation filter, fine resolution volume control and digital de-emphasis, followed by a multi-bit sigma delta modulator and switched capacitor multi-bit stage with differential voltage outputs. The device supports both PCM and DSD digital audio input formats.

The WM8742 includes a configurable digital audio interface support for a 3-wire and 2-wire serial control interface, and a hardware control interface. The software control interface may be asynchronous to the audio data interface; in which case control data will be re-synchronised to the audio processing internally. It is fully compatible with, and an ideal partner for, a range of industry standard microprocessors, controllers and DSPs.

Uniquely, the WM8742 has a large range of high performance low latency advanced digital filters.

The full range of filters is selectable in software mode, and a limited range of filters are available under hardware control. The filters allow users the flexibility to choose characteristics to match their group delay, phase and latency requirements.

Operation using a master clock of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is supported. Sample rates (fs) from 32kHz to 192kHz are allowed, provided the appropriate master clock is input (see

Table 11 for details).

In normal PCM mode, the audio data interface supports right justified, left justified and I

2

S interface formats along with a highly flexible DSP serial port interface.

There are two DSD modes. In DSD Direct mode, the datastream is subjected to the minimum possible processing steps between input and output. In DSD Plus mode, the datastream is converted to PCM and filtered to allow reduction of out of band components. This step also provides additional benefits in allowing access to other PCM features such as volume control and advanced digital filtering.

The device is packaged in a small 28-lead SSOP.

CLOCKING SCHEMES

In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s

Master Clock. The external master system clock can be applied directly through the MCLK input pin with no software configuration necessary for sample rate selection.

MCLK is used to derive clocks for the DAC path in PCM mode. The DAC path consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the DAC.

CONTROL INTERFACE

The WM8742 supports 2-wire and 3-wire serial control, and hardware control. Selection of control mode is made by controlling the state of the MODE pin.

PIN NAME

24 MODE/

DESCRIPTION

0 = Hardware control mode

LRSEL 1 = 3-wire serial control mode

Z = 2-wire serial control mode

Table 8 Control Mode Configuration

w


18

Production Data

WM8742

SOFTWARE CONTROL INTERFACE

The software control interface may be operated using a 2-wire or 3-wire (SPI-compatible) serial interface. When operating under serial control, hardware configuration pins are ignored.

Note: DIFFHW will override all other pins, forcing the device into hardware control mode and differential mono mode.

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

Every rising edge of SCLK clocks in one bit of data on SDIN. A rising edge on CSB latches a complete control word consisting of 16 bits. The 3-wire interface protocol is shown in Figure 9.

Figure 9 3-wire Serial Interface Protocol

Notes:

1. A[6:0] are Control Address Bits

2. D[7:0] are Control Data Bits

3. D[8] is always set to zero

3-WIRE CONTROL INTERFACE DAISY CHAINING

In daisy chaining mode, SDOUT (pin 25) outputs control data sampled on SDIN with a delay of 16

SCLK cycles. This data signal can be used to control another WM8742 in a daisy chain circuit as shown in Figure 10. w

DAC #1 DAC #2 DAC #3

Figure 10 Control Interface Daisy Chaining Setup

To configure devices into daisy chain mode the CSB signal should be driven low while there is a register write to set register bit SDOUT=1. CSB should then be driven high, this sets the first device in daisy chain mode. CSB should then be driven low again while register bit SDOUT is set high.

Setting CSB high again will cause the first register write to be output to the second device from the

SDOUT pin, this sets the second device into daisy chain mode. This method must be repeated for the number of devices in the chain until they are all set into daisy chain mode. Figure 11 shows the protocol for configuring the first two devices in the daisy chain.


19

WM8742

Production Data

Figure 11 Initial Setup of Two WM8742 Devices into Control Interface Daisy Chain Mode

To write to a single device in the chain a complete sequence needs to be written to all the devices.

Devices that do not require a register change must also be written to. The user can choose to write either the same data as the previous write, or write all 1s for the register address and data. All 1s will result in writing to a non-existent register, address 7Fh, preserving the current register settings.

Figure 12 shows an example of how to access three WM8742 devices (the devices have all previously been configured in daisy chain mode):

Figure 12 Daisy Chain Control Interface Example for Three WM8742 Devices

To ensure that only valid data is written to the devices in daisy chain mode, a pull up resistor is used in SDOUT. When connected to the SDIN pin of the next device in the chain, this results in all ones being written to the control interface of that device until the correct daisy chain data is written and latched.

Serial daisy chaining is available only when using 3-wire serial control mode. It is not available in 2wire serial control mode or hardware control mode.

REGISTER ADDRESS BIT LABEL DEFAULT

R8

Mode Control 2

08h

5 SDOUT 0

DESCRIPTION

3 wire Serial Interface Daisy Chaining

0 = No Output

1 = Output on pin 25.

Table 9 Control Interface Daisy Chaining Selection

w


20

Production Data

WM8742

2-WIRE SERIAL CONTROL MODE

The WM8742 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the WM8742).

The WM8742 operates as a slave device on the 2-wire control bus. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8742 and the R/W bit is ‘0’, indicating a write, then the

WM8742 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’, the WM8742 returns to the idle condition and wait for a new start condition and valid address.

Once the WM8742 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8742 register address plus the first bit of register data). The WM8742 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the

WM8742 acknowledges again by pulling SDIN low.

The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.

After receiving a complete address and data sequence the WM8742 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device reverts to the idle condition.

Figure 13 2-wire Serial Control Interface

The WM8742 device address can be configured between two options. This is selected by the

SADDR pin.

PIN NAME

28 CSB/

SADDR/I

2

S

DESCRIPTION

0 = 2-wire address 0011010

1 = 2-wire address 0011011

Table 10 2-wire Serial Control Mode Address Selection

DIGITAL AUDIO INTERFACE

PCM MODE

There are a number of valid PCM data input modes. Two channel and one channel differential mono modes can be selected by serial or hardware control. It is also possible to bypass the WM8742 digital filters and apply a signal at a rate 8fs (where fs is the sampling rate) directly to the switched capacitor stage. w


21

WM8742

Production Data

PCM DIGITAL AUDIO INTERFACE

Audio data is applied to the DAC system via the Digital Audio Interface. Five popular interface formats are supported:



Left Justified mode



Right Justified mode



I

2

S mode



DSP mode A



DSP mode B

All five formats require the MSB to be transmitted first, and support word lengths of 16, 20, 24 and 32 bits, with the exception that 32 bit data is not supported in right justified mode. DIN and LRCLK may be configured to be sampled on the rising or falling edge of BCLK by adjusting register bits LRP and

BCP.

In left justified, right justified and I

2

S audio interface modes, the digital audio interface receives data on the DIN input pin. Stereo audio data is time multiplexed on DIN, with LRCLK indicating whether the left or right channel is present. LRCLK is also used as a timing reference to indicate the beginning or end of the data words.

The minimum number of BCLK periods per LRCLK period is two times the selected word length.

LRCLK must be high for a period equal to the minimum number of BCLK periods, and low for a minimum of the same period. Any mark-to-space ratio on LRCLK is acceptable provided the above requirements are met.

The WM8742 will automatically detect when data with a LRCLK period of exactly 32 BCLKs is received, and select 16-bit mode. This overrides any previously programmed word length. The operating word length will revert to a programmed value only if a LRCLK period other than 32 BCLKs is detected.

In DSP mode A or DSP mode B, the data is time multiplexed onto DIN. LRCLK is used as a frame sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRCLK period is two times the selected word length. Any mark to space ratio is acceptable on LRCLK provided the rising edge is correctly positioned.

LEFT JUSTIFIED MODE

In left justified mode, the MSB is sampled on the first rising edge of BCLK following a LRCLK transition. LRCLK is high during the left data word and low during the right data word. w

Figure 14 Left Justified Mode Timing Diagram


22

Production Data

WM8742

RIGHT JUSTIFIED MODE

In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK transition.

LRCLK is high during the left data word and low during the right data word.

Figure 15 Right Justified Mode Timing Diagram

I

2

S MODE

In I

2

S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK transition.

LRCLK is low during the left data word and high during the right data word.

Figure 16 I

2

S Mode Timing Diagram

w


23

WM8742

Production Data

DSP MODE A

In DSP mode A, the first bit is sampled on the BCLK rising edge following the one that detects a low to high transition on LRCLK. No BCLK edges are allowed between the data words. The word order is DIN left, DIN right.

Figure 17 DSP Mode A Timing Diagram

DSP MODE B

In DSP mode B, the first bit is sampled on the BCLK rising edge, which detects a low to high transition on LRCLK. No BCLK edges are allowed between the data words. The word order is DIN left, DIN right. w

Figure 18 DSP Mode B Timing Diagram

PCM MODE SAMPLING RATES

The WM8742 supports master clock rates of 128fs to 768fs, where fs is the audio sampling frequency

(LRCLK), typically 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz or 192kHz.

The WM8742 has a master clock detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate. The master clock should be synchronised with LRCLK, although the WM8742 is tolerant of phase differences or jitter on this clock.


24

Production Data

WM8742

SAMPLING

RATE

(LRCLK)

MASTER CLOCK (MCLK) FREQUENCY (MHZ)

32kHz Unavailable Unavailable

44.1kHz Unavailable Unavailable

48kHz Unavailable Unavailable

8.192 12.288 16.384 24.576

11.2896 16.9344 22.5792 33.8688

12.288 18.432 24.576 36.864

Table 11 Typical Relationships Between Master Clock Frequency and Sampling Rate in normal

PCM mode

8FS MODE

Operation in 8FS mode requires that audio data for left and right channels is input separately on two pins. DINR (pin 4) is the input for right channel data and DINL (pin 2) is the input for left channel data. Hardware control of the device is not available.

The data can be input in two formats (left or right justified), selectable by register FMT[1:0], and two word lengths (20 or 24 bit), selectable by register IWL[1:0]. In both modes the data is clocked into the

WM8742 MSB first.

For left justified data the word start is identified by the falling edge of LRCLK. The data is clocked in on the next 20/24 BCLK rising edges. This format is compatible with industry-standard DSPs and decoders such as the PMD100.

Figure 19 8FS Mode Left Justified Timing Requirements

For right justified mode, the data is justified to the rising edge of LRCLK and the data is clocked in on the preceding 20/24 BCLK rising edges before the LRCLK rising edge. This format is compatible with industry standard DSPs and decoders such as the DF1704 or SM5842. w

Figure 20 8FS Mode Right Justified Timing Requirements


25

WM8742

Production Data

In both modes the polarity of LRCLK can be switched using register bit LRP.

8FS MODE SAMPLING RATES

Since the data rate in 8FS mode is much faster than in standard PCM mode, there are restrictions on the MCLK rate that can be used. Specifically, only 512fs and 768fs modes are permitted restricting the sample rate to a maximum of 8x48kHz. The master clock should be synchronised with LRCLK, although the WM8742 is tolerant of phase differences or jitter on this clock.

Unlike in normal PCM mode, the master clock detection circuit does not operate in 8FS mode. The rate must be manually programmed using the control interface.

SAMPLING

RATE

LRCLK

FREQUENCY

(kHz)

MASTER CLOCK (MCLK)

FREQUENCY (MHz)

8fs 512fs 768fs fs

32kHz 256

44.1kHz 352.8

48kHz 384

16.384 24.576

22.5792 33.8688

24.576 36.864

Table 12 Typical Relationships Between Master Clock Frequency and Sampling Rate in 8FS

Mode

AUDIO INTERFACE DAISY CHAINING

In daisy chain mode the DOUT pin outputs the audio data received on the DIN pin but delayed by two times the input word length. When this output is connected to the DIN pin of the next device in the chain, each WM8742 device will simultaneously sample different channel data in the same LRCLK period. Daisy chaining is only available in DSP audio interface mode and is limited by a maximum

BCLK frequency of 24.576MHz.


R8

Mode Control 2

08h

4 DOUT

DESCRIPTION

0 Daisy Chaining Multiple devices – multichannel off one PCM feed.

0 = No Output

1 = Output on pin 23.

Table 13 Daisy Chaining Audio Data Output Control

The following diagram illustrates timing for a daisy chain with 2 WM8742 devices. w

Figure 21 Audio Interface Daisy Chaining Timing


26

Production Data

DSD MODE

WM8742

The WM8742 supports DSD input bitstreams at 64x the oversampling rate. The data is supplied at a rate of 64 bits per normal word clock. In DSD, no word clock is provided.

The WM8742 supports two channels of bitstream or DSD audio. Data bitstreams and the 64fs clock are supplied to pins 1, 22 and 3 respectively. The MODESEL[1:0] register bits control whether the device operates in DSD direct, DSD plus or PCM modes.

DSD DIRECT

In DSD Direct mode the internal digital filters are bypassed, the input bitstream data is subjected to the minimal possible processing and is applied directly to the switched capacitor stage of the DAC system. Using this mode provides the purest possible representation of a DSD stream.

It is normally desirable to use an external analogue post-DAC analogue filter to combine the differential outputs of the DAC and remove high frequency energy from the output. This is particularly important in the case of DSD operation due to the presence of high frequency energy which is a result of the aggressive high order noise shaping used in the creation of the modulated DSD datastream.

DSD PLUS MODE

In DSD Plus mode the DSD data can be filtered in a similar manner to the data in the PCM path. The

DSD Plus filters are selected using register bits DSDFILT[1:0]. DSD Plus mode is not available under hardware control.

Although DSD Plus mode requires that the bitstream is more heavily processed than DSD Direct, the advantage is that DSD Plus mode reduces the high frequency energy which is a result of the aggressive high order noise shaping used in the creation of the modulated DSD datastream. This means that a less aggressive, lower order, analogue filter can be used at the output. Furthermore the slew-rate requirements of the op-amps can be relaxed compared to DSD direct mode, due to the reduction in high frequency energy.

DSD DIGITAL AUDIO INTERFACE

DSD audio data is input to the WM8742 via the DSD digital audio interface. Two interface formats are supported:

 Uni-phase

 Bi-phase

To use this interface apply left data on input pin 1 (LRCLK/DSDL) and pin 22 (OSR/DSDR). A DSD clock is also required, running at 64FS, and should be applied to pin 3 (BCLK/DSD64CLK). w

Figure 22 Uni-phase DSD Mode Timing Diagram


27

WM8742

Production Data

Figure 23 Bi-phase DSD Mode Timing Diagram

SOFTWARE CONTROL MODE

Software control allows access to all features of the WM8742. Selection of control mode is achieved by configuring the state of MODE/LRSEL (pin 24):

PIN NAME

24 MODE/

LRSEL

DESCRIPTION


1 = 3-wire serial control mode


Table 14 Control Mode Configuration

DSD AND PCM MODE SWITCHING

The audio interface mode can be switched between DSD and PCM by writing MODESEL[1:0] in R7.

It is recommended that the chip is forced into a MUTE state before dynamically switching modes.

REGISTER ADDRESS BIT

R7

Mode Control 1

07h

LABEL

[1:0] MODESEL

DEFAULT

00

DESCRIPTION

DSD/PCM mode select :

00 = PCM mode

01 = Direct DSD Operation

10 = DSD plus mode

11 = Unused

Table 15 PCM/DSD Software Mode Selection

PCM DIGITAL AUDIO INTERFACE CONTROL REGISTERS

The PCM digital audio input format is configured by register bits FMT [1:0] and IWL[1:0]:


R5

Format Control

05h

1:0 IWL[1:0] 10

3:2 FMT[1:0] 10

DESCRIPTION

Audio interface input word length select

00 = 16-bit

01 = 20-bit

10 = 24-bit

11 = 32-bit

Audio interface input format select

00 = Right justified

01 = Left justified

10 = I

2

S

11 = DSP

Table 16 Interface Format Controls

Note:

1. In all modes, the data is signed 2's complement. The WM8742 digital filters always input

24-bit data. If the interface is programmed into 32 bits, dither is applied according to

Table 37 before truncation to the internal wordlength.

PD, Rev 4.3, February 2013 w

28

Production Data

WM8742

LRCLK POLARITY

In left justified, right justified or I

2

S modes, the LRP register bit controls the polarity of LRCLK. If this bit is set high, the expected polarity of LRCLK will be the opposite of that shown in Figure 14, Figure

15 and Figure 16. If this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced.


R5

Format Control

05h

4 LRP 0

Table 17 LRCLK Polarity Control

DESCRIPTION

LRCLK polarity select:

0 = normal LRCLK polarity

1 = inverted LRCLK polarity

In DSP modes, the LRP register bit is used to select between DSP mode A and B (see Figure 17 and

Figure 18).


R5

Format Control

05h

4 LRP 0

Table 18 DSP Format Control

DESCRIPTION

DSP format select:

0 = DSP mode A

1 = DSP mode B

BCLK / DSDCLK64 POLARITY

In PCM mode, LRCLK and DIN are sampled on the rising edge of BCLK by default, and should ideally change on the falling edge. Data sources which change LRCLK and DIN on the rising edge of BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in Figure 14, Figure 15, Figure 16, Figure 17 and Figure 18.

In DSD mode, DSDL and DSDR inputs are sampled a fixed delay after a falling 64fs clock edge.

When BCP is set in DSD mode, DSDL and DSDR are sampled a fixed delay after a rising 64fs clock edge.


R5

Format Control

05h

5 BCP 0

Table 19 BCLK Polarity Control

DESCRIPTION

BCLK / DSD64CLK polarity select:

0 = normal polarity

1 = inverted polarity

OVERSAMPLING RATE CONTROL

The user has control of the oversampling ratio of the WM8742, and can set to the device to operate in low, medium or high rate modes. For correct operation of the digital filtering and other processing on the WM8742, the user must ensure the correct value of OSR[1:0] is set at all times.


R7

Mode Control 1

07h

[6:5] OSR[1:0] 00

DESCRIPTION

Oversampling Rate Selection

00 = Low rate (32/44.1/48kHz)

01 = Medium rate (96kHz)

10 = High rate (192kHz)

11 = Unused

Table 20 Oversampling Rate Control

w


29

WM8742

Production Data

MCLK/LRCLK RATIO CONTROL (NORMAL PCM MODE)

The ratio of MCLK/LRCLK can be programmed directly or auto-detected.


R7

Mode Control 1

07h

[4:2] SR[3:0] 000

DESCRIPTION

MCLK to LRCLK sampling rate ratio control (Normal PCM Mode):

000 = auto detect sample rate

001 = 128fs

010 = 192fs

011 = 256fs

100 = 384fs

101 = 512fs

110 = 768fs

111 = reserved

Table 21 MCLK/LRCLK Ratio Control (Normal PCM Mode)

8FS MODE

8FS Mode allows the use of custom digital filters by bypassing the WM8742 internal digital filters.

When MODE8X is set, the PCM data input to the WM8742 is applied only to the digital volume control and then the analogue section of the DAC system, bypassing the digital filters.


R7

Format Control

07h

7 MODE8X 0

DESCRIPTION

8FS mode select:

0 = Normal operation

1 = 8FS mode (digital filters bypassed)

Table 22 8FS Mode Control

MCLK/LRCLK RATIO CONTROL (8FS MODE)

In 8FS mode the choice of clock ratios and sampling rates is limited – see Table 12 for details.

Autodetect of MCLK/LRCLK ratio is not available in 8FS mode and must be set manually by the user for correct operation.


R7

Mode Control 1

07h

[4:2] SR[2:0] 000

DESCRIPTION

MCLK to LRCLK sampling rate ratio control (8FS Mode):

000 = reserved

001 = 512fs

010 = 768fs

011 to 111 = reserved

Table 23 MCLK/LRCLK Ratio Control (8FS Mode)

ATTENUATION CONTROL

Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation is set to 0dB by default but can be set between 0dB and -127.5dB in 0.125dB steps using the ten attenuation control bits LAT[4:0], LAT[9:5], RAT[4:0] and RAT[9:5].

All attenuation registers are double latched allowing new values to be pre-latched to both channels before being updated synchronously. Setting the UPDATE bit on any attenuation write will cause all pre-latched values to be immediately applied to the DAC channels. w


30

Production Data

WM8742

REGISTER

ADDRESS

R0

DACLLSB

Attenuation

00h

BITS LABEL DEFAULT

[4:0] LAT[4:0] 00

Table 25 for details.

DESCRIPTION

R1

DACLMSB

Attenuation

01h

R2

DACRLSB

Attenuation

02h

R3

DACRMSB

Attenuation

03h

5 UPDATE 0 Attenuation data load control for left channel.

0 = Store LAT[4:0] value but don’t update

1 = Store LAT[4:0] and update attenuation on registers 0-3

[4:0] LAT[9:5] 00

25 for details.

5 UPDATE 0 Attenuation data load control for left channel.



[4:0] RAT[4:0] 00


5 UPDATE 0 Attenuation data load control for right channel.

0 = Store RAT[4:0] value but don’t update

1 = Store RAT[4:0] and update attenuation on registers 0-3

[4:0] RAT[9:5] 00

25 for details.

5 UPDATE 0 Attenuation data load control for right channel.



Table 24 Attenuation Control

Note:

1. The UPDATE bit is not latched. If UPDATE=0, the attenuation value will be written to the pre-latch but not applied to the relevant DAC. If UPDATE=1, all pre-latched values and the current value being written will be applied on the next input sample.

DAC OUTPUT ATTENUATION

Registers LAT[9:0] and RAT[9:0] control the left and right channel attenuation. Table 25 shows how the attenuation levels are configured by the 10-bit words. w

000(hex) 0dB

001(hex) -0.125dB

: :

: :

: :

3FE(hex) -127.75dB

3FF(hex) -

dB (mute)

Table 25 Attenuation Control Levels

ATTENUATION CONTROL MODE

Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. Right channels register settings are preserved regardless of the status of ATC.


R4

Volume Control

04h

2 ATC 0

DESCRIPTION

Attenuator Control Mode:

0 = Right channels use Right attenuation

1 = Right Channels use Left

Attenuation

Table 26 Attenuator Control Mode


31

WM8742

Production Data

VOLUME RAMP MODE

There are two ways to change the volume in the WM8742, controlled by VOL_RAMP. When

VOL_RAMP=0, the volume changes in a single step from the current volume setting to the new volume when an update is applied to the gain control registers. When VOL_RAMP=1, the volume is automatically ramped from the current volume setting to the new volume setting when an update is applied to the volume control registers. The speed at which this happens is dependant on the sample rate as shown in Table 27 below:

SAMPLE RATE (kHz)

32

44.1

48

88.2

96

176.4

196

Table 27 Volume Ramp Rates

RAMP RATE (ms/dB)

1.000

0.726

0.667

0.726

0.667

0.726

0.667


R4

Volume Control

04h

0 VOL_

RAMP

0

DESCRIPTION

Volume ramp mode control:

0 = Apply volume change in a single step.

1 = Ramp between current volume setting and new volume setting.

Table 28 Volume Ramp Control

ANTI-CLIPPING DIGITAL ATTENUATION MODE

Audio material is regularly recorded up to 0dB level and heavily compressed. This may cause clipping and occasional distortion when the digital media is applied to a DAC. In order to prevent this in the WM8742, an anti-clipping mode is provided, which attenuates the digital signal by 2dB as it is processed through the digital filters.


R4

Volume Control

04h

1 ATT2DB 0

DESCRIPTION

Anti-clipping mode control:

0 = Off, 0dB attenuation

1 = On, 2dB attenuation applied

Table 29 Anti-Clipping Digital Attenuation Control

DSD PLUS GAIN CONTROL

The gain in the DSD Plus data path can be adjusted. The default setting provides a 1.4Vrms differential output level.


R8

Mode Control 2

6 DSD_

GAIN

0

08h

DESCRIPTION

DSD Plus gain control:

0 = Low gain, 1.4Vrms differential output level

1 = High gain, 2.0Vrms differential output level

Table 30 DSD Plus Gain Control

w


32

Production Data

MUTE MODES

WM8742

0.000

0.020

0.040

0.060

0.080

Time (s)

0.100

0.120

0.140

Figure 24 Application and Release of Soft Mute

Figure 24 shows the application and release of SOFTMUTE for a full amplitude sinusoid being played at 48kHz sampling rate. When SOFTMUTE (lower trace) is asserted, the WM8742 output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output decays towards V

MID

in 1022x4/fs seconds. When SOFTMUTE is de-asserted, the signal gain will return to its previous value.

REGISTER ADDRESS BIT LABEL

R4

PCM Control

04h

Table 31 Soft Mute Control

3 SOFTMUTE

DEFAULT

0

DESCRIPTION

Soft mute select


1 = Soft mute both channels w


33

WM8742

Production Data

ZERO FLAG OUTPUT

The WM8742 has one zero flag output pin, ZFLAG (pin 21). The zero flag feature is only valid for

PCM data.

The WM8742 asserts Logic 1 on the ZFLAG pin when a sequence of more than 1024 zeros is input to the chip. The default value is a logical AND of both left and right channels. Under software control, the user can also set the zero flag pin to respond to either the left channel OR the right channel.

The zero flag pin can be used to control external muting circuits if required.

REGISTER

ADDRESS

R4

Volume Control

04h

BIT LABEL DEFAULT

6:5 ZEROFLR

[1:0]

00

DESCRIPTION

Zero flag output:

00 = Pin assigned to logical AND of

LEFT and RIGHT channels

01 = Pin assigned to LEFT channel

10 = Pin assigned to RIGHT channel

11 = ZFLAG disabled

Table 32 Zero Flag Output

ZFLAG FORCE HIGH CONTROL

It is possible to force the ZFLAG pin to Logic 1 by setting ZFLAG_HI=1 in R7. This is useful in situations where an application processor may require manual control of an external mute circuit.

Setting ZFLAG_HI=0 will allow the ZFLAG pin to function as defined by ZFLAGLR[1:0].


R6

Mode Control 1

06h

LABEL DEFAULT

7 ZFLAG_HI 0

DESCRIPTION

ZFLAG Force High Control


1 = Output Logic 1

Table 33 ZFLAG Force High Control

INFINITE ZERO DETECT

The IZD register configures the operation of the WM8742 analogue mute in conjunction with the zero flag feature. Table 20 shows the interdependency of the MUTEB pin, the IZD register and the zero flag.


R4

Volume Control

04h

LABEL DEFAULT DESCRIPTION

4 IZD 0 IZD control of analogue mute:

0 = Never analogue mute

1 = Analogue mute when ZFLAG set

Table 20 Infinite Zero Detect Control

w


34

Production Data

MUTEB ZFLAG

WM8742

ZDET

DINL

DINR

DAC

SOFT

L&R

ANA

L&R

DSD Direct

Infinite

Zero

Detect

Figure 25 Software Control Mode MUTEB and ZFLAG Configuration

DE-EMPHASIS

Setting the DEEMPH[1:0] register bits enables de-emphasis support in the WM8742 digital filters.

There are three de-emphasis filters, one each for sampling rates of 32kHz, 44.1kHz and 48kHz.


R6

Filter Control

06h

[6:5] DEEMPH

[1:0]

00

DESCRIPTION

De-emphasis mode select:

00 = De-emphasis Off

01 = De-emphasis 32kHz

10 = De-emphasis 44.1kHz


Table 34 De-emphasis Control

OUTPUT PHASE REVERSAL

The REV register bit controls the phase of the output signal. Setting the REV bit causes the phase of the output signal to be inverted.

Note: The REV bit can only be used in stereo mode. When in differential mono mode, the REV bit must remain set as 0.


R5

Format Control

05h

6 REV 0

Table 35 Output Phase Control

DESCRIPTION

Analogue output phase control:

0 = Normal

1 = Inverted w


35

WM8742

Production Data

DIFFERENTIAL MONO MODE

DIFF[1:0] sets the required differential output mode; normal stereo, reversed stereo, mono left or mono right, as shown in Table 36.


R8

Mode Control 2

08h

[3:2] DIFF[1:0] 00

DESCRIPTION

00 = Stereo

10 = Stereo reverse (left and right channels swapped)

01 = Mono left – differential outputs

VOUTLP (17) is left channel.

VOUTLN (16) is left channel inverted.

VOUTRP (12) is left channel inverted.

VOUTRN (13) is left channel.

11 = Mono right – differential outputs.

VOUTLP (17) is right channel inverted.

VOUTLN (16) is right channel.

VOUTRP (12) is right channel.

VOUTRN (13) is right channel inverted.

Table 36 Differential Output Modes

Using these controls a pair of WM8742 devices may be used to build a dual differential stereo implementation with higher performance and differential output.

DITHER

Dither is applied whenever internal truncation occurs. It is also used when a 32 bit input word is applied to the DAC prior to truncation to the internal wordlength. Three types of dither can be selected to allow the sound quality if the device to be optimised.

TDF has a triangular probability density function and causes zero noise modulation i.e. the quantisation noise is invariant to the changes in the signal level. This mode is recommended and is selected by default.

RPDF has a rectangular probability density function and may cause noise modulation.

HPDF has a triangular probability density function with a high pass characteristic, which has a lower noise at low frequencies at the expense of raised noise levels at higher frequencies.

Alternatively the dither can be disabled.


R8

Mode Control 2

[1:0] DITHER

[1:0]

10

08h

DESCRIPTION

Digital filter dither mode select:

00 = dither off

01 = RPDF dither applied in Digital filter

10 = TPDF dither applied in Digital filter

11 = HPDF dither applied in Digital filter

Note: DITHER[1:0] applies only to the dither mode in the Digital filter.

Table 37 Dither Control

w


36

Production Data

WM8742

NORMAL PCM MODE DIGITAL FILTER SELECTION

The WM8742 has a number of advanced digital filters that can be selected in all PCM operation modes (with the exception of 8FS mode).


R6

Filter Control

06h

[2:0] FIRSEL 000

DESCRIPTION

Selects FIR1 filter response

000 = Response 1

001 = Response 2

010 = Response 3

011 = Response 4

100 = Response 5

Table 38 PCM Advanced Digital Filter Selection

Five digital filters are available for selection in each of the three OSR modes (low, medium and high rate) as selected by the OSR bit described in Table 20. It is recommended that the device is muted before the filter response is changed to prevent noise as the filters are reset from appearing on the outputs. A summary of the filter characteristics is given in Table 39 below: w

Low

Medium

High

4

5

1

1

2

3

1

2

3

4

5

2

3

4

5

Table 39 PCM Digital Filter Summary

Linear phase half-band filter for backward compatibility

Minimum phase ‘soft-knee’ filter

Minimum phase half-band filter

Linear phase apodising filter

Minimum phase apodising filter

Linear phase ‘soft-knee’ filter


Linear phase ‘brickwall’ filter



Linear phase ‘soft-knee’ filter


Linear phase ‘brickwall’ filter



For full details of the filter characteristics available in normal PCM mode, please see Table 64 to

Table 66 and Figure 28 to Figure 57.

8FS MODE DIGITAL FILTER

In 8FS mode, the majority of the internal filters are bypassed. In this mode, the data is filtered using only the filter characteristic described by Table 67 and shown in Figure 58 and Figure 59.

DSD PLUS FILTER SELECTION

The WM8742 has a number of compensation filters that can be selected in DSD Plus mode.


R6

Filter Control

06h

[4:3] DSDFILT

[1:0]

00

DESCRIPTION

Selects Compensation Filter response

00 = Response 1

01 = Response 2

10 = Response 3

11 = Response 4

Table 40 DSD Plus Digital Filter Selection


37

WM8742

Production Data

It is recommended that the device is muted before the filter response is changed to prevent noise as the filters are reset from appearing on the outputs.

Full details of these filters are described in Table 68 and Figure 60 to Figure 67.

DSD DIRECT DIGITAL FILTERS

The DSD Direct filters have been designed to provide the minimal of processing to the data with no decimation, re-quantisation or noise-shaping, in order to preserve the signal integrity as much as possible. As a result the filters have a wide bandwidth and a very gradual attenuation. It is recommended that whichever DSD Direct filter is chosen it is augmented by analogue post-DAC filtering in order to adhere to the Scarlet-Book SACD standard.

There are a total of four DSD Direct filter responses available, controlled by two register bits as described in Table 41 below:


R32

Additional Control 1

20h

LABEL

NOTCH

DEFAULT

0 DSD_NO_ 0

1 DSD_

LEVEL

1

DESCRIPTION

DSD Direct 8fs Notch Filter

0: Enable 8fs notch filter

1: Disable 8fs notch filter

DSD Direct Filter Gain

0: High gain

1: Low gain

Table 41 DSD Direct Digital Filter Selection

DSD MUTE CONTROL

In DSD Direct mode, an analogue mute can be applied at the output of the DAC. This is controlled by register bit AMUTE.


R4

Volume Control

04h

7 AMUTE 0

DESCRIPTION

DSD Direct mute control:

0 = mute off

1 = mute on

Table 42 DSD Analogue Mute Control

POWER SAVING STANDBY CONTROL

Setting the PWDN register bit immediately connects all outputs to V

MID and resets the digital sections of the DAC system including the DLL, the audio interface and the DSP. Input data samples are not preserved, but all control register settings are maintained. When PWDN is cleared the WM8742 will repeat its power-on initialisation sequence.


R5

Format Control

05h

7 PWDN

DESCRIPTION

0

Power Down Mode Select:

0 = Normal Mode

1 = Power Down Mode

Table 43 Powerdown Control

w


38

Production Data

WM8742

HARDWARE CONTROL MODE

When the MODE pin is held ‘low’ the WM8742 is set to hardware control mode and a limited feature set can be configured.

PIN NAME

24

MODE/

LRSEL

DESCRIPTION


1 = 3-wire serial control mode


Table 44 MODE/LRSEL Hardware Control Pin Function

DSD AND PCM MODE SWITCHING

The audio interface mode can be switched between DSD Direct and PCM by controlling the state of pin DSD. It is recommended that the chip is forced into a MUTE state before dynamically switching modes.

PIN NAME

27 SCLK/DSD

DESCRIPTION

0 = PCM Mode

1 = DSD Direct Mode

Table 45 SCLK/DSD Hardware Control Pin Function

AUDIO INPUT FORMAT

Under hardware control, it is possible to select between four different modes of operation for the PCM audio interface.

PIN NUMBER 28 23

NAME CSB/SADDR/I2S IWO/DOUT

DESCRIPTION

STATUS

0

0

0

1

16-bit right justified

24-bit right justified

1 0 24-bit left justified

1 1

2

S

Table 46 CSB/SADDR/I2S and IWO/DOUT Hardware Control Pin Function

w


39

WM8742

Production Data

OVERSAMPLING RATE CONTROL

The user has control of the oversampling ratio of the WM8742, and can set to the device to operate in low, medium or high rate modes. For optimum operation of the digital filtering and other processing on the WM8742 in PCM hardware mode, the user must ensure the correct value of OSR is set at all times. Table 47 shows the correct settings:

PIN NAME

22 OSR/DSDR

DESCRIPTION

Oversampling Rate Selection

0 = Low rate (32/44.1/48kHz)

Z = Medium rate (88.2/96kHz)

1 = High rate (176.4/192kHz)

Table 47 OSR/DSDR Hardware Control Pin Function

MUTE PIN

A soft mute can be applied to the WM8742 in the digital domain in all PCM. A logic low on the

MUTEB pin will cause the attenuation to ramp to infinite attenuation at a rate of 1022x(4/fs). Setting

MUTEB high will return the signal gain to its previous value. Figure 26 shows the soft mute characteristic.

In DSD Direct mode the MUTEB pin controls the analogue mute in the DAC. This analogue mute is a

‘hard’ mute and is applied and released as soon as the MUTEB pin is toggled.

PIN NAME

25

MUTEB/

SDOUT

DESCRIPTION

Mute control

0 = Mute on (no output)

1 = Mute off (normal operation

Table 48 MUTEB Hardware Control Pin Function

w

0 0.02

0.04

0.06

Time (s)

0.08

Figure 26 Hardware Control Mode Soft Mute Characteristic

0.1

0.12

0.14


40

Production Data

WM8742

ZERO FLAG

In hardware control mode the ZFLAG pin asserts when 1024 consecutive zero samples are applied to the left and right channels of the WM8742 when in PCM mode. In DSD mode, the ZFLAG has no function.

In hardware mode there is no access to the infinite zero detect and so there is no automute function.

If this functionality is required, software mode must be used. Figure 27 shows the MUTEB and

ZFLAG configuration.

Figure 27 Hardware Control Mode MUTEB and ZFLAG Configuration

DE-EMPHASIS CONTROL AND ANTI-CLIPPING MODE

In hardware control mode, de-emphasis is supported with a maximum error of +1.5dB at a sampling rate of 44.1kHz.

Audio material is regularly recorded up to 0dB level and heavily compressed. This causes clipping and distortion when the digital media is applied to a DAC. In order to prevent this in the WM8742, an anti-clipping mode is provided, which attenuates the digital signal by 2dB as it is processed through the digital filters.

Under hardware control de-emphasis and the anti-clipping mode are only available when using PCM mode.

PIN NAME

26 SDIN/

DEEMPH

DESCRIPTION

Deemphasis Control

0 = De-emphasis off

1 = De-emphasis on

Z = Digital filter anti-clipping mode

Table 49 DEEMPH Hardware Control Pin Function

w


41

WM8742

Production Data

DIGITAL FILTER SELECTION

The WM8742 includes a wide range of digital filters. A limited set of these can be selected in hardware control mode as listed in Table 50. Full details of each digital filter response can be found in section PCM Digital Filter Selection, from page 37.

PIN NAME

4 FSEL/

DINR

DESCRIPTION

Digital filter selection

(32/44.1/48kHz):

0 = Response 1

1 = Response 5

Z = Response 4

Digital filter selection (88.2/96kHz and 176.4/192kHz):

0 = Response 1

1 = Response 3

Z = Response 2

Table 50 FSEL/DINR Hardware Control Pin Function

There is no choice of digital filters in DSD Direct mode – only the very minimal filtering described in

Figure 72 and Figure 73 is available.

DIFFERENTIAL MONO MODE

If DIFFHW (pin 6) is held to Logic 1, hardware controlled differential mono mode is selected. This overrides any other control pin or register bit. Differential mono mode allows the user to build a dual differential stereo DAC implementation with higher performance and differential output. DIFFHW is used in conjunction with MODE/LRSEL (pin 24) to define a ‘left’ or ‘right’ DAC as shown in Table 51.

PIN NUMBER 6

0

0

0

24

0

Z

1

DESCRIPTION

Hardware control (stereo)

2-wire Software Control

3-wire software control)

VOUTLP = left channel

VOUTLN = left channel inverted

VOUTRP = left channel inverted

VOUTRN = left channel

VOUTLP = right channel inverted

VOUTLN = right channel

VOUTRP = right channel

VOUTRN = right channel inverted

Table 51 DIFFHW and MODE/LRSEL Hardware Control Pin Functions

Differential mono mode is available for all PCM hardware controlled modes and DSD Direct hardware mode. w


42

Production Data

WM8742

OVERVIEW OF FUNCTIONS

The WM8742 has many modes of operation, and certain restrictions on what functions are available in which modes. Table 52 gives an overview of the functions available in hardware and software control modes across all modes of operation:

Selectable Digital Filters

Deemphasis Support

Adjustable DSP Dither

Differential Mono Mode

Digital Softmute

Analogue Mute

Zero Detect (ZFLAG)

Automute Function

Anti-Clipping Mode

Digital Attenuation

Powerdown Mode

Audio Interface Daisy Chain

3-wire Software Interface

Daisy Chain

PCM

5

























SOFTWARE MODE

DSD

PLUS MODE



























4

























Table 52 Comparison of Functions Available across Operating Modes



= function available



= function not available

DSD

DIRECT

4

























3

























HARDWARE MODE

NORMAL

PCM

DSD

DIRECT

























 w


43

WM8742

REGISTER MAP

Reg

0

1

2

3

Name

DACLLSB

Attenuation

DACLMSB

Attenuation

DACRLSB

Attenuation

DACRMSB

Attenuation

Addr

00h

01h

02h

03h

Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3

4 Volume

0 AMUTE ZEROFLR[1:0] IZD

SOFT

MUTE

Bit 2 Bit 1

LAT[4:0]

LAT[9:5]

RAT[4:0]

RAT[9:5]

5 Format

0 PWDN FMT[1:0]

Production Data

Bit 0 Default

0x000

0x000

0x000

0x000

0x000

IWL[1:0]

0x00A

6 Filter

0 ZFLAG_HI DEEMPH[1:0] DSDFILT[1:0]

7 Mode Control 1 07h

8 Mode Control 2 08h

0 MODE8X OSR[1:0] SR[2:0]

FIRSEL[2:0]

0x000

MODESEL[1:0]

0x000

32

Additional

Control 1

20h

RESET

0x000

DSD_NO_

NOTCH

0x000 w


44

Production Data

REGISTER

ADDRESS

R0

DACLLSB

Attenuation

00h

5 UPDATE

25 for details.

0

Attenuation data load control for left channel.



Table 53 R0 DACL LSB Attenuation Control Register

WM8742

REGISTER

ADDRESS

R1

DACLMSB

Attenuation

01h

5 UPDATE for details.

0 Attenuation data load control for left channel.



Table 54 R1 DACL MSB Attenuation Control Register

REGISTER

ADDRESS

R2

DACRLSB

Attenuation

02h

5 UPDATE


0 Attenuation data load control for right channel.



Table 55 R2 DACR LSB Attenuation Control Register

REGISTER

ADDRESS

R3

DACRMSB

Attenuation

03h

5 UPDATE for details.

0 Attenuation data load control for right channel.



Table 56 R3 DACR MSB Attenuation Control Register

w


45

WM8742

REGISTER

ADDRESS

R4

Volume

Control

04h

Production Data

0 VOL_RAMP

1 ATT2DB

2 ATC

3 SOFTMUTE

4 IZD

6:5 ZEROFLR

[1:0]

7 AMUTE

0

0 Anti-clipping mode control. Attenuates PCM gain path by 2 dB:

0: 0dB gain

1: -2dB gain

0

Ramps volume from existing attenuation setting to new setting when

UPDATE applied.

0: Step volume change

1: Ramp volume change

Attenuator Control Mode:

0 = Right channels use Right attenuation

1 = Right Channels use Left Attenuation

0

0 Enables infinite zero detect (detects 1024 zeros on input):

0 = Disable infinite zero detect

1 = Enable infinite zero detect

00

Soft mute select

0: Normal Operation

1: Soft mute both channels

Zero flag output:

00 = Pin assigned to logical AND of LEFT and RIGHT channels

01 = Pin assigned to LEFT channel

10 = Pin assigned to RIGHT channel

11 = ZFLAG disabled

0 Applies analogue mute in DSD mode


1 = Analogue mute applied

Table 57 R4 Volume Control Register

REGISTER

ADDRESS

R5

Format

Control

05h

[1:0] IWL[1:0]

[3:2] FMT[1:0]

4 LRP

5

6

BCP

REV

7 PWDN

10 Audio interface input word length.

00 = 16-bit

01 = 20-bit

10 = 24-bit

11 = 32-bit

10 Audio data format select.

00 = right justified mode

01 = left justified mode

10 = I2S mode

11 = DSP mode

0 Polarity select for LRCLK/DSP mode select.

0 = normal LRCLK polarity/DSP mode A

1 = inverted LRCLK polarity/DSP mode B

0

0

BCLK / DSD64CLK polarity select:

0 = normal polarity

1 = inverted polarity

Analogue output phase control:

0 = Normal

1 = Inverted

0 Power Down Mode Select:

0 = Normal Mode

1 = Power Down Mode

Table 58 R5 Format Control Register

w


46

Production Data

REGISTER

ADDRESS

R6

Filter Control

06h

[2:0] FIRSEL 000 Select advanced digital filter response:

000 = Response 1

001 = Response 2

010 = Response 3

011 = Response 4

100 = Response 5

[4:3] DSDFILT 00

[6:5] DEEMPH

[1:0]

00

Select DSD compensation filter response:

00 = Response 1

01 = Response 2

10 = Response 3

11 = Response 4

De-emphasis mode select:

00 = De-emphasis Off


10 = De-emphasis 44.1kHz


7 ZFLAG_HI 0 ZFLAG Force High Control


1 = Output Logic 1

Table 59 R6 Filter Control Register

WM8742

REGISTER

ADDRESS

R7

Mode Control 1

07h

[1:0] MODESEL

[1:0]

[4:2] SR[3:0]

[6:5] OSR[1:0]

7 MODE8X

00

DSD/PCM mode select.

00 = PCM mode

01 = DSD Direct mode

10 = DSD Plus mode

11 = Unused

000 MCLK to LRCLK sampling rate ratio control:

000 = auto detect sample rate

001 = 128fs

010 = 192fs

011 = 256fs

100 = 384fs

101 = 512fs

110 = 768fs

00 Selects low, medium or high sample rate mode for filter selection

(equivalent to OSR pin functionality in Hardware Mode)

00 = Low rate (32/44.1/48kHz)

01 = Medium rate (96kHz)

10 = High rate (192kHz)

11 = Unused

0 8FS mode select:


1 = 8FS mode (digital filters bypassed)

Table 60 R7 Mode Control Register 1

w


47

WM8742

REGISTER

ADDRESS

R8

Mode Control 2

08h

[1:0] DITHER[1:0]

[3:2] DIFF[1:0]

4 DOUT

5 SDOUT

6 DSD_GAIN

Production Data

10

00

ALU dither mode select:

00 = dither off

01 = RPDF dither applied in ALU

10 = TPDF dither applied in ALU

11 = HPDF dither applied in ALU

Note: DITHER[1:0] applies only to the dither mode in the ALU.

00 = Stereo

10 = Stereo reverse (left and right channels swapped)

01 = Mono left – differential outputs

VOUTLP is left channel.

VOUTLN is left channel inverted.

VOUTRP is left channel inverted.

VOUTRN is left channel.

11 = Mono right – differential outputs.

VOUTLP is right channel inverted.

VOUTLN is right channel.

VOUTRP is right channel.

VOUTRN is right channel inverted.

0 Daisychaining Mode. Audio data output control:

0 = No audio data daisychaining

1 = Audio data output on pin 23

0 Daisychaining Mode. Control data output control:

0 = No control data daisychaining

1 = Control data output on pin 25

0 DSD Plus gain control:

0 = Low gain, 1.4Vrms differential output level

1 = High gain, 2.0Vrms differential output level

Table 61 R8 Mode Control Register 2

REGISTER

ADDRESS

R9

Software reset

09h

[7:0] RESET 00000000 Software reset. Writing to the register resets the entire chip, including

Table 62 R9 Software Reset Control Register

the register map.

REGISTER

ADDRESS

R32

Additional

Control 1

20h

0 DSD_NO_

NOTCH

0 DSD Direct 8fs Notch Filter

0: Enable 8fs notch filter

1: Disable 8fs notch filter

0: High Gain

1: Low Gain

Table 63 R32 Additional Control 1

w


48

Production Data

DIGITAL FILTER CHARACTERISTICS

PCM MODE FILTER CHARACTERISTICS

Low Rate (32/44.1/48kHz) PCM Filter Response 1

Passband

 0.000057dB

Passband Ripple

Stopband Attenuation

Attenuation at fs/2

Group Delay


Passband

 0.000036 dB

Passband Ripple

-111.8


Attenuation at fs/2

Group Delay

Fs/2


Passband

 0.000058 dB

Passband Ripple

-111.1


Attenuation at fs/2

Fs/2

Group Delay


Passband

 0.000066 dB

Passband Ripple

-110.3


Attenuation at fs/2

Fs/2

Group Delay


Passband

 0.000041 dB

Passband Ripple

-110.4


Attenuation at fs/2

Group Delay

Fs/2

Table 64 Low Rate PCM Filter Characteristics

-111.8

WM8742

-6.02

43

TYP MAX UNIT

0.454fs

0.000057 dB dB dB fs

-28.07

8

-6.43

7

-116.19

47

-112.45

8

0.408fs


0.454fs


0.417fs


0.417fs

0.000041 dB dB dB fs w


49

WM8742

Medium Rate (88.2/96kHz) PCM Filter Response 1

Passband

 0.000021 dB

Passband Ripple


Attenuation at fs/2

Fs/2

Group Delay


Passband

 0.000014 dB

Passband Ripple

-120.3


Attenuation at fs/2

Fs/2

Group Delay


Passband

Passband Ripple

 0.000048 dB

-120.8


Attenuation at fs/2

Fs/2

Group Delay


Passband

 0.000021 dB

Passband Ripple

-115.5


Attenuation at fs/2

Fs/2

Group Delay


Passband

 0.000023 dB

Passband Ripple

-120.0


Attenuation at fs/2

Fs/2

Group Delay

Table 65 Medium Rate PCM Filter Characteristics

-122.5

Production Data

TYP

-120.41

17

-127.96

9

-116.89

48

MAX UNIT

0.208fs


0.208fs


0.417fs


-126.82

9

-130.52

8

0.208fs


0.208fs

0.000023 dB dB dB fs w


50

Production Data

High Rate (176.4/192kHz) PCM Filter Response 1

Passband

Passband Ripple

 0.000010 dB


Attenuation at fs/2

Fs/2

Group Delay


Passband

 0.000031 dB

Passband Ripple

-120.0


Attenuation at fs/2

Fs/2

Group Delay


Passband

Passband Ripple

 0.000873 dB

-120.0


Attenuation at fs/2

Fs/2

Group Delay


Passband

 0.000015 dB

Passband Ripple

-110.1


Attenuation at fs/2

Fs/2

Group Delay


Passband

 0.000001 dB

Passband Ripple

-120.0


Attenuation at fs/2

Fs/2

Group Delay

Table 66 High Rate PCM Filter Characteristics

8FS MODE FILTER CHARACTERISTICS

-122.8

8FS Mode Filter

Passband

Passband Ripple

 0.000021 dB

-3dB point

Filter Cut-off

Group Delay

Table 67 8FS Mode Filter Characteristics

WM8742

TYP

-127.5

10

-124.93

4

-112.67

31

MAX UNIT

0.104fs


0.104fs


0.400fs


-120.58

6

-128.58

18

0.104fs


0.104fs


TYP

121.13

5

MAX UNIT

0.455 fs

0.000021 dB kHz fs w


51

WM8742

DSD PLUS MODE FILTER CHARACTERISTICS

DSD Plus Filter Response 1

Passband

 0.020423 dB

Passband Ripple


Filter Cut-off

-3dB point

Group Delay


Passband

 0.011308dB

Passband Ripple


Filter Cut-off

Group Delay


Passband

-3dB point

 0.019762 dB

Passband Ripple


Filter Cut-off

-3dB point

Group Delay


Passband

Passband Ripple

 0.004140 dB


Filter Cut-off

-3dB point

Group Delay

Table 68 DSD Plus Filter Characteristics

-26.28

-48.05

-38.51

-44.52

Production Data

58.91

71

TYP MAX UNIT

22.48 kHz

0.020423 dB kHz dB kHz fs

49.83

127

49.74

46

49.78

127

23.04 kHz

0.011308 dB kHz dB kHz fs

27.35 kHz

0.019762 dB kHz dB kHz

Fs

20.24 kHz

0.004140 dB kHz dB kHz fs w


52

Production Data

PCM MODE FILTER RESPONSES

0

-50

-100

-150

4

0.02

0

-0.02

-0.04

0.1

0.08

0.06

0.04

-0.06

-0.08

-0.1

0 0.1

0.2

0.3

Frequency (fs)

Figure 29 Low Rate PCM Filter 1 Ripple

-200

0 0.5

1 1.5

2

Frequency (fs)

2.5

3 3.5

Figure 28 Low Rate PCM Filter 1 Frequency Response

0

-50

-100

-150

-200

0 0.5

1 1.5

2

Frequency (fs)

2.5

3 3.5


4

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.1

0.2

0.3

Frequency (fs)


0

-50

-100

-150

-200

0 0.5

1 1.5

2

Frequency (fs)

2.5

3 3.5


4

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.1

0.2

0.3

Frequency (fs)


0.4

WM8742

0.4

0.4

0.5

0.5

0.5

w


53

WM8742

0

-50

-100

-150

4

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.1

0.2

0.3

Frequency (fs)


-200

0 0.5

1 1.5

2

Frequency (fs)

2.5

3 3.5


0

-50

-100

-150

4

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.1

0.2

0.3

Frequency (fs)


-200

0 0.5

1 1.5

2

Frequency (fs)

2.5

3 3.5


0

-50

-100

-150

-200

0 0.5

1

Frequency (fs)

1.5

Figure 38 Medium Rate PCM Filter 1 Frequency Response

2

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.05

0.1

0.15

Frequency (fs)

Figure 39 Medium Rate PCM Filter 1 Ripple

Production Data

0.4

0.4

0.2

0.5

0.5

0.25

w


54

Production Data

0

-50

-100

-150

-200

0 0.5

1

Frequency (fs)

1.5


2

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.05

0.1

0.15

Frequency (fs)


0

-50

-100

-150

-200

0 0.5

1

Frequency (fs)

1.5


2

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.05

0.1

0.15

Frequency (fs)


0

-50

-100

-150

-200

0 0.5

1

Frequency (fs)

1.5


2

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.05

0.1

0.15

Frequency (fs)


0.2

0.2

0.2

WM8742

0.25

0.25

0.25

w


55

WM8742

0

-50

-100

-150

-200

0 0.5

1

Frequency (fs)

1.5


2

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.05

0.1

0.15

Frequency (fs)


Production Data

0.2

0.25

0

-50

-100

-150

-200

0 0.2

0.4

0.6

Frequency (fs)

0.8

Figure 48 High Rate PCM Filter 1 Frequency Response

1

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.025

0.05

0.075

Frequency (fs)

Figure 49 High Rate PCM Filter 1 Ripple

0.1

0

-50

-100

-150

-200

0 0.2

0.4

0.6

Frequency (fs)

0.8


1

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.025

0.05

0.075

Frequency (fs)


0.1

0.125

0.125

0.15

0.15

w


56

Production Data

0

-50

-100

-150

-200

0 0.2

0.4

0.6

Frequency (fs)

0.8


1

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.025

0.05

0.075

Frequency (fs)


0.1

0

-50

-100

-150

-200

0 0.2

0.4

0.6

Frequency (fs)

0.8


1

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.025

0.05

0.075

Frequency (fs)


0.1

0

-50

-100

-150

-200

0 0.2

0.4

0.6

Frequency (fs)

0.8


1

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.025

0.05

0.075

Frequency (fs)


0.1

WM8742

0.125

0.15

0.125

0.125

0.15

0.15

w


57

WM8742

8FS MODE FILTER RESPONSES

0

-50

-100

-150

-200

0 0.5

1 1.5

2

Frequency (fs)

2.5

3

Figure 58 8FS Mode Filter Frequency Response

3.5

DSD PLUS MODE FILTER RESPONSES

4

0.1

0.08

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.1

0 0.1

0.2

0.3

Frequency (fs)

Figure 59 8FS Mode Filter Ripple

15

0

10

-20

5

-40

0

-60

-5

-80

-10

-100

0 50 100

Frequency (kHz)

150

Figure 60 DSD Plus Mode Filter 1 Frequency Response

200

-15

0 5 10 15

Frequency (kHz)

Figure 61 DSD Plus Mode Filter 1 Ripple

15

0

10

-20

5

-40

0

-60

-5

-80

-10

-100

0 50 100

Frequency (kHz)

150


200

-15

0 5 10 15

Frequency (kHz)


Production Data

0.4

20

20

0.5

25

25 w


58

Production Data

0

15

10

-20

-40

-60

5

0

-5

-80

-10

-100

0 50 100

Frequency (kHz)

150


200

-15

0 5 10 15

Frequency (kHz)


15

0

10

-20

5

-40

0

-60

-5

-80

-10

-100

0 50 100

Frequency (kHz)

150


200

-15

0 5 10 15

Frequency (kHz)


DSD DIRECT MODE FILTER RESPONSES

15

0

10

-20

5

-40

0

-60

-5

-80

-10

20

20

WM8742

25

25

-100

0 50 100 150 200 250

Frequency (kHz)

300 350 400

Figure 68 DSD Direct Mode Standard Low Gain Filter

Frequency Response

-15

0 5 10 15

Frequency (kHz)

20 25

Figure 69 DSD Direct Mode Standard Low Gain Filter Ripple

(Normalised)

w


59

WM8742

Production Data

0

-20

-40

-60

-80

25

20

15

10

5

0

-5

-10

-15

-20

-100

0 50 100 150 200 250

Frequency (kHz)

300 350 400

Figure 70 DSD Direct Mode Standard High Gain Filter


-25

0 5 10 15

Frequency (kHz)

20 25

Figure 71 DSD Direct Mode Standard High Gain Filter Ripple

(Normalised)

15

0

10

-20

5

-40

0

-60

-5

-80

-10

-100

0 50 100 150 200 250

Frequency (kHz)

300 350 400

Figure 72 DSD Direct Mode 8fs Notch Low Gain Filter


-15

0 5 10 15

Frequency (kHz)

20 25

Figure 73 DSD Direct Mode 8fs Notch Low Gain Filter Ripple

(Normalised)

0

-20

-40

-60

-80

20

15

10

5

0

-5

-10

-15

-100

0 50 100 150 200 250

Frequency (kHz)

300 350 400

Figure 74 DSD Direct Mode 8fs Notch High Gain Filter


-20

0 5 10 15

Frequency (kHz)

20 25

Figure 75 DSD Direct Mode 8fs Notch High Gain Filter Ripple

(Normalised)

w


60

Production Data

DEEMPHASIS FILTER RESPONSES

0.0

-2.0

-4.0

-6.0

-8.0

-10.0

0 5000 10000

Frequency (Hz)

15000 20000

Figure 76 De-emphasis Frequency Response (32kHz)

0.4

0.3

0.2

0.1

0.0

-0.1

-0.2

-0.3

-0.4

0 5000 10000

Frequency (Hz)

Figure 77 De-emphasis Error (32kHz)

15000

WM8742

20000

0.0

-2.0

-4.0

-6.0

-8.0

-10.0

0 5000 10000

Frequency (Hz)

15000 20000

Figure 78 De-emphasis Fequency Response (44.1kHz)

0.4

0.3

0.2

0.1

0.0

-0.1

-0.2

-0.3

-0.4

0 5000 10000

Frequency (Hz)

Figure 79 De-emphasis Error (44.1kHz)

15000 20000

0.0

-2.0

-4.0

-6.0

-8.0

-10.0

0 5000 10000

Frequency (Hz)

15000 20000

Figure 80 De-emphasis Frequency Response (48kHz)

0.4

0.3

0.2

0.1

0.0

-0.1

-0.2

-0.3

-0.4

0 5000 10000

Frequency (Hz)

Figure 81 De-emphasis Error (48kHz)

15000 20000 w


61

WM8742

APPLICATIONS INFORMATION

Production Data

Figure 82 External Components

Figure 83 External Filter Components

w


62

Production Data

PACKAGE DIMENSIONS

DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) b e

28

15

E1 E

GAUGE

PLANE



1

D

14

A A2

A1

-C-

0.10 C

SEATING PLANE

Symbols

A

A

1

A

2 b c

D e

E

E

L

1

L



1

MIN

-----

0.05

1.65

0.22

0.09

9.90

7.40

5.00

0.55

0 o

Dimensions

(mm)

NOM

-----

-----

1.75

0.30

-----

10.20

0.65 BSC

7.80

5.30

0.75

1.25 REF

4 o

MAX

2.0

0.25

1.85

0.38

0.25

10.50

8.20

5.60

0.95

8 o

REF:

JEDEC.95, MO-150

NOTES:

A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.

B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.

D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

c

L

L

1

0.25

WM8742

DM007.E

w


63

WM8742

Production Data

IMPORTANT NOTICE

Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.

Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.

Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.

Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.

In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.

Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.

Any use of products by the customer for such purposes is at the customer’s own risk.

Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute

Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.

Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.

Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.

ADDRESS:

Wolfson Microelectronics plc

Westfield House

26 Westfield Road

Edinburgh

EH11 2QB

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Email :: [email protected]

w


64

Production Data

REVISION HISTORY

DATE REV DESCRIPTION OF CHANGES

14/02/13 4.3 Digital supply operation changed from 3.0V to 3.6V to 3.15 to 3.6V

14/02/13 4.3 Operating temp changed from -40 o

C to +85 o

C to 0 o

C to +70 o

C

WM8742

CHANGED BY

JMacD

JMacD w


65

WM8742 Product Datasheet

24-bit 192kHz DAC with Advanced Digital Filtering

MASTER CLOCK TIMING

PCM DIGITAL AUDIO INTERFACE TIMINGS

DSD AUDIO INTERFACE TIMINGS

CONTROL INTERFACE TIMING – 3-WIRE MODE

CONTROL INTERFACE TIMING – 2-WIRE MODE

INTERNAL POWER ON RESET CIRCUIT

INTRODUCTION

CLOCKING SCHEMES

CONTROL INTERFACE

SOFTWARE CONTROL INTERFACE

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

3-WIRE CONTROL INTERFACE DAISY CHAINING

2-WIRE SERIAL CONTROL MODE

DIGITAL AUDIO INTERFACE

PCM MODE

PCM DIGITAL AUDIO INTERFACE

LEFT JUSTIFIED MODE

RIGHT JUSTIFIED MODE

I

S MODE

DSP MODE A

DSP MODE B

PCM MODE SAMPLING RATES

8FS MODE

8FS MODE SAMPLING RATES

AUDIO INTERFACE DAISY CHAINING

DSD MODE

DSD DIRECT

DSD PLUS MODE

DSD DIGITAL AUDIO INTERFACE

SOFTWARE CONTROL MODE

DSD AND PCM MODE SWITCHING

PCM DIGITAL AUDIO INTERFACE CONTROL REGISTERS

LRCLK POLARITY

BCLK / DSDCLK64 POLARITY

OVERSAMPLING RATE CONTROL

MCLK/LRCLK RATIO CONTROL (NORMAL PCM MODE)

8FS MODE

MCLK/LRCLK RATIO CONTROL (8FS MODE)

ATTENUATION CONTROL

DAC OUTPUT ATTENUATION

ATTENUATION CONTROL MODE

VOLUME RAMP MODE

ANTI-CLIPPING DIGITAL ATTENUATION MODE

DSD PLUS GAIN CONTROL

MUTE MODES

ZERO FLAG OUTPUT

ZFLAG FORCE HIGH CONTROL

INFINITE ZERO DETECT

DE-EMPHASIS

OUTPUT PHASE REVERSAL

DIFFERENTIAL MONO MODE

DITHER

NORMAL PCM MODE DIGITAL FILTER SELECTION

8FS MODE DIGITAL FILTER

DSD PLUS FILTER SELECTION

DSD DIRECT DIGITAL FILTERS

DSD MUTE CONTROL

POWER SAVING STANDBY CONTROL

HARDWARE CONTROL MODE

DSD AND PCM MODE SWITCHING

AUDIO INPUT FORMAT

OVERSAMPLING RATE CONTROL

MUTE PIN

ZERO FLAG

DE-EMPHASIS CONTROL AND ANTI-CLIPPING MODE

DIGITAL FILTER SELECTION

DIFFERENTIAL MONO MODE

PCM MODE FILTER CHARACTERISTICS

8FS MODE FILTER CHARACTERISTICS

DSD PLUS MODE FILTER CHARACTERISTICS

PCM MODE FILTER RESPONSES

8FS MODE FILTER RESPONSES

DSD PLUS MODE FILTER RESPONSES

DSD DIRECT MODE FILTER RESPONSES

DEEMPHASIS FILTER RESPONSES

ADDRESS:

Related manuals