datasheet for AK4621 by Asahi Kasei Microdevices

[AK4621]

AK4621

24-Bit 192kHz Stereo Audio CODEC

GENERAL DESCRIPTION

The AK4621 is a high performance 24-bit CODEC that supports up to 192kHz recording and playback.

The on-board analog-to-digital converter has a high dynamic range due to AKM’s Enhanced Dual-Bit architecture. The DAC utilizes AKM’s Advanced Multi-Bit architecture that achieves low out-of-band noise and high jitter tolerance through the use of Switched Capacitor Filter (SCF) technology. The AK4621 is ideal for Pro Audio sound cards, Digital Audio Workstations, DVD-R, hard disk, CD-R recording/playback systems, and musical instrument recording.

FEATURES

24-bit 2-channel ADC

- Full Differential Inputs

- Selectable Digital Filter

1. ADC Sharp Roll Off Filter (GD=39/fs)

Passband: 0 ~ 21.8kHz (@fs=48kHz)

Stopband Attenuation: 100dB

2. ADC Short Delay Sharp Roll Off Filter (GD=14/fs)



- S/(N+D): 102dB

- S/N: 115dB

- Digital High-pass Filter for Offset Cancellation

- Overflow Flag

- Audio Interface Format: MSB justified or I

2

S

24-bit 2-channel DAC

- Selectable Digital Filter

1. DAC Sharp Roll Off Filter (GD=27/fs)



2. DAC Slow Roll Off Filter (GD=27/fs)



3. DAC Short Delay Sharp Roll Off Filter (GD=7/fs)



- Switched-cap Low Pass Filter

- Differential Outputs

- S/(N+D): 100dB

- S/N: 115dB

- De-emphasis for 32kHz, 44.1kHz, 48kHz Sampling

- Output Digital Attenuator: 0dB ~ – 72dB, Linear 256 + 16steps

- Zero Detection Function

- Audio Interface Format: MSB justified, LSB justified, I

2

S

High Jitter Tolerance

Sampling Rate: 32kHz ~ 216kHz

μP Interface: 3-wire Serial Interface

Master Clock: 128fs/192fs/256fs/384fs/512fs/768fs/1024fs

MS1258-E-01

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2011/01

Block Diagram

Power Supply

Analog: 4.75 ~ 5.25V (typ. 5.0V)

Digital: 3.0 ~ 3.6V (typ. 3.3V)

Digital I/O: DVDD ~ 5.25V (typ. 5.0V)

Package: 30pin VSOP

Ta: -10 ~ 70

°C

AINL+

AINL-

AINR+

AINR-

OVFL/DZFL

OVFR/DZFR

AOUTL+

AOUTL-

AVDD VSS1 VCOM VREF

ADC

HPF

OVF

DATT

SMUTE

DAC

AOUTR+

AOUTR-

DVDD TVDD VSS2

Audio

Interface

Control

Register I/F

PDN

LRCK

BICK

SDTO

SDTI

MCLK

DFS0

P/S

SDFIL DEM0

CSN/ CCLK/

DIF CKS1

CDTI/

CKS0

Figure 1. Block Diagram

[AK4621]

MS1258-E-01

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2011/01

Ordering Guide

AK4621EF 30pin

Pin Layout

VCOM

1

AINR+ 2

AINR- 3

4

AINL+

AINL-

VREF

5

6

VSS1 7

AVDD 8

P/S

MCLK

9

10

LRCK

11

BICK 12

13

SDTO

SDTI

14

OVFR/DZFR

15

Top View

20

19

18

17

16

24

23

22

21

27

26

25

30

29

28

AOUTR+

AOUTR-

AOUTL+

AOUTL-

VSS2

DVDD

TVDD

SDFIL

DEM0

PDN

DFS0

CSN/DIF

CCLK/CKS1

CDTI/CKS0

OVFL/DZFL

[AK4621]

MS1258-E-01

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[AK4621]

Compatibility with AK4620B

1. Function

Function AK4620B

Max fs

ADC Inputs

Input analog PGA

Input digital ATT

ADC S/(N+D)

ADC DR, S/N

ADC Digital Filter Type

ADC Digital Filter SA

ADC Digital Filter GD

DAC S/(N+D)

DAC DR, S/N

DAC Digital Filter Type

DAC Digital Filter SA

DAC Digital Filter GD

Output digital Attenuator

DAC DSD mode

DAC Zero-data detection

Parallel Mode

AK4621

216kHz

Single-ended

0 ~ +18dB

0.5dB/step

Mute,-63.5dB ~ 0dB

0.5dB/step

90dB

110dB

Differential Differential

- -

Mute,-63.5dB ~ 0dB

0.5dB/step

100dB

113dB

-

102dB

115dB

Sharp Roll-off

100dB

43.2/fs

Sharp Roll-off

100dB

39/fs

Short Delay

Sharp Roll-off

80dB

14/fs

97dB (0dBFS)

115dB

Sharp Roll-off

75dB

28/fs

Mute, -48dB ~ 0dB

Linear 256 steps

X

X

X

Slow Roll-off

72dB

28/fs

Mute, -48dB ~ 0dB

Linear 256 steps

100dB (-1dBFS)

Sharp Roll-off

70dB

27/fs

Slow Roll-off

73dB

27/fs

Mute, -72dB ~ 0dB

Linear 16 + 256 steps

-

Short Delay

Sharp Roll-off

70dB

7/fs

X: Available, -: Not Available

2. Register (difference from AK4620B)

Addr Register D7 D6 D5 D4 D3 D2 D1 D0

00H Power Down Control SLOW

D/P

DZFB

DCKS

ZOE

DCKB

ZOS

SDAD

02H Clock and Format Control DIF2 DIF1 DIF0 CMODE

03H Deem and Volume Control SMUTE HPRN HPLN ZCEI

04H Reserved

SDDA PWVR PWAD PWDA

AML

CKS1

ZTM1

AMR RSTAD

CKS0 DFS1

RSTDA

DFS0

ZTM0 DEM1 DEM0

IATTL7 IATTL6 IATTL5 IATTL4 IATTL3 IATTL2 IATTL1 IATTL0

05H Reserved

06H Lch DATT Control

07H Rch DATT Control

08H

Lch Extension DATT Control

IATTR7

DATTL7

DATTR7

IATTR6

DATTL6

DATTR6

IATTR5

DATTL5

DATTR5

IATTR4

DATTL4

DATTR4

IATTR3

DATTL3

DATTR3

EXTE 0

IATTR2

EATTL2

IATTR1

DATTL2 DATTL1

DATTR2 DATTR1

EATTL1

IATTR0

DATTL0

DATTR0

EATTL0

09H

Rch Extension DATT Control

0 0 0 0 EATTR2 EATTR1 EATTR0

These bits were added in the AK4621.

These bits were deleted in the AK4621.

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[AK4621]

PIN/FUNCTION

Function

1 VCOM O

Common Voltage Output Pin, (AVDD)/2

Bias voltage of ADC inputs and DAC outputs.

2 AINR+

3 AINR-

4 AINL+

I

I

I

Rch Positive Input Pin

Rch Negative Input Pin

Lch Positive Input Pin

5 AINL- I Lch Negative Input Pin

Voltage Reference Input Pin, AVDD

6 VREF I Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered

AVDD.

7 VSS1 - Analog Ground Pin

8 AVDD - Analog Power Supply Pin, 4.75

∼ 5.25V

9 P/S

10 MCLK

11 LRCK

12 BICK

13 SDTO

14 SDTI

15

OVFR

DZFR

I

Parallel/Serial Mode Select Pin

“L”: Serial Mode, “H”: Parallel Mode

Do not change this pin during PDN pin = “H”.

I

I

I

O

I

O

O

Master Clock Input Pin

Input/Output Channel Clock Pin

Audio Serial Data Clock Pin

Audio Serial Data Output Pin

Audio Serial Data Input Pin

Rch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)

Rch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)

16

17

OVFL

DZFL

CDTI

CKS0

O Lch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)

O Lch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)

I Control Data Input Pin (in Serial Mode)

I Master Clock Select Pin (in Parallel Mode)

CCLK I Control Data Clock Pin (in Serial Mode)

18

CKS1

CSN

I Master Clock Select Pin (in Parallel Mode)

I Chip Select Pin in Serial Mode (in Serial Mode)

19 Digital Audio Interface Select Pin (in Parallel Mode)

DIF I

“L”: 24bit MSB justified, “H”: I2S compatible

20 DFS0

21 PDN

I Double Speed Sampling Mode Pin

Power-Down Mode Pin

I

“L”: Power down reset and initialize the control register, “H”: Power up

22 DEM0 I De-emphasis Control Pin

Digital Filter Select Pin

23 SDFIL I

24 TVDD

“H”: Sharp Roll Off Filter (ADC), Sharp Roll Off Filter (DAC)

- Digital I/O Power Supply Pin, DVDD

25 DVDD - Digital Power Supply Pin, 3.0

∼ 3.6V

∼ 5.25V

26 VSS2 - Digital Ground Pin

27 AOUTL- O Lch Negative Analog Output Pin

28 AOUTL+ O Lch Positive Analog Output Pin

30 AOUTR+ O Rch Positive Analog Output Pin

Note 1. All digital input pins (P/S, MCLK, LRCK, BICK, SDTI, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN,

DEM0 and SDFIL) must not be left floating.

MS1258-E-01

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[AK4621]

Handling of Unused Pin

The unused I/O pin must be processed appropriately as below.

Setting

Analog Input

AINL+, AINL-

AINR+, AINR-

AINL+ pin is connected to AINL- pin.

AINR+ pin is connected to AINR- pin.

Analog Output AOUTL+, AOUTL-, AOUTR+, AOUTR- These pins must be open.

Digital Output OVFL/DZFL, OVFR/DZFR These pins must be open.

ABSOLUTE MAXIMUM RATINGS

(VSS1=VSS2=0V;

Note 2, Note 3

)

Power Supplies: Analog

Digital

Digital I/O

AVDD

DVDD

TVDD

Input Current, Any Pin Except Supplies IIN

Analog Input Voltage ( Note 4 ) VINA

Digital Input Voltage ( Note 5 )

-0.3

-0.3

-0.3

-

-0.3

6.0

6.0

6.0

±10

V

V

V mA

AVDD+0.3 V

Ambient Temperature (power applied)

Storage Temperature

Ta

Tstg

-10

-65

70

150

Note 2. All voltages with respect to ground.

Note 3. VSS1 and VSS2 must be connected to the same analog ground plane.

Note 4. AINL+, AINL-, AINR+ and AINR- pins

Note 5. P/S, MCLK, LRCK, BICK, SDTI, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN, DEM0 and SDFIL pins.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

°C

°C

(VSS1=VSS2=0V;

Note 2

)

Parameter

Power Supplies

(

Note 6

)

Voltage Reference

Analog

Digital

Digital I/O

Symbol min typ max Units

AVDD

DVDD

TVDD

VREF

4.75

3.0

DVDD

3.0

5.0

3.3

5.0

-

Note 2. All voltages with respect to ground.

Note 6: The power up sequence among AVDD, DVDD and TVDD is not critical.

WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

5.25

3.6

5.25

AVDD

V

V

V

V

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[AK4621]

ANALOG CHARACTERISTICS

(Ta=25

°C; AVDD=5V, DVDD=3.3V, TVDD=5V; VSS1=VSS2=0V; VREF=AVDD; fs=48kHz; Signal Frequency

=1kHz; 24bit Data; Measurement frequency=20Hz

∼ 20kHz; unless otherwise specified)

ADC Analog Input Characteristics:

Input Voltage (

Note 7

)

Input Resistance

S/(N+D) fs=48kHz

BW=20kHz fs=96kHz

BW=40kHz

±2.62 ±2.82 ±3.02

Vpp k

Ω fs=192kHz - 13 -

-1dBFS

-60dBFS

-1dBFS

-60dBFS

92

-

-

-

102

52

101

48

-

-

-

- dB dB dB dB fs=192kHz

BW=40kHz

-1dBFS

-60dBFS

Dynamic Range (-60dBFS with A-weighted)

S/N (A-weighted)

-

-

-

105

101

48

115

115

-

-

-

- dB dB dB dB

Interchannel Isolation 90 110 - dB

Interchannel Gain Mismatch - 0 0.3 dB

Gain Drift ( Note 12

) - 20 -

°C

Power Supply Rejection ( Note 8 ) - 50 - dB

DAC Analog Output Characteristics:

Dynamic Characteristics

S/(N+D) fs=48kHz

BW=20kHz fs=96kHz

−1dBFS

−60dBFS

−1dBFS

−60dBFS

BW=40kHz fs=192kHz

BW=40kHz

−1dBFS

−60dBFS

Dynamic Range (

−60dBFS with A-weighted) (

Note 9

,

Note 10 )

S/N (A-weighted) ( Note 10

,

Note 11 )

Interchannel Isolation (1kHz)

90

-

-

-

-

-

100

52

97

49

97

49

-

-

-

-

-

- dB dB dB dB dB dB

107 115 - dB

90 110 - dB

DC Accuracy

Interchannel Gain Mismatch - 0 0.3 dB

Gain Drift (

Note 12 ) -

20 - ppm/

°C

Output Voltage ( Note 13 )

±2.6 ±2.8 ±3.0

Vpp

Load Capacitance - - 25 pF

Load Resistance (

Note 14 ) 2

- - k

Ω

Note 7. Full scale (0dB) of the input voltage. Vin (typ) =

±2.82Vpp x VREF/5.

Note 8. PSR is applied to AVDD, DVDD, TVDD with 1kHz, 50mVpp. VREF pin is held a constant voltage.

Note 9. 100dB at 16bit data and 114dB at 20bit data.

Note 10. By

Figure 20

. External LPF Circuit Example 2.

Note 11. S/N does not depend on input bit length.

Note 12. The voltage on VREF is held +5V externally.

Note 13. Full scale voltage (0dB). Output voltage scales with the voltage of VREF.

AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 5.6Vpp x VREF/5.

Note 14. For AC-load.

MS1258-E-01

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[AK4621]

Power Supplies

Power Supply Current

Normal Operation (PDN pin = “H”)

DVDD+TVDD (fs=48kHz)

(fs=96kHz)

(fs=192kHz)

-

-

-

11

20

27

-

30

41 mA mA mA

Power-down mode (PDN pin = “L”) (

AVDD

Note 15

)

μA

DVDD+TVDD

-

-

10

10

100

100

μA

Note 15. All digital input pins are held TVDD or VSS2.

MS1258-E-01

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[AK4621]

ADC SHARP ROLL OFF FILTER CHARACTERISTICS (fs=48kHz)

(Ta=25

°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Normal Speed Mode; SDAD bit = “0”)

ADC Digital Filter (Decimation LPF):

Passband (

Note 16

)

−0.005dB

−0.02dB

−0.06dB

−6.0dB

PB 0

-

-

-

-

22.0

22.3

24.0

21.8

-

-

- kHz kHz kHz kHz

Stopband (

Passband Ripple

Stopband Attenuation

Group Delay (

Note 17 ) GD

Group Delay Distortion

Note 16 ) SB

PR

SA

ΔGD

26.5

-

-

-

-

±0.005 kHz dB

100 - - dB

- 39 - 1/fs

- 0 -

μs

ADC Digital Filter (HPF):

Frequency Response (

Note 16 )

−3dB

−0.1dB

FR -

-

1.0

6.5

-

-

Hz

Hz


(Ta=25

°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Double Speed Mode; SDAD bit = “0”)


Passband (

Note 16

)

−0.005dB

−0.02dB

−0.06dB

−6.0dB

PB 0

-

-

-

-

44.1

44.5

48.0

43.7

-

-

- kHz kHz kHz kHz

Stopband (

Passband Ripple


Group Delay (

Note 17 ) GD


Note 16 ) SB

PR

SA

ΔGD

53.0

-

-

-

-

±0.005 kHz dB

100 - - dB

- 39 - 1/fs

- 0 -

μs


Frequency Response ( Note 16

)

−3dB

−0.1dB

FR -

-

2.0

13.0

-

-

Hz

Hz

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[AK4621]


(Ta=25

°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Quad Speed Mode; SDAD bit = “0”)


Passband (

Note 16

)

−0.005dB

−0.02dB

−0.06dB

−6.0dB

PB 0

-

-

-

-

88.2

89.0

96.0

87.0

-

-

- kHz kHz kHz kHz

Stopband (

Passband Ripple


Group Delay (


Note 16

Note 17

) SB

PR

SA

) GD

ΔGD

106.0

-

-

-

-

±0.01

- kHz dB

100 - dB

- 36 - 1/fs

- 0 -

μs



Note 16 )

−3dB

−0.1dB

FR -

-

4.0

26.0

-

-

Hz

Hz

Note 16: The passband and stopband frequencies scale with fs. Each response refers to that of 1kHz

Note 17: The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 24bit data both channels to the ADC output register for ADC. If the signal is outputted to the SDTO pin, group delay is increased 0.5/fs from the above value.

MS1258-E-01

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[AK4621]

ADC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs=48kHz)

(Ta=25

°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Normal Speed Mode; SDAD bit = “1”)


Passband (

Note 16

)

−0.01dB

−0.1dB

−3.0dB

−6.0dB

PB 0

-

-

-

-

22.1

23.8

24.4

21.7

-

-

- kHz kHz kHz kHz

Stopband (

Passband Ripple


Group Delay (

Note 17 ) GD


Note 16 ) SB

PR

SA

ΔGD

28.2

-

-

-

-

±0.01 kHz dB

80 - - dB

- 14 - 1/fs

- ±0.01 -

μs



Note 16 )

−3dB

−0.1dB

FR -

-

1.0

6.5

-

-

Hz

Hz


(Ta=25

°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Double Speed Mode; SDAD bit = “1”)


Passband (

Note 16

)

−0.01dB

−0.1dB

−3.0dB

−6.0dB

PB 0

-

-

-

-

44.2

47.6

48.9

43.3

-

-

- kHz kHz kHz kHz

Stopband (

Passband Ripple


Group Delay (

Note 17 ) GD


Note 16 ) SB

PR

SA

ΔGD

55.9

-

-

-

-

±0.01 kHz dB

80 - - dB

- 14 - 1/fs

- ±0.013 -

μs


Frequency Response ( Note 16

)

−3dB

−0.1dB

FR -

-

2.0

13.0

-

-

Hz

Hz


(Ta=25

°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Quad Speed Mode; SDAD bit = “1”)


Passband (

Note 16

)

−0.01dB

−0.1dB

−3.0dB

−6.0dB

PB 0

-

-

-

-

81.1

99.9

106.7

76.1

-

-

- kHz kHz kHz kHz

Stopband (

Passband Ripple



Note 16 ) SB

PR

SA

Group Delay (

Note 17 ) GD

ΔGD

141.1

-

-

-

-

±0.01 kHz dB

79 - - dB

- 11 - 1/fs

- 0 -

μs



Note 16 )

−3dB

−0.1dB

FR -

-

4.0

26.0

-

-

Hz

Hz

MS1258-E-01

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[AK4621]

DAC SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 48kHz)

(Ta = 25

°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Normal Speed Mode; DEM = OFF;

SLOW bit = “0”, SDDA bit = “0”)

Digital Filter

Passband ( Note 18

) -0.04dB

-6.0dB

PB 0

-

-

24.0

Stopband ( Note 18

) SB 26.2 -

Passband Ripple PR - -

Stopband Attenuation SA

Group Delay (

Note 19 ) GD

70

-

-

27

21.8

- kHz kHz

- kHz

±0.06 dB

- dB

- 1/fs

Digital Filter + SCF

Frequency Response: 0

∼ 20.0kHz

- dB


(Ta = 25

°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Double Speed Mode; DEM = OFF;


Digital Filter

Passband ( Note 18

) -0.04dB

-6.0dB

PB 0

-

-

48.0

Stopband ( Note 18

) SB 52.4 -

Passband Ripple


PR

SA

-

70

Group Delay (

Note 19 ) GD

-

-

-

27



∼ 40.0kHz

43.5

- kHz kHz

- kHz

±0.06

- dB dB

- 1/fs

- dB


(Ta = 25

°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Quad Speed Mode; DEM = OFF;


Digital Filter

Passband ( Note 18

) -0.02B

-6.0dB

PB 0

-

-

95.9

Stopband ( Note 18

) SB 105 -


Stopband Attenuation SA 70

Group Delay (

Note 19 ) GD

-

-

27

87.0

- kHz kHz

- kHz

±0.06 dB

- dB

- 1/fs



∼ 80.0kHz

Note 18. The passband and stopband frequencies scale with fs. Each response refers to that of 1kHz.

Note 19. Delay time caused by digital filtering. This time is from setting the 16/20/24bit data of both channels to input register to the output of analog signal.

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[AK4621]

DAC SLOW ROLL OFF FILTER CHARACTERISTICS (fs = 48kHz)

(Ta = 25



Digital Filter

Passband ( Note 18

) -0.07dB

-3.0dB

PB 0

-

-

19.8

Stopband ( Note 18 ) SB

42.6 -


8.9

-

-

±0.07 kHz kHz kHz dB

Stopband Attenuation SA 73 - - dB

Group Delay (

Note 19 )

1/fs



∼ 20.0kHz

- +0/-5 - dB


(Ta = 25



Digital Filter

Passband ( Note 18

) -0.07dB

-3.0dB

PB 0

-

-

39.5

Stopband ( Note 18 ) SB

85.1 -



Group Delay (

Note 19 ) GD

-

-

27



∼ 40.0kHz

17.7

-

-

±0.07

-

- kHz kHz kHz dB dB

1/fs


(Ta = 25



Digital Filter

Passband ( Note 18

) -0.07dB

-3.0dB

PB 0

-

-

79.0

Stopband ( Note 18 ) SB 170.7

-

35.5

- kHz kHz

- kHz

Passband Ripple


PR

SA

-

73

-

-

±0.07

- dB dB

Group Delay (

Note 19

) GD - 27 - 1/fs



∼ 80.0kHz

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[AK4621]

DAC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 48kHz)

(Ta = 25



Digital Filter

Passband ( Note 18

) -0.04dB

-6.0dB

PB 0

-

-

24.0

Stopband ( Note 18

) SB 26.2 -


Stopband Attenuation SA

Group Delay (

Note 19 ) GD

70

-

-

7

21.8

- kHz kHz

- kHz

±0.06 dB

- dB

- 1/fs



∼ 20.0kHz

- dB


(Ta = 25



Digital Filter

Passband ( Note 18

) -0.03dB

-6.0dB

PB 0

-

-

48.0

Stopband ( Note 18

) SB 52.4 -

Passband Ripple


PR

SA

-

70

Group Delay (

Note 19 ) GD

-

-

-

7

43.5

- kHz kHz

- kHz

±0.06

- dB dB

- 1/fs



∼ 40.0kHz

- dB


(Ta = 25



Digital Filter

Passband ( Note 18

) -0.02dB

-6.0dB

PB 0

-

-

96.2

Stopband ( Note 18

) SB 104.9 -



Group Delay (

Note 19 ) GD

-

-

7



∼ 80.0kHz

87.0

- kHz kHz

- kHz

±0.06 dB

- dB

- 1/fs

MS1258-E-01

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2011/01

[AK4621]

DC CHARACTERISTICS

(Ta=25

°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V)

Parameter Symbol

High-Level Input Voltage

Low-Level Input Voltage

High-Level Output Voltage (Iout=-100

μA)

Low-Level Output Voltage (Iout=100

μA)

VIH

VIL

VOH

VOL

Input Leakage Current Iin

70%DVDD

-

DVDD-0.5

-

-

SWITCHING CHARACTERISTICS

(Ta=25

°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; C

L

=20pF)


-

-

-

-

-

TVDD

30%DVDD

-

0.5

±10

V

V

V

V

μA

Master Clock Timing

Frequency

Pulse Width Low

Pulse Width High fCLK tCLKL tCLKH

8.192

0.4/fCLK

0.4/fCLK

-

-

-

55.296

-

-

MHz ns ns

LRCK Frequency (

Note 20 )

Normal Speed Mode (DFS0=“0”, DFS1=“0”)

Double Speed Mode (DFS0=“1”, DFS1=“0”)

Quad Speed Mode (DFS0=“0”, DFS1=“1”)

Duty Cycle

PCM Audio Interface Timing

BICK Period

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

BICK Pulse Width Low

Pulse Width High

LRCK Edge to BICK “

↑” (

Note 21 )

BICK “

↑” to LRCK Edge (

Note 21 )

LRCK to SDTO (MSB) (Except I

BICK “

↓” to SDTO

2

S mode)

SDTI Hold Time

SDTI Setup Time fsn fsd fsq tBCK tBCK tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS

32

54

108

45

1/128fsn

1/64fsd

1/64fsq

33

33

20

20

-

-

20

20

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

54

108

216

55

-

-

-

-

-

-

-

20

20

-

- kHz kHz kHz

%

Note 20. When the normal/double/quad speed modes are switched, the AK4621 must be reset by the PDN pin or RSTN bit.

Note 21. BICK rising edge must not occur at the same time as LRCK edge. ns ns ns ns ns ns ns ns ns ns ns

MS1258-E-01

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2011/01


Control Interface Timing

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN “H” Time

CSN “

↓” to CCLK “↑”

CCLK “

↑” to CSN “↑” tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH

Reset Timing

PDN Pulse Width ( Note 22

)

RSTAD “

↑” to SDTO Valid (

Note 23

) tPD tPDV

Note 22. The AK4621 can be reset by bringing the PDN pin “L”.

Note 23. These cycles are the number of LRCK rising from RSTAD bit.

150

-

200

80

80

50

50

150

50

50

-

-

-

-

-

-

-

-

-

516

-

-

-

-

-

-

-

-

-

-

[AK4621] ns ns ns ns ns ns ns ns ns

1/fs

MS1258-E-01

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2011/01

Timing Diagram

MCLK

LRCK

BICK

LRCK

BICK

SDTO

SDTI

1/fCLK tCLKH

1/fs tCLKL

VIH

VIL

VIH

VIL tBCK

VIH

VIL tBCKH tBCKL

Figure 2. Clock Timing tBLR tLRB tLRS tBSD

VIH

VIL

VIH

VIL

50%TVDD tSD S tSDH

VIH

VIL

Figure 3. Audio Interface Timing

[AK4621]

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2011/01

CSN

CCLK

CDTI

CSN

CCLK

VIH

VIL tCSH tCSS tCCKL tCCKH

VIH

VIL tCDS tCDH

C1 C0 R/W A4

VIH

VIL

Figure 4. WRITE Command Input Timing tCSW

VIH

VIL tCSH tCSS

VIH

VIL

[AK4621]

VIH

VIL

CDTI D3 D2 D1 D0

Figure 5. WRITE Data Input Timing tPD

PDN

Figure 6. Power Down & Reset Timing

VIL

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[AK4621]

OPERATION OVERVIEW

System Clock Input

The AK4621 requires MCLK, BICK and LRCK external clocks. MCLK must be synchronized with LRCK but the phase is not critical. The AK4621 is automatically placed in power-down state when MCLK is stopped more than 9.38µs during a normal operation (PDN pin =“H”), then the digital output becomes “0” data and the analog output becomes Hi-Z. When

MCLK and LRCK are input again, the AK4621 exit power-down state and starts the operation.

After exiting system reset

(PDN pin =“L” “H”) at power-up and other situations, the AK4621 is in power-down mode until MCLK is supplied.

As the AK4621 includes the phase detect circuit for LRCK, the AK4621 is reset automatically when the synchronization is out of phase by changing the clock frequencies.

1. Serial mode (P/S pin= “L”)

As shown in Table 1 , Table 2 and Table 3 , select the MCLK frequency by setting CMODE, CKS1-0 and DFS1-0 bits.

These registers are changed when RSTAD bit = RSTDA bit = “0”.

DFS1 bit DFS0 bit Mode Sampling Rate

1 1 N/A -

Table 1. Sampling Speed in Serial Mode (N/A: Not Available)

CMODE bit CKS1 bit CKS0 bit

MCLK

Normal Speed

(DFS1-0 = “00”)

MCLK

Double Speed

(DFS1-0 = “01”)

0 0 0 256fs N/A

MCLK

Quad Speed

(DFS1-0 = “10”)

0 0 1 512fs 256fs 128fs

0 1 0 1024fs 512fs 256fs

0 1 1 N/A Auto Setting Mode (*)

1 0 0 384fs N/A

N/A

N/A

1 0 1 768fs 384fs 192fs

Table 2. Master Clock frequency in Serial Mode (“*”; refer to

Table 3

.) (N/A: Not Available)

The Auto Setting Mode detects MCLK/LRCK ratio and selects Normal/Double/Quad speed mode automatically ( Table

3 ).

MCLK/LRCK ratio

512 or 768

256 or 384

128 or 192

Mode

Normal speed

Double speed

Quad speed

Sampling Rate

32kHz-54kHz

54kHz-108kHz

108kHz-216kHz

Table 3. Auto Setting Mode in Serial Mode (DFS1-0 bits = “01”, CMODE bit = “0”, CKS1-0 bits = “11”)

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2011/01

[AK4621]

2. Parallel mode (P/S pin= “H”)

As shown in

Table 4 , Table 5

and

Table 6 , select the MCLK frequency with the CKS0-1 and DFS0 pins. These pins must

be changed when the PDN pin = “L”.

DFS0 pin Mode Sampling Rate

Table 4. Sampling Speed in Parallel Mode

CKS1 pin CKS0 pin

MCLK

Normal Speed

(DFS0 pin = “L”)

MCLK

Double Speed

(DFS0 pin = “H”)

L L 256fs N/A

L H 512fs 256fs

H L 384fs Auto Setting Mode (*)

H H 1024fs 512fs

Table 5. Master Clock Frequency in Parallel Mode (“*”; refer to

Table 6

.) (N/A: Not Available)

The Auto Setting Mode detects MCLK/LRCK ratio and selects Normal/Double/Quad speed mode automatically.

( Table 6 ).

MCLK/LRCK ratio

512 or 768

256 or 384

128 or 192

Mode

Normal speed

Double speed

Quad speed

Sampling Rate

32kHz-54kHz

54kHz-108kHz

108kHz-216kHz

Table 6. Auto Setting Mode in Parallel Mode (DFS0 pin = “H”, CKS1 pin = “H”, CKS0 pin = “L”)

MCLK (Normal speed) fs=44.1kHz fs=48kHz MCLK (Double speed) fs=88.2kHz fs=96kHz

N/A N/A N/A

N/A N/A N/A

MCLK (Quad speed) fs=176.4kHz fs=192kHz

Table 7. Master Clock Frequency Example (N/A: Not Available)

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2011/01

[AK4621]

Audio Serial Interface Format

Five serial modes are supported and selected by the DIF2-0 bits in Serial Mode (two modes by DIF pin in Parallel Mode) as shown in

Table 8 and Table 9 . In all modes the serial data has MSB first, 2’s complement format. The SDTO is clocked

out on the falling edge of BICK and the SDTI is latched on the rising edge. Mode2 can be used for 20 and 16 MSB justified formats by zeroing the unused LSBs.

Mode DIF2 DIF1 DIF0

0

1

2

4

0

0

0

0

0

0

1

24bit, MSB justified


3 0 1 1

1

1

0

0

0

SDTO


24bit,


SDTI

16bit, LSB justified



I

2


LRCK BICK

H/L

H/L

H/L

≥ 48fs

≥ 48fs

≥ 48fs

(default)

H/L

≥ 48fs

Table 8. Audio Data Format (Serial Mode)

SDTO SDTI

2 L 24bit, MSB justified 24bit, MSB justified

3 H 24bit, I

2

Table 9. Audio Data Format (Parallel Mode)

LRCK BICK

H/L

≥ 48fs

LRCK

0 1 2 3 17 18 20 30 31 0 1 2 3 17 18 19 20 31 0 1

BICK(64fs)

SDTO(o) 23 22 7 6 23 22 21 7 6 5 4 3 23

SDTI(i)

Don’t Care 15

SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB

Lch Data

Don’t Care

Figure 7. Mode 0 Timing

LRCK

BICK(64fs)

0 1 2 12 13 14 24 25 31 0 1 2

15 14 13 12 11 2 1 0

Rch Data

12 13 14 24 25 31 0 1

SDTO(o) 23 22 12 11 10 0 23 22 12 11 10 0 23

SDTI(i)

Don’t Care

SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB

Lch Data

Don’t Care


19 18

Rch Data

8 7 1 0

MS1258-E-01

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2011/01

[AK4621]

LRCK

BICK(64fs)

0 1 2 18 19 20 21 22 23 24 25

SDTO(o)

23 22 5 4 3 2 1 0

0 1 2 18 19 20 21 22 23 24 25 0 1

23 22 5 4 3 2 1 0 23

SDTI(i) Don’t Care

23 22

23:MSB, 0:LSB

Lch Data


LRCK

BICK(64fs)

0 1 2 3 19 20 21 22 23 24 25 0 1 2

5 4 3 2 1 0

Don’t Care

Rch Data

3 19 20 21 22 23 24 25 0 1

SDTO(o)

23 22 5 4 3 2 1 0 23 22 5 4 3 2 1 0

SDTI(i)

5 4

23:MSB, 0:LSB

Don’t Care

23 22

Lch Data


LRCK

BICK(64fs)

0 1 2 8 9 10 20 21 31 0 1 2

5 4 3 2 1 0

Don’t Care

Rch Data

8 9 10 31 0 1

SDTO(o) 23 22 16 15 14 0 23 22 16 15 14 0 23

SDTI(i)

Don’t Care

23:MSB, 0:LSB

Lch Data

Don’t Care


23 22

Rch Data

12 11 1 0

MS1258-E-01

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2011/01

[AK4621]

Output Volume

The AK4621 includes channel independent digital output volumes (DATT) with 256 levels and extension digital output volumes (EATT) with 16 levels at linear steps including MUTE. When EXTE bit = “1”, the extension digital output volumes are enabled.

These volumes are in front of the DAC. If the extension digital output volumes are disabled, the volumes can attenuate the input data from 0dB to

−48dB and mute. If the extension digital output volumes are enabled, the volumes can attenuate the input data from 0dB to

−72dB and mute. When changing levels, transitions are executed via soft changes, eliminating any switching noises. The transition time of 1 level, all 256 levels and all 256+16 is shown in

Table 10

. Volume calculating formula is shown in Table 13

.

Transition Time

Sampling Speed

1 Level

255 to 0

(EXTE bit = “0”)

255+15 to 0

(EXTE bit = “1”)

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

4LRCK

8LRCK

16LRCK

1020LRCK

2040LRCK

4080LRCK

Table 10. Output Digital Volume Transition Time

1080LRCK

2160LRCK

4320LRCK

DATTL7-0 bits

DATTR7-0 bits

DATT_DATA

EATTL3-0 bits

EATTR3-0 bits

GAIN(0dB)

FFH 255

FEH 254

FDH 253

: :

FH

02H 2

01H 1

00H -

-0.034

-0.068

:

-42.11

-48.13

Mute

Table 11. Output Digital Volume Setting (EXTE bit = “0”)

DATTL7-0 bits

DATTR7-0 bits

DATT_DATA

EATTL3-0 bits

EATTR3-0 bits

EATT_DATA GAIN(0dB)

FFH 255

FEH 254

+0

-0.034

FDH 253

FH -

: :

-0.068

:

02H 2

01H 1

-42.11

-48.13

FH 15 -48.72

EH 14 -49.32

: : :

00H -

2H 2 -66.22

1H 1 -72.25

0H - Mute

Note 24. If the volume is set from DATT gain to EATT gain or from EATT gain to DATT gain, these register must be wrote continuously within 4LRCK cycles in Normal Speed Mode. When the volume setting is not complete within 4LRCK cycles, the volume transition may stop.

Table 12. Output Digital Volume Setting (EXTE bit = “1”)

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2011/01

[AK4621]

DATTL7-0 bits

DATTR7-0 bits

EATTL3-0 bits

EATTR3-0 bits

GAIN(dB)

FFH

:

FH

20 log10 (DATT_DATA / 255)

01H

00H

FH

:

20 log10 (EATT_DATA / 4095)

1H

Table 13. Output Digital Volume Formula

Overflow Detection

The ADC has a channel independent overflow detection function. This function is enabled in parallel control mode, or when the ZOS bit = ZOE bit = “0” in serial control mode. OVFL/R pins go to “H” if each Lch/Rch analog input overflows

(exceeds -0.3dBFS). The output of each OVFL/R pin has same group delay as ADC against analog inputs. OVFL/R pin is

“L” for 516/fs (=10.8ms @fs=48kHz) after the PDN pin = “

↑”, and then overflow detection is enabled.

Zero Detection

The DAC has a channel-independent zero detect function. The zero detect function is enabled when the ZOS bit = “1” and the ZOE bit = “0” in serial control mode. When the input data at both channels is continuously zero for 8192 LRCK cycles, the DZF pin of each channel goes to “H”. The DZF pin of each channel immediately returns to “L” if the input data of each channel is not zero after DZF “H”. If the RSTDA bit is “0”, the DZF pins of both channels go to “H”. The DZF pins of both channels return to “L” in 2~3fs if the input data of each channel is not zero. Zero detect function can be disabled by the ZOE bit. In this case, the DZF pins of both channels are always “L”. The DZFB bit can invert the polarity of the DZF pin.

Digital High Pass Filter

The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz.

The digital high pass filter cut-off frequency scales with the sampling rate (fs). In parallel mode, the HPF is always enabled. In serial mode, the HPF can control each channel by HPLN/HPRN bits.

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[AK4621]

Digital Filter

The AK4621 has two kinds of Digital Filter for ADC and three kinds of Digital Filter for DAC. The outputs of ADC and

DAC can be controlled by using the SDFIL pin or SDAD/SDDA/SLOW bits.

SDFIL pin ADC DAC

L

H

Short Delay Sharp Roll Off Filter Short Delay Sharp Roll Off Filter

Sharp Roll Off Filter Sharp Roll Off Filter

Table 14. Digital Filter Selection in Parallel Mode

SDAD bit ADC

0

1

Sharp Roll Off Filter

Short Delay Sharp Roll Off Filter

Table 15. ADC Digital Filter Selection in Serial Mode

SDDA bit SLOW bit DAC

(default)

0

0

1

0

1

0

Sharp Roll Off Filter

Slow Roll Off Filter

Short Delay Sharp Roll Off Filter

(default)

1 1 N/A

Table 16. DAC Digital Filter Selection in Serial Mode (N/A: Not Available)

De-emphasis Filter

The DAC includes a digital de-emphasis filter (tc=50/15

μs for 32kHz, 44.1kHz or 48kHz sampling rates) by an integrated

IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter. This filter is always OFF in double and quad speed modes. The DEM0 pin and DEM0 bit are OR’d in serial control mode. In parallel control mode, the DEM1 bit is fixed to

“0” and only the DEM0 pin can be controlled (44.1kHz or OFF).

No DEM1 DEM0 Mode

0 0 0 44.1kHz

1 0 1 OFF

2 1 0 48kHz

3 1 1 32kHz

Table 17. De-emphasis control (Normal Speed Mode)

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[AK4621]

Soft Mute Operation

Soft mute operation is performed in the digital domain of the DAC input. When the SMUTE bit goes to “1”, the output signal is attenuated by

−∞ during ATT_DATA × ATT transition time (

Table 10

) from the current ATT level. When

SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during

ATT_DATA

× ATT transition time. If soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued and returns to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.

S M U T E bit

(1) (1)

A T T _Level

A ttenuation

-

∞

(3)

G D

(2)

G D

(2)

A O U T

(4)

8192/fs

D Z F pin

Notes:

(1) ATT_DATA

× ATT transition time (

Table 10

). For example, in Normal Speed Mode, if the EATT is disabled, this time is 1020LRCK cycles (1020/fs). If the EATT is enabled, this time is 1080LRCK cycles (1080/fs).

(2) Analog output corresponding to digital input has group delay (GD).

(3) If the soft mute is cancelled before attenuating

−∞, the attenuation is discontinued and returned to ATT level by the same cycle.

(4) When the input data at each channel is continuously zero for 8192 LRCK cycles, the DZF pin of each channel goes to “H”. The DZF pin immediately returns to “L” if input data are not zero after going to “H”.

Figure 12. Soft Mute and Zero Detection

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[AK4621]

Power Down & Reset

The ADC and DAC of AK4621 are placed in power-down mode by bringing the PDN pin = “L”. Each digital filter is also reset at the same time. The internal register values are initialized by bringing the PDN pin to “L”. This reset must always be done after power-up. As both control registers of the ADC and the DAC go to the reset state (RSTAD bit = RSTDA bit

= “0”), each register must be cleared after executing the reset. In the case of the ADC, an analog initialization cycle starts after exiting the power-down or reset state. The output data (SDTO) is available after 516 cycles of LRCK clock. This initialization cycle does not affect the DAC operation. Power down mode can be also controlled by the registers (PWAD bit, PWDA bit).

Power Supply

PD N pin

RSTAD/RSTDA bit

PWAD/PWDA bit

PWVR bit

(1) (1) (1)

AD C Internal State

ADC In (Analog)

PD Reset Normal

GD (2)

PD Normal

GD (2)

PD INITA Normal

GD (2)

AD C Out (Digital)

“0” data (3) “0” data (3) “0” data (3)

DAC Internal State

PD Reset

(4) (4) (4)

DATT

FFH XXH=>YYH YYH ZZH

DAC In (Digital)

“0”data

DAC Out (Analog)

Hi-Z

VCOM

GD (2)

Hi-Z

GD (2)

Hi-Z

Mute On (7)

FADE

External Mute

Example

Mute On (7)

Mute On (7)

Clock In

MCLK, LRCK, BICK

Don’t care

(8)

Stop

Notes:

(1) After exiting power down and reset state, the analog part of ADC is initialized (516/fs).

(2) Digital output corresponding to analog input and analog input corresponding to digital input have group delay

(GD).

(3) ADC output is “0” data in power-down state.

(4) After exiting power down and reset state, ATT value fades in/out.

*1 When RSTDA is “L” and DATT value is written to “XXH”, DATT value changes from FFH to XXH according to fade operation.

*2 When PWDA is “L” and DATT value is written to “YYH”, DATT value changes from XXH to YYH according to fade operation.

*3 When the external clocks (MCLK, SCLK, LRCK) are stopped and DATT value is written to “ZZH”, DATT value changes from YYH to ZZH according to fade operation.

(5) In the power-down mode, the DAC output is VCOM level. In the reset state, the DAC output is floating (Hi-z).

(6) Click noise occurs after RSTDA bit or PWDA bit is changed.

(7) Mute the analog output externally if the click noise (6) influences system application.

(8) When MCLK is stopped more than 9.38µs, the AK4621 becomes power down mode. Then ADC output is “0” data and DAC output is floating (Hi-Z).

Figure 13. Reset & Power down sequence in serial mode

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[AK4621]

In parallel mode, both ADC and DAC are powered up when releasing internal reset state by the PDN pin = “H”. When the

PDN pin is “L”, after exiting power down mode ADC s output “0” during first 516/fs cycles. DAC does not have the initialization cycle and the operation of fade-in.

Power Supply

PD N pin

(1) (1) (1)

AD C Internal State

PD INITA Normal PD Normal

GD (2) GD (2)

PD INITA Normal

GD (2)

ADC In (Analog)

AD C Out (Digital)

“0” data (3)

“0” data (3)

“0” data (3)

DAC Internal State

Normal

DAC In (Digital)

“0”data

GD (2) GD (2)

DAC Out (Analog)

Hi-Z Hi-Z Hi-Z

(5)

(5) (5)

(5) (5)

External Mute

Example

Mute On (6) Mute On (6)

Mute On (6)

(7)

Clock In

MCLK, LRCK, BICK

Don’t care Stop

Notes:

(1) After exiting power down and reset state, the analog part of ADC is initialized (516/fs).

(2) Digital output corresponding to analog input and analog input corresponding to digital input have group delay

(GD).

(3) ADC output is “0” data in power-down state.

(4) DAC output is floating (Hi-z) in power-down state.

(5) Click noise occurs at the rising/falling edge of PDN.

(6) Mute the analog output externally if the click noise (5) influences system application.

(7) When MCLK is stopped more than 9.38µs, the AK4621 becomes power down mode. Then ADC output is “0” data and DAC output is floating (Hi-Z).

Figure 14. Reset & Power Down Sequence in parallel mode

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2011/01

[AK4621]

Serial Control Interface

The internal registers may be written by the 3-wire

μP interface pins: CSN, CCLK, CDTI. The data on this interface consists of Chip address (2bits, C0/1) Read/Write (1 bit), Register address (MSB first, 5 bits) and Control data (MSB first,

8 bits). Address and data are clocked in on the rising edge of CCLK and data is latched after the 16th rising edge of

CCLK, following a high-to-low transition of CSN. Operation of the control serial port may be completely asynchronous with the audio sample rate. The maximum clock speed of the CCLK is 5MHz. The chip address is fixed to “10”. The access to the chip address except for “10” is invalid. PDN pin = “L” resets the registers to their default values.

Function

Overflow detection

DAC Slow Roll Off Filter

Zero detection

Soft Mute

Parallel mode

X

-

-

-

Serial mode

X

X

X

X

HPF OFF

16/20/24 bit LSB justified format of DAC

MCLK = 256fs @ Quad Speed

-

-

-

De-emphasis: 32kHz, 48kHz -

Table 18. Function List (X: available, -: not available)

X

X

X

X

CSN

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

CCLK

CDTI

A4 A3 A1 D7 D6 D5 D4 D3 D2 D1 D0

C1-C0: Chip Address (Fixed to “10”)

R/W: READ/WRITE (Fixed to “1”:WRITE)

Figure 15. Control I/F Timing

* READ command is not supported.

* The control data can not be written when the CCLK rising edge is 15times or less or 17times or more during CSN is “L”.

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[AK4621]

Register Map

Addr Register D7 D6 D5 D4 D3 D2 D1 D0

00H Power Down Control SLOW

02H Clock and Format Control DIF2 DIF1 DIF0

03H Deem and Volume Control SMUTE

06H

07H

Lch DATT Control

Rch DATT Control

CMODE

0 0 RSTDA

CKS1 CKS0 DFS1 DFS0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

DATTL7 DATTL6 DATTL5 DATTL4 DATTL3 DATTL2 DATTL1 DATTL0

DATTR7 DATTR6 DATTR5 DATTR4 DATTR3 DATTR2 DATTR1 DATTR0

08H

Lch Extension DATT Control

09H Rch Extension DATT Control

0 EATTL1 EATTL0

0 0 0 0 EATTR1 EATTR0

Note 25: Data must not be written to addresses 0AH through 1FH.

PDN pin = “L” resets the registers to their default values.

Control Register Setup Sequence

When the PDN pin goes “L” to “H” upon power-up etc., the AK4621 will be ready for normal operation by the sequence below. In this case, all control registers are set to default values and the AK4621 is in the reset state.

(1) Set the clock mode and the audio data interface mode.

(2) Cancel the reset state by setting RSTAD bit or RSTDA bit to “1”. Refer to Reset Contorl Register (01H).

(3) ADC output and DAC output must be muted externally until canceling each reset state.

The clock mode must be changed after setting RSTAD bit and RSTDA bit to “0”. At that time, ADC outputs and DAC outputs must be muted externally.

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Register Definitions

00H Power Down Control

Default

PWDA: DAC power down

D7 D6 D5 D4 D3 D2 D1 D0

SLOW DZFB ZOE ZOS SDDA PWVR PWAD PWDA

0 0 0 0 0 1 1 1

When PWDA bit = “0”, only the DAC block is powered down and the AOUT becomes Hi-z immediately.

In this time, all registers are not initialized, and register writings are valid. After exiting power down mode, the OATT fades in/out the setting value of the control register (06H, 07H, 08H, 09H). The analog output must be muted externally as a pop noise may occur when entering and exiting this mode.

PWAD: ADC power down

When PWAD bit = “0”, only the ADC block is powered-down and the SDTO pin becomes “L” immediately. After exiting power down mode, the ADC outputs “0” during first 516 LRCK cycles.

PWVR: Vref power down

When PWVR bit = “0”, all blocks are powered down. Both ADC and DAC cannot operate. In this time, all registers are not initialized, and register writings are valid. Only the VRFE block can be powered up by setting PWAD = PWDA bit = “0” and PWVR bit = “1”.

SDDA: DAC Short Delay Sharp Roll Off Filter Enable ( Table 16

)

0: Overflow detection for ADC input (default)

1: Zero detection for DAC input.

Zero-detection Overflow-detection Disable

DZFB: Inverting Enable of DZF

0: DZF goes “H” at Zero Detection (default)

1: DZF goes “L” at Zero Detection

SLOW: DAC Slow Roll Off Filter Enable (

Table 16 )

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Default

D7 D6 D5 D4 D3 D2 D1 D0

0 0

RSTDA

0 0 0 0 0 0 0 0

When RSTDA bit =“0”, the internal timing of DAC is reset and the AOUT becomes VCOM voltage immediately. In this time, all registers are not initialized, and register writings are valid. After exiting the power down mode, the OATT fades in the setting values of the control register (06H, 07H, 08H, 09H). The analog outputs must be muted externally since a pop noise may occur when entering to and exiting from this mode.

When RSTAD bit =“0”, the internal timing of ADC is reset and the SDTO pin becomes “L” immediately.

In this time, all registers are not initialized, and register writings are valid. After exiting the power down mode, the ADCs output “0” during first 516 LRCK cycles.

SDAD: ADC Short Delay Sharp Roll Off Filter Enable ( Table 15

)

D7 D6 D5 D4 D3 D2 D1 D0

02H Clock and Format Control DIF2 DIF1 DIF0

CMODE

CKS1 CKS0 DFS1 DFS0

Default 0 1 0 0 0 0 0 0

DFS1-0: Sampling Speed Control (

Table 1

)

CMODE, CKS1-0: Master Clock Frequency Select (

Table 2

)

DIF2-0: Audio data interface modes ( Table 8 )

Mode (default)

Default: 24bit MSB justified for both ADC and DAC

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D7 D6 D5 D4 D3 D2 D1 D0

03H

Deem and Volume Control SMUTE

HPRN HPLN

Default 0 0 0 0 0 0 0 1

DEM1-0: De-emphasis response ( Table 17 )

HPLN/RN: Left/Right channel Digital High Pass Filter Disable

SMUTE: DAC Input Soft Mute control

The soft mute is independent of the output ATT and performed digitally.

Register D7 D6 D5 D4 D3 D2 D1 D0

06H Lch DATT Control

DATTL7 DATTL6 DATTL5 DATTL4 DATTL3 DATTL2 DATTL1 DATTL0

07H Rch DATT Control DATTR7 DATTR6 DATTR5 DATTR4 DATTR3 DATTR2 DATTR1 DATTR0

Default 1 1 1 1 1 1 1 1

DATT7-0: DAC Output Attenuation Level, Linear step. ( Table 12

,

Table 13 )

08H Lch Extension DATT Control

09H

Rch Extension DATT Control

D7 D6 D5 D4 D3 D2 D1 D0

0 EATTL2 EATTL1 EATTL0

0 0 0 0 EATTR1

Default 0 0 0 0 1 1 1 1

EATT3-0: DAC Output Extension Attenuation Level; Linear step. (

Table 12 ,

Table 13

)

EXTE: Extension DATT Enable

1: Enable

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SYSTEM DESIGN

Figure 16 shows the system connection diagram. An evaluation board (AKD4621) is available for fast evaluation as well

as suggestions for peripheral circuitry.

0.1u

+

10u

1 VCOM AOUTR+ 30

Rch

LPF

Rch Out

Rch

Input

Buffer

2

3

AINR +

AINR -

AOUTR-

AOUTL+

29

28

Lch

LPF

Lch Out

Lch

Input

Buffer

4

5

AINL+

AINL-

AOUTL-

VSS2

27

26

4.75

∼ 5.25V

Analog Supply

+

10u

6

7

VREF

VSS1

DVDD

TVDD

25

24

0.1u

0.1u

3.0

∼ 3.6V

Digital Supply

DVD D

∼ 5.25V

Digital Supply

0.1u

8 AVDD

AK4621

SDFIL 23

9

P/S

DEM0 22

Audio

DSP

10 MCLK

11 LRCK

12 BICK

13 SDTO

PDN

DFS0

C SN/DIF

CCLK/CKS1

CDTI/CKS0

OVFL/DZFL

21

20

19

18

Mode

Setting/ uP

Notes:

- VSS1 and VSS2 must be connected to the same analog ground plane.

- When AOUT+/- drives some capacitive load, some resistance must be added in series between AOUT+/- and capacitive load.

- All digital input pins must not be left floating.

Figure 16. Typical Connection Diagram

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Digital Ground Analog Ground

System

Controller

5

6

3

4

1

2

VCOM

AINR+

AINR-

AINL+

9

10

7

8

AINL-

VREF

VSS1

AVDD

P/S

MCLK

AK4621

AOUTR+

AOUTR-

30

29

AOUTL+

AOUTL-

28

27

VSS2

DVDD

26

25

TVDD

NC

24

23

22 DEM0

PDN 21

11

12

13

LRCK

BICK

DFS0

CSN/DIF

20

CCLK/CKS1

19

18

SDTO

SDTI

14 CDTI/CKS0 17

15

OVFR/DZFR

OVFL/DZFL 16

Figure 17. Ground Layout

1. Ground and Power Supply Decoupling

The AK4621 requires careful attention to power supply and grounding layout. To minimize coupling from digital noise, decoupling capacitors must be connected to AVDD, DVDD and TVDD respectively. AVDD is supplied from the analog supply in the system, and DVDD and TVDD are supplied from the digital supply in the system. Power lines of AVDD,

DVDD and TVDD must be distributed separately from the point with low impedance of regulator etc. The power up sequence is not critical among AVDD, DVDD and TVDD. VSS1 and VSS2 must be connected to one analog

ground plane. Decoupling capacitors must be as near to the AK4621 as possible, with the small value ceramic capacitor being the nearest.

2. Voltage Reference

The differential voltage between VREF and VSS1 sets the analog input/output range. The VREF pin is normally connected to AVDD with a 0.1

μF ceramic capacitor. VCOM is the signal ground of this chip. A 10μF electrolytic capacitor in parallel with a 0.1

μF ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, must be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into the AK4621.

3. ADC Output

The ADC output data format is 2’s complement. The DC offset, including the ADC’s own DC offset, is removed by the internal HPF (fc=1.0Hz@fs=48kHz). The AK4621 samples the analog inputs at 128fs (@Normal Speed Mode), 64fs

(@Double Speed Mode) or 32fs (@Quad Speed Mode). The digital filter rejects noise above the stopband except for multiples of 128fs (@Normal Speed Mode), 64fs (@Double Speed Mode) or 32fs (@Quad Speed Mode).

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4. Analog Inputs

The AK4621 can accept input voltages from VSS1 to AVDD. The input signal range scales with the VREF voltage and is

nominally 2.82Vpp (VREF = 5V), centered around the internal common voltage (about VA/2). Figure 18

shows an input buffer circuit example. This is a fully differential input buffer circuit with an inverted amplifier (gain:

−10dB). The capacitor of 10nF between AINL+/

− (AINR+/−) decreases the clock feedthrough noise of the modulator, and it composes a 1st order LPF (fc=360kHz) with a 22

Ω resistor before the capacitor. This circuit also has a 1st order LPF (fc=370kHz) composed of op-amp. Refer to an evaluation board for details.

910

4.7k

470p

4.7k

VP+

47

μ

Analog In

3k

22

2.82Vpp

AIN+

9.3Vpp

VP-

NJM5532

Bias

910

470p

10n

AK4621

VA

47

μ

3k

22

10k

0.1

μ

10

μ

AIN-

10k

Bias

VA = 5V

VP+ = 15V

VP- = -15V

Bias

2.82Vpp

Figure 18. Input Buffer Example

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5. Analog Outputs

The analog outputs are fully differential and 2.8Vpp (typ. VREF = 5V), centered around VCOM. The differential outputs are summed externally: Vout = (AOUT+)-(AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output range is 5.6Vpp (typ. VREF = 5V). The bias voltage of the external summing circuit is supplied externally. The input data format is 2’s complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for

800000H(@24bit). The ideal AOUT is 0V for 000000H(@24bit).

The internal switched-capacitor filter and the external LPF attenuate the noise generated by the delta-sigma modulator beyond the audio passband.

Figure 19 shows an example of external LPF circuit summing the differential outputs by an op-amp.

Figure 20 shows an

example of differential outputs and LPF circuit example by three op-amps.

AK4621

4.7k

4.7k

AOUT-

200 330p

+Vop

4.7k

2.2n

200

AOUT+

Analog

Out

4.7k

330p

-Vop

Figure 19. External LPF Circuit Example 1 (fc = 136kHz, Q=0.694)

Frequency Response

20kHz

40kHz

80kHz

Gain

−0.01dB

−0.06dB

−0.59dB

Table 19. Frequency Response of External LPF Circuit Example 1

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[AK4621]

AOUTL-

+

100u

330 3.9n

3.3n

180

3

2

7

+

-

6

4

NJM5534D

+

0.1u

10u

680

+

0.1u

10u

AOUT L+

+

100u

330

3.9n

3.3n

180

+

10u

3

2

7

+

-

6

4

NJM5534D

+

0.1u

10u

680

0.1u

+15

-15

620

620

560

0.1u

1.0n

2

-

4

100

6

3

+

1.0n

7

NJM5534D

Lch

0.1u

+

10u

Figure 20. External LPF Circuit Example 2

Cut-off Frequency

1 st

Stage

182kHz

2 nd

Stage

284kHz

Total

-

Gain +3.9dB +3.02dB

Frequency

Response

20kHz

40kHz

80kHz

-0.025 -0.021 -0.046dB

-0.106 -0.085 -0.191dB

-0.517 -0.331 -0.848dB

Table 20. Frequency Response of External LPF Circuit Example 2

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30pin VSOP (Unit: mm)

*9. 7

±0.1

0. 3

30

PACKAGE

16

1. 5MAX

A

[AK4621]

1

0.24

± 0.06

0.12

M

15

0.65

0. 17

+0.06

-0.05

D et ail A

0.08

S

0° ~ 8°

N OTE: Dimension "* " does not include mold flash.

Package & Lead frame material

Package molding compound: Epoxy Resin, Halogen (bromine and chlorine) free

Lead frame material: Cu Alloy

Lead frame surface treatment: Solder (Pb free) plate

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[AK4621]

MARKING

AKM

AK4621EF

XXXXYYYYZ

XXXX, Z: Internal control code

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[AK4621]

REVISION HISTORY

Date (

YY/MM/DD

) Revision Reason Page/Line Contents

First

Digital filter names were changed.

Change

IMPORTANT NOTICE

These products and their specifications are subject to change without notice.

When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei

Microdevices Corporation (AKM) or authorized distributors as to current status of the products.

Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein.

Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials.

AKM products are neither intended nor authorized for use as critical components

Note1)

in any safety, life support, or other hazard related device or system

Note2)

, and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here:

Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability.

Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property.

It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

MS1258-E-01

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datasheet for AK4621 by Asahi Kasei Microdevices

24-Bit 192kHz Stereo Audio CODEC

Top View

30pin VSOP (Unit: mm)

AK4621EF

XXXXYYYYZ

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Table of contents

datasheet for AK4621 by Asahi Kasei Microdevices

24-Bit 192kHz Stereo Audio CODEC

Top View

30pin VSOP (Unit: mm)

AK4621EF

XXXXYYYYZ

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Table of contents