AN 471: High-Performance FPGA PLL Analysis with TimeQuest

AN 471: High-Performance FPGA PLL Analysis with TimeQuest
High-Performance FPGA
PLL Analysis with TimeQuest
Application Note 471
August 2007, ver. 1.0
Introduction
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Phase-locked loops (PLLs) provide robust clock management and clock
synthesis capabilities for maximum total system performance. Altera’s
high-density Stratix device families provide many highly versatile PLLs,
and each PLL can be customized as a zero delay buffer, jitter attenuator,
low skew fan-out buffer, or as a frequency synthesizer. To take advantage
of the numerous features and capabilities provided by the Stratix device
families, you should have a full understanding of all PLL-related reports
generated by the Quartus® II software and the TimeQuest Timing
Analyzer. This application note guides you through constraining PLLs
and performing a timing analysis on the PLLs. Each of these steps
includes examples and guidelines on how to read and understand the
various reports relating to PLLs, and how to analyze and constrain PLLs
in the TimeQuest Timing Analyzer.
Refer to the respective Stratix device handbook for specifications of the
PLL features available on your selected device. Also, refer to the altpll
Megafunction User Guide for information about how to customize the
Stratix PLLs.
This document includes the following topics:
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■
■
■
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PLL Overview
“PLL Overview”
“PLL Reports” on page 3
“Constraining PLLs” on page 7
“TimeQuest Reports” on page 9
“PLL Features” on page 13
One of the primary uses of a PLL is to synchronize the phase and
frequency of an internal or external clock to an input reference clock.
Numerous PLL components must work together to achieve this phase
alignment.
PLLs in the Stratix device families align the rising edge of the reference
input clock to a feedback clock using a phase frequency detector (PFD)
(Figure 1). The falling edges are determined by the duty cycle
specifications. The PFD produces an up or down signal that determines
whether the voltage controlled oscillator (VCO) should operate at a
higher or lower frequency. The PFD output is applied to the charge pump
and loop filter, which produce a control voltage for setting the frequency
of the VCO. If the PFD produces an up signal, the VCO frequency
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AN-471-1.0
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High-Performance FPGA PLL Analysis with TimeQuest
increases, while a down signal causes the VCO frequency to decrease. The
PFD outputs these up and down signals to a charge pump. If the charge
pump receives an up signal, current is driven into the loop filter.
Conversely, if the charge pump receives a down signal, current is drawn
from the loop filter. The loop filter converts these up and down signals to
a voltage that is used to bias the VCO. The loop filter also removes
glitches from the charge pump and prevents voltage overshoot, which
minimizes the jitter on the VCO.
The voltage from the loop filter determines how fast the VCO operates.
The VCO is implemented as a four-stage differential ring oscillator. A
divide counter (M) is inserted in the feedback loop to increase the VCO
frequency above the input reference frequency, making the VCO
frequency (fVCO) equal to M times the input reference clock (fREF). The fREF
to the PFD is equal to the input clock (fIN) divided by the pre-scale counter
(N). Therefore, the feedback clock (fFB) that is applied to one input of the
PFD is locked to the fREF that is applied to the other input of the PFD.
Figure 1 is a simplified block diagram that shows the major components
of the Stratix III PLL.
Figure 1. Stratix III PLL Block Diagram
To DPA block on
Left/Right PLLs
Lock
Circuit
pfdena
Casade output
to adjacent PLL
locked
/2, /4
÷C0
4
÷n
inclk0
Clock
GCLK/RCLK
inclk1 Switchover
Block
PFD
CP
LF
VCO
8
8
÷2
8
÷C1
÷C2
clkswitch
clkbad0
clkbad1
activeclock
÷C3
Cascade input
from adjacent PLL
÷Cn
÷m
no compensation mode
ZDB, External feedback modes
LVDS Compensation mode
Source Synchronous, normal modes
PLL Output Mux
GCLKs
Clock inputs
from pins
RCLKs
External clock
outputs
DIFFIOCLK from
Left/Right PLLs
LOAD_EN from
Left/Right PLLs
FBOUT
External
memory
interface DLL
FBIN
DIFFIOCLK network
GCLK/RCLK network
The following section provides an overview of the altpll megafunction.
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PLL Reports
altpll Megafunction Overview
The altpll megafunction provides support for the customization of the
PLLs in the Stratix device families. The altpll megafunction implements
different PLL configurations to generate and customize clock signals,
distribute clock signals to different devices in a design, reduce clock skew
between devices, and generate internal clock signals.
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PLL Reports
For more information about the altpll megafunction, refer to the altpll
Megafunction User Guide.
PLL reports play an important part in PLL analysis. Both the Quartus II
software and the TimeQuest Timing Analyzer generate reports that allow
you to verify the functionality and implemenation of all PLLs in your
design.
This section describes the various reports available.
Fitter Reports
After a full compilation in the Quartus II software, the Fitter report,
contained in the Compilation Report, provides details that show the
various configurations of all the PLLs implemented in the target Stratix
device. There are two reports that provide information on the PLL
implementation in the device: the PLL Summary report and the PLL
Usage report. Both reports are located under Resource Section in the
Fitter folder of the Compilation Report.
1
These reports are not generated if the design does not include
PLLs.
PLL Summary Report
The PLL Summary report lists information about the specific type of PLL
chosen in the design. Table 1 describes the different PLL properties
shown in the PLL Summary report.
1
Not all PLL properties shown in Table 1 are available for all
PLLs in the Stratix device families.
Table 1. PLL Summary Report Values (Part 1 of 3)
PLL Property
Description
PLL type
Shows the type of PLL.
PLL mode
Shows the PLL operating mode.
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Table 1. PLL Summary Report Values (Part 2 of 3)
PLL Property
Description
Feedback source
Shows which output clock has a board level connection to the external
feedback input pin to the PLL.
Compensate clock
Shows the PLL compensate clock source.
Switchover type
Shows the clock switchover type selected by the user.
Switchover on loss of clock
Shows whether or not the switchover on loss of clock was turned on for the
PLL.
Switchover counter
Shows the value of the PLL switchover counter.
Self reset on gated loss of lock
Shows whether a self reset is asserted on loss of lock.
Gate lock counter
Shows the value of the 20-bit counter (0–1048575) that gates the locked
output from the PLL.
Input frequency 0
Shows the input frequency for input clock 0 in MHz.
Input frequency 1
Shows the input frequency for input clock 1 in MHz.
Nominal PFD frequency
Shows the value of the nominal PFD frequency for the PLL in MHz.
Nominal VCO frequency
Shows the value of the nominal VCO frequency for the PLL in MHz.
VCO post scale
Shows the value of the VCO post-scale counter.
VCO frequency control
Shows the VCO frequency control mode.
VCO multiply
Shows the multiplication factor for the VCO output clock.
VCO divide
Shows the division factor for the VCO output clock.
Freq min lock
Shows the minimum lock input frequency, in MHz, for the PLL.
Freq max lock
Shows the maximum lock input frequency, in MHz, for the PLL.
M VCO Tap
Shows the value of the M VCO tap.
M initial
Shows the number of initial VCO cycles before the M counter starts.
M value
Shows the value of the M counter.
N value
Shows the value of the N counter.
M2 value
Shows the spread spectrum modulus for the M counter.
N2 value
Shows the spread spectrum modulus for the N counter.
SS counter
Shows the value for the spread spectrum counter for the PLL.
Downspread
Shows the downspread percentage for the PLL.
Spread frequency
Shows the spread frequency for the PLL in MHz.
Charge pump current
Shows the charge pump current value for the PLL in microamperes.
Loop filter resistance
Shows the value for the loop filter R resistor in Ohms.
Loop filter capacitance
Shows the value for the loop filter C capacitor in picoFarads.
Bandwidth
Shows the typical and minimum to maximum bandwidth value for the PLL in
MHz or KHz.
Real time configurable
Shows whether the real time configuration option was turned on for the PLL.
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PLL Reports
Table 1. PLL Summary Report Values (Part 3 of 3)
PLL Property
Scan chain MIF file
Description
Shows the Memory Initialization File (.mif) generated by the compiler to
represent the initial state of the scan chain. Use with the altpll_reconfig
megafunction to reconfigure the PLL.
Preserve counter order
Allows you to use specific counters with specific clock outputs.
PLL location
Shows the location of the PLL.
Inclk0 signal
Shows the primary clock input to the PLL.
Inclk1 signal
Shows the secondary clock input to the PLL.
Inclk0 signal type
Shows the primary clock input to the PLL type.
Inclk1 signal type
Shows the secondary clock input to the PLL type
Figure 2 shows a portion of the PLL Summary report generated for a
sample design.
Figure 2. Sample PLL Summary Report
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PLL Usage Report
The PLL Usage report shows the values of the specific output clock(s) for
the PLLs in the design.
Table 2 describes the PLL properties shown in the PLL Usage report.
Table 2. PLL Usage Report Values
Column Heading
Name
Description
Shows the instance name of the PLL.
Output clock
Shows the output clock that was specified for the PLL.
Mult
Shows the multiplication factor for the PLL output clock.
Div
Shows the division factor for the PLL output clock.
Output Frequency
Shows the clock frequency value for the PLL output port.
This value is equal to the input frequency multiplied by the
multiplication factor for the PLL output port, divided by the
division factor for the PLL output port.
Phase Shift
Shows the value specified for the phase shift of the PLL
output clock, measured in degrees and picoseconds.
Duty Cycle
Shows the duty cycle of the output clock.
Counter
Shows the counter specified for the PLL output clock.
Counter Value
Shows the counter value for the PLL. This value is equal to
the sum of the high and low cycles specified for the PLL.
Bypass is shown if there are no high or low cycles specified
for the PLL.
High/Low
Shows the number of high and low cycles for the PLL.
Cascade Input
Specifies the name of the preceding counter that is feeding
the cascade input of the current counter.
Initial
Shows the number of initial VCO cycles before the counter
starts.
VCO Tap
Shows the VCO tap value for the counter.
Figure 3 shows a portion of the PLL Usage report generated for a sample
design.
Figure 3. Sample PLL Usage Report
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Constraining PLLs
Constraining
PLLs
All clocks of the Stratix PLLs must be constrained to obtain a thorough
static timing analysis with the TimeQuest Timing Analyzer. Without the
proper clock constraints on the input and outupt clocks of the PLL, the
TimeQuest Timing Analyzer will not analyze any clock transfers from
these clocks. The TimeQuest Timing Analyzer supports three clock
constraints for constraining PLL clocks:
■
■
■
derive_pll_clocks—Used to automatically create generated
clocks on the PLL output clocks.
create_clock—Used to create a base clock.
create_generated_clock—Used to create a derived/generated
clock.
Perform the following steps to constrain all PLLs:
1.
Constrain all input clocks to the PLL. Use the create_clock
command. For example, create_clock -period 10 -name \
clk_sys [get_ports inclk_pll]
2.
Constrain all PLL output clocks in one of the following ways:
●
Use derive_pll_clocks to automatically constrain the PLL
output clocks.
or
●
Use create_generated_clock to constrain the PLL output
clocks individually.
Altera recommends that you use the derive_pll_clocks command to
automatically constrain the PLL output clocks. This allows the PLL
output clock properties to be automatically updated if any of the clock
properties are changed by the PLL MegaWizard® plug-in. Without the
derive_pll_clocks command, each individual
create_generated_clock constraint needs to be updated if any PLL
output clock properties change.
If the derive_pll_clocks command is used, any input clocks to the
PLL must still be constrained. There is no need to issue the
derive_pll_clocks command multiple times in the same analysis.
The first time the command is issued, all PLL output clocks are
constrained.
If individual create_generated_clock constraints are used to
constrain the PLL output clocks, the TimeQuest Timing Analyzer issues a
warning if there are differences between the parameters specified in the
create_generated_clock constraints and the parameters specified
for the PLL output clocks in the megafunction.
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Figure 4 shows a typical PLL design in a Stratix III device.
Figure 4. Stratix III PLL Design
To constrain the clocks shown in Figure 4, the following constraints can
be applied:
# create a base clock for the input of the PLL
create_clock -period 10 -name clk_sys [get_ports inclk_pll]
# automatically create generated clocks on the output clocks of the PLL
derive_pll_clocks
Without the use of the derive_pll_clocks command, the PLL output
clocks can be constrained as shown in the following example:
# create a generated clock on the first output clock of the PLL
create_generated_clock -source \
pll|altpll_component|auto_generated|pll1|inclk[0] \
-name my_pll_clk[0] pll|altpll_component|auto_generated|pll1|clk[0]
# create a generated clock on the second output clock of the PLL
create_generated_clock -source \
pll|altpll_component|auto_generated|pll1|inclk[0] \
-multiply_by 2 -name my_pll_clk[1] \
pll|altpll_component|auto_generated|pll1|clk[1]
# create a base clock for the input of the PLL
create_clock -period 10 -name clk_sys [get_ports inclk_pll]
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TimeQuest Reports
TimeQuest
Reports
The TimeQuest Timing Analyzer provides various reports that can be
used to verify that all PLL parameters have been specified correctly.
Report Clocks Report
The Report Clocks report summarizes all clocks that have been created in
the design. This report details all parameters specified for all base clocks
and all generated clocks in the design.
Table 3 describes the clock properties shown in the Report Clock report.
Table 3. Report Clocks Report Properties
Column Heading
Description
Clock Name
Shows the name of the clock.
Type
Shows the type of clock—either Base or Generated.
Period
Shows the period for the clock.
Rise
Shows the initial rise edge of the clock.
Fall
Shows the initial fall edge of the clock.
Duty Cycle
Shows the duty cycle of the clock.
Divide by
Shows any divide by factor for the clock.
Multiply by
Shows any multiply by factor for the clock.
Phase
Shows any phase shift of the clock.
Offset
Shows any offset of the clock.
Edge List
Shows the edge list for the clock.
Edge Shift
Shows the edge shift for the clock.
Inverted
Shows whether the clock is inverted with respect to the
source clock.
Master
Shows the master clock.
Slave
Shows the source node for the clock.
Targets
Shows the node that the clock has been applied to.
Figure 5 shows a sample Report Clocks report.
Figure 5. Report Clocks Report
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The Report Clocks report contains various columns that show the
properties of each clock in the design. Use the report_clocks
command to generate a Report Clocks report.
Usage:
report_clocks [-append] [-desc] [-file <name>]
[-panel_name <name>] [-stdout] [-summary]
-append
If output is sent to a file, this option appends the
result to that file. Otherwise, the file is overwritten.
-desc
Sorts the clocks by name in descending order
(ascending order is the default).
-file <name>
Sends the results to a file.
-panel_name
<name>
Sends the results to the panel and specifies the name
of the new panel.
-stdout
Sends the output to stdout, via messages. Use this
option if you have selected another output format,
such as a file, and would also like to receive
messages.
-summary
Creates a single table with a summary of each clock.
Report Timing Report
The Report Timing report shows the data arrival and data required times,
and the associated slack for any register-to-register path. Various analysis
types can be performed, including setup, hold, recovery, and removal.
The Report Timing report also shows the timing delays, including
compensation delay, for any PLLs that are part of the clock path.
Figure 6 shows a sample Report Timing report, with the detail level set to
Full Path, for a register-to-register path.
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For more information about the Report Timing detail levels, refer to the
Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the
Quartus II Handbook.
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TimeQuest Reports
Figure 6. Report Timing Report
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With the detail level set to Full Path, the entire clock path is shown in the
Data Arrival Path and Data Required Path sections of the report. The
report includes the columns shown in Table 4
Table 4. Report Timing Report Description
Column Heading
Incr
Description
Shows the time delay increment by the element.
RF
Shows the input and output transitions for the element.
Type
Shows the type of resource of the element.
Fanout
Shows the number of fanouts from the element.
Location
Shows the location on the Stratix device.
Element
Shows the name of the element.
For the Data Arrival Path, lines 3 to 9 detail the clock path to the source
register, as shown in Table 5.
Table 5. Clock Path Description
Line Number
Line 3
Description
Shows the input clock port named inclk_pll located at
IOPAD X0 Y23.
Lines 4 and 5
Show the path through the input buffer of IOPAD X0 Y23.
Line 6
Shows the interconnect delay to the input pin of the PLL.
Line 7
Shows the compensation delay due to the PLL. This is
indicated by the COMP entry in the Type column.
Lines 8 and 9
Show the interconnect and global buffer delays, respectively.
Line 7 shows the total PLL compensation if the PLL is in normal mode,
source-synchronous mode, or zero delay buffer mode.
1
The TimeQuest Timing Analyzer does not report which mode
the PLL has been set to. The PLL mode can be determined in the
PLL Summary report.
Any specified phase shift of the PLL output clocks appears as part of the
Launch Time or Latch Time, depending on the clock path to either the
source register or destination register, respectively.
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PLL Features
PLL Features
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The following sections describe some of the PLL features available in the
Stratix device family.
Refer to the respective Stratix device handbook for specifications of the
PLL features available on your selected device.
Clock Switchover
Clock switchover is a feature that allows the PLL to switch between two
input reference clocks. You can use clock switchover for clock
redundancy, or for a dual clock domain application. This feature of the
Stratix PLLs can be used to develop a highly reliable system in which you
can use a redundant clock in case the primary clock fails. Clock
switchover can be performed automatically, when the clock is no longer
toggling, or manually through a user control signal.
You must create clocks on the inputs of the PLL clock pins in the
TimeQuest Timing Analyzer. The PLL output clocks can be either created
individually or with the derive_pll_clocks command.
Figure 7 shows a typical PLL with clock switchover enabled.
Figure 7. Typical PLL with Clock Switchover Enabled
The PLL input clock 0 is set to 100 MHz and the input clock 1 is set to 200
MHz. To constrain the clocks in this design you can specify the following
constraints:
# create input clock 0
create_clock -period 10 -name clk_100 [get_ports clk_a]
# create input clock 1
create_clock -period 5 -name clk_200 [get_ports clk_b]
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# create the PLL output clocks
derive_pll_clocks
The derive_pll_clocks command will constrain the two PLL output
clocks with respect to the two input clocks. For the above design, the
following constraints are created:
create_generated_clock -source inst1|altpll_component|pll|inclk[0] -name \
inst1|altpll_component|pll|clk[0] inst1|altpll_component|pll|clk[0]
create_generated_clock -source inst1|altpll_component|pll|inclk[1] -name \
inst1|altpll_component|pll|clk[0]~1 inst1|altpll_component|pll|clk[0]
create_generated_clock -source inst1|altpll_component|pll|inclk[0] -phase 90.00 -name \
inst1|altpll_component|pll|clk[1] inst1|altpll_component|pll|clk[1]
create_generated_clock -source inst1|altpll_component|pll|inclk[1] -phase 90.00 -name \
inst1|altpll_component|pll|clk[1]~1 inst1|altpll_component|pll|clk[1]
Alternatively, to manually constrain the PLL in Figure 7, you can specify
the following constraints:
# create input clock 0
create_clock -period 10 -name clk_100 [get_ports clk_a]
# create input clock 1
create_clock -period 5 -name clk_200 [get_ports clk_b]
# create the PLL output clocks
derive_pll_clocks
# create the generated clocks on the output of PLL clk0
# sourced from inclk0
create_generated_clock -source inst1|altpll_component|pll|inclk[0] -name pll_inclk0_clk0 \
inst1|altpll_component|pll|clk[0]
# sourced from inclk1
create_generated_clock -source inst1|altpll_component|pll|inclk[1] -name pll_inclk1_clk0 \
inst1|altpll_component|pll|clk[0] -add
# create the generated clocks on the output of PLL clk1
# sourced from inclk0
create_generated_clock -source inst1|altpll_component|pll|inclk[0] -phase 90.00 -name \
pll_inclk0_clk1 inst1|altpll_component|pll|clk[1]
# sourced from inclk1
create_generated_clock -source inst1|altpll_component|pll|inclk[1] -phase 90.00 -name \
pll_inclk1_clk1 inst1|altpll_component|pll|clk[1] -add
1
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When manually applying two or more clocks to the same node,
-add must be included.
Altera Corporation
PLL Features
Clock Uncertainty
Clock uncertainty is defined as the interval of confidence around the ideal
clock value such that the measured value is always inside this stated
interval.
The following are the common sources of clock uncertainty:
■
■
■
■
Clock jitter
Clock skew
Duty cycle distortion
Phase shift error (when using non-zero PLL phase shifts)
Use the set_clock_uncertainty constraint to model jitter, skew, and
a guard band associated with clock signals. When a clock uncertainty
assignment exists for a clock signal, the TimeQuest Timing Analyzer
performs the most conservative setup and hold checks. An uncertainty
value of 0.5 ns for clk0 (with a clock period of 10 ns) means the first
rising edge of clk0 can arrive at any time between –0.5 and 0.5 ns, and
the first falling edge of clk0 can arrive at any time between 4.5 and 5.5
ns. This uncertainty interval effectively reduces the available launch and
latch time period to 10 – 1 = 9 ns (Figure 8).
Figure 8. Clock Uncertainty
Effective Clock Setup Relationship = 9 ns
Clock Uncertainty
1
-0.5 0.5
4.5 5.5
9.5 10.5
0
5
10
The set_clock_uncertainty constraint does not change the
micro tSU and tH values of the internal registers of the device, but
decreases the clock setup and clock hold relationships for any
register-to-register paths.
Use set_clock_uncertainty -setup to apply a setup uncertainty
value or set_clock_uncertainty -hold to apply a hold uncertainty
value to a clock signal, or as a point-to-point assignment between two
clocks. For a setup check, the TimeQuest Timing Analyzer subtracts the
specified clock setup uncertainty from the data required time. For a hold
check, the TimeQuest Timing Analyzer adds the specified clock hold
uncertainty to the data required time.
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High-Performance FPGA PLL Analysis with TimeQuest
Figure 9 shows the Data Arrival Path and Data Required Path reports for
a setup check performed on a single clock domain register-to-register
path. A 10 ns clock drives the clock port of the registers and no
uncertainty constraints have been applied to the clock. The data arrival
time is 3.331 ns, and the data required time is 12.639 ns. The slack time for
this path is 9.308.
Figure 9. Data Arrival and Data Required Times without Clock Uncertainty
Figure 10 shows the Data Arrival Path and Data Required Path reports for
a setup check performed on a single clock domain register-to-register
path. A 10 ns clock drives the clock port of the registers and a setup
uncertainty of 0.2 ns (Data Required Path line 2) has been applied to the
clock. The data arrival time is 3.331 ns (Data Arrival Path line 8), and the
data required time is 12.439 ns (Data Required Path line 3). The slack time
for this path is 9.108 ns.
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Conclusion
Figure 10. Data Arrival and Data Required Times with Clock Uncertainty
Conclusion
The Stratix device family PLLs provide complete control of device clocks
and system timing. This application note enables you to take advantage
of the numerous features and capabilities provided by the Stratix PLLs.
Detailed information about all reports and analysis performed by the
Quartus II software and the TimeQuest Timing Analyzer is presented,
along with examples and guidelines on how to read and understand the
various Timing Analysis reports relating to PLLs.
Referenced
Documents
This application note references the following documents:
■
■
■
■
■
■
■
■
Altera Corporation
altpll Megafunction User Guide
Cyclone III Device Handbook
Cyclone II Device Handbook
Cyclone Device Handbook
Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the
Quartus II Handbook
Stratix III Device Handbook
Stratix II Device Handbook
Stratix Device Handbook
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High-Performance FPGA PLL Analysis with TimeQuest
Document
Revision History
Table 6 shows the revision history for this application note.
Table 6. Document Revision History
Date and Document
Version
August 2007
v1.0
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Technical Support:
www.altera.com/support/
Literature Services:
[email protected]
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Changes Made
Initial release.
Summary of Changes
—
Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company,
the stylized Altera logo, specific device designations, and all other words and logos that are identified as
trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending
applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products
to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability
arising out of the application or use of any information, product, or service described
herein except as expressly agreed to in writing by Altera Corporation. Altera customers
are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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