RM STM32L052K6 (RM0376)

RM STM32L052K6 (RM0376)
RM0376
Reference manual
Ultra-low-power STM32L0x2 advanced ARM®-based 32-bit MCUs
Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32L0x2 microcontroller memory and peripherals.
The STM32L0x2 is a line of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics please refer to the
corresponding datasheets.
For information on the ARM® Cortex®-M0+ core, please refer to the Cortex®-M0+ Technical
Reference Manual.
Related documents
• Cortex®-M0+ Technical Reference Manual, available from www.arm.com.
• STM32L0x2 datasheets.
April 2014
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Contents
RM0376
Contents
1
2
Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.1
List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.2
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.3
Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.4
Product category definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.1
System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.1.1
S0: Cortex-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.1.2
S1: DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.1.3
BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
AHB/APB bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
2.2
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.2.2
Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 48
2.3
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.4
Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Physical remap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Embedded boot loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3
Flash program memory and data EEPROM (FLASH) . . . . . . . . . . . . . . 54
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.2
NVM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3
NVM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3.1
NVM organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3.2
Reading the NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Protocol to read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Relation between CPU frequency/Operation mode/NVM read time. . . . . . . . . . .56
Data buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.3.3
Writing/erasing the NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Write/erase protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Unlocking/locking operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Detailed description of NVM write/erase operations. . . . . . . . . . . . . . . . . . . . . . .67
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
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3.4
Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4.1
RDP (Read Out Protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4.2
PcROP (Proprietary Code Read-Out Protection) . . . . . . . . . . . . . . . . . 78
3.4.3
Protections against unwanted write/erase operations . . . . . . . . . . . . . . 79
3.4.4
Write/erase protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.4.5
Protection errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Write protection error flag (WRPERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Read error (RDERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
3.5
NVM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.5.1
3.6
Bus error (Hard fault) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Memory interface management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.6.1
Operation priority and evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Write/erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Option byte loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
3.6.2
Sequence of operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Read as data while write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Fetch while write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Write while another write operation is ongoing . . . . . . . . . . . . . . . . . . . . . . . . . . .84
3.7
3.6.3
Change the number of wait states while reading . . . . . . . . . . . . . . . . . . 85
3.6.4
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Flash register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Read registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Write to registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
3.8
3.7.1
Access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.7.2
Program and erase control register (FLASH_PECR) . . . . . . . . . . . . . . 89
3.7.3
Power-down key register (FLASH_PDKEYR) . . . . . . . . . . . . . . . . . . . . 92
3.7.4
PECR unlock key register (FLASH_PEKEYR) . . . . . . . . . . . . . . . . . . . 92
3.7.5
Program and erase key register (FLASH_PRGKEYR) . . . . . . . . . . . . . 92
3.7.6
Option bytes unlock key register (FLASH_OPTKEYR) . . . . . . . . . . . . . 93
3.7.7
Status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.7.8
Option bytes register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.7.9
Write protection register (FLASH_WRPROT) . . . . . . . . . . . . . . . . . . . . 98
3.7.10
Flash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.8.1
Option bytes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.8.2
Mismatch when loading protection flags . . . . . . . . . . . . . . . . . . . . . . . 100
3.8.3
Reloading Option bytes by software . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 102
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.2
CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.3
CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Polynomial programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
4.4
5
CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.4.1
Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.4.2
Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . 105
4.4.3
Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.4.4
Initial CRC value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.4.5
CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.4.6
CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Firewall (FW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.2
Firewall main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.3
Firewall functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.3.1
Firewall AMBA bus snoop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.3.2
Functional requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Debug consideration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Interruptions management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
5.3.3
Firewall segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Code segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Non-volatile data segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Volatile data segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
5.3.4
Segment accesses and properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Segment access depending on the Firewall state . . . . . . . . . . . . . . . . . . . . . . .111
Segments properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
5.3.5
Firewall initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.3.6
Firewall states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Opening the Firewall. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Closing the Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
5.4
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Firewall registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
5.4.1
Code segment start address (FW_CSSA) . . . . . . . . . . . . . . . . . . . . . . 115
5.4.2
Code segment length (FW_CSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.4.3
Non-volatile data segment start address (FW_NVDSSA) . . . . . . . . . . 116
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5.4.4
Non-volatile data segment length (FW_NVDSL) . . . . . . . . . . . . . . . . . 117
5.4.5
Volatile data segment start address (FW_VDSSA) . . . . . . . . . . . . . . . 117
5.4.6
Volatile data segment length (FW_VDSL) . . . . . . . . . . . . . . . . . . . . . . 118
5.4.7
Configuration register (FW_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.4.8
Firewall register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1.1
Independent A/D and DAC converter supply and reference voltage . . 122
On TFBGA64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
On packages with 64 pins or less (except BGA package) . . . . . . . . . . . . . . . . .122
6.1.2
RTC and RTC backup registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
RTC registers access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
6.1.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.1.4
Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . 123
Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Range 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
6.2
6.3
6.1.5
Dynamic voltage scaling configuration . . . . . . . . . . . . . . . . . . . . . . . . 125
6.1.6
Voltage regulator and clock management when VDD drops
below 1.71 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.1.7
Voltage regulator and clock management when modifying the
VCORE range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.1.8
Voltage range and limitations when VDD ranges from 1.71 V to 2.0 V 126
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.2.1
Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . 129
6.2.2
Brown out reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.2.3
Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 130
6.2.4
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . 131
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.1
Behavior of clocks in low power modes . . . . . . . . . . . . . . . . . . . . . . . . 133
Sleep and Low power sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
6.3.2
Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.3
Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.4
Low power run mode (LP run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Entering Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Exiting Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
6.3.5
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Entering Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
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Exiting Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
6.3.6
Low power sleep mode (LP sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Entering Low power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Exiting Low power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
6.3.7
Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Entering Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Exiting Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
6.3.8
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Entering Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Exiting Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
I/O states in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
6.3.9
Waking up the device from Stop and Standby modes using the RTC
and comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
RTC auto-wakeup (AWU) from the Stop mode . . . . . . . . . . . . . . . . . . . . . . . . .141
RTC auto-wakeup (AWU) from the Standby mode. . . . . . . . . . . . . . . . . . . . . . .142
Comparator auto-wakeup (AWU) from the Stop mode. . . . . . . . . . . . . . . . . . . .142
6.4
7
Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.4.1
PWR power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . 143
6.4.2
PWR power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . 146
6.4.3
PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.1
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.1.1
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Low-power management reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Option byte loader reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
7.2
7.1.2
Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.1.3
RTC and backup registers reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.2.1
HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . . . . . . . .154
7.2.2
HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
7.2.3
MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
7.2.4
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HSI48 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
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7.2.5
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.2.6
LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
7.2.7
LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
LSI measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
7.3
7.2.8
System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
7.2.9
System clock source frequency versus voltage range . . . . . . . . . . . . . 158
7.2.10
HSE clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.2.11
LSE Clock Security System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.2.12
RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
7.2.13
Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
7.2.14
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
7.2.15
Internal/external clock measurement using TIM21 . . . . . . . . . . . . . . . 160
7.2.16
Clock-independent system clock sources for TIM2/TIM21/TIM22 . . . . 161
RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.3.1
Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.3.2
Internal clock sources calibration register (RCC_ICSCR) . . . . . . . . . . 165
7.3.3
Clock recovery RC register (RCC_CRRCR) . . . . . . . . . . . . . . . . . . . . 166
7.3.4
Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 166
7.3.5
Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 169
7.3.6
Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 171
7.3.7
Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 172
7.3.8
GPIO reset register (RCC_IOPRSTR) . . . . . . . . . . . . . . . . . . . . . . . . . 173
7.3.9
AHB peripheral reset register (RCC_AHBRSTR) . . . . . . . . . . . . . . . . 174
7.3.10
APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 175
7.3.11
APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 176
7.3.12
GPIO clock enable register (RCC_IOPENR) . . . . . . . . . . . . . . . . . . . . 178
7.3.13
AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 180
7.3.14
APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 182
7.3.15
APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 184
7.3.16
GPIO clock enable in sleep mode register (RCC_IOPSMENR) . . . . . 186
7.3.17
AHB peripheral clock enable in sleep mode
register (RCC_AHBSMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.3.18
APB2 peripheral clock enable in sleep mode
register (RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
7.3.19
APB1 peripheral clock enable in sleep mode
register (RCC_APB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.3.20
Clock configuration register (RCC_CCIPR) . . . . . . . . . . . . . . . . . . . . . 191
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7.3.21
Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.3.22
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
8.2
CRS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
8.3
CRS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
8.3.1
CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
8.3.2
Synchronization input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
8.3.3
Frequency error measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
8.3.4
Frequency error evaluation and automatic trimming . . . . . . . . . . . . . . 202
8.3.5
CRS initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
RELOAD value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
FELIM value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
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8.4
CRS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
8.5
CRS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
8.6
CRS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
8.6.1
CRS control register (CRS_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
8.6.2
CRS configuration register (CRS_CFGR) . . . . . . . . . . . . . . . . . . . . . . 206
8.6.3
CRS interrupt and status register (CRS_ISR) . . . . . . . . . . . . . . . . . . . 207
8.6.4
CRS interrupt flag clear register (CRS_ICR) . . . . . . . . . . . . . . . . . . . . 209
8.6.5
CRS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
9.2
GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
9.3
GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
9.3.1
General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
9.3.2
I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 214
9.3.3
I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
9.3.4
I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
9.3.5
I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
9.3.6
GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
9.3.7
I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
9.3.8
External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
9.3.9
Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
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9.4
10
9.3.10
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
9.3.11
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
9.3.12
Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
9.3.13
Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 219
9.3.14
Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 219
GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
9.4.1
GPIO port mode register (GPIOx_MODER) (x = A..D and H) . . . . . . . 220
9.4.2
GPIO port output type register (GPIOx_OTYPER) (x = A..D and H) . . 220
9.4.3
GPIO port output speed register (GPIOx_OSPEEDR)
(x = A..D and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
9.4.4
GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A..D and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
9.4.5
GPIO port input data register (GPIOx_IDR) (x = A..D and H) . . . . . . . 222
9.4.6
GPIO port output data register (GPIOx_ODR) (x = A..D and H) . . . . . 223
9.4.7
GPIO port bit set/reset register (GPIOx_BSRR) (x = A..D and H) . . . . 223
9.4.8
GPIO port configuration lock register (GPIOx_LCKR)
(x = A..D and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
9.4.9
GPIO alternate function low register (GPIOx_AFRL) (x = A..D and H) 225
9.4.10
GPIO alternate function high register (GPIOx_AFRH)
(x = A..D and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
9.4.11
GPIO port bit reset register (GPIOx_BRR) (x = A..D and H) . . . . . . . . 226
9.4.12
GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 229
10.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
10.2
SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
10.2.1
SYSCFG memory remap register (SYSCFG_CFGR1) . . . . . . . . . . . . 230
10.2.2
SYSCFG peripheral mode configuration register (SYSCFG_CFGR2) 231
10.2.3
Reference control and status register (REF_CFGR3) . . . . . . . . . . . . . 232
10.2.4
SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
10.2.5
SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
10.2.6
SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
10.2.7
SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
10.2.8
SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
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Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 238
11.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
11.2
DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
11.3
DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
11.3.1
DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
11.3.2
Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
11.3.3
DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Programmable data sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
Pointer incrementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
Channel configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Circular mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Memory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
11.3.4
Programmable data width, data alignment and endians . . . . . . . . . . . 241
Addressing an AHB peripheral that does not support byte or halfword write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
11.3.5
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
11.3.6
DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
11.3.7
DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
11.4
12
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DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
11.4.1
DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 246
11.4.2
DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 247
11.4.3
DMA channel x configuration register (DMA_CCRx) (x = 1..7,
where x= channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
11.4.4
DMA channel x number of data register (DMA_CNDTRx) (x = 1..7,
where x= channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
11.4.5
DMA channel x peripheral address register (DMA_CPARx) (x = 1..7,
where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
11.4.6
DMA channel x memory address register (DMA_CMARx) (x = 1..7,
where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
11.4.7
DMA channel selection register (DMA_CSELR) . . . . . . . . . . . . . . . . . 252
11.4.8
DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 256
12.1
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
12.2
SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
12.3
Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . 259
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13.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
13.2
EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
13.3
EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
13.3.1
EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
13.3.2
Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
13.3.3
Peripherals asynchronous interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 260
13.3.4
Hardware interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
13.3.5
Hardware event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
13.3.6
Software interrupt/event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
13.4
EXTI interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
13.5
EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
13.5.1
EXTI interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . 263
13.5.2
EXTI event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . 264
13.5.3
EXTI rising edge trigger selection register (EXTI_RTSR) . . . . . . . . . . 265
13.5.4
Falling edge trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . 265
13.5.5
EXTI software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . 266
13.5.6
EXTI pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
13.5.7
EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
14.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
14.2
ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
14.3
ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
14.4
ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
14.4.1
ADC voltage regulator (ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . 272
Analog reference for the ADC internal voltage regulator . . . . . . . . . . . . . . . . . .273
ADVREG enable sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
ADVREG disable sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
14.4.2
Calibration (ADCAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Calibration factor forcing Software Procedure . . . . . . . . . . . . . . . . . . . . . . . . . .274
14.4.3
ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . 275
14.4.4
ADC clock (CKMODE, PRESC[3:0], LFMEN) . . . . . . . . . . . . . . . . . . . 276
Low Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
14.4.5
Configuring the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
14.4.6
Channel selection (CHSEL, SCANDIR) . . . . . . . . . . . . . . . . . . . . . . . . 278
Temperature sensor, VREFINT internal channels. . . . . . . . . . . . . . . . . . . . . . . . .278
14.4.7
Programmable sampling time (SMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 278
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14.4.8
Single conversion mode (CONT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
14.4.9
Continuous conversion mode (CONT=1) . . . . . . . . . . . . . . . . . . . . . . . 279
14.4.10 Starting conversions (ADSTART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
14.4.11 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
14.4.12 Stopping an ongoing conversion (ADSTP) . . . . . . . . . . . . . . . . . . . . . 281
14.5
14.6
Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . 282
14.5.1
Discontinuous mode (DISCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
14.5.2
Programmable resolution (RES) - fast conversion mode . . . . . . . . . . 283
14.5.3
End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . 284
14.5.4
End of conversion sequence (EOSEQ flag) . . . . . . . . . . . . . . . . . . . . 285
14.5.5
Example timing diagrams (single/continuous modes . . . . . . . . . . . . . . . . .
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
14.6.1
Data register and data alignment (ADC_DR, ALIGN) . . . . . . . . . . . . . 287
14.6.2
ADC overrun (OVR, OVRMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
14.6.3
Managing a sequence of data converted without using the DMA . . . . 288
14.6.4
Managing converted data without using the DMA without overrun . . . 288
14.6.5
Managing converted data using the DMA . . . . . . . . . . . . . . . . . . . . . . 288
DMA one shot mode (DMACFG=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
DMA circular mode (DMACFG=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
14.7
Low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
14.7.1
Wait mode conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
14.7.2
Auto-off mode (AUTOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
14.8
Analog window watchdog (AWDEN, AWDSGL, AWDCH,
AWD_HTR/LTR, AWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
14.9
Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
14.9.1
ADC operating modes support when oversampling . . . . . . . . . . . . . . 294
14.9.2
Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
14.9.3
Triggered mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
14.10 Temperature sensor and internal reference voltage . . . . . . . . . . . . . . . . 296
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
Reading the temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
Calculating the actual VDDA voltage using the internal reference voltage . . . . .297
Converting a supply-relative ADC measurement to an absolute voltage value .297
14.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
14.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
14.12.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 299
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14.12.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 300
14.12.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
14.12.4 ADC configuration register 1 (ADC_CFGR1) . . . . . . . . . . . . . . . . . . . 304
14.12.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . . 307
14.12.6 ADC sampling time register (ADC_SMPR) . . . . . . . . . . . . . . . . . . . . . 308
14.12.7 ADC watchdog threshold register (ADC_TR) . . . . . . . . . . . . . . . . . . . 309
14.12.8 ADC channel selection register (ADC_CHSELR) . . . . . . . . . . . . . . . . 310
14.12.9 ADC data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
14.12.10 ADC Calibration factor (ADC_CALFACT) . . . . . . . . . . . . . . . . . . . . . . 311
14.12.11 ADC common configuration register (ADC_CCR) . . . . . . . . . . . . . . . . 312
14.12.12 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
15
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
15.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
15.2
DAC1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
15.3
Single mode functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
15.3.1
DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
15.3.2
DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
15.3.3
DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
15.3.4
DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Independent trigger with single LFSR generation . . . . . . . . . . . . . . . . . . . . . . .319
Independent trigger with single triangle generation . . . . . . . . . . . . . . . . . . . . . .319
15.3.5
DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
15.3.6
DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
15.4
Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
15.5
Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
15.6
DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
DMA underrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
15.7
DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
15.7.1
DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
15.7.2
DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . . 325
15.7.3
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
15.7.4
DAC channel1 12-bit left-aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
15.7.5
DAC channel1 8-bit right-aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
15.7.6
DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 326
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15.7.7
DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
15.7.8
DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
16.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
16.2
COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
16.3
COMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
16.3.1
COMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
16.3.2
COMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
16.3.3
COMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
16.3.4
Comparator LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
16.4
Power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
16.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
16.6
COMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
16.6.1
Comparator 1 control and status register (COMP1_CSR) . . . . . . . . . . 332
16.6.2
Comparator 2 control and status register (COMP2_CSR) . . . . . . . . . . 333
16.6.3
COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
17.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
17.2
TSC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
17.3
TSC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
17.3.1
TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
17.3.2
Surface charge transfer acquisition overview . . . . . . . . . . . . . . . . . . . 337
17.3.3
Reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
17.3.4
Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . 340
17.3.5
Spread spectrum feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
17.3.6
Max count error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
17.3.7
Sampling capacitor I/O and channel I/O mode selection . . . . . . . . . . . 342
17.3.8
Acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
17.3.9
I/O hysteresis and analog switch control . . . . . . . . . . . . . . . . . . . . . . . 343
17.3.10 Capacitive sensing GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
17.4
TSC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
17.5
TSC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
17.6
TSC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
17.6.1
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TSC control register (TSC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
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17.6.2
TSC interrupt enable register (TSC_IER) . . . . . . . . . . . . . . . . . . . . . . 347
17.6.3
TSC interrupt clear register (TSC_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 348
17.6.4
TSC interrupt status register (TSC_ISR) . . . . . . . . . . . . . . . . . . . . . . . 349
17.6.5
TSC I/O hysteresis control register (TSC_IOHCR) . . . . . . . . . . . . . . . 349
17.6.6
TSC I/O analog switch control register (TSC_IOASCR) . . . . . . . . . . . 350
17.6.7
TSC I/O sampling control register (TSC_IOSCR) . . . . . . . . . . . . . . . . 351
17.6.8
TSC I/O channel control register (TSC_IOCCR) . . . . . . . . . . . . . . . . . 351
17.6.9
TSC I/O group control status register (TSC_IOGCSR) . . . . . . . . . . . . 352
17.6.10 TSC I/O group x counter register (TSC_IOGxCR) (x = 1..8) . . . . . . . . 352
17.6.11 TSC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
18
Advanced encryption standard hardware accelerator (AES) . . . . . . 355
18.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
18.2
AES main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
18.3
AES functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
18.4
Encryption and derivation keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
18.5
AES chaining algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
18.5.1
Electronic CodeBook (ECB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
18.5.2
Cipher block chaining (CBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Suspended mode for a given message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
18.5.3
Counter Mode (CTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Suspend mode in CTR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
18.6
Data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
18.7
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
18.7.1
Mode 1: encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
18.7.2
Mode 2: key derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
18.7.3
Mode 3: decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
18.7.4
Mode 4: key derivation and decryption . . . . . . . . . . . . . . . . . . . . . . . . 369
18.8
AES DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
18.9
Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
18.10 Processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
18.11 AES interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
18.12 AES registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
18.12.1 AES control register (AES_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
18.12.2 AES status register (AES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
18.12.3 AES data input register (AES_DINR) . . . . . . . . . . . . . . . . . . . . . . . . . 375
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18.12.4 AES data output register (AES_DOUTR) . . . . . . . . . . . . . . . . . . . . . . 375
18.12.5 AES key register 0(AES_KEYR0) (LSB: key [31:0]) . . . . . . . . . . . . . . 376
18.12.6 AES key register 1 (AES_KEYR1) (Key[63:32]) . . . . . . . . . . . . . . . . . 376
18.12.7 AES key register 2 (AES_KEYR2) (Key [95:64]) . . . . . . . . . . . . . . . . . 377
18.12.8 AES key register 3 (AES_KEYR3) (MSB: key[127:96]) . . . . . . . . . . . . 377
18.12.9 AES initialization vector register 0 (AES_IVR0) (LSB: IVR[31:0]) . . . . 377
18.12.10 AES initialization vector register 1 (AES_IVR1) (IVR[63:32]) . . . . . . . 378
18.12.11 AES initialization vector register 2 (AES_IVR2) (IVR[95:64]) . . . . . . . 379
18.12.12 AES initialization vector register 3 (AES_IVR3) (MSB: IVR[127:96]) . 379
18.12.13 AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
19
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
19.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
19.2
RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
19.3
RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
19.3.1
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
19.3.2
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
If the CEIS bit is read as ‘1’ (clock error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
If the SEIS bit is read as ‘1’ (seed error). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
19.4
20
RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
19.4.1
RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
19.4.2
RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
19.4.3
RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
19.4.4
RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
General-purpose timers (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
20.1
TIM2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
20.2
TIM2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
20.3
TIM2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
20.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Prescaler description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
20.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Upcounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389
Downcounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
Center-aligned mode (up/down counting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
20.3.3
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Internal clock source (CK_INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
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External clock source mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
External clock source mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
20.3.4
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
20.3.5
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
20.3.6
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
20.3.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
20.3.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
20.3.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
PWM edge-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
Downcounting configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
PWM center-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
20.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Particular case: OCx fast enable: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413
20.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 413
20.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
20.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
20.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 417
Slave mode: Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
Slave mode: Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418
Slave mode: Trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418
Slave mode: External Clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . .419
20.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Using one timer as prescaler for another . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
Using one timer to enable another timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421
Using one timer to start another timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
Using one timer as prescaler for another timer . . . . . . . . . . . . . . . . . . . . . . . . .424
Starting 2 timers synchronously in response to an external trigger . . . . . . . . . .424
20.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
20.4
TIM2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
20.4.1
TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 426
20.4.2
TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 428
20.4.3
TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 429
20.4.4
TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 431
20.4.5
TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
20.4.6
TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 434
20.4.7
TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 435
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .435
Input capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437
20.4.8
TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 438
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Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .438
Input capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .439
20.4.9
TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . 439
20.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
20.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
20.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 441
20.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 441
20.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 442
20.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 443
20.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 443
20.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 444
20.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 444
Example of how to use the DMA burst feature . . . . . . . . . . . . . . . . . . . . . . . . . .444
20.4.19 TIM2 option register (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
20.4.20 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
21
General-purpose timers (TIM21/22) . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
21.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
21.2
TIM21/22 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
21.2.1
21.3
TIM21/22 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
TIM21/22 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
21.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Prescaler description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451
21.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Upcounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453
Downcounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .457
Center-aligned mode (up/down counting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .460
21.3.3
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Internal clock source (CK_INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .464
External clock source mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .466
21.3.4
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
21.3.5
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
21.3.6
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
21.3.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
21.3.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
21.3.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
PWM center-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474
Hints on using center-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .475
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21.3.10 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 476
21.3.11 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
Particular case: OCx fast enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478
21.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
21.3.13 TIM21/22 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 481
Slave mode: Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .481
Slave mode: Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .482
Slave mode: Trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .482
21.3.14 Timer synchronization (TIM21/22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
21.3.15 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
21.4
TIM21/22 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
21.4.1
TIM21/22 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . 485
21.4.2
TIM21/22 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . 487
21.4.3
TIM21/22 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . 488
21.4.4
TIM21/22 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 491
21.4.5
TIM21/22 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 491
21.4.6
TIM21/22 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . 493
21.4.7
TIM21/22 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . 494
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494
Input capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .496
21.4.8
TIM21/22 capture/compare enable register (TIMx_CCER) . . . . . . . . . 497
21.4.9
TIM21/22 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
21.4.10 TIM21/22 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
21.4.11 TIM21/22 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . 498
21.4.12 TIM21/22 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . 499
21.4.13 TIM21/22 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . 499
21.4.14 TIM21 option register (TIM21_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
21.4.15 TIM22 option register (TIM22_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
21.4.16 TIM21/22 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
22
Basic timers (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
22.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
22.2
TIM6 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
22.3
TIM6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
22.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Prescaler description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .505
22.3.2
Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
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22.4
23
22.3.3
Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
22.3.4
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
TIM6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .511
22.4.1
TIM6 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 511
22.4.2
TIM6 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 513
22.4.3
TIM6 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . 513
22.4.4
TIM6 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
22.4.5
TIM6 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 514
22.4.6
TIM6 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
22.4.7
TIM6 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
22.4.8
TIM6 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 515
22.4.9
TIM6 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Low power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
23.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
23.2
LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
23.3
LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
23.4
LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
23.4.1
LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
23.4.2
LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
23.4.3
Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
23.4.4
Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
23.4.5
Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
23.4.6
Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
23.4.7
Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
23.4.8
Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
23.4.9
Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
23.4.10 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
23.4.11 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
23.4.12 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
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23.5
LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
23.6
LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
23.6.1
LPTIM Interrupt and Status Register (LPTIMx_ISR) . . . . . . . . . . . . . . 526
23.6.2
LPTIM Interrupt Clear Register (LPTIMx_ICR) . . . . . . . . . . . . . . . . . . 527
23.6.3
LPTIM Interrupt Enable Register (LPTIMx_IER) . . . . . . . . . . . . . . . . . 528
23.6.4
LPTIM Configuration Register (LPTIMx_CFGR) . . . . . . . . . . . . . . . . . 529
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23.6.5
LPTIM Control Register (LPTIMx_CR) . . . . . . . . . . . . . . . . . . . . . . . . 532
23.6.6
LPTIM Compare Register (LPTIMx_CMP) . . . . . . . . . . . . . . . . . . . . . 533
23.6.7
LPTIM Autoreload Register (LPTIMx_ARR) . . . . . . . . . . . . . . . . . . . . 533
23.6.8
LPTIM Counter Register (LPTIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . 534
23.6.9
LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
24.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
24.2
IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
24.3
IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
24.3.1
IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
24.3.2
Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Configuring the IWDG when the window option is enabled . . . . . . . . . . . . . . . .537
Configuring the IWDG when the window option is disabled . . . . . . . . . . . . . . . .537
24.4
25
24.3.3
Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
24.3.4
Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
24.3.5
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
24.4.1
Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
24.4.2
Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
24.4.3
Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
24.4.4
Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
24.4.5
Window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
24.4.6
IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . 544
25.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
25.2
WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
25.3
WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
25.4
25.3.1
Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
25.3.2
Controlling the downcounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
25.3.3
Advanced watchdog interrupt feature . . . . . . . . . . . . . . . . . . . . . . . . . 545
25.3.4
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . 546
25.3.5
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
25.4.1
Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
25.4.2
Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 548
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25.4.3
Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
25.4.4
WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
26.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
26.2
RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
26.3
RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
26.3.1
RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
26.3.2
GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
26.3.3
Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
26.3.4
Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
26.3.5
Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
26.3.6
Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
26.3.7
RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
RTC register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
RTC register write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
Calendar initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
Daylight saving time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .558
Programming the alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .558
Programming the wakeup timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .558
26.3.8
Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
When BYPSHAD control bit is cleared in the RTC_CR register. . . . . . . . . . . . .558
When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .559
26.3.9
Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
26.3.10 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
26.3.11 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
26.3.12 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
Calibration when PREDIV_A<3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .562
Verifying the RTC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .562
Re-calibration on-the-fly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .563
26.3.13 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
26.3.14 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
RTC backup registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564
Tamper detection initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564
Trigger output generation on tamper event . . . . . . . . . . . . . . . . . . . . . . . . . . . .564
Timestamp on tamper event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .565
Edge detection on tamper inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .565
Level detection with filtering on RTC_TAMPx inputs . . . . . . . . . . . . . . . . . . . . .565
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26.3.15 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
26.3.16 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Alarm alternate function output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .566
26.4
RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
26.5
RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
26.6
RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
26.6.1
RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
26.6.2
RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
26.6.3
RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
26.6.4
RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . . 573
26.6.5
RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 576
26.6.6
RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . . 577
26.6.7
RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 578
26.6.8
RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . . 579
26.6.9
RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 580
26.6.10 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 581
26.6.11 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 582
26.6.12 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . . 583
26.6.13 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 584
26.6.14 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . 585
26.6.15 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 586
26.6.16 RTC tamper configuration register (RTC_TAMPCR) . . . . . . . . . . . . . . 587
26.6.17 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 590
26.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . . 591
26.6.19 RTC option register (RTC_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
26.6.20 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . . 593
26.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
27
Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 596
27.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
27.2
I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
27.3
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
27.4
I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
27.4.1
I2C1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
27.4.2
I2C2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
27.4.3
I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
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27.4.4
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600
27.4.5
I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Enabling and disabling the peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .601
Noise filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .601
I2C timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .602
27.4.6
Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
27.4.7
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606
Hardware transfer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .607
27.4.8
I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
I2C slave initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608
Slave clock stretching (NOSTRETCH = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .609
Slave without clock stretching (NOSTRETCH = 1). . . . . . . . . . . . . . . . . . . . . . .609
Slave Byte Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .609
Slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .610
Slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .615
27.4.9
I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
I2C master initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .617
Master communication initialization (address phase) . . . . . . . . . . . . . . . . . . . . .619
Initialization of a master receiver addressing a 10-bit address slave . . . . . . . . .620
Master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .621
Master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .625
27.4.10 I2Cx_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . 629
27.4.11 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .630
SMBUS is based on I2C specification rev 2.1. . . . . . . . . . . . . . . . . . . . . . . . . . .630
Bus protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .630
Address resolution protocol (ARP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .630
Received Command and Data acknowledge control . . . . . . . . . . . . . . . . . . . . .631
Host Notify protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .631
SMBus alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .631
Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .631
Timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .631
Bus idle detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .632
27.4.12 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Received Command and Data Acknowledge control (Slave mode) . . . . . . . . . .633
Specific address (Slave mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .633
Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .633
Timeout detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .634
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Bus Idle detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .634
27.4.13 SMBus: I2Cx_TIMEOUTR register configuration examples . . . . . . . . 634
27.4.14 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
SMBus Slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .635
SMBus Slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637
SMBus Master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639
SMBus Master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .641
27.4.15 Wakeup from Stop mode on address match . . . . . . . . . . . . . . . . . . . . 642
27.4.16 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Bus error (BERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .643
Arbitration lost (ARLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .643
Overrun/underrun error (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .644
Packet Error Checking Error (PECERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .644
Timeout Error (TIMEOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .644
Alert (ALERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .644
27.4.17 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .645
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .645
27.4.18 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
27.5
I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
27.6
I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
27.7
I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
27.7.1
Control register 1 (I2Cx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
27.7.2
Control register 2 (I2Cx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
27.7.3
Own address 1 register (I2Cx_OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . 654
27.7.4
Own address 2 register (I2Cx_OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . 655
27.7.5
Timing register (I2Cx_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
27.7.6
Timeout register (I2Cx_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 657
27.7.7
Interrupt and Status register (I2Cx_ISR) . . . . . . . . . . . . . . . . . . . . . . . 658
27.7.8
Interrupt clear register (I2Cx_ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
27.7.9
PEC register (I2Cx_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
27.7.10 Receive data register (I2Cx_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 662
27.7.11 Transmit data register (I2Cx_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 662
27.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
28
Universal synchronous asynchronous receiver
transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
28.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
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28.2
USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
28.3
USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
28.4
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
28.5
USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
28.5.1
USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
28.5.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Character transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .672
Single byte communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .673
Break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .674
Idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .674
28.5.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
Start bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .674
Character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .676
Break character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .676
Idle character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .676
Overrun error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .677
Selecting the clock source and the proper oversampling method . . . . . . . . . . .677
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .680
Configurable stop bits during reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .680
28.5.4
Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
How to derive USARTDIV from USARTx_BRR register values . . . . . . . . . . . . .681
28.5.5
Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . . 683
28.5.6
Auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
28.5.7
Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Idle line detection (WAKE=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .685
4-bit/7-bit address mark detection (WAKE=1) . . . . . . . . . . . . . . . . . . . . . . . . . .686
28.5.8
Modbus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Modbus/RTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .687
Modbus/ASCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .687
28.5.9
Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Even parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .688
Odd parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .688
Parity checking in reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .688
Parity generation in transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .688
28.5.10 LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 688
LIN transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .689
LIN reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .689
28.5.11 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
28.5.12 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 693
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28.5.13 Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Block mode (T=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .696
Direct and inverse convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .697
28.5.14 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
IrDA low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .699
28.5.15 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 700
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .700
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .702
Error flagging and interrupt generation in multibuffer communication . . . . . . . .702
28.5.16 RS232 Hardware flow control and RS485 Driver Enable . . . . . . . . . . 703
RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .703
RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .703
RS485 Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .704
28.5.17 Wakeup from Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
Using Mute mode with Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .705
28.6
USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
28.7
USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
28.7.1
Control register 1 (USARTx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
28.7.2
Control register 2 (USARTx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
28.7.3
Control register 3 (USARTx_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
28.7.4
Baud rate register (USARTx_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
28.7.5
Guard time and prescaler register (USARTx_GTPR) . . . . . . . . . . . . . 718
28.7.6
Receiver timeout register (USARTx_RTOR) . . . . . . . . . . . . . . . . . . . . 719
28.7.7
Request register (USARTx_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
28.7.8
Interrupt & status register (USARTx_ISR) . . . . . . . . . . . . . . . . . . . . . . 721
28.7.9
Interrupt flag clear register (USARTx_ICR) . . . . . . . . . . . . . . . . . . . . . 726
28.7.10 Receive data register (USARTx_RDR) . . . . . . . . . . . . . . . . . . . . . . . . 727
28.7.11 Transmit data register (USARTx_TDR) . . . . . . . . . . . . . . . . . . . . . . . . 727
28.7.12 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
29
Low-power universal asynchronous receiver transmitter (LPUART) 730
29.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
29.2
LPUART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
29.3
LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
29.4
LPUART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
29.4.1
LPUART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
29.4.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
Character transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .736
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Single byte communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .737
Break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .738
Idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .738
29.4.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Start bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .738
Character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .739
Break character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .739
Idle character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .739
Overrun error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .739
Selecting the clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .740
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .740
Configurable stop bits during reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .741
29.4.4
Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
29.4.5
Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Idle line detection (WAKE=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .742
4-bit/7-bit address mark detection (WAKE=1) . . . . . . . . . . . . . . . . . . . . . . . . . .743
29.4.6
Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Even parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .744
Odd parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .744
Parity checking in reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .745
Parity generation in transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .745
29.4.7
Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 745
29.4.8
Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 745
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .745
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .747
Error flagging and interrupt generation in multibuffer communication . . . . . . . .747
29.4.9
RS232 Hardware flow control and RS485 Driver Enable . . . . . . . . . . 748
RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .748
RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .748
RS485 Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .749
29.4.10 Wakeup from Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
Using Mute mode with Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .750
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29.5
LPUART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
29.6
LPUART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
29.6.1
Control register 1 (LPUARTx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
29.6.2
Control register 2 (LPUARTx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
29.6.3
Control register 3 (LPUARTx_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
29.6.4
Baud rate register (LPUARTx_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . 759
29.6.5
Request register (LPUARTx_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
29.6.6
Interrupt & status register (LPUARTx_ISR) . . . . . . . . . . . . . . . . . . . . . 760
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29.6.7
Interrupt flag clear register (LPUARTx_ICR) . . . . . . . . . . . . . . . . . . . . 763
29.6.8
Receive data register (LPUARTx_RDR) . . . . . . . . . . . . . . . . . . . . . . . 764
29.6.9
Transmit data register (LPUARTx_TDR) . . . . . . . . . . . . . . . . . . . . . . . 764
29.6.10 LPUART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
30
Serial peripheral interface/ inter-IC sound (SPI/I2S) . . . . . . . . . . . . . 767
30.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
30.1.1
SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
30.1.2
SPI extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
30.1.3
I2S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
30.2
SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
30.3
SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
30.3.1
30.3.2
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
Communications between one master and one slave . . . . . . . . . . . . . 771
Full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .771
Half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .771
Simplex communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .772
30.3.3
Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . . 773
30.3.4
Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . . 774
30.3.5
Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Clock phase and polarity controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .776
Data frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .777
30.3.6
SPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
30.3.7
Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
30.3.8
Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 779
Rx and Tx buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .779
Tx buffer handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .779
Rx buffer handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .779
Sequence handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .779
30.3.9
Procedure for disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
30.3.10 Communication using DMA (direct memory addressing) . . . . . . . . . . 782
30.3.11 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
Tx buffer empty flag (TXE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .784
Rx buffer not empty (RXNE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .784
Busy flag (BSY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .784
30.3.12 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
Overrun flag (OVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .784
Mode fault (MODF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .785
CRC error (CRCERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .785
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TI mode frame format error (FRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .785
30.4
SPI special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
30.4.1
TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
TI protocol in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .785
30.4.2
CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
CRC principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .787
CRC transfer managed by CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .787
CRC transfer managed by DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .787
Resetting the SPIx_TXCRC and SPIx_RXCRC values . . . . . . . . . . . . . . . . . . .787
30.5
SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
30.6
I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
30.6.1
I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
30.6.2
Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
I2S Philips standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .791
MSB justified standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .793
LSB justified standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .794
PCM standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .795
30.6.3
Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
30.6.4
I2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .799
Transmission sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .799
Reception sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .800
30.6.5
I2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Transmission sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .801
Reception sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .802
30.6.6
I2S status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
Busy flag (BSY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .802
Tx buffer empty flag (TXE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .803
RX buffer not empty (RXNE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .803
Channel Side flag (CHSIDE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .803
30.6.7
I2S error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Underrun flag (UDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .803
Overrun flag (OVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .803
Frame error flag (FRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .804
30.7
30/869
30.6.8
I2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
30.6.9
DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
30.7.1
SPI control register 1 (SPI_CR1) (not used in I2S mode) . . . . . . . . . . 805
30.7.2
SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
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30.7.3
SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
30.7.4
SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
30.7.5
SPI CRC polynomial register (SPI_CRCPR) (not used in I2S
mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
30.7.6
SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode) . . . . . . 811
30.7.7
SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode) . . . . . . 811
30.7.8
SPI_I2S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 812
30.7.9
SPI_I2S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 813
30.7.10 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
31
Universal serial bus full-speed device interface (USB) . . . . . . . . . . . 815
31.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
31.2
USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
31.3
USB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
31.4
USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
31.4.1
31.5
Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
31.5.1
Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
31.5.2
System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
USB reset (RESET interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .819
Structure and usage of packet buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .819
Endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .821
IN packets (data transmission) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .821
OUT and SETUP packets (data reception) . . . . . . . . . . . . . . . . . . . . . . . . . . . .822
Control transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .823
31.6
31.5.3
Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
31.5.4
Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
31.5.5
Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
USB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
31.6.1
Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
USB control register (USB_CNTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .829
USB interrupt status register (USB_ISTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .831
USB frame number register (USB_FNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .834
USB device address (USB_DADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .835
Buffer table address (USB_BTABLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .835
LPM control and status register (USB_LPMCSR) . . . . . . . . . . . . . . . . . . . . . . .836
Battery charging detector (USB_BCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .836
31.6.2
Endpoint-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
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USB endpoint n register (USB_EPnR), n=[0..7] . . . . . . . . . . . . . . . . . . . . . . . . .838
31.6.3
Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
Transmission buffer address n (USB_ADDRn_TX) . . . . . . . . . . . . . . . . . . . . . .842
Transmission byte count n (USB_COUNTn_TX) . . . . . . . . . . . . . . . . . . . . . . . .843
Reception buffer address n (USB_ADDRn_RX) . . . . . . . . . . . . . . . . . . . . . . . .843
Reception byte count n (USB_COUNTn_RX) . . . . . . . . . . . . . . . . . . . . . . . . . .844
31.6.4
32
USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
32.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
32.2
Reference ARM documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
32.3
Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
32.4
32.3.1
SWD port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
32.3.2
SW-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
32.3.3
Internal pull-up & pull-down on SWD pins . . . . . . . . . . . . . . . . . . . . . . 849
ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
32.4.1
MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
DBG_IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .850
32.5
SWD port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
32.5.1
SWD protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
32.5.2
SWD protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
32.5.3
SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . . 852
32.5.4
DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
32.5.5
SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
32.5.6
SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
32.6
Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
32.7
BPU (Break Point Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
32.7.1
32.8
32.9
32/869
BPU functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
DWT (Data Watchpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
32.8.1
DWT functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
32.8.2
DWT Program Counter Sample Register . . . . . . . . . . . . . . . . . . . . . . 855
MCU debug component (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
32.9.1
Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 856
32.9.2
Debug support for timers, watchdog and I2C . . . . . . . . . . . . . . . . . . . . 856
32.9.3
Debug MCU configuration register (DBG_CR) . . . . . . . . . . . . . . . . . . 857
32.9.4
Debug MCU APB1 freeze register (DBG_APB1_FZ) . . . . . . . . . . . . . 858
32.9.5
Debug MCU APB2 freeze register (DBG_APB2_FZ) . . . . . . . . . . . . . 860
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32.10 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
33
Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
33.1
Memory size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
33.1.1
33.2
34
Flash size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
Unique device ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
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List of tables
RM0376
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
34/869
STM32L0x2 memory density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
STM32L0x2 peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
NVM organization (STM32L0x2 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Link between master clock power range and frequencies . . . . . . . . . . . . . . . . . . . . . . . . . 56
Delays to memory access and number of wait states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Internal buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Configurations for buffers and speculative reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Dhrystone performances in all memory interface configurations . . . . . . . . . . . . . . . . . . . . 62
NVM write/erase timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
NVM write/erase duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Protection level and content of RDP Option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Link between protection bits of FLASH_WRPROT register
and protected address in Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Memory access vs mode, protection and Flash program memory sectors. . . . . . . . . . . . . 80
Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Flash interface - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Segment accesses according to the Firewall state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Segment granularity and area ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Firewall register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Performance versus VCORE ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Summary of low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Sleep-now . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Sleep-now . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
PWR - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
System clock source frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Effect of low-power modes on CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
CRS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Programmable data width & endian behavior (when bits PINC = MINC = 1) . . . . . . . . . . 242
DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Summary of the DMA requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
EXTI lines connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Extended interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . 267
ADC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
DocID025941 Rev 1
RM0376
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
List of tables
ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Latency between trigger and start of conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
tSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Analog watchdog comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Maximum output results vs N and M. Grayed values indicates truncation . . . . . . . . . . . . 293
ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
DAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
DAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
COMP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Acquisition sequence summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Spread spectrum deviation versus AHB clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . 341
I/O state depending on its mode and IODEF bit value . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Capacitive sensing GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Effect of low-power modes on TSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
TSC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Processing time (in clock cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
AES interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
TIM2 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
TIM2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
TIM21/22 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
TIM6 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
STM32L0x2 LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
LPTIM external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
STM32L0x2 I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
I2C-SMBUS specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
I2C Configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
I2C-SMBUS specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Examples of timings settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
DocID025941 Rev 1
35/869
36
List of tables
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
36/869
RM0376
Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
SMBUS with PEC configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . . 635
Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
STM32L0x2 USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Error calculation for programmed baud rates at fCK = 32 MHz in both cases of
oversampling by 16 or by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . . 683
Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . . . . . . . . . . 683
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Error calculation for programmed baudrates at fck = 32,768 KHz . . . . . . . . . . . . . . . . . . 741
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
LPUART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
LPUART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
STM32L0x2 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
Audio-frequency precision using standard 8 MHz HSE . . . . . . . . . . . . . . . . . . . . . . . . . . 798
I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
STM32L0x2 USB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
Bulk double-buffering memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Endpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
Endpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
SW debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 854
Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
DocID025941 Rev 1
RM0376
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Structure of one internal buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Timing to fetch and execute instructions with prefetch disabled. . . . . . . . . . . . . . . . . . . . . 60
Timing to fetch and execute instructions with prefetch enabled . . . . . . . . . . . . . . . . . . . . . 61
RDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
STM32L0x2 firewall connection schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Firewall functional states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Performance versus VDD and VCORE range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Using TIM21 channel 1 input capture to measure
frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
CRS counter behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Extended interrupts and events controller (EXTI) block diagram . . . . . . . . . . . . . . . . . . . 260
Extended interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Calibration factor forcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Enabling/disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
ADC conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Stopping an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 286
Data alignment and resolution (oversampling disabled: OVSE = 0). . . . . . . . . . . . . . . . . 287
Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Wait mode conversion (continuous mode, software trigger). . . . . . . . . . . . . . . . . . . . . . . 290
Behavior with WAIT=0, AUTOFF=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
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42
List of figures
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
Figure 98.
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RM0376
Behavior with WAIT=1, AUTOFF=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Numerical example with 5-bits shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Triggered oversampling mode (TOVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 296
DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 319
DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 321
DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 322
Comparator 1 and 2 block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Surface charge transfer analog I/O group structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Sampling capacitor voltage variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Spread spectrum variation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
ECB encryption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
ECB decryption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
CBC mode encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
CBC mode decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
CTR mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
CTR mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
32-bit counter + nonce organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
128-bit block construction according to the data type. . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
128-bit block construction according to the data type (continued) . . . . . . . . . . . . . . . . . . 367
Mode 1: encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Mode 2: key derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Mode 3: decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Mode 4: key derivation and decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
DMA requests and data transfers during Input phase (AES_IN) . . . . . . . . . . . . . . . . . . . 370
DMA requests during Output phase (AES_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 388
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 389
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 392
Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 392
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Counter timing diagram, Update event when repetition counter
is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
DocID025941 Rev 1
RM0376
Figure 99.
Figure 100.
Figure 101.
Figure 102.
Figure 103.
Figure 104.
Figure 105.
Figure 106.
Figure 107.
Figure 108.
Figure 109.
Figure 110.
Figure 111.
Figure 112.
Figure 113.
Figure 114.
Figure 115.
Figure 116.
Figure 117.
Figure 118.
Figure 119.
Figure 120.
Figure 121.
Figure 122.
Figure 123.
Figure 124.
Figure 125.
Figure 126.
Figure 127.
Figure 128.
Figure 129.
Figure 130.
Figure 131.
Figure 132.
Figure 133.
Figure 134.
Figure 135.
Figure 136.
Figure 137.
Figure 138.
Figure 139.
Figure 140.
Figure 141.
Figure 142.
Figure 143.
Figure 144.
Figure 145.
Figure 146.
Figure 147.
Figure 148.
List of figures
Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 397
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 398
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 399
Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 399
Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 400
TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 404
Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 405
PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 416
Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 416
Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Gating timer y with OC1REF of timer x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Gating timer y with Enable of timer x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Triggering timer y with update of timer x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Triggering timer y with Enable of timer x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Triggering timer x and y with timer x TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
General-purpose timer block diagram (TIM21/22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 452
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 453
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 461
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 462
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 463
DocID025941 Rev 1
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List of figures
Figure 149.
Figure 150.
Figure 151.
Figure 152.
Figure 153.
Figure 154.
Figure 155.
Figure 156.
Figure 157.
Figure 158.
Figure 159.
Figure 160.
Figure 161.
Figure 162.
Figure 163.
Figure 164.
Figure 165.
Figure 166.
Figure 167.
Figure 168.
Figure 169.
Figure 170.
Figure 171.
Figure 172.
Figure 173.
Figure 174.
Figure 175.
Figure 176.
Figure 177.
Figure 178.
Figure 179.
Figure 180.
Figure 181.
Figure 182.
Figure 183.
Figure 184.
Figure 185.
Figure 186.
Figure 187.
Figure 188.
Figure 189.
Figure 190.
Figure 191.
Figure 192.
Figure 193.
Figure 194.
Figure 195.
Figure 196.
Figure 197.
Figure 198.
40/869
RM0376
Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 463
Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 464
TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 468
Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Output stage of capture/compare channel (channel 1 and 2). . . . . . . . . . . . . . . . . . . . . . 469
PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 480
Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 480
Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Basic timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 506
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 506
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 511
Low Power Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
I2C1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
I2C2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0. . . . . . . . . . . . . 612
Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1. . . . . . . . . . . . . 613
Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . . . 615
DocID025941 Rev 1
RM0376
Figure 199.
Figure 200.
Figure 201.
Figure 202.
Figure 203.
Figure 204.
Figure 205.
Figure 206.
Figure 207.
Figure 208.
Figure 209.
Figure 210.
Figure 211.
Figure 212.
Figure 213.
Figure 214.
Figure 215.
Figure 216.
Figure 217.
Figure 218.
Figure 219.
Figure 220.
Figure 221.
Figure 222.
Figure 223.
Figure 224.
Figure 225.
Figure 226.
Figure 227.
Figure 228.
Figure 229.
Figure 230.
Figure 231.
Figure 232.
Figure 233.
Figure 234.
Figure 235.
Figure 236.
Figure 237.
Figure 238.
Figure 239.
Figure 240.
Figure 241.
Figure 242.
Figure 243.
Figure 244.
Figure 245.
Figure 246.
Figure 247.
Figure 248.
Figure 249.
Figure 250.
List of figures
Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . . . 616
Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Transfer sequence flowchart for I2C master transmitter for N<=255 bytes . . . . . . . . . . . 622
Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . . 623
Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Transfer sequence flowchart for I2C master receiver for N<=255 bytes . . . . . . . . . . . . . 626
Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . . . . . . . . . . . 627
Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Timeout intervals for tLOW:SEXT, tLOW:MEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . 636
Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . . 636
Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . . 638
Bus transfer diagrams for SMBus slave receiver (SBC=1) . . . . . . . . . . . . . . . . . . . . . . . 639
Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 690
Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 691
USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
USART data clock timing diagram (M bits = 00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
USART data clock timing diagram (M bits = 01). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
IrDA data modulation (3/16) -Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
LPUART Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
DocID025941 Rev 1
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42
List of figures
Figure 251.
Figure 252.
Figure 253.
Figure 254.
Figure 255.
Figure 256.
Figure 257.
Figure 258.
Figure 259.
Figure 260.
Figure 261.
Figure 262.
Figure 263.
Figure 264.
Figure 265.
Figure 266.
Figure 267.
Figure 268.
Figure 269.
Figure 270.
Figure 271.
Figure 272.
Figure 273.
Figure 274.
Figure 275.
Figure 276.
Figure 277.
Figure 278.
Figure 279.
Figure 280.
Figure 281.
Figure 282.
Figure 283.
Figure 284.
Figure 285.
Figure 286.
Figure 287.
Figure 288.
Figure 289.
Figure 290.
42/869
RM0376
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
Hardware flow control between 2 LPUARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
LPUART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0 and
RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0,
RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . . . . . . . . . . . . . . 791
I2S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . 791
Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
I2S Philips standard (16-bit extended to 32-bit packet frame
with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 792
MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 793
MSB justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 793
LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 794
LSB justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 795
Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 795
PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 796
Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . . 820
Block diagram of STM32L0x2 MCU and Cortex®-M0+-level debug support . . . . . . . . . . 847
DocID025941 Rev 1
RM0376
Documentation conventions
1
Documentation conventions
1.1
List of abbreviations for registers
The following abbreviations are used in register descriptions:
1.2
read/write (rw)
Software can read and write to these bits.
read-only (r)
Software can only read these bits.
write-only (w)
Software can only write to this bit. Reading the bit returns the reset
value.
read/clear (rc_w1)
Software can read as well as clear this bit by writing 1. Writing ‘0’ has
no effect on the bit value.
read/clear (rc_w0)
Software can read as well as clear this bit by writing 0. Writing ‘1’ has
no effect on the bit value.
read/clear by read
(rc_r)
Software can read this bit. Reading this bit automatically clears it to
‘0’. Writing ‘0’ has no effect on the bit value.
read/set (rs)
Software can read as well as set this bit. Writing ‘0’ has no effect on
the bit value.
Reserved (Res.)
Reserved bit, must be kept at reset value.
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
•
Sector: 32 pages write protection granularity in the Code area
•
Page: 32 words for Code and System Memory areas, 1 word for Data, Factory Option
and User Option areas
•
Word: data of 32-bit length.
•
Half-word: data of 16-bit length.
•
Byte: data of 8-bit length.
•
IAP (in-application programming): IAP is the ability to re-program the Flash memory
of a microcontroller while the user program is running.
•
ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
•
Option bytes: product configuration bits stored in the Flash memory.
•
OBL: option byte loader.
•
AHB: advanced high-performance bus.
•
NVM: non-volatile memory
•
ECC: error code correction.
•
DMA: direct memory access.
•
MIF: NVM interface.
•
PCROP: proprietary code read-out protection.
DocID025941 Rev 1
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44
Documentation conventions
1.3
RM0376
Peripheral availability
For peripheral availability and number across all sales types, please refer to the particular
device datasheet.
1.4
Product category definition
Table 1 gives an overview of memory density versus product line.
Table 1. STM32L0x2 memory density
44/869
Memory density
Cat. 1
Cat. 2
Cat. 3
16 Kbytes
-
-
-
32 Kbytes
-
STM32L052x
STM32L062x (AES)
-
64 Kbytes
-
STM32L052x
STM32L062x (AES)
-
128 Kbytes
-
-
-
192 Kbytes
-
-
-
DocID025941 Rev 1
RM0376
System and memory overview
2
System and memory overview
2.1
System architecture
The main system consists of:
•
•
Two masters:
–
Cortex®-M0+ core (AHB-lite bus)
–
GP-DMA (general-purpose DMA)
Three slaves:
–
Internal 8 Kbyte SRAM
–
Internal 64 Kbyte Flash memory
–
AHB to APB, which connects all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 1:
Figure 1. System architecture
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System and memory overview
2.1.1
RM0376
S0: Cortex-bus
This bus connects the DCode/ICode bus of the Cortex®-M0+ core to the BusMatrix. This
bus is used by the core to fetch instructions, get data and access the AHB/APB resources.
2.1.2
S1: DMA-bus
This bus connects the AHB master interface of the DMA to the BusMatrix which
manages the access of the different masters to Flash memory and data EEPROM,
the SRAM and the AHB/APB peripherals.
2.1.3
BusMatrix
The BusMatrix manages the access arbitration between masters. The arbitration uses a
Round Robin algorithm. The BusMatrix is composed of two masters (CPU, DMA) and three
slaves (NVM interface, SRAM, AHB2APB1/2 bridges).
AHB/APB bridges
The AHB/APB bridge provide full synchronous connections between the AHB and the 2
APB buses. APB1 and APB2 operate at a maximum frequency of 32 MHz.
Refer to Section 2.2.2: Memory map and register boundary addresses on page 48 for the
address mapping of the peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and MIF).
Before using a peripheral you have to enable its clock in the RCC_AHBENR,
RCC_APB2ENR, RCC_APB1ENR or RCC_IOPENR register.
Note:
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When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
DocID025941 Rev 1
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2.2
Memory organization
2.2.1
Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
The addressable memory space is divided into 8 main blocks, each of 512 Mbytes.
Figure 2. Memory map
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RM0376
All the memory areas that are not allocated to on-chip memories and peripherals are
considered “Reserved”. For the detailed mapping of available memory and register areas,
please refer to the Memory map and register boundary addresses chapter and peripheral
chapters.
2.2.2
Memory map and register boundary addresses
See the datasheet corresponding to your device for a comprehensive diagram of the
memory map.
The following table gives the boundary addresses of the peripherals available in the
devices.
Table 2. STM32L0x2 peripheral register boundary addresses
Bus
IOPORT
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Boundary address
Size (bytes)
Peripheral
Peripheral register map
0X5000 1C00 - 0X5000 1FFF
1K
GPIOH
Section 9.4.12: GPIO register
map
0X5000 1000 - 0X5000 1BFF
3K
Reserved
0X5000 0C00 - 0X5000 0FFF
1K
GPIOD
Section 9.4.12: GPIO register
map
0X5000 0800 - 0X5000 0BFF
1K
GPIO C
Section 9.4.12: GPIO register
mapSection 9.4.12: GPIO
register map
0X5000 0400 - 0X5000 07FF
1K
GPIOB
Section 9.4.12: GPIO register
map
0X5000 0000 - 0X5000 03FF
1K
GPIOA
Section 9.4.12: GPIO register
map
DocID025941 Rev 1
RM0376
Table 2. STM32L0x2 peripheral register boundary addresses (continued)
Bus
AHB
Boundary address
Size (bytes)
Peripheral
0X4002 6400 - 0X4002 67FF
49K
Reserved
0X4002 6000 - 0X4002 63FF
1K
AES (Cat. 2
with AES only)
0X4002 5400 - 0X4002 5FFF
3K
Reserved
0X4002 5000 - 0X4002 53FF
1K
RNG
0X4002 4400 - 0X4002 4FFF
3K
Reserved
0X4002 4000 - 0X4002 43FF
1K
TSC
0X4002 3400 - 0X4002 43FF
3K
Reserved
0X4002 3000 - 0X4002 33FF
1K
CRC
0X4002 2400 - 0X4002 2FFF
3K
Reserved
0X4002 2000 - 0X4002 23FF
1K
FLASH
0X4002 1400 - 0X4002 1FFF
3K
Reserved
0X4002 1000 - 0X4002 13FF
1K
RCC
0X4002 0400 - 0X4002 0FFF
3K
Reserved
0X4002 0000 - 0X4002 03FF
1K
DMA1
DocID025941 Rev 1
Peripheral register map
Section 18.12.13: AES register
map
Section 19.4.4: RNG register
map
Section 17.6.11: TSC register
map
Section 4.4.6: CRC register map
Section 3.7.10: Flash register
map
Section 7.3.22: RCC register
map
Section 11.4.8: DMA register
map
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RM0376
Table 2. STM32L0x2 peripheral register boundary addresses (continued)
Bus
APB2
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Boundary address
Size (bytes)
Peripheral
0X4001 5C00 - 0X4001 FFFF
42K
Reserved
0X4001 5800 - 0X4001 5BFF
1K
DBG
0X4001 3C00 - 0X4001 57FF
7K
Reserved
0X4001 3800 - 0X4001 3BFF
1K
USART1
0X4001 3400 - 0X4001 37FF
1K
Reserved
0X4001 3000 - 0X4001 33FF
1K
SPI1
0X4001 2800 - 0X4001 2FFF
2K
Reserved
0X4001 2400 - 0X4001 27FF
1K
ADC1
0X4001 2000 - 0X4001 23FF
1K
Reserved
0X4001 1C00 - 0X4001 1FFF
1K
Firewall
0X4001 1800 - 0X4001 1BFF
1K
Reserved
0X4001 1400 - 0X4001 17FF
1K
TIM22
0X4001 0C000 - 0X4001 13FF
2K
Reserved
0X4001 0800 - 0X4001 0BFF
1K
TIM21
Section 21.4.16: TIM21/22
register map
0X4001 0400 - 0X4001 07FF
1K
EXTI
Section 13.5.7: EXTI register
map
0X4001 0000 - 0X4001 03FF
1K
SYSCFG
Section 10.2.8: SYSCFG
register map
DocID025941 Rev 1
Peripheral register map
Section 32.10: DBG register
map
Section 28.7.12: USART
register map
Section 30.7.10: SPI register
map
Section 14.12.12: ADC register
map
Section 5.4.8: Firewall register
map
Section 21.4.16: TIM21/22
register map
RM0376
Table 2. STM32L0x2 peripheral register boundary addresses (continued)
Bus
APB1
Boundary address
Size (bytes)
Peripheral
0X4000 8000 - 0X4000 FFFF
32 K
Reserved
0X4000 7C00 - 0X4000 7FFF
1K
LPTIM1
0X4000 7800 - 0X4000 7BFF
1K
Reserved
0X4000 7400 - 0X4000 77FF
1K
DAC1
Section 15.7.8: DAC register
map
0X4000 7000 - 0X4000 73FF
1K
PWR
Section 6.4.3: PWR register
map
0X4000 6C00 - 0X4000 6FFF
1K
CRS
Section 8.6.5: CRS register map
0X4000 68000 - 0X4000 6BFF
1K
Reserved
0X4000 6000 - 0X4000 67FF
2K
USB (SRAM
512x16bit)
0X4000 5C00 - 0X4000 5FFF
1K
USB FS
Section 31.6.4: USB register
map
0X4000 5800 - 0X4000 5BFF
1K
I2C2
Section 27.7.12: I2C register
map
0X4000 5400 - 0X4000 57FF
1K
I2C1
Section 27.7.12: I2C register
map
0X4000 4C000 - 0X4000 53FF
2K
Reserved
0X4000 4800 - 0X4000 4BFF
1K
LPUART1
Section 29.6.10: LPUART
register map
0X4000 4400 - 0X4000 47FF
1K
USART2
Section 28.7.12: USART
register map
0X4000 3C000 - 0X4000 43FF
2K
Reserved
0X4000 3800 - 0X4000 3BFF
1K
SPI2
0X4000 3400 - 0X4000 37FF
1K
Reserved
0X4000 3000 - 0X4000 33FF
1K
IWDG
Section 24.4.6: IWDG register
map
0X4000 2C00 - 0X4000 2FFF
1K
WWDG
Section 25.4.4: WWDG register
map
0X4000 2800 - 0X4000 2BFF
1K
RTC +
BKP_REG
Section 26.6.21: RTC register
map
0X4000 1400 - 0X4000 27FF
4K
Reserved
0X4000 1000 - 0X4000 13FF
1K
TIMER6
0X4000 0400 - 0X4000 0FFF
3K
Reserved
0X4000 0000 - 0X4000 03FF
1K
TIMER2
DocID025941 Rev 1
Peripheral register map
Section 23.6.9: LPTIM register
map
Section 30.7.10: SPI register
map
Section 22.4.9: TIM6 register
map
Section 20.4.20: TIMx register
map
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RM0376
Table 2. STM32L0x2 peripheral register boundary addresses (continued)
Bus
SRAM
Boundary address
Size (bytes)
Peripheral
0X2000 2000 - 0X3FFF FFFF
~524 M
Reserved
0X2000 0000 - 0X2000 1FFF
8K
SRAM
-
0X0800 0000 - 0X0800 FFFF
64 K
Flash program
memory
-
0x0808 0000 - 0x0808 07FF
2K
Data EEPROM
-
4 K + 32
Information
block (System
memory, user
and factory
option bytes)
-
NVM
0x1FF8 0000 - 0x1FF0 0FFF
2.3
Peripheral register map
Embedded SRAM
STM32L0x2 devices feature 8 Kbytes of static SRAM.This RAM can be accessed as bytes,
half-words (16 bits) or full words (32 bits). This memory can be addressed at maximum
system clock frequency without wait state and thus by both CPU and DMA.
The SRAM start address is 0x2000 0000.
The CPU can access the SRAM through the system bus or through the I-Code/D-Code bus
when boot in SRAM is selected or when physical remap is selected (see Section 10.2.1:
SYSCFG memory remap register (SYSCFG_CFGR1)register in the SYSCFG controller). To
get the best SRAM execution performance, physical remap must be selected (boot or
software selection).
2.4
Boot configuration
In the STM32L0x2, three different boot modes can be selected through the BOOT0 pin and
nBOOT1 bit in the User option byte, as shown in the following table.
Table 3. Boot modes
Boot mode selection
Boot mode
Aliasing
BOOT1(1)
BOOT0
x
0
Flash program
memory
Flash Program memory is selected as boot
space
0
1
System memory
System memory is selected as boot space
1
1
Embedded SRAM
Embedded SRAM is selected as boot space
1. The BOOT1 value is the opposite of the nBOOT1 Option Bit.
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The values on both BOOT0 pin and nBOOT1 bit are latched on the 4th rising edge of
SYSCLK after a reset. It is up to the user to set nBOOT1 and BOOT0 to select the required
boot mode.
The BOOT0 pin and nBOOT1 bit are also re-sampled when exiting from Standby mode.
Consequently they must be kept in the required Boot mode configuration in Standby mode.
After this startup delay has elapsed, the CPU fetches the top-of-stack value from address
0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.
Depending on the selected boot mode, Flash program memory, system memory or SRAM is
accessible as follows:
•
Boot from Flash program memory: the Flash program memory is aliased in the boot
memory space (0x0000 0000), but still accessible from its original memory space
(0x0800 0000). In other words, the Flash memory contents can be accessed starting
from address 0x0000 0000 or 0x0800 0000.
•
Boot from system memory: the system memory is aliased in the boot memory space
(0x0000 0000), but still accessible from its original memory space (0x1FF0 0000).
•
Boot from the embedded SRAM: the SRAM is aliased in the boot memory space
(0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).
Physical remap
Once the boot pin and bit are selected, the application software can modify the memory
accessible in the code area. This modification is performed by programming the
MEM_MODE bits in the SYSCFG memory remap register (SYSCFG_CFGR1).
Embedded boot loader
The embedded boot loader is located in the System memory, programmed by ST during
production. It is used to reprogram the Flash memory using one of the following serial
interfaces: USART1 (PA9, PA10), USART2 (PA2, PA3), SPI1 (PA4, PA5, PA6, PA7) or SPI2
(PB12, PB13, PB14, PB15).
For further details, please refer to AN2606.
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Flash program memory and data EEPROM (FLASH)
RM0376
3
Flash program memory and data EEPROM (FLASH)
3.1
Introduction
The non-volatile memory (NVM) is composed of:
3.2
•
Up to 64 Kbytes of Flash program memory organized as 16 Kwords (16 K × 32 bits).
This area is used to store the application code.
•
2 Kbytes of data EEPROM
•
An information block:
–
Up to 4 Kbytes of system memory
–
Up to 8x4 bytes of user Option bytes
–
Up to 96 bytes of factory Option bytes
NVM main features
The NVM interface features:
•
Read interface organized by word, half-word or byte in every area
•
Programming in the Flash memory performed by word or half-page
•
Programming in the Option bytes area performed by word
•
Programming in the data EEPROM performed by word, half-word or byte
•
Erase operation performed by page (in Flash memory, data EEPROM and Option
bytes)
•
Option byte Loader
•
ECC (Error Correction Code): 6 bits stored for every word to recognize and correct just
one error
•
Mass erase operation
•
Read / Write protection
•
PCROP protection
•
Low-power mode
3.3
NVM functional description
3.3.1
NVM organization
The NVM is organized as 32-bit memory cells that can be used to store code, data, boot
code or Option bytes.
The memory array is divided into pages. A page is composed of 32 words (or 128 bytes) in
Flash program memory and system memory, and 1 single word (or 4 bytes) in data
EEPROM and Option bytes areas (user and factory).
A Flash sector is made of 32 pages (or 4 Kbytes). The sector is the granularity of the write
protection.
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Flash program memory and data EEPROM (FLASH)
Table 4. NVM organization (STM32L0x2 devices)
NVM
Flash program
memory
Data EEPROM
Information block
3.3.2
NVM addresses
Size
(bytes)
Name
0x0800 0000 - 0x0800 007F
128 Bytes
Page 0
0x0800 0080 - 0x0800 00FF
128 Bytes
Page 1
-
-
-
0x0800 0F80 - 0x0800 0FFF
128 Bytes
Page 31
.
.
.
.
.
.
.
.
.
0x0800 7000 - 0x0800 707F
128 bytes
Page 224
0x0800 7080 - 0x0800 70FF
128 bytes
Page 225
-
-
-
0x0800 7F80 - 0x0800 7FFF
128 bytes
Page 255
.
.
.
.
.
.
.
.
.
0x0800 F000 - 0x0800 F07F
128 bytes
Page 480
0x0800 F080 - 0x0800 F0FF
128 bytes
Page 481
-
-
-
0x0800 FF80 - 0x0800 FFFF
128 bytes
Page 511
0x0808 0000 - 0x0808 07FF
2 Kbytes
Data EEPROM
0x1FF0 0000 - 0x1FF0 0FFF
4 Kbytes
System memory
0x1FF8 0020 - 0x1FF8 007F
96 bytes
Factory Options
0x1FF8 0000 - 0x1FF8 001F
32 bytes
User Option bytes
Description
sector 0
.
.
.
sector 7
.
.
.
sector 15
Reading the NVM
Protocol to read
To read the NVM content, take any address from Table 4. The clock of the memory interface
must be running.
Depending on the clock frequency, a 0 or a 1 wait state can be necessary to read the NVM.
The user must set the correct number of wait states (LATENCY bit in the FLASH_ACR
register). No control is done to verify if the frequency or the power used is correct, with
respect to the number of wait states. A wrong number of wait states can generate wrong
read values (high frequency and 0 wait states) or a long time to execute a code (low
frequency with 1 wait state).
You can read the NVM by word (4 bytes), half-word (2 bytes) or byte.
In the NVM, there is only one bank, which means that it is not possible to read during a
write/erase operation. If a write/erase operation is ongoing, the reading will be in a wait state
until the write/erase operation completes, stalling the master that requested the read
operation, except when the address is read-protected. In this case, the error is sent to the
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Flash program memory and data EEPROM (FLASH)
RM0376
master by a bus error or a memory interface flag; no stall is generated and no read is
waiting.
Relation between CPU frequency/Operation mode/NVM read time
The device (and the NVM) can work at different power ranges. For every range, some
master clock frequencies can be set. Table 5 resumes the link between the power range
and the frequencies to ensure a correct time access to the NVM.
Table 5. Link between master clock power range and frequencies
Name
Power range
Maximum frequency
(with 1 wait state)
Maximum frequency
(without wait states)
Range 1
1.65 V - 1.95 V
32 MHz
16 MHz
Range 2
1.35 V - 1.65 V
16 MHz
8 MHz
Range 3
1.05 V - 1.35 V
4.2 MHz
4.2 MHz
Table 6 shows the delays to read a word in the NVM. Comparing the complete time to read
a word (Ttotal) with the clock period, you can see that in Range 3 no wait state is necessary,
also with the maximum frequency (4.2 MHz) allowed by the device. Ttotal is the time that the
NVM needs to return a value, and not the complete time to read it (from memory to Core
through the memory interface); all remaining time is lost.
Table 6. Delays to memory access and number of wait states
Name
Ttotal
Range 1
46.1 ns
Range 2
86.8 ns
Range 3
184.6 ns
Frequency
Period
No wait state
required
32 MHz
31.25
1
16 MHz
62.5
0
16 MHz
62.5
1
8 MHz
125
0
4 MHz
250
0
2 MHz
500
0
Change the CPU Frequency
After reset, the clock used is the MSI (2.1 MHz) and 0 wait state is configured in the
FLASH_ACR register. The following software sequences have to be respected to tune the
number of wait states needed to access the NVM with the CPU frequency.
A CPU clock or a number of wait state configuration changes may take some time before
being effective. Checking the AHB prescaler factor and the clock source status values is a
way to ensure that the correct CPU clock frequency is the configured one. Similarly, the read
of FLASH_ACR is a way to ensure that the number of programmed wait states is effective.
Increasing the CPU frequency (in the same voltage range)
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1.
Program 1 wait state in LATENCY bit of FLASH_ACR register, if necessary.
2.
Check that the new number of wait states is taken into account by reading the
FLASH_ACR register. When the number of wait states changes, the memory interface
modifies the way the read access is done to the NVM. The number of wait states
DocID025941 Rev 1
RM0376
Flash program memory and data EEPROM (FLASH)
cannot be modified when a read operation is ongoing, so the memory interface waits
until no read is done on the NVM. If the master reads back the content of the
FLASH_ACR register, this reading is stopped (and also the master which requested
the reading) until the number of wait states is really changed. If the user does not read
back the register, the following access to the NVM may be done with 0 wait states,
even if the clock frequency has been increased, and consequently the values are
wrong.
3.
Modify the CPU clock source and/or the AHB clock prescaler in the Reset & Clock
Controller (RCC).
4.
Check that the new CPU clock source and/or the new CPU clock prescaler value is
taken into account by reading respectively the clock source status and/or the AHB
prescaler value in the Reset & Clock Controller (RCC). This check is important as some
clocks may take time to get available.
Decreasing CPU frequency (in the same voltage range)
1.
Modify the CPU clock source and/or the AHB clock prescaler in the Reset & Clock
Controller (RCC).
2.
Check that the new CPU clock source and/or the new CPU clock prescaler value is
taken into account by reading respectively the clock source status and/or the AHB
prescaler value in the Reset & Clock Controller (RCC).
3.
Program 0 wait state in LATENCY bit of the FLASH_ACR register, if needed.
4.
Check that the new number of wait states is taken into account by reading
FLASH_ACR. It is necessary to read back the register for the reasons explained in the
previous paragraph.
Data buffering
In the NVM, six buffers can impact the performance (and in some conditions help to reduce
the power consumption) during read operations, both for fetch and data. The structure of
one buffer is shown on Figure 3.
Figure 3. Structure of one internal buffer
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Each buffer stores 3 different types of information: address, data and history. In a read
operation, if the address is found, the memory interface can return data without accessing
the NVM. Data in the buffer is 32 bit wide (even if the master only reads 8 or 16 bits), so that
a value can be returned whatever the size used in a previous reading. The history is used to
know if the content of a buffer is valid and to delete (with a new value) the older one.
The buffers are used to store the value received by the NVM during normal read operations,
and for speculative readings. Disabling the speculative reading makes that only the data
requested by masters is stored in buffers, if enabled (default). This can increase the
performance as no wait state is necessary if the value is already available in buffers, and
reduce the power consumption as the number of reads in memory is reduced and all
combinatorial paths from memory are stable.
The buffers are divided in groups to manage different tasks. The number of buffers in every
group can change starting from the configuration selected by the user (see Table 7). The
total number of buffers used is always 6 (if enabled). The history is always managed by
group.
The memory interface always searches if a particular address is available in all buffers
without checking the group of buffers and if the read is fetch or data.
At reset or after a write/erase operation that changes several addresses, all buffers are
empty and the history is set to EMPTY. After a program by word, half-word or byte, only the
buffer with the concerned address is cleaned.
Table 7. Internal buffer management
Buffers for fetch
DISAB_BUF
PREFTEN
PRE_READ
1
-
0
Buffers for data
Buffers for
jumps
Buffers for
prefetch
Buffers for
last value
Buffers for
pre-read
Buffers for
last value
-
0
0
0
0
0
0
0
3
0
1
0
2
0
1
0
2
1
1
0
2
0
0
1
3
0
1
1
1
0
1
1
2
1
1
1
1
If a value in a buffer is not empty, the history shows the time elapsed between the moment it
has been read or written. The history is organized as a list of values from the latest to the
oldest one. At a given instant, only one buffer in a group can have a particular value of
history (except the empty value). Moving a buffer to the latest position, all other buffers in
the group move one step further, thus maintaining the order. The history is changed to the
latest position when the buffer is read (the master requests for the buffer content) or written
(with a new value from the NVM). The memory interface always writes the oldest buffer (or
one empty buffer, if any) of the right group when a new address is required in memory.
Three configuration bits of the FLASH_ACR register are used to manage the buffering:
•
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DISAB_BUF
Setting this bit disables all buffers. When this bit is 1, the prefetch or the pre-read
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Flash program memory and data EEPROM (FLASH)
operations cannot be enabled and if, for example, the master requests the same
address twice, two readings are generated in the NVM.
•
PRFTEN
Setting this bit to 1 (with DISAB_BUF to 0) enables the prefetch. When the memory
interface does not have any operation in progress, the address following the last
address fetched is read and stored in a buffer.
•
PRE_READ
Setting this bit to 1 (with DISAB_BUF to 0) enables the pre-read. When the memory
interface does not have any operation in progress or prefetch to execute, the address
following the last data address is read and stored in a buffer.
Fetch and prefetch
A memory interface fetch is a read from the NVM to execute the operation that has been
read. The memory interface does not check the master who performs the read operation, or
the location it reads from, but it only verifies if the read operation is done to execute what
has been read. It means that a fetch can be performed:
•
in all areas,
•
with any size (16 or 32 bits).
The memory interface stores in the buffers:
•
The address of jumps so that, in a loop, it is only necessary to access the NVM the first
time, because then the jump address is already available.
•
The last read address so that, when performing a fetching on 16 bits, the other 16 bits
are already available.
To manage the fetch, the memory interface uses 4 buffers: at reset (DISAB_BUF = 0,
PRFTEN = 0, PRE_READ = 0). 3 buffers are used to manage the jumps and 1 buffer to
store the last value fetched. With this configuration, the 4 buffers for fetch are organized in 2
groups with separate histories: the group for loops and the group for the last value fetched.
Setting the PRFTEN bit to 1 enables the prefetch. The prefetch is a speculative read in the
NVM, which is executed when no read is requested by masters, and where the memory
interface reads from the last address fetched increased by 4 (one word). This read is with a
lower priority and it is aborted if a master requests a read (data or fetch) to a different
address than the prefetch one. When the prefetch is enabled, one buffer for loops is moved
to a new group (of only one buffer) to store the prefetched value: 2 buffers continue to store
the jumps, 1 buffer is used for prefetch and 1 buffer is used for the last value.
The memory interface can only prefetch one address, so the function is temporarily disabled
when no fetch is done and the prefetch is already completed. After a prefetch, if the master
requests the prefetched value, the content of the prefetch buffer is copied to the last value
buffer and a new prefetch is enabled. If, instead, the master requests a different address,
the content of the prefetch buffer is lost, a read in the NVM is started (if necessary) and,
when it is complete, a new prefetch is enabled at the new address fetched increased by 4.
The prefetch can only increase the performance when reading with 1 wait state and for
mostly linear codes: the user must evaluate the pros and cons to enable or not the prefetch
in every situation. The prefetch increases the consumption because many more readings
are done in the NVM (and not all of them will be used by the master). To see the advantages
of prefetch on Dhrystone code, refer to the Dhrystone performances section.
Figure 4 shows the timing to fetch a linear code in the NVM when the prefetch is disabled,
both for 0 wait state (a) and 1 wait state (b). You can compare these two sequences with the
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ones in Figure 5, when the prefetch is enabled, to have an idea of the advantages of a
prefetch on a linear code with 0 and 1 wait states.
Figure 4. Timing to fetch and execute instructions with prefetch disabled
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1. (a) corresponds to 0 wait state.
2. (b) corresponds to 1 wait state.
Figure 5 shows the timing to fetch and execute instructions from the NVM with 0 wait states
(a) and 1 wait state (b) when the prefetch is enabled. The read executed by the prefetch
appears in green.
Read as data and pre-read
A data read from the memory interface, corresponds to any read operation that is not a
fetch. The master reads operation constants and parameters as data. All reads done by
DMA (to copy from one address to another) are read as data. No check is done on the
location of the data read (can be in every area of the NVM).
At reset, (DISAB_BUF = 0, PRFTEN = 0, PRE_READ = 0), the memory interface uses 2
buffers organized in one group to store the last two values read as data.
In some particular cases (for example when the DMA is reading a lot of consecutive words
in the NVM), it can be useful to enable the pre-read (PRE_READ = 1 with DISAB_BUF = 0).
The pre-read works exactly like the prefetch: it is a speculative reading at the last data
address increased by 4 (one word). With this configuration, one buffer of data is moved to a
new group to store the pre-read value, while the second buffer continues to store the last
value read. For a prefetch, the pre-read value is copied in the last read value if the master
requests it, or is lost if the master requests a different address.
The pre-read has a lower priority than a normal read or a prefetch operation: this means that
it will be launched only when no other type of read is ongoing. Pay attention to the fact that
a pre-read used in a wrong situation can be harmful: in a code where a data read is not
done linearly, reducing the number of buffers (from 2 to 1) used for the last read value can
increase the number of accesses to the NVM (and the time to read the value). Moreover,
this can generate a delay on prefetch. An example of this situation is the code Dhrystone,
whose results are shown in the corresponding section.
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Flash program memory and data EEPROM (FLASH)
As for a prefetch operation, the user must select the right moment to enable and disable the
pre-read.
Figure 5. Timing to fetch and execute instructions with prefetch enabled
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Table 8 is a summary of the possible configurations.
Table 8. Configurations for buffers and speculative reading
DISAB_BUF
PRFTEN
PRE_READ
Description
1
X
X
Buffers disabled
0
0
0
Buffer enabled: no speculative reading is done
0
1
0
Prefetch enabled: speculative reading on fetch
enabled
0
0
1
pre-read enabled: speculative reading on data
enabled
0
1
1
Prefetch and pre-read enabled: speculative reading
on fetch and data enabled
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Dhrystone performances
The Dhrystone test is used to evaluate the memory interface performances. The test has
been executed in all memory interface configurations. Refer to Table 9 for a summary of the
results.
Common parameters are:
•
the matrix size is 20 x 20
•
the loop is executed 1757 times
•
the version of ARM compiler is 4.1 [Build 561]
Here is some explanation about the results:
Table 9. Dhrystone performances in all memory interface configurations
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Number of
wait states
DISAB_BUF
PRFTEN
PRE_READ
Number of
DMIPS (x1000)
DMIPS x MHz
0
1
0
0
953
15.25
0
0
0
0
953
15.25
0
0
1
0
953
15.25
0
0
0
1
953
15.25
0
0
1
1
953
15.25
1
1
0
0
677
21.66
1
0
0
0
690
22.08
1
0
1
0
823
26.34
1
0
0
1
691
22.11
1
0
1
1
816
26.11
•
The pre-read is not useful for this test: when enabled with the prefetch, it reduces the
memory interface performance because only one buffer is used to store the last data
read and, in this code, the master rarely reads the data linearly. This justifies the very
small increase of performance when enabled without a prefetch.
•
The buffers (without speculative readings) with 1 wait state give a little advantage that
can be considered without any costs.
•
At a 0 wait state, the best performance (as certified by ARM) may be due to a different
code alignment during the compilation.
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3.3.3
Flash program memory and data EEPROM (FLASH)
Writing/erasing the NVM
There are many ways to change the NVM content. The memory interface helps to reduce
the possibility of unwanted changes and to implement by hardware all sequences necessary
to erase or write in the different memory areas.
Write/erase protocol
To write/erase memory content when the protections have been removed, the user needs
to:
1.
configure the operation to execute,
2.
send to the memory interface the right number of data, writing one or several
addresses in the NVM,
3.
wait for the operation to complete.
During the waiting time, the user can prepare the next operation (except in very particular
cases) writing the new configuration and starting to write data for the next write/erase
operation.
The waiting time depends on the type of operation. A write/erase can last from Tprog (3.2
ms) to 2 x Tglob (3.7 ms) + Tprog (3.2 ms). The memory interface can be configured to write
a half-page (16 words in the Flash program memory) with only one waiting time. This can
reduce the time to program a big amount of data.
Two different protocols can be used: single programming and multiple programming
operation.
Single programming operation
With this protocol, the software has to write a value in a not-protected address of the NVM.
When the memory interface receives this writing request, it stalls the master for some
pulses of clock (for more details, see Table 10) while it checks the protections and the
previous value and it latches the new value inside the NVM. The software can then start to
configure the next operation. The operation will complete when the EOP bit of FLASH_SR
register rises (if it was 0 at the operation start). The operation time is resumed in Table 12
for all operations.
Multiple programming operation (half page)
You can write a half-page (16 words) in Flash program memory, To execute this protocol,
follow the next conditions:
•
PGAERR bit in the FLASH_SR register has to be zero (no previous alignment errors).
•
The first address has to be half-page aligned (the 6 lower bits of the address have to be
at zero).
•
All 16 words must be in the same half-page (address bits 7 to 31 must be the same for
all 16 words). This means that the first address sets the half-page and the next ones
must be inside this half-page. The written data will be stored sequentially in the next
addresses. It is not important that the addresses increase or change (for example, the
same address can be used 16 times), as the memory interface will automatically
increase the address internally.
•
Only words (32 bits) can be written.
When the memory interface receives the first address, it stalls the master for some pulses of
clock while it checks the protections and the previous value and it latches the new value
inside the NVM (for more details, see Table 10). Then, the memory interface waits for the
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second address. No read is accepted: only a fetch will be executed, but it aborts the ongoing
write operation. After the second address, the memory interface stalls the core for a short
time (less than the previous one) to perform a check and to latch it in the NVM before
waiting for the next one. This sequence continues until all 16 words have been latched
inside the NVM. A wrong alignment or size will abort the write operation. If the 16 addresses
are correctly latched, the memory interface starts the write operation. The operation will
complete when EOP bit of FLASH_SR register rises (if it was 0 at the operation start). The
operation time is resumed in Table 12.
This protocol can be used either through application code running from RAM or through
DMA with application code running from RAM or core sleeping.
Unlocking/locking operations
Before performing a write/erase operation, it is necessary to enable it. The user can write
into the Flash program memory, data EEPROM and Option bytes areas.
To perform a write/erase operation, unlock PELOCK bit of the FLASH_PECR register. When
this bit is unlocked (its value is 0), the other bits of the same register can be modified. When
PELOCK is 0, the write/erase operations can be executed in the data EEPROM.
To write/erase the Flash program memory, unlock PRGLOCK bit of the FLASH_PECR
register. The bit can only be unlocked when PELOCK is 0.
To write/erase the user Option bytes, unlock OPTLOCK bit of the FLASH_PECR register.
The bit can only be unlocked when PELOCK is 0. No relation exists between PRGLOCK
and OPTLOCK: the first one can be unlocked when the second one is locked and vice
versa.
Unlocking the data EEPROM and the FLASH_PECR register
After a reset, the data EEPROM and the FLASH_PECR register are not accessible in write
mode because PELOCK bit in the FLASH_PECR register is set. The same unlocking
sequence unprotects both of them at the same time.
The following sequence is used to unlock the data EEPROM and the FLASH_PECR
register:
•
Write PEKEY1 = 0x89ABCDEF to the FLASH_PEKEYR register
•
Write PEKEY2 = 0x02030405 to the FLASH_PEKEYR register
Any wrong key sequence will lock up FLASH_PECR until the next reset and generate a bus
error. Idem if the master tries to write another register between the two key sequences or if it
uses the wrong key. A reading access does not generate an error and does not interrupt the
sequence. A bus error is returned in any of the four cases below:
•
After the first write access if the PEKEY1 value entered is erroneous.
•
During the second write access if PEKEY1 is correctly entered but the value of
PEKEY2 does not match.
•
If there is any attempt to write a third value to PEKEYR (attention: this is also true for
the debugger).
•
If there is any attempt to write a different register of the memory interface between
PEKEY1 and PEKEY2.
When properly executed, the unlocking sequence clears PELOCK bit in the FLASH_PECR
register.
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To lock FLASH_PECR and the data EEPROM again, the software only needs to set
PELOCK bit in FLASH_PECR. When locked again, PELOCK bit needs a new sequence to
return to 0.
Unlocking the Flash program memory
An additional protection is implemented to write/erase the Flash program memory.
After a reset, the Flash program memory is no more accessible in write mode: PRGLOCK
bit is set in the FLASH_PECR register. A write access to the Flash program memory is
granted by clearing PRGLOCK bit.
The following sequence is used to unlock the Flash program memory:
•
Unlock the FLASH_PECR register (see the Unlocking the data EEPROM and the
FLASH_PECR register section).
•
Write PRGKEY1 = 0x8C9DAEBF to the FLASH_PRGKEYR register.
•
Write PRGKEY2 = 0x13141516 to the FLASH_PRGKEYR register.
If the keys are written with PELOCK set to 1, no error is generated and PRGLOCK remains
at 1. It will be unlocked while re-executing the sequence with PELOCK = 0.
Any wrong key sequence will lock up PRGLOCK in FLASH_PECR until the next reset, and
return a bus error. A bus error is returned in any of the four cases below:
•
After the first write access if the entered PRGKEY1 value is erroneous.
•
During the second write access if PRGKEY1 is correctly entered but the PRGKEY2
value does not match.
•
If there is any attempt to write a third value to PRGKEYR (this is also true for the
debugger).
•
If there is any attempt to write a different register of the memory interface between
PRGKEY1 and PRGKEY2.
When properly executed, the unlocking sequence clears the PRGLOCK bit and the Flash
program memory is write-accessible.
To lock the Flash program memory again, the software only needs to set PRGLOCK bit in
FLASH_PECR. When locked again, PRGLOCK bit needs a new sequence to return to 0. If
PELOCK returns to 1 (locked), PRGLOCK is automatically locked, too.
Unlocking the Option btyes area
An additional write protection is implemented on the Option bytes area. It is necessary to
unlock OPTLOCK to reload or write/erase the Option bytes area.
After a reset, the Option bytes area is not accessible in write mode: OPTLOCK bit in the
FLASH_PECR register is set. A write access to the Option bytes area is granted by clearing
OPTLOCK.
The following sequence is used to unlock the Option bytes area:
1.
Unlock the FLASH_PECR register (see the Unlocking the data EEPROM and the
FLASH_PECR register section).
2.
Write OPTKEY1 = 0xFBEAD9C8 to the FLASH_OPTKEYR register.
3.
Write OPTKEY2 = 0x24252627 to the FLASH_OPTKEYR register.
If the keys are written with PELOCK = 1, no error is generated, OPTLOCK remains at 1 and
it will be unlocked when re-executing the sequence with PELOCK to 0.
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Any wrong key sequence will lock up OPTLOCK in FLASH_PECR until the next reset, and
return a bus error. A bus error is returned in any of the four cases below:
•
After the first write access if the OPTKEY1 value entered is erroneous.
•
During the second write access if OPTKEY1 is correctly entered but the OPTKEY2
value does not match.
•
If there is any attempt to write a third value to OPTKEYR (this is also true for the
debugger).
•
If there is any attempt to write a different register of the memory interface between
OPTKEY1 and OPTKEY2.
When properly executed, the unlocking sequence clears the OPTLOCK bit and the Option
bytes area is write-accessible.
To lock the Option bytes area again, the software only needs to set OPTLOCK bit in
FLASH_PECR. When relocked, OPTLOCK bit needs a new sequence to return to 0. If
PELOCK returns to 1 (locked), OPTLOCK is automatically locked, too.
Select between different types of operations
When the necessary unlock sequence has been executed (PELOCK, PRGLOCK and
OPTLOCK), the user can enable different types of write and erase operations, writing the
right configuration in the FLASH_PECR register. The bits involved are:
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•
PRG
•
DATA
•
FIX
•
ERASE
•
FPRG
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Flash program memory and data EEPROM (FLASH)
Detailed description of NVM write/erase operations
This section details the different types of write and erase operations, showing the necessary
bits for each one.
Write to data EEPROM
•
Purpose
Write one word in the data EEPROM with a specific value.
•
Size
Write by byte, half-word or word.
•
Address
Select a valid address in the data EEPROM.
•
Protocol
Single programming operation.
•
Requests
PELOCK = 0.
•
Errors
WRPERR is set to 1 (and the write operation is not executed) if PELOCK = 1 or if the
memory is read-out protected.
•
Description
This operation aims at writing a word or a part of a word in the data EEPROM. The user
must write the right value at the right address and with the right size. The memory
interface automatically executes an erase operation when necessary (if all bits are
currently set to 0, there is no need to delete the old content before writing). Similarly, if
the data to write is at 0, only the erase operation is executed. When only a write
operation or an erase operation is executed, the duration is Tprog (3.2 ms); if both are
executed, the duration is 2 x Tprog (6.4 ms). It is possible to force the memory interface
to execute every time both erase and write operations set the FIX flag to 1.
•
Duration
Tprog (3.2 ms) or 2 x Tprog (6.4 ms).
•
Options
Set the FIX bit to force the memory interface to execute every time an erase (to delete
the old content) and a write operation (to write new data) occur. This gives a fix time for
the operation for any data value and for previous data.
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Erase data EEPROM
•
Purpose
Delete one row in the data EEPROM.
•
Size
Erase only by word.
•
Address
Select one valid address in the data EEPROM.
•
Protocol
Single programming operation.
•
Requests
PELOCK = 0, ERASE = 1 (optional DATA = 1).
•
Errors
WRPERR is set to 1 if PELOCK = 1 or if the memory is read-out protected.
SIZERR is set to 1 if the size is not a word.
•
Description
This operation aims at deleting the content of a row in the data EEPROM. A row
contains only 1 word. The user must write a value at the right address with a word size.
The data is not important: only an erase is executed (also with data different from zero).
•
Duration
Tprog (3.2 ms).
Write Option bytes
•
Purpose
Write one word in the Option bytes area with a specific value.
•
Size
Write only by word.
•
Address
Select a valid address in the Option bytes area.
•
Protocol
Single programming operation.
•
Requests
PELOCK = 0, OPTLOCK = 0.
•
Errors
WRPERR is set to 1 if PELOCK = 1 or OPTLOCK = 1.
WRPERR is set to 1 if the actual read-out protection level is 2 (the Option bytes area
cannot be written at Level 2).
SIZERR is set to 1 if the size is not the word
•
Description
This operation aims at writing a word in the Option bytes area. The Option bytes area
can only be written in Level 0 or Level 1.
The user must consider that, in a word, the 16 higher bits (from 16 to 31) have to be the
complement of the 16 lower bits (from 0 to 15): a mismatch between the higher and
lower parts of data would generate an error during the Option bytes loading (see
Section 3.8: Option bytes) and force the memory interface to load the default values.
The memory interface does not check at the write time if the data is correctly
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complemented. The user must write the desired value at the right address with a word
size.
As for data EEPROM, the memory interface deletes the previous content before
writing, if necessary. If the data to write is at 0, the memory interface does not execute
the useless write operation. When only a write operation or only an erase operation is
executed, the duration is Tprog (3.2 ms). If both are executed, the duration is 2 x Tprog
(6.4 ms). The memory interface can be forced to execute every time both erase and
write operations set the FIX flag to 1.
Some configurations need a closer attention because they change the protections. The
memory interface can change the Option bytes write in a Mass Erase or force some
bits not to reduce the protections: for more details, see Section 3.4.4: Write/erase
protection management.
•
Duration
Tprog (3.2 ms) or 2 x Tprog (6.4 ms).
•
Options
FIX bit can be set to force the memory interface to execute every time an erase (to
delete the old content) and a write operation (to write the new data) occur. This gives a
fix time to program for every data value and for previous data.
Erase Option bytes
•
Purpose
Delete one row in the Option bytes area.
•
Size
Erase only by word.
•
Address
Select a valid address in the Option bytes area.
•
Protocol
Single programming operation.
•
Requests
PELOCK = 0, OPTLOCK = 0, ERASE = 1 (optional OPT = 1).
•
Errors
WRPERR is set to 1 if PELOCK = 1 or OPTLOCK = 1.
WRPERR is set to 1 if the actual protection level is 2 (the Option bytes area cannot be
erased at Level 2).
SIZERR is set to 1 if the size is not the word.
•
Description
This operation aims at deleting the content of a row in the Option bytes area. A row
contains only 1 word. The data is not important: only an erase is executed (also with
data different from zero). The user has to write a value at the right address with a word
size.
Refer to Section : Write Option bytes for additional information.
Since all bits are set to 0 after an erase operation, there will be a mismatch during the
Option bytes loading and the default values will be loaded.
•
Duration
Tprog (3.2 ms).
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Program a single word to Flash program memory
•
Purpose
Write one word in the Flash program memory with a specific value.
•
Size
Write only by word.
•
Address
Select an address in the Flash program memory.
•
Protocol
Single programming operation.
•
Requests
PELOCK = 0, PRGLOCK = 0.
•
Errors
WRPERR is set to 1 if PELOCK = 1 or PRGLOCK = 1.
WRPERR is set to 1 if the user tries to write in a write-protected sector (see the PcROP
(Proprietary Code Read-Out Protection) section).
NOTZEROERR is set to 1 if the user tries to write a value in a word which is not zero.
This error does not stop the write operation: this means that reading back the written
address may return a value different from the one that was written.
SIZERR is set to 1 if the size is not a word.
•
Description
This operation aims at writing a word in the Flash program memory. The user must
write the right value at the right address with a word size. The memory interface cannot
execute an erase to delete the previous content before a write. If the previous content
is not null, the real value written in the memory is the OR of the previous value with the
new value (the memory interface writes 1 when there was 0 before). This is done both
for data and the ECC part of data. When data is read later on, it may not correspond to
the old ones, to the new ones or to the OR. The ECC is not compatible with the data
any more.
•
Duration
Tprog (3.2 ms).
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Program half-page in Flash program memory
•
Purpose
Write one half page (16 words) in the Flash program memory.
•
Size
Write only by word.
•
Address
Select one address in the Flash program memory aligned to a half-page (for the first
address) and inside the same half-page selected by the second address for the next 15
addresses.
•
Protocol
Multiple programming operation.
•
Requests
PELOCK = 0, PRGLOCK = 0, FPRG = 1, PRG = 1.
•
Errors
WRPERR is set to 1 if PELOCK = 1 or PRGLOCK = 1.
WRPERR is set to 1 if the user tries to write in a write-protected sector (see the PcROP
(Proprietary Code Read-Out Protection) section).
NOTZEROERR is set to 1 if the user tries to write a value in a word which is not zero.
This error does not stop the write operation: this means that reading back the written
address may return a value which is different from the written one. The check is done
on all 16 addresses at the beginning of the operation and the error rises only once at
the end of all checks, if at least one check failed.
SIZERR is set to 1 if the size is not the word.
PGAERR is set to 1 if the first address is not aligned to a half-page.
PGAERR is set to 1 if one of the following addresses (the addresses from 2 to 16) is
outside the half-page determined by the first address. No check is done to verify if the
address has increased or if it has changed: this is done automatically by the memory
interface. What is important is that the first address is aligned to the half-page, and that
the next addresses are in the same half-page.
FWWERR is set to 1 if the write is aborted because the master fetched in the NVM.
The read as data does not stop the write operation.
•
Description
This operation aims at writing a half-page in the Flash program memory. The user must
write the 16 desired values at the right address with a word size (as explained in the
multiple programming operation). The memory interface cannot execute an erase to
delete the previous content before writing (the user must delete the page before
writing). As for the single programming operation, the written value is the OR of
previous and new data. When a half-page operation starts, the memory interface waits
for 16 addresses/data, aborting (with a bus error) all read accesses that are not a fetch
(refer to Fetch and prefetch). A fetch stops the half-page operation but the FWWERR
error is set in the FLASH_SR register.
•
Duration
Tprog (3.2 ms).
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Erase a page in Flash program memory
•
Purpose
Delete one page (32 words) in the Flash program memory.
•
Size
Erase only by word (it deletes a page of the Flash program memory writing with a word
size)
•
Address
Select a valid address in the Flash program memory.
•
Protocol
Single programming operation.
•
Requests
PELOCK = 0, PRGLOCK = 0, ERASE = 1, PRG = 1.
•
Errors
WRPERR is set to 1 if PELOCK = 1 or PRGLOCK = 1.
WRPERR is set to 1 if the row is in a protected sector (see PcROP (Proprietary Code
Read-Out Protection)).
SIZERR is set to 1 if the size is not the word.
•
Description
This operation aims at deleting the content of a row in the Flash program memory. The
user must write a value in the right address with a word size. The data is not important:
only an erase is executed (also with data not at zero). The address does not need to be
aligned to the page: the memory interface will delete the page which contents the
address.
•
Duration
Tprog (3.2 ms).
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Flash program memory and data EEPROM (FLASH)
Mass erase
•
Purpose
Remove the read and write protection on the Flash program memory and data
EEPROM.
•
Size
Erase only by word.
•
Address
To generate a mass erase, it is necessary to write 0x015500AA to the first Option bytes
address (bits 31 to 25 and 15 to 9 are not complemented because they are not used,
and not checked) with Level 1 as the actual level.
•
Protocol
Single programming operation.
•
Requests
PELOCK = 0, OPTLOCK = 0, Protection Level = 1, the lower nibble of data has to be
0xAA (Level 0), with 0x55 as the third nibble.
•
Errors
WRPERR is set to 1 if PELOCK = 1 or OPTLOCK = 1.
WRPERR is set to 1 if the actual protection level is 2 (the Option bytes area cannot be
written in Level 2).
SIZERR is set to 1 if the size is not the word.
•
Description
This operation is similar to the write user Option byte operation: the memory interface
changes it in a mass erase when the actual Protection Level is 1 and the requested
Protection Level is 0. The user must write the desired value in the first address of the
Option bytes area with a word size.
A mass erase deletes the content of the Flash program memory and data EEPROM,
changes the protection level to Level 0 and disables PcROP. (WPRMOD = 0). The bits
write protection and BOR_LEVEL remain unchanged.
Unlike all other operations, the software cannot request new writing operations while a
mass erase is ongoing. To be sure that a mass erase has completed, the software can
reset the EOP bit of FLASH_SR register before the write operation and check when
EOP goes to 1 (End Of Program). If this limitation is not respected, a wrong value may
be written in the Flash program memory and data EEPROM when the Protection Level
is written, thus adding unwanted protections (also for mismatch) that could make the
device useless.
•
Duration
2 x Tprog (6.4 ms) + Tglob (3.7 ms)
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Timing tables
Table 10. NVM write/erase timings
Delay to latch the first
address/data
(in AHB clock pulses)
Delay to latch the next
address/data
(in AHB clock pulses)
Write to data EEPROM
18
--
Erase data EEPROM
17
--
Write Option bytes
18
--
Erase Option bytes
17
--
Program a single word in Flash
program memory
78
--
Program half-page in Flash
program memory
63
6
Erase a page in Flash program
memory
76
--
Operation
Table 11. NVM write/erase duration
Operation
Parameters/Conditions
Duration
Previous data = 0
FIX = 0
Tprog (3.2 ms)
Previous data /= 0
New data = 0
Size = word
FIX = 0
Tprog (3.2 ms)
Other situations
2 x Tprog (6.4 ms)
--
Tprog (3.2 ms)
Previous data = 0
FIX = 0
Tprog (3.2 ms)
Previous data /= 0
New data = 0
FIX = 0
Tprog (3.2 ms)
Other situations
2 x Tprog (6.4 ms)
Erase Option bytes
--
Tprog (3.2 ms)
Program a single word in
Flash program memory
--
Tprog (3.2 ms)
Program a half-page in
Flash program memory
--
Tprog (3.2 ms)
Erase a page in Flash
program memory
--
Tprog (3.2 ms)
Write to data EEPROM
Erase data EEPROM
Write Option bytes
Mass erase
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Flash program memory and data EEPROM (FLASH)
Status register
The FLASH_SR Status Register gives some information on the memory interface or the
NVM status (operation(s) ongoing) and about errors that happened.
BSY
This flags is set and reset by hardware. It is set to 1 every time the memory interface
executes a write/erase operation, and it informs that no other operation can be executed. If
a new operation is requested, different behaviors can occur:
•
Waiting for read, or waiting for write/erase, or waiting for option loading:
If the software requests a write operation while a write/erase operation is executing
(HVOFF = 0), the memory interface stalls the master and has the pending operation
execute as soon as the write/erase operation is complete.
•
Bus error:
If the software requests a data read in a half-page operation when the memory
interface is waiting for the next address/data (BSY is already 1 but HVOFF = 0), the
memory interface generates a bus error (because it cannot execute the read) and
continues to wait for missing addresses.
•
RDERR error:
If the software requests a read operation while a write/erase operation is executing
(HVOFF = 0) but the address is protected, the memory interface rises the flag and
continues to wait for the end of the write/erase operation.
•
Write abort:
If the software fetches in the NVM when the memory interface is waiting for an
address/data in a half-page operation, the write/erase operation is aborted, the
FWWERR flag is raised and the fetch is executed.
EOP
This flag is set by hardware and reset by software. The software can reset it writing 1 in the
status register. This bit is set when the write/erase operation is completed and the memory
interface can work on other operations (or start to work on pending operations).
It is useful to clear it before starting a new write/erase operation, in order to know when the
actual operation is complete. It is very important to wait for this flag to rise when a mass
erase is ongoing, before requesting a new operation.
HVOFF
This flag is set and reset by hardware and it is a memory interface information copy coming
from the NVM: it informs when the High-Voltage Regulators are on (= 0) or off (= 1).
PGAERR
This flag is set by hardware and reset by software. It informs when an alignment error
happened. It is raised when:
•
The first address in a half-page operation is not aligned to a half-page (lower 6 bits
equal to zero).
•
A half-page change happened in a half-page operation (the addresses from 2 to 16 in a
half-page operation are not in the same half-page, selected by the first address).
An alignment error aborts the write/erase operation and an interrupt can be generated (if
ERRIE = 1 in the FLASH_PECR register). The content of the NVM is not changed.
If this flag is set, the memory interface blocks all other half-page operations.
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To reset this flag, the software need to write it to 1.
SIZERR
This flag is set by hardware and reset by software. It informs when a size error happened. It
is raised when:
•
A write by byte and half-word occurs in the Flash program memory and Option bytes.
•
An erase (with bit ERASE = 1 in FLASH_PECR register) by byte or half-word occurs in
all areas.
A size error aborts the write/erase operation and an interrupt can be generated (if
ERRIE = 1 in the FLASH_PECR register). The content of the NVM is not changed.
To reset this flag, the software needs to write it to 1.
NOTZEROERR
This flag is set by hardware and reset by software. It informs when the software is writing, in
the NVM, a value which can result in a corruption because the actual content is not at 0 and
the memory interface cannot execute an erase operation to delete the old content before
writing.
In a write by half-page, all 16 words are checked between the first address/value and the
second one, and the flag is only set when all words are checked. If the flag is set, it means
that at least one word has an actual value not at zero.
In a write by word, only the word concerned is checked and the flag is immediately set if the
content is not zero.
A not-zero error does not abort the write/erase operation but can generate an interrupt if
ERRIE = 1 in the FLASH_PECR register.
To reset this flag, the software needs to write it to 1.
3.4
Memory protection
The user can protect part of the NVM (Flash program memory, data EEPROM and Option
bytes areas) from unwanted write and against code hacking (unwanted read).
Three types of protections are implemented.
3.4.1
RDP (Read Out Protection)
This type of protection aims at protecting against unwanted read (hacking) of the NVM
content. This protection is managed by RDPROT bitfield in the FLASH_OPTR register. The
value is loaded from the Option bytes area during a boot and copied in the read-only
register.
Three protection levels are defined:
•
Level 0: no protection
Level 0 is set when RDPROT is set to 0xAA. When this level is enabled, and if no other
protection is enabled, read and write can be done in the Flash program memory, data
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Flash program memory and data EEPROM (FLASH)
EEPROM and Option bytes areas without restrictions. It is also possible to read and
write the backup registers freely.
•
Level 1: memory read protection
Level 1 is set when RDPROT is set to any value except 0xAA and 0xCC, respectively
used for Level 0 and Level 2. This is the default protection level after an Option bytes
erase or when there is a mismatch in the RDPROT field.
The memory interface saves internally if the device boot in the RAM, or the System
Memory, or the debug features (single-wire) is connected. This information is reset only
with power-down (the system reset or the option loading is not sufficient) or when the
device moves to Level 2. It protects the Flash program memory and data EEPROM.
When this level is enabled:
•
–
No access to the Flash program memory and data EEPROM (read both for fetch
and data and write) and no backup register reading is performed if the debug
features (single-wire), or the device boot in the RAM, or the System memory is
connected. If the user tries to read the Flash memory or data EEPROM, a bus
error is generated. No restriction is present on other areas: it is possible to read
and write/erase the Option bytes area and to execute or read in the System
Memory.
–
All operations are possible when the boot is done in the Flash program memory.
–
Writing the first Option byte with a value that changes the protection level to Level
0 (it is necessary that byte 0 is 0xAA and byte 2 is 0x55), a mass erase is
generated. The mass erase deletes the Flash program memory and data
EEPROM, deletes the first Option byte and then rewrites it to enable Level 0 and
disable PCROP (WPRMOD = 0), and deletes the backup registers content.
Level 2: disable debug and chip read protection
Level 2 is set when RDPROT is set to 0xCC. When this level is enabled, it is only
possible to boot from the Flash program memory, and the debug features (single-wire)
are disabled. The Option bytes are protected against write/erase and the protection
level can no longer be changed. The application can write/erase to the Flash program
memory and data EEPROM (it is only possible to boot from the Flash program memory
and execute the customer code) and access the backup registers. When an Option
bytes loading is executed and Level 2 is enabled, old information on debug or boot in
the RAM or System memory are deleted.
Figure 6 resumes the way the protection level can be changed and Table 12 the link
between the values read in the Option bytes and the protection level.
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Figure 6. RDP levels
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-36
Table 12. Protection level and content of RDP Option bytes
RDP byte value
RDP complementary value
Read Protection status
0xAA
0x55
Level 0
0xCC
0x33
Level 2
Any other value
Complement of RDP byte
Level 1
Any value
Not the complement value of RDP byte
Level 1
3.4.2
PcROP (Proprietary Code Read-Out Protection)
The Flash program memory can be protected from being read by a hacking code: the read
data are blocked (not for a fetch). The protected code must not access data in the protected
zone, including the literal pool.
The Flash program memory can be protected against a hacking code read: this blocks the
data read (not for a fetch), assuming that the native code is compiled according to the
PcROP option. This mode is activated setting WPRMOD = 1 in the FLASH_OPTR register.
The protection granularity is the sector (1 sector = 32 pages = 4 KB). To protect a sector, set
to 0 the right bit in the WRPROT configuration: 0 means read and write protection, 1 means
no protection.
Table 13 shows the link between the bits of the WRPROT configuration and the address of
the Flash memory sectors.
Any read access performed as data (see Read as data and pre-read) in a protected sector
will trigger the RDERR flag in the FLASH_SR register. Any read-protected sector is also
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Flash program memory and data EEPROM (FLASH)
write-protected and any write access to one of these sectors will trigger the WRPERR flag in
the FLASH_SR register.
Table 13. Link between protection bits of FLASH_WRPROT register
and protected address in Flash program memory
Bit
Start address
End address
Bit
Start address
End address
0
0x0800 0000
0x0800 0FFF
8
0x0800 8000
0x0800 8FFF
1
0x0800 1000
0x0800 1FFF
9
0x0800 9000
0x0800 9FFF
2
0x0800 2000
0x0800 2FFF
10
0x0800 A000
0x0800 AFFF
3
0x0800 3000
0x0800 3FFF
11
0x0800 B000
0x0800 BFFF
4
0x0800 4000
0x0800 4FFF
12
0x0800 C000
0x0800 CFFF
5
0x0800 5000
0x0800 5FFF
13
0x0800 D000
0x0800 DFFF
6
0x0800 6000
0x0800 6FFF
14
0x0800 E000
0x0800 EFFF
7
0x0800 7000
0x0800 7FFF
15
0x0800 F000
0x0800 FFFF
When WPRMOD = 1 (PcROP enabled), it is not possible to reduce the protection on a
sector: new zeros (to protect new sectors) can be set, but new ones (to remove the
protection from sectors) cannot be added. This is valid regardless of the protection level
(RDPROT configuration). When WPRMOD is active, if the user tries to reset WPRMOD or
to remove the protection from a sector, the programming is launched but WPRMOD or
protected sectors remain unchanged.
The only way to remove a protection from a sector is to request a mass erase (which
changes the protection level to 0 and disables PcROP): when PcROP is disabled, the
protection on sectors can be changed freely.
3.4.3
Protections against unwanted write/erase operations
The memory interface implements two ways to protect against unwanted write/erase
operations which are valid for all matrix or only for specific sectors of the Flash program
memory.
As explained in the Unlocking/locking operations section, the user can:
•
Write/erase to the data EEPROM only when PELOCK = 0 in the FLASH_PECR
register.
•
Write/erase to the Option bytes area only when PELOCK = 0 and OPTLOCK = 0 in the
FLASH_PECR register.
•
Write/erase to the Flash program memory only when PELOCK = 0 and PRGLOCK = 0
in the FLASH_PECR register.
To see the sequences to set PELOCK, PRGLOCK and OPTLOCK, refer to the Unlocking
the data EEPROM and the FLASH_PECR register, Unlocking the Flash program memory
and Unlocking the Option btyes area sections.
In the Flash program memory, it is possible to add another write protection with the sector
granularity. When PcROP is disabled (WPRMODE = 0), the bits of WRPROT are used to
enable the write protection on the sectors. The polarity is opposed relatively to PcROP: to
protect a sector, it is necessary to set the bit to 1; to remove the protection, it is necessary to
set the bit to 0. Table 13 is valid for a write protection as well. As explained, when PcROP is
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enabled, the sectors protected against read are also protected against write/erase. It is
always possible to change the write protection on sectors both in Level 0 and Level 1
(provided that it is possible to write/erase to Option bytes and that PcROP is disabled).
Table 14 resumes the protections.
Table 14. Memory access vs mode, protection and Flash program memory sectors
Mode
Flash program memory
sectors
User
(including In Application
Programming)
no Debug, or
no Boot in RAM, or
no Boot in System memory
User
in Debug, or
with Boot in RAM, or
with Boot in System memory
RDP
Level 1
Level 0
Level 2
Level 0
Level 1
Level 2
Flash program memory
(FLASH_PRGLOCK = 1)
R
R
R
Protected
(no access)
NA(1)
Flash memory
(FLASH_PRLOCK = 0)
R/W
R/W
R/W
Protected
(no access)
NA(1)
Flash program memory
in WRP pages
R
R
R
Protected
(no access)
NA(1)
Flash program memory
in PCROP pages
Fetch
Fetch
Fetch
Protected
(no access)
NA(1)
Data EEPROM
(FLASH_PELOCK = 1)
R
R
R
Protected
(no access)
NA(1)
Data EEPROM
(FLASH_PELOCK = 0)
R/W
R/W
R/W
Protected
(no access)
NA(1)
Option bytes
(FLASH_OPTLOCK = 1)
R
R
R
R
NA(1)
Option bytes
(FLASH_OPTLOCK = 0)
R/W
R
R/W
R/W
NA(1)
1. NA stands for “not applicable”.
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3.4.4
Flash program memory and data EEPROM (FLASH)
Write/erase protection management
Here is a summary of the rules to change all previous protections:
3.4.5
•
When the protection Level is 2, no protection change can be done.
•
When in Level 0 or 1, it is always possible to move to Level 2, writing xx33xxCC (the x
are the hexadecimal digits that can have any value) in the first Option byte word.
•
When in Level 0, it is possible to move to Level 1, writing any value in the first Option
byte word that is not xx33xxCC (Level 2) or xx55xxAA (Level 0).
•
when in Level 1, the protection can be reduced to Level 0, writing xx55xxAA in the first
Option byte word. This generates a mass erase and deletes the PcROP field too.
•
It is always possible to enable PcROP (except in Level 2), writing x0xxx1xx in the first
Option byte word. If there is a mismatch during an Option byte loading on this flag,
PcROP is enabled.
•
PcROP can be removed on requesting a mass erase (move from Level 1 to Level 0).
•
When PcROP is disabled, a write protection can be added on sectors (writing 1) or
removed (writing 0) in the third word of the Option bytes. A mismatch concerns all
write-protected sectors (if PcROP is disabled).
•
When PcROP is enabled, protected sectors can be added (writing 0) but cannot be
removed. A mismatch concerns all read- and write-protected sectors (if PcROP is enabled).
•
A mass erase does not delete the third word of the Option bytes: the user must write it
correctly.
Protection errors
Write protection error flag (WRPERR)
If an erase/program operation to a write-protected page of the Flash program memory and
data EEPROM is launched, the Write Protection Error flag (WRPERR) is set in the
FLASH_SR register.
Consequently, the WRPERR flag is set when the software tries to:
•
Write to a WRP page.
•
Write to a System memory page or to factory option bytes.
•
Write to the Flash program memory, data EEPROM or Option bytes if they are not
unlocked by PEKEY, PRGKEY or OPTKEY.
•
Write to the Flash program memory, data EEPROM or Option bytes when the RDP
Option byte is set and the device is in debug mode or is booting from the RAM or from
the System memory.
A write-protection error aborts the write/erase operation and an interrupt can be generated
(if ERRIE = 1 in the FLASH_PECR register).
To reset this flag, the software needs to write it to 1.
Read error (RDERR)
If the software tries to read a sector protected by PcROP, the RDERR flag of FLASH_SR is
raised. The data received on the bus is at 0.
If the error interrupt is enabled (ERRIE = 1 in the FLASH_PECR register), an interrupt is
generated.
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To reset this flag, the software needs to write it to 1.
3.5
NVM interrupts
Setting the End of programming interrupt enable bit (EOPIE) in the FLASH_PECR register
enables an interrupt generation when an erase or a programming operation ends
successfully. In this case, the End of programming (EOP) bit in the FLASH_SR register is
set. To reset it, the software needs to write it to 1.
Setting the Error interrupt enable bit (ERRIE) in the FLASH_PECR register enables an
interrupt generation if an error occurs during a programming or an erase operation request.
In this case, one or several error flags are set in the FLASH_SR register:
•
RDERR (PCROP Read protection error flags)
•
WRPERR (Write protection error flags)
•
PGAERR (Programming alignment error flag)
•
OPTVERR (Option validity error flag)
•
SIZERR (Size error flag)
•
FWWERR (Fetch while write error flag)
•
NOTZEROERR (Write a not zero word error flag)
To reset the error flag, the software needs to write the right flag to 1.
Table 15. Flash interrupt request
Interrupt event
End of operation
Error
3.5.1
Event flag
Enable control bit
EOP
EOPIE
RDERR
WRPERR
PGAERR
OPTVERR
SIZERR
FWWERR
NOTZEROERR
ERRIE
Bus error (Hard fault)
A bus error is generate on:
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•
The memory bus if a read access is attempted when RDP is set.
•
The memory bus if a read as data is received; then, the memory interface is waiting for
a data/address during a half-page write (after the 1st address and before the 16th
address).
•
The register bus if an incorrect value is written in PEKEYR, PRGKEYR, or OPTKEYR.
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3.6
Flash program memory and data EEPROM (FLASH)
Memory interface management
The purpose of this section is to clarify what happens when one operation is requested
while another is ongoing: the way the different operations work together and are managed
by the memory interface.
3.6.1
Operation priority and evolution
There are three types of operations and each of them has different flows:
Read
•
If no operation is ongoing and the read address is not protected, the read is executed
without delays and with the actual configurations.
•
If the read address is protected, the operation is filtered (the read requested is never
sent to the memory) and an error is raised.
•
If the read address is not protected but the memory interface is busy and cannot
perform the operation, the read is put on hold to be executed as soon as possible.
Write/erase
•
If no operation is ongoing and the write address is not protected, the write/erase will
start immediately; after some clock pulses (see Table 10) during which the bus and the
master are blocked, the memory interface continues the operation freeing the bus and
the master.
•
If the address is protected, the write/erase is filtered (the write/erase requested is never
sent to the memory) and an error is raised.
•
If the address is not protected but one or several conditions are not met, the operation
is aborted (the abort needs more time to be executed because the NVM and data
EEPROM need to return to default configuration) and an error is raised.
•
If the address to write/erase is not protected and all rules are respected, and if the
memory interface is busy, the operation is put on hold to be executed as soon as
possible.
Option byte loading
•
If a write/erase is ongoing, the Option byte loading waits for the end of operation then it
is executed: no other write/erase is accepted, even if waiting.
•
If no write/erase is ongoing, the Option byte is executed directly (the read operation is
executed until the system reset goes to 0 as a result of the Option byte request).
This means that the Option byte loading has a bigger priority than the read and write/erase
operations. All other operations are executed in the order of request.
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Sequence of operations
Read as data while write
If the master requests a read as data (see Read as data and pre-read) while a write
operation is ongoing, there are three different cases:
1.
If the read is in a protected area, the RDERR flag is raised and the write operation
continues.
2.
If the write operation uses a Single programming operation or a Multiple programming
operation (half page) and all addresses/data have been sent to the memory interface,
the read is put on hold and will be executed when the write operation is complete. It is
important to emphasize that, during all the time spent when the read waits to be
executed, the master is blocked and no other operation can be executed until the write
and read operations are complete.
3.
if the write operation uses a Multiple programming operation (half page) and not all
addresses/data have been sent to the memory interface, the read is not accepted, a
bus error is generated and the memory interface continues to wait for the missing
addresses/data to complete the write operation.
Fetch while write
If the master fetches an instruction while a write is ongoing, the situation is similar to a read
as data (see 1. and 2.), but the last case is as follows:
•
If the write operation uses a Multiple programming operation (half page) and not all
addresses/data have been sent to the memory interface, the write is aborted and it is
as it had never happened: the read is accepted and the value is sent to the master.
Write while another write operation is ongoing
If the master requests a write operation while another one is ongoing, there are different
cases:
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•
If the previous write uses a Single programming operation or a Multiple programming
operation (half page) and all addresses/data have been sent to the memory interface,
and if the new write is in a protected area, the WRPERR flag is raised, the previous
write continues and the new write is deleted.
•
If the previous write uses a Single programming operation or a Multiple programming
operation (half page) and all addresses/data have been sent to the memory interface,
and if the new Single programming operation or Multiple programming operation (half
page) is not in a protected area, the new write is put on hold and will be executed when
the first write operation is complete. It is important to emphasize that the master who
requested the second write is blocked until the first write completes and the second has
stored the address and data internally.
•
It is forbidden to request a new write when a mass erase is ongoing: during all the
steps of the mass erase, the data is not stored internally and the new data can change
the value stored as a protection, adding unwanted protections.
•
It is possible to change configurations to prepare a new write operation when the first
operation uses a Single programming operation or a Multiple programming operation
(half page) and all addresses/data have been sent to the memory interface.
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3.6.3
Flash program memory and data EEPROM (FLASH)
Change the number of wait states while reading
To change the number of wait states, it is necessary to write to the FLASH_ACR register.
The read/write of a register uses a different interface than the memory read/write. The
number of wait states cannot be changed while the memory interface is reading and the
memory interface cannot be stopped if a request is sent to the register interface. For this
reason, while a master is reading the memory and another master changes the wait state
number, the register interface will be locked until the change takes effect (until the readings
stop). To stop the master which is changing the number of wait states, it is important to read
back the content of the FLASH_ACR register: it is not possible to know the number of clock
cycles that will be necessary to change the number of wait states as it depends on the
customer code.
3.6.4
Power-down
To put the NVM in power-down, it is necessary to execute an unlocking sequence.
The following sequence is used to unlock RUN_PD bit of the FLASH_ACR register:
•
Write PDKEY1 = 0x04152637 to the FLASH_PDKEYR register.
•
Write PEKEY2 = 0xFAFBFCFD to the FLASH_PDKEYR register.
It is necessary to write the two keys without constraints about other read or write. No error is
generated if the wrong key is used: when both have been written, RUN_PD bit is unlocked
and can be written to 1, putting the NVM in power-down mode.
Resetting the RUN_PD flag to 0 (making the NVM available) automatically resets the
sequence and the two keys are requested to re-enable RUN_PD.
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RM0376
Flash register description
Read registers
To read all internal registers of the memory interface, the user must read at the register
addresses. The content is available immediately (no wait state is necessary to read
registers). If the user tries to read the FLASH_ACR register after modifying the number of
wait states, the content will be available when the change takes effect (when no read is
done in the NVM memory, so the number of wait states is changed).
When no register is selected or when a wrong address is sent to the memory interface, a
zero value is sent as an answer. No error is generated.
When the master sends a request to read 8 or 16 bits, the memory interface returns the
corresponding part of the register on the data output bus. For example, if a register content
is 0x12345678 and the master sends a request to read the second byte, the output will be
0x34343434 (because 0x34 is the content of the second register byte when starting to count
bytes from zero). Similarly, if the master sends a request to read half-word zero of the
previous register, the output will be 0x56785678.
Write to registers
In the configuration registers of the memory interface, there are two types of bits:
•
the bits that can be written to directly
•
the bits needing a particular sequence to unlock.
To know which category a bit belongs to, see the next sections where every bit is explained
in details.
When it is possible to write directly to a register or a key-register, the user must write the
expected value at the register address. If the address is not correct, no error is generated. If
the user tries to modify a read-only register, no error is generated and the modify operation
does not take any effect. It is possible to write registers by byte, half-word and word.
When an unlock sequence is necessary, the correct values to use are given.
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Flash program memory and data EEPROM (FLASH)
3.7.1
Access control register (FLASH_ACR)
Address offset: 0x00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PRE_READ
DISAB_BUF
RUN_PD
SLEEP_PD
Res.
PRFTEN
LATENCY
Reset value: 0x0000 0000
rw
rw
rw
rw
rw
rw
Bits 31:7 Reserved
Bit 6 PRE_READ
This bit enables the pre-read.
0: The pre-read is disabled
1: The pre-read is enabled. The memory interface stores the last address read as data and
tries to read the next one when no other read or write or prefetch operation is ongoing.
Note: It is automatically reset every time the DISAB_BUF bit (in this register) is set to 1.
Bit 5 DISAB_BUF
This bit disables the buffers used as a cache during a read. This means that every read will
access the NVM even for an address already read (for example, the previous address). When
this bit is reset, the PRFTEN and PRE_READ bits are automatically reset, too.
0: The buffers are enabled
1: The buffers are disabled. Every time one NVM value is necessary, one new memory read
sequence has do be done.
Bit 4 RUN_PD
This bit determines if the NVM is in power-down mode or in idle mode when the device is in run
mode. It is possible to write this bit only when there is an unlocked writing of the
FLASH_PDKEYR register.
The correct sequence is explained in Section 3.6.4: Power-down. When writing this bit to 0, the
keys are automatically lost and a new unlock sequence is necessary to re-write it to 1.
0: When the device is in Run mode, the NVM is in Idle mode.
1: When the device is in Run mode, the NVM is in power-down mode.
Bit 3 SLEEP_PD
This bit allows to have the Flash program memory and data EEPROM in power-down mode or
in idle mode when the device is in SLEEP mode.
0: When the device is in SLEEP mode, the NVM is in Idle mode.
1: When the device is in SLEEP mode, the NVM is in power-down mode.
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RM0376
Bit 2 Reserved
Bit 1 PRFTEN
This bit enables the prefetch. It is automatically reset every time the DISAB_BUF bit (in this
register) is set to 1. To know how the prefetch works, see the Fetch and prefetch section.
0: The prefetch is disabled.
1: The prefetch is enabled. The memory interface stores the last address fetched and tries to
read the next one when no other read or write operation is ongoing.
Bit 0 LATENCY
The value of this bit specifies if a 0 or 1 wait-state is necessary to read the NVM. The user must
write the correct value relative to the core frequency and the operation mode (power). The
correct value to use can be found in Table 6. No check is done to verify if the configuration is
correct.
To increase the clock frequency, the user has to change this bit to ‘1’, then to increase the
frequency. To reduce the clock frequency, the user has to decrease the frequency, then to
change this bit to ‘0’.
0: Zero wait state is used to read a word in the NVM.
1: One wait state is used to read a word in the NVM.
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Flash program memory and data EEPROM (FLASH)
3.7.2
Program and erase control register (FLASH_PECR)
Address offset: 0x04
Reset value: 0x0000 0007
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OBL_LAUNCH
ERRIE
EOPIE
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
FPRG
ERASE
FIX
Res.
Res.
Res.
DATA
PROG
OPT_LOCK
PRG_LOCK
PE_LOCK
This register can only be written after a good write sequence done in FLASH_PEKEYR,
resetting the PELOCK bit.
rw
rw
rw
rw
rw
rs
rs
rs
Bits 31:19 Reserved.
Bit 18 OBL_LAUNCH
Setting this bit, the software requests the reloading of Option byte. The Option byte reloading
does not stop an ongoing modify operation, but it blocks new ones. The Option byte reloading
generates a system reset.
0: Option byte loading completed.
1: Option byte loading to be done.
Note: This bit can only be modified when OPTLOCK is 0. Locking OPTLOCK (or other lock
bits) does not reset this bit.
Bit 17 ERRIE: Error interrupt enable
0: Error interrupt disable.
1: Error interrupt enable.
Note: This bit can only be modified when PELOCK is 0. Locking PELOCK does not reset this
bit; the interrupt remains enabled.
Bit 16 EOPIE: End of programming interrupt enable
0: End of program interrupt disable.
1: End of program interrupt enable.
Note: This bit can only be modified when PELOCK is 0. Locking PELOCK does not reset this
bit; the interrupt remains enabled.
Bits 15:11 Reserved
Bit 10 FPRG: Half Page programming mode
0: Half Page programming disabled.
1: Half Page programming enabled.
Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.
Bit 9 ERASE
0: No erase operation requested.
1: Erase operation requested.
Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.
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RM0376
Bit 8 FIX
0: An erase phase is automatically performed, when necessary, before a program operation
in the data EEPROM and the Option bytes areas. The programming time can be:
Tprog (program operation) or 2 * Tprog (erase + program operations).
1: The program operation is always performed with a preliminary erase and the
programming time is: 2 * Tprog.
Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.
Bits 5:7
Reserved
Bit 4 DATA
0: Data EEPROM not selected.
1: Data memory selected.
Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.This bit is
not very useful as the page and word have the same size in the data EEPROM, but it is
used to identify an erase operation (by page) from a word operation.
Bit 3 PROG
This bit is used for half-page program operations and for page erase operations in the Flash
program memory.
0: The Flash program memory is not selected.
1: The Flash program memory is selected.
Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.
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Bit 2 OPTLOCK: Option bytes lock
This bit blocks the write/erase operations to the user Option bytes area and the
OBL_LAUNCH bit (in this register). It can only be written to 1 to re-lock. To reset to 0, a correct
sequence of unlock with OPTKEYR register is necessary (see Unlocking the Option btyes
area), with PELOCK bit at 0. If the sequence is not correct, the bit will be locked until the next
system reset and a bus error is generated. If the sequence is executed when PELOCK = 1,
the bit remains locked and no bus error is generated. The keys to unlock are:
– First key:0xFBEAD9C8
– Second key: 0x24252627
0: The write and erase operations in the Option bytes area are disabled.
1: The write and erase operations in the Option bytes area are enabled.
Note: This bit is set when PELOCK is set.
Bit 1 PRGLOCK: Program memory lock
This bit blocks the write/erase operations to the Flash program memory. It can only be written
to 1 to re-lock. To reset to 0, a correct sequence of unlock with PRGKEYR register is
necessary (see Unlocking the Flash program memory), with PELOCK bit at 0. If the sequence
is not correct, the bit will be locked until the next system reset and a bus error is generated. If
the sequence is executed when PELOCK = 1, the bit remains locked and no bus error is
generated. The keys to unlock are:
– First key:0x8C9DAEBF
– Second key: 0x13141516
0: The write and erase operations in the Flash program memory are disabled.
1: The write and erase operations in the Flash program memory are enabled.
Note: This bit is set when PELOCK is set.
Bit 0 PELOCK: FLASH_PECR lock
This bit locks the FLASH_PECR register. It can only be written to 1 to re-lock. To reset to 0, a
correct sequence of unlock with PEKEYR register (see Unlocking the data EEPROM and the
FLASH_PECR register) is necessary. If the sequence is not correct, the bit will be locked until
the next system reset and one bus error is generated. The keys to unlock are:
– First key: 0x89ABCDEF
– Second key: 0x02030405
0: The FLASH_PECR register is unlocked; it can be modified and the other bits unlocked.
Data write/erase operations are enabled.
1: The FLASH_PECR register is locked and no write/erase operation can start.
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3.7.3
RM0376
Power-down key register (FLASH_PDKEYR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FLASH_PDKEYR[31:16]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
FLASH_PDKEYR15:0]
Bits 31:0
3.7.4
w
w
This is a write-only register. With a sequence of two write operations (the first one with
0x04152637 and the second one with 0xFAFBFCFD), the write size being that of a word, it is
possible to unlock the RUN_PD bit of the FLASH_ACR register. For more details, refer to
Section 3.6.4: Power-down.
PECR unlock key register (FLASH_PEKEYR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
w
w
w
w
w
w
w
w
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
FLASH_PEKEYR[31:16]
FLASH_PEKEYR15:0]
w
w
w
w
w
w
w
w
w
Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with
0x89ABCDEF and the second one with 0x02030405), the write size being that of a word, it is
possible to unlock the FLASH_PECR register. For more details, refer to Unlocking the data
EEPROM and the FLASH_PECR register.
3.7.5
Program and erase key register (FLASH_PRGKEYR)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FLASH_PRGKEYR[31:16]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
FLASH_PRGKEYR15:0]
w
w
w
w
w
w
w
w
w
Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with
0x8C9DAEBF and the second one with 0x13141516), the write size being that of a word, it is
possible to unlock the Flash program memory. The sequence can only be executed when
PELOCK is already unlocked. For more details, refer to Unlocking the Flash program memory.
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Flash program memory and data EEPROM (FLASH)
3.7.6
Option bytes unlock key register (FLASH_OPTKEYR)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FLASH_OPTKEYR[31:16]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
FLASH_OPTKEYR[15:0]
w
w
Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with
0xFBEAD9C8 and the second one with 0x24252627), the write size being that of a word, it is
possible to unlock the Option bytes area and the OBL_LAUNCH bit. The sequence can only be
executed when PELOCK is already unlocked. For more details, refer to Unlocking the Option
btyes area.
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3.7.7
RM0376
Status register (FLASH_SR)
Address offset: 0x018
26
25
24
23
22
21
20
19
18
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
Res.
Res.
OPTVERR
SIZERR
PGAERR
WRPERR
Res.
Res.
Res.
Res.
READY
rc_w1
rc_w1
rc_w1
rc_w1
r
rc_w1
17
16
NOTZERO
ERR
27
rc_w1
rc_w1
1
0
BSY
28
FWWER
29
EOP
30
HWOFF
31
RDERR
Reset value: 0x0000 000C
r
rc_w1
r
Bits 31:18 Reserved
Bit 17 FWWERR
This bit is set by hardware when a write/erase operation is aborted to perform a fetch. This is
not a real error, but it is used to inform that the write/erase operation did not execute. To reset
this flag, write 1.
0: No write/erase operation aborted to perform a fetch.
1: A write/erase operation aborted to perform a fetch.
Bit 16 NOTZEROERR
This bit is set by hardware when a program in the Flash program or System Memory tries to
overwrite a not-zero area. This flag does not stop the program operation: it is possible that the
value found when reading back is not what the user wrote. To reset this flag, write 1.
0: The write operation is done in an erased region or the memory interface can apply an
erase before a write.
1: The write operation is done in a not-erased region and the memory interface cannot apply
an erase before a write.
Bit 15:14 Reserved
Bit 13 RDERR
This bit is set by hardware when the user tries to read an area protected by PcROP. It is
cleared by writing 1.
0: No read protection error happened.
1: One read protection error happened.
Bit 12 Reserved
Bit 11 OPTVERR: Option valid error
This bit is set by hardware when, during an Option byte loading, there was a mismatch for one
or more configurations. It means that the configurations loaded may be different from what the
user wrote in the memory. It is cleared by writing 1.
If an error happens while loading the protections (WPRMOD, RDPROT, WRPROT), the source
code in the Flash program memory may not execute correctly.
0: No error happened during the Option bytes loading.
1: One or more errors happened during the Option bytes loading.
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Bit 10 SIZERR: Size error
This bit is set by hardware when the size of data to program is not correct. It is cleared by
writing 1.
0: No size error happened.
1: One size error happened.
Bit 9 PGAERR: Programming alignment error
This bit is set by hardware when an alignment error has happened: the first word of a half-page
operation is not aligned to a half-page, or one of the following words in a half-page operation
does not belong to the same half-page as the first word. When this bit is set, it has to be
cleared before writing 1, and no half-page operation is accepted.
0: No alignment error happened.
1: One alignment error happened.
Bit 8 WRPERR: Write protection error
This bit is set by hardware when an address to be programmed or erased is write-protected. It
is cleared by writing 1.
0: No protection error happened.
1: One protection error happened.
Bit 7:4 Reserved
Bit 3 READY
When this bit is set, the NVM is ready for read and write/erase operations.
0: The NVM is not ready. No read or write/erase operation can be done.
1: The NVM is not ready.
Bit 2 HVOFF
This bit is set and reset by hardware.
0: High voltage is executing a write/erase operation in the NVM.
1: High voltage is off, no write/erase operation is ongoing.
Bit 1 EOP: End of program
This bit is set by hardware at the end of a write or erase operation when the operation has not
been aborted. It is reset by software (writing 1).
0: No EOP operation occurred
1: An EOP event occurred. An interrupt is generated if EOPIE bit is set.
Bit 0 BSY: Memory interface busy
Write/erase operations are in progress.
0: No write/erase operation is in progress.
1: A write/erase operation is in progress.
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3.7.8
RM0376
Option bytes register (FLASH_OPTR)
Address offset 0x1C
27
26
25
24
23
22
21
20
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WPRMOD
r
17
16
r
r
r
r
r
r
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
RDPROT
14
18
r
r
15
19
BOR_LEV[3:0]
28
WDG_SW
29
nRTS_STOP
30
nRST_STDBY
31
BOOT1
Reset value: 0xX0XX 0XXX
Bit 31 BOOT1
Together with input pad Boot0, this bit selects the boot source:
– If BOOT0 = 0 and BOOT1 = X, then the boot is in the Flash program memory.
– If BOOT0 = 1 and BOOT1 = 0, then the boot is in the RAM memory.
– If BOOT0 = 1 and BOOT1 = 1, then the boot is in the System memory.
This bit is read-only: to change boot sources, an Option bytes reloading is necessary. If there is
a mismatch on this configuration during the Option bytes loading, it is loaded with 1.
If the device is protected at Level 2, Boot0 and Boot1 lose their meaning: the boot is always
forced in the Flash program memory.
Bit 30:23 Reserved
Bit 22 nRST_STDBY
This bit is read-only. If there is a mismatch on this configuration during the Option bytes
loading, it is loaded with 1.
0: Reset generated when entering the standby mode.
1: No reset generated.
Bit 21 nRST_STOP
This bit is read-only. If there is a mismatch on this configuration during the Option bytes
loading, it is loaded with 1.
0: Reset generated when entering the stop mode.
1: No reset generated.
Bit 20 WDG_SW
This bit is read-only. If there is a mismatch on this configuration during the Option bytes
loading, it is loaded with 1.
0: Hardware watchdog.
1: Software watchdog.
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Bit 19:16 BOR_LEV: Brown out reset threshold level
These bits reset the threshold level for a 1.45 V to 1.55 V voltage range (power-down only). In
this particular case, VDD33 must have been above BOR LEVEL 0 to start the device OBL
sequence, in order to disable the BOR. The power-down is then monitored by the PDR. If the
BOR is disabled, a “grey zone” exists between 1.65 V and the VPDR threshold (this means
VDD33 can be below the minimum operating voltage (1.65 V) without any reset until the VPDR
threshold).
These bits are read-only. If there is a mismatch on this configuration during the Option bytes
loading, it is loaded with 0x8.
1000: BOR LEVEL 0 is the reset threshold level for a 1.69 V to 1.8 V voltage range
(power on).
1001: BOR LEVEL 1 is the reset threshold level for a1.94 V to 2.1 V voltage range
(power on).
1010: BOR LEVEL 2 is the reset threshold level for a 2.3 V to 2.49 V voltage range
(power on).
1011: BOR LEVEL 3 is the reset threshold level for a 2.54 V to 2.74 V voltage range
(power on).
1100: BOR LEVEL 4 is the reset threshold level for a 2.77 V to 3.0 V voltage range
(power on).
Bit 15:9 Reserved
Bit 8 WPRMOD
This bit selects between write and read protection of Flash program memory sectors. This bit is
read-only. If there is a mismatch on this configuration during the Option bytes loading, it is
loaded with 1.
0: PCROP disabled. The WRPROT bits are used as a write protection on a sector.
1: PCROP enabled. The WRPROT bits are used as a read protection on a sector.
Bits 7:0 RDPROT: Read protection
These bits contain the protection level loaded during the Option byte loading. These bits are
read-only. If there is a mismatch on this configuration during the Option bytes loading, it is
loaded with 0x00.
0xAA: Level 0
0xCC: Level 2
Others: Level 1
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3.7.9
RM0376
Write protection register (FLASH_WRPROT)
Address offset: 0x20
Reset value: 0x0000 XXXX
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
WRPROT[15:0]
r
r
Bit 31:16 Reserved
Bits 15:0 WRPROT: Write protection
– If WPRMOD = 0 in the FLASH_OPTR register, these bits contain the write protection
configuration for the Flash memory (every bit protects a 16-Kbyte sector: the first bit
protects the first sector, the second bit protects the second page and so on). In this case,
1 = sector protected, 0 = no protection.
– If WPRMOD = 1, these bits are used to protect from reading as data (see Read as data and
pre-read), and then also from writing, with the same granularity and with the same
combination of bits and sectors. The read protection does not protect against a fetch. In this
case, 1 = no protection, 0 = sector protected.
When WPRMOD = 0, it is possible to set or reset these bits without any limitation changing
the relative Option bytes.
When WPRMOD = 1, it is only possible to increase the protection, which means that the user
can add zeros but cannot add ones.
The mass erase deletes the WPRMOD bits but does not delete the content of this register.
After a mass erase, the user must write the relative Option bytes with zeros to remove
completely the write protections.
If there is a mismatch on this configuration during the Option bytes loading, and the content of
WPRMOD in the FLASH_OPTR register is:
1, this configuration is loaded with 0x0000.
0, this configuration is loaded with 0xFFFF.
If there was a mismatch when WPRMOD was loaded in the FLASH_OPTR register (thus
loaded with ones), the register is loaded with 0x0000.
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3.7.10
Flash program memory and data EEPROM (FLASH)
Flash register map
0
0
0
0
0
0
0
0
0
0
0
0
0
LATENCY
PELOCK
Res.
PRFTEN
OPTLOCK
0
PRGLOCK
RUN_PD
SLEEP_PD
0
PRG
DESAB_8BUF
Res.
Res.
0
DATA
FIX
PRE_READ
ERASE
Res.
FPRG
Res.
Res.
Res.
Res.
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PKEYR[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PRGKEYR[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLASH_
OPTKEYR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLASH_SR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FWWERR
NOTZEROERR
Res.
Res.
RDERR
Res.
Res.
Res.
Res.
Res.
READY
0
0
1
X
X
X
X
Res.
Res.
Res.
Res.
Res.
Res.
0x0000XXXX
0
0
0
0
X
1
0
0
X X X X
X
X
X X X X
X
X
RDPROT[7:0]
X
X
WRPROT[15:0]
X
DocID025941 Rev 1
Res.
WDG_SW
X
Res.
nRST_STOP
X
BOR_LEV:0]
Res.
nRST_STBY
X
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
X
FLASH_
WRPROT
Res.
BOOT1
0xX0XX0XXX
Res.
FLASH_OPTR
0
BSY
0
EOP
0
HWOFF
0
WRPERR
0
WPRMOD
0
PGAERR
0
Res.
0
SIZERR
0
Res.
0
OPTVERR
0
Res.
0x00000000
Res.
OPTKEYR[31:0]
Res.
0x020
Res.
EOPIE
0
0x0000000C
0x01C
0
0
Res.
0x018
0
0
PDKEYR[31:0]
FLASH_
PRGKEYR
0x00000000
0x014
0
FLASH_
PKEYR
0x00000000
0x010
0
FLASH_
PDKEYR
0x00000000
0x00C
0
Res.
0x008
ERRIE
0x00000007
OBL_LAUNCH
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FLASH_PECR
Res.
0x004
Res.
0x00000000
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FLASH_ACR
Res.
0x00
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 16. Flash interface - register map and reset values
X
X
X
X
X
X
X
X
X
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Flash program memory and data EEPROM (FLASH)
3.8
RM0376
Option bytes
On the NVM, a part is reserved to store a set of Option bytes. This information is used to
configure the product. A part is written in factory and another part is under control of the end
user.
The configuration managed by an end user is in the Option bytes area (32 bytes). The first
12 bytes (3 words) are automatically loaded during the boot and are used to set the content
of the FLASH_OPTR and FLASH_WRPROT registers.
Every word, when read during the boot, is interpreted as in Table 17: the lower 16 bits
contain the data to copy in the memory interface registers and the higher 16 bits contain the
complemented value, used to check that what is read is correct. If there is an error during
loading (the higher part is not the complement of the lower one), the default value is stored
in the registers. The check is done by configuration. Section 3.8.2 explains what happens
when there is a mismatch on protection configurations.
During a write, no control is done to check if the higher part of a word is the complement of
the lower part; the user must control it.
Table 17. Option byte format
3.8.1
31-24
23-16
15-8
7-0
Complemented
Option byte 1
Complemented
Option byte 0
Option byte 1
Option byte 0
Option bytes description
The Option bytes can be read from the memory locations listed in Table 18.
Table 18. Option byte organization
3.8.2
Address
[31:16]
[15:0]
0x1FF8 0000
nFLASH_OPTR[15:0]
FLASH_OPTR[15:0]
0x1FF8 0004
nFLASH_OPTR[31:16]
FLASH_OPTR[31:16]
0x1FF8 0008
nFLASH_WRPROT[15:0]
FLASH_WRPROT[15:0]
Mismatch when loading protection flags
When there is a mismatch during an Option byte loading, the memory interface sets the
default value in registers.
In the Option byte area, there are three kinds of protection information:
•
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RDPROT
This configuration sets the Protection Level. As explained in the next section, changing
this level changes the possibility to access the NVM and the product. The default value
is Level 1. It is possible to return to Level 0 from Level 1 but all content of the data
EEPROM and Flash program memory will be deleted (mass erase). It is always
possible to move to Level 2, but not to change protection levels when Level 2 is loaded
(if the user writes in Option bytes a Level 2 but never reloads the Option bytes, the
DocID025941 Rev 1
RM0376
Flash program memory and data EEPROM (FLASH)
memory interface continues to works in the previous level and it is possible to write
again a different protection level in the Option bytes area).
•
WPRMOD
This flag is independent from RDPROT and set if the Flash program memory is
protected from read or write. When this flag is 1 (read protection), the only way to reset
it is to request a mass erase (also returning to Level 0). This means that there is no
way to remove the read protection when the device is in Level 2. The default value is 1
(read protection) and a mismatch on this bit also generates the default value for the
WRPROT configuration.
•
WRPROT
This configuration sets which sectors of the Flash program memory are read- or writeprotected. If the read protection is disabled (WPRMOD = 0), 1 must be set in the right
bit to protect a sector. If the read protection is enabled (WPRMOD = 1), 0 must be in
the right bit to protect a sector. If during boot there is a mismatch on WPRMOD, this
configuration is loaded with zeros so that all sectors of the Flash program memory are
protected from read. If WPRMOD has been read correctly but there is a mismatch
reading WRPROT, the register will be loaded with zeros if WPRMOD = 1, and with
ones if WPRMOD = 0.
Thus, a mismatch on a protection can have a serious impact on the normal execution of
code (if it is in the Flash program memory): when there is a read protection, only a fetch is
possible. In the Flash program memory, some values are read as data (the constants, for
example) during a code execution; protecting all sectors from read prevents the execution of
the application code from the Flash program memory.
3.8.3
Reloading Option bytes by software
It is possible to request an Option byte reloading by setting the OBL_LAUNCH flag to 1 in
the FLASH_PECR register. This bit can be set only when OPTLOCK = 0 (and PELOCK =
0). Setting this bit, the ongoing write/erase is completed, but no new write/erase or read
operation is executed.
The reload of Option bytes generates a reset of the device but without a power-down. The
options must be reloaded after every change of the Option bytes in the NVM, so that the
changes can apply. It is possible to reload by setting OBL_LAUNCH, or with a power-on of
the V18 domain (i.e. after a power-on reset or after a standby).
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Cyclic redundancy check calculation unit (CRC)
4
Cyclic redundancy check calculation unit (CRC)
4.1
Introduction
RM0376
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16or 32-bit data word and a generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the functional safety standards, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.
4.2
CRC main features
•
Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1
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•
Alternatively uses a fully programmable polynomial with programmable size (7, 8, 16,
32 bits).
•
Handles 8-,16-, 32-bit data size
•
Programmable CRC initial value
•
Single input/output 32-bit data register
•
Input buffer to avoid bus stall during calculation
•
CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size
•
General-purpose 8-bit register (can be used for temporary storage)
•
Reversibility option on I/O data
DocID025941 Rev 1
RM0376
4.3
Cyclic redundancy check calculation unit (CRC)
CRC functional description
Figure 7. CRC calculation unit block diagram
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The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to
input new data (write access), and holds the result of the previous CRC calculation (read
access).
Each write operation to the data register creates a combination of the previous CRC value
(stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data
word or byte by byte depending on the format of the data being written.
The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned
byte. For the other registers only 32-bit access is allowed.
The duration of the computation depends on data width:
•
4 AHB clock cycles for 32-bit
•
2 AHB clock cycles for 16-bit
•
1 AHB clock cycles for 8-bit
An input buffer allows to immediately write a second data without waiting for any wait states
due to the previous CRC calculation.
The data size can be dynamically adjusted to minimize the number of write accesses for a
given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write
followed by a byte write.
The input data can be reversed, to manage the various endianness schemes. The reversing
operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits
in the CRC_CR register.
For example: input data 0x1A2B3C4D is used for CRC calculation as:
0x58D43CB2 with bit-reversal done by byte
0xD458B23C with bit-reversal done by half-word
0xB23CD458 with bit-reversal done on the full word
The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.
The operation is done at bit level: for example, output data 0x11223344 is converted into
0x22CC4488.
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Cyclic redundancy check calculation unit (CRC)
RM0376
The CRC calculator can be initialized to a programmable value using the RESET control bit
in the CRC_CR register (the default value is 0xFFFFFFFF).
The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR
register is automatically initialized upon CRC_INIT register write access.
The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It
is not affected by the RESET bit in the CRC_CR register.
Polynomial programmability
The polynomial coefficients are fully programmable through the CRC_POL register, and the
polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the
POLYSIZE[1:0] bits in the CRC_CR register.
If the CRC data is less than 32-bit, its value can be read from the least significant bits of the
CRC_DR register.
To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can
not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the
application must either reset it or perform a CRC_DR read before changing the polynomial.
The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7.
4.4
CRC registers
4.4.1
Data register (CRC_DR)
Address offset: 0x00
Reset value: 0xFFFF FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
DR[31:16]
rw
15
14
13
12
11
10
9
8
7
DR[15:0]
rw
Bits 31:0 DR[31:0]: Data register bits
This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.
If the data size is less than 32 bits, the least significant bits are used to write/read the
correct value.
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Cyclic redundancy check calculation unit (CRC)
4.4.2
Independent data register (CRC_IDR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
IDR[7:0]
rw
Bits 31:8 Reserved, must be kept cleared.
Bits 7:0 IDR[7:0]: General-purpose 8-bit data register bits
These bits can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register
4.4.3
Control register (CRC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
REV_
OUT
Res.
Res.
RESET
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
REV_IN[1:0]
rw
rw
POLYSIZE[1:0]
rw
rw
rs
Bits 31:8 Reserved, must be kept cleared.
Bit 7 REV_OUT: Reverse output data
This bit controls the reversal of the bit order of the output data.
0: Bit order not affected
1: Bit-reversed output format
Bits 6:5 REV_IN[1:0]: Reverse input data
These bits control the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word
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Cyclic redundancy check calculation unit (CRC)
RM0376
Bits 4:3 POLYSIZE[1:0]: Polynomial size
These bits control the size of the polynomial.
00: 32 bit polynomial
01: 16 bit polynomial
10: 8 bit polynomial
11: 7 bit polynomial
Bits 2:1 Reserved, must be kept cleared.
Bit 0 RESET: RESET bit
This bit is set by software to reset the CRC calculation unit and set the data register to the value stored
in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware
4.4.4
Initial CRC value (CRC_INIT)
Address offset: 0x10
Reset value: 0xFFFF FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
22
21
20
19
18
17
16
6
5
4
3
2
1
0
CRC_INIT[31:16]
rw
15
14
13
12
11
10
9
8
7
CRC_INI[15:0]
rw
Bits 31:0 CRC_INIT: Programmable initial CRC value
This register is used to write the CRC initial value.
4.4.5
CRC polynomial (CRC_POL)
Address offset: 0x14
Reset value: 0x04C11DB7
31
30
29
28
27
26
25
24
23
POL[31:16]
rw
15
14
13
12
11
10
9
8
7
POL[15:0]
rw
Bits 31:0 POL[31:0]: Programmable polynomial
This register is used to write the coefficients of the polynomial to be used for CRC calculation.
If the polynomial size is less than 32-bits, the least significant bits have to be used to program the
correct value.
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4.4.6
Cyclic redundancy check calculation unit (CRC)
CRC register map
Offset
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 19. CRC register map and reset values
CRC_DR
DR[31:0]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CRC_IDR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRC_CR
0
Res.
0x08
Reset value
0x10
CRC_INIT
Reset value
0x14
1
1
1
1
1
1
1
0
0
0
IDR[7:0]
REV_OUT
0x04
1
Res.
1
RESET
1
0
0
0
0
Res.
1
POLYSIZE[1:0]
1
REV_IN[1:0]
Reset value
Res.
0x00
0
0
0
0
0
1
1
1
1
1
0
CRC_INIT[31:0]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CRC_POL
Polynomial coefficients
Reset value
0x04C11DB7
1
1
1
1
1
1
1
1
Refer to Section 2.2.2 for the register boundary addresses.
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Firewall (FW)
RM0376
5
Firewall (FW)
5.1
Introduction
The Firewall is made to protect a specific part of code or data into the Non-Volatile Memory,
and/or to protect the Volatile data into the SRAM from the rest of the code executed outside
the protected area.
5.2
Firewall main features
•
•
The code to protect by the Firewall (Code Segment) may be located in:
–
The Flash program memory map
–
The SRAM memory, if declared as an executable protected area during the
Firewall configuration step.
The data to protect can be located either
–
in the Flash program or the Data EEPROM memory (non-volatile data segment)
–
in the SRAM memory (volatile data segment)
The software can access these protected areas once the Firewall is opened. The Firewall
can be opened or closed using a mechanism based on “call gate” (Refer to Opening the
Firewall).
The start address of each segment and its respective length must be configured before
enabling the Firewall (Refer to Section 5.3.5: Firewall initialization).
Each illegal access into these protected segments (if the Firewall is enabled) generates a
reset which immediately kills the detected intrusion.
Any DMA access to protected segments is forbidden whatever the Firewall state (opened or
closed). It is considered as an illegal access and generates a reset.
5.3
Firewall functional description
5.3.1
Firewall AMBA bus snoop
The Firewall peripheral is snooping the AMBA buses on which the memories (volatile and
non-volatile) are connected. A global architecture view is illustrated in Figure 8.
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RM0376
Firewall (FW)
Figure 8. STM32L0x2 firewall connection schematics
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5.3.2
Functional requirements
There are several requirements to guaranty the highest security level by the application
code/data which needs to be protected by the Firewall and to avoid unwanted Firewall alarm
(reset generation).
Debug consideration
In debug mode, if the Firewall is opened, the accesses by the debugger to the protected
segments are not blocked. For this reason, the Read out level 2 protection must be active in
conjunction with the Firewall implementation.
If the debug is needed, it is possible to proceed in the following way:
•
A dummy code having the same API as the protected code may be developed during
the development phase of the final user code. This dummy code may send back
coherent answers (in terms of function and potentially timing if needed), as the
protected code should do in production phase.
•
In the development phase, the protected code can be given to the customer-end under
NDA agreement and its software can be developed in level 0 protection. The customerend code needs to embed an IAP located in a write protected segment in order to allow
future code updates when the production parts will be Level 2 ROP.
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Firewall (FW)
RM0376
Write protection
In order to offer a maximum security level, the following points need to be respected:
•
It is mandatory to keep a write protection on the part of the code enabling the Firewall.
This activation code should be located outside the segments protected by the Firewall.
•
The write protection is also mandatory on the code segment protected by the Firewall.
•
The sector including the reset vector must be write-protected.
Interruptions management
The code protected by the Firewall must not be interruptible. It is up to the user code to
disable any interrupt source before executing the code protected by the Firewall. If this
constraint is not respected, if an interruption comes while the protected code is executed
(Firewall opened), the Firewall will be closed as soon as the interrupt subroutine is
executed. When the code returns back to the protected code area, a Firewall alarm will raise
since the “call gate” sequence will not be applied and a reset will be generated.
Concerning the interrupt vectors and the first user sector in the Flash program memory:
•
If the first user sector (including the reset vector) is protected by the Firewall, the NVIC
vector should be reprogrammed outside the protected segment.
•
If the first user sector is not protected by the Firewall, the interrupt vectors may be kept
at this location.
There is no interruption generated by the Firewall.
5.3.3
Firewall segments
The Firewall has been designed to protect three different segment areas:
Code segment
This segment is located into the Flash program memory. It should contain the code to
execute which requires the Firewall protection. The segment must be reached using the
“call gate” entry sequence to open the Firewall. A system reset is generated if the “call gate”
entry sequence is not respected (refer to Opening the Firewall) and if the Firewall is enabled
using the FWDIS bit in the system configuration register. The length of the segment and the
segment base address must be configured before enabling the Firewall (refer to
Section 5.3.5: Firewall initialization).
Non-volatile data segment
This segment contains non-volatile data used by the protected code which must be
protected by the Firewall. The access to this segment is defined into Section 5.3.4: Segment
accesses and properties. The Firewall must be opened before accessing the data in this
area. The Non-Volatile data segment should be located into the Flash program or 2-Kbyte
Data EEPROM memory. The segment length and the base address of the segment must be
configured before enabling the Firewall (refer to Section 5.3.5: Firewall initialization).
Volatile data segment
Volatile data used by the protected code located into the code segment must be defined into
the SRAM memory. The access to this segment is defined into the Section 5.3.4: Segment
accesses and properties. Depending on the Volatile data segment configuration, the
Firewall must be opened or not before accessing this segment area. The segment length
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Firewall (FW)
and the base address of the segment as well as the segment options must be configured
before enabling the Firewall (refer to Section 5.3.5: Firewall initialization).
The Volatile data segment can also be defined as executable (for the code execution) or
shared using two bit of the Firewall configuration register (bit VDS for the volatile data
sharing option and bit VDE for the volatile data execution capability). For more details, refer
to Table 20.
5.3.4
Segment accesses and properties
All DMA accesses to the protected segments are forbidden, whatever the Firewall state, and
generate a system reset.
Segment access depending on the Firewall state
Each of the three segments has specific properties which are presented in Table 20.
Table 20. Segment accesses according to the Firewall state
Firewall opened
access allowed
Segment
Code segment
Non-volatile data
segment
Volatile data
segment
Read and execute
Read and write
Read and Write
Execute if VDE = 1 and
VDS = 0 into the Firewall
configuration register
Firewall closed
access allowed
Firewall disabled
access allowed
No access allowed.
Any access to the segment
(except the “call gate” entry)
generates a system reset
All accesses are allowed
(according to the EEPROM
protection properties in which
the code is located)
No access allowed
All accesses are allowed
(according to the EEPROM
protection properties in which
the code is located)
No access allowed if VDS = 0
and VDE = 0 into the Firewall
configuration register
Read/write/execute accesses
allowed if VDS = 1 (whatever
VDE bit value)
Execute if VDE = 1 and VDS = 0
but with a “call gate” entry to
open the Firewall at first.
All accesses are allowed
The Volatile data segment is a bit different from the two others. The segment can be:
•
Shared (VDS bit in the register)
It means that the area and the data located into this segment can be shared between
the protected code and the user code executed in a non-protected area. The access is
allowed whether the Firewall is opened or closed or disabled.
The VDS bit gets priority over the VDE bit, this last bit value being ignored in such a
case. It means that the Volatile data segment can execute parts of code located there
without any need to open the Firewall before executing the code.
Note:
When the Firewall is closed (and so enabled), if the “call gate” entry is applied on the code
segment and if the code executed from the code segment jumps to the Volatile data
segment declared as shared (without doing a new “call gate” entry sequence), the code is
executed from the Volatile data segment but the Firewall is closed from the branch
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instruction. At the end of the code execution from the Volatile data segment, if the code is
going back to the code segment (for instance a return to function), a system reset will be
generated.
•
Execute
the VDE bit is considered as soon as the VDS bit = 0 in the FW_CR register. If the VDS
bit = 1, refer to the description above on the Volatile data segment sharing. If VDS = 0
and VDE = 1, the Volatile data segment is executable. To avoid a system reset
generation from the Firewall, the “call gate” sequence should be applied on the Volatile
data segment to open the Firewall as an entry point for the code execution.
Segments properties
Each segment has a specific length register to define the segment size to be protected by
the Firewall: CSL register for the Code segment length register, NVDSL for the Non-volatile
data segment length register, and VDSL register for the Volatile data segment length
register. Granularity and area ranges for each of the segments are presented in Table 21.
Table 21. Segment granularity and area ranges
Segment
5.3.5
Granularity
Area range
Code segment
256 bytes
up to 64 Kbytes - 256 bytes
Non-volatile data segment
256 bytes
up to 64 Kbytes - 256 bytes
Volatile data segment
64 bytes
8 Kbytes - 64 bytes
Firewall initialization
The initialization phase should take place at the beginning of the user code execution (refer
to the Write protection).
The initialization phase consists of setting up the addresses and the lengths of each
segment which needs to be protected by the Firewall. It must be done before enabling the
Firewall, because the enabling bit can be written once. Thus, when the Firewall is enabled,
It cannot be disabled anymore until the next system reset.
Once the Firewall is enabled, the accesses to the address and length segments are no
longer possible. All write attempts are discarded.
A segment defined with a length equal to 0 is not considered as protected by the Firewall.
As a consequence, there is no reset generation from the Firewall when an access to the
base address of this segment is performed.
After a reset, the Firewall is disabled by default (FWDIS bit in the SYSCFG register is set). It
has to be cleared to enable the Firewall feature.
Below is the initialization procedure to follow:
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1.
Configure the RCC to enable the clock to the Firewall module
2.
Configure the RCC to enable the clock of the system configuration registers
3.
Set the base address and length of each segment (CSSA, CSL, NVDSSA, NVDSL,
VDSSA, VDSL registers)
4.
Set the configuration register of the Firewall (FW_CR register)
5.
Enable the Firewall clearing the FWDIS bit in the system configuration register.
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Firewall (FW)
The Firewall configuration register (FW_CR register) is the only one which can be managed
in a dynamic way even if the Firewall is enabled. However, this register is protected in the
same way as the Non-volatile data segment. The accesses to this register are only possible
when the Firewall is opened and if the Non-Volatile data segment is defined (meaning the
NVDSL register is different from 0).
5.3.6
Firewall states
The Firewall has three different states as shown in Figure 9:
•
Disabled: The FWDIS bit is set by default after the reset. The Firewall is not active.
•
Closed: The Firewall protects the accesses to the three segments (Code, Non-volatile
data, and Volatile data segments).
•
Opened: The Firewall allows access to the protected segments as defined in
Section 5.3.4: Segment accesses and properties.
Figure 9. Firewall functional states
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Opening the Firewall
As soon as the Firewall is enabled, it is closed. It means that most of the accesses to the
protected segments are forbidden (refer to Section 5.3.4: Segment accesses and
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properties). In order to open the Firewall to interact with the protected segments, it is
mandatory to apply the “call gate” sequence described hereafter.
“call gate” sequence
The “call gate” is composed of 3 words located on the first three 32-bit addresses of the
base address of the code segment and of the Volatile data segment if it is declared as
not shared (VDS = 0) and executable (VDE = 1).
–
1st word: Dummy 32-bit words always closed in order to protect the “call gate”
opening from an access due to a prefetch buffer.
–
2nd and 3rd words: 2 specific 32-bit words called “call gate” and always opened.
To open the Firewall, the code currently executed must jump to the 2nd words of the “call
gate” and execute the code from this point. The 2nd word and 3rd word execution must not
be interrupted by any intermediate instruction fetch; otherwise, the Firewall is not
considered open and comes back to a close state. Then, executing the 3rd words after
having the intermediate instruction fetch would generate a system reset as a consequence.
As soon as the Firewall is opened, the protected segments can be accessed as described in
Section 5.3.4: Segment accesses and properties.
Closing the Firewall
The Firewall is closed immediately after it is enabled (clearing the FWDIS bit in the system
configuration register).
To close the Firewall, the protected code must:
•
Write the correct value in the Firewall Pre Arm Flag into the FW_CR register.
•
Jump to any executable location outside the Firewall segments.
If the Firewall Pre Arm Flag is not set when the protected code jumps to a non protected
segment, a reset is generated. This control bit is an additional protection to avoid an
undesired attempt to close the Firewall with the private information not yet cleaned (see the
note below).
Note:
If VDS = VDE = 1, the Firewall will be closed when the protected code jumps to the Volatile
data segment.
For security reasons, following the application for which the Firewall is used, it is advised to
clean all private information from CPU registers and hardware cells.
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5.4
Firewall registers
5.4.1
Code segment start address (FW_CSSA)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
23
22
21
20
19
18
17
16
ADD[23:16]
rw
15
14
13
12
11
ADD[15:8]
10
9
8
7
6
5
4
3
2
1
0
Res
Res
Res
Res
Res
Res
Res
Res
rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23:8 ADD[23:8]: code segment start address
The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a
256-byte granularity.
Note: These bits can be written only before enabling the Firewall. Refer to Section 5.3.5:
Firewall initialization.
Bits 7:0 Reserved, must be kept at the reset value.
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5.4.2
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Code segment length (FW_CSL)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
21
20
19
18
17
16
LENG[21:16]
rw
15
14
13
12
11
10
9
8
LENG15:8]
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:22 Reserved, must be kept at the reset value.
Bit 21:8 LENG[21:8]: code segment length
LENG[21:8] selects the size of the code segment expressed in bytes but is a multiple of
256 bytes.
The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01
Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not
protected by the Firewall.
These bits can only be written before enabling the Firewall. Refer to Section 5.3.5:
Firewall initialization.
Bit 7:0 Reserved, must be kept at the reset value.
5.4.3
Non-volatile data segment start address (FW_NVDSSA)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
ADD[23:16]
rw
ADD[15:8]
7
6
5
4
3
2
1
0
Res
Res
Res
Res
Res
Res
Res
Res
rw
Bits 31:24 Reserved, must be kept at the reset value.
Bit 23:8 ADD[23:8]: Non-volatile data segment start address
The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a
256-byte granularity.
Note: These bits can only be written before enabling the Firewall. Refer to Section 5.3.5:
Firewall initialization.
Bits 7:0 Reserved, must be kept at the reset value.
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5.4.4
Non-volatile data segment length (FW_NVDSL)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
21
20
19
18
17
16
LENG[21:16]
rw
15
14
13
12
11
10
9
8
LENG[15:8]
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:22 Reserved, must be kept at the reset value.
Bit 21:8 LENG[21:8]: Non-volatile data segment length
LENG[21:8] selects the size of the Non-volatile data segment expressed in bytes but is a
multiple of 256 bytes.
The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01
Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not
protected by the Firewall.
These bits can only be written before enabling the Firewall. Refer to Section 5.3.5:
Firewall initialization.
Bit 7:0 Reserved, must be kept at the reset value.
5.4.5
Volatile data segment start address (FW_VDSSA)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res
Res
Res
Res
Res
Res
ADD[15:6]
rw
Bits 31:16 Reserved, must be kept at the reset value.
Bit 15:6 ADD[15:6]: Volatile data segment start address
The LSB bit of the start address (bits 5:0) are reserved and forced to 0 in order to allow a
64-byte granularity.
Note: These bits can only be written before enabling the Firewall. Refer to Section 5.3.5:
Firewall initialization.
Bits 5:0 Reserved, must be kept at the reset value.
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5.4.6
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Volatile data segment length (FW_VDSL)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
LENG[15:6]
rw
Bits 31:16 Reserved, must be kept at the reset value.
Bit 15:6 LENG[15:6]: Non-volatile data segment length
LENG[15:6] selects the size of the Non-volatile data segment expressed in bytes but is a
multiple of 64 bytes.
The segment area is defined from {ADD[15:6],0x00} to {ADD[15:6]+LENG[15:6], 0x00} - 0x01
Note: If LENG[15:6] = 0 after enabling the Firewall, this segment is not defined, thus not
protected by the Firewall.
These bits can only be written before enabling the Firewall. Refer to Section 5.3.5:
Firewall initialization.
Bit 5:0 Reserved, must be kept at the reset value.
5.4.7
Configuration register (FW_CR)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
VDE
VDS
FPA
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Firewall (FW)
Bits 31:3 Reserved, must be kept at the reset value.
Bit 2 VDE: Volatile data execution
0: Volatile data segment cannot be executed if VDS = 0
1: Volatile data segment is declared executable whatever VDS bit value
When VDS = 1, this bit has no meaning. The Volatile data segment can be executed whatever
the VDE bit value.
If VDS = 1, the code can be executed whatever the Firewall state (opened or closed)
If VDS = 0, the code can only be executed if the Firewall is opened or applying the “call gate”
entry sequence if the Firewall is closed.
Refer to Segment access depending on the Firewall state.
Bit 1 VDS: Volatile data shared
0: Volatile data segment is not shared and cannot be hit by a non protected executable code
when the Firewall is closed. If it is accessed in such a condition, a system reset will be
generated by the Firewall.
1: Volatile data segment is shared with non protected application code. It can be accessed
whatever the Firewall state (opened or closed).
Refer to Segment access depending on the Firewall state.
Bit 0 FPA: Firewall pre alarm
0: any code executed outside the protected segment when the Firewall is opened will
generate a system reset.
1: any code executed outside the protected segment will close the Firewall.
Refer to Closing the Firewall.
This register is protected in the same way as the Non-volatile data segment (refer to
Section 5.3.5: Firewall initialization).
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0x20
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0x18
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
VDE
VDS
FPA
Reset Value
Res.
FW_CR
Res.
Reset Value
Res.
0x1C
Res.
Reset Value
Res.
0
0
0
0
0
0
0
0
0
DocID025941 Rev 1
Res.
0
0
0
0
0
0
0
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res.
0
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Reset Value
0
Res.
Reset Value
0
Res.
0
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
ADD
0
LENG
0
Res.
0
Res.
0
Res.
0
0
Res.
0
Res.
LENG
0
Res.
ADD
0
Res.
LENG
0
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Reset Value
Res.
0
Res.
Reset Value
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset Value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset Value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FW_VDSL
Res.
FW_VDSSA
Res.
0x14
FW_NVDSL
Res.
0x10
Res.
0xC
FW_NVDSSA
Res.
0x8
FW_CSL
Res.
0x4
Res.
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0
FW_CSSA
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADD
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Offset
Res.
5.4.8
Res.
Firewall (FW)
RM0376
Firewall register map
The table below provides the Firewall register map and reset values.
Table 22. Firewall register map and reset values
RM0376
Power control (PWR)
6
Power control (PWR)
6.1
Power supplies
The device requires a 1.8-to-3.6 V VDD operating voltage supply (down to 1.65 V at powerdown) when the BOR is available. The device requires a 1.65-to-3.6 V VDD operating
voltage supply when the BOR is not available.
An embedded linear voltage regulator is used to supply the internal digital power, ranging
from 1.2 to 1.8 V.
•
VDD = 1.8 V (at power-on) or 1.65 V (at power-down) to 3.6 V when the BOR is
available. VDD = 1.65 V to 3.6 V, when BOR is not available
VDD is the external power supply for I/Os and internal regulator. It is provided externally
through VDD pins
•
VCORE = 1.2 to 1.8 V
VCORE is the power supply for digital peripherals, SRAM and Flash memory. It is
generated by a internal voltage regulator. Three VCORE ranges can be selected by
software depending on VDD (refer Figure 11).
•
VSSA, VDDA = 1.8 V (at power-on) or 1.65 V (at power-down) to 3.6 V, when BOR is
available and VSSA, VDDA = 1.65 to 3.6 V, when BOR is not available.
VDDA is the external analog power supply for ADC, DAC, reset blocks, RC oscillators
and PLL. The minimum voltage to be applied to VDDA is 1.8 V when the ADC is used.
•
VREF+
VREF+ is the input reference voltage.
VREF+ is only available as an external pin on TFBGA64 package, otherwise it is bonded
to VDDA.
•
VDD_USB = 3.0 to 3.6 V
VDD_USB is a dedicated independent USB power supply for full speed transceivers. It is
available on PA11 and PA12 pins provided they are configured as USB alternate
function.
Note:
VDD_USB value does not dependent on VDD and VDDA. However, VDD_USB must be the last
supply to be delivered to the device and the first to be switched off. When the three power
supplies are shut down, if VDD_USB remains active for a short period of time and VDDA/VDDIO
fall below the functional range, the device is not be damaged.
The device is still functional when VDD_USB is switched off.
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RM0376
Figure 10. Power supply overview
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1. VDDA and VSSA must be connected to VDD and VSS, respectively.
2. Depending on the operating power supply range used, some peripherals may be used with limited features
or performance.
3. VREF+ is only available on TFBGA64 package.
6.1.1
Independent A/D and DAC converter supply and reference voltage
To improve conversion accuracy, the ADC and the DAC have an independent power supply
that can be filtered separately, and shielded from noise on the PCB.
•
The ADC voltage supply input is available on a separate VDDA pin
•
An isolated supply ground connection is provided on the VSSA pin
On TFBGA64
To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to
VREF+ a separate external reference voltage lower than VDD. VREF+ is the highest voltage,
represented by the full scale value, for an analog input (ADC) or output (DAC) signal.
For ADC and DAC:
1.8 V ≤ VREF+ < VDDA
On packages with 64 pins or less (except BGA package)
VREF+ pin is not available. It is internally connected to the ADC voltage supply (VDDA).
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6.1.2
Power control (PWR)
RTC and RTC backup registers
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar, two programmable alarm interrupts, and a periodic programmable
wakeup flag with interrupt capability. The RTC contains 5 backup data registers (20 bytes).
These backup registers are reset when a tamper detection event occurs. For more details
refer to Real-time clock (RTC) section.
RTC registers access
After reset, the RTC Registers (RTC registers and RTC backup registers) are protected
against possible stray write accesses. To enable access to the RTC Registers, proceed as
follows:
6.1.3
1.
Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR
register.
2.
Set the DBP bit in the PWR_CR register (see Section 6.4.1).
3.
Select the RTC clock source through RTCSEL[1:0] bits in RCC_CSR register.
4.
Enable the RTC clock by programming the RTCEN bit in the RCC_CSR register.
Voltage regulator
An embedded linear voltage regulator supplies all the digital circuitries except for the
Standby circuitry. The regulator output voltage (VCORE) can be programmed by software to
three different ranges within 1.2 - 1.8 V (typical) (see Section 6.1.4).
The voltage regulator is always enabled after Reset. It works in three different modes: main
(MR), low power (LPR) and power-down, depending on the application modes.
6.1.4
•
In Run mode, the regulator is main (MR) mode and supplies full power to the VCORE
domain (core, memories and digital peripherals).
•
In Low power run mode, the regulator is in low power (LPR) mode and supplies low
power to the VCORE domain, preserving the contents of the registers and internal
SRAM.
•
In Sleep mode, the regulator is main (MR) mode and supplies full power to the VCORE
domain, preserving the contents of the registers and internal SRAM.
•
In low power sleep mode, the regulator is in low power (LPR) mode and supplies low
power to the VCORE domain, preserving the contents of the registers and internal
SRAM.
•
In Stop mode the regulator supplies low power to the VCORE domain, preserving the
content of registers and internal SRAM.
•
In Standby mode, the regulator is powered off. The content of the registers and SRAM
are lost except for the Standby circuitry.
Dynamic voltage scaling management
The dynamic voltage scaling is a power management technique which consists in
increasing or decreasing the voltage used for the digital peripherals (VCORE), according to
the circumstances.
Dynamic voltage scaling to increase VCORE is known as overvolting. It allows to improve the
device performance. Refer to Figure 11 for a description of the STM32L0x2 operating
conditions versus performance.
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Dynamic voltage scaling to decrease VCORE is known as undervolting. It is performed to
save power, particularly in laptops and other mobile devices where the energy comes from a
battery and is thus limited.
Range 1
Range 1 is the “high performance” range.
The voltage regulator outputs a 1.8 V voltage (typical) as long as the VDD input voltage is
above 1.71 V. Flash program and erase operations can be performed in this range.
The CPU frequency changes from initial to final state must respect the conditions:
•
fCPU initial < 4fCPU final.
•
In addition, a 5 μs delay must be respected between two changes. For example to
switch from 4.2 to 32 MHz, switch from 4.2 to 16 MHz, wait for 5 μs, then switch from
16 to 32 MHz.
Range 2 and 3
The regulator can also be programmed to output a regulated 1.5 V (typical, range 2) or a
1.2 V (typical, range 3) without any limitations on VDD (1.65 to 3.6 V).
•
At 1.5 V, the Flash memory is still functional but with medium read access time. This is
the “medium performance” range. Program and erase operations on the Flash memory
are still possible.
•
At 1.2 V, the Flash memory is still functional but with slow read access time. This is the
“low performance” range. Program and erase operations on the Flash memory are not
possible under these conditions.
Refer to Table 23 for details on the performance for each range.
Table 23. Performance versus VCORE ranges
CPU
performance
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Power
performance
VCORE
range
Typical
Value (V)
Max frequency
(MHz)
1 WS
0 WS
High
Low
1
1.8
32
16
Medium
Medium
2
1.5
16
8
Low
High
3
1.2
4.2
4.2
DocID025941 Rev 1
VDD range
1.71 - 3.6
1.65 - 3.6
RM0376
Power control (PWR)
Figure 11. Performance versus VDD and VCORE range
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6.1.5
Dynamic voltage scaling configuration
The following sequence is required to program the voltage regulator ranges:
Note:
1.
Check VDD to identify which ranges are allowed (see Figure 11: Performance versus
VDD and VCORE range).
2.
Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0.
3.
Configure the voltage scaling range by setting the VOS[12:11] bits in the PWR_CR
register.
4.
Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0.
During voltage scaling configuration, the system clock is stopped until the regulator is
stabilized (VOSF=0). This must be taken into account during application development, in
case a critical reaction time to interrupt is needed, and depending on peripheral used (timer,
communication,...).
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6.1.6
RM0376
Voltage regulator and clock management when VDD drops
below 1.71 V
When VCORE range 1 is selected and VDD drops below 1.71 V, the application must
reconfigure the system.
A three-step sequence is required to reconfigure the system:
1.
Detect that VDD drops below 1.71 V:
Use the PVD to monitor the VDD voltage and to generate an interrupt when the voltage
goes under the selected level. To detect the 1.71 V voltage limit, the application can
select by software PVD threshold 2 (2.26 V typical). For more details on the PVD, refer
to Section 6.2.3.
2.
Adapt the clock frequency to the voltage range that will be selected at next step:
Below 1.71 V, the system clock frequency is limited to 16 MHz for range 2 and 4.2 MHz
for range 3.
3.
Select the required voltage range:
Note that when VDD is below 1.71 V, only range 2 or range 3 can be selected.
Note:
When VCORE range 2 or range 3 is selected and VDD drops below 1.71 V, no system
reconfiguration is required.
6.1.7
Voltage regulator and clock management when modifying the
VCORE range
When VDD is above 1.71 V, any of the 3 voltage ranges can be selected:
•
•
When the voltage range is above the targeted voltage range (e.g. from range 1 to 2):
a)
Adapt the clock frequency to the lower voltage range that will be selected at next
step.
b)
Select the required voltage range.
When the voltage range is below the targeted voltage range (e.g. from range 3 to 1):
a)
Select the required voltage range.
b)
Tune the clock frequency if needed.
When VDD is below 1.71 V, only range 2 and 3 can be selected:
•
•
6.1.8
From range 2 to range 3
a)
Adapt the clock frequency to voltage range 3.
b)
Select voltage range 3.
From range 3 to range 2
a)
Select the voltage range 2.
b)
Tune the clock frequency if needed.
Voltage range and limitations when VDD ranges from 1.71 V to 2.0 V
The STM32L0x2 voltage regulator is based on an architecture designed for ultra low power.
It does not use any external capacitor. Such regulator is sensitive to fast changes of load. In
this case, the output voltage is reduced for a short period of time. Considering that the core
voltage must be higher than 1.65 V to ensure a 32 MHz operation, this phenomenon is
critical for very low VDD voltages (e.g. 1.71 V VDD minimum value).
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Power control (PWR)
To guarantee 32 MHz operation at VDD =1.8 V±5%, at a junction temperature of 105 °C,
with 1 wait state, and VCORE range 1, the CPU frequency in run mode must be managed to
prevent any changes exceeding a ratio of 4 in one shot. A delay of 5 μs must be respected
between 2 changes. There is no limitation when waking up from low power mode.
6.2
Power supply supervisor
The device has an integrated zeropower power-on reset (POR)/power-down reset (PDR),
coupled with a brown out reset (BOR) circuitry. For devices operating between 1.8 and 3.6
V, the BOR is always active at power-on and ensures proper operation starting from 1.8 V.
After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to
confirm or modify default thresholds, or to disable BOR permanently (in which case, the VDD
min value at power-down is 1.65 V). For devices operating between 1.65 V and 3.6 V, the
BOR is permanently disabled. Consequently, the start-up time at power-on can be
decreased down to 1 ms typically.
Five BOR thresholds can be configured by option bytes, starting from 1.65 to 3 V. To reduce
the power consumption in Stop mode, the internal voltage reference, VREFINT, can be
automatically switch off. The device remains in reset mode when VDD is below a specified
threshold, VPOR, VPDR or VBOR, without the need for any external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. 7 different PVD levels can
be selected by software between 1.85 and 3.05 V, with a 200 mV step. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine then generates a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
The different power supply supervisor (POR, PDR, BOR, PVD) are illustrated in Figure 12.
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Figure 12. Power supply supervisors
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1. The PVD is available on all devices and it is enabled or disabled by software.
2. The BOR is available only on devices operating from 1.8 to 3.6 V, and unless disabled by option byte it will
mask the POR/PDR threshold.
3. When the BOR is disabled by option byte, the reset is asserted when VDD goes below PDR level
4. For devices operating from 1.65 to 3.6 V, there is no BOR and the reset is released when VDD goes above
POR level and asserted when VDD goes below PDR level
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6.2.1
Power control (PWR)
Power-on reset (POR)/power-down reset (PDR)
The device has an integrated POR/PDR circuitry that allows operation down to 1.5 V.
During power-on, the device remains in Reset mode when VDD/VDDA is below a specified
threshold, VPOR, without the need for an external reset circuit. The POR feature is always
enabled and the POR threshold is 1.5 V.
During power-down, the PDR keeps the device under reset when the supply voltage (VDD)
drops below the VPDR threshold. The PDR feature is always enabled and the PDR threshold
is 1.5 V.
The POR and PDR are used only when the BOR is disabled (see Section 6.2.2: Brown out
reset (BOR))). To insure the minimum operating voltage (1.65 V), the BOR should be
configured to BOR Level 0. When the BOR is disabled, a “gray zone” exist between the
minimum operating voltage (1.65 V) and the VPOR/VPDR threshold. This means that VDD
can be lower than 1.65 V without device reset until the VPDR threshold is reached.
For more details concerning the power-on/power-down reset threshold, refer to the
electrical characteristics of the datasheet.
Figure 13. Power-on reset/power-down reset waveform
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6.2.2
Brown out reset (BOR)
During power-on, the Brown out reset (BOR) keeps the device under reset until the supply
voltage reaches the specified VBOR threshold.
For devices operating from 1.65 to 3.6 V, the BOR option is not available and the power
supply is monitored by the POR/PDR. As the POR/PDR thresholds are at 1.5 V, a “gray
zone” exists between the VPOR/VPDR thresholds and the minimum product operating
voltage 1.65 V.
For devices operating from 1.8 to 3.6 V, the BOR is always active at power-on and it's
threshold is 1.8 V.
Then when the system reset is released, the BOR level can be reconfigured or disabled by
option byte loading.
If the BOR level is kept at the lowest level, 1.8 V at power-on and 1.65 V at power-down, the
system reset is fully managed by the BOR and the product operating voltages are within
safe ranges.
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And when the BOR option is disabled by option byte, the power-down reset is controlled by
the PDR and a “gray zone” exists between the 1.65 V and VPDR.
VBOR is configured through device option bytes. By default, the Level 4 threshold is
activated. 5 programmable VBOR thresholds can be selected.
•
BOR Level 0 (VBOR0): reset threshold level for 1.69 to 1.80 V voltage range
•
BOR Level 1 (VBOR1): reset threshold level for 1.94 to 2.1 V voltage range
•
BOR Level 2 (VBOR2): reset threshold level for 2.3 to 2.49 V voltage range
•
BOR Level 3 (VBOR3): reset threshold level for 2.54 to 2.74 V voltage range
•
BOR Level 4 (VBOR4): reset threshold level for 2.77 to 3.0 V voltage range
When the supply voltage (VDD) drops below the selected VBOR threshold, a device reset is
generated. When the VDD is above the VBOR upper limit the device reset is released and the
system can start.
BOR can be disabled by programming the device option bytes. To disable the BOR function,
VDD must have been higher than VBOR0 to start the device option byte programming
sequence. The power-on and power-down is then monitored by the POR and PDR (see
Section 6.2.1: Power-on reset (POR)/power-down reset (PDR))
The BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the
supply voltage).
Figure 14. BOR thresholds
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6.2.3
Programmable voltage detector (PVD)
You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the PWR_CR (see Section 6.4.1).
The PVD can use an external input analog voltage (PVD_IN) which is compared internally to
VREFINT. The PVD_IN (PB7) has to be configured in Analog mode when PLS[2:0] = 111.
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the PWR_CSR (see Section 6.4.2), to indicate if VDD is higher
or lower than the PVD threshold. This event is internally connected to the EXTI line16 and
can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt
can be generated when VDD drops below the PVD threshold and/or when VDD rises above
the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an
example the service routine could perform emergency shutdown tasks.
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Power control (PWR)
Figure 15. PVD thresholds
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Internal voltage reference (VREFINT)
The internal reference (VREFINT) provides stable voltage for analog peripherals. The
functions managed through the internal voltage reference (VREFINT) are BOR, PVD, ADC,
HSI48 and comparators. The internal voltage reference (VREFINT) is always enabled when
one of these features is used.
The internal voltage reference consumption is not negligible, in particular in Stop and
Standby mode. To reduce power consumption, the ULP bit (Ultra low power) in the
PWR_CR register can be set to disable the internal voltage reference. However, in this
case, when exiting from the Stop/Standby mode, the functions managed through the internal
voltage reference are not reliable during the internal voltage reference startup time (up to
3 ms).
To reduce the wakeup time, the device can exit from Stop/Standby mode without waiting for
the internal voltage reference startup time. This is performed by setting the FWU bit (Fast
wakeup) in the PWR_CR register before entering Stop/Standby mode.
If the ULP bit is set, the functions that were enabled before entering Stop/Standby mode will
be disabled during these modes, and enabled again only after the end of the internal voltage
reference startup time whatever FWU value. The VREFINTRDYF flag in the PWR_CSR
register indicates that the internal voltage reference is ready.
6.3
Low-power modes
By default, the microcontroller is in Run mode after a system or a power-on reset. In Run
mode the CPU is clocked by HCLK and the program code is executed. Several low-power
modes are available to save power when the CPU does not need to be kept running, for
example when waiting for an external event. It is up to the user to select the mode that gives
the best compromise between low-power consumption, performance, short startup time and
available wakeup sources.
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The devices feature five low-power modes:
•
Low power run mode: regulator in low power mode, limited clock frequency, limited
number of peripherals running
•
Sleep mode: Cortex®-M0+ core stopped, peripherals kept running
•
Low power sleep mode: Cortex®-M0+core stopped, limited clock frequency, limited
number of peripherals running, regulator in low power mode, RAM in power-down,
Flash stopped.
•
Stop mode (all clocks are stopped, regulator running, regulator in low power mode
•
Standby mode: VCORE domain powered off
In addition, the power consumption in Run mode can be reduced by one of the following
means:
•
Slowing down the system clocks
•
Gating the clocks to the APBx and AHBx peripherals when they are unused.
Table 24. Summary of low-power modes
Mode name
Low power
run
Sleep
(Sleep now or
Sleep-on-exit)
Low power
sleep (Sleep
now or Sleepon-exit)
Stop
Standby
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Effect on
VDD
Voltage regulator
domain
clocks
Entry
Wakeup
Effect on VCORE
domain clocks
LPSDSR and
LPRUN bits +
Clock setting
The regulator is forced in
Main regulator (1.8 V)
None
None
In low power
mode
WFI
Any interrupt
WFE
Wakeup event
CPU CLK OFF
no effect on other
clocks or analog
clock sources
None
ON
LPSDSR bits +
WFI
Any interrupt
CPU CLK OFF
no effect on other
clocks or analog
clock sources,
Flash CLK OFF
None
In low power
mode
LPSDSR bits +
WFE
Wakeup event
PDDS, LPSDSR
Any EXTI line (configured
bits +
in the EXTI registers,
SLEEPDEEP bit +
internal and external lines)
WFI or WFE
PDDS bit +
SLEEPDEEP bit +
WFI or WFE
WKUP pin rising edge,
RTC alarm (Alarm A or
Alarm B), RTC Wakeup
event, RTC tamper event,
RTC timestamp event,
external reset in NRST
pin, IWDG reset
All VCORE
domain clocks
OFF
DocID025941 Rev 1
HSI16
and HSE
and MSI
oscillators
OFF
ON, in low power
mode (depending
on PWR_CR)
OFF
RM0376
6.3.1
Power control (PWR)
Behavior of clocks in low power modes
APB peripheral and DMA clocks can be disabled by software.
Sleep and Low power sleep modes
The CPU clock is stopped in Sleep and Low power sleep mode. The memory interface
clocks (Flash memory and RAM interfaces) and all peripherals clocks can be stopped by
software during Sleep. The memory interface clock is stopped and the RAM is in powerdown when in Low power sleep mode. The AHB to APB bridge clocks are disabled by
hardware during Sleep/Low power sleep mode when all the clocks of the peripherals
connected to them are disabled.
Stop and Standby modes
The system clock and all high speed clocks are stopped in Stop and Standby modes:
•
PLL is disabled
•
Internal RC 16 MHz (HSI16) oscillator is disabled
•
External 1-24 MHz (HSE) oscillator is disabled
•
Internal 65 kHz - 4.2 MHz (MSI) oscillator is disabled
When exiting this mode by an interrupt (Stop mode), the internal MSI or HSI16 can be
selected as system clock. For both oscillators, their respective configuration (range and
trimming) value is kept on Stop mode exit.
When exiting this mode by a reset (standby mode), the internal MSI oscillator is selected as
system clock. The range and the trimming value are reset to the default 2.1 MHz.
If a Flash program operation or an access to APB domain is ongoing, the Stop/Standby
mode entry is delayed until the Flash memory or the APB access has completed.
6.3.2
Slowing down system clocks
In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.
For more details refer to Section 7.3.4: Clock configuration register (RCC_CFGR).
6.3.3
Peripheral clock gating
In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped
at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB peripheral clock enable register
(RCC_AHBENR), APB2 peripheral clock enable register (RCC_APB2ENR), APB1
peripheral clock enable register (RCC_APB1ENR) (see Section 7.3.13: AHB peripheral
clock enable register (RCC_AHBENR), Section 7.3.15: APB1 peripheral clock enable
register (RCC_APB1ENR) and Section 7.3.14: APB2 peripheral clock enable register
(RCC_APB2ENR)).
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in RCC_AHBLPENR and RCC_APBxLPENR registers (x can 1 or 2).
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6.3.4
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Low power run mode (LP run)
To further reduce the consumption when the system is in Run mode, the regulator can be
configured in low power mode. In this mode, the system frequency should not exceed
f_MSI range1.
Please refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
Note:
To be able to read the RTC calendar register when the APB1 clock frequency is less than
seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar
time and date registers twice.
If the second read of the RTC_TR gives the same result as the first read, this ensures that
the data is correct. Otherwise a third read access must be done.
Low power run mode can only be entered when VCORE is in range 2. In addition, the
dynamic voltage scaling must not be used when Low power run mode is selected. Only Stop
and Sleep modes with regulator configured in Low power mode is allowed when Low power
run mode is selected.
Note:
In Low power run mode, all I/O pins keep the same state as in Run mode.
Entering Low power run mode
To enter Low power run mode proceed as follows:
•
Each digital IP clock must be enabled or disabled by using the RCC_APBxENR and
RCC_AHBENR registers.
•
The frequency of the system clock must be decreased to not exceed the frequency of
f_MSI range1.
•
The regulator is forced in low power mode by software (LPRUN and LPSDSR bits set)
Exiting Low power run mode
To exit Low power run mode proceed as follows:
6.3.5
•
The regulator is forced in Main regulator mode by software.
•
The Flash memory is switched on, if needed.
•
The frequency of the clock system can be increased.
Sleep mode
Entering Sleep mode
The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for
Event) instructions. Two options are available to select the Sleep mode entry mechanism,
depending on the SLEEPONEXIT bit in the Cortex®-M0+ System Control register:
Note:
•
Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon
as WFI or WFE instruction is executed.
•
Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as
it exits the lowest priority ISR.
In Sleep mode, all I/O pins keep the same state as in Run mode.
Refer to Table 25: Sleep-now and Table 26: Sleep-on-exit for details on how to enter Sleep
mode.
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Exiting Sleep mode
If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by
the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.
If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as
an event occurs. The wakeup event can be generated either by:
•
Enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex®-M0+ System Control register. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ
channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
•
Or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit.
Refer to Table 25: Sleep-now and Table 26: Sleep-on-exit for more details on how to exit
Sleep mode.
Table 25. Sleep-now
Sleep-now mode
Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 0
Refer to the Cortex®-M0+ System Control register.
Mode exit
If WFI was used for entry:
Interrupt: Refer to Table 44: Vector table
If WFE was used for entry
Wakeup event: Refer to Section 13.3.2: Wakeup event management
Wakeup latency
None
Table 26. Sleep-on-exit
Sleep-on-exit
6.3.6
Description
Mode entry
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex®-M0+ System Control register.
Mode exit
Interrupt: refer to Table 44: Vector table
Wakeup latency
None
Low power sleep mode (LP sleep)
Entering Low power sleep mode
The Low power sleep mode is entered by configuring the voltage regulator in low power
mode, and by executing the WFI (wait for interrupt) or WFE (wait for event) instructions. In
this mode, the Flash memory is not available but the RAM memory remains available.
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In this mode, the system frequency should not exceed f_MSI range1.
Please refer to product datasheet for more details on voltage regulator and peripherals
operating conditions.
Low power sleep mode can only be entered when VCORE is in range 2.
Note:
To be able to read the RTC calendar register when the APB1 clock frequency is less than
seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar
time and date registers twice.
If the second read of the RTC_TR gives the same result as the first read, this ensures that
the data is correct. Otherwise a third read access must be done.
Two options are available to select the Sleep low power mode entry mechanism, depending
on the SLEEPONEXIT bit in the Cortex®-M0+ System Control register:
•
Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon
as WFI or WFE instruction is executed.
•
Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as
it exits the lowest priority ISR.
To enter Low power sleep mode, proceed as follows:
Note:
•
The Flash memory can be switched off by using the control bits (SLEEP_PD in the
FLASH_ACR register. For more details refer to PM0062). This reduces power
consumption but increases the wake-up time.
•
Each digital IP clock must be enabled or disabled by using the RCC_APBxENR and
RCC_AHBENR registers.
•
The frequency of the system clock must be decreased.
•
The regulator is forced in low power mode by software (LPSDSR bits set).
•
A WFI/WFE instruction must be executed to enter in Sleep mode.
In Low power sleep mode, all I/O pins keep the same state as in Run mode.
Refer to Table 27: Sleep-now and Table 28: Sleep-on-exit for details on how to enter Low
power sleep mode.
Exiting Low power sleep mode
If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt
acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device
from Low power sleep mode.
If the WFE instruction was used to enter Low power sleep mode, the MCU exits Sleep mode
as soon as an event occurs. The wakeup event can be generated:
•
By enabling an interrupt in the peripheral control register but not in the NVIC, and by
enabling the SEVONPEND bit in the Cortex®-M0+ System Control register. When the
MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC
IRQ channel pending bit in the NVIC interrupt clear pending register must be cleared.
•
Or by configuring an external or internal EXTI line in event mode. When the CPU
resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or
the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is
not set.
When exiting Low power sleep mode by issuing an interrupt or a wakeup event, the
regulator is configured in Main regulator mode, the Flash memory is switched on (if
necessary), and the system clock can be increased.
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When the voltage regulator operates in low power mode, an additional startup delay is
incurred when waking up from Low power sleep mode.
Refer to Table 27: Sleep-now and Table 28: Sleep-on-exit for more details on how to exit
Sleep low power mode.
Table 27. Sleep-now
Sleep-now mode
Description
Mode entry
Voltage regulator in low power mode and the Flash memory switched off
WFI (Wait for Interrupt) or WFE (wait for event) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 0
Refer to the Cortex®-M0+ System Control register.
Mode exit
Voltage regulator in Main regulator mode and the Flash memory switched on
If WFI was used for entry:
Interrupt: Refer to Table 44: Vector table
If WFE was used for entry
Wakeup event: Refer to Section 13.3.2: Wakeup event management
Wakeup latency
Regulator wakeup time from low power mode
Table 28. Sleep-on-exit
Sleep-on-exit
6.3.7
Description
Mode entry
Voltage regulator in low power mode and the Flash memory switched off
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex®-M0+ System Control register.
Mode exit
Interrupt: refer to Table 44: Vector table.
Wakeup latency
regulator wakeup time from low power mode
Stop mode
The Stop mode is based on the Cortex®-M0+ deepsleep mode combined with peripheral
clock gating. The voltage regulator can be configured either in normal or low-power mode.
In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16 and
the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.
To get the lowest consumption in Stop mode, the internal Flash memory also enters low
power mode. When the Flash memory is in power-down mode, an additional startup delay is
incurred when waking up from Stop mode.
To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
sensor can be switched off before entering Stop mode. They can be switched on again by
software after exiting Stop mode using the ULP bit in the PWR_CR register.
Note:
In Stop mode, all I/O pins keep the same state as in Run mode.
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Entering Stop mode
Refer to Table 29 for details on how to enter the Stop mode.
If the application needs to disable the external clock before entering Stop mode, the HSEON
bit must be first disabled and the system clock switched to HSI16.
Otherwise, if the HSEON bit is kept enabled while external clock (external oscillator) can be
removed before entering Stop mode, the clock security system (CSS) feature must be
enabled to detect any external oscillator failure and avoid a malfunction behavior when
entering Stop mode.
To further reduce power consumption in Stop mode, the internal voltage regulator can be put
in low power mode. This is configured by the LPSDSR bit in the PWR_CR register (see
Section 6.4.1).
If Flash memory programming or an access to the APB domain is ongoing, the Stop mode
entry is delayed until the memory or APB access has completed.
In Stop mode, the following features can be selected by programming individual control bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. Refer to
Section 24.3: IWDG functional description in Section 24: Independent watchdog
(IWDG).
•
Real-time clock (RTC): this is configured by the RTCEN bit in the RCC_CSR register
(see Section 7.3.21).
•
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC_CSR
register.
•
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
RCC_CSR register.
The ADC, DAC can also consume power in Stop mode, unless they are disabled before
entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the
DAC_CR register must both be written to 0.
Exiting Stop mode
Refer to Table 29 for more details on how to exit Stop mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the MSI or HSI16 RC
oscillator is selected as system clock depending the bit STOPWUCK in the RCC_CFGR
register.
When the voltage regulator operates in low power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.
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Table 29. Stop mode
Stop mode
6.3.8
Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP bit in Cortex®-M0+ System Control register
– Clear PDDS bit in Power Control register (PWR_CR)
– Clear WUF bit in Power Control/Status register (PWR_CSR)
– Select the MSI or HSI16 RC oscillator as system clock for Stop mode exit
by configuring the STOPWUCK bit in the RCC_CFGR register.
Note: To enter the Stop mode, all EXTI Line pending bits (in
Section 13.5.6: EXTI pending register (EXTI_PR)), all peripherals
interrupt pending bits, the RTC Alarm (Alarm A and Alarm B), RTC
wakeup, RTC tamper, and RTC time-stamp flags, must be reset.
Otherwise, the Stop mode entry procedure is ignored and program
execution continues.
Mode exit
If WFI was used for entry:
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). Refer to Table 44: Vector
table.
If WFE was used for entry:
Any EXTI Line configured in event mode. Refer to Section 13.3.2:
Wakeup event management on page 260
Wakeup latency
MSI or HSI16 RC wakeup time + regulator wakeup time from Low-power
mode + FLASH wakeup time
Standby mode
The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex®-M0+ deepsleep mode, with the voltage regulator disabled. The VCORE domain is
consequently powered off. The PLL, the MSI, the HSI16 oscillator and the HSE oscillator
are also switched off. SRAM and register contents are lost except for the RTC registers,
RTC backup registers and Standby circuitry (see Figure 10).
Entering Standby mode
Refer to Table 30 for more details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. Refer to
Section 15.3: IWDG functional description on page 409.
•
Real-time clock (RTC): this is configured by the RTCEN bit in the RCC_CSR register
(see Section 7.3.21).
•
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC_CSR
register.
•
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
RCC_CSR register.
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Exiting Standby mode
The microcontroller exits Standby mode when an external Reset (NRST pin), an IWDG
Reset, a rising edge on WKUP pins (WUKP1, WKUP2 or WKUP3), an RTC alarm, a tamper
event, or a time-stamp event is detected. All registers are reset after wakeup from Standby
except for PWR power control/status register (PWR_CSR).
After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the
PWR_CSR register (see Section 6.4.2) indicates that the MCU was in Standby mode.
Refer to Table 30 for more details on how to exit Standby mode.
Table 30. Standby mode
Standby mode
Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP in Cortex®-M0+ System Control register
– Set PDDS bit in Power Control register (PWR_CR)
– Clear WUF bit in Power Control/Status register (PWR_CSR)
– Clear the RTC flag corresponding to the chosen wakeup source (RTC
Alarm A, RTC Alarm B, RTC wakeup, Tamper or Time-stamp flags)
Mode exit
WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
Wakeup latency
Reset phase
I/O states in Standby mode
In Standby mode, all I/O pins are high impedance except for:
•
Reset pad (still available)
•
Pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, time-stamp, RTC Alarm
out, or RTC clock calibration out.
•
WKUP pin 1 (PA0) if enabled.
Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop or Standby
mode while the debug features are used. This is due to the fact that the Cortex®-M0+ core is
no longer clocked.
However, by setting some configuration bits in the DBG_CR register, the software can be
debugged even when using the low-power modes extensively. For more details, refer to
Section 23.16.1: Debug support for low-power modes.
6.3.9
Waking up the device from Stop and Standby modes using the RTC
and comparators
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC Wakeup
event, a tamper event, a time-stamp event, or a comparator event, without depending on an
external interrupt (Auto-wakeup mode).
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These RTC alternate functions can wake up the system from Stop and Standby low power
modes while the comparator events can only wake up the system from Stop mode.
The system can also wake up from low power modes without depending on an external
interrupt (Auto-wakeup mode) by using the RTC alarm or the RTC wakeup events.
The RTC provides a programmable time base for waking up from Stop or Standby mode at
regular intervals. For this purpose, two of the three alternative RTC clock sources can be
selected by programming the RTCSEL[1:0] bits in the RCC_CSR register (see
Section 7.3.21):
•
Low-power 32.768 kHz external crystal oscillator (LSE OSC).
This clock source provides a precise time base with very low-power consumption (less
than 1 µA added consumption in typical conditions)
•
Low-power internal RC oscillator (LSI RC)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC Oscillator is designed to use minimum power consumption.
RTC auto-wakeup (AWU) from the Stop mode
•
To wake up from the Stop mode with an RTC alarm event, it is necessary to:
a)
•
•
Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event
modes)
b)
Enable the RTC Alarm interrupt in the RTC_CR register
c)
Configure the RTC to generate the RTC alarm
To wake up from the Stop mode with an RTC Tamper or time stamp event, it is
necessary to:
a)
Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event
modes)
b)
Enable the RTC TimeStamp Interrupt in the RTC_CR register or the RTC Tamper
Interrupt in the RTC_TCR register
c)
Configure the RTC to detect the tamper or time stamp event
To wake up from the Stop mode with an RTC Wakeup event, it is necessary to:
a)
Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event
modes)
b)
Enable the RTC Wakeup Interrupt in the RTC_CR register
c)
Configure the RTC to generate the RTC Wakeup event
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RTC auto-wakeup (AWU) from the Standby mode
•
•
•
To wake up from the Standby mode with an RTC alarm event, it is necessary to:
a)
Enable the RTC Alarm interrupt in the RTC_CR register
b)
Configure the RTC to generate the RTC alarm
To wake up from the Stop mode with an RTC Tamper or time stamp event, it is
necessary to:
a)
Enable the RTC TimeStamp Interrupt in the RTC_CR register or the RTC Tamper
Interrupt in the RTC_TCR register
b)
Configure the RTC to detect the tamper or time stamp event
To wake up from the Stop mode with an RTC Wakeup event, it is necessary to:
a)
Enable the RTC Wakeup Interrupt in the RTC_CR register
b)
Configure the RTC to generate the RTC Wakeup event
Comparator auto-wakeup (AWU) from the Stop mode
•
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To wake up from the Stop mode with a comparator 1 or comparator 2 wakeup event, it
is necessary to:
a)
Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
(Interrupt or Event mode) to be sensitive to the selected edges (falling, rising or
falling and rising)
b)
Configure the comparator to generate the event
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6.4
Power control registers
The peripheral registers have to be accessed by half-words (16-bit) or words (32-bit).
6.4.1
PWR power control register (PWR_CR)
Address offset: 0x00
Reset value: 0x0000 1000 (reset by wakeup from Standby mode)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FWU
ULP
DBP
PVDE
CSBF
CWUF
rw
rw
rw
rw
rc_w1
rc_w1
Res.
DS_EE
LPRUN
_KOFF
rw
rw
VOS[1:0]
rw
rw
PLS[2:0]
rw
rw
rw
PDDS LPSDSR
rw
rw
Bits 31:15 Reserved, always read as 0.
Bit 14 LPRUN: Low power run mode
When LPRUN bit is set together with the LPSDSR bit, the regulator is switched from main
mode to low power mode. Otherwise, it remains in main mode. The regulator goes back to
operate in main mode when LPRUN is reset.
It is forbidden to reset LPSDSR when the MCU is in Low power run mode. LPSDSR is used as
a prepositioning for the entry into low power mode, indicating to the system which
configuration of the regulator will be selected when entering Low power mode. The LPSDSR
bit must be set before the LPRUN bit is set. LPSDSR can be reset only when LPRUN bit=0.
0: Voltage regulator in main mode in Low power run mode
1: Voltage regulator in low power mode in Low power run mode
Bits 13 DS_EE_KOFF: Deep-sleep mode with Flash memory kept off
When entering low power mode (stop or standby only), if DS_EE_KOFF and RUN_PD of
FLASH_ACR register are both set (refer to Section 3.7.1: Access control register
(FLASH_ACR), the Flash memory will not be woken up when exiting from deep-sleep mode.
0: Flash memory is woken up when exiting from Deep Sleep mode even if the bit RUN_PD is
set
1: EEPROM will not be woken up when exiting from Low Power mode (if the bit RUN_PD is
set)
Bits 12:11 VOS[1:0]: Voltage scaling range selection
These bits are used to select the internal regulator voltage range.
Before resetting the power interface by resetting the PWRRST bit in the RCC_APB1RSTR
register, these bits have to be set to ‘10’ and the frequency of the system has to be configured
accordingly.
00: forbidden (bits are unchanged and keep the previous value, no voltage change occurs)
01: 1.8 V (range 1)
10: 1.5 V (range 2)
11: 1.2 V (range 3)
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Bit 10 FWU: Fast wakeup
This bit works in conjunction with ULP bit.
If ULP = 0, FWU is ignored
If ULP = 1 and FWU = 1: VREFINT startup time is ignored when exiting from low power mode.
The VREFINTRDYF flag in the PWR_CSR register indicates when the VREFINT is ready again.
If ULP=1 and FWU = 0: Exiting from low power mode occurs only when the VREFINT is ready
(after its startup time). This bit is not reset by resetting the PWRRST bit in the
RCC_APB1RSTR register.
0: Low power modes exit occurs only when VREFTINT is ready
1: VREFTINT start up time is ignored when exiting low power modes
Bit 9 ULP: Ultralow power mode
When set, the VREFINT is switched off in low power mode. This bit is not reset by resetting the
PWRRST bit in the RCC_APB1RSTR register.
0: VREFTINT is on in low power mode
1: VREFTINT is off in low power mode
Bit 8 DBP: Disable backup write protection
In reset state, the RTC, RTC backup registers and RCC CSR register are protected against
parasitic write access. This bit must be set to enable write access to these registers.
0: Access to RTC, RTC Backup and RCC CSR registers disabled
1: Access to RTC, RTC Backup and RCC CSR registers enabled
Note: If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, this bit must remain set to
1.
Bits 7:5 PLS[2:0]: PVD level selection
These bits are written by software to select the voltage threshold detected by the power
voltage detector:
000: 1.9 V
001: 2.1 V
010: 2.3 V
011: 2.5 V
100: 2.7 V
101: 2.9 V
110: 3.1 V
111: External input analog voltage (Compare internally to VREFINT)
PVD_IN input (PB7) has to be configured as analog input when PLS[2:0] = 111.
Note: Refer to the electrical characteristics of the datasheet for more details.
Bit 4 PVDE: Power voltage detector enable
This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF: Clear standby flag
This bit is always read as 0.
0: No effect
1: Clear the SBF Standby flag (write).
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Bit 2 CWUF: Clear wakeup flag
This bit is always read as 0.
0: No effect
1: Clear the WUF Wakeup flag after 2 system clock cycles
Bit 1 PDDS: Power-down deepsleep
This bit is set and cleared by software.
0: Enter Stop mode when the CPU enters deepsleep. The regulator is in low-power mode.
1: Enter Standby mode when the CPU enters deepsleep.
Bit 0 LPSDSR: Low-power deepsleep/sleep/low power run
– DeepSleep/Sleep modes
When this bit is set, the regulator switches in low power mode when the CPU enters sleep or
deepsleep mode. The regulator goes back to main mode when the CPU exits from these
modes.
– Low power run mode
When this bit is set, the regulator switches in low power mode when the bit LPRUN is set.
The regulator goes back to main mode when the bit LPRUN is reset.
This bit is set and cleared by software.
0: Voltage regulator on during deepsleep/Sleep/Low power run mode
1: Voltage regulator in low power mode during deepsleep/Sleep/Low power run mode
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6.4.2
RM0376
PWR power control/status register (PWR_CSR)
Address offset: 0x04
Reset value: 0x0000 0008 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
EWUP
2
EWUP
1
Res.
REG
LPF
VOSF
VREFIN
TRDYF
PVDO
SBF
WUF
rw
rw
r
r
r
r
r
r
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 EWUP2: Enable WKUP pin 2
This bit is set and cleared by software.
0: WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not
wakeup the device from Standby mode.
1: WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode).
Note: This bit is reset by a system reset.
Bit 8 EWUP1: Enable WKUP pin 1
This bit is set and cleared by software.
0: WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not
wakeup the device from Standby mode.
1: WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode).
Note: This bit is reset by a system reset.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 REGLPF: Regulator LP flag
This bit is set by hardware when the MCU is in Low power run mode.
When the MCU exits from Low power run mode, this bit stays at 1 until the regulator is ready in
main mode. A polling on this bit is recommended to wait for the regulator main mode. This bit is
reset by hardware when the regulator is ready.
0: Regulator is ready in main mode
1: Regulator voltage is in low power mode
Bit 4 VOSF: Voltage Scaling select flag
A delay is required for the internal regulator to be ready after the voltage range is changed.
The VOSF bit indicates that the regulator has reached the voltage level defined with bits VOS
of PWR_CR register.
This bit is reset when VOS[1:0] in PWR_CR register change.
It is set once the regulator is ready.
0: Regulator is ready in the selected voltage range
1: Regulator voltage output is changing to the required VOS level.
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Bit 3 VREFINTRDYF: Internal voltage reference (VREFINT) ready flag
This bit indicates the state of the internal voltage reference, VREFINT.
0: VREFINT is OFF
1: VREFINT is ready
Bit 2 PVDO: PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits.
1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits.
Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
Standby or reset until the PVDE bit is set.
Bit 1 SBF: Standby flag
This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down
reset) or by setting the CSBF bit in the PWR power control register (PWR_CR)
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0 WUF: Wakeup flag
This bit is set by hardware and cleared by a system reset or by setting the CWUF bit in the
PWR power control register (PWR_CR)
0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or
Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup).
Note: An additional wakeup event is detected if the WKUP pins are enabled (by setting the
EWUPx (x=1, 2, 3) bits) when the WKUP pin levels are already high.
6.4.3
PWR register map
The following table summarizes the PWR registers.
CSBF
CWUF
PDDS
LPSDSR
0
0
0
0
PVDO
SBF
WUF
0
PVDE
0
0
VOSF
Reset value
0
VREFINTRDYF
0
REGLPF
0
0
0
1
0
0
0
PLS[2:0]
0
0
Res.
Res.
ULP
DBP
0
EWUP1
0
FWU
PWR_CSR
1
EWUP2
0x004
0
VOS
[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
LPRUN
PWR_CR
DS_EE_KOFF.
0x000
Register
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 31. PWR - register map and reset values
Refer to Section 2.2.2 for the register boundary addresses.
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7
Reset and clock control (RCC)
7.1
Reset
There are three types of reset, defined as system reset, power reset and RTC domain reset.
7.1.1
System reset
A system reset sets all registers to their reset values except for the RTC, RTC backup
registers and control/status registers (RCC_CR and RCC_CSR).
A system reset is generated when one of the following events occurs:
•
A low level on the NRST pin (external reset)
•
Window watchdog end-of-count condition (WWDG reset)
•
Independent watchdog end-of-count condition (IWDG reset)
•
A software reset (SW reset) (see Software reset)
•
Low-power management reset (see Low-power management reset)
•
Option byte loader reset (see Option byte loader reset)
•
Exit from standby mode
•
Firewall protection (see Section 5: Firewall (FW))
The reset source can be identified by checking the reset flags in the control/status register,
RCC_CSR (see Section 7.3.21).
Software reset
The SYSRESETREQ bit in Cortex®-M0+ AIRCR register (Application Interrupt and Reset
Control Register) must be set to force a software reset on the device. Refer to ARM
Cortex®-M0+ Technical Reference Manual for more details.
Low-power management reset
There are two ways to generate a low-power management reset:
•
Reset generated when entering standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this
case, whenever a standby mode entry sequence is successfully executed, the device is
reset instead of entering standby mode.
•
Reset when entering stop mode:
This type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this
case, whenever a stop mode entry sequence is successfully executed, the device is
reset instead of entering stop mode.
Option byte loader reset
The Option byte loader reset is generated when the OBL_LAUNCH bit (bit 18) is set in the
FLASH_PECR register. This bit is used to launch by software the option byte loading.
For further information on the user option bytes, refer to Section 3: Flash program memory
and data EEPROM (FLASH).
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7.1.2
Reset and clock control (RCC)
Power reset
A power reset is generated when one of the following events occurs:
•
Power-on/power-down reset (POR/PDR reset)
•
BOR reset
A power reset sets all registers to their reset values including for the RTC domain (see
Figure 16)
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map. For
more details, refer to Table 44: Vector table.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each internal reset
source. In case of an external reset, the reset pulse is generated while the NRST pin is
asserted low.
Figure 16. Simplified diagram of the reset circuit
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RTC and backup registers reset
The RTC peripheral, RTC clock source selection (in RCC_CSR) and the backup registers
are reset only when one of the following events occurs:
•
A software reset, triggered by setting the RTCRST bit in the RCC_CSR register (see
Section 7.3.21)
•
Power reset (BOR/POR/PDR).
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7.2
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Clocks
Four different clock sources can be used to drive the system clock (SYSCLK):
•
•
HSI16 (high-speed internal) oscillator clock
HSE (high-speed external) oscillator clock
The HSE is not available on Cat.2 with AES.
•
PLL clock
•
MSI (multispeed internal) oscillator clock
The MSI at 2.1MHz is used as system clock source after startup from power reset,
system or RTC domain reset, and after wake-up from standby mode.
The HSI16, HSI16 divided by 4, or the MSI at any of its possible frequency can be used
to wake up from stop mode.
The devices have two secondary clock sources:
•
37 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from stop/standby mode and the LPTIMER.
•
32.768 kHz low speed external crystal (LSE crystal) which optionally drives the realtime clock (RTCCLK), the LPTIMER and UARTs.
Each clock source can be switched on or off independently when it is not used to optimize
power consumption.
Several prescalers can be used to configure the AHB frequency and the two APBs (APB1
and APB2) domains. The maximum frequency of AHB, APB1 and the APB2 domains is
32 MHz. It depends on the device voltage range. For more details refer to Section 6.1.4:
Dynamic voltage scaling management.
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All the peripheral clocks are derived from the system clock (SYSCLK) except:
•
The 48 MHz USB and RNG clocks which are derived from one of the two following
source:
–
PLL VCO clock.
–
RC48 Clock (HSI48)
•
The ADC clock which is always the HSI16 clock or the HSI16 divided by 4 to adapt the
clock frequency to the device operating conditions. For more details refer to
Section 6.1: Power supplies.
•
The LPUART1 and USART1/2 clock which is derived (selected by software) from one
of the four following sources:
•
•
•
•
–
system clock
–
HSI16 clock
–
LSE clock
–
APB clock (PCLK)
The I2C1 clock which is derived (selected by software) from one of the three following
sources:
–
system clock
–
HSI16 clock
–
APB clock (PCLK)
The LPTIMER clock which is derived (selected by software) from one of the three
following sources:
–
HSI16 clock
–
LSE clock
–
LSI clock
–
APB clock (PCLK)
The RTC clock which is derived from the following clock sources:
–
LSE clock,
–
LSI clock,
–
1 MHz HSE_RTC (HSE divided by a programmable prescaler).
IWDG clock which is always the LSI clock.
The system clock (SYSCLK) frequency must be higher or equal to the RTC clock frequency.
The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock
(HCLK), configurable in the SysTick Control and Status Register.
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Figure 17. Clock tree
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1. For full details about the internal and external clock source characteristics, please refer to the “Electrical
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characteristics” section in your device datasheet.
The timer clock frequencies are automatically fixed by hardware. There are two cases:
1.
If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as
that of the APB domain to which the timers are connected.
2.
Otherwise, they are set to twice (×2) the frequency of the APB domain to which the
timers are connected.
fCLK acts as Cortex®-M0+ free running clock. For more details refer to the Section 32:
Debug support (DBG).
7.2.1
HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
•
HSE external crystal/ceramic resonator
•
HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
Figure 18. HSE/ LSE clock sources
Clock source
Hardware configuration
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External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
32 MHz. This mode is selected by setting the HSEBYP and HSEON bits in the RCC_CR
register (see Section 7.3.1: Clock control register (RCC_CR)). The external clock signal with
~50% duty cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z
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(see Figure 18). The external clock signal can be square, sinus or triangle. To minimize the
consumption, it is recommended to use the square signal.
External crystal/ceramic resonator (HSE crystal)
The 1 to 24 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.
The associated hardware configuration is shown in Figure 18. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag of the RCC_CR register (see Section 7.3.1) indicates whether the HSE
oscillator is stable or not. At startup, the HSE clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the RCC_CR register.
The HSE Crystal can be switched on and off using the HSEON bit in the RCC_CR register.
7.2.2
HSI16 clock
The HSI16 clock signal is generated from an internal 16 MHz RC oscillator. It can be used
directly as a system clock or as PLL input.
The HSI16 clock can be used after wake-up from the stop low power mode, this ensure a
smaller wake-up time than a wake-up using MSI clock.
The HSI16 RC oscillator has the advantage of providing a clock source at low cost (no
external components). It also has a faster startup time than the HSE crystal oscillator
however, even with calibration the frequency is less accurate than an external crystal
oscillator or ceramic resonator.
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at an ambient
temperature, TA, of 25 °C.
After reset, the factory calibration value is loaded in the HSI16CAL[7:0] bits in the Internal
Clock Sources Calibration Register (RCC_ICSCR) (see Section 7.3.2).
If the application is subject to voltage or temperature variations, this may affect the RC
oscillator speed. You can trim the HSI16 frequency in the application by using the
HSI16TRIM[4:0] bits in the RCC_ICSCR register. For more details on how to measure the
HSI16 frequency variation please refer to Section 7.2.15: Internal/external clock
measurement using TIM21.
The HSI16RDY flag in the RCC_CR register indicates whether the HSI16 oscillator is stable
or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware.
The HSI16 RC oscillator can be switched on and off using the HSI16ON bit in the RCC_CR
register.
7.2.3
MSI clock
The MSI clock signal is generated from an internal RC oscillator. Its frequency range can be
adjusted by software by using the MSIRANGE[2:0] bits in the RCC_ICSCR register (see
Section 7.3.2: Internal clock sources calibration register (RCC_ICSCR)). Seven frequency
ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz,
2.097 MHz (default value) and 4.194 MHz.
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The MSI clock is always used as system clock after restart from Reset and wake-up from
standby. After wake-up from stop mode, the MSI clock can be selected as system clock
instead of HSI16 (or HSI16/4).
When the device restarts after a reset or a wake-up from standby, the MSI frequency is set
to its default value. The MSI frequency does not change after waking up from stop.
The MSI RC oscillator has the advantage of providing a low-cost (no external components)
low-power clock source. It is used as wake-up clock in low power modes to reduce power
consumption.
The MSIRDY flag in the RCC_CR register indicates whether the MSI RC is stable or not. At
startup, the MSI RC output clock is not released until this bit is set by hardware.
The MSI RC can be switched on and off by using the MSION bit in the RCC_CR register
(see Section 7.3.1).
It can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator
fails. Refer to Section 7.2.10: HSE clock security system (CSS) on page 158.
Calibration
The MSI RC oscillator frequency can vary from one chip to another due to manufacturing
process variations, this is why each device is factory calibrated by ST for 1% accuracy at an
ambient temperature, TA, of 25 °C.
After reset, the factory calibration value is loaded in the MSICAL[7:0] bits in the
RCC_ICSCR register. If the application is subject to voltage or temperature variations, this
may affect the RC oscillator speed. You can trim the MSI frequency in the application by
using the MSITRIM[7:0] bits in the RCC_ICSCR register. For more details on how to
measure the MSI frequency variation please refer to Section 7.2.15: Internal/external clock
measurement using TIM21.
7.2.4
HSI48 clock
The HSI48 clock signal is generated from an internal 48 MHz RC oscillator and can be used
directly for USB and for random number generator (RNG).
The internal 48MHz RC oscillator is mainly dedicated to provide a high precision clock to the
USB peripheral by means of a special Clock Recovery System (CRS) circuitry. The CRS
can use the USB SOF signal, the LSE or an external signal to automatically and quickly
adjust the oscillator frequency on-fly. It is disabled as soon as the system enters stop or
standby mode. When the CRS is not used, the HSI48 RC oscillator runs on its default
frequency which is subject to manufacturing process variations.
For more details on how to configure and use the CRS peripheral please refer to Section 8:
Clock recovery system (CRS).
The HSI48 requires VREFINT and its buffer with 48 MHz RC to be enabled (see
ENREF_HSI48 and EN_VREFINT in Section 10.2.3: Reference control and status register
(REF_CFGR3))
The HSI48RDY flag in the Clock recovery RC register (RCC_CRRCR) indicates whether the
HSI48 RC is stable or not. At startup, the HSI48 RC output clock is not released until this bit
is set by hardware.
The HSI48 RC can be switched on and off using the HSI48ON bit in the Clock recovery RC
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register (RCC_CRRCR).
7.2.5
PLL
The internal PLL can be clocked by the HSI16 RC or HSE crystal. It drives the system clock
and can be used to generate the 48 MHz clock for the USB peripheral (refer to Figure 17
and Section 7.3.1: Clock control register (RCC_CR).
The PLL input clock frequency must range between 2 and 24 MHz.
The desired frequency is obtained by using the multiplication factor and output division
embedded in the PLL:
Note:
•
If the USB uses the PLL as clock source, the PLL VCO clock (defined by the PLL
multiplication factor) must be programmed to output a 96 MHz frequency (USBCLK =
PLLVCO/2).
•
The system clock is derived from the PLL VCO divided by the output division factor.
The application software must set correctly the PLL multiplication factor to avoid exceeding
96 MHz as PLLVCO when the product is in range 1,
48 MHz as PLLVCO when the product is in range 2,
24 MHz when the product is in range 3.
It must also set correctly the output division to avoid exceeding 32 MHz as SYSCLK.
The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source).
The PLL configuration (selection of the source clock, multiplication factor and output division
factor) must be performed before enabling the PLL. Once the PLL is enabled, these
parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1.
Disable the PLL by setting PLLON to 0.
2.
Wait until PLLRDY is cleared. The PLL is now fully stopped.
3.
Change the desired parameter.
4.
Enable the PLL again by setting PLLON to 1.
An interrupt can be generated when the PLL is ready if enabled in the RCC_CIER register
(see Section 7.3.5).
7.2.6
LSE clock
The LSE crystal is a 32.768 kHz low speed external crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off through the LSEON bit in the RCC_CSR register
(see Section 7.3.21).
The crystal oscillator driving strength can be changed at runtime through the LSEDRV[1:0]
bits of the RCC_CSR register to obtain the best compromise between robustness and short
start-up time on one hand and low power-consumption on the other hand. The driving
capability can be changed dynamically between the different drive level, except when the
low drive mode is reached. In this case it can only be changed to another mode through a
power-on reset or an RTC reset.
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The LSERDY flag in the RCC_CSR register indicates whether the LSE crystal is stable or
not. At startup, the LSE crystal output clock signal is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the RCC_CIER register (see
Section 7.3.5).
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the RCC_CR (see
Section 7.3.1). The external clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi-Z (see
Figure 18).
7.2.7
LSI clock
The LSI RC acts as an low-power clock source that can be kept running in stop and standby
mode for the independent watchdog (IWDG). The clock frequency is around 37 kHz.
The LSI RC oscillator can be switched on and off using the LSION bit in the RCC_CSR
register (see Section 7.3.21).
The LSIRDY flag in RCC_CSR indicates whether the low-speed internal oscillator is stable
or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can
be generated if enabled in the RCC_CIER (see Section 7.3.5).
LSI measurement
The frequency dispersion of the LSI oscillator can be measured to have accurate RTC time
base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an
acceptable accuracy. For more details, refer to the electrical characteristics section of the
datasheets. For more details on how to measure the LSI frequency, please refer to
Section 7.2.15: Internal/external clock measurement using TIM21.
7.2.8
System clock (SYSCLK) selection
Four different clock sources can be used to drive the system clock (SYSCLK):
•
The HSI16 oscillator
•
The HSE oscillator
•
The PLL
•
The MSI oscillator clock (default after reset)
When a clock source is used directly or through the PLL as system clock, it is not possible to
stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source will be ready. Status bits in the
RCC_CR register indicate which clock(s) is (are) ready and which clock is currently used as
system clock.
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System clock source frequency versus voltage range
The following table gives the different clock source maximum frequencies depending on the
product voltage range.
Table 32. System clock source frequency
Product voltage
range
Clock frequency
MSI
HSI16
HSE
PLL
HSE 32 MHz (external clock)
or 24 MHz (crystal)
32 MHz
(PLLVCO max = 96 MHz)
Range 1 (1.8 V)
4.2 MHz 16 MHz
Range 2 (1.5 V)
4.2 MHz
16 MHz
16 MHz
16 MHz
(PLLVCO max = 48 MHz)
Range 3 (1.2 V)
4.2 MHz
NA
8 MHz
4 MHz
(PLLVCO max = 24 MHz)
7.2.10
HSE clock security system (CSS)
The Clock security system can be activated on the HSE by software. In this case, the clock
detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is
stopped.
If an HSE clock failure is detected, this oscillator is automatically disabled and an CSSHSEI
interrupt (Clock Security System Interrupt) is generated to inform the software of the failure,
thus allowing the MCU to perform rescue operations. The CSSHSEI is linked to the
Cortex®-M0+ NMI (Non-Maskable Interrupt) exception vector.
Note:
Once the CSSHSE is enabled, if the HSE clock fails, the CSSHSE interrupt occurs and an
NMI is automatically generated. The NMI is executed indefinitely unless the CSSHSE
interrupt pending bit is cleared. As a consequence, the NMI interrupt service routine (ISR)
must clear the CSSHSE interrupt by setting the CSSHSEC bit in the RCC_CICR register.
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock to the MSI oscillator and the disabling of the HSE
oscillator. If the HSE oscillator clock is the clock entry of the PLL used as system clock when
the failure occurs, the PLL is disabled too.
7.2.11
LSE Clock Security System
Clock Security System can be activated on the LSE by software. This is done by writing the
CSSLSEON bit in the RCC_CSR register. This bit can be disabled by a hardware reset, an
RTC software reset, or after an LSE clock failure detection. CSSLSEON bit must be written
after the LSE and LSI clocks are enabled (LSEON and LSION set) and ready (LSERDY and
LSIRDY bits set by hardware), and after the RTC clock has been selected through the
RTCSEL bit.
The LSE CSS works in all modes: run, sleep, stop and standby.
If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied
to the RTC but the content of the registers does not change.
A wakeup is generated in standby mode. In any other modes, an interrupt can be sent to
wake-up the software (see Section 7.3.5).
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The software MUST then reset the CSSLSEON bit and stop the defective 32 kHz oscillator
by resetting LSEON bit. It can change the RTC clock source (LSI, HSE or no clock) through
the RTCSEL bit, or take any required action to secure the application.
7.2.12
RTC clock
The RTC has the same clock source which can be either the LSE, the LSI, or the HSE
1 MHz clock (HSE divided by a programmable prescaler). It is selected by programming the
RTCSEL[1:0] bits in the RCC_CSR register (see Section 7.3.21) and the RTCPRE[1:0] bits
in the RCC_CR register (see Section 7.3.1).
Once the RTC clock source have been selected, the only possible way of modifying the
selection is to set the RTCRST bit in the RCC_CSR register, or by a POR.
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in stop and
standby low power modes, and can be used as wakeup source. However, when the HSE is
the RTC clock source, the RTC cannot be used in the stop and standby low power modes.
To be able to read the RTC calendar register when the APB1 clock frequency is less than
seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar
time and date registers twice.
If the second read of the RTC_TR gives the same result as the first read, this ensures that
the data is correct. Otherwise a third read access must be done.
7.2.13
Watchdog clock
If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
7.2.14
Clock-out capability
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin (PA8 or PA9) using a configurable prescaler (1, 2, 4, 8, or 16). The
configuration registers of the corresponding GPIO port must be programmed in alternate
function mode. One of 7 clock signals can be selected as the MCO clock:
•
SYSCLK
•
HSI16
•
HSI48
•
MSI
•
HSE
•
PLL
•
LSI
•
LSE
The selection is controlled by the MCOSEL[3:0] bits of the RCC_CFGR register (see
Section 7.3.20).
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Reset and clock control (RCC)
7.2.15
RM0376
Internal/external clock measurement using TIM21
It is possible to indirectly measure the frequency of all on-board clock source generators by
means of the TIM21 channel 1 input capture, as represented on Figure 19.
Figure 19. Using TIM21 channel 1 input capture to measure
frequencies
7,B503>@
*3,2
06,
/6,
+6(B57&
/6(
7,0
7,
(75
/6(
7,
*3,2
069
TIM21 has an input multiplexer that selects which of the I/O or the internal clock is to trigger
the input capture. This selection is performed through the TI1_RMP [2:0] bits in the
TIM21_OR register.
The primary purpose of connecting the LSE to the channel 1 input capture is to be able to
accurately measure the HSI16 and MSI system clocks (for this, either the HSI16 or MSI
should be used as the system clock source). The number of HSI16 (MSI, respectively) clock
counts between consecutive edges of the LSE signal provides a measure of the internal
clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of
ppm’s), it is possible to determine the internal clock frequency with the same resolution, and
trim the source to compensate for manufacturing-process- and/or temperature- and voltagerelated frequency deviations.
The MSI and HSI16 oscillators both have dedicated user-accessible calibration bits for this
purpose.
The basic concept consists in providing a relative measurement (e.g. the HSI16/LSE ratio):
the precision is therefore closely related to the ratio between the two clock sources. The
higher the ratio, the better the measurement.
It is however not possible to have a good enough resolution when the MSI clock is low
(typically below 1 MHz). In this case, it is advised to:
•
accumulate the results of several captures in a row
•
use the timer’s input capture prescaler (up to 1 capture every 8 periods)
•
use the RTC_OUT signal at 512 Hz (when the RTC is clocked by the LSE) as the input
for the channel1 input capture. This improves the measurement precision
TIM21 can also be used to measure the LSI, MSI, or HSE_RTC: this is useful for
applications with no crystal. The ultralow power LSI oscillator has a wide manufacturing
process deviation: by measuring it as a function of the HSI16 clock source, its frequency
can be determined with the precision of the HSI16.The HSE_RTC frequency (HSE divided
by a programmable prescaler) being relatively high (1 MHz), the relative frequency
measurement is not very accurate. Its main purpose is consequently to obtain a rough
indication of the external crystal frequency. This can be useful to meet the requirements of
the IEC 60730/IEC 61335 standards, which require to be able to determine harmonic or
subharmonic frequencies (–50/+100% deviations).
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7.2.16
Reset and clock control (RCC)
Clock-independent system clock sources for TIM2/TIM21/TIM22
In a number of applications using the 32.768 kHz clock as RTC timebase, timebases
completely independently from the system clock are useful. This allows to schedule tasks
without having to take into account the processor state (the processor may be stopped or
executing at low, medium or full speed).
For this purpose, the LSE clock is internally redirected to the 3 timers’ ETR inputs, which are
used as additional clock sources. This gives up to three independent time bases (using the
auto-reload feature) with 1 or 2 compare additional channels for fractional events. For
instance, the TIM21 auto-reload interrupt can be programmed for a 1 second tick interrupt
with an additional interrupt occurring 250 ms after the main tick.
Note:
In this configuration, make sure that you have at least a ratio of 2 between the external clock
(LSE) and the APB clock. If the application uses an APB clock frequency lower than twice
the LSE clock frequency (typically LSE = 32.768 kHz, so twice LSE = 65.536 kHz), it is
mandatory to use the external trigger prescaler feature of the timer: it can divide the ETR
clock by up to 8.
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7.3
RM0376
RCC registers
Refer to Section 1.1 for a list of abbreviations used in register descriptions.
7.3.1
Clock control register (RCC_CR)
Address offset: 0x00
System Reset value: 0b0000 0000 00XX 0X00 0000 0011 0000 0000 where X is undefined
Power-on reset value: 0x0000 0300
Access: no wait state, word, half-word and byte access
31
Res.
15
Res.
30
Res.
14
Res.
29
Res.
13
Res.
28
Res.
12
Res.
27
Res.
11
Res.
26
25
Res.
PLL
RDY
24
PLLON
r
rw
10
9
8
Res.
MSI
RDY
MSION
r
rw
23
Res.
22
Res.
21
RTCPRE[1:0]
rw
7
Res.
6
Res.
20
rw
19
18
17
16
CSSHS
EON.
HSE
BYP
HSE
RDY
HSE
ON
rw
rw
r
rw
5
4
3
2
1
0
Res.
HSI16
DIVF
HSI16
DIVEN
HSI16
RDYF.
HSI16K
ERON
HSI16
ON
r
rw
r
rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 PLLRDY: PLL clock ready flag
This bit is set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: PLL enable bit
This bit is set and cleared by software to enable PLL.
Cleared by hardware when entering stop or standby mode. This bit can not be reset if the
PLL clock is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:20 RTCPRE[1:0] RTC prescaler
These bits are set and reset by software to obtain a 1 MHz clock from HSE. This prescaler
cannot be modified if HSE is enabled (HSEON = 1).These bits are reset by a power -on
reset,. Their value is not modified by a system reset.
00: HSE is divided by 2 for RTC clock
01: HSE is divided by 4 for RTC clock
10: HSE is divided by 8 for RTC clock
11: HSE is divided by 16 for RTC clock
Bit 19 CSSHSEON: Clock security system on HSE enable bit
This bit is set and cleared by software to enable the clock security system (CSS) on HSE.
When CSSHSEON is set, the clock detector is enabled by hardware when the HSE oscillator
is ready, and disabled by hardware if an oscillator failure is detected.
0: Clock security system OFF (clock detector OFF)
1: Clock security system ON (clock detector ON if HSE oscillator is stable, OFF otherwise)
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Reset and clock control (RCC)
Bit 18 HSEBYP: HSE clock bypass bit
This bit is set and cleared by software to bypass the oscillator with an external clock. The
external clock must be enabled with the HSEON bit, to be used by the device.
The HSEBYP bit can be written only if the HSE oscillator is disabled. This bit is reset by
power-on reset. Its value is not modified by system reset
0: HSE oscillator not bypassed
1: HSE oscillator bypassed with an external clock
Bit 17 HSERDY: HSE clock ready flag
This bit is set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is
cleared, HSERDY goes low after 6 HSE oscillator clock cycles.
0: HSE oscillator not ready
1: HSE oscillator ready
Bit 16 HSEON: HSE clock enable bit
This bit is set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering stop or standby mode. This bit
cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 MSIRDY: MSI clock ready flag
This bit is set by hardware to indicate that the MSI oscillator is stable.
0: MSI oscillator not ready
1: MSI oscillator ready
Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles.
Bit 8 MSION: MSI clock enable bit
This bit is set and cleared by software.
Set by hardware to force the MSI oscillator ON when exiting from stop or standby mode, or in
case of a failure of the HSE oscillator used directly or indirectly as system clock. This bit
cannot be cleared if the MSI is used as system clock.
0: MSI oscillator OFF
1: MSI oscillator ON
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 HSI16DIVF HSI16 divider flag
This bit is set and reset by hardware. As a write in HSI16DIVEN has not an immediate effect
on the frequency, this flag indicates the current status of the HSI16 divider.
0: 16 MHz HSI clock not divided
1: 16 MHz HSI clock divided by 4
Bit 3 HSI16DIVEN HSI16 divider enable bit
This bit is set and reset by software to enable/disable the 16 MHz HSI divider by 4. It can be
written anytime.
0: no 16 MHz HSI division requested
1: 16 MHz HSI division by 4 requested
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RM0376
Bit 2 HSI16RDYF: Internal high-speed clock ready flag
This bit is set by hardware to indicate that the HSI 16 MHz oscillator is stable. After the
HSI16ON bit is cleared, HSI16RDY goes low after 6 HSI16 clock cycles.
0: HSI 16 MHz oscillator not ready
1: HSI 16 MHz oscillator ready
Bit 1 HSI16KERON: High-speed internal clock enable bit for some IP kernels
This bit is set and reset by software to force the HSI 16 MHz RC ON, even in stop mode, so
that it can be quickly available as kernel clock for USARTs or I2C1. This bit has no effect on
the value of HSI16ON.
0: HSI 16 MHz oscillator not forced ON
1: HSI 16 MHz oscillator forced ON even in stop mode
Bit 0 HSI16ON: 16 MHz high-speed internal clock enable
This bit is set and cleared by software. It cannot be cleared if the 16 MHz HSI is used directly
or indirectly as system clock.
0: HSI16 oscillator OFF
1: HSI16 oscillator ON
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Reset and clock control (RCC)
7.3.2
Internal clock sources calibration register (RCC_ICSCR)
Address offset: 0x04
Reset value: 0x00XX B0XX where X is undefined.
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
MSITRIM[7:0]
20
19
18
17
16
MSICAL[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
r
r
r
r
r
r
MSIRANGE[2:0]
rw
rw
HSI16TRIM[4:0]
rw
HSI16CAL[7:0]
r
r
Bits 31:24 MSITRIM[7:0]: MSI clock trimming
These bits are set by software to adjust MSI calibration.
These bits provide an additional user-programmable trimming value that is added to the
MSICAL[7:0] bits. They can be programmed to compensate for the variations in voltage and
temperature that influence the frequency of the internal MSI RC.
Bits 23:16 MSICAL[7:0]: MSI clock calibration
These bits are automatically initialized at startup.
Bits 15:13 MSIRANGE[2:0]: MSI clock ranges
These bits are set by software to choose the frequency range of MSI.7 frequency ranges are
available:
000: range 0 around 65.536 kHz
001: range 1 around 131.072 kHz
010: range 2 around 262.144 kHz
011: range 3 around 524.288 kHz
100: range 4 around 1.048 MHz
101: range 5 around 2.097 MHz (reset value)
110: range 6 around 4.194 MHz
111: not allowed
Bits 12:8 HSI16TRIM[4:0]: High speed internal clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSI16CAL[7:0] bits. They can be programmed to compensated for the variations in voltage
and temperature that influence the frequency of the internal HSI16 RC.
Bits 7:0 HSI16CAL[7:0] Internal high speed clock calibration
These bits are initialized automatically at startup.
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7.3.3
RM0376
Clock recovery RC register (RCC_CRRCR)
Address: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
1
0
HSI48CAL[7:0]
r
r
r
r
r
r
r
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
HSI48RDY HSI48ON
r
r
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 HSI48CAL[7:0]: 48 MHz HSI clock calibration
These bits are read-only. They are set by hardware by loading option bytes during system
reset.
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 HSI48RDY: 48MHz HSI clock ready flag
This bit is set by hardware to indicate that the 48 MHz RC oscillator is stable. It requires 6
48 MHz RC oscillator clock cycles to fall down after HSION reset.
0: 48 MHz HSI clock not ready
1: 48 MHz HSI clock ready
Bit 0 HSI48ON: 48MHz HSI clock enable bit
This bit is set and cleared by software.
0: 48 MHz HSI clock OFF
1: 48 MHz HSI clock ON
7.3.4
Clock configuration register (RCC_CFGR)
Address offset: 0x0C
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.
31
30
Res.
29
28
27
MCOPRE[2:0]
26
25
24
MCOSEL[3:0]
23
22
21
PLLDIV[1:0]
20
19
18
PLLMUL[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
STOP
WUCK.
Res.
rw
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PPRE2[2:0]
rw
rw
PPRE1[2:0]
rw
rw
rw
HPRE[3:0]
rw
rw
rw
DocID025941 Rev 1
rw
SWS[1:0]
rw
r
r
17
16
Res.
PLL
SRC
rw
1
0
SW[1:0]
rw
rw
RM0376
Reset and clock control (RCC)
Bits 31 Reserved, must be kept at reset value.
Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler
These bits are set and cleared by software.
It is highly recommended to change this prescaler before MCO output is enabled.
000: MCO is divided by 1
001: MCO is divided by 2
010: MCO is divided by 4
011: MCO is divided by 8
100: MCO is divided by 16
Others: not allowed
Bits 27:24 MCOSEL[3:0]: Microcontroller clock output selection
These bits are set and cleared by software.
0000: MCO output disabled, no clock on MCO
0001: SYSCLK clock selected
0010: HSI16 oscillator clock selected
0011: MSI oscillator clock selected
0100: HSE oscillator clock selected
0101: PLL clock selected
0110: LSI oscillator clock selected
0111: LSE oscillator clock selected
1000: HSI48 oscillator clock selected
Others: reserved
Note: This clock output may have some truncated cycles at startup or during MCO clock
source switching.
Bits 23:22 PLLDIV[1:0]: PLL output division
These bits are set and cleared by software to control PLL output clock division from PLL
VCO clock. These bits can be written only when the PLL is disabled.
00: not allowed
01: PLL clock output = PLLVCO / 2
10: PLL clock output = PLLVCO / 3
11: PLL clock output = PLLVCO / 4
Bits 21:18 PLLMUL[3:0]: PLL multiplication factor
These bits are written by software to define the PLL multiplication factor to generate the PLL
VCO clock. These bits can be written only when the PLL is disabled.
0000: PLLVCO = PLL clock entry x 3
0001: PLLVCO = PLL clock entry x 4
0010: PLLVCO = PLL clock entry x 6
0011: PLLVCO = PLL clock entry x 8
0100: PLLVCO = PLL clock entry x 12
0101: PLLVCO = PLL clock entry x 16
0110: PLLVCO = PLL clock entry x 24
0111: PLLVCO = PLL clock entry x 32
1000: PLLVCO = PLL clock entry x 48
others: not allowed
Caution: The PLL VCO clock frequency must not exceed 96 MHz when the product is in
Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
in Range 3.
Bit 17 Reserved, must be kept at reset value.
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RM0376
Bit 16 PLLSRC: PLL entry clock source
This bit is set and cleared by software to select PLL clock source. This bit can be written
only when PLL is disabled.
0: HSI16 oscillator clock selected as PLL input clock
1: HSE oscillator clock selected as PLL input clock
Note: The PLL minimum input clock frequency is 2 MHz.
Bit 15 STOPWUCK: Wake-up from stop clock selection
This bit is set and cleared by software to select the wake-up from stop clock.
0: internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from stop clock
1: internal 16 MHz (HSI16) oscillator selected as wake-up from stop clock (or HSI16/4 if
HSI16DIVEN=1)
Bit 14 Reserved, must be kept at reset value.
Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2)
These bits are set and cleared by software to control the division factor of the APB highspeed clock (PCLK2).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Bits 10:8 PPRE1[2:0]: APB low-speed prescaler (APB1)
These bits are set and cleared by software to control the division factor of the APB lowspeed clock (PCLK1).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
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Reset and clock control (RCC)
Bits 7:4 HPRE[3:0]: AHB prescaler
These bits are set and cleared by software to control the division factor of the AHB clock.
Caution: Depending on the device voltage range, the software has to set correctly these bits
to ensure that the system frequency does not exceed the maximum allowed
frequency (for more details please refer to the Dynamic voltage scaling
management section in the PWR chapter.) After a write operation to these bits and
before decreasing the voltage range, this register must be read to be sure that the
new value has been taken into account.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Bits 3:2 SWS[1:0]: System clock switch status
These bits are set and cleared by hardware to indicate which clock source is used as
system clock.
00: MSI oscillator used as system clock
01: HSI16 oscillator used as system clock
10: HSE oscillator used as system clock
11: PLL used as system clock
Bits 1:0 SW[1:0]: System clock switch
These bits are set and cleared by software to select SYSCLK source.
Set by hardware to force MSI selection when leaving standby mode or in case of failure of
the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is
enabled).
00: MSI oscillator used as system clock
01: HSI16 oscillator used as system clock
10: HSE oscillator used as system clock
11: PLL used as system clock
7.3.5
Clock interrupt enable register (RCC_CIER)
Address: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CSS
LSE
HSI48
RDYIE
MSI
RDYIE
PLL
RDYIE
LSE
RDYIE
LSI
RDYIE
r
r
r
r
r
r
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HSI16
RDYIE RDYIE
r
r
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RM0376
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 CSSLSE: LSE CSS interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the Clock
Security System on external 32 kHz oscillator.
0: LSE CSS interrupt disabled
1: LSE CSS interrupt enabled
Bit 6 HSI48RDYIE: HSI48 ready interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the HSI48
oscillator stabilization.
0: HSI48 ready interrupt disabled
1: HSI48 ready interrupt enabled
Bit 5 MSIRDYIE: MSI ready interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the MSI
oscillator stabilization.
0: MSI ready interrupt disabled
1: MSI ready interrupt enabled
Bit 4 PLLRDYIE: PLL ready interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 3 HSERDYIE: HSE ready interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the HSE
oscillator stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 2 HSI16RDYIE: HSI16 ready interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the HSI16
oscillator stabilization.
0: HSI16 ready interrupt disabled
1: HSI16 ready interrupt enabled
Bit 1 LSERDYIE: LSE ready interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the LSE
oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 0 LSIRDYIE: LSI ready interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the LSI
oscillator stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
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Reset and clock control (RCC)
7.3.6
Clock interrupt flag register (RCC_CIFR)
Address: 0x14
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CSS
HSEF
CSS
LSEF
HSI48
RDYF
MSI
RDYF
PLL
RDYF
HSE
RDYF
HSI16
RDYF
LSE
RDYF
LSI
RDYF
r
r
r
r
r
r
r
r
r
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 CSSHSEF: Clock Security System Interrupt flag
This bit is reset by software by writing the CSSHSEC bit. It is set by hardware in case of HSE
clock failure.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bit 7 CSSLSEF: LSE Clock Security System Interrupt flag
This bit is reset by software by writing the CSSLSEC bit. It is set by hardware in case of LSE
clock failure and the CSSLSE is set.
0: No failure detected on LSE clock failure
1: Failure detected on LSE clock failure
Bit 6 HSI48RDYF: HSI48 ready interrupt flag
This bit is reset by software by writing the HSI48RDYC bit. It is set by hardware when the
CSS becomes stable and the HSI48RDYIE is set.
0: No clock ready interrupt caused by HSI48 clock failure
1: Clock ready interrupt caused by HSI48 clock failure
Bit 5 MSIRDYF: MSI ready interrupt flag
This bit is reset by software by writing the MSIRDYC bit. It is set by hardware when the MSI
clock becomes stable and the MSIRDYIE is set.
0: No clock ready interrupt caused by MSI clock failure
1: Clock ready interrupt caused by MSI clock failure
Bit 4 PLLRDYF: PLL ready interrupt flag
This bit is reset by software by writing the PLLRDYC bit. It is set by hardware when the PLL
clock becomes stable and the PLLRDYIE is set.
0: No clock ready interrupt caused by PLL clock failure
1: Clock ready interrupt caused by PLL clock failure
Bit 3 HSERDYF: HSE ready interrupt flag
This bit is reset by software by writing the HSERDYC bit. It is set by hardware when the HSE
clock becomes stable and the HSERDYIE is set.
0: No clock ready interrupt caused by HSE clock failure
1: Clock ready interrupt caused by HSE clock failure
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Reset and clock control (RCC)
RM0376
Bit 2 HSI16RDYF: HSI16 ready interrupt flag
This bit is reset by software by writing the HSI16RDYC bit. It is set by hardware when the
HSE clock becomes stable and the HSI16RDYIE is set.
0: No clock ready interrupt caused by HSI16 clock failure
1: Clock ready interrupt caused by HSI16 clock failure
Bit 1 LSERDYF: LSE ready interrupt flag
This bit is reset by software by writing the LSERDYC bit. It is set by hardware when the LSE
clock becomes stable and the LSERDYIE is set.
0: No clock ready interrupt caused by LSE clock failure
1: Clock ready interrupt caused by LSE clock failure
Bit 0 LSIRDYF: LSI ready interrupt flag
This bit is reset by software by writing the LSIRDYC bit. It is set by hardware when the LSI
clock becomes stable and the LSIRDYIE is set.
0: No clock ready interrupt caused by LSI clock failure
1: Clock ready interrupt caused by LSI clock failure
7.3.7
Clock interrupt clear register (RCC_CICR)
Address: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
CSS
HSEC
CSS
LSEC
HSI48
RDYC
MSI
RDYC
PLL
RDYC
HSE
RDYC
HSI16
RDYC
LSE
RDYIC
LSI
RDYC
r
r
r
r
r
r
r
r
r
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 CSSHSEC: Clock Security System Interrupt clear
This bit is set by software to clear the CSSHSEF flag. It is reset by hardware.
0: No effect
1: CSSHSEF flag cleared
Bit 7 CSSLSEC: LSE Clock Security System Interrupt clear
This bit is set by software to clear the CSSLSEF flag. It is reset by hardware.
0: No effect
1: CSSLSEF flag cleared
Bit 6 HSI48RDYC: HSI48 ready Interrupt clear
This bit is set by software to clear the HSI48RDYF flag. It is reset by hardware.
0: No effect
1: HSI48RDYF flag cleared
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Reset and clock control (RCC)
Bit 5 MSIRDYC: MSI ready Interrupt clear
This bit is set by software to clear the MSIRDYF flag. It is reset by hardware.
0: No effect
1: MSIRDYF flag cleared
Bit 4 PLLRDYC: PLL ready Interrupt clear
This bit is set by software to clear the PLLRDYF flag. It is reset by hardware.
0: No effect
1: PLLRDYF flag cleared
Bit 3 HSERDYC: HSE ready Interrupt clear
This bit is set by software to clear the HSERDYF flag. It is reset by hardware.
0: No effect
1: HSERDYF flag cleared
Bit 2 HSI16RDYC: HSI16 ready Interrupt clear
This bit is set by software to clear the HSI16RDYF flag. It is reset by hardware.
0: No effect
1: HSI16RDYF flag cleared
Bit 1 LSERDYC: LSE ready Interrupt clear
This bit is set by software to clear the LSERDYF flag. It is reset by hardware.
0: No effect
1: LSERDYF flag cleared
Bit 0 LSIRDYC: LSI ready Interrupt clear
This bit is set by software to clear the LSIRDYF flag. It is reset by hardware.
0: No effect
1: LSIRDYF flag cleared
7.3.8
GPIO reset register (RCC_IOPRSTR)
Address: 0x1C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
IOPH
RST
Res.
IOPD
RST
IOPC
RST
IOPB
RST
IOPA
RST
rw
rw
rw
rw
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 IOPHRST: I/O port H reset
This bit is set and cleared by software.
0: no effect
1: resets I/O port H
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Bits 6:4 Reserved, must be kept at reset value.
Bit 3 IOPDRST: I/O port D reset
This bit is set and cleared by software.
0: no effect
1: resets I/O port D
Bit 2 IOPCRST: I/O port C reset
This bit is set and cleared by software.
0: no effect
1: resets I/O port C
Bit 1 IOPBRST: I/O port B reset
This bit is set and cleared by software.
0: no effect
1: resets I/O port B
Bit 0 IOPARST: I/O port A reset
This bit is set and cleared by software.
0: no effect
1: resets I/O port A
7.3.9
AHB peripheral reset register (RCC_AHBRSTR)
Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRYP
RST
Res.
Res.
Res.
RNGR
ST
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
3
2
1
0
Res.
CRC
RST
Res.
MIF
RST
Res.
DMA
RST
rw
Res.
Res.
rw
Res.
Res.
rw
Res.
Res.
rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 CRYPTRST: Crypto module reset
This bit is set and reset by software.
0: no effect
1: resets CRYPTO module
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 RNGRST: Random Number Generator module reset
This bit is set and reset by software.
0: no effect
1: resets RNG module
Bits 19:17 Reserved, must be kept at reset value.
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4
Res.
16
rw
Res.
Res.
rw
RM0376
Reset and clock control (RCC)
Bit 16 TSCRST: Touch Sensing reset
This bit is set and reset by software.
0: no effect
1: resets Touch sensing module
Bits 15: 13 Reserved, must be kept at reset value.
Bit 12 CRCRST: Test integration module reset
This bit is set and reset by software.
0: no effect
1: resets test integration module
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 MIFRST: Memory interface reset
This bit is set and reset by software.
This reset can be activated only when the E2 is in IDDQ mode.
0: no effect
1: resets memory interface
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 DMARST: DMA reset
This bit is set and reset by software.
0: no effect
1: resets DMA
7.3.10
APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x24
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DBG
RST
Res.
Res.
Res.
Res.
Res.
Res.
6
5
4
3
2
1
0
Res.
TIM22
RST
Res.
TIM21
RST
Res.
SYSCF
GRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
Res.
USART1
RST
Res.
SPI1
RST
Res.
ADC
RST
rw
rw
rw
Res.
Res.
Res.
rw
rw
Res.
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DBGRST: DBG reset
This bit is set and cleared by software.
0: No effect
1: Resets DBG
Bits 21:15 Reserved, must be kept at reset value.
Bit 14 USART1RST: USART1 reset
This bit is set and cleared by software.
0: No effect
1: Reset USART1
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Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI 1 reset
This bit is set and cleared by software.
0: No effect
1: Reset SPI 1
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 ADCRST: ADC interface reset
This bit is set and cleared by software.
0: No effect
1: Reset ADC interface
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 TIM22RST: TIM22 timer reset
This bit is set and cleared by software.
0: No effect
1: Reset TIM22 timer
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 TIM21RST: TIM21 timer reset
This bit is set and cleared by software.
0: No effect
1: Reset TIM21 timer
Bit 1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: System configuration controller reset
This bit is set and cleared by software.
0: No effect
1: Reset System configuration controller
7.3.11
APB1 peripheral reset register (RCC_APB1RSTR)
Address offset: 0x28
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
LPTIM1
RST
30
29
28
27
Res.
DACR
ST
PWR
RST
CRS
RST
rw
rw
rw
13
12
11
Res.
WWDG
RST
rw
15
14
Res.
SPI2
RST
rw
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rw
26
Res.
10
Res.
25
24
Res.
9
Res.
8
Res.
Res.
23
22
21
USBRST
I2C2
RST
I2C1
RST
rw
rw
rw
7
6
5
4
Res.
TIM6
RST
Res.
Res.
rw
20
Res.
rw
DocID025941 Rev 1
19
Res.
3
Res.
18
17
LPUART1 USART2
RST
RST
16
Res.
rw
rw
2
1
0
Res.
TIM2
RST
Res.
rw
RM0376
Reset and clock control (RCC)
Bit 31 LPTIM1RST: Low power timer reset
This bit is set and cleared by software.
0: No effect
1: Resets low power timer
Bit 30 Reserved, must be kept at reset value.
Bit 29 DACRST: DAC interface reset
This bit is set and cleared by software.
0: No effect
1: Resets DAC interface
Bit 28 PWRRST: Power interface reset
This bit is set and cleared by software.
0: No effect
1: Reset power interface
Bit 27 CRSRST: Clock recovery system reset
This bit is set and cleared by software.
0: No effect
1: Resets Clock recovery system
Bits 26:24 Reserved, must be kept at reset value.
Bit 23 USBRST: USB reset
This bit is set and cleared by software.
0: No effect
1: Reset USB
Bit 22 I2C2RST: I2C2 reset
This bit is set and cleared by software.
0: No effect
1: Resets I2C2
Bit 21 I2C1RST: I2C1 reset
This bit is set and cleared by software.
0: No effect
1: Resets I2C1
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 LPUART1RST: LPUART1 reset
This bit is set and cleared by software.
0: No effect
1: Resets LPUART1
Bit 17 UART2RST: UART2 reset
This bit is set and cleared by software.
0: No effect
1: Resets UART2
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2RST: SPI2 reset
This bit is set and cleared by software.
0: No effect
1: Resets SPI2
Bits 13:12 Reserved, must be kept at reset value.
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RM0376
Bit 11 WWDGRST: Window watchdog reset
This bit is set and cleared by software.
0: No effect
1: Resets window watchdog
Bits 10:9 Reserved, must be kept at reset value.
Bits 8:5 Reserved, must be kept at reset value.
Bit 4 TIM6RST: Timer 6 reset
Set and cleared by software.
0: No effect
1: Resets timer6
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 TIM2RST: Timer2 reset
Set and cleared by software.
0: No effect
1: Resets timer2
7.3.12
GPIO clock enable register (RCC_IOPENR)
Address: 0x2C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
IOPH
EN
Res.
Res.
Res.
IOPD
EN
IOPC
EN
IOPB
EN
IOPA
EN
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 IOPHEN: I/O port H clock enable bit
This bit is set and cleared by software.
0: port H clock disabled
1: port H clock enabled
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 IOPDEN: I/O port D clock enable bit
This bit is set and cleared by software.
0: port D clock disabled
1: port D clock enabled
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Reset and clock control (RCC)
Bit 2 IOPCEN: IO port C clock enable bit
This bit is set and cleared by software.
0: port C clock disabled
1: port C clock enabled
Bit 1 IOPBEN: IO port B clock enable bit
This bit is set and cleared by software.
0: port B clock disabled
1: port B clock enabled
Bit 0 IOPAEN: IO port A clock enable bit
This bit is set and cleared by software.
0: port A clock disabled
1: port A clock enabled
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7.3.13
RM0376
AHB peripheral clock enable register (RCC_AHBENR)
Address offset: 0x30
Reset value: 0x0000 0100
Access: no wait state, word, half-word and byte access
When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31
30
29
28
27
26
25
24
CRYP
EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
Res.
Res.
Res.
CRC
EN
Res.
Res.
Res.
23
22
21
20
RNGE
N
Res.
Res.
Res.
8
7
6
5
MIF
EN
Res.
Res.
Res.
rw
rw
18
17
16
TOUCH
EN
Res.
Res.
Res.
4
3
2
1
0
Res.
Res.
Res.
Res.
DMA
EN
rw
rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 CRYPEN: Crypto clock enable bit
This bit is set and reset by software.
0: Crypto clock disabled
1: Crypto clock enabled
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 RNGEN: Random Number Generator clock enable bit
This bit is set and reset by software.
0: RNG clock disabled
1: RNG clock enabled
Bits 19:17 Reserved, must be kept at reset value.
Bit 16 TOUCHEN: Touch Sensing clock enable bit
This bit is set and reset by software.
0: Touch sensing clock disabled
1: Touch sensing clock enabled
Bits 15: 13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable bit
This bit is set and reset by software.
0: Test integration module clock disabled
1: Test integration module clock enabled
Bits 11:9 Reserved, must be kept at reset value.
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rw
RM0376
Reset and clock control (RCC)
Bit 8 MIFEN: NVM interface clock enable bit
This bit is set and reset by software.
This reset can be activated only when the NVM is in power-down mode.
0: NVM interface clock disabled
1: NVM interface clock enabled
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 DMAEN: DMA clock enable bit
This bit is set and reset by software.
0: DMA clock disabled
1: DMA clock enabled
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7.3.14
RM0376
APB2 peripheral clock enable register (RCC_APB2ENR)
Address: 0x34
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB2
domain is on going. In this case, wait states are inserted until the access to APB2 peripheral
is finished.
Note:
When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DBG
EN
Res.
Res.
Res.
Res.
Res.
Res.
6
5
4
3
2
1
0
Res.
TIM22
EN
Res.
TIM21
EN
Res.
SYSCF
EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
Res.
USART1
EN
Res.
SPI1
EN
Res.
ADC
EN
Res.
MIFI
EN
rw
rw
rw
Res.
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DBGEN: DBG clock enable bit
This bit is set and cleared by software.
0: DBG clock disabled
1: DBG clock enabled
Bits 21:15 Reserved, must be kept at reset value.
Bit 14 USART1EN: USART1 clock enable bit
This bit is set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable bit
This bit is set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 ADCEN: ADC clock enable bit
This bit is set and cleared by software.
0: ADC clock disabled
1: ADC clock enabled
Bit 8 Reserved, must be kept at reset value.
Bit 7 MIFIEN: MiFaRe Firewall clock enable bit
This bit is set by software and cleared by hardware.
0: MIFI clock disabled
1: MIFI clock enabled
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rw
RM0376
Reset and clock control (RCC)
Bit 6 Reserved, must be kept at reset value.
Bit 5 TIM22EN: TIM22 timer clock enable bit
This bit is set and cleared by software.
0:TIM22 clock disabled
1: TIM22 clock enabled
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 TIM21EN: TIM21 timer clock enable bit
This bit is set and cleared by software.
0: TIM21 clock disabled
1: TIM21 clock enabled
Bit 1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: System configuration controller clock enable bit
This bit is set and cleared by software.
0: System configuration controller clock disabled
1: System configuration controller clock enabled
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Reset and clock control (RCC)
7.3.15
RM0376
APB1 peripheral clock enable register (RCC_APB1ENR)
Address: 0x38
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
Note:
31
When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
30
29
28
27
Res.
DACE
N
PWR
EN
CRSE
N
rw
rw
rw
15
14
13
12
11
Res.
SPI2
EN
Res.
WWDG
EN
LPTIM1
EN
rw
rw
Res.
rw
26
25
24
Res.
Res.
Res.
10
9
8
Res.
Res.
Res.
23
22
21
USBEN
I2C2
EN
I2C1
EN
rw
rw
rw
7
6
Res.
Res.
rw
Bit 30 Reserved, must be kept at reset value.
Bit 29 DACEN: DAC interface clock enable bit
This bit is set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enabled
Bit 28 PWREN: Power interface clock enable bit
This bit is set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enabled
Bit 27 CRSEN: Clock recovery system clock enable bit
This bit is set and cleared by software.
0: Clock recovery system clock disabled
1: Clock recovery system clock enabled
Bits 26:24 Reserved, must be kept at reset value.
Bit 23 USBEN: USB clock enable bit
This bit is set and cleared by software.
0: USB clock disabled
1: USB clock enabled
Bit 22 I2C2EN: I2C2 clock enable bit
This bit is set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
DocID025941 Rev 1
19
Res.
Res.
5
4
3
Res.
TIM6
EN
rw
Bit 31 LPTIM1EN: Low power timer clock enable bit
This bit is set and cleared by software.
0: Low power timer clock disabled
1: Low power timer clock enabled
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20
Res.
18
17
LPUART1 USART2
EN
EN
16
Res.
rw
rw
2
1
0
Res.
TIM2
EN
Res.
rw
RM0376
Reset and clock control (RCC)
Bit 21 I2C1EN: I2C1 clock enable bit
This bit is set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 LPUART1EN: LPUART1 clock enable bit
This bit is set and cleared by software.
0: LPUART1 clock disabled
1: LPUART1 clock enabled
Bit 17 UART2EN: UART2 clock enable bit
This bit is set and cleared by software.
0: UART2 clock disabled
1: UART2 clock enabled
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2EN: SPI2 clock enable bit
This bit is set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable bit
This bit is set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bits 10:9 Reserved, must be kept at reset value.
Bits 8:5 Reserved, must be kept at reset value.
Bit 4 TIM6EN: Timer 6 clock enable bit
Set and cleared by software.
0: Timer 6 clock disabled
1: Timer 6 clock enabled
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 TIM2EN: Timer2 clock enable bit
Set and cleared by software.
0: Timer2 clock disabled
1: Timer2 clock enabled
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Reset and clock control (RCC)
7.3.16
RM0376
GPIO clock enable in sleep mode register (RCC_IOPSMENR)
Address: 0x3C
Reset value: 0x0000 008F
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
IOPHS
MEN
Res.
IOPDS
MEN
IOPCS
MEN
IOPBS
MEN
IOPAS
MEN
rw
rw
rw
rw
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31: 8 Reserved, must be kept at reset value.
Bit 7 IOPHSMEN: Port H clock enable during sleep mode bit
This bit is set and cleared by software.
0: Port H clock is disabled in sleep mode
1: Port H clock is enabled in sleep mode (if enabled by IOPHEN)
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 IOPDSMEN: Port D clock enable during sleep mode bit
This bit is set and cleared by software.
0: Port D clock is disabled in sleep mode
1: Port D clock is enabled in sleep mode (if enabled by IOPDEN)
Bit 2 IOPCSMEN: Port C clock enable during sleep mode bit
This bit is set and cleared by software.
0: Port C clock is disabled in sleep mode
1: Port C clock is enabled in sleep mode (if enabled by IOPCEN)
Bit 1 IOPBSMEN: Port B clock enable during sleep mode bit
This bit is set and cleared by software.
0: Port B clock is disabled in sleep mode
1: Port B clock is enabled in sleep mode (if enabled by IOPBEN)
Bit 0 IOPASMEN: Port A clock enable during sleep mode bit
This bit is set and cleared by software.
0: Port A clock is disabled in sleep mode
1: Port A clock is enabled in sleep mode (if enabled by IOPAEN)
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Reset and clock control (RCC)
7.3.17
AHB peripheral clock enable in sleep mode
register (RCC_AHBSMENR)
Address: 0x40
Reset value: 0x0111 1301
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
CRYP
SMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
Res.
Res.
Res.
CRC
SMEN
Res.
Res.
23
22
21
20
RNGS
MEN
Res.
Res.
Res.
8
7
6
5
SRAM
SMEN
MIF
SMEN
Res.
Res.
Res.
rw
rw
rw
rw
19
18
17
16
TSCSM
EN
Res.
Res.
Res.
4
3
2
1
0
Res.
Res.
Res.
Res.
DMA
SMEN
rw
rw
rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 CRYPTSMEN: Crypto clock enable during sleep mode bit
This bit is set and reset by software.
0: Crypto clock disabled in sleep mode
1: Crypto clock enabled in sleep mode
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 RNGSMEN: Random Number Generator clock enable during sleep mode bit
This bit is set and reset by software.
0: RNG clock disabled in sleep mode
1: RNG clock enabled in sleep mode (if enabled by RNGEN)
Bits 19:17 Reserved, must be kept at reset value.
Bit 16 TSCSMEN: Touch Sensing clock enable during sleep mode bit
This bit is set and reset by software.
0: Touch Sensing clock disabled in sleep mode
1: Touch sensing clock enabled in sleep mode (if enabled by TOUCHEN)
Bits 15: 13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN: CRC clock enable during sleep mode bit
This bit is set and reset by software.
0: Test integration module clock disabled in sleep mode
1: Test integration module clock enabled in sleep mode (if enabled by CRCEN)
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 SRAMSMEN: SRAM interface clock enable during sleep mode bit
This bit is set and reset by software.
0: NVM interface clock disabled in sleep mode
1: NVM interface clock enabled in sleep mode
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RM0376
Bit 8 MIFSMEN: NVM interface clock enable during sleep mode bit
This bit is set and reset by software.
0: NVM interface clock disabled in sleep mode
1: NVM interface clock enabled in sleep mode
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 DMASMEN: DMA clock enable during sleep mode bit
This bit is set and reset by software.
0: DMA clock disabled in sleep mode
1: DMA clock enabled in sleep mode
7.3.18
APB2 peripheral clock enable in sleep mode
register (RCC_APB2SMENR)
Address: 0x44
Reset value: 0x0040 5225.
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DBG
SMEN
Res.
Res.
Res.
Res.
Res.
Res.
6
5
4
3
2
1
0
Res.
TIM22
SMEN
Res.
TIM21
SMEN
Res.
SYSCF
SMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
Res.
USART1
SMEN
Res.
SPI1
SMEN
Res.
ADC
SMEN
rw
rw
rw
Res.
Res.
Res.
rw
Res.
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DBGSMEN: DBG clock enable during sleep mode bit
This bit is set and cleared by software.
0: DBG clock disabled in sleep mode
1: DBG clock enabled in sleep mode (if enabled by DBGEN)
Bits 21:15 Reserved, must be kept at reset value.
Bit 14 USART1SMEN: USART1 clock enable during sleep mode bit
This bit is set and cleared by software.
0: USART1 clock disabled in sleep mode
1: USART1 clock enabled in sleep mode (if enabled by USART1EN)
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1SMEN: SPI1 clock enable during sleep mode bit
This bit is set and cleared by software.
0: SPI1 clock disabled in sleep mode
1: SPI1 clock enabled in sleep mode (if enabled by SPI1EN)
Bits 11:10 Reserved, must be kept at reset value.
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rw
RM0376
Reset and clock control (RCC)
Bit 9 ADCSMEN: ADC clock enable during sleep mode bit
This bit is set and cleared by software.
0: ADC clock disabled in sleep mode
1: ADC clock enabled in sleep mode (if enabled by ADCEN)
Bit 8:6 Reserved, must be kept at reset value.
Bit 5 TIM22SMEN: TIM22 timer clock enable during sleep mode bit
This bit is set and cleared by software.
0:TIM22 clock disabled in sleep mode
1: TIM22 clock enabled in sleep mode (if enabled by TIM22EN)
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 TIM21SMEN: TIM21 timer clock enable during sleep mode bit
This bit is set and cleared by software.
0: TIM21 clock disabled in sleep mode
1: TIM21 clock enabled in sleep mode (if enabled by TIM21EN)
Bit 1 Reserved, must be kept at reset value.
Bit 0 SYSCFGSMEN: System configuration controller clock enable during sleep mode bit
This bit is set and cleared by software.
0: System configuration controller clock disabled in sleep mode
1: System configuration controller clock enabled in sleep mode
7.3.19
APB1 peripheral clock enable in sleep mode
register (RCC_APB1SMENR)
Address: 0x48
Reset value: 0xB8E6 4A11
Note:
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
LPTIM1
SMEN
Res.
DACS
MEN
PWR
SMEN
CRSS
MEN
Res.
Res.
Res.
USBS
MEN
I2C2
SMEN
I2C1
SMEN
Res.
Res.
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
SPI2
SMEN
Res.
Res.
WWDG
SMEN
Res.
Res.
Res.
Res.
Res.
Res.
TIM6
SMEN
Res.
Res.
Res.
TIM2
SMEN
rw
rw
rw
rw
18
17
16
LPUART1 USART2
SMEN
SMEN
rw
Res.
rw
Bit 31 LPTIM1SMEN: Low power timer clock enable during sleep mode bit
This bit is set and cleared by software.
0: Low power timer clock disabled in sleep mode
1: Low power timer clock enabled in sleep mode (if enabled by LPTIM1EN)
Bit 30 Reserved, must be kept at reset value.
Bit 29 DACSMEN: DAC interface clock enable during sleep mode bit
This bit is set and cleared by software.
0: DAC interface clock disabled in sleep mode
1: DAC interface clock enabled in sleep mode (if enabled by DACEN)
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Bit 28 PWRSMEN: Power interface clock enable during sleep mode bit
This bit is set and cleared by software.
0: Power interface clock disabled in sleep mode
1: Power interface clock enabled in sleep mode (if enabled by PWREN)
Bit 27 CRSSMEN: Clock recovery system clock enable during sleep mode bit
This bit is set and cleared by software.
0: Clock recovery system clock disabled in sleep mode
1: Clock recovery system clock enabled in sleep mode (if enabled by CRSEN)
Bits 26:24 Reserved, must be kept at reset value.
Bit 23 USBSMEN: USB clock enable during sleep mode bit
This bit is set and cleared by software.
0: USB clock disabled in sleep mode
1: USB clock enabled in sleep mode (if enabled by USBEN)
Bit 22 I2C2SMEN: I2C2 clock enable during sleep mode bit
This bit is set and cleared by software.
0: I2C2 clock disabled in sleep mode
1: I2C2 clock enabled in sleep mode (if enabled by I2C2EN)
Bit 21 I2C1SMEN: I2C1 clock enable during sleep mode bit
This bit is set and cleared by software.
0: I2C1 clock disabled in sleep mode
1: I2C1 clock enabled in sleep mode (if enabled by I2C1EN)
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 LPUART1SMEN: LPUART1 clock enable during sleep mode bit
This bit is set and cleared by software.
0: LPUART1 clock disabled in sleep mode
1: LPUART1 clock enabled in sleep mode (if enabled by LPUART1EN)
Bit 17 UART2SMEN: UART2 clock enable during sleep mode bit
This bit is set and cleared by software.
0: UART2 clock disabled in sleep mode
1: UART2 clock enabled in sleep mode (if enabled by UART2EN)
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2SMEN: SPI2 clock enable during sleep mode bit
This bit is set and cleared by software.
0: SPI2 clock disabled in sleep mode
1: SPI2 clock enabled in sleep mode (if enabled by SPI2SEN)
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGSMEN: Window watchdog clock enable during sleep mode bit
This bit is set and cleared by software.
0: Window watchdog clock disabled in sleep mode
1: Window watchdog clock enabled in sleep mode (if enabled by WWDGEN)
Bits 10:9 Reserved, must be kept at reset value.
Bits 8:5 Reserved, must be kept at reset value.
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Reset and clock control (RCC)
Bit 4 TIM6SMEN: Timer 6 clock enable during sleep mode bit
Set and cleared by software.
0: Timer 6 clock disabled in sleep mode
1: Timer 6 clock enabled in sleep mode (if enabled by TIM6EN)
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 TIM2SMEN: Timer2 clock enable during sleep mode bit
Set and cleared by software.
0: Timer2 clock disabled in sleep mode
1: Timer2 clock enabled in sleep mode (if enabled by TIM2EN)
7.3.20
Clock configuration register (RCC_CCIPR)
Address: 0x4C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
Res.
30
Res.
29
Res.
28
Res.
27
26
Res.
HSI48SE
L
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
19
18
17
16
Res.
LPTIM1
SEL1
LPTIM1
SEL0
Res.
Res.
rw
rw
3
2
1
0
rw
15
Res.
14
13
12
Res.
I2C1
SEL1
I2C1
SEL0
rw
rw
11
10
LPUART1 LPUART1
SEL1
SEL0
rw
9
Res.
8
Res.
7
Res.
6
Res.
5
Res.
4
Res.
rw
USART2 USART2 USART1 USART1
SEL1
SEL0
SEL1
SEL0
rw
rw
rw
rw
Bits 31:27 Reserved, must be kept at reset value.
Bit26 HSI48SEL: 48 MHz HSI48 clock source selection bit
This bit is set and cleared by software to select the HSI48 clock source for USB and RNG.
0: PLL USB clock selected as HSI48 clock
1: RC48 clock selected as HSI48 clock
Bits 25:20 Reserved, must be kept at reset value.
Bits 19:18 LPTIM1SEL: Low Power Timer clock source selection bits
This bit is set and cleared by software.
00: APB clock selected as LP Timer clock
01: LSI clock selected as LP Timer clock
10: HSI16 clock selected as LP Timer clock
11: LSE clock selected as LP Timer clock
Bits 17:14 Reserved, must be kept at reset value.
Bits 13:12 I2C1SEL: I2C1 clock source selection bits
This bit is set and cleared by software.
00: APB clock selected as I2C1 clock
01: System clock selected as I2C1 clock
10: HSI16 clock selected as I2C1 clock
11: not used
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Bits 11:10 LPUART1SEL: LPUART1 clock source selection bits
This bit is set and cleared by software.
00: APB clock selected as LPUART1 clock
01: System clock selected as LPUART1 clock
10: HSI16 clock selected as LPUART1 clock
11: LSE clock selected as LPUART1 clock
Bits 9:4 Reserved, must be kept at reset value.
Bits 3:2 USART2SEL: USART2 clock source selection bits
This bit is set and cleared by software.
00: APB clock selected as USART2 clock
01: System clock selected as USART2 clock
10: HSI16 clock selected as USART2 clock
11: LSE clock selected as USART2 clock
Bits 1:0 USART1SEL: USART1 clock source selection bits
This bit is set and cleared by software.
00: APB clock selected as USART1 clock
01: System clock selected as USART1 clock
10: HSI16 clock selected as USART1 clock
11: LSE clock selected as USART1 clock
7.3.21
Control/status register (RCC_CSR)
Address: 0x50
Power-on reset value: 0x0C00 0000,
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note:
The LSEON, LSEBYP, RTCSEL,LSEDRV and RTCEN bits in the RCC control and status
register (RCC_CSR) are in the RTC domain. As these bits are write protected after reset,
the DBP bit in the Power control register (PWR_CR) has to be set to be able to modify them.
Refer to Section 6.1.2: RTC and RTC backup registers for further information. These bits
are only reset after a RTC domain reset (see Section 6.1.2). Any internal or external reset
does not have any effect on them.
31
30
29
28
27
26
25
LPWR
RSTF
WWDG
RSTF
IWDG
RSTF
SFT
RSTF
POR
RSTF
PIN
RSTF
OBLRS
TF
24
RMVF
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
Res.
CSSLS CSSLS
ED
EON
rw
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LSEDRV[1:0]
LSE
BYP
rw
rw
LSERDY LSEON
r
23
22
21
20
19
18
RTC
RST.
RTC
EN
rw
rw
rw
rw
3
2
1
0
Res.
LSI
RDY
LSION
r
rw
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
rw
DocID025941 Rev 1
Res.
Res.
Res.
17
16
RTCSEL[1:0]
RM0376
Reset and clock control (RCC)
Bit 31 LPWRRSTF: Low-power reset flag
This bit is set by hardware when a Low-power management reset occurs.
It is cleared by writing to the RMVF bit, or by a POR.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to Section : Low-power
management reset.
Bit 30 WWDGRSTF: Window watchdog reset flag
This bit is set by hardware when a window watchdog reset occurs.
It is cleared by writing to the RMVF bit, or by a POR.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent watchdog reset flag
This bit is set by hardware when an independent watchdog reset from VDD domain occurs.
It is cleared by writing to the RMVF bit, or by a POR.
0: No watchdog reset occurred
1: Watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
This bit is set by hardware when a software reset occurs.
It is cleared by writing to the RMVF bit, or by a POR.
0: No software reset occurred
1: Software reset occurred
Bit 27 PORRSTF: POR/PDR reset flag
This bit is set by hardware when a POR/PDR reset occurs.
It is cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
Bit 26 PINRSTF: PIN reset flag
This bit is set by hardware when a reset from the NRST pin occurs.
It is cleared by writing to the RMVF bit, or by a POR.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 OBLRSTF Options bytes loading reset flag
This bit is set by hardware when an OBL reset occurs.
It is cleared by writing to the RMVF bit, or by a POR.
0: No OBL reset occurred
1: OBL reset occurred
Bit 24 RMVF: Remove reset flag
This bit is set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 RTCRST: RTC software reset bit
This bit is set and cleared by software.
0: Reset not activated
1: Resets the RTC peripheral, its clock source selection and the backup registers.
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Bit 18 RTCEN: RTC clock enable bit
This bit is set and cleared by software.
It is reset by setting the RTCRST bit or by a POR.
0: RTC clock disabled
1: RTC clock enabled
Bits 17:16 RTCSEL[1:0]: RTC clock source selection bits
These bits are set by software to select the clock source for the RTC.
Once the RTC clock source has been selected it cannot be switched until RTCRST is set or
a Power On Reset occurred. The only exception is if the LSE oscillator clock was selected, if
the LSE clock stops and it is detected by the CSSHSE, in that case the clock can be
switched.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by a programmable prescaler (selection through the
RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock
If the LSE or LSI is used as RTC clock source, the RTC continues to work in Stop and
Standby low power modes, and can be used as wake-up source. However, when the HSE
clock is used as RTC clock source, the RTC cannot be used in Stop and Standby low power
modes.
Bit 15: Reserved, must be kept at reset value.
Bit 14 CSSLSED: CSS on LSE failure detection flag
This bit is set by hardware to indicate when a failure has been detected by the clock security
system on the external 32 kHz oscillator (LSE).
It is cleared by a power-on reset or by an RTC software reset (RTCRST bit).
0: No failure detected on LSE (32 kHz oscillator)
1: Failure detected on LSE (32 kHz oscillator)
Bit 13 CSSLSEON CSS on LSE enable bit
This bit is set by software to enable the Clock Security System on LSE (32 kHz oscillator).
CSSLSEON must be enabled after the LSE and LSI oscillators are enabled (LSEON and
LSION bits enabled) and ready (LSERDY and LSIRDY flags set by hardware), and after the
RTCSEL bit is selected.
Once enabled this bit cannot be disabled, except after an LSE failure detection (CSSLSED
=1). In that case the software MUST disable the CSSLSEON bit.
Reset by power on reset and RTC software reset (RTCRST bit).
0: CSS on LSE (32 kHz oscillator) OFF
1: CSS on LSE (32 kHz oscillator) ON
Bits 12-11 LSEDRV; LSE oscillator Driving capability bits
These bits are set by software to select the driving capability of the LSE oscillator.
They are cleared by a power-on reset or an RTC reset. Once “00” has been written, the
content of LSEDRV cannot be changed by software.
00: Lowest drive
01: Medium low drive
10: Medium high drive
11: Highest drive
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Reset and clock control (RCC)
Bit 10 LSEBYP: External low-speed oscillator bypass bit
This bit is set and cleared by software to bypass oscillator in debug mode. This bit can be
written only when the LSE oscillator is disabled.
It is reset by setting the RTCRST bit or by a POR.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 9 LSERDY: External low-speed oscillator ready bit
This bit is set and cleared by hardware to indicate when the LSE oscillator is stable. After the
LSEON bit is cleared, LSERDY goes low after 6 LSE oscillator clock cycles.
It is reset by setting the RTCRST bit or by a POR.
0: External 32 kHz oscillator not ready
1: External 32 kHz oscillator ready
Bit 8 LSEON: External low-speed oscillator enable bit
This bit is set and cleared by software.
It is reset by setting the RTCRST bit or by a POR.
0: LSE oscillator OFF
1:LSE oscillator ON
Bits 7:2
Reserved, must be kept at reset value.
Bit 1 LSIRDY: Internal low-speed oscillator ready bit
This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After the
LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles.
This bit is reset by system reset.
0: LSI oscillator not ready
1: LSI oscillator ready
Bit 0 LSION: Internal low-speed oscillator enable
This bit is set and cleared by software.
It is reset by system reset.
0: LSI oscillator OFF
1: LSI oscillator ON
7.3.22
RCC register map
The following table gives the RCC register map and the reset values.
DocID025941 Rev 1
HSI16ON
0
HSI16RDYF
0
HSI16KERON
HSI16DIVF
1
HSI16DIVEN
MSION
1
Res.
Res.
Res.
MSIRDY
0
Res.
Res.
Res.
Res.
Res.
Res.
X X 0 X 0
RTC
PRE
[1:0]
HSEBYP
HSEON
CSSLSEON
0
Res.
Res.
0
HSERDY
Reset value
PLL ON
RCC_CR
PLL RDY
0x00
Register
Res.
Res.
Res.
Res.
Res.
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 33. RCC register map and reset values
0
0
0
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RCC_APB2RSTR
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0
0
0
0
LSERDYIE
LSIRDYIE
LSIRDYF
0
0
0
0
0
LSIRDYC
0
0
0
0
0
0
IOPARST
LSERDYF
0
LSERDYC
0
HSI16RDYC
0
IOPBRST
0
IOPCRST
HSI16RDYF
0
0
0
DMARST
Reset value
HSI16RDYIE
0
PLLRDYIE
0
HSERDYIE
0
Res.
Res.
Res.
Res.
Res.
Res.
x
x
HSI48RDY
HSI48ON
x
SYSCFGRST
Reset value
0
x
Res.
Reset value
0
x
TIM21RST
0
PLLRDYF
Reset value
HSERDYF
0
0
0
0
PLLRDYC
SW
[1:0]
0
HSERDYC
SWS
[1:0]
0
x
IOPDRST
HPRE[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
HSI48RDYIE
MSIRDYIE
0
x
Res.
Res.
0
0
HSI48RDYF
MSIRDYF
PPRE1
[2:0]
0
0
x
HSI48RDYC
MSIRDYC
PPRE2
[2:0]
0
0
0
Res.
Res.
Res.
HSI48CAL[7:0]
0
CSSLSE
0
0
0
CSSLSEF.
0
0
0
CSSHSEF.
1
CSSLSEC.
1
0
CSSHSEC.
1
IOPHRST
HSI16TRIM[4:0
]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
MSIRAN
GE[2:0]
TM12RST
0
0
STOPWUCK
Reset value
PLLSRC
0
x
MIFRST
0
x
Res.
Res.
Res.
0
0
x
Res.
0
0
x
Res.
Res.
Res.
0
x
CRCRST
Res.
PLLMUL[3:
0]
0
x
ADCRST
Reset value
x
Res.
Res.
RCC_AHBRSTR
PLL
DIV
[1:0]
0
x
SPI1RST
0x20
MCOSE
L [3:0]
0
0
Res.
RCC_IOPRSTR
0
Res.
Res.
Res.
0x1C
0
0
MSICAL[7:0]
USART1RST
RCC_CICR
MCOPR
E
[2:0]
0
TSCRST
0x18
0
0
Res.
Res.
Res.
RCC_CIFR
0
0
RNGRST
0x14
MSITRIM[7:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RCC_CIER
0
Res.
Res.
Res.
0x10
0
DBGRST
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RCC_ICSCR
CRYPRST
0x0C
RCC_CFGR
Res.
RCC_CRRCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x08
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x04
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Offset
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset and clock control (RCC)
RM0376
Table 33. RCC register map and reset values (continued)
HSI16CAL[7:0]
0
0
0
0
0
0
0
0
0x44
RCC_APB2SM
ENR
Reset value
1
DocID025941 Rev 1
1
1
1
1
IOPBSMEN
IOPASMEN
0
0
TIM2EN
0
Res.
Res.
Res.
TIM6EN
Res.
1
0
SYSCFGEN
Res.
TIM21EN
Res.
Res.
TIM22EN
1
DMASMEN
1
IOPCSMEN
0
IOPDSMEN
0
Res.
1
Res.
Res.
Res.
Res.
DMAEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MIFEN
IOPDEN
IOPCEN
IOPBEN
IOPAEN
Res.
Res.
Res.
IOPHEN
TIM2RST
Res.
Res.
Res.
TIM6RST
Res.
Res.
Res.
Res.
Res.
Res.
WWDRST
Res.
Res.
SPI2RST
Res.
Res.
LPUART1RST
LPUART12RST
Res.
Res.
I2C1RST
USBRST.
I2C2RST
Res.
Res.
Res.
CRSRST.
DACRST.
PWRRST
Res.
LPTIM1RST
0
SYSCFGSMEN
1
MIFIEN
0
TIM21SMEN
Reset value
IOPHSMEN
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRCEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
1
MIFSMEN
0
ADCEN
Res.
Res.
SPI1EN
Res.
USART1EN
Res.
Res.
Res.
Res.
Res.
Res.
RNGEN
Res.
Res.
Res.
CRYPEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
TIM22SMEN
1
Res.
Res
Res.
Res.
Res.
Res.
0
SRAMSMEN
0
WWDGEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
1
0
ADCSMEN
0
SPI2EN
0
Res.
Res.
0
Res.
Res.
USART2EN
Res.
Res.
LPUART1EN
0
0
Res.
Res.
1
I2C1EN
0
CRCSMEN
0
0
SPI1SMEN
0
DBGEN
0
Res.
Res.
Res.
0
0
Res.
Reset value
0
0
USART1SMEN
RCC_AHBSM
ENR
0
USBEN
I2C2EN
Reset value
0
TSCSMEN
RCC_IOPSMEN
0
Res.
Res.
Res.
Reset value
0
Res.
Res.
Res.
0
0
RNGSMEN
Reset value
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RCC_APB1ENR
CRSEN.
RCC_APB2ENR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RCC_AHBENR
0
DBGSMEN
0x40
RCC_IOPENR
0
Res.
Res.
Res.
0x3C
0
CRYPSMEN
0x38
Reset value
DACEN.
PWREN
0x34
RCC_APB1RSTR
Res.
0x30
LPTIM1EN
0x2C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x28
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Offset
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RM0376
Reset and clock control (RCC)
Table 33. RCC register map and reset values (continued)
0
0
0
0
0
0
0
1
1
1
1
1
1
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0x50
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OBLRSTF
RMVF
0
0
0
0
1
1
0
0
0
0
0
RTC
SEL
[1:0]
0
0
0
DocID025941 Rev 1
LPUART1SEL1
LPUART1SEL0
0
0
0
LSE
DRV
[1:0]
LSEBYP
LSERDY
LSEON
0
0
0
0
0
0
Refer to Section 2.2.2 for the register boundary addresses.
LSIRDY
LSION
0
USART2SEL0
USART1SEL1
USART1SEL0
1
USART2SEL1
1
Res.
Res.
Res.
Res.
Res.
Res.
I2C1SEL0
1
Res.
Res.
Res.
Res.
Res.
Res.
I2C1SEL1
0
0
CSSLSED
1
CSSLSEON
1
1
TIM2SMEN
Res.
Res.
Res.
TIM6SMEN
Res.
Res
Res.
Res.
Res.
Res.
WWDGSMEN
Res.
Res.
SPI2SMEN
Res.
Res.
USART2SMEN
Res.
Res.
I2C1SMEN
USBSMEN
I2C2SMEN
Res.
Res.
Res.
CRSSMEN.
DACSMEN.
PWRSMEN
LPUART1SMEN
1
Res.
Res.
Res.
Res.
LPTIM1SEL0
1
Res.
Reset value
1
RTCEN
1
LPTIM1SEL1
1
RTCRST
1
Res.
Res.
Res.
Res.
Res.
Res.
1
HSI48SEL
LPTIM1SMEN
Reset value
Res.
RCC_APB1
SMENR
Res.
Res.
Res.
Res.
PINRSTF
Reset value
PORRSTF
RCC_CSR
SFTRSTF
RCC_CCIPR
IWDGRSTF
0x4C
Res.
Res.
Res.
Res.
Res.
0x48
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
LPWRSTF
Offset
WWDGRSTF
Reset and clock control (RCC)
RM0376
Table 33. RCC register map and reset values (continued)
1
0
0
0
0
0
0
RM0376
Clock recovery system (CRS)
8
Clock recovery system (CRS)
8.1
Introduction
The clock recovery system (CRS) is an advanced digital controller acting on the internal
fine-granularity trimmable RC oscillator HSI48. The CRS provides a powerful means for
oscillator output frequency evaluation, based on comparison with a selectable
synchronization signal. It is capable of doing automatic adjustment of oscillator trimming
based on the measured frequency error value, while keeping the possibility of a manual
trimming.
The CRS is ideally suited to provide a precise clock to the USB peripheral. In such case, the
synchronization signal can be derived from the start-of-frame (SOF) packet signalization on
the USB bus, which is sent by a USB host at precise 1-ms intervals.
The synchronization signal can also be derived from the LSE oscillator output or from an
external pin, or it can be generated by user software.
8.2
CRS main features
•
Selectable synchronization source with programmable prescaler and polarity:
–
External pin
–
LSE oscillator output
–
USB SOF packet reception
•
Possibility to generate synchronization pulses by software
•
Automatic oscillator trimming capability with no need of CPU action
•
Manual control option for faster start-up convergence
•
16-bit frequency error counter with automatic error value capture and reload
•
Programmable limit for automatic frequency error value evaluation and status reporting
•
Maskable interrupts/events:
–
Expected synchronization (ESYNC)
–
Synchronization OK (SYNCOK)
–
Synchronization warning (SYNCWARN)
–
Synchronization or trimming error (ERR)
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Clock recovery system (CRS)
RM0376
8.3
CRS functional description
8.3.1
CRS block diagram
Figure 20. CRS block diagram
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8.3.2
Synchronization input
The CRS synchronization (SYNC) source, selectable through the CRS_CFGR register, can
be the signal from the external CRS_SYNC pin, the LSE clock or the USB SOF signal. For a
better robustness of the SYNC input, a simple digital filter (2 out of 3 majority votes,
sampled by the HSI48 clock) is implemented to filter out any glitches. This source signal
also has a configurable polarity and can then be divided by a programmable binary
prescaler to obtain a synchronization signal in a suitable frequency range (usually around
1 kHz).
For more information on the CRS synchronization source configuration, refer to
Section 8.6.2: CRS configuration register (CRS_CFGR).
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Clock recovery system (CRS)
It is also possible to generate a synchronization event by software, by setting the SWSYNC
bit in the CRS_CR register.
8.3.3
Frequency error measurement
The frequency error counter is a 16-bit down/up counter which is reloaded with the RELOAD
value on each SYNC event. It starts counting down till it reaches the zero value, where the
ESYNC (expected synchronization) event is generated. Then it starts counting up to the
OUTRANGE limit where it eventually stops (if no SYNC event is received) and generates a
SYNCMISS event. The OUTRANGE limit is defined as the frequency error limit (FELIM field
of the CRS_CFGR register) multiplied by 128.
When the SYNC event is detected, the actual value of the frequency error counter and its
counting direction are stored in the FECAP (frequency error capture) field and in the FEDIR
(frequency error direction) bit of the CRS_ISR register. When the SYNC event is detected
during the downcounting phase (before reaching the zero value), it means that the actual
frequency is lower than the target (and so, that the TRIM value should be incremented),
while when it is detected during the upcounting phase it means that the actual frequency is
higher (and that the TRIM value should be decremented).
Figure 21. CRS counter behavior
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DocID025941 Rev 1
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Clock recovery system (CRS)
8.3.4
RM0376
Frequency error evaluation and automatic trimming
The measured frequency error is evaluated by comparing its value with a set of limits:
–
TOLERANCE LIMIT, given directly in the FELIM field of the CRS_CFGR register
–
WARNING LIMIT, defined as 3 * FELIM value
–
OUTRANGE (error limit), defined as 128 * FELIM value
The result of this comparison is used to generate the status indication and also to control the
automatic trimming which is enabled by setting the AUTOTRIMEN bit in the CRS_CR
register:
•
•
•
•
Note:
When the frequency error is below the tolerance limit, it means that the actual trimming
value in the TRIM field is the optimal one and that then, no trimming action is
necessary.
–
SYNCOK status indicated
–
TRIM value not changed in AUTOTRIM mode
When the frequency error is below the warning limit but above or equal to the tolerance
limit, it means that some trimming action is necessary but that adjustment by one
trimming step is enough to reach the optimal TRIM value.
–
SYNCOK status indicated
–
TRIM value adjusted by one trimming step in AUTOTRIM mode
When the frequency error is above or equal to the warning limit but below the error
limit, it means that a stronger trimming action is necessary, and there is a risk that the
optimal TRIM value will not be reached for the next period.
–
SYNCWARN status indicated
–
TRIM value adjusted by two trimming steps in AUTOTRIM mode
When the frequency error is above or equal to the error limit, it means that the
frequency is out of the trimming range. This can also happen when the SYNC input is
not clean or when some SYNC pulse is missing (for example when one USB SOF is
corrupted).
–
SYNCERR or SYNCMISS status indicated
–
TRIM value not changed in AUTOTRIM mode
If the actual value of the TRIM field is so close to its limits that the automatic trimming would
force it to overflow or underflow, then the TRIM value is set just to the limit and the
TRIMOVF status is indicated.
In AUTOTRIM mode (AUTOTRIMEN bit set in the CRS_CR register), the TRIM field of
CRS_CR is adjusted by hardware and is read-only.
8.3.5
CRS initialization and configuration
RELOAD value
The RELOAD value should be selected according to the ratio between the target frequency
and the frequency of the synchronization source after prescaling. It is then decreased by
one in order to reach the expected synchronization on the zero value. The formula is the
following:
RELOAD = (fTARGET / fSYNC) -1
The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a
synchronization signal frequency of 1 kHz (SOF signal from USB).
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Clock recovery system (CRS)
FELIM value
The selection of the FELIM value is closely coupled with the HSI48 oscillator characteristics
and its typical trimming step size. The optimal value corresponds to half of the trimming step
size, expressed as a number of HSI48 oscillator clock ticks. The following formula can be
used:
FELIM = (fTARGET / fSYNC) * STEP[%] / 100% / 2
The result should be always rounded up to the nearest integer value in order to obtain the
best trimming response. If frequent trimming actions are not wanted in the application, the
trimming hysteresis can be increased by increasing slightly the FELIM value.
The reset value of the FELIM field corresponds to (fTARGET / fSYNC) = 48000 and to a typical
trimming step size of 0.14%.
Caution:
There is no hardware protection from a wrong configuration of the RELOAD and FELIM
fields which can lead to an erratic trimming response. The expected operational mode
requires proper setup of the RELOAD value (according to the synchronization source
frequency), which is also greater than 128 * FELIM value (OUTRANGE limit).
8.4
CRS low-power modes
Table 34. Effect of low-power modes on CRS
Mode
Sleep
Description
No effect.
CRS interrupts cause the device to exit the Sleep mode.
Stop
CRS registers are frozen.
The CRS stops operating until the Stop or Standby mode is exited and the HSI48 oscillator
Standby restarted.
8.5
CRS interrupts
Table 35. Interrupt control bits
Interrupt event
Event flag
Enable
control bit
Clear
flag bit
Expected synchronization
ESYNCF
ESYNCIE
ESYNCC
Synchronization OK
SYNCOKF
SYNCOKIE
SYNCOKC
Synchronization warning
SYNCWARNF
SYNCWARNIE
SYNCWARNC
Synchronization or trimming error
(TRIMOVF, SYNCMISS, SYNCERR)
ERRF
ERRIE
ERRC
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Clock recovery system (CRS)
8.6
RM0376
CRS registers
Refer to Section 1.1 on page 43 of the reference manual for a list of abbreviations used in
register descriptions.
The peripheral registers can be accessed by words (32-bit).
8.6.1
CRS control register (CRS_CR)
Address offset: 0x00
Reset value: 0x0000 2000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
SWSY AUTOT
NC
RIMEN
TRIM[5:0]
rw
rw
rw
rw
rw
rw
rt_w
rw
CEN
rw
Res.
SYNC
ESYNC
SYNCO
ERRIE WARNI
IE
KIE
E
rw
rw
rw
rw
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:8 TRIM[5:0]: HSI48 oscillator smooth trimming
These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be
programmed to adjust to variations in voltage and temperature that influence the frequency
of the HSI48.
The default value is 32, which corresponds to the middle of the trimming interval. The
trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
corresponds to a higher output frequency.
When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only.
Bit 7 SWSYNC: Generate software SYNC event
This bit is set by software in order to generate a software SYNC event. It is automatically
cleared by hardware.
0: No action
1: A software SYNC event is generated.
Bit 6 AUTOTRIMEN: Automatic trimming enable
This bit enables the automatic hardware adjustment of TRIM bits according to the measured
frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The
TRIM value can be adjusted by hardware by one or two steps at a time, depending on the
measured frequency error value. Refer to Section 8.3.4: Frequency error evaluation and
automatic trimming for more details.
0: Automatic trimming disabled, TRIM bits can be adjusted by the user.
1: Automatic trimming enabled, TRIM bits are read-only and under hardware control.
Bit 5 CEN: Frequency error counter enable
This bit enables the oscillator clock for the frequency error counter.
0: Frequency error counter disabled
1: Frequency error counter enabled
When this bit is set, the CRS_CFGR register is write-protected and cannot be modified.
Bit 4 Reserved, must be kept at reset value.
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Clock recovery system (CRS)
Bit 3 ESYNCIE: Expected SYNC interrupt enable
0: Expected SYNC (ESYNCF) interrupt disabled
1: Expected SYNC (ESYNCF) interrupt enabled
Bit 2 ERRIE: Synchronization or trimming error interrupt enable
0: Synchronization or trimming error (ERRF) interrupt disabled
1: Synchronization or trimming error (ERRF) interrupt enabled
Bit 1 SYNCWARNIE: SYNC warning interrupt enable
0: SYNC warning (SYNCWARNF) interrupt disabled
1: SYNC warning (SYNCWARNF) interrupt enabled
Bit 0 SYNCOKIE: SYNC event OK interrupt enable
0: SYNC event OK (SYNCOKF) interrupt disabled
1: SYNC event OK (SYNCOKF) interrupt enabled
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Clock recovery system (CRS)
8.6.2
RM0376
CRS configuration register (CRS_CFGR)
This register can be written only when the frequency error counter is disabled (CEN bit is
cleared in CRS_CR). When the counter is enabled, this register is write-protected.
Address offset: 0x04
Reset value: 0x2022 BB7F
31
30
SYNCP
OL
Res.
rw
15
14
29
28
SYNCSRC[1:0]
rw
rw
13
12
27
26
Res.
11
25
24
23
22
21
SYNCDIV[2:0]
20
19
18
17
16
FELIM[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
RELOAD[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bit 31 SYNCPOL: SYNC polarity selection
This bit is set and cleared by software to select the input polarity for the SYNC signal source.
0: SYNC active on rising edge (default)
1: SYNC active on falling edge
Bit 30 Reserved, must be kept at reset value.
Bits 29:28 SYNCSRC[1:0]: SYNC signal source selection
These bits are set and cleared by software to select the SYNC signal source.
00: GPIO selected as SYNC signal source
01: LSE selected as SYNC signal source
10: USB SOF selected as SYNC signal source (default)
11: Reserved
Bit 27 Reserved, must be kept at reset value.
Bits 26:24 SYNCDIV[2:0]: SYNC divider
These bits are set and cleared by software to control the division factor of the SYNC signal.
000: SYNC not divided (default)
001: SYNC divided by 2
010: SYNC divided by 4
011: SYNC divided by 8
100: SYNC divided by 16
101: SYNC divided by 32
110: SYNC divided by 64
111: SYNC divided by 128
Bits 23:16 FELIM[7:0]: Frequency error limit
FELIM contains the value to be used to evaluate the captured frequency error value latched
in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section 8.3.4: Frequency error
evaluation and automatic trimming for more details about FECAP evaluation.
Bits 15:0 RELOAD[15:0]: Counter reload value
RELOAD is the value to be loaded in the frequency error counter with each SYNC event.
Refer to Section 8.3.3: Frequency error measurement for more details about counter
behavior.
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Clock recovery system (CRS)
8.6.3
CRS interrupt and status register (CRS_ISR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
r
r
r
r
r
r
r
FECAP[15:0]
r
15
r
14
r
13
12
r
r
11
10
r
r
9
r
8
r
7
6
5
4
3
2
1
0
FEDIR Res. Res. Res. Res. TRIMOVF SYNCMISS SYNCERR Res. Res. Res. Res. ESYNCF ERRF SYNCWARNF SYNCOKF
r
r
r
r
r
r
r
r
Bits 31:16 FECAP[15:0]: Frequency error capture
FECAP is the frequency error counter value latched in the time of the last SYNC event.
Refer to Section 8.3.4: Frequency error evaluation and automatic trimming for more details
about FECAP usage.
Bit 15 FEDIR: Frequency error direction
FEDIR is the counting direction of the frequency error counter latched in the time of the last
SYNC event. It shows whether the actual frequency is below or above the target.
0: Upcounting direction, the actual frequency is above the target.
1: Downcounting direction, the actual frequency is below the target.
Bits 14:11 Reserved, must be kept at reset value.
Bit 10 TRIMOVF: Trimming overflow or underflow
This flag is set by hardware when the automatic trimming tries to over- or under-flow the
TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is
cleared by software by setting the ERRC bit in the CRS_ICR register.
0: No trimming error signalized
1: Trimming error signalized
Bit 9 SYNCMISS: SYNC missed
This flag is set by hardware when the frequency error counter reached value FELIM * 128
and no SYNC was detected, meaning either that a SYNC pulse was missed or that the
frequency error is too big (internal frequency too high) to be compensated by adjusting the
TRIM value, and that some other action should be taken. At this point, the frequency error
counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is
set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the
CRS_ICR register.
0: No SYNC missed error signalized
1: SYNC missed error signalized
Bit 8 SYNCERR: SYNC error
This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the
measured frequency error is greater than or equal to FELIM * 128. This means that the
frequency error is too big (internal frequency too low) to be compensated by adjusting the
TRIM value, and that some other action should be taken. An interrupt is generated if the
ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in
the CRS_ICR register.
0: No SYNC error signalized
1: SYNC error signalized
Bits 7:4 Reserved, must be kept at reset value.
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Clock recovery system (CRS)
RM0376
Bit 3 ESYNCF: Expected SYNC flag
This flag is set by hardware when the frequency error counter reached a zero value. An
interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by
software by setting the ESYNCC bit in the CRS_ICR register.
0: No expected SYNC signalized
1: Expected SYNC signalized
Bit 2 ERRF: Error flag
This flag is set by hardware in case of any synchronization or trimming error. It is the logical
OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE
bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit
in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits.
0: No synchronization or trimming error signalized
1: Synchronization or trimming error signalized
Bit 1 SYNCWARNF: SYNC warning flag
This flag is set by hardware when the measured frequency error is greater than or equal to
FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency
error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the
SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the
SYNCWARNC bit in the CRS_ICR register.
0: No SYNC warning signalized
1: SYNC warning signalized
Bit 0 SYNCOKF: SYNC event OK flag
This flag is set by hardware when the measured frequency error is smaller than FELIM * 3.
This means that either no adjustment of the TRIM value is needed or that an adjustment by
one trimming step is enough to compensate the frequency error. An interrupt is generated if
the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the
SYNCOKC bit in the CRS_ICR register.
0: No SYNC event OK signalized
1: SYNC event OK signalized
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Clock recovery system (CRS)
8.6.4
CRS interrupt flag clear register (CRS_ICR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ESYNCC
ERRC
SYNCWARNC
SYNCOKC
rw
rw
rw
rw
Bits 31:4 Reserved, must be kept at reset value
Bit 3 ESYNCC: Expected SYNC clear flag
Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register.
Bit 2 ERRC: Error clear flag
Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
the ERRF flag in the CRS_ISR register.
Bit 1 SYNCWARNC: SYNC warning clear flag
Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register.
Bit 0 SYNCOKC: SYNC event OK clear flag
Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register.
8.6.5
CRS register map
0
1
0
0
0
0
0
0
0
0
0
0
0
0
DocID025941 Rev 1
1
0
1
1
0
CEN
Res.
ESYNCIE
ERRIE
SYNCWARNIE
SYNCOKIE
SWSYNC
1
0
1
1
0
1
1
1
1
1
1
1
SYNCOKF
0
ERRF
0
SYNCWARNF
0
0
ESYNCF
0
0
Res.
0
0
Res.
0
0
Res.
1
FECAP[15:0]
0
0
Res.
0
0
SYNCERR
0
0
SYNCMISS
Reset value
0
0
Res.
CRS_ISR
0
0
TRIMOVF
0
Res.
0
0
RELOAD[15:0]
Res.
1
0
FELIM[7:0]
Res.
0
SYNC
DIV
[2:0]
Res.
Reset value
SYNC
SRC
[1:0]
0
FEDIR
0x08
CRS_CFGR
Res.
0x04
1
SYNCPOL
Reset value
TRIM[5:0]
AUTOTRIMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRS_CR
Res.
0x00
Res.
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 36. CRS register map and reset values
0
0
0
0
0
0
0
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Refer to Section 2.2.2 for the register boundary addresses.
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ERRC
SYNCOKC
0
SYNCWARNC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ESYNCC
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRS_ICR
0x0C
Res.
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 36. CRS register map and reset values (continued)
0
0
0
RM0376
General-purpose I/Os (GPIO)
9
General-purpose I/Os (GPIO)
9.1
Introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition
all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function
selection registers (GPIOx_AFRH and GPIOx_AFRL).
9.2
9.3
GPIO main features
•
Output states: push-pull or open drain + pull-up/down
•
Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
•
Speed selection for each I/O
•
Input states: floating, pull-up/down, analog
•
Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
•
Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
•
Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
•
Analog function
•
Alternate function selection registers
•
Fast toggle capable of changing every two clock cycles
•
Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several
peripheral functions
GPIO functional description
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in
several modes:
•
Input floating
•
Input pull-up
•
Input-pull-down
•
Analog
•
Output open-drain with pull-up or pull-down capability
•
Output push-pull with pull-up or pull-down capability
•
Alternate function push-pull with pull-up or pull-down capability
•
Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR and
GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR
registers. In this way, there is no risk of an IRQ occurring between the read and the modify
access.
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Figure 22 and Figure 23 show the basic structures of a standard and a 5 V tolerant I/O port
bit, respectively. Table 38 gives the possible port bit configurations.
Figure 22. Basic structure of an I/O port bit
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Figure 23. Basic structure of a five-volt tolerant I/O port bit
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1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD.
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General-purpose I/Os (GPIO)
Table 37. Port bit configuration table(1)
MODE(i)
[1:0]
01
10
00
11
OTYPER(i)
OSPEED(i)
[1:0]
PUPD(i)
[1:0]
I/O configuration
0
0
0
GP output
PP
0
0
1
GP output
PP + PU
0
1
0
GP output
PP + PD
1
1
Reserved
0
0
GP output
OD
1
0
1
GP output
OD + PU
1
1
0
GP output
OD + PD
1
1
1
Reserved (GP output OD)
0
0
0
AF
PP
0
0
1
AF
PP + PU
0
1
0
AF
PP + PD
1
1
Reserved
0
0
AF
OD
1
0
1
AF
OD + PU
1
1
0
AF
OD + PD
1
1
1
Reserved
0
SPEED
[1:0]
1
0
SPEED
[1:0]
1
x
x
x
0
0
Input
Floating
x
x
x
0
1
Input
PU
x
x
x
1
0
Input
PD
x
x
x
1
1
Reserved (input floating)
x
x
x
0
0
Input/output
x
x
x
0
1
x
x
x
1
0
x
x
x
1
1
Analog
Reserved
1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF =
alternate function.
9.3.1
General-purpose I/O (GPIO)
During and just after reset, the alternate functions are not active and most of the I/O ports
are configured in analog mode.
The debug pins are in AF pull-up/pull-down after reset:
•
PA14: SWCLK in pull-down
•
PA13: SWDIO in pull-up
When the pin is configured as output, the value written to the output data register
(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull
mode or open-drain mode (only the low level is driven, high level is HI-Z).
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The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.
9.3.2
I/O pin alternate function multiplexer and mapping
The device I/O pins are connected to on-board peripherals/modules through a multiplexer
that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In
this way, there can be no conflict between peripherals available on the same I/O pin.
Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that
can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to
15) registers:
•
After reset all I/Os are connected to alternate function 0 (AF0)
•
The specific alternate function assignments for each pin are detailed in the device
datasheet.
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped onto different I/O pins to optimize the number of peripherals available in
smaller packages.
To use an I/O in a given configuration, you have to proceed as follows:
•
Debug function: after each device reset these pins are assigned as alternate function
pins immediately usable by the debugger host
•
GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER
register.
•
Peripheral alternate function:
•
–
Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH
register.
–
Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.
–
Configure the desired I/O as an alternate function in the GPIOx_MODER register.
Additional functions:
–
For the ADC, DAC and COMP, configure the desired I/O in analog mode in the
GPIOx_MODER register and configure the required function in the ADC, DAC and
COMP registers.
–
For the additional functions like RTC, WKUPx and oscillators, configure the
required function in the related RTC, PWR and RCC registers. These functions
have priority over the configuration in the standard GPIO registers.
Please refer to the “Alternate function mapping” table in the device datasheet for the
detailed mapping of the alternate function I/O pins.
9.3.3
I/O port control registers
Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The
GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The
GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-
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pull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pullup/pull-down whatever the I/O direction.
9.3.4
I/O port data registers
Each GPIO has two 16-bit memory-mapped data registers: input and output data registers
(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write
accessible. The data input through the I/O are stored into the input data register
(GPIOx_IDR), a read-only register.
See Section 9.4.5: GPIO port input data register (GPIOx_IDR) (x = A..D and H) and
Section 9.4.6: GPIO port output data register (GPIOx_ODR) (x = A..D and H) for the register
descriptions.
9.3.5
I/O data bitwise handling
The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to
set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset
register has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i).
When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i)
resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a
“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always
be accessed directly. The GPIOx_BSRR register provides a way of performing atomic
bitwise handling.
There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify one or more bits in a single atomic AHB write access.
9.3.6
GPIO locking mechanism
It is possible to freeze the GPIO control registers by applying a specific write sequence to
the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When
the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used
to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must
be the same). When the LOCK sequence has been applied to a port bit, the value of the port
bit can no longer be modified until the next reset. Each GPIOx_LCKR bit freezes the
corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The LOCK sequence (refer to Section 9.4.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A..D and H)) can only be performed using a word (32-bit long) access
to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the
same time as the [15:0] bits.
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For more details please refer to LCKR register description in Section 9.4.8: GPIO port
configuration lock register (GPIOx_LCKR) (x = A..D and H).
9.3.7
I/O alternate function input/output
Two registers are provided to select one of the alternate function inputs/outputs available for
each I/O. With these registers, you can connect an alternate function to some other pin as
required by your application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can
thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of a given I/O.
To know which functions are multiplexed on each GPIO pin, refer to the device datasheet.
9.3.8
External interrupt/wakeup lines
All ports have external interrupt capability. To use external interrupt lines, the port must be
configured in input mode. Refer to Section 14: Extended interrupts and events controller
(EXTI) and to Section 14.3.2: Wakeup event management.
9.3.9
Input configuration
When the I/O port is programmed as input:
•
The output buffer is disabled
•
The Schmitt trigger input is activated
•
The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
•
A read access to the input data register provides the I/O state
Figure 24 shows the input configuration of the I/O port bit.
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Figure 24. Input floating/pull up/pull down configurations
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9.3.10
Output configuration
When the I/O port is programmed as output:
•
The output buffer is enabled:
–
Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1”
in the Output register leaves the port in Hi-Z (the P-MOS is never activated)
–
Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in
the Output register activates the P-MOS
•
The Schmitt trigger input is activated
•
The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
•
A read access to the input data register gets the I/O state
•
A read access to the output data register gets the last written value
Figure 25 shows the output configuration of the I/O port bit.
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9.3.11
Alternate function configuration
When the I/O port is programmed as alternate function:
•
The output buffer can be configured in open-drain or push-pull mode
•
The output buffer is driven by the signals coming from the peripheral (transmitter
enable and data)
•
The Schmitt trigger input is activated
•
The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
•
A read access to the input data register gets the I/O state
Figure 26 shows the Alternate function configuration of the I/O port bit.
Figure 26. Alternate function configuration
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9.3.12
General-purpose I/Os (GPIO)
Analog configuration
When the I/O port is programmed as analog configuration:
•
The output buffer is disabled
•
The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
•
The weak pull-up and pull-down resistors are disabled by hardware
•
Read access to the input data register gets the value “0”
Figure 27 shows the high-impedance, analog-input configuration of the I/O port bit.
Figure 27. High impedance-analog configuration
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Using the HSE or LSE oscillator pins as GPIOs
When the HSE or LSE oscillator is switched OFF (default state after reset), the related
oscillator pins can be used as normal GPIOs.
When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the
RCC_CSR register) the oscillator takes control of its associated pins and the GPIO
configuration of these pins has no effect.
When the oscillator is configured in a user external clock mode, only the OSC_IN or
OSC32_IN pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be
used as normal GPIO.
9.3.14
Using the GPIO pins in the RTC supply domain
The PC13/PC14/PC15 GPIO functionality is lost when the core supply domain is powered
off (when the device enters Standby mode). In this case, if their GPIO configuration is not
bypassed by the RTC configuration, these pins are set in an analog input mode.
For details about I/O control by the RTC, refer to Section 26.3: RTC functional description
on page 552.
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General-purpose I/Os (GPIO)
9.4
RM0376
GPIO registers
This section gives a detailed description of the GPIO registers.
For a summary of register bits, register address offsets and reset values, refer to Table 38.
The peripheral registers can be written in word, half word or byte mode.
9.4.1
GPIO port mode register (GPIOx_MODER) (x = A..D and H)
Address offset:0x00
Reset values:
31
30
•
0xEBFF FCFF for port A
•
0xFFFF FFFF for the other ports
29
MODE15[1:0]
28
MODE14[1:0]
27
26
MODE13[1:0]
25
24
MODE12[1:0]
23
22
MODE11[1:0]
21
20
MODE10[1:0]
19
18
17
16
MODE9[1:0]
MODE8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE7[1:0]
MODE6[1:0]
MODE5[1:0]
MODE4[1:0]
MODE3[1:0]
MODE2[1:0]
MODE1[1:0]
MODE0[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 2y+1:2y MODEy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O mode.
00: Input mode
01: General purpose output mode
10: Alternate function mode
11: Analog mode (reset state)
9.4.2
GPIO port output type register (GPIOx_OTYPER) (x = A..D and H)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OT15
OT14
OT13
OT12
OT11
OT10
OT9
OT8
OT7
OT6
OT5
OT4
OT3
OT2
OT1
OT0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 OTy: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain
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General-purpose I/Os (GPIO)
9.4.3
GPIO port output speed register (GPIOx_OSPEEDR)
(x = A..D and H)
Address offset: 0x08
Reset value:
31
30
OSPEED15
[1:0]
•
0x0C00 0000 for port A
•
0x0000 0000 for the other ports
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OSPEED14
[1:0]
OSPEED13
[1:0]
OSPEED12
[1:0]
OSPEED11
[1:0]
OSPEED10
[1:0]
OSPEED9
[1:0]
OSPEED8
[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OSPEED7
[1:0]
OSPEED6
[1:0]
OSPEED5
[1:0]
OSPEED4
[1:0]
OSPEED3
[1:0]
OSPEED2
[1:0]
OSPEED1
[1:0]
OSPEED0
[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 2y+1:2y OSPEEDy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O output speed.
00: Very low speed
01: Low speeed
10: Medium speed
11: High speed
Note: Refer to the device datasheet for the frequency specifications and the power supply
and load conditions for each speed.
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General-purpose I/Os (GPIO)
9.4.4
RM0376
GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A..D and H)
Address offset: 0x0C
Reset values:
31
30
•
0x2400 0000 for port A
•
0x0000 0000 for the other ports
29
PUPD15[1:0]
28
PUPD14[1:0]
27
26
PUPD13[1:0]
25
24
23
22
21
20
19
18
17
16
PUPD12[1:0]
PUPD11[1:0]
PUPD10[1:0]
PUPD9[1:0]
PUPD8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PUPD7[1:0]
PUPD6[1:0]
PUPD5[1:0]
PUPD4[1:0]
PUPD3[1:0]
PUPD2[1:0]
PUPD1[1:0]
PUPD0[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 2y+1:2y PUPDy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
9.4.5
GPIO port input data register (GPIOx_IDR) (x = A..D and H)
Address offset: 0x10
Reset value: 0x0000 XXXX (where X means undefined)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 IDy: Port input data bit (y = 0..15)
These bits are read-only. They contain the input value of the corresponding I/O port.
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General-purpose I/Os (GPIO)
9.4.6
GPIO port output data register (GPIOx_ODR) (x = A..D and H)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ODy: Port output data bit (y = 0..15)
These bits can be read and written by software.
Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the
GPIOx_BSRR or GPIOx_BRR registers (x = A..F).
9.4.7
GPIO port bit set/reset register (GPIOx_BSRR) (x = A..D and H)
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BR15
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BS15
BS14
BS13
BS12
BS11
BS10
BS9
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Bits 31:16 BRy: Port x reset bit y (y = 0..15)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Resets the corresponding ODx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BSy: Port x set bit y (y= 0..15)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Sets the corresponding ODx bit
9.4.8
GPIO port configuration lock register (GPIOx_LCKR)
(x = A..D and H)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
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RM0376
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next reset.
Note:
A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LCKK
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LCK15
LCK14
LCK13
LCK12
LCK11
LCK10
LCK9
LCK8
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until an MCU reset
occurs.
LOCK key write sequence:
WR LCKR[16] = ‘1’ + LCKR[15:0]
WR LCKR[16] = ‘0’ + LCKR[15:0]
WR LCKR[16] = ‘1’ + LCKR[15:0]
RD LCKR
RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit will
return ‘1’ until the next CPU reset.
Bits 15:0 LCKy: Port x lock bit y (y= 0..15)
These bits are read/write but can only be written when the LCKK bit is ‘0.
0: Port configuration not locked
1: Port configuration locked
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General-purpose I/Os (GPIO)
9.4.9
GPIO alternate function low register (GPIOx_AFRL) (x = A..D and H)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
27
AFSEL7[3:0]
26
25
24
23
AFSEL6[3:0]
22
21
20
19
AFSEL5[3:0]
18
17
16
AFSEL4[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
AFSEL3[3:0]
rw
rw
rw
AFSEL2[3:0]
rw
rw
AFSEL1[3:0]
rw
rw
AFSEL0[3:0]
rw
rw
rw
18
17
16
Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 0..7)
These bits are written by software to configure alternate function I/Os
AFSELy selection:
0000: AF0
0001: AF1 (Port A, B, C, D only)
0010: AF2 (Port A, B, C only)
0011: AF3 (Port A, B and C only)
0100: AF4 (Port A and B only)
0101: AF5 (Port A and B only)
0110: AF6 (Port A and B only)
0111: AF7 (Port A only)
9.4.10
1000: Reserved
1001: Reserved
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
GPIO alternate function high register (GPIOx_AFRH)
(x = A..D and H)
Address offset: 0x24
Reset value: 0x0000 0000
31
30
29
28
27
AFSEL15[3:0]
26
25
24
23
AFSEL14[3:0]
22
21
20
19
AFSEL13[3:0]
AFSEL12[3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AFSEL11[3:0]
rw
rw
rw
AFSEL10[3:0]
rw
rw
rw
rw
AFSEL9[3:0]
rw
rw
rw
rw
AFSEL8[3:0]
rw
rw
rw
rw
rw
Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 8..15)
These bits are written by software to configure alternate function I/Os
AFSELy selection:
0000: AF0
0001: AF1 (Port A, B, C, D only)
0010: AF2 (Port A, B, C only)
0011: AF3 (Port A, B and C only)
0100: AF4 (Port A and B only)
0101: AF5 (Port A and B only)
0110: AF6 (Port A and B only)
0111: AF7 (Port A only)
1000: Reserved
1001: Reserved
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
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General-purpose I/Os (GPIO)
9.4.11
RM0376
GPIO port bit reset register (GPIOx_BRR) (x = A..D and H)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BR15
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Bits 31:16 Reserved
Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15)
These bits are write-only. A read to these bits returns the value 0x0000
0: No action on the corresponding ODx bit
1: Reset the corresponding ODx bit
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BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIOx_LCKR
(where x = A..D,H)
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
0
0
LCK6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x10
Res.
Res.
0x14
GPIOx_ODR
(where x = A..D,H)
DocID025941 Rev 1
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Reset value
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Reset value
OD14
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GPIOx_OTYPER
(where x = A..D,H)
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OT1
OT0
0
0
0
0
0
0
0
0
0
0
OSPEED0[1:0]
MODE0[1:0]
MODE1[1:0]
1
OSPEED0[1:0]
OT2
1
PUPD0[1:0]
OT3
OSPEED1[1:0]
MODE2[1:0]
1
OSPEED1[1:0]
OT4
1
PUPD1[1:0]
OT5
OSPEED2[1:0]
MODE3[1:0]
1
OSPEED2[1:0]
OT6
MODE4[1:0]
1
PUPD2[1:0]
OT7
OSPEED3[1:0]
0
OSPEED3[1:0]
OT8
MODE5[1:0]
MODE6[1:0]
MODE7[1:0]
MODE8[1:0]
MODE9[1:0]
MODE10[1:0]
MODE11[1:0]
MODE12[1:0]
MODE13[1:0]
MODE14[1:0]
MODE15[1:0]
1
PUPD3[1:0]
OT9
OSPEED4[1:0]
0
OSPEED4[1:0]
0
PUPD4[1:0]
OT11
OT10
OSPEED5[1:0]
0
OSPEED5[1:0]
OT12
0
PUPD5[1:0]
OT13
OSPEED6[1:0]
0
OSPEED6[1:0]
0
PUPD6[1:0]
0
0
1
PUPD0[1:0]
1
0
1
PUPD1[1:0]
1
0
1
PUPD2[1:0]
0
1
PUPD3[1:0]
0
1
PUPD4[1:0]
1
Res.
1
PUPD5[1:0]
OSPEED7[1:0]
OSPEED8[1:0]
1
OT14
OSPEED7[1:0]
OSPEED8[1:0]
1
OT15
PUPD7[1:0]
PUPD8[1:0]
Reset value
Res.
1
PUPD6[1:0]
PUPD7[1:0]
PUPD8[1:0]
OSPEED9[1:0]
OSPEED10[1:0]
OSPEED11[1:0]
OSPEED12[1:0]
OSPEED13[1:0]
OSPEED14[1:0]
OSPEED15[1:0]
Reset value
OD15
Res.
OSPEED9[1:0]
0
LCK7
0
Res.
PUPD9[1:0]
0
BS8
0
PUPD9[1:0]
0
BS9
0
Res.
0
0
LCK8
0
Res.
0
Res.
OSPEED10[1:0]
0
0
LCK9
0
Res.
PUPD10[1:0]
0
0
0
BS11
0
PUPD10[1:0]
0
0
1
BS10
0
Res.
0
0
1
LCK11
0
Res.
0
Res.
OSPEED11[1:0]
0
Res.
PUPD11[1:0]
0
0
1
LCK10
0
PUPD11[1:0]
0
0
1
BS12
0
Res.
0
1
BS13
0
Res.
0
0
Res.
OSPEED12[1:0]
1
Res.
PUPD12[1:0]
0
0
1
LCK12
0
PUPD12[1:0]
0
0
1
LCK13
0
Res.
0
0
1
BS14
0
Res.
0
1
Res.
OSPEED13[1:0]
0
Res.
PUPD13[1:0]
1
PUPD13[1:0]
0
1
0
BS15
0
Res.
0
0
1
LCK14
0
Res.
OSPEED14[1:0]
0
0
Res.
PUPD14[1:0]
0
Res.
0
PUPD14[1:0]
Reset value
0
1
BR0
0
Res.
GPIOA_PUPDR
0
1
LCKK
LCK15
Reset value
GPIOx_IDR
(where x = A..D,H)
Res.
Reset value
1
Res.
GPIOx_OSPEEDR
(where x = B,C,H)
0
Res.
Reset value
OSPEED15[1:0]
GPIOA_OSPEEDR
1
Res.
BR12
0x1C
GPIOx_BSRR
(where x = A..D,H)
BR13
0x18
Res.
0x0C
GPIOx_MODER
(where x = A,B,C,H)
PUPD15[1:0]
0x08
Res.
GPIOx_PUPDR
(where x = B,C,H)
Res.
Reset value
PUPD15[1:0]
0x0C
Res.
0x08
MODE0[1:0]
MODE1[1:0]
MODE2[1:0]
MODE3[1:0]
MODE4[1:0]
MODE5[1:0]
MODE6[1:0]
MODE7[1:0]
MODE8[1:0]
MODE9[1:0]
MODE10[1:0]
MODE11[1:0]
MODE12[1:0]
MODE13[1:0]
MODE14[1:0]
MODE15[1:0]
GPIOA_MODER
Res.
0x04
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
0x00
BR14
0x00
BR15
Offset
Res.
9.4.12
Res.
RM0376
General-purpose I/Os (GPIO)
GPIO register map
The following table gives the GPIO register map and reset values.
Table 38. GPIO register map and reset values
1
1
1
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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General-purpose I/Os (GPIO)
RM0376
0x20
GPIOx_AFRL
AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]
(where x = A..D,H)
0x24
GPIOx_AFRH
AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0] AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0]
(where x = A..D,H)
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x28
GPIOx_BRR
(where x = A..D,H)
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 38. GPIO register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
Refer to Section 2.2.2 for the register boundary addresses.
228/869
0
BR0
0
BR1
0
BR2
0
BR3
0
BR4
0
BR5
0
BR6
0
BR7
0
BR8
0
BR9
0
BR11
0
BR10
0
BR12
0
BR13
0
BR14
0
Res.
0
BR15
Reset value
DocID025941 Rev 1
RM0376
System configuration controller (SYSCFG)
10
System configuration controller (SYSCFG)
10.1
Introduction
The devices feature a set of configuration registers. The main purposes of the system
configuration controller are the following:
•
Remapping memories
•
Remapping some trigger sources to timer input capture channels
•
Managing external interrupts line multiplexing to the internal edge detector
•
Enabling dedicated functions such as input capture multiplexing or oscillator pin
remapping
•
I2C Fm+ mode management
•
Firewall management
•
Temperature sensor and Internal voltage reference management (including for
Comparator, 48 MHz HSI and ADC purposes).
The Cortex®-M0+ can wake up from WFE (Wait For Event) when a transition occurs on the
eventin input signal. To support semaphore management in multiprocessor environment,
the core can also output events on the signal output EVENTOUT, during SEV instruction
execution.
In STM32L0x2 devices, an event input can be generated by an external interrupt line or by
an RTC alarm interrupt. It is also possible to select which output pin is connected to the
EVENTOUT signal of the Cortex®-M0+. The EVENTOUT multiplexing is managed by the
GPIO alternate function capability (see Section 9.4.9: GPIO alternate function low register
(GPIOx_AFRL) (x = A..D and H) and Section 9.4.10: GPIO alternate function high register
(GPIOx_AFRH) (x = A..D and H)).
Note:
EVENTOUT is not mapped on all GPIOs (for example PC13, PC14, PC15).
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System configuration controller (SYSCFG)
10.2
RM0376
SYSCFG registers
The peripheral registers have to be accessed by words (32-bit).
10.2.1
SYSCFG memory remap register (SYSCFG_CFGR1)
This register is used for specific configurations related to memory remap:
Note:
This register is not reset through the SYSCFGRST bit in the RCC_APB2RSTR register.
Address offset: 0x00
Reset value: 0x000x 000x (X is the memory mode selected by the BOOT pins)
)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
9
8
1
0
15
14
13
12
11
10
Res.
Res.
Res.
Res.
Res.
Res.
BOOT_MODE
r
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
r
MEM_MODE
rw
rw
Bits 31:2 Reserved, must be kept at reset value
Bits 9:8 BOOT_MODE: Boot mode selected by the boot pins status bits
These bits are read-only. They indicate the boot mode selected by the boot pins. Bit 9
corresponds to the complement of BOOT1 bit in the FLASH_OPTR register. Its value is
defined in the option bytes (see Section 2.4: Boot configuration on page 52). Bit 8
corresponds to the value sampled on the BOOT0 pin.
00: Main Flash memory boot mode
01: System Flash memory boot mode
10: Reserved
11: Embedded SRAM boot mode
Bits 7:2 Reserved, must be kept at reset value
Bits 1:0 MEM_MODE: Memory mapping selection bits
These bits are set and cleared by software. This bit controls the memory’s internal mapping
at address 0x0000 0000. After reset these bits take on the memory mapping selected by the
BOOT pins.
00: Main Flash memory mapped at 0x0000 0000
01: System Flash memory mapped at 0x0000 0000
10: reserved
11: SRAM mapped at 0x0000 0000.
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RM0376
System configuration controller (SYSCFG)
10.2.2
SYSCFG peripheral mode configuration register (SYSCFG_CFGR2)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
Res.
Res.
Res.
Res.
Res.
Res.
I2C2_FMP I2C1_FMP
rw
I2C_PB9 I2C_PB8 I2C_PB7 I2C_PB6
_FMP
_FMP
_FMP
_FMP
rw
18
17
2
1
Res.
rw
16
Res. Res.
rw
Res.
0
FWDIS
rw
rw
Bits 31:14 Reserved, must be kept at reset value
Bit 13 I2C2 FMP: I2C2 Fm+ drive capability enable bit
This bit is set and cleared by software. When it is set, Fm+ mode is enabled on I2C2 pins
PB13 and PB14 selected through the IOPORT control registers AF selection bits.
Bit 12 I2C1 FMP: I2C1 Fm+ drive capability enable bit
This bit is set and cleared by software. When it is set, Fm+ mode is enabled on I2C1 pins
selected through the IOPORT control registers AF selection bits. This bit is bit is OR-ed with
I2C_PBx_FMP bits.
Bit 11 I2C PB9 FMP: Fm+ drive capability on PB9 enable bit
This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB9.
Bit 10 I2C PB8 FMP: Fm+ drive capability on PB8 enable bit
This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB8.
Bit 9 I2C PB7 FMP: Fm+ drive capability on PB7 enable bit
This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB7.
Bit 8 I2C PB6 FMP: Fm+ drive capability on PB6 enable bit
This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB6.
Bits 7:1 Reserved, must be kept at reset value
Bit 0 FWDIS: Firewall disable bit
This bit is set by default (after reset). It is cleared by software to protect the access to the
memory segments according to the Firewall configuration.Once cleared it cannot be set by
software. Only a system reset set the bit.
0: Firewall access enabled
1: Firewall access disabled
Note: This bit cannot be set by an APB reset. A system reset is required to set it.
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237
System configuration controller (SYSCFG)
10.2.3
RM0376
Reference control and status register (REF_CFGR3)
The REF_CFGR3 register is the reference control/status register. It contains all the
bits/flags related to VREFINT and temperature sensor.
Address offset: 0x20
System reset value: 0x0000 0000
31
REF_
LOCK
30
29
28
27
26
VREFINT
SENSOR_
REF_
VREFINT
VREFINT_A
_COMP_
ADC_RDY HSI48MHz
_RDYF
DC_RDYF.
RDYF
F
_ RDYF
rs
r
15
14
Res.
Res.
r
r
r
r
13
12
11
10
ENREF_ ENBUF_VR
HSI48MH
EFINT_
z
COMP
rw
rw
Res.
Res.
25
24
Res.
Res.
9
8
23
22
21
20
19
18
17
Res. Res. Res. Res. Res. Res. Res.
7
6
5
4
3
2
rw
rw
Res.
1
ENBUF_ ENBUF_
SEL_VREF
SENSOR VREFINT Res. Res.
Res. Res. Res.
_OUT
_ADC
_ ADC
rw
16
rw
0
EN_
VREF
INT
rw
Bit 31 REF_LOCK: REF_CFGR3 lock bit
This bit is set by software and cleared by a hardware system reset. It locks the whole
content of the reference control/Status register, REF_CFGR3[31:0].
0: REF_CFGR3[31:0] bits are read/write
1: REF_CFGR3[31:0] bits are read-only
Bit 30 VREFINT_RDYF: VREFINT ready flag
This bit is read-only. It shows the state of the internal voltage reference, VREFINT. When
set, it indicates that VREFINT is available for BOR, PVD.
0: VREFINT OFF
1: VREFINT ready
Bit 29 VREFINT_COMP_RDYF: VREFINT for comparator ready flag
This bit is read-only. It shows the state of the buffered internal voltage reference, VREFINT.
When set, it indicates that VREFINT is available for comparators.
0: VREFINT buffer for comparator not ready
1: VREFINT for comparator ready
Bit 28 VREFINT_ADC_RDYF: VREFINT for ADC ready flag
This bit is read-only. It shows the state of the internal voltage reference, VREFINT. When
set, it indicates that VREFINT is available for the ADC.
0: VREFINT buffer for ADC not ready
1: VREFINT for ADC ready
Bit 27 SENSOR_ADC_RDYF: Temperature sensor for ADC ready flag
This bit is read-only. It shows the state of the temperature sensor for the ADC. When set, it
indicates that the temperature sensor is available for the ADC.
0: Temperature sensor buffer for ADC not ready
1: Temperature sensor for ADC ready
Bit 26 REF_HSI48_RDYF: VREFINT for HSI48 ready flag
This bit is read-only. It shows the state of the buffered internal voltage reference, VREFINT.
When set it indicates that the VREFINT is available for the HSI48 oscillator.
0: VREFINT buffer for HSI48 not ready
1: VREFINT to HSI48 ready
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System configuration controller (SYSCFG)
Bits 25:14 Reserved, must be kept at reset value
Bit 13 ENREF_HSI48: VREFINT reference for HSI48 oscillator enable bit
This bit is set and cleared by software (only if REF_LOCK not set).
0: Buffer used to generate VREFINT reference for the HSI48 oscillator switched OFF.
1: Buffer used to generate VREFINT reference for the HSI48oscillator switched ON.
Bit 12 ENBUF_VREFINT_COMP: VREFINT reference for comparator 2 enable bit
This bit is set and cleared by software (only if REF_LOCK not set).
0: Buffer used to generate VREFINT reference for comparator 2 switched OFF.
1: Buffer used to generate VREFINT reference for comparator 2 switched ON.
Bits 11:10 Reserved, must be kept at reset value
Bit 9 ENBUF_SENSOR_ADC: Temperature sensor reference for ADC enable bit
This bit is set and cleared by software (only if REF_LOCK not set).
0: Buffer used to generate the temperature sensor reference for the ADC switched OFF.
1: Buffer used to generate the temperature sensor reference for the ADC switched ON.
Bit 8 ENBUF_VREFINT_ADC: VREFINT reference for ADC enable bit
This bit is set and cleared by software (only if REF_LOCK not set).
0: Buffer used to generate VREFINT reference for the ADC switched OFF.
1: Buffer used to generate VREFINT reference for the ADC switched ON.
Bits 7:6 Reserved, must be kept at reset value
Bits 5:4 SEL_VREF_OUT: VREFINT_ADC connection bit
These bits are set and cleared by software (only if REF_LOCK not set). These bits select
which pad is connected to VREFINT_ADC when ENBUF_VREFINT_ADC is set.
00: no pad connected
01: PB0 connected
10: PB1 connected
11: PB0 and PB1 connected
Bits 3:1 Reserved, must be kept at reset value
Bit 0 EN_VREFINT: VREFINT enable bit
This bit is set and cleared by software (only if REF_LOCK not set). It switches ON the
VREFINT internal reference voltage and the temperature sensor.
0: VREFINT switched OFF.
1: VREFINT switched ON.
If this bit is locked at 1 in stop mode or sleep mode, VREFINT is always ON.
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System configuration controller (SYSCFG)
10.2.4
RM0376
SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1)
Address offset: 0x08
Reset value: 0x0000
31
30
29
28
27
26
25
24
23
22
21
20
19
6
5
4
3
18
17
16
2
1
0
Reserved
15
14
13
12
11
EXTI3[3:0]
rw
rw
rw
10
9
8
7
EXTI2[3:0]
rw
rw
rw
EXTI1[3:0]
rw
rw
rw
rw
rw
EXTI0[3:0]
rw
rw
rw
rw
rw
Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3)
These bits are written by software to select the source input for the EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin (only PD2)
0100: Reserved
0101: PH[x] (only PH[1:0])
Other configurations are reserved
10.2.5
SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2)
Address offset: 0x0C
Reset value: 0x0000
31
30
29
28
27
26
25
24
23
22
21
20
19
6
5
4
3
18
17
16
2
1
0
Reserved
15
14
13
12
11
EXTI7[3:0]
rw
rw
rw
10
9
8
7
EXTI6[3:0]
rw
rw
rw
EXTI5[3:0]
rw
rw
rw
rw
rw
EXTI4[3:0]
rw
rw
rw
rw
rw
Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7)
These bits are written by software to select the source input for the EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
Other configurations are reserved
10.2.6
SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3)
Address offset: 0x10
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System configuration controller (SYSCFG)
Reset value: 0x0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
5
4
3
2
1
0
rw
rw
rw
Reserved
15
14
13
12
11
rw
rw
EXTI11[3:0]
rw
rw
rw
10
9
8
7
6
rw
rw
rw
EXTI10[3:0]
rw
rw
EXTI9[3:0]
rw
EXTI8[3:0]
rw
rw
Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11)
These bits are written by software to select the source input for the EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
Other configurations are reserved.
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237
System configuration controller (SYSCFG)
10.2.7
RM0376
SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4)
Address offset: 0x14
Reset value: 0x0000
31
30
29
28
27
26
25
24
23
22
21
20
19
6
5
4
3
18
17
16
2
1
0
Reserved
15
14
13
12
11
10
EXTI15[3:0]
rw
rw
rw
9
8
7
EXTI14[3:0]
rw
rw
rw
EXTI13[3:0]
rw
rw
rw
rw
EXTI12[3:0]
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15)
These bits are written by software to select the source input for the EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
Other configurations are reserved.
10.2.8
SYSCFG register map
The following table gives the SYSCFG register map and the reset values.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_
EXTICR1
Res.
0x08
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
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0
0
0
0
0
0
EXTI2[3:0]
0
0
0
0
EXTI6[3:0]
0
0
0
0
EXTI11[3:0]
EXTI10[3:0]
0
0
0
0
0
0
0
0
MEM_MODE
Res.
Res.
Res.
Res.
0
EXTI1[3:0]
0
0
0
0
EXTI5[3:0]
0
0
0
0
EXTI9[3:0]
0
0
0
0
0
x
FWDISEN
Res.
Res.
0
Res.
I2C_PB6_FMP
0
Res.
Res.
I2C_PB7_FMP
0
Res.
I2C_PB8_FMP
0
x
Res.
I2C_PB9_FMP
0
EXTI7[3:0]
0
Res.
0x10
SYSCFG_
EXTICR3
Res.
Reset value
0
EXTI3[3:0]
0
Res.
0x0C
SYSCFG_
EXTICR2
Res.
Reset value
x
I2C1_FMP
Reset value
x
I2C2_FMP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_CFGR2
Res.
0x04
Res.
Reset value
BOOT_MODE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_CFGR1
Res.
0x00
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 39. SYSCFG register map and reset values
0
1
EXTI0[3:0]
0
0
0
0
EXTI4[3:0]
0
0
0
0
EXTI8[3:0]
0
0
0
0
RM0376
System configuration controller (SYSCFG)
0
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
0
EN_VREFINT
0
0
Res.
0
Res.
EXTI12[3:0]
SEL_VREF_OUT
0
Res.
0
Res.
ENBUF_VREFINT_COMP
Res.
ENREF_HSI48
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res.
0
Res.
REF_HSI48_RDYF
0
Res.
SENSOR_ADC_RDYF
0
Res.
VREFINT_ADC_RDYF
0
Res.
VREFINT_COMP_RDYF
Reset value
REF_LOCK
REF_CFGR3
EXTI13[3:0]
Refer to Section 16: Comparator (COMP)
VREFINT_RDYF
0x20
EXTI14[3:0]
ENBUF_VREFINT_ADC
Reset value
EXTI15[3:0]
ENBUF_SENSOR_ADC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
COMP2_CTRL
Res.
0x1C
Res.
COMP1_CTRL
Res.
0x18
Res.
SYSCFG_
EXTICR4
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x14
Res.
Register
Res.
Offset
Res.
Table 39. SYSCFG register map and reset values (continued)
0
0
0
Refer to Section 2.2.2 for the register boundary addresses.
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Direct memory access controller (DMA)
RM0376
11
Direct memory access controller (DMA)
11.1
Introduction
Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The DMA controller has up to 7 channels in total, each dedicated to managing memory
access requests from one or more peripherals. It has an arbiter for handling the priority
between DMA requests.
11.2
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DMA main features
•
Up to 7 independently configurable channels (requests)
•
Each channel is connected to dedicated hardware DMA requests, software trigger is
also supported on each channel. This configuration is done by software.
•
Priorities between requests from the DMA channels are software programmable (4
levels consisting of very high, high, medium, low) or hardware in case of equality
(request 1 has priority over request 2, etc.)
•
Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
•
Support for circular buffer management
•
3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel
•
Memory-to-memory transfer
•
Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers
•
Access to Flash, SRAM, APB and AHB peripherals as source and destination
•
Programmable number of data to be transferred: up to 65535
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Direct memory access controller (DMA)
The block diagram is shown in the following figure.
Figure 28. DMA block diagram
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11.3
DMA functional description
The DMA controller performs direct memory transfer by sharing the system bus with the
Cortex®-M0+ core. The DMA request may stop the CPU access to the system bus for some
bus cycles, when the CPU and DMA are targeting the same destination (memory or
peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half
of the system bus bandwidth (both to memory and peripheral) for the CPU.
11.3.1
DMA transactions
After an event, the peripheral sends a request signal to the DMA Controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA
Controller. The peripheral releases its request as soon as it gets the Acknowledge from the
DMA Controller. Once the request is de-asserted by the peripheral, the DMA Controller
release the Acknowledge. If there are more requests, the peripheral can initiate the next
transaction.
In summary, each DMA transfer consists of three operations:
•
The loading of data from the peripheral data register or a location in memory addressed
through an internal current peripheral/memory address register. The start address used
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Direct memory access controller (DMA)
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for the first transfer is the base peripheral/memory address programmed in the
DMA_CPARx or DMA_CMARx register
11.3.2
•
The storage of the data loaded to the peripheral data register or a location in memory
addressed through an internal current peripheral/memory address register. The start
address used for the first transfer is the base peripheral/memory address programmed
in the DMA_CPARx or DMA_CMARx register
•
The post-decrementing of the DMA_CNDTRx register, which contains the number of
transactions that have still to be performed.
Arbiter
The arbiter manages the channel requests based on their priority and launches the
peripheral/memory access sequences.
The priorities are managed in two stages:
•
•
11.3.3
Software: each channel priority can be configured in the DMA_CCRx register. There
are four levels:
–
Very high priority
–
High priority
–
Medium priority
–
Low priority
Hardware: if 2 requests have the same software priority level, the channel with the
lowest number will get priority versus the channel with the highest number. For
example, channel 2 gets priority over channel 4.
DMA channels
Each channel can handle DMA transfer between a peripheral register located at a fixed
address and a memory address. The amount of data to be transferred (up to 65535) is
programmable. The register which contains the amount of data items to be transferred is
decremented after each transaction.
Programmable data sizes
Transfer data sizes of the peripheral and memory are fully programmable through the
PSIZE and MSIZE bits in the DMA_CCRx register.
Pointer incrementation
Peripheral and memory pointers can optionally be automatically post-incremented after
each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If
incremented mode is enabled, the address of the next transfer will be the address of the
previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer
address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During
transfer operations, these registers keep the initially programmed value. The current
transfer addresses (in the current internal peripheral/memory address register) are not
accessible by software.
If the channel is configured in non-circular mode, no DMA request is served after the last
transfer (that is once the number of data items to be transferred has reached zero). In order
to reload a new number of data items to be transferred into the DMA_CNDTRx register, the
DMA channel must be disabled.
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Note:
Direct memory access controller (DMA)
If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers
(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during
the channel configuration phase.
In circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded
with the initially programmed value. The current internal address registers are reloaded with
the base address values from the DMA_CPARx/DMA_CMARx registers.
Channel configuration procedure
The following sequence should be followed to configure a DMA channel x (where x is the
channel number).
1.
Set the peripheral register address in the DMA_CPARx register. The data will be
moved from/ to this address to/ from the memory after the peripheral event.
2.
Set the memory address in the DMA_CMARx register. The data will be written to or
read from this memory after the peripheral event.
3.
Configure the total number of data to be transferred in the DMA_CNDTRx register.
After each peripheral event, this value will be decremented.
4.
Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register
5.
Configure data transfer direction, circular mode, peripheral & memory incremented
mode, peripheral & memory data size, and interrupt after half and/or full transfer in the
DMA_CCRx register
6.
Activate the channel by setting the ENABLE bit in the DMA_CCRx register.
As soon as the channel is enabled, it can serve any DMA request from the peripheral
connected on the channel.
Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is
generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer,
the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer
Complete Interrupt Enable bit (TCIE) is set.
Circular mode
Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC
scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register.
When circular mode is activated, the number of data to be transferred is automatically
reloaded with the initial value programmed during the channel configuration phase, and the
DMA requests continue to be served.
Memory-to-memory mode
The DMA channels can also work without being triggered by a request from a peripheral.
This mode is called Memory to Memory mode.
If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers
as soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx
register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory to
Memory mode may not be used at the same time as Circular mode.
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11.3.4
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Programmable data width, data alignment and endians
When PSIZE and MSIZE are not equal, the DMA performs some data alignments as
described in Table 40: Programmable data width & endian behavior (when bits PINC =
MINC = 1).
Table 40. Programmable data width & endian behavior (when bits PINC = MINC = 1)
Number
Source
of data
Destination
port
items to
port width
width
transfer
(NDT)
Source content:
address / data
Transfer operations
Destination
content:
address / data
8
8
4
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0
2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1
3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2
4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
8
16
4
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0
2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2
3: READ B3[7:0] @0x2 then WRITE 00B2[15:0] @0x4
4: READ B4[7:0] @0x3 then WRITE 00B3[15:0] @0x6
@0x0 / 00B0
@0x2 / 00B1
@0x4 / 00B2
@0x6 / 00B3
8
32
4
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0
2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4
3: READ B3[7:0] @0x2 then WRITE 000000B2[31:0] @0x8
4: READ B4[7:0] @0x3 then WRITE 000000B3[31:0] @0xC
@0x0 / 000000B0
@0x4 / 000000B1
@0x8 / 000000B2
@0xC / 000000B3
16
8
4
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0
2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1
3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2
4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3
@0x0 / B0
@0x1 / B2
@0x2 / B4
@0x3 / B6
16
16
4
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0
2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2
3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4
4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
16
32
4
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0
2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4
3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8
4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC
@0x0 / 0000B1B0
@0x4 / 0000B3B2
@0x8 / 0000B5B4
@0xC / 0000B7B6
32
8
4
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0
2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1
3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2
4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3
@0x0 / B0
@0x1 / B4
@0x2 / B8
@0x3 / BC
32
16
4
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[:0] @0x0
2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[:0] @0x
3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[:0] @0x
4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[:0] @0x
@0x0 / B1B0
@0x2 / B5B4
@0x4 / B9B8
@0x6 / BDBC
4
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
@0x0 / B3B2B1B0
1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0
@0x4 / B7B6B5B4
2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4
@0x8 / BBBAB9B8
3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8
@0xC /
4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC
BFBEBDBC
32
32
Addressing an AHB peripheral that does not support byte or halfword write
operations
When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on
the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does
not support byte or halfword write operations (when HSIZE is not used by the peripheral)
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and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two
examples below:
•
To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD”
with HSIZE = HalfWord
•
To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with
HSIZE = Byte
Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the
HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit
APB operation in the following manner:
•
an AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be
converted to an APB word write operation of the data “0xB0B0B0B0” to 0x0
•
an AHB halfword write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be
converted to an APB word write operation of the data “0xB1B0B1B0” to 0x0
For instance, if you want to write the APB backup registers (16-bit registers aligned to a 32bit address boundary), you must configure the memory source size (MSIZE) to “16-bit” and
the peripheral destination size (PSIZE) to “32-bit”.
11.3.5
Error management
A DMA transfer error can be generated by reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or a write access, the faulty
channel is automatically disabled through a hardware clear of its EN bit in the corresponding
Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag
(TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error
interrupt enable bit (TEIE) in the DMA_CCRx register is set.
11.3.6
DMA interrupts
An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for
each DMA channel. Separate interrupt enable bits are available for flexibility.
Table 41. DMA interrupt requests
Interrupt event
Event flag
Enable control bit
Half-transfer
HTIF
HTIE
Transfer complete
TCIF
TCIE
Transfer error
TEIF
TEIE
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11.3.7
RM0376
DMA request mapping
DMA controller
The hardware requests from the peripherals (TIM2/6, ADC, DAC, SPI1/2, I2C1/2, AES
(available only on Cat. 2 with AES), USART1/2 and LPUART1) are mapped to the DMA
channels (1 to 7) through the DMA channel selection register (s). On one channel, only one
request must be enabled at a time. Refer to Figure 29: DMA request mapping.
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.
Figure 29. DMA request mapping
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Table 42 lists the DMA requests for each channel.
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Table 42. Summary of the DMA requests for each channel
Request
Channel
Peripherals
number
1
0
ADC
1
SPI1
2
SPI2
3
Channel 2
ADC
Channel 3
Channel 4 Channel 5
Channel 6
Channel 7
SPI2_RX
SPI2_TX
USART2_
RX
USART2_
TX
ADC
SPI1_RX
SPI1_TX
SPI2_RX
SPI2_TX
USART1
USART1_T
USART1_
USART1_RX
X
TX
USART1_
RX
4
USART2
USART2_
TX
USART2_
RX
5
LPUART1
LPUART1_
TX
LPUART1_
RX
6
I2C1
I2C1_TX
I2C1_RX
7
I2C2
8
TIM2
9
TIM6_UP
/DAC_
channel1
11
AES(1)
LPUART1_ LPUART1_
RX
TX
I2C1_TX
I2C2_TX
TIM2_
CH3
TIM2_UP
TIM2_CH2
I2C1_RX
I2C2_RX
TIM2_CH4 TIM2_CH1
TIM2_CH2
TIM2_CH4
TIM6/DAC_
channel1
AES_IN
AES_OUT
AES_OUT
AES_IN
1. Available only on Cat. 2 with AES.
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11.4
RM0376
DMA registers
Refer to Section 1.1 on page 43 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32bit).
11.4.1
DMA interrupt status register (DMA_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
TEIF7
HTIF7
TCIF7
GIF7
TEIF6
HTIF6
TCIF6
GIF6
TEIF5
HTIF5
TCIF5
GIF5
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TEIF4
HTIF4
TCIF4
GIF4
TEIF3
HTIF3
TCIF3
GIF3
TEIF2
HTIF2
TCIF2
GIF2
TEIF1
HTIF1
TCIF1
GIF1
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:28 Reserved, must be kept at reset value.
Bits 27, 23, 19, 15, TEIFx: Channel x transfer error flag (x = 1 ..7)
11, 7, 3 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer error (TE) on channel x
1: A transfer error (TE) occurred on channel x
Bits 26, 22, 18, 14, HTIFx: Channel x half transfer flag (x = 1 ..7)
10, 6, 2 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No half transfer (HT) event on channel x
1: A half transfer (HT) event occurred on channel x
Bits 25, 21, 17, 13, TCIFx: Channel x transfer complete flag (x = 1 ..7)
9, 5, 1 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer complete (TC) event on channel x
1: A transfer complete (TC) event occurred on channel x
Bits 24, 20, 16, 12, GIFx: Channel x global interrupt flag (x = 1 ..7)
8, 4, 0 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No TE, HT or TC event on channel x
1: A TE, HT or TC event occurred on channel x
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11.4.2
DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
CHTIF
CTCIF7
7
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
CTEIF
7
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CTEIF
4
CHTIF
4
CTCIF
4
CGIF4
CTEIF
3
w
w
w
w
w
CHTIF
CTCIF3
3
w
w
CGIF7
CGIF3
w
CTEIF6 CHTIF6 CTCIF6 CGIF6
CTEIF2 CHTIF2 CTCIF2 CGIF2
w
w
w
w
CTEIF5 CHTIF5 CTCIF5
CTEIF1 CHTIF1 CTCIF1
w
w
w
CGIF5
CGIF1
w
Bits 31:28 Reserved, must be kept at reset value.
Bits 27, 23, 19, 15, CTEIFx: Channel x transfer error clear (x = 1 ..7)
11, 7, 3 This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TEIF flag in the DMA_ISR register
Bits 26, 22, 18, 14, CHTIFx: Channel x half transfer clear (x = 1 ..7)
10, 6, 2 This bit is set and cleared by software.
0: No effect
1: Clears the corresponding HTIF flag in the DMA_ISR register
Bits 25, 21, 17, 13, CTCIFx: Channel x transfer complete clear (x = 1 ..7)
9, 5, 1 This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TCIF flag in the DMA_ISR register
Bits 24, 20, 16, 12, CGIFx: Channel x global interrupt clear (x = 1 ..7)
8, 4, 0 This bit is set and cleared by software.
0: No effect
1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register
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11.4.3
RM0376
DMA channel x configuration register (DMA_CCRx) (x = 1..7,
where x= channel number)
Address offset: 0x08 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
MEM2
MEM
MINC
PINC
CIRC
DIR
TEIE
HTIE
TCIE
EN
rw
rw
rw
rw
rw
rw
rw
rw
rw
PL[1:0]
rw
rw
MSIZE[1:0]
PSIZE[1:0]
rw
rw
rw
rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 MEM2MEM: Memory to memory mode
This bit is set and cleared by software.
0: Memory to memory mode disabled
1: Memory to memory mode enabled
Bits 13:12 PL[1:0]: Channel priority level
These bits are set and cleared by software.
00: Low
01: Medium
10: High
11: Very high
Bits 11:10 MSIZE[1:0]: Memory size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bits 9:8 PSIZE[1:0]: Peripheral size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bit 7 MINC: Memory increment mode
This bit is set and cleared by software.
0: Memory increment mode disabled
1: Memory increment mode enabled
Bit 6 PINC: Peripheral increment mode
This bit is set and cleared by software.
0: Peripheral increment mode disabled
1: Peripheral increment mode enabled
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RM0376
Direct memory access controller (DMA)
Bit 5 CIRC: Circular mode
This bit is set and cleared by software.
0: Circular mode disabled
1: Circular mode enabled
Bit 4 DIR: Data transfer direction
This bit is set and cleared by software.
0: Read from peripheral
1: Read from memory
Bit 3 TEIE: Transfer error interrupt enable
This bit is set and cleared by software.
0: TE interrupt disabled
1: TE interrupt enabled
Bit 2 HTIE: Half transfer interrupt enable
This bit is set and cleared by software.
0: HT interrupt disabled
1: HT interrupt enabled
Bit 1 TCIE: Transfer complete interrupt enable
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled
Bit 0 EN: Channel enable
This bit is set and cleared by software.
0: Channel disabled
1: Channel enabled
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Direct memory access controller (DMA)
11.4.4
RM0376
DMA channel x number of data register (DMA_CNDTRx) (x = 1..7,
where x= channel number)
Address offset: 0x0C + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
NDT[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0]: Number of data to transfer
Number of data to be transferred (0 up to 65535). This register can only be written when the
channel is disabled. Once the channel is enabled, this register is read-only, indicating the
remaining bytes to be transmitted. This register decrements after each DMA transfer.
Once the transfer is completed, this register can either stay at zero or be reloaded
automatically by the value previously programmed if the channel is configured in auto-reload
mode.
If this register is zero, no transaction can be served whether the channel is enabled or not.
11.4.5
DMA channel x peripheral address register (DMA_CPARx) (x = 1..7,
where x = channel number)
Address offset: 0x10 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
This register must not be written when the channel is enabled.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PA [31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
PA [15:0]
rw
Bits 31:0 PA[31:0]: Peripheral address
Base address of the peripheral data register from/to which the data will be read/written.
When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address.
When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word
address.
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RM0376
Direct memory access controller (DMA)
11.4.6
DMA channel x memory address register (DMA_CMARx) (x = 1..7,
where x = channel number)
Address offset: 0x14 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
This register must not be written when the channel is enabled.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MA [31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
MA [15:0]
rw
Bits 31:0 MA[31:0]: Memory address
Base address of the memory area from/to which the data will be read/written.
When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address.
When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word
address.
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Direct memory access controller (DMA)
11.4.7
RM0376
DMA channel selection register (DMA_CSELR)
Address offset: 0xA8
Reset value: 0x0000 0000
This register is used to manage the remapping of DMA channels (see Figure 29).
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
27
rw
rw
25
24
23
22
C7S [3:0]
20
19
18
17
16
C5S [3:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
C3S [3:0]
rw
21
C6S [3:0]
rw
C4S [3:0]
rw
26
rw
rw
C2S [3:0]
rw
rw
rw
rw
rw
C1S [3:0]
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 C7S[3:0]: DMA channel 7 selection
0010: DMA channel 7 remapped to SPI2_TX
0100: DMA channel 7 remapped to USART2_TX
0101: DMA channel 7 remapped to LPUART1_TX
0110: DMA channel 7 remapped to I2C1_RX
1000: DMA channel 7 remapped to TIM2_CH2/TIM2_CH4
Other configurations: DMA channel 7 not remapped
Bits 23:20 C6S[3:0]: DMA channel 6 selection
0010: DMA channel 6 remapped to SPI2_RX
0100: DMA channel 6 remapped to USART2_RX
0101: DMA channel 6 remapped to LPUART1_RX
0110: DMA channel 6 remapped to I2C1_TX
Other configurations: DMA channel 6 not remapped
Bits 19:16 C5S[3:0]: DMA channel 5 selection
0010: DMA channel 5 remapped to SPI2_TX
0011: DMA channel 5 remapped to USART1_RX
0100: DMA channel 5 remapped to USART2_RX
0111: DMA channel 5 remapped to I2C2_RX
1000: DMA channel 5 remapped to TIM2_CH1
1011: DMA channel 5 remapped to AES_IN (available only on Cat. 2 with AES, otherwise
not remapped)
Other configurations: DMA channel 5 not remapped
Bits 15:12 C4S[3:0]: DMA channel 4 selection
0010: DMA channel 4 remapped to SPI2_RX
0011: DMA channel 4 remapped to USART1_TX
0100: DMA channel 4 remapped to USART2_TX
0111: DMA channel 4 remapped to I2C2_TX
1000: DMA channel 4 remapped to TIM2_CH4
Other configurations: DMA channel 4 not remapped
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Direct memory access controller (DMA)
Bits 11:8 C3S[3:0]: DMA channel 3 selection
0001: DMA channel 3 remapped to SPI1_TX
0011: DMA channel 3 remapped to USART1_RX
0101: DMA channel 3 remapped to LPUART1_RX
0110: DMA channel 3 remapped to I2C1_RX
1000: DMA channel 3 remapped to TIM2_CH2
1011: DMA channel 3 remapped to AES_OUT(available only on Cat. 2 with AES), otherwise
not remapped)
Other configurations: DMA channel 3 not remapped
Bits 7:4 C2S[3:0]: DMA channel 2 selection
0000: DMA channel 2 remapped to ADC
0001: DMA channel 2 remapped to SPI1_RX
0011: DMA channel 2 remapped to USART1_TX
0101: DMA channel 2 remapped to LPUART1_TX
0110: DMA channel 2 remapped to I2C1_TX
1000: DMA channel 2 remapped to TIM2_UP
1001: DMA channel 2 remapped to TIM6_UP/DAC channel 1
1011: DMA channel 2 remapped to AES_OUT (available only on Cat. 2 with AES), otherwise
not remapped)
Other configurations: DMA channel 2 not remapped
Bits 3:0 C1S[3:0]: DMA channel 1 selection
0000: DMA channel 1 remapped to ADC
1000: DMA channel 1 remapped to TIM2_CH3
1011: DMA channel 1 remapped to AES_IN (available only on Cat. 2 with AES°, otherwise
not remapped)
Other configurations: DMA channel 1 not remapped
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DMA_CNDTR4
0
0
0
DMA_CPAR3
DMA_CMAR3
0
0
Reset value
0
0
Reset value
DocID025941 Rev 1
TCIF1
GIF1
CTCIF7
CGIF7
CTEIF6
CHTIF6
CTCIF6
CGIF6
CTEIF5
CHTIF5
CTCIF5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MA[31:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
PL
[1:0]
PA[31:0]
MA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PL
[1:0]
0
0
0
0
0
0
0
0
PSIZE [1:0]
MSIZE [1:0]
CTEIF3
CHTIF3
CTCIF3
CGIF1
0
CTCIF1
0
CHTIF1
0
0
0
0
0
0
0
0
PINC
CIRC
DIR
TEIE
HTIE
TCIE
EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MINC
NDT[15:0]
0
0
0
EN
CHTIF7
0
CTEIF1
0
0
NDT[15:0]
EN
0
CGIF2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NDT[15:0]
EN
HTIF1
0
0
0
TCIE
0
0
0
HTIE
0
CTCIF2
0
0
TCIE
0
CHTIF2
0
0
HTIE
0
CTEIF2
0
TCIE
GIF2
TEIF1
0
0
0
TEIE
TCIF2
0
MINC
0
0
TEIE
HTIF2
0
0
0
DIR
GIF3
TEIF2
0
0
0
PINC
TCIF3
0
CGIF3
0
HTIE
0
0
TEIE
0
0
PL
[1:0]
DIR
Reset value
0
DIR
MA[31:0]
0
CIRC
HTIF3
0
0
0
PINC
GIF4
TEIF3
0
0
CIRC
TCIF4
0
0
MINC
PA[31:0]
0
PSIZE [1:0]
HTIF4
0
0
PINC
PA[31:0]
MINC
0
0
PL
[1:0]
PSIZE [1:0]
GIF5
TEIF4
0
0
MSIZE [1:0]
TCIF5
0
CGIF4
HTIF5
0
CTCIF4
GIF6
TEIF5
0
CHTIF4
TCIF6
0
MEM2MEM
HTIF6
0
0
MSIZE [1:0]
0
0
MEM2MEM
GIF7
TEIF6
0
CTEIF4
TCIF7
0
Res.
HTIF7
0
0
CIRC
Reset value
MEM2MEM
Reset value
Res.
0
Res.
TEIF7
Res.
Res.
Res.
Res.
0
CTEIF7
Res.
Res.
Res.
Res.
0
CGIF5
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
PSIZE [1:0]
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
MSIZE [1:0]
0
0
MEM2MEM
DMA_CMAR2
Res.
Reset value
Res.
DMA_CPAR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CMAR1
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CPAR1
Res.
0
0
0
Res.
0
0
Res.
0
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
0
Res.
0
0
0
0
Res.
0
0
0
Res.
0
0
0
0
Res.
0
0
0
0
Res.
0
0
0
Res.
0
0
0
Res.
0
0
0
0
0
Res.
DMA_CCR4
0
0
0
0
0
Res.
0x44
Reset value
0
0
0
0
Res.
0x3C
Reset value
Res.
Reset value
Res.
0x38
DMA_CNDTR3
Res.
Reset value
Res.
0x34
DMA_CCR3
0
0
0
Res.
0x30
Reset value
0
Res.
0x28
Reset value
0
0
Res.
0x24
DMA_CNDTR2
0
0
Res.
0x20
DMA_CCR2
0
Res.
0x1C
Reset value
Res.
0x14
Reset value
Res.
0x10
DMA_CNDTR1
Res.
0x0C
DMA_CCR1
Res.
0x08
DMA_IFCR
Res.
0x04
DMA_ISR
Res.
0x00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
11.4.8
Res.
Direct memory access controller (DMA)
RM0376
DMA register map
The following table gives the DMA register map and the reset values.
Table 43. DMA register map and reset values
0
0
0
0
0
0
0
NDT[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0376
Direct memory access controller (DMA)
0
0
0
0
0
0
0
0
0
0
0
0
DMA_CMAR4
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x08C
PINC
CIRC
DIR
TEIE
HTIE
TCIE
EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CIRC
DIR
TEIE
HTIE
TCIE
EN
PSIZE [1:0]
0
PINC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MEM2MEM
MINC
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_CMAR6
Reset value
0
Res.
Reset value
0
NDT[15:0]
0
DMA_CPAR6
PL
[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR6
0
0
MA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
CIRC
DIR
TEIE
HTIE
TCIE
EN
PSIZE [1:0]
0
PINC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_CMAR7
Reset value
0
NDT[15:0]
0
DMA_CPAR7
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR7
0
PL
[1:0]
MSIZE [1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CCR7
Res.
Reserved
0
0
MA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
Res.
Res.
DMA_CSELR
Res.
Reserved
Res.
0x090
0x0A8
PSIZE [1:0]
0
0
Reset value
0x088
0
0
Reset value
0x084
0
0
MSIZE [1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CCR6
0x07C
0x080
0
Reserved
Res.
0x078
0
MA[31:0]
Reset value
0x074
0
0
Reset value
0x070
0
MINC
0
0x068
0x06C
0
MEM2MEM
0
DMA_CMAR5
Reset value
0
NDT[15:0]
0
Res.
0x64
Reset value
0
PA[31:0]
Res.
0x60
0
Res.
Reset value
DMA_CPAR5
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR5
Res.
0x5C
0
Res.
Reset value
PL
[1:0]
MSIZE [1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CCR5
Res.
Reserved
Res.
0x54
0x58
0
MINC
0
Res.
PA[31:0]
0
MEM2MEM
Reset value
Res.
0x50
DMA_CPAR4
Res.
0x4C
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 43. DMA register map and reset values (continued)
C7S[3:0]
0
0
0
C6S[3:0]
0
0
0
0
C5S[3:0]
0
0
0
0
C4S[3:0]
0
0
C3S[3:0]
0
0
C2S[3:0]
0
0
C1S[3:0]
0
0
0
Refer to Section 2.2.2 for the register boundary addresses.
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Nested vectored interrupt controller (NVIC)
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12
Nested vectored interrupt controller (NVIC)
12.1
Main features
•
39 maskable interrupt channels (see Table 44), These do not include the 16 interrupt
lines of Cortex®-M0+.
•
16 programmable priority levels (4 bits of interrupt priority are used)
•
Low-latency exception and interrupt handling
•
Power management control
•
Implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low-latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to the PM0056 programming manual.
12.2
SysTick calibration value register
The SysTick calibration value is fixed to 4000, which gives a reference time base of 1 ms
with the SysTick clock set to 4 MHz (max HCLK/8).
12.3
Interrupt and exception vectors
Table 44 is the vector table for STM32L0x2 devices.
Table 44. Vector table(1)
Position
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Priority
Type of
priority
-
-
-3
Acronym
Description
Address
-
Reserved
0x0000_0000
fixed
Reset
Reset
0x0000_0004
-2
fixed
NMI_Handler
Non maskable interrupt. The RCC
Clock Security System (CSS) is
linked to the NMI vector.
0x0000_0008
-1
fixed
HardFault_Handler
All class of fault
0x0000_000C
0
settable
MemManage_Handler Memory management
0x0000_0010
1
settable
BusFault_Handler
Pre-fetch fault, memory access fault
0x0000_0014
2
settable
UsageFault_Handler
Undefined instruction or illegal state
0x0000_0018
-
-
-
Reserved
3
settable
SVC_Handler
System service call via SWI
instruction
0x0000_002C
4
settable
DebugMon_Handler
Debug Monitor
0x0000_0030
-
-
-
Reserved
0x0000_0034
DocID025941 Rev 1
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RM0376
Nested vectored interrupt controller (NVIC)
Table 44. Vector table(1) (continued)
Priority
Type of
priority
5
settable
6
0
Position
Acronym
Description
Address
PendSV_Handler
Pendable request for system service
0x0000_0038
settable
SysTick_Handler
System tick timer
0x0000_003C
7
settable
WWDG
Window Watchdog interrupt
0x0000_0040
1
8
settable
PVD
PVD through EXTI Line detection
interrupt
0x0000_0044
2
9
settable
RTC
RTC global interrupt through
EXTI17/19/20 line interrupts
0x0000_0048
3
10
settable
FLASH
Flash memory and data EEPROM
global interrupt
0x0000_004C
4
11
settable
RCC_CRS
RCC and CRS global interrupt
0x0000_0050
5
12
settable
EXTI[1:0]
EXTI Line0 and 1 interrupts
0x0000_0054
6
13
settable
EXTI[3:2]
EXTI Line2 and 3 interrupts
0x0000_0058
7
14
settable
EXTI[15:4]
EXTI Line4 to 15 interrupts
0x0000_005C
8
15
settable
TSC
Touch sense controller interrupt
0x0000_0060
9
16
settable
DMA1_Channel1
DMA1 Channel1 global interrupt
0x0000_0064
10
17
settable
DMA1_Channel[3:2]
DMA1 Channel2 and 3 interrupts
0x0000_0068
11
18
settable
DMA1_Channel[7:4]
DMA1 Channel4 to 7 interrupts
0x0000_006C
12
19
settable
ADC_COMP
ADC and comparator interrupts
through EXTI21 and 22
0x0000_0070
13
20
settable
LPTIM1
LPTIMER1 interrupt through EXTI29
0x0000_0074
14
21
settable
-
reserved
0x0000_0078
15
22
settable
TIM2
TIMER2 global interrupt
0x0000_007C
16
23
settable
-
reserved
0x0000_0080
17
24
settable
TIM6_DAC
TIMER6 global interrupt and DAC
interrupt
0x0000_0084
18
25
settable
-
reserved
0x0000_0088
19
26
settable
-
reserved
0x0000_008C
20
27
settable
TIM21
TIMER21 global interrupt
0x0000_0090
21
28
settable
-
reserved
0x0000_0094
22
29
settable
TIM22
TIMER22 global interrupt
0x0000_0098
23
30
settable
I2C1
I2C1 global interrupt through EXTI23
0x0000_009C
24
31
settable
I2C2
I2C2 global interrupt
0x0000_00A0
25
32
settable
SPI1
SPI1 global interrupt
0x0000_00A4
26
33
settable
SPI2
SPI2 global interrupt
0x0000_00A8
27
34
settable
USART1
USART1 global interrupt through
EXTI25
0x0000_00AC
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Table 44. Vector table(1) (continued)
Position
Priority
Type of
priority
28
35
settable
USART2
USART2 global interrupt through
EXTI26
0x0000_00B0
29
36
settable
LPUART1 + AES(2)
+RNG
LPUART1 global interrupt through
EXTI28 + AES global interrupt +
RNG global interrupt
0x0000_00B4
31
38
settable
USB
USB event interrupt through EXTI18
0x0000_00BC
Acronym
Description
®
1. The grayed cells correspond to the Cortex -M0+ interrupts.
2. Available only on Cat.2 with AES.
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RM0376
Extended interrupt and event controller (EXTI)
13
Extended interrupt and event controller (EXTI)
13.1
Introduction
The extended interrupts and events controller (EXTI) manages the external and internal
asynchronous events/interrupts and generates the event request to the CPU/interrupt
controller plus a wake-up request to the power controller.
The EXTI allows the management of up to 30 event lines which can wake up the device
from Stop mode.
Some of the lines are configurable: in this case the active edge can be chosen
independently, and a status flag indicates the source of the interrupt. The configurable lines
are used by the I/Os external interrupts, and by few peripherals. Some of the lines are
direct: they are used by some peripherals to generate a wakeup from Stop event or
interrupt. In this case the status flag is provided by the peripheral.
Each line can be masked independently for interrupt or event generation.
Te EXTI controller also allows to emulate, by programming to a dedicated register, events or
interrupts by software multiplexed with the corresponding hardware event line.
13.2
EXTI main features
The EXTI main features are the following:
•
13.3
Generation of up to 30 event/interrupt requests
–
22 configurable lines
–
6 direct lines
•
Independent mask on each event/interrupt line
•
Configurable rising or falling edge (configurable lines only)
•
Dedicated status bit (configurable lines only)
•
Emulation of event/interrupt requests (configurable lines only)
EXTI functional description
For the configurable interrupt lines, the interrupt line should be configured and enabled in
order to generate an interrupt. This is done by programming the two trigger registers with
the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the
corresponding bit in the interrupt mask register. When the selected edge occurs on the
interrupt line, an interrupt request is generated. The pending bit corresponding to the
interrupt line is also set. This request is cleared by writing a ‘1’ in the pending register.
For the direct interrupt lines: the interrupt is enabled by default in the interrupt mask register
and there is no corresponding pending bit in the pending register.
To generate an event, the event line should be configured and enabled. This is done by
programming the two trigger registers with the desired edge detection and by enabling the
event request by writing a ‘1’ to the corresponding bit in the event mask register. When the
selected edge occurs on the event line, an event pulse is generated. The pending bit
corresponding to the event line is not set.
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Extended interrupt and event controller (EXTI)
RM0376
For the configurable lines, an interrupt/event request can also be generated by software by
writing a ‘1’ in the software interrupt/event register.
Note:
The interrupts or events associated to the direct lines are triggered only when the system is
in Stop mode. If the system is still running, no interrupt/event is generated by the EXTI.
13.3.1
EXTI block diagram
The block diagram is shown in Figure 30.
Figure 30. Extended interrupts and events controller (EXTI) block diagram
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13.3.2
Wakeup event management
The STM32L0x2 microcontrollers are able to handle external or internal events in order to
wake up the core (WFE). The wakeup event can be generated by either:
13.3.3
•
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex®-M0+ system control register. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ
channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
•
or configuring an EXTI line in event mode. When the CPU resumes from WFE, it is not
necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel
pending bit as the pending bit corresponding to the event line is not set.
Peripherals asynchronous interrupts
Some peripherals can generate events when the system is in Run mode or in Stop mode,
thus allowing to wake up the system from Stop mode.
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Extended interrupt and event controller (EXTI)
To accomplish this, the peripheral generates both a synchronized (to the system clock, e.g.
APB clock) and an asynchronous version of the event. This asynchronous event is
connected to an EXTI direct line.
Note:
Few peripherals with wakeup from Stop capability are connected to an EXTI configurable
line. In this case the EXTI configuration is required to allow the wakeup from Stop mode.
13.3.4
Hardware interrupt selection
To configure a line as an interrupt source, use the following procedure:
1.
Configure the mask bits of the Interrupt lines (EXTI_IMR)
2.
Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and
EXTI_FTSR)
3.
Configure the enable and mask bits that control the NVIC IRQ channel mapped to the
extended interrupt controller (EXTI) so that an interrupt coming from any one of the
lines can be correctly acknowledged.
The direct lines do not require any EXTI configuration.
13.3.5
Hardware event selection
To configure a line as an event source, use the following procedure:
13.3.6
1.
Configure the mask bits of the Event lines (EXTI_EMR)
2.
Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR).
Software interrupt/event selection
Any of the configurable lines can be configured as software interrupt/event lines. The
procedure below must be followed to generate a software interrupt.
13.4
1.
Configure the mask bits of the Interrupt/Event lines (EXTI_IMR, EXTI_EMR)
2.
Set the required bit in the software interrupt register (EXTI_SWIER).
EXTI interrupt/event line mapping
In the STM32L0x2, 30 interrupt/event lines are available.The GPIOs are connected to 16
configurable interrupt/event lines as shown in Figure 31.
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Extended interrupt and event controller (EXTI)
RM0376
Figure 31. Extended interrupt/event GPIO mapping
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Note:
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Refer to the datasheet for the list of available I/O ports.
DocID025941 Rev 1
RM0376
Extended interrupt and event controller (EXTI)
The 30 lines are connected as shown in Table 45: EXTI lines connections:
Table 45. EXTI lines connections
EXTI line
Line source
Line type
0-15
GPIO
configurable
16
PVD
configurable
17
RTC alarm
configurable
18
USB wakeup event
direct
19
RTC tamper or timestamp or
CSS_LSE
configurable
20
RTC wakeup timer
configurable
21
COMP1 output
configurable
22
COMP2 output
configurable
23
I2C1 wakeup
direct
24
Reserved
25
USART 1 wakeup
direct
26
USART2 wakeup
direct
27
13.5
Reserved
28
LPUART1 wakeup
direct
29
LPTIM1 wakeup
direct
EXTI registers
Refer to Section 1.1 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).
13.5.1
EXTI interrupt mask register (EXTI_IMR)
Address offset: 0x00
Reset value: 0xFF84 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
IM29
IM28
Res.
IM26
IM25
Res.
IM23
IM22
IM21
IM20
IM19
IM18
IM17
IM16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IM15
IM14
IM13
IM12
IM11
IM10
IM9
IM8
IM7
IM6
IM5
IM4
IM3
IM2
IM1
IM0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
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RM0376
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:28 IMx: Interrupt mask on line x (x = 29 to 28)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
Bit 27 Reserved, must be kept at reset value.
Bits 26:25 IMx: Interrupt mask on line x (x = 26 to 25)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
Bit 24 Reserved, must be kept at reset value.
Bits 23:0 IMx: Interrupt mask on line x (x = 23 to 0)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
13.5.2
EXTI event mask register (EXTI_EMR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
EM29
EM28
Res.
EM26
EM25
Res.
EM23
EM22
EM21
EM20
EM19
EM18
EM17
EM16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EM15
EM14
EM13
EM12
EM11
EM10
EM9
EM8
EM7
EM6
EM5
EM4
EM3
EM2
EM1
EM0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:28 EMx: Event mask on line x (x = 29 to 28)
0: Event request from Line x is masked
1: Event request from Line x is not masked
Bit 27 Reserved, must be kept at reset value.
Bits 26:25 EMx: Event mask on line x (x = 26 to 25)
0: Event request from Line x is masked
1: Event request from Line x is not masked
Bit 24 Reserved, must be kept at reset value.
Bits 23:0 EMx: Event mask on line x (x = 23 to 0)
0: Event request from Line x is masked
1: Event request from Line x is not masked
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Extended interrupt and event controller (EXTI)
13.5.3
EXTI rising edge trigger selection register (EXTI_RTSR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RT22
RT21
RT20
RT19
Res.
RT17
RT16
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
RT16
2
1
0
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
RT0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:19 RTx: Rising trigger event configuration bit of line x (x = 22 to 19)
0: Rising trigger disabled (for Event and Interrupt) for input line x
1: Rising trigger enabled (for Event and Interrupt) for input line x
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 RTx: Rising trigger event configuration bit of line x (x = 17 to 0)
0: Rising trigger disabled (for Event and Interrupt) for input line x
1: Rising trigger enabled (for Event and Interrupt) for input line x
Note:
The configurable wakeup lines are edge triggered, no glitch must be generated on these
lines.
If a rising edge on the configurable interrupt line occurs while writing to the EXTI_RTSR
register, the pending bit will not be set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
13.5.4
Falling edge trigger selection register (EXTI_FTSR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FT22
FT21
FT20
FT19
Res.
FT17
FT16
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FT15
FT14
FT13
FT12
FT11
FT10
FT9
FT8
FT7
FT6
FT5
FT4
FT3
FT2
FT1
FT0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:23
Reserved, must be kept at reset value.
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Bits 22:19 FTx: Falling trigger event configuration bit of line x (x = 22 to 19)
0: Falling trigger disabled (for Event and Interrupt) for input line x
1: Falling trigger enabled (for Event and Interrupt) for input line x
Bit 18
Reserved, must be kept at reset value.
Bits 17:0 FTx: Falling trigger event configuration bit of line x (x = 17 to 0)
0: Falling trigger disabled (for Event and Interrupt) for input line x
1: Falling trigger enabled (for Event and Interrupt) for input line x
Note:
The configurable wakeup lines are edge triggered, no glitch must be generated on these
lines.
If a falling edge on the configurable interrupt line occurs while writing to the EXTI_FTSR
register, the pending bit will not be set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
13.5.5
EXTI software interrupt event register (EXTI_SWIER)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SWI22
SWI21
SWI20
SWI19
Res.
SWI17
SWI16
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SWI15
SWI14
SWI13
SWI12
SWI11
SWI10
SWI9
SWI8
SWI7
SWI6
SWI5
SWI4
SWI3
SWI2
SWI1
SWI0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:19 SWIx: Software interrupt on line x (x = 22 to 19)
Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the
interrupt is enabled on this line in EXTI_IMR and EXTI_EMR, an interrupt request is
generated.
This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to this bit).
Bit 18
Reserved, must be kept at reset value.
Bits 17:0 SWIx: Software interrupt on line x (x = 17 to 0)
Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the
interrupt is enabled on this line in EXTI_IMR and EXTI_EMR, an interrupt request is
generated.
This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to this bit).
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13.5.6
EXTI pending register (EXTI_PR)
Address offset: 0x14
Reset value: undefined
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PIF22
PIF21
PIF20
PIF19
Res.
PIF17
PIF16
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PIF15
PIF14
PIF13
PIF12
PIF11
PIF10
PIF9
PIF8
PIF7
PIF6
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:19 PIFx: Pending interrupt flag on line x (x = 22 to 19)
0: No trigger request occurred
1: The selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared
by writing it to 1 or by changing the sensitivity of the edge detector.
Bit 18
Reserved, must be kept at reset value.
Bits 17:0 PIFx: Pending interrupt flag on line x (x = 17 to 0)
0: No trigger request occurred
1: The selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared
by writing it to 1 or by changing the sensitivity of the edge detector.
13.5.7
EXTI register map
The following table gives the EXTI register map and the reset values.
Reset value
Res.
Res.
IM[26:25]
IM[23:0]
1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
EM[26:25]
EXTI_EMR
1 1
Res.
0x04
1 1
Res.
Res.
Reset value
IM[29:28]
EXTI_IMR
EM[29:28]
0x00
Register
Res.
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 46. Extended interrupt/event controller register map and reset values
EM[23:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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RM0376
0x14
0 0 0 0
EXTI_SWIER
SWI
[22:19]
Reset value
0 0 0 0
EXTI_PR
PIF
[22:19]
Reset value
0 0 0 0
Res.
RT[17:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
FT[22:19]
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x10
EXTI_FTSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x0C
0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
RT[22:19]
FT[17:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
EXTI_RTSR
SWI[17:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
0x08
Register
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 46. Extended interrupt/event controller register map and reset values (continued)
PIF[17:0]
0 0
0
0
0
Refer to Section 2.2.2 for the register boundary addresses.
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Analog-to-digital converter (ADC)
14
Analog-to-digital converter (ADC)
14.1
Introduction
The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19
multiplexed channels allowing it to measure signals from 16 external and 3 internal sources.
A/D conversion of the various channels can be performed in single, continuous, scan or
discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit
data register.
The analog watchdog feature allows the application to detect if the input voltage goes
outside the user-defined higher or lower thresholds.
An efficient low-power mode is implemented to allow very low consumption at low
frequency.
A built-in hardware oversampler allows to improve analog performances while off-loading
the related computational burden from the CPU.
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ADC main features
•
•
•
•
•
High performance
–
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
–
ADC conversion time: 0.87 µs for 12-bit resolution (1.14 MHz), 0.81 µs conversion
time for 10-bit resolution, faster conversion times can be obtained by lowering
resolution.
–
Self-calibration
–
Programmable sampling time
–
Data alignment with built-in data coherency
–
DMA support
low-power
–
Application can reduce PCLK frequency for low-power operation while still
keeping optimum ADC performance. For example, 1.0 µs conversion time is kept,
whatever the frequency of PCLK)
–
Wait mode: prevents ADC overrun in applications with low frequency PCLK
–
Auto off mode: ADC is automatically powered off except during the active
conversion phase. This dramatically reduces the power consumption of the ADC.
Analog input channels
–
16 external analog inputs
–
1 channel for internal temperature sensor (VSENSE)
–
1 channel for internal reference voltage (VREFINT)
Start-of-conversion can be initiated:
–
By software
–
By hardware triggers with configurable polarity (internal timer events from TIM2,
TIM6, TIM21, TIM22 or GPIO input events)
Conversion modes
–
Can convert a single channel or can scan a sequence of channels.
–
Single mode converts selected inputs once per trigger
–
Continuous mode converts selected inputs continuously
–
Discontinuous mode
•
Interrupt generation at the end of sampling, end of conversion, end of sequence
conversion, and in case of analog watchdog or overrun events
•
Analog watchdog
•
Oversampler
–
16-bit data register
–
Oversampling ratio adjustable from 2 to 256x
–
Programmable data shift up to 8-bits
•
ADC supply requirements: 1.8 to 3.6 V
•
ADC input range: VSSA ≤ VIN ≤ VDDA
Figure 32 shows the block diagram of the ADC.
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14.3
Analog-to-digital converter (ADC)
ADC pins and internal signals
Table 47. ADC internal signals
Internal signal
name
Signal type
Description
TRGx
Input
ADC conversion triggers
VSENSE
Input
Internal temperature sensor output voltage
VREFINT
Input
Internal voltage reference output voltage
Table 48. ADC pins
Name
Signal type
Remarks
VDDA
Input, analog power
supply
Analog power supply and positive reference voltage
for the ADC, VDDA ≥ VDD
VSSA
Input, analog supply
ground
Ground for analog power supply. Must be at VSS
potential
ADC_IN[15:0]
Analog input signals
16 analog input channels
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ADC functional description
Figure 32 shows the ADC block diagram and Table 48 gives the ADC pin description.
Figure 32. ADC block diagram
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14.4.1
ADC voltage regulator (ADVREGEN)
The ADC has a specific internal voltage regulator which must be enabled and stable before
using the ADC.
The ADC voltage regulator stabilization time is entirely managed by the hardware and
software does not need to care about it.
After ADC operations are complete, the ADC is disabled (ADEN=0). It is then possible to
save more power by disabling the ADC voltage regulator (refer to the ADC voltage regulator
disable sequence).
Note:
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When the internal voltage regulator is disabled, the internal analog calibration is kept.
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Analog-to-digital converter (ADC)
Analog reference for the ADC internal voltage regulator
The internal ADC voltage regulator uses a buffered copy of the VREFINT internal voltage
reference. This buffer is always enabled when the main voltage regulator is in normal Run
mode (MR mode, with the device operating either in Run or Sleep mode). When the main
voltage regulator is in Low-power run mode (LPR mode, with the device operating in Lowpower run, Low-power sleep or Stop mode), this buffer can be disabled and the software
must follow the procedure described below to use the ADC:
1.
Enter Low-power run mode (the ADC and the internal ADC voltage regulator must both
be disabled)
2.
Enable the VREFINT internal voltage reference by setting the EN_VREFINT bit in the
REF_CTRL register. The VREFINT_RDYF bit must be polled until the voltage
reference is ready.
3.
Enable the buffer by setting the ENBUF_EN_VREFINT_ADC bit in the REF_CTRL
register. The VREFINT_ADC_RDYF bit must be polled until the buffer is ready. The
buffer consumption is in the range of 8 µA.
4.
Enable the internal ADC voltage regulator by setting the ADVREGEN bit. The ADC is
then ready to be used.
ADVREG enable sequence
There are three ways to enable the voltage regulator:
•
by writing ADVREGEN=1.
•
by launching the calibration by writing by ADCAL=1 (the ADVREGEN bit will be
automatically set to 1)
•
by enabling the ADC by writing ADEN=1
ADVREG disable sequence
To disable the ADC voltage regulator, perform the sequence below:
14.4.2
1.
Ensure that the ADC is disabled (ADEN=0)
2.
Write ADVREGEN=0
Calibration (ADCAL)
The ADC has a calibration feature. During the procedure, the ADC calculates a calibration
factor which is internally applied to the ADC until the next ADC power-off. The application
must not use the ADC during calibration and must wait until it is complete.
Calibration should be performed before starting A/D conversion. It removes the offset error
which may vary from chip to chip due to process variation.
The calibration is initiated by software by setting bit ADCAL=1. Calibration can only be
initiated when the ADC is disabled (when ADEN=0). ADCAL bit stays at 1 during all the
calibration sequence. It is then cleared by hardware as soon the calibration completes. After
this, the calibration factor can be read from the ADC_DR register (from bits 6 to 0).
The internal analog calibration is kept if the ADC is disabled (ADEN=0) or if the ADC voltage
reference is disabled (ADVREGEN = 0). When the ADC operating conditions change (VDDA
changes are the main contributor to ADC offset variations and temperature change to a
lesser extend), it is recommended to re-run a calibration cycle.
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The calibration factor is lost in the following cases:
•
The product is in STANDBY mode (power supply removed from the ADC)
•
The ADC peripheral is reset.
The calibration factor is maintained in the following low-power modes: Low-power run, Lowpower sleep and STOP.
It is still possible to save and restore the calibration factor by software to save time when restarting the ADC (as long as temperature and voltage are stable during the ADC power
down).
The calibration factor can be written if the ADC is enabled but not converting (ADEN=1 and
ADSTART=0). Then, at the next start of conversion, the calibration factor is automatically
injected into the analog ADC. This loading is transparent and does not add any cycle
latency to the start of the conversion.
Calibration software procedure:
1.
Ensure that ADEN=0
2.
Set ADCAL=1
3.
Wait until ADCAL=0 (or until EOCAL=1). This can be handled by interrupt if the
interrupt is enabled by setting the EOCALIE bit in the ADC_IER register
4.
The calibration factor can be read from bits 6:0 of ADC_DR or ADC_CALFACT
registers.
Figure 33. ADC calibration
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If the ADC voltage regulator was not previously set, it will be automatically enabled when
setting ADCAL=1 (bit ADVREGEN is automatically set by hardware). In this case, the ADC
calibration time is longer to take into account the stabilization time of the ADC voltage
regulator.
At the end of the calibration, the ADC voltage regulator remains enabled.
Calibration factor forcing Software Procedure
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1.
Ensure that ADEN= 1 and ADSTART =0 (ADC started with no conversion on-going)
2.
Write ADC_CALFACT with the saved calibration factor
3.
The calibration factor will be used as soon as a new conversion will be launched.
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Analog-to-digital converter (ADC)
Figure 34. Calibration factor forcing
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14.4.3
ADC on-off control (ADEN, ADDIS, ADRDY)
At MCU power-up, the ADC is disabled and put in power-down mode (ADEN=0).
As shown in Figure 35, the ADC needs a stabilization time of tSTAB before it starts
converting accurately.
Two control bits are used to enable or disable the ADC:
•
Set ADEN=1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready
for operation.
•
Set ADDIS=1 to disable the ADC and put the ADC in power down mode. The ADEN
and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully
disabled.
If the ADC voltage regulator was not previously set, it will be automatically enabled when
setting ADEN=1 (bit ADVREGEN is automatically set by hardware). In this case, the ADC
stabilization time tSTAB is longer to take into account the stabilization time of the ADC
voltage regulator.
Conversion can then start either by setting SWSTART=1 (refer to Section 14.5: Conversion
on external trigger and trigger polarity (EXTSEL, EXTEN) on page 282) or when an external
trigger event occurs if triggers are enabled.
Follow this procedure to enable the ADC:
1.
Set ADEN=1 in the ADC_CR register.
2.
Wait until ADRDY=1 in the ADC_ISR register (ADRDY is set after the ADC startup
time). This can be handled by interrupt if the interrupt is enabled by setting the
ADRDYIE bit in the ADC_IER register.
Follow this procedure to disable the ADC:
1.
Check that ADSTART=0 in the ADC_CR register to ensure that no conversion is
ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the
the ADC_CR register and waiting until this bit is read at 0.
2.
Set ADDIS=1 in the ADC_CR register.
3.
If required by the application, wait until ADEN=0 in the ADC_CR register, indicating that
the ADC is fully disabled (ADDIS is automatically reset once ADEN=0).
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Figure 35. Enabling/disabling the ADC
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Note:
In auto-off mode (AUTOFF=1) the power-on/off phases are performed automatically, by
hardware and the ADRDY flag is not set.
14.4.4
ADC clock (CKMODE, PRESC[3:0], LFMEN)
The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock
(ADC asynchronous clock) independent from the APB clock (PCLK).
Figure 36. ADC clock scheme
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1. Refer to Section 7: Reset and clock control (RCC) on page 97 to see how PCLK and ADC asynchronous
clock are enabled.
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The input clock of the analog ADC can be selected between two different clock sources (see
Figure 36: ADC clock scheme to see how PCLK and the ADC asynchronous clock are
enabled):
a)
The ADC clock can be a specific clock source, named “ADC asynchronous clock
“which is independent and asynchronous with the APB clock.
Refer to RCC Section for more information on generating this clock source.
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
reset.
b)
The ADC clock can be derived from the APB clock of the ADC bus interface,
divided by a programmable factor (2 or 4) according to bits CKMODE[1:0].
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
different from “00”.
In option a), the generated ADC clock can eventually be divided by a prescaler (1, 2, 4, 6, 8,
12, 16, 32, 64, 128, 256) when programming the bits PRESC[3:0] in the ADC_CFGR2
register).
Option a) has the advantage of reaching the maximum ADC clock frequency whatever the
APB clock scheme selected.
Option b) has the advantage of bypassing the clock domain resynchronizations. This can be
useful when the ADC is triggered by a timer and if the application requires that the ADC is
precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is
added by the resynchronizations between the two clock domains).
Table 49. Latency between trigger and start of conversion
ADC clock source
Caution:
CKMODE[1:0]
Latency between the trigger event
and the start of conversion
HSI16 MHz clock
00
Latency is not deterministic (jitter)
PCLK divided by 2
01
Latency is deterministic (no jitter) and equal to
4.25 ADC clock cycles
PCLK divided by 4
10
Latency is deterministic (no jitter) and equal to
4.125 ADC clock cycles
PCLK divided by 1
11
Latency is deterministic (no jitter) and equal to
4.5 ADC clock cycles
When selecting CKMODE[1:0]=11 (PCLK divided by 1), the user must ensure that PCLK
has a 50% duty cycle. For this, inside the RCC, the user must select a system clock which
has a 50% duty cycle and must configure the APB prescaler inside the RCC in bypass
modes (refer to RCC section).
Low Frequency
When selecting an analog ADC clock frequency lower than 2.8MHz, it is mandatory to first
enable the Low Frequency Mode by setting bit LFMEN=1 into the ADC_CCR register
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14.4.5
RM0376
Configuring the ADC
Software must write to the ADCAL and ADEN bits in the ADC_CR register if the ADC is
disabled (ADEN must be 0).
Software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if
the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and
ADDIS = 0).
For all the other control bits in the ADC_IER, ADC_CFGRi, ADC_SMPR, ADC_TR,
ADC_CHSELR and ADC_CCR registers, software must only write to the configuration
control bits if the ADC is enabled (ADEN = 1) and if there is no conversion ongoing
(ADSTART = 0).
Software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled
(and possibly converting) and there is no pending request to disable the ADC (ADSTART =
1 and ADDIS = 0)
Note:
There is no hardware protection preventing software from making write operations forbidden
by the above rules. If such a forbidden write access occurs, the ADC may enter an
undefined state. To recover correct operation in this case, the ADC must be disabled (clear
ADEN=0 and all the bits in the ADC_CR register).
14.4.6
Channel selection (CHSEL, SCANDIR)
There are up to 19 multiplexed channels:
•
16 analog inputs from GPIO pins (ADC_IN0...ADC_IN15)
•
3 internal analog inputs (Temperature Sensor, Internal Reference Voltage )
It is possible to convert a single channel or to automatically scan a sequence of channels.
The sequence of the channels to be converted must be programmed in the ADC_CHSELR
channel selection register: each analog input channel has a dedicated selection bit
(CHSEL0...CHSEL18).
The order in which the channels will be scanned can be configured by programming the bit
SCANDIR bit in the ADC_CFGR1 register:
•
SCANDIR=0: forward scan Channel 0 to Channel 18
•
SCANDIR=1: backward scan Channel 18 to Channel 0
Temperature sensor, VREFINT internal channels
The temperature sensor is connected to channel ADC_IN18. The internal voltage reference
VREFINT is connected to channel ADC_IN17.
14.4.7
Programmable sampling time (SMP)
Before starting a conversion, the ADC needs to establish a direct connection between the
voltage source to be measured and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the sample and hold
capacitor to the input voltage level.
Having a programmable sampling time allows to trim the conversion speed according to the
input resistance of the input voltage source.
The ADC samples the input voltage for a number of ADC clock cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR register.
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This programmable sampling time is common to all channels. If required by the application,
the software can change and adapt this sampling time between each conversions.
The total conversion time is calculated as follows:
tCONV = Sampling time + 12.5 x ADC clock cycles
Example:
With ADC_CLK = 16 MHz and a sampling time of 1.5 ADC clock cycles:
tCONV = 1.5 + 12.5 = 14 ADC clock cycles = 0.875 µs
The ADC indicates the end of the sampling phase by setting the EOSMP flag.
14.4.8
Single conversion mode (CONT=0)
In Single conversion mode, the ADC performs a single sequence of conversions, converting
all the channels once. This mode is selected when CONT=0 in the ADC_CFGR1 register.
Conversion is started by either:
•
Setting the ADSTART bit in the ADC_CR register
•
Hardware trigger event
Inside the sequence, after each conversion is complete:
•
The converted data are stored in the 16-bit ADC_DR register
•
The EOC (end of conversion) flag is set
•
An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
•
The EOSEQ (end of sequence) flag is set
•
An interrupt is generated if the EOSEQIE bit is set
Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set
again.
Note:
To convert a single channel, program a sequence with a length of 1.
14.4.9
Continuous conversion mode (CONT=1)
In continuous conversion mode, when a software or hardware trigger event occurs, the ADC
performs a sequence of conversions, converting all the channels once and then
automatically re-starts and continuously performs the same sequence of conversions. This
mode is selected when CONT=1 in the ADC_CFGR1 register. Conversion is started by
either:
•
Setting the ADSTART bit in the ADC_CR register
•
Hardware trigger event
Inside the sequence, after each conversion is complete:
•
The converted data are stored in the 16-bit ADC_DR register
•
The EOC (end of conversion) flag is set
•
An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
•
The EOSEQ (end of sequence) flag is set
•
An interrupt is generated if the EOSEQIE bit is set
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Then, a new sequence restarts immediately and the ADC continuously repeats the
conversion sequence.
Note:
To convert a single channel, program a sequence with a length of 1.
It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN=1 and CONT=1.
14.4.10
Starting conversions (ADSTART)
Software starts ADC conversions by setting ADSTART=1.
When ADSTART is set, the conversion:
•
Starts immediately if EXTEN = 0x0 (software trigger)
•
At the next active edge of the selected hardware trigger if EXTEN ≠ 0x0
The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It
is possible to re-configure the ADC while ADSTART=0, indicating that the ADC is idle.
The ADSTART bit is cleared by hardware:
•
In single mode with software trigger (CONT=0, EXTSEL=0x0)
–
•
In all cases (CONT=x, EXTSEL=x)
–
Note:
At any end of conversion sequence (EOSEQ=1)
After execution of the ADSTP procedure invoked by software (see
Section 14.4.12: Stopping an ongoing conversion (ADSTP) on page 281)
In continuous mode (CONT=1), the ADSTART bit is not cleared by hardware when the
EOSEQ flag is set because the sequence is automatically relaunched.
When hardware trigger is selected in single mode (CONT=0 and EXTSEL ≠ 0x00),
ADSTART is not cleared by hardware when the EOSEQ flag is set. This avoids the need for
software having to set the ADSTART bit again and ensures the next trigger event is not
missed.
14.4.11
Timings
The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:
tADC = tSMPL + tSAR = [ 1.5 |min + 12.5 |12bit ] x tADC_CLK
tADC = tSMPL + tSAR = 93.8 ns |min + 781.3 ns |12bit = 0.875 µs |min (for fADC_CLK = 16 MHz)
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Figure 37. Analog to digital conversion time
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Figure 38. ADC conversion timings
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1. EXTEN =00 or EXTEN ≠ 00
2. Trigger latency (refer to datasheet for more details)
3. ADC_DR register write latency (refer to datasheet for more details)
14.4.12
Stopping an ongoing conversion (ADSTP)
The software can decide to stop any ongoing conversions by setting ADSTP=1 in the
ADC_CR register.
This will reset the ADC operation and the ADC will be idle, ready for a new operation.
When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is
discarded (ADC_DR register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that restarting the ADC would restart a new sequence).
Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by
hardware and the software must wait until ADSTART=0 before starting new conversions.
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Figure 39. Stopping an ongoing conversion
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14.5
Conversion on external trigger and trigger polarity (EXTSEL,
EXTEN)
A conversion or a sequence of conversion can be triggered either by software or by an
external event (for example timer capture). If the EXTEN[1:0] control bits are not equal to
“0b00”, then external events are able to trigger a conversion with the selected polarity. The
trigger selection is effective once software has set bit ADSTART=1.
Any hardware triggers which occur while a conversion is ongoing are ignored.
If bit ADSTART=0, any hardware triggers which occur are ignored.
Table 50 provides the correspondence between the EXTEN[1:0] values and the trigger
polarity.
Table 50. Configuring the trigger polarity
Source
Note:
EXTEN[1:0]
Trigger detection disabled
00
Detection on rising edge
01
Detection on falling edge
10
Detection on both rising and falling edges
11
The polarity of the external trigger can be changed only when the ADC is not converting
(ADSTART= 0).
The EXTSEL[2:0] control bits are used to select which of 8 possible events can trigger
conversions.
Table 51 gives the possible external trigger for regular conversion.
Software source trigger events can be generated by setting the ADSTART bit in the
ADC_CR register.
Table 51. External triggers
Name
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Source
EXTSEL[2:0]
TRG0
TIM6_TRGO
000
TRG1
TIM21_CH2
001
TRG2
TIM2_TRGO
010
TRG3
TIM2_CH4
011
TRG4
TIM22_TRGO
100
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Table 51. External triggers (continued)
Name
Source
EXTSEL[2:0]
TRG5
Reserved
101
TRG6
Reserved
110
TRG7
EXTI line 11
111
Note:
The trigger selection can be changed only when the ADC is not converting (ADSTART= 0).
14.5.1
Discontinuous mode (DISCEN)
This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register.
In this mode (DISCEN=1), a hardware or software trigger event is required to start each
conversion defined in the sequence. On the contrary, if DISCEN=0, a single hardware or
software trigger event successively starts all the conversions defined in the sequence.
Example:
•
•
DISCEN=1, channels to be converted = 0, 3, 7, 10
–
1st trigger: channel 0 is converted and an EOC event is generated
–
2nd trigger: channel 3 is converted and an EOC event is generated
–
3rd trigger: channel 7 is converted and an EOC event is generated
–
4th trigger: channel 10 is converted and both EOC and EOSEQ events are
generated.
–
5th trigger: channel 0 is converted an EOC event is generated
–
6th trigger: channel 3 is converted and an EOC event is generated
–
...
DISCEN=0, channels to be converted = 0, 3, 7, 10
–
1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10. Each
conversion generates an EOC event and the last one also generates an EOSEQ
event.
–
Any subsequent trigger events will restart the complete sequence.
Note:
It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN=1 and CONT=1.
14.5.2
Programmable resolution (RES) - fast conversion mode
It is possible to obtain faster conversion times (tSAR) by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the
RES[1:0] bits in the ADC_CFGR1 register. Lower resolution allows faster conversion times
for applications where high data precision is not required.
Note:
The RES[1:0] bit must only be changed when the ADEN bit is reset.
The result of the conversion is always 12 bits wide and any unused LSB bits are read as
zeroes.
Lower resolution reduces the conversion time needed for the successive approximation
steps as shown in Table 52.
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Table 52. tSAR timings depending on resolution
RES[1:0]
bits
14.5.3
tSAR
(ADC clock
cycles)
tSAR (ns) at
fADC = 16 MHz
tSMPL (min)
tADC
(ADC clock
cycles)
(ADC clock cycles)
(with min. tSMPL)
tADC (µs) at
fADC = 16 MHz
12
12.5
781 ns
1.5
14
875 ns
10
11.5
719 ns
1.5
13
812 ns
8
9.5
594 ns
1.5
11
688 ns
6
7.5
469 ns
1.5
9
562 ns
End of conversion, end of sampling phase (EOC, EOSMP flags)
The ADC indicates each end of conversion (EOC) event.
The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data
result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is
set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or
by reading the ADC_DR register.
The ADC also indicates the end of sampling phase by setting the EOSMP flag in the
ADC_ISR register. The EOSMP flag is cleared by software by writing1 to it. An interrupt can
be generated if the EOSMPIE bit is set in the ADC_IER register.
The aim of this interrupt is to allow the processing to be synchronized with the conversions.
Typically, an analog multiplexer can be accessed in hidden time during the conversion
phase, so that the multiplexer is positioned when the next sampling starts.
Note:
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As there is only a very short time left between the end of the sampling and the end of the
conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt
and a WFI instruction.
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14.5.4
End of conversion sequence (EOSEQ flag)
The ADC notifies the application of each end of sequence (EOSEQ) event.
The ADC sets the EOSEQ flag in the ADC_ISR register as soon as the last data result of a
conversion sequence is available in the ADC_DR register. An interrupt can be generated if
the EOSEQIE bit is set in the ADC_IER register. The EOSEQ flag is cleared by software by
writing 1 to it.
14.5.5
Example timing diagrams (single/continuous modes
hardware/software triggers)
Figure 40. Single conversions of a sequence, software trigger
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2. CHSEL=0x20601, WAIT=0, AUTOFF=0
Figure 41. Continuous conversion of a sequence, software trigger
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1. EXTEN=0x0, CONT=1,
2. CHSEL=0x20601, WAIT=0, AUTOFF=0
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Figure 42. Single conversions of a sequence, hardware trigger
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1. EXTSEL=TRGx (over-frequency), EXTEN=0x1 (rising edge), CONT=0
2. CHSEL=0xF, SCANDIR=0, WAIT=0, AUTOFF=0
Figure 43. Continuous conversions of a sequence, hardware trigger
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1. EXTSEL=TRGx, EXTEN=0x2 (falling edge), CONT=1
2. CHSEL=0xF, SCANDIR=0, WAIT=0, AUTOFF=0
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14.6
Data management
14.6.1
Data register and data alignment (ADC_DR, ALIGN)
At the end of each conversion (when an EOC event occurs), the result of the converted data
is stored in the ADC_DR data register which is 16-bit wide.
The format of the ADC_DR depends on the configured data alignment and resolution.
The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after
conversion. Data can be right-aligned (ALIGN=0) or left-aligned (ALIGN=1) as shown in
Figure 44.
Figure 44. Data alignment and resolution (oversampling disabled: OVSE = 0)
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14.6.2
ADC overrun (OVR, OVRMOD)
The overrun flag (OVR) indicates a data overrun event, when the converted data was not
read in time by the CPU or the DMA, before the data from a new conversion is available.
The OVR flag is set in the ADC_ISR register if the EOC flag is still at ‘1’ at the time when a
new conversion completes. An interrupt can be generated if the OVRIE bit is set in the
ADC_IER register.
When an overrun condition occurs, the ADC keeps operating and can continue to convert
unless the software decides to stop and reset the sequence by setting the ADSTP bit in the
ADC_CR register.
The OVR flag is cleared by software by writing 1 to it.
It is possible to configure if the data is preserved or overwritten when an overrun event
occurs by programming the OVRMOD bit in the ADC_CFGR1 register:
•
OVRMOD=0
–
•
An overrun event preserves the data register from being overwritten: the old data
is maintained and the new conversion is discarded. If OVR remains at 1, further
conversions can be performed but the resulting data is discarded.
OVRMOD=1
–
The data register is overwritten with the last conversion result and the previous
unread data is lost. If OVR remains at 1, further conversions can be performed
and the ADC_DR register always contains the data from the latest conversion.
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Figure 45. Example of overrun (OVR)
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14.6.3
Managing a sequence of data converted without using the DMA
If the conversions are slow enough, the conversion sequence can be handled by software.
In this case the software must use the EOC flag and its associated interrupt to handle each
data result. Each time a conversion is complete, the EOC bit is set in the ADC_ISR register
and the ADC_DR register can be read. The OVRMOD bit in the ADC_CFGR1 register
should be configured to 0 to manage overrun events as an error.
14.6.4
Managing converted data without using the DMA without overrun
It may be useful to let the ADC convert one or more channels without reading the data after
each conversion. In this case, the OVRMOD bit must be configured at 1 and the OVR flag
should be ignored by the software. When OVRMOD=1, an overrun event does not prevent
the ADC from continuing to convert and the ADC_DR register always contains the latest
conversion data.
14.6.5
Managing converted data using the DMA
Since all converted channel values are stored in a single data register, it is efficient to use
DMA when converting more than one channel. This avoids losing the conversion data
results stored in the ADC_DR register.
When DMA mode is enabled (DMAEN bit set to 1 in the ADC_CFGR1 register), a DMA
request is generated after the conversion of each channel. This allows the transfer of the
converted data from the ADC_DR register to the destination location selected by the
software.
Note:
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The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase.
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Analog-to-digital converter (ADC)
Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA
transfer request in time, the ADC stops generating DMA requests and the data
corresponding to the new conversion is not transferred by the DMA. Which means that all
the data transferred to the RAM can be considered as valid.
Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten
(refer to Section 14.6.2: ADC overrun (OVR, OVRMOD) on page 287).
The DMA transfer requests are blocked until the software clears the OVR bit.
Two different DMA modes are proposed depending on the application use and are
configured with bit DMACFG in the ADC_CFGR1 register:
•
DMA one shot mode (DMACFG=0).
This mode should be selected when the DMA is programmed to transfer a fixed
number of data words.
•
DMA circular mode (DMACFG=1)
This mode should be selected when programming the DMA in circular mode or double
buffer mode.
DMA one shot mode (DMACFG=0)
In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available and stops generating DMA requests once the DMA has reached the last
DMA transfer (when a DMA_EOT interrupt occurs, see Section 11: Direct memory access
controller (DMA) on page 238) even if a conversion has been started again.
When the DMA transfer is complete (all the transfers configured in the DMA controller have
been done):
•
The content of the ADC data register is frozen.
•
Any ongoing conversion is aborted and its partial result discarded
•
No new DMA request is issued to the DMA controller. This avoids generating an
overrun error if there are still conversions which are started.
•
The scan sequence is stopped and reset
•
The DMA is stopped
DMA circular mode (DMACFG=1)
In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available in the data register, even if the DMA has reached the last DMA transfer.
This allows the DMA to be configured in circular mode to handle a continuous analog input
data stream.
14.7
Low-power features
14.7.1
Wait mode conversion
Wait mode conversion can be used to simplify the software as well as optimizing the
performance of applications clocked at low frequency where there might be a risk of ADC
overrun occurring.
When the WAIT bit is set to 1 in the ADC_CFGR1 register, a new conversion can start only
if the previous data has been treated, once the ADC_DR register has been read or if the
EOC bit has been cleared.
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This is a way to automatically adapt the speed of the ADC to the speed of the system that
reads the data.
Note:
Any hardware triggers which occur while a conversion is ongoing or during the wait time
preceding the read access are ignored.
Figure 46. Wait mode conversion (continuous mode, software trigger)
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1. EXTEN=0x0, CONT=1
2. CHSEL=0x3, SCANDIR=0, WAIT=1, AUTOFF=0
14.7.2
Auto-off mode (AUTOFF)
The ADC has an automatic power management feature which is called auto-off mode, and
is enabled by setting AUTOFF=1 in the ADC_CFGR1 register.
When AUTOFF=1, the ADC is always powered off when not converting and automatically
wakes-up when a conversion is started (by software or hardware trigger). A startup-time is
automatically inserted between the trigger event which starts the conversion and the
sampling time of the ADC. The ADC is then automatically disabled once the sequence of
conversions is complete.
Auto-off mode can cause a dramatic reduction in the power consumption of applications
which need relatively few conversions or when conversion requests are timed far enough
apart (for example with a low frequency hardware trigger) to justify the extra power and
extra time used for switching the ADC on and off.
Auto-off mode can be combined with the wait mode conversion (WAIT=1) for applications
clocked at low frequency. This combination can provide significant power savings if the ADC
is automatically powered-off during the wait phase and restarted as soon as the ADC_DR
register is read by the application (see Figure 48: Behavior with WAIT=1, AUTOFF=1).
Note:
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Please refer to the Section 7: Reset and clock control (RCC) on page 97 for the description
of how to manage the dedicated 14 MHz internal oscillator. The ADC interface can
automatically switch ON/OFF the 14 MHz internal oscillator to save power.
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Figure 47. Behavior with WAIT=0, AUTOFF=1
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Figure 48. Behavior with WAIT=1, AUTOFF=1
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14.8
Analog window watchdog (AWDEN, AWDSGL, AWDCH,
AWD_HTR/LTR, AWD)
The AWD analog watchdog feature is enabled by setting the AWDEN bit in the
ADC_CFGR1 register. It is used to monitor that either one selected channel or all enabled
channels (see Table 54: Analog watchdog channel selection) remain within a configured
voltage range (window) as shown in Figure 49.
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can
be enabled by setting the AWDIE bit in the ADC_IER register.
The AWD flag is cleared by software by writing 1 to it.
When converting a data with a resolution of less than 12-bit (according to bits DRES[1:0]),
the LSB of the programmed thresholds must be kept cleared because the internal
comparison is always performed on the full 12-bit raw converted data (left aligned).
Table 53 describes how the comparison is performed for all the possible resolutions.
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Table 53. Analog watchdog comparison
Resolution
bits
RES[1:0]
Analog Watchdog comparison between:
Comments
Raw converted
data, left aligned(1)
Thresholds
00: 12-bit
DATA[11:0]
LT[11:0] and HT[11:0]
-
01: 10-bit
DATA[11:2],00
LT[11:0] and HT[11:0]
The user must configure LT1[1:0] and HT1[1:0] to “00”
10: 8-bit
DATA[11:4],0000
LT[11:0] and HT[11:0]
The user must configure LT1[3:0] and HT1[3:0] to
“0000”
11: 6-bit
DATA[11:6],000000
LT[11:0] and HT[11:0]
The user must configure LT1[5:0] and HT1[5:0] to
“000000”
1. The watchdog comparison is performed on the raw converted data before any alignment calculation.
Table 54 shows how to configure the AWDSGL and AWDEN bits in the ADC_CFGR1
register to enable the analog watchdog on one or more channels.
Figure 49. Analog watchdog guarded area
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Table 54. Analog watchdog channel selection
Channels guarded by the analog watchdog
AWDSGL bit
AWDEN bit
None
x
0
All channels
0
1
Single(1) channel
1
1
1. Selected by the AWDCH[4:0] bits
14.9
Oversampler
The oversampling unit performs data preprocessing to offload the CPU. It can handle
multiple conversions and average them into a single data with increased data width, up to
16-bit.
It provides a result with the following form, where N and M can be adjusted:
n = N–1
1
Result = ----- ×
M

Conversion ( t n )
n=0
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It allows to perform by hardware the following functions: averaging, data rate reduction,
SNR improvement, basic filtering.
The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register. It
can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits.
It is configured through the OVSS[3:0] bits in the ADC_CFGR2 register.
The summation unit can yield a result up to 20 bits (256 x 12-bit), which is first shifted right.
The upper bits of the result are then truncated, keeping only the 16 least significant bits
rounded to the nearest value using the least significant bits left apart by the shifting, before
being finally transferred into the ADC_DR data register.
Note:
If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are
simply truncated.
Figure 50. 20-bit to 16-bit result truncation
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The Figure 51 gives a numerical example of the processing, from a raw 20-bit accumulated
data to the final 16-bit result.
Figure 51. Numerical example with 5-bits shift and rounding
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The Table 55 below gives the data format for the various N and M combination, for a raw
conversion data equal to 0xFFF.
Table 55. Maximum output results vs N and M. Grayed values indicates truncation
No-shift
Oversa
Max
mpling
OVSS =
Raw data
ratio
0000
1-bit
shift
2-bit
shift
3-bit
shift
4-bit
shift
5-bit
shift
6-bit
shift
7-bit
shift
8-bit
shift
OVSS =
0001
OVSS =
0010
OVSS =
0011
OVSS =
0100
OVSS =
0101
OVSS =
0110
OVSS = OVSS =
0111
1000
2x
0x1FFE
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
0x0020
4x
0x3FFC
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
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Table 55. Maximum output results vs N and M. Grayed values indicates truncation (continued)
No-shift
Oversa
Max
mpling
OVSS =
Raw data
ratio
0000
1-bit
shift
2-bit
shift
3-bit
shift
4-bit
shift
5-bit
shift
6-bit
shift
7-bit
shift
8-bit
shift
OVSS =
0001
OVSS =
0010
OVSS =
0011
OVSS =
0100
OVSS =
0101
OVSS =
0110
OVSS = OVSS =
0111
1000
8x
0x7FF8
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
0x0100
0x0080
16x
0xFFF0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
0x0100
32x
0x1FFE0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
0x0200
64x
0x3FFC0
0xFFC0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
0x0400
128x
0x7FF80
0xFF80
0xFFC0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x0800
256x
0xFFF00
0xFF00
0xFF80
0xFFC0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
The conversion timings in oversampled mode do not change compared to standard
conversion mode: the sample time is maintained equal during the whole oversampling
sequence. New data are provided every N conversion, with an equivalent delay equal to N x
tADC = N x (tSMPL + tSAR). The flags features are raised as following:
14.9.1
•
the end of the sampling phase (EOSMP) is set after each sampling phase
•
the end of conversion (EOC) occurs once every N conversions, when the oversampled
result is available
•
the end of sequence (EOCSEQ) occurs once the sequence of oversampled data is
completed (i.e. after N x sequence length conversions total)
ADC operating modes support when oversampling
In oversampling mode, most of the ADC operating modes are available:
•
Single or continuous mode conversions, forward or backward scanned sequences
•
ADC conversions start either by software or with triggers
•
ADC stop during a conversion (abort)
•
Data read via CPU or DMA with overrun detection
•
Low-power modes (WAIT, AUTOFF)
•
Programmable resolution: in this case, the reduced conversion values (as per RES[1:0]
bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the
same way as 12-bit conversions are
Note:
The alignment mode is not available when working with oversampled data. The ALIGN bit in
ADC_CFGR1 is ignored and the data are always provided right-aligned.
14.9.2
Analog watchdog
The analog watchdog functionality is available (AWDSGL and AWDEN bits), with the
following difference:
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•
the RES[1:0] bits are ignored, comparison is always done on using the full 12-bits
values HT[11:0] and LT[11:0]
•
the comparison is performed on the most significant 12 bits of the 16 bits oversampled
results ADC_DR[15:4]
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Analog-to-digital converter (ADC)
Note:
Care must be taken when using high shifting values. This reduces the comparison range.
For instance, if the oversampled result is shifted by 4 bits thus yielding a 12-bit data rightaligned, the affective analog watchdog comparison can only be performed on 8 bits. The
comparison is done between ADC_DR[11:4] and HT[0:7] / LT[[0:7], and HT[11:8] / LT[11:8]
must be kept reset.
14.9.3
Triggered mode
The averager can also be used for basic filtering purposes. Although not a very efficient filter
(slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject
constant parasitic frequencies (typically coming from the mains or from a switched mode
power supply). For this purpose, a specific discontinuous mode can be enabled with TOVS
bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a user and
independent from the conversion time itself.
Figure 52 below shows how conversions are started in response to triggers in discontinuous
mode.
If the TOVS bit is set, the content of the DISCEN bit is ignored and considered as 1.
Figure 52. Triggered oversampling mode (TOVS bit = 1)
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14.10
RM0376
Temperature sensor and internal reference voltage
The temperature sensor can be used to measure the junction temperature (TJ) of the
device. The temperature sensor is internally connected to the ADC_IN18 input channel
which is used to convert the sensor’s output voltage to a digital value. The sampling time for
the temperature sensor’s analog pin must be greater than 2.2 µs.When not in use, the
sensor can be put in power down mode.
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. The
precise voltage of VREFINT is individually measured for each part by ST during production
test and stored in the system memory area. It is accessible in read-only mode.
Figure 53 shows the block diagram of connections between the temperature sensor, the
internal voltage reference and the ADC.
The TSEN bit must be set to enable the conversion of ADC_IN18 (temperature sensor) and
the VREFEN bit must be set to enable the conversion of ADC_IN17 (VREFINT).
The temperature sensor output voltage changes linearly with temperature. The offset of this
line varies from chip to chip due to process variation (up to 45 °C from one chip to another).
The uncalibrated internal temperature sensor is more suited for applications that detect
temperature variations instead of absolute temperatures. To improve the accuracy of the
temperature sensor measurement, calibration values are stored in system memory for each
device by ST during production.
During the manufacturing process, the calibration data of the temperature sensor and the
internal voltage reference are stored in the system memory area. The user application can
then read them and use them to improve the accuracy of the temperature sensor or the
internal reference. Refer to the datasheet for additional information.
Main features
•
Supported temperature range: –40 to 125 °C
•
Linearity: ±2 °C max., precision depending on calibration
Figure 53. Temperature sensor and VREFINT channel block diagram
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Analog-to-digital converter (ADC)
Reading the temperature
1.
Select the ADC_IN18 input channel
2.
Select an appropriate sampling time specified in the device datasheet (TS_temp)
3.
Set the TSEN bit in the ADC_CCR register to wake up the temperature sensor from
power down mode and wait for its stabilization time (tSTART)
4.
Start the ADC conversion by setting the ADSTART bit in the ADC_CR register (or by
external trigger)
5.
Read the resulting VSENSE data in the ADC_DR register
6.
Calculate the temperature using the following formula:
130 °C – 30 °C
Temperature ( in °C ) = ---------------------------------------------------------- × ( TS_DATA – TS_CAL1 ) + 30 °C
TS_CAL2 – TS_CAL1
Where:
•
TS_CAL2 is the temperature sensor calibration value acquired at 130°C
•
TS_CAL1 is the temperature sensor calibration value acquired at 30°C
•
TS_DATA is the actual temperature sensor output value converted by ADC
Refer to the specific device datasheet for more information about TS_CAL1 and
TS_CAL2 calibration points.
A.7.16: Temperature computation code example.
Note:
The sensor has a startup time after waking from power down mode before it can output
VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize
the delay, the ADEN and TSEN bits should be set at the same time.
Calculating the actual VDDA voltage using the internal reference voltage
The VDDA power supply voltage applied to the microcontroller may be subject to variation or
not precisely known. The embedded internal voltage reference (VREFINT) and its
calibration data acquired by the ADC during the manufacturing process at VDDA = 3.3 V can
be used to evaluate the actual VDDA voltage level.
The following formula gives the actual VDDA voltage supplying the device:
VDDA = 3.3 V x VREFINT_CAL / VREFINT_DATA
Where:
•
VREFINT_CAL is the VREFINT calibration value
•
VREFINT_DATA is the actual VREFINT output value converted by ADC
Converting a supply-relative ADC measurement to an absolute voltage value
The ADC is designed to deliver a digital value corresponding to the ratio between the analog
power supply and the voltage applied on the converted channel. For most application use
cases, it is necessary to convert this ratio into a voltage independent of VDDA. For
applications where VDDA is known and ADC converted values are right-aligned you can use
the following formula to get this absolute value:
V DDA
V CHANNELx = ------------------------------------- × ADC_DATA x
FULL_SCALE
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RM0376
For applications where VDDA value is not known, you must use the internal voltage
reference and VDDA can be replaced by the expression provided in the section Calculating
the actual VDDA voltage using the internal reference voltage, resulting in the following
formula:
3.3 V × VREFINT_CAL × ADC_DATA x
V CHANNELx = ----------------------------------------------------------------------------------------------------VREFINT_DATA × FULL_SCALE
Where:
•
VREFINT_CAL is the VREFINT calibration value
•
ADC_DATAx is the value measured by the ADC on channel x (right-aligned)
•
VREFINT_DATA is the actual VREFINT output value converted by the ADC
•
FULL_SCALE is the maximum digital value of the ADC output. For example with 12-bit
resolution, it will be 212 - 1 = 4095 or with 8-bit resolution, 28 - 1 = 255.
Note:
If ADC measurements are done using an output format other than 12 bit right-aligned, all the
parameters must first be converted to a compatible format before the calculation is done.
14.11
ADC interrupts
An interrupt can be generated by any of the following events:
•
End Of Calibration (EOCAL flag)
•
ADC power-up, when the ADC is ready (ADRDY flag)
•
End of any conversion (EOC flag)
•
End of a sequence of conversions (EOSEQ flag)
•
When an analog watchdog detection occurs (AWD flag)
•
When the end of sampling phase occurs (EOSMP flag)
•
when a data overrun occurs (OVR flag)
Separate interrupt enable bits are available for flexibility.
Table 56. ADC interrupts
Interrupt event
Event flag
Enable control bit
End Of Calibration
EOCAL
EOCALIE
ADC ready
ADRDY
ADRDYIE
EOC
EOCIE
End of sequence of conversions
EOSEQ
EOSEQIE
Analog watchdog status bit is set
AWD
AWDIE
EOSMP
EOSMPIE
OVR
OVRIE
End of conversion
End of sampling phase
Overrun
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14.12
ADC registers
Refer to Section 1.1 on page 43 for a list of abbreviations used in register descriptions.
14.12.1
ADC interrupt and status register (ADC_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
EOCAL
Res.
Res.
Res.
AWD
Res.
Res.
OVR
EOSEQ
EOC
r_w1
r_w1
rc_w1
r_w1
r_w1
EOSMP ADRDY
r_w1
r_w1
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 EOCAL: End Of Calibration flag
This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
0: Calibration is not complete
1: Calibration is complete
Bit 10:8 Reserved, must be kept at reset value.
Bit 7 AWD: Analog watchdog flag
This bit is set by hardware when the converted voltage crosses the values programmed in the
ADC_LTR and ADC_HTR registers. It is cleared by software writing 1 to it.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
Bit 6:5 Reserved, must be kept at reset value.
Bit 4 OVR: ADC overrun
This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete
while the EOC flag was already set. It is cleared by software writing 1 to it.
0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
1: Overrun has occurred
Bit 3 EOSEQ: End of sequence flag
This bit is set by hardware at the end of the conversion of a sequence of channels selected by the
CHSEL bits. It is cleared by software writing 1 to it.
0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by
software)
1: Conversion sequence complete
Bit 2 EOC: End of conversion flag
This bit is set by hardware at the end of each conversion of a channel when a new data result is
available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR
register.
0: Channel conversion not complete (or the flag event was already acknowledged and cleared by
software)
1: Channel conversion complete
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Bit 1 EOSMP: End of sampling flag
This bit is set by hardware during the conversion, at the end of the sampling phase.
0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by
software)
1: End of sampling phase reached
Bit 0 ADRDY: ADC ready
This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC reaches
a state where it is ready to accept conversion requests.
It is cleared by software writing 1 to it.
0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared
by software)
1: ADC is ready to start conversion
14.12.2
ADC interrupt enable register (ADC_IER)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
EOCAL
IE
Res.
Res.
Res.
AWDIE
Res.
Res.
OVRIE
rw
rw
rw
EOSEQ
EOSMP ADRDY
EOCIE
IE
IE
IE
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 EOCALIE: End of calibration interrupt enable
This bit is set and cleared by software to enable/disable the end of calibration interrupt.
0: End of calibration interrupt disabled
1: End of calibration interrupt enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 10:8 Reserved, must be kept at reset value.
Bit 7 AWDIE: Analog watchdog interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 6:5 Reserved, must be kept at reset value.
Bit 4 OVRIE: Overrun interrupt enable
This bit is set and cleared by software to enable/disable the overrun interrupt.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
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Bit 3 EOSEQIE: End of conversion sequence interrupt enable
This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt.
0: EOSEQ interrupt disabled
1: EOSEQ interrupt enabled. An interrupt is generated when the EOSEQ bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 2 EOCIE: End of conversion interrupt enable
This bit is set and cleared by software to enable/disable the end of conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 1 EOSMPIE: End of sampling flag interrupt enable
This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt.
0: EOSMP interrupt disabled.
1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bits 0 ADRDYIE: ADC ready interrupt enable
This bit is set and cleared by software to enable/disable the ADC Ready interrupt.
0: ADRDY interrupt disabled.
1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
14.12.3
ADC control register (ADC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31
ADCAL
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
ADVR
EGEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
ADSTA
RT
ADDIS
ADEN
rs
rs
rs
rs
15
Res.
rw
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADSTP
rs
Bit 31 ADCAL: ADC calibration
This bit is set by software to start the calibration of the ADC.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.
Note: Software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0,
ADSTP=0, ADDIS=0 and ADEN=0).
Note: Software is allowed to update the calibration factor by writing ADC_CALFACT only when
ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
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Bits 30:29
RM0376
Reserved, must be kept at reset value.
Bits 28 ADVREGEN: ADC Voltage Regulator Enable
This bit is set:
- by software to enable the ADC internal voltage regulator.
- by hardware when launching the calibration (setting ADCAL=1) or when enabling the ADC (setting
ADEN=1)
It is cleared by software to disable the voltage regulator (it can be cleared only if ADEN=0).
0: ADC voltage regulator disabled
1: ADC voltage regulator enabled
Note: The software can program this bit field only when the ADC is disabled (ADCAL=0,
ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bits 27:5
Reserved, must be kept at reset value.
Bit 4 ADSTP: ADC stop conversion command
This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept
a new start conversion command.
0: No ADC stop conversion command ongoing
1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.
Note: Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is enabled and
may be converting and there is no pending request to disable the ADC)
Bit 3
Reserved, must be kept at reset value.
Bit 2 ADSTART: ADC start conversion command
This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a
conversion either starts immediately (software trigger configuration) or once a hardware trigger event
occurs (hardware trigger configuration).
It is cleared by hardware:
– In single conversion mode when software trigger is selected (EXTSEL=0x0): at the assertion of the
End of Conversion Sequence (EOSEQ) flag.
– In all cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is
cleared by hardware.
0: No ADC conversion is ongoing.
1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.
Note: Software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and
there is no pending request to disable the ADC)
Bit 1 ADDIS: ADC disable command
This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state
(OFF state).
It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at
this time).
0: No ADDIS command ongoing
1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
Note: Software is allowed to set ADDIS only when ADEN=1 and ADSTART=0 (which ensures that no
conversion is ongoing)
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Bit 0 ADEN: ADC enable command
This bit is set by software to enable the ADC. The ADC will be effectively ready to operate once the
ADRDY flag has been set.
It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.
0: ADC is disabled (OFF state)
1: Write 1 to enable the ADC.
Note: Software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0,
ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
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14.12.4
RM0376
ADC configuration register 1 (ADC_CFGR1)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
Res.
28
27
26
AWDCH[4:0]
15
rw
rw
rw
rw
rw
14
13
12
11
10
AUTOFF WAIT CONT OVRMOD
rw
rw
rw
rw
EXTEN[1:0]
25
24
Res.
Res.
9
8
Res.
rw
23
22
AWDEN AWDSGL
rw
rw
7
6
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
DISCEN
5
4
3
2
1
rw
EXTSEL[2:0]
ALIGN
RES[1:0]
rw
rw
rw
SCAND DMAC
IR
FG
rw
rw
0
DMAEN
rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:26 AWDCH[4:0]: Analog watchdog channel selection
These bits are set and cleared by software. They select the input channel to be guarded by the analog
watchdog.
00000: ADC analog input Channel 0 monitored by AWD
00001: ADC analog input Channel 1 monitored by AWD
.....
10011: ADC analog input Channel 18 monitored by AWD
other values: Reserved, must not be used
Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 25:24
Reserved, must be kept at reset value.
Bit 23 AWDEN: Analog watchdog enable
This bit is set and cleared by software.
0: Analog watchdog disabled
1: Analog watchdog enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 22 AWDSGL: Enable the watchdog on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the channel identified by the
AWDCH[4:0] bits or on all the channels
0: Analog watchdog enabled on all channels
1: Analog watchdog enabled on a single channel
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bits 21:17 Reserved, must be kept at reset value.
Bit 16 DISCEN: Discontinuous mode
This bit is set and cleared by software to enable/disable discontinuous mode.
0: Discontinuous mode disabled
1: Discontinuous mode enabled
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden
to set both bits DISCEN=1 and CONT=1.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
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Bit 15 AUTOFF: Auto-off mode
This bit is set and cleared by software to enable/disable auto-off mode..
0: Auto-off mode disabled
1: Auto-off mode enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 14 WAIT: Wait conversion mode
This bit is set and cleared by software to enable/disable wait conversion mode..
0: Wait conversion mode off
1: Wait conversion mode on
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 13 CONT: Single / continuous conversion mode
This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared.
0: Single conversion mode
1: Continuous conversion mode
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden
to set both bits DISCEN=1 and CONT=1.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 12 OVRMOD: Overrun management mode
This bit is set and cleared by software and configure the way data overruns are managed.
0: ADC_DR register is preserved with the old data when an overrun is detected.
1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection
These bits are set and cleared by software to select the external trigger polarity and enable the trigger.
00: Hardware trigger detection disabled (conversions can be started by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 9 Reserved, must be kept at reset value.
Bits 8:6 EXTSEL[2:0]: External trigger selection
These bits select the external event used to trigger the start of conversion (refer to Table 51: External
triggers for details):
000: TRG0
001: TRG1
010: TRG2
011: TRG3
100: TRG4
101: TRG5
110: TRG6
111: TRG7
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
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Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to Figure 44: Data
alignment and resolution (oversampling disabled: OVSE = 0) on page 287
0: Right alignment
1: Left alignment
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12 bits
01: 10 bits
10: 8 bits
11: 6 bits
Note: Software is allowed to write these bits only when ADEN=0.
Bit 2 SCANDIR: Scan sequence direction
This bit is set and cleared by software to select the direction in which the channels will be scanned in
the sequence.
0: Upward scan (from CHSEL0 to CHSEL18)
1: Backward scan (from CHSEL18 to CHSEL0)
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 1 DMACFG: Direct memory access configuration
This bit is set and cleared by software to select between two DMA modes of operation and is effective
only when DMAEN=1.
0: DMA one shot mode selected
1: DMA circular mode selected
For more details, refer to Section 14.6.5: Managing converted data using the DMA on page 288
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 0 DMAEN: Direct memory access enable
This bit is set and cleared by software to enable the generation of DMA requests. This allows to use
the DMA controller to manage automatically the converted data. For more details, refer to
Section 14.6.5: Managing converted data using the DMA on page 288.
0: DMA disabled
1: DMA enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
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14.12.5
ADC configuration register 2 (ADC_CFGR2)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
CKMODE[1:0]
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
8
7
6
5
4
3
2
1
0
Res.
OVSE
rw
rw
15
14
13
12
11
10
9
Res.
Res.
Res.
Res.
Res.
Res.
TOVS
rw
OVSS[3:0]
rw
rw
rw
OVSR[2:0]
rw
rw
rw
rw
rw
Bits 31:30 CKMODE[1:0]: ADC clock mode
These bits are set and cleared by software to define how the analog ADC is clocked:
00: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)
01: PCLK/2 (Synchronous clock mode)
10: PCLK/4 (Synchronous clock mode)
11: PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50%
duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
must by 50% duty cycle)
In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a
conversion.
Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0,
ADSTP=0, ADDIS=0 and ADEN=0).
Bits 29:10
Reserved, must be kept at reset value.
Bits 9 TOVS: Triggered Oversampling
This bit is set and cleared by software.
0: All oversampled conversions for a channel are done consecutively after a trigger
1: Each oversampled conversion for a channel needs a trigger
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bits 8:5 OVSS[3:0]: Oversampling shift
This bit is set and cleared by software.
0000: No shift
0001: Shift 1-bit
0010: Shift 2-bits
0011: Shift 3-bits
0100: Shift 4-bits
0101: Shift 5-bits
0110: Shift 6-bits
0111: Shift 7-bits
1000: Shift 8-bits
Other codes reserved
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
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Bits 4:2 OVSR[2:0]: Oversampling ratio
This bit filed defines the number of oversampling ratio.
000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101: 64x
110: 128x
111: 256x
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 1
Reserved, must be kept at reset value.
Bit 0 OVSE: Oversampler Enable
This bit is set and cleared by software.
0: Oversampler disabled
1: Oversampler enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
14.12.6
ADC sampling time register (ADC_SMPR)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SMP[2:0]
rw
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 SMP[2:0]: Sampling time selection
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 7.5 ADC clock cycles
010: 13.5 ADC clock cycles
011: 28.5 ADC clock cycles
100: 41.5 ADC clock cycles
101: 55.5 ADC clock cycles
110: 71.5 ADC clock cycles
111: 239.5 ADC clock cycles
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
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14.12.7
ADC watchdog threshold register (ADC_TR)
Address offset: 0x20
Reset value: 0x0FFF 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
27
25
24
23
22
21
20
19
18
17
16
HT[11:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
LT[11:0]
rw
Bits 31:28
26
rw
rw
rw
rw
rw
Reserved, must be kept at reset value.
Bit 27:16 HT[11:0]: Analog watchdog higher threshold
These bits are written by software to define the higher threshold for the analog watchdog. Refer to
Section 14.8: Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR, AWD) on
page 291
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 15:12
Reserved, must be kept at reset value.
Bit 11:0 LT[11:0]: Analog watchdog lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 14.8: Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR,
AWD) on page 291
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
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14.12.8
RM0376
ADC channel selection register (ADC_CHSELR)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
18
17
16
CHSEL CHSEL CHSEL
18
17
16
rw
rw
rw
2
1
0
CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:0 CHSELx: Channel-x selection
These bits are written by software and define which channels are part of the sequence of channels to
be converted.
0: Input Channel-x is not selected for conversion
1: Input Channel-x is selected for conversion
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
14.12.9
ADC data register (ADC_DR)
Address offset: 0x40
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
DATA[15:0]
r
r
r
r
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: Converted data
These bits are read-only. They contain the conversion result from the last converted channel. The data
are left- or right-aligned as shown in Figure 44: Data alignment and resolution (oversampling disabled:
OVSE = 0) on page 287.
Just after a calibration is complete, DATA[6:0] contains the calibration factor.
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14.12.10 ADC Calibration factor (ADC_CALFACT)
Address offset: 0xB4
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
CALFACT[6:0]
rw
rw
rw
rw
Bits 31:7 Reserved, must be kept at reset value.
Bits 6:0 CALFACT[6:0]: Calibration factor
These bits are written by hardware or by software.
– Once a single-ended inputs calibration is complete, they are updated by hardware with the
calibration factors.
– Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it will then be applied once a new single-ended
calibration is launched.
– Just after a calibration is complete, DATA[6:0] contains the calibration factor.
Note: Software is allowed to write these bits only when ADEN=1 and ADSTART=0 (ADC is enabled
and no calibration is ongoing and no conversion is ongoing).
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14.12.11 ADC common configuration register (ADC_CCR)
Address offset: 0x308
Reset value: 0x0000 0000
31
30
29
28
27
26
25
LFMEN
24
23
22
Res.
TS
EN
VREF
EN
21
20
19
18
PRESC[3:0]
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 25 LFMEN: Low Frequency Mode enable
This bit is set and cleared by software to enable/disable the Low Frequency Mode.
It is mandatory to enable this mode the user selects an ADC clock frequency lower than 2.8MHz
0: Low Frequency Mode disabled
1: Low Frequency Mode enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 24 Reserved, must be kept at reset value.
Bit 23 TSEN: Temperature sensor enable
This bit is set and cleared by software to enable/disable the temperature sensor.
0: Temperature sensor disabled
1: Temperature sensor enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 22 VREFEN: VREFINT enable
This bit is set and cleared by software to enable/disable the VREFINT.
0: VREFINT disabled
1: VREFINT enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
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Bits 21:18 PRESC[3:0]: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADC. The clock is common for
all the ADCs.
0000: input ADC clock not divided
0001: input ADC clock divided by 2
0010: input ADC clock divided by 4
0011: input ADC clock divided by 6
0100: input ADC clock divided by 8
0101: input ADC clock divided by 10
0110: input ADC clock divided by 12
0111: input ADC clock divided by 16
1000: input ADC clock divided by 32
1001: input ADC clock divided by 64
1010: input ADC clock divided by 128
1011: input ADC clock divided by 256
other: reserved
Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0,
ADSTP=0, ADDIS=0 and ADEN=0).
Bits 17:0 Reserved, must be kept at reset value.
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0xB4
0xB8
...
0x304
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Reserved
Reserved
Reset value
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1
1
CHSEL18
CHSEL17
CHSEL16
CHSEL15
CHSEL14
CHSEL13
Reset value
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHSEL8
CHSEL7
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TOVS
Res.
0
0
0
0
0
0
0
0
0
Reserved
DATA[15:0]
0
0
0
CHSEL0
0
CHSEL9
Res.
0
CHSEL1
0
CHSEL10
Res.
EXTEN[1:0]
OVRMOD
0
Res.
Res.
WAIT
AUTOFF
CONT
DISCEN
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
CHSEL2
0
CHSEL11
1
Reserved
CHSEL12
Res.
Res.
Res.
Reserved
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTSEL
[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ALIGN
0
0
0
OVSS
[3:0]
0
0
OVSR
[2:0]
0
DMAEN
RES
[1:0]
0
0
0
OVSE
ADRDYIE
0
0
0
ADEN
EOCIE
EOSMPIE
0
ADDIS
0
ADSTART
0
DMACFG
0
SCANDIR
OVR
EOC
EOSMP
ADRDY
Res.
AWD
Res.
Res.
Res.
Res.
EOCAL.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EOSEQ
0
Res.
OVRIE
Res.
AWDIE
Res.
Res.
Res.
EOCALIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EOSEQIE
0
ADSTP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
CHSEL3
0
Res.
1
Res.
Res.
Res.
AWDSGL
Res.
Res.
Res.
Res.
Reset value
CHSEL4
0
Res.
1
Res.
Res.
Res.
AWDEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
CHSEL5
0
Res.
1
Res.
Res.
Res.
Res.
Res.
Res.
ADVREGEN
Res.
Res.
ADCAL
Res.
Reset value
CHSEL6
0
Res.
Reserved
0
Res.
0
Res.
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Reserved
0
Res.
1
Res.
HT[11:0]
Res.
1
Res.
Reset value
Reserved
Reserved
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Reset value
1
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CKMODE[1:0]
0
Res.
Res.
ADC_DR
AWDCH[4:0]
Res.
0x44
...
0xB0
Reset value
Reserved
0
Res.
0x40
ADC_CHSELR
0
Res.
0x2C
0x30
0x34
0x38
0x3C
0
0
Res.
0x28
0
Res.
0x24
ADC_TR
0
Res.
0x20
0
Res.
Reset value
Res.
0x18
0x1C
Reset value
ADC_SMPR
Res.
0x14
ADC_CFGR2
Res.
0x10
ADC_CFGR1
Res.
Reset value
Res.
0x0C
ADC_CR
Res.
0x08
ADC_IER
Res.
0x04
ADC_ISR
Res.
0x00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
Analog-to-digital converter (ADC)
RM0376
14.12.12 ADC register map
The following table summarizes the ADC registers.
Table 57. ADC register map and reset values
0
0
0
0
0
0
0
0
0
0
SMP
[2:0]
0 0 0
LT[11:0]
CALFACT[6:0]
0
0
0
RM0376
Analog-to-digital converter (ADC)
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
PRESC[3:0]
VREFEN
Res.
Res.
Res.
LFMEN
0
TSEN
Reset value
Res.
ADC_CCR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x308
Register
Res.
Offset
Res.
Table 57. ADC register map and reset values (continued)
0
Refer to Section 2.2.2 for the register boundary addresses.
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15
Digital-to-analog converter (DAC)
15.1
Introduction
The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In
12-bit mode, the data could be left- or right-aligned. An input reference voltage, VREF+
(shared with ADC), is available. The output can optionally be buffered for higher current
drive.
15.2
DAC1 main features
The devices integrate one 12-bit DAC channel DAC_OUT1.
DAC1 main features are the following:
•
One data holding register
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation
•
Triangular-wave generation
•
DMA capability (including underrun detection
•
External triggers for conversion
•
Input voltage reference, VDDA
Figure 54 shows the block diagram of a DAC channel and Table 58 gives the pin
description.
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Figure 54. DAC block diagram
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Table 58. DAC pins
Name
Note:
Signal type
Remarks
VDDA
Input, analog supply
Analog power supply
VSSA
Input, analog supply ground
Ground for analog power supply
VREF+
Input, analog positive
reference
The higher/positive reference voltage for the DAC1
DAC_OUT1
Analog output signal
DAC channelx analog output
Once DAC_Channelx is enabled, the corresponding GPIO pin (PA4) is automatically
connected to the analog converter output (DAC_OUT1). In order to avoid parasitic
consumption, the PA4 pin should first be configured to analog (AIN).
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15.3
Single mode functional description
15.3.1
DAC channel enable
The DAC channel can be powered on by setting the EN1 bit in the DAC_CR register. The
DAC channel is then enabled after a startup time tWAKEUP.
Note:
The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital
interface is enabled even if the ENx bit is reset.
15.3.2
DAC output buffer enable
The DAC integrates an output buffer that can be used to reduce the output impedance, and
to drive external loads directly without having to add an external operational amplifier. The
DAC channel output buffer can be enabled and disabled using the BOFF1 bit in the
DAC_CR register.
15.3.3
DAC data format
Depending on the selected configuration mode, the data have to be written into the specified
register as described below:
•
There are three possibilities:
–
8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0]
bits (stored into the DHRx[11:4] bits)
–
12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4]
bits (stored into the DHRx[11:0] bits)
–
12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0]
bits (stored into the DHRx[11:0] bits)
Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and
stored into the corresponding DHRx (data holding registerx, which are internal non-memorymapped registers). The DHRx register is then loaded into the DORx register either
automatically, by software trigger or by an external event trigger.
Figure 55. Data registers in single DAC channel mode
31
24
15
7
0
8-bit right aligned
12-bit left aligned
12-bit right aligned
ai14710
15.3.4
DAC channel conversion
The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must
be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx,
DAC_DHR12Rx).
Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx
register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR
register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR
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Digital-to-analog converter (DAC)
register is set) and a trigger occurs, the transfer is performed three PCLK1 clock cycles
later.
When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage
becomes available after a time tSETTLING that depends on the power supply voltage and the
analog output load.
Figure 56. Timing diagram for conversion with trigger disabled TEN = 0
APB1_CLK
DHR
DOR
0x1AC
0x1AC
Output voltage
available on DAC_OUT pin
tSETTLING
ai14711b
Independent trigger with single LFSR generation
To configure the DAC in this conversion mode (see Section 15.4: Noise generation), the
following sequence is required:
1.
Set the DAC channel trigger enable bit TENx.
2.
Configure the trigger source by setting TSELx[2:0] bits.
3.
Configure the DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in
the MAMPx[3:0] bits
4.
Load the DAC channel data into the desired DAC_DHRx register (DHR12RD,
DHR12LD or DHR8RD).
When a DAC channelx trigger arrives, the LFSRx counter, with the same mask, is added to
the DHRx register and the sum is transferred into DAC_DORx (three APB clock cycles
later). Then the LFSRx counter is updated.
Independent trigger with single triangle generation
To configure the DAC in this conversion mode (see Section 15.5: Triangle-wave generation),
the following sequence is required:
1.
Set the DAC channelx trigger enable TENx bits.
2.
Configure the trigger source by setting TSELx[2:0] bits.
3.
Configure the DAC channelx WAVEx[1:0] bits as “1x” and the same maximum
amplitude value in the MAMPx[3:0] bits
4.
Load the DAC channelx data into the desired DAC_DHRx register. (DHR12RD,
DHR12LD or DHR8RD).
When a DAC channelx trigger arrives, the DAC channelx triangle counter, with the same
triangle amplitude, is added to the DHRx register and the sum is transferred into
DAC_DORx (three APB clock cycles later). The DAC channelx triangle counter is then
updated.
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RM0376
DAC output voltage
Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+.
The analog output voltages on each DAC channel pin are determined by the following
equation:
DOR
DACoutput = V REF+ × -------------4095
15.3.6
DAC trigger selection
If the TENx control bit is set, conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8
possible events will trigger conversion as shown in Table 59.
Table 59. External triggers
Source
Type
TSEL[2:0]
TIM6 TRGO event
000
Reserved
001
Reserved
TIM21 TRGO event
Internal signal from on-chip
timers
010
011
TIM2 TRGO event
100
Reserved
101
EXTI line9
External pin
110
SWTRIG
Software control bit
111
Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on
the selected external interrupt line 9, the last data stored into the DAC_DHRx register are
transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1
cycles after the trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
Note:
TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is
selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only
one APB1 clock cycle.
15.4
Noise generation
In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift
register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The
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preloaded value in LFSR is 0xAAA. This register is updated three APB clock cycles after
each trigger event, following a specific calculation algorithm.
Figure 57. DAC LFSR register calculation algorithm
XOR
X6
X 12
11
10
9
8
7
6
X4
5
4
X0
X
3
2
1
0
12
NOR
ai14713b
The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in
the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this
value is then stored into the DAC_DORx register.
If LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.
Figure 58. DAC conversion (SW trigger enabled) with LFSR wave generation
APB1_CLK
DHR
DOR
0x00
0xAAA
0xD55
SWTRIG
ai14714
Note:
The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CR register.
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15.5
RM0376
Triangle-wave generation
It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is
configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter
is incremented three APB clock cycles after each trigger event. The value of this counter is
then added to the DAC_DHRx register without overflow and the sum is stored into the
DAC_DORx register. The triangle counter is incremented as long as it is less than the
maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is
reached, the counter is decremented down to 0, then incremented again and so on.
It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.
Figure 59. DAC triangle wave generation
N
TIO
EN
EM
CR
N
TIO
TA
)N
EN
EM
CR
TA
$E
-!-0X;=MAXAMPLITUDE
$!#?$(2XBASEVALUE
$!#?$(2XBASEVALUE
AIC
Figure 60. DAC conversion (SW trigger enabled) with triangle wave generation
APB1_CLK
DHR
DOR
0xABE
0xABE
0xABF
0xAC0
SWTRIG
ai14714
Note:
The DAC trigger must be enabled for triangle generation by setting the TENx bit in the
DAC_CR register.
The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot
be changed.
15.6
DMA request
Each DAC channel has a DMA capability. Two DMA channels are used to service DAC
channel DMA requests.
A DAC DMA request is generated when an external trigger (but not a software trigger)
occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred
to the DAC_DORx register.
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DMA underrun
The DAC DMA request is not queued so that if a second external trigger arrives before the
acknowledgment for the first external trigger is received (first request), then no new request
is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set,
reporting the error condition. DMA data transfers are then disabled and no further DMA
request is treated. The DAC channelx continues to convert old data.
The software should clear the DMAUDRx flag by writing “1”, clear the DMAEN bit of the
used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer
correctly. The software should modify the DAC trigger conversion frequency or lighten the
DMA workload to avoid a new DMA. Finally, the DAC conversion can be resumed by
enabling both DMA data transfer and conversion trigger.
For each DAC channel, an interrupt is also generated if the corresponding DMAUDRIEx bit
in the DAC_CR register is enabled.
15.7
DAC registers
Refer to Section 1.1 on page 43 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).
15.7.1
DAC control register (DAC_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
DMAU
DRIE1
DMA
EN1
rw
rw
Res.
27
26
25
24
23
Res.
11
10
rw
21
Res.
9
8
MAMP1[3:0]
rw
22
rw
7
rw
19
Res.
6
5
WAVE1[1:0]
rw
20
rw
4
3
TSEL1[2:0]
rw
rw
rw
18
17
16
Res.
Res.
Res.
2
1
0
TEN1
BOFF1
EN1
rw
rw
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable
This bit is set and cleared by software.
0: DAC channel1 DMA Underrun Interrupt disabled
1: DAC channel1 DMA Underrun Interrupt enabled
Bit 12 DMAEN1: DAC channel1 DMA enable
This bit is set and cleared by software.
0: DAC channel1 DMA mode disabled
1: DAC channel1 DMA mode enabled
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Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector
These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable
These bits are set and cleared by software.
00: Wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
Bits 5:3 TSEL1[2:0]: DAC channel1 trigger selection
These bits select the external event used to trigger DAC channel1.
000: Timer 6 TRGO event
001: Reserved
010: Reserved
011: Timer 21 TRGO event
100: Timer 2 TRGO event
101: Reserved
110: EXTI line9
111: Software trigger
Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
Bit 2 TEN1: DAC channel1 trigger enable
This bit is set and cleared by software to enable/disable DAC channel1 trigger.
0: DAC channel1 trigger disabled and data written into the DAC_DHRx register are
transferred one APB1 clock cycle later to the DAC_DOR1 register
1: DAC channel1 trigger enabled and data from the DAC_DHRx register are transferred
three APB1 clock cycles later to the DAC_DOR1 register
Note: When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DOR1 register takes only one APB1 clock cycle.
Bit 1 BOFF1: DAC channel1 output buffer disable
This bit is set and cleared by software to enable/disable DAC channel1 output buffer.
0: DAC channel1 output buffer enabled
1: DAC channel1 output buffer disabled
Bit 0 EN1: DAC channel1 enable
This bit is set and cleared by software to enable/disable DAC channel1.
0: DAC channel1 disabled
1: DAC channel1 enabled
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15.7.2
DAC software trigger register (DAC_SWTRIGR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SWTRIG1
w
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SWTRIG1: DAC channel1 software trigger
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1
register value has been loaded into the DAC_DOR1 register.
15.7.3
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
15
14
13
12
Res.
Res.
Res.
Res.
DACC1DHR[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
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RM0376
DAC channel1 12-bit left-aligned data holding register
(DAC_DHR12L1)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
DACC1DHR[11:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
3
2
1
0
Res.
Res.
Res.
Res.
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.
15.7.5
DAC channel1 8-bit right-aligned data holding register
(DAC_DHR8R1)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
rw
rw
rw
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DACC1DHR[7:0]
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel1.
15.7.6
DAC channel1 data output register (DAC_DOR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
15
14
13
12
Res.
Res.
Res.
Res.
DACC1DOR[11:0]
r
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Bits 31:12 Reserved, must be kept at reset value.
Bit 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.
15.7.7
DAC status register (DAC_SR)
Address offset: 0x34
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
DMAUDR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rc_w1
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 DMAUDR1: DAC channel1 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel1
1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is
driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
Bits 12:0 Reserved, must be kept at reset value.
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0x34
DAC_SR
Reset value
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0
Refer to Section 2.2.2 for the register boundary addresses.
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
Reset value
0
DACC1DHR[11:0]
0
0
0
0
0
0
0
0
0
0
0
DACC1DHR[7:0]
0
Res.
0
Res.
0
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMAEN1
TEN1
BOFF1
EN1
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SWTRIG1
TSEL1[2:0]
WAVE1[1:0]
MAMP1[3:0].
DMAUDRIE1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
DMAUDR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DAC_DOR1
Res.
0x2C
Res.
DAC_
DHR8R1
Res.
0x10
DAC_
DHR12L1
Res.
0x0C
DAC_
DHR12R1
Res.
0x08
DAC_
SWTRIGR
Res.
DAC_CR
Res.
0x00
Res.
0x04
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
name
Res.
Offset
Res.
15.7.8
Res.
Digital-to-analog converter (DAC)
RM0376
DAC register map
Table 60 summarizes the DAC registers.
Table 60. DAC register map and reset values
Reset value
0
DACC1DHR[11:0]
0
0
0
0
DACC1DOR[11:0]
RM0376
Comparator (COMP)
16
Comparator (COMP)
16.1
Introduction
STM32L0x2 devices embed two ultra-low power comparators COMP1, and COMP2 that
can be used either as standalone devices (all terminal are available on I/Os) or combined
with the timers. They can be used for a variety of functions including:
16.2
•
Wake-up from low-power mode triggered by an analog signal,
•
Analog signal conditioning,
•
Cycle-by-cycle current control loop when combined with the DAC and a PWM output
from a timer.
COMP main features
•
COMP1 comparator with ultra low consumption
•
COMP2 comparator with rail-to-rail inputs, fast or slow mode
•
Each comparator has positive and configurable negative inputs used for flexible voltage
selection:
–
I/O pins
–
DAC
–
Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by
scaler (buffered voltage divider)
•
Programmable speed / consumption (COMP2 only)
•
The outputs can be redirected to an I/O or to multiple timer inputs for triggering:
–
•
Capture events
COMP1, and COMP2 can be combined in a window comparator. Each comparator has
interrupt generation capability with wake-up from Sleep and Stop modes (through the
EXTI controller)
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16.3
COMP functional description
16.3.1
COMP block diagram
The block diagram of the comparators is shown in Figure 61: Comparator 1 and 2 block
diagrams.
Figure 61. Comparator 1 and 2 block diagrams
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16.3.2
COMP pins and internal signals
The I/Os used as comparators inputs must be configured in analog mode in the GPIOs
registers.
The comparator output can be connected to the I/Os using the alternate function channel
given in “Alternate function mapping” table in the datasheet.
The output can also be internally redirected to a variety of timer input for the following
purposes:
•
Input capture for timing measures
It is possible to have the comparator output simultaneously redirected internally and
externally.
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16.3.3
Comparator (COMP)
COMP reset and clocks
The COMP clock provided by the clock controller is synchronous with the PCLK (APB
clock).
There is no clock enable control bit provided in the RCC controller. Reset and clock enable
bits are common for COMP and SYSCFG.
Note:
Important: The polarity selection logic and the output redirection to the port works
independently from the PCLK clock. This allows the comparator to work even in Stop mode.
16.3.4
Comparator LOCK mechanism
The comparators can be used for safety purposes, such as over-current or thermal
protection. For applications having specific functional safety requirements, it is necessary to
insure that the comparator programming cannot be altered in case of spurious register
access or program counter corruption.
For this purpose, the comparator control and status registers can be write-protected (readonly).
Once the programming is completed, the COMPxLOCK bit can be set to 1. This causes the
whole COMPx_CSR register to become read-only, including the COMPxLOCK bit.
The write protection can only be reset by a MCU reset.
16.4
Power mode
COMP2 power consumption versus propagation delay can be adjusted to have the optimum
trade-off for a given application.
COMP2_SPEED bit in the COMP2_CSR register can be programmed to provide either
higher speed/consumption or lower speed/consumption.
16.5
Interrupts
The comparator outputs are internally connected to the Extended interrupts and events
controller. Each comparator has its own EXTI line and can generate either interrupts or
events. The same mechanism is used to exit from low-power modes.
Refer to Interrupt and events section for more details.
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16.6
COMP registers
16.6.1
Comparator 1 control and status register (COMP1_CSR)
The COMP1_CSR is the Comparator1 control/status register. It contains all the bits /flags
related to comparator1.
Address offset: 0x18
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
COMP1
LOCK
COMP1
VALUE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
13
12
11
10
9
8
7
6
5
4
Res.
COMP1
WM
rs
r
15
14
COMP1
POLARITY
Res.
Res.
Res.
Res.
Res.
rw
rw
Res.
Res.
COMP1INN
SEL
rw
19
18
17
Res. Res. Res.
3
2
1
16
Res.
0
COMP1
Res. Res. Res.
EN
rw
rw
Bit 31 COMP1LOCK: COMP1_CSR register lock bit
This bit is set by software and cleared by a hardware system reset. It locks the whole
content of the comparator 1 control register, COMP1_CSR[31:0]
0: COMP1_CSR[31:0] for comparator 1 are read/write
1: COMP1_CSR[31:0] for comparator 1 are read-only
Bit 30 COMP1VALUE: Comparator 1 output status bit
This bit is read-only. It reflects the current comparator 1 output taking into account
COMP1POLARITY bit effect.
Bits 29:16 Reserved, must be kept at reset value
Bit 15 COMP1POLARITY: Comparator 1 polarity selection bit
This bit is set and cleared by software (only if COMP1LOCK not set). It inverts Comparator
1 polarity.
0: Comparator 1 output value not inverted
1: Comparator 1output value inverted
Bits 14:9 Reserved, must be kept at reset value
Bit 8 COMP1WM: Comparator 1 window mode selection bit
This bit is set and cleared by software (only if COMP1LOCK not set). It selects comparator
1 window mode where the Plus inputs of both comparators are connected together.
0: Plus input of comparator 1 connected to PA1.
1: Plus input of comparator 1 shorted with Plus input of comparator 2 (see COMP1_CSR).
Bits 7:6 Reserved, must be kept at reset value
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Comparator (COMP)
Bits 5:4 COMP1INNSEL: Comparator 1 Input Minus connection configuration bit
These bits are set and cleared by software (only if COMP1LOCK not set). They select which
input is connected with the Input Minus of comparator 1
00: VREFINT
01: PA0
10: DAC 1/PA4
11: PA5
Bits 3:1 Reserved, must be kept at reset value
Bit 0 COMP1EN: Comparator 1 enable bit
This bit is set and cleared by software (only if COMP1LOCK not set). It switches
oncomparator1
0: Comparator 1 switched OFF.
1: Comparator 1 switched ON.
16.6.2
Comparator 2 control and status register (COMP2_CSR)
The COMP2_CSR is the Comparator2 control/status register. It contains all the bits /flags
related to comparator2.
Address offset: 0x1C
System reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
COMP2
LOCK
COMP2
VALUE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
13
12
11
10
9
8
7
rs
r
15
14
COMP2
POLARITY
rw
Res.
Res.
Res.
Res.
COMP2INPSEL
rw
rw
Res.
rw
22
21
Res. Res.
6
5
20
19
Res.
Res.
4
COMP2INNSEL
rw
rw
rw
3
COMP2
SPEED
18
17
16
Res. Res.
2
Res.
1
0
COMP2
Res. Res.
EN
rw
rw
Bit 31 COMP2LOCK: COMP2_CSR register lock bit
This bit is set by software and cleared by a hardware system reset. It locks the whole
content of the comparator 2 control register, COMP2_CSR[31:0]
0: COMP2_CSR[31:0] for comparator 1 are read/write
1: COMP2_CSR[31:0] for comparator 1 are read-only
Bit 30 COMP2VALUE: Comparator 2 output status bit
This bit is read-only. It reflects the current comparator 2 output taking into account
COMP2POLARITY bit effect.
Bits 29:16 Reserved, must be kept at reset value
Bit 15 COMP2POLARITY: Comparator 2 polarity selection bit
This bit is set and cleared by software (only if COMP2LOCK not set). It inverts Comparator
1 polarity.
0: Comparator 2 output value not inverted
1: Comparator 2 output value inverted
Bits 14:11 Reserved, must be kept at reset value
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Bits 10:8 COMP2INPSEL: Comparator 2 Input Plus connection configuration bit
These bits are set and cleared by software (only if COMP2LOCK not set). They select which
input is connected with the Input Plus of comparator 2
000: PA3
001: PB4
010: PB5
011: PB6
100: PB7
101: PB7
110: PB7
111: PB7
Bits 7 Reserved, must be kept at reset value
Bits 6:4 COMP2INNSEL: Comparator 2 Input Minus connection configuration bit
These bits are set and cleared by software (only if COMP2LOCK not set). They select which
input is connected with the Input Minus of comparator 2.
000: VREFINT
001: PA2
010: DAC 1/PA4
011: PA5
100: 1/4 VREFINT
101: 1/2 VREFINT
110: 3/4 VREFINT
111: PB3
Bit 3 COMP2SPEED: Comparator 2 power mode selection bit
This bit is set and cleared by software (only if COMP2LOCK not set). It selects comparator
2 power mode.
0: slow speed
1: fast speed
Bit 2 Reserved, must be kept at reset value
Bit 0 COMP2EN: Comparator 2 enable bit
This bit is set and cleared by software (only if COMP2LOCK not set). It switches
oncomparator2.
0: Comparator 2 switched off.
1: Comparator 2 switched ON.
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16.6.3
Comparator (COMP)
COMP register map
The following table summarizes the comparator registers.
The comparator registers share SYS_CFG peripheral register base addresses.
0
0
0
0
0
0
0
Res.
COMP1EN
Res.
Res.
0
COMP2EN
Res.
COMP2SPEED
0
Res.
0
COMP2INNSEL
0
Res.
COMP2INPSEL
Res.
Res.
Res.
Res.
0
COMP1INNSEL
Res.
Res.
Res.
COMP1WM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
COMP1POLARITY
COMP2POLARITY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
0
Res.
Reset value
Res.
COMP2_CSR
0
Res.
0
Res.
0
Res.
Reset value
Res.
COMP1LOCK
COMP1VALUE
0x1C
COMP1_CSR
COMP2LOCK
0x18
Register
COMP2VALUE
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 61. COMP register map and reset values
0
Refer to Section 2.2.2 for the register boundary addresses.
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17
Touch sensing controller (TSC)
17.1
Introduction
The touch sensing controller provides a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect finger
presence near an electrode which is protected from direct touch by a dielectric (glass,
plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
17.2
TSC main features
The touch sensing controller has the following main features:
Note:
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•
Proven and robust surface charge transfer acquisition principle
•
Supports up to 24 capacitive sensing channels
•
Up to 8 capacitive sensing channels can be acquired in parallel offering a very good
response time
•
Spread spectrum feature to improve system robustness in noisy environments
•
Full hardware management of the charge transfer acquisition sequence
•
Programmable charge transfer frequency
•
Programmable sampling capacitor I/O pin
•
Programmable channel I/O pin
•
Programmable max count value to avoid long acquisition when a channel is faulty
•
Dedicated end of acquisition and max count error flags with interrupt capability
•
One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
•
Compatible with proximity, touchkey, linear and rotary touch sensor implementation
•
Designed to operate with STMTouch touch sensing firmware library
The number of capacitive sensing channels is dependent on the size of the packages and
subject to IO availability.
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Touch sensing controller (TSC)
17.3
TSC functional description
17.3.1
TSC block diagram
The block diagram of the touch sensing controller is shown in Figure 62: TSC block
diagram.
Figure 62. TSC block diagram
39.#
0ULSEGENERATOR
F(#,+
'?)/
#LOCK
PRESCALERS
'?)/
'?)/
3PREADSPECTRUM
'?)/
'?)/
'?)/
'ROUPCOUNTERS
)/CONTROL
LOGIC
'?)/
'?)/
43#?)/'#2
43#?)/'#2
'X?)/
'X?)/
43#?)/'X#2
'X?)/
'X?)/
-36
17.3.2
Surface charge transfer acquisition overview
The surface charge transfer acquisition is a proven, robust and efficient way to measure a
capacitance. It uses a minimum number of external components to operate with a single
ended electrode type. This acquisition is designed around an analog I/O group which is
composed of four GPIOs (see Figure 63). Several analog I/O groups are available to allow
the acquisition of several capacitive sensing channels simultaneously and to support a
larger number of capacitive sensing channels. Within a same analog I/O group, the
acquisition of the capacitive sensing channels is sequential.
One of the GPIOs is dedicated to the sampling capacitor CS. Only one sampling capacitor
I/O per analog I/O group must be enabled at a time.
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The remaining GPIOs are dedicated to the electrodes and are commonly called channels.
For some specific needs (such as proximity detection), it is possible to simultaneously
enable more than one channel per analog I/O group.
Figure 63. Surface charge transfer analog I/O group structure
%LECTRODE
23
'?)/
!NALOG
)/GROUP
#8
'?)/
#3
%LECTRODE
23
'?)/
23
'?)/
#8
%LECTRODE
#8
-36
Note:
Gx_IOy where x is the analog I/O group number and y the GPIO number within the selected
group.
The surface charge transfer acquisition principle consists of charging an electrode
capacitance (CX) and transferring a part of the accumulated charge into a sampling
capacitor (CS). This sequence is repeated until the voltage across CS reaches a given
threshold (VIH in our case). The number of charge transfers required to reach the threshold
is a direct representation of the size of the electrode capacitance.
The Table 62 details the charge transfer acquisition sequence of the capacitive sensing
channel 1. States 3 to 7 are repeated until the voltage across CS reaches the given
threshold. The same sequence applies to the acquisition of the other channels. The
electrode serial resistor RS improves the ESD immunity of the solution.
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Table 62. Acquisition sequence summary
State
G1_IO1
(electrode)
G1_IO2
(sampling)
#1
Input floating
with analog
switch closed
Output opendrain low with
analog switch
closed
#2
#3
G1_IO4
(electrode)
State description
Input floating with analog switch Discharge all CX and
CS
closed
Input floating
Output pushpull high
#4
#5
G1_IO3
(electrode)
Dead time
Input floating
Charge CX1
Input floating
Input floating with analog switch
closed
Dead time
Input floating
Charge transfer from
CX1 to CS
#6
Input floating
Dead time
#7
Input floating
Measure CS voltage
The voltage variation over the time on the sampling capacitor CS is detailed below:
Figure 64. Sampling capacitor voltage variation
6#3
6$$
4HRESHOLD6)(
T
"URSTDURATION
-36
17.3.3
Reset and clocks
The TSC clock source is the AHB clock (HCLK). Two programmable prescalers are used to
generate the pulse generator and the spread spectrum internal clocks:
•
The pulse generator clock (PGCLK) is defined using the PGPSC[2:0] bits of the
TSC_CR register
•
The spread spectrum clock (SSCLK) is defined using the SSPSC bit of the TSC_CR
register
The Reset and Clock Controller (RCC) provides dedicated bits to enable the touch sensing
controller clock and to reset this peripheral. For more information, please refer to Section 7:
Reset and clock control (RCC).
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17.3.4
RM0376
Charge transfer acquisition sequence
An example of a charge transfer acquisition sequence is detailed in Figure 65.
Figure 65. Charge transfer acquisition sequence
#HARGETRANSFERFREQUENCY
#,+?!("
#8 (I:
$EADTIMESTATE
#3READINGSTATE
$EADTIMESTATE
0ULSELOWSTATE
CHARGETRANSFER
FROM#8TO#3
#3READINGSTATE
0ULSEHIGHSTATE
CHARGEOF#8
$EADTIMESTATE
$ISCHARGE
#8AND#3
$EADTIMESTATE
3TATE
$EADTIMESTATE
3PREAD3PECTRUMSTATE
#3 (I:
T
-36
For higher flexibility, the charge transfer frequency is fully configurable. Both the pulse high
state (charge of CX) and the pulse low state (transfer of charge from CX to CS) duration can
be defined using the CTPH[3:0] and CTPL[3:0] bits in the TSC_CR register. The standard
range for the pulse high and low states duration is 500 ns to 2 µs. To ensure a correct
measurement of the electrode capacitance, the pulse high state duration must be set to
ensure that CX is always fully charged.
A dead time where both the sampling capacitor I/O and the channel I/O are in input floating
state is inserted between the pulse high and low states to ensure an optimum charge
transfer acquisition sequence. This state duration is 2 periods of HCLK.
At the end of the pulse high state and if the spread spectrum feature is enabled, a variable
number of periods of the SSCLK clock are added.
The reading of the sampling capacitor I/O, to determine if the voltage across CS has
reached the given threshold, is performed at the end of the pulse low state and its duration
is one period of HCLK.
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17.3.5
Touch sensing controller (TSC)
Spread spectrum feature
The spread spectrum feature allows to generate a variation of the charge transfer
frequency. This is done to improve the robustness of the charge transfer acquisition in noisy
environments and also to reduce the induced emission. The maximum frequency variation
is in the range of 10 % to 50 % of the nominal charge transfer period. For instance, for a
nominal charge transfer frequency of 250 KHz (4 µs), the typical spread spectrum deviation
is 10 % (400 ns) which leads to a minimum charge transfer frequency of ~227 KHz.
In practice, the spread spectrum consists of adding a variable number of SSCLK periods to
the pulse high state using the principle shown below:
Figure 66. Spread spectrum variation principle
$EVIATIONVALUE
33$
N N
N
.UMBEROFPULSES
-36
The table below details the maximum frequency deviation with different HCLK settings:
Table 63. Spread spectrum deviation versus AHB clock frequency
fHCLK
Spread spectrum step
Maximum spread spectrum deviation
24 MHz
41.6 ns
10666.6 ns
32 MHz
27.7 ns
7111.1 ns
The spread spectrum feature can be disabled/enabled using the SSE bit in the TSC_CR
register. The frequency deviation is also configurable to accommodate the device HCLK
clock frequency and the selected charge transfer frequency through the SSPSC and
SSD[6:0] bits in the TSC_CR register.
17.3.6
Max count error
The max count error prevents long acquisition times resulting from a faulty capacitive
sensing channel. It consists of specifying a maximum count value for the analog I/O group
counters. This maximum count value is specified using the MCV[2:0] bits in the TSC_CR
register. As soon as an acquisition group counter reaches this maximum value, the on-going
acquisition is stopped and the end of acquisition (EOAF bit) and max count error (MCEF bit)
flags are both set. An interrupt can also be generated if the corresponding end of acquisition
(EOAIE bit) or/and max count error (MCEIE bit) interrupt enable bits are set.
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17.3.7
RM0376
Sampling capacitor I/O and channel I/O mode selection
To allow the GPIOs to be controlled by the touch sensing controller, the corresponding
alternate function must be enabled through the standard GPIO registers and the GPIOxAFR
registers.
The GPIOs modes controlled by the TSC are defined using the TSC_IOSCR and
TSC_IOCCR register.
When there is no on-going acquisition, all the I/Os controlled by the touch sensing controller
are in default state. While an acquisition is on-going, only unused I/Os (neither defined as
sampling capacitor I/O nor as channel I/O) are in default state. The IODEF bit in the
TSC_CR register defines the configuration of the I/Os which are in default state. The table
below summarizes the configuration of the I/O depending on its mode.
Table 64. I/O state depending on its mode and IODEF bit value
IODEF bit
Acquisition
status
Unused I/O
mode
Electrode I/O
mode
Sampling
capacitor I/O
mode
0
(output push-pull
low)
No
Output push-pull
low
Output push-pull
low
Output push-pull
low
0
(output push-pull
low)
On-going
Output push-pull
low
-
-
1
(input floating)
No
Input floating
Input floating
Input floating
1
(input floating)
On-going
Input floating
-
-
Unused I/O mode
An unused I/O corresponds to a GPIO controlled by the TSC peripheral but not defined as
an electrode I/O nor as a sampling capacitor I/O.
Sampling capacitor I/O mode
To allow the control of the sampling capacitor I/O by the TSC peripheral, the corresponding
GPIO must be first set to alternate output open drain mode and then the corresponding
Gx_IOy bit in the TSC_IOSCR register must be set.
Only one sampling capacitor per analog I/O group must be enabled at a time.
Channel I/O mode
To allow the control of the channel I/O by the TSC peripheral, the corresponding GPIO must
be first set to alternate output push-pull mode and the corresponding Gx_IOy bit in the
TSC_IOCCR register must be set.
For proximity detection where a higher equivalent electrode surface is required or to speedup the acquisition process, it is possible to enable and simultaneously acquire several
channels belonging to the same analog I/O group.
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Note:
During the acquisition phase and even if the TSC peripheral alternate function is not
enabled, as soon as the TSC_IOSCR or TSC_IOCCR bit is set, the corresponding GPIO
analog switch is automatically controlled by the touch sensing controller.
17.3.8
Acquisition mode
The touch sensing controller offers two acquisition modes:
•
Normal acquisition mode: the acquisition starts as soon as the START bit in the
TSC_CR register is set.
•
Synchronized acquisition mode: the acquisition is enabled by setting the START bit in
the TSC_CR register but only starts upon the detection of a falling edge or a rising
edge and high level on the SYNC input pin. This mode is useful for synchronizing the
capacitive sensing channels acquisition with an external signal without additional CPU
load.
The GxE bits in the TSC_IOGCSR registers specify which analog I/O groups are enabled
(corresponding counter is counting). The CS voltage of a disabled analog I/O group is not
monitored and this group does not participate in the triggering of the end of acquisition flag.
However, if the disabled analog I/O group contains some channels, they will be pulsed.
When the CS voltage of an enabled analog I/O group reaches the given threshold, the
corresponding GxS bit of the TSC_IOGCSR register is set. When the acquisition of all
enabled analog I/O groups is complete (all GxS bits of all enabled analog I/O groups are
set), the EOAF flag in the TSC_ISR register is set. An interrupt request is generated if the
EOAIE bit in the TSC_IER register is set.
In the case that a max count error is detected, the on-going acquisition is stopped and both
the EOAF and MCEF flags in the TSC_ISR register are set. Interrupt requests can be
generated for both events if the corresponding bits (EOAIE and MCEIE bits of the TSCIER
register) are set. Note that when the max count error is detected the remaining GxS bits in
the enabled analog I/O groups are not set.
To clear the interrupt flags, the corresponding EOAIC and MCEIC bits in the TSC_ICR
register must be set.
The analog I/O group counters are cleared when a new acquisition is started. They are
updated with the number of charge transfer cycles generated on the corresponding
channel(s) upon the completion of the acquisition.
17.3.9
I/O hysteresis and analog switch control
In order to offer a higher flexibility, the touch sensing controller also allows to take the control
of the Schmitt trigger hysteresis and analog switch of each Gx_IOy. This control is available
whatever the I/O control mode is (controlled by standard GPIO registers or other
peripherals, ...) assuming that the touch sensing controller is enabled. This may be useful to
perform a different acquisition sequence or for other purposes.
In order to improve the system immunity, the Schmitt trigger hysteresis of the GPIOs
controlled by the TSC must be disabled by resetting the corresponding Gx_IOy bit in the
TSC_IOHCR register.
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17.3.10
RM0376
Capacitive sensing GPIOs
The table below provides an overview of the capacitive sensing GPIOs.
Table 65. Capacitive sensing GPIOs
Group
1
2
3
4
17.4
Capacitive sensing
group name
Pin name
Capacitive sensing
group name
Pin name
TSC_G1_IO1
PA0
TSC_G5_IO1
PB3
TSC_G1_IO2
PA1
TSC_G5_IO2
PB4
TSC_G1_IO3
PA2
TSC_G5_IO3
PB6
TSC_G1_IO4
PA3
TSC_G5_IO4
PB7
TSC_G2_IO1
PA4
TSC_G6_IO1
PB11
TSC_G2_IO2
PA5
TSC_G6_IO2
PB12
TSC_G2_IO3
PA6
TSC_G6_IO3
PB13
TSC_G2_IO4
PA7
TSC_G6_IO4
PB14
TSC_G3_IO1
PC5
TSC_G7_IO1
PC0
TSC_G3_IO2
PB0
TSC_G7_IO2
PC1
TSC_G3_IO3
PB1
TSC_G7_IO3
PC2
TSC_G3_IO4
PB2
TSC_G7_IO4
PC3
TSC_G4_IO1
PA9
TSC_G8_IO1
PC6
TSC_G4_IO2
PA10
TSC_G8_IO2
PC7
TSC_G4_IO3
PA11
TSC_G8_IO3
PC8
TSC_G4_IO4
PA12
TSC_G8_IO4
PC9
Group
5
6
7
8
TSC low-power modes
Table 66. Effect of low-power modes on TSC
Mode
Sleep
Description
No effect
TSC interrupts cause the device to exit Sleep mode.
Stop
TSC registers are frozen
Standby The TSC stops its operation until the Stop or Standby mode is exited.
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17.5
TSC interrupts
Table 67. Interrupt control bits
Interrupt event
Enable
control bit
Event flag
Clear flag
bit
Exit the
Sleep
mode
Exit the
Stop mode
Exit the
Standby
mode
End of acquisition
EOAIE
EOAIF
EOAIC
yes
no
no
Max count error
MCEIE
MCEIF
MCEIC
yes
no
no
17.6
TSC registers
Refer to Section 1.1 on page 43 of the reference manual for a list of abbreviations used in
register descriptions.
The peripheral registers can be accessed by words (32-bit).
17.6.1
TSC control register (TSC_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
CTPH[3:0]
26
25
24
23
22
21
CTPL[3:0]
20
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
rw
PGPSC[2:0]
rw
rw
Res.
rw
Res.
18
17
16
SSD[6:0]
rw
SSPSC
19
Res.
Res.
MCV[2:0]
rw
rw
rw
SSE
rw
rw
rw
rw
4
3
2
1
0
IODEF
SYNC
POL
AM
START
TSCE
rw
rw
rw
rw
rw
Bits 31:28 CTPH[3:0]: Charge transfer pulse high
These bits are set and cleared by software. They define the duration of the high state of the
charge transfer pulse (charge of CX).
0000: 1x tPGCLK
0001: 2x tPGCLK
...
1111: 16x tPGCLK
Note: These bits must not be modified when an acquisition is on-going.
Bits 27:24 CTPL[3:0]: Charge transfer pulse low
These bits are set and cleared by software. They define the duration of the low state of the
charge transfer pulse (transfer of charge from CX to CS).
0000: 1x tPGCLK
0001: 2x tPGCLK
...
1111: 16x tPGCLK
Note: These bits must not be modified when an acquisition is on-going.
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Bits 23:17 SSD[6:0]: Spread spectrum deviation
These bits are set and cleared by software. They define the spread spectrum deviation which
consists in adding a variable number of periods of the SSCLK clock to the charge transfer
pulse high state.
0000000: 1x tSSCLK
0000001: 2x tSSCLK
...
1111111: 128x tSSCLK
Note: These bits must not be modified when an acquisition is on-going.
Bit 16 SSE: Spread spectrum enable
This bit is set and cleared by software to enable/disable the spread spectrum feature.
0: Spread spectrum disabled
1: Spread spectrum enabled
Note: This bit must not be modified when an acquisition is on-going.
Bit 15 SSPSC: Spread spectrum prescaler
This bit is set and cleared by software. It selects the AHB clock divider used to generate the
spread spectrum clock (SSCLK).
0: fHCLK
1: fHCLK /2
Note: This bit must not be modified when an acquisition is on-going.
Bits 14:12 PGPSC[2:0]: pulse generator prescaler
These bits are set and cleared by software.They select the AHB clock divider used to generate
the pulse generator clock (PGCLK).
000: fHCLK
001: fHCLK /2
010: fHCLK /4
011: fHCLK /8
100: fHCLK /16
101: fHCLK /32
110: fHCLK /64
111: fHCLK /128
Note: These bits must not be modified when an acquisition is on-going.
Bits 11:8 Reserved, must be kept at reset value.
Bits 7:5 MCV[2:0]: Max count value
These bits are set and cleared by software. They define the maximum number of charge
transfer pulses that can be generated before a max count error is generated.
000: 255
001: 511
010: 1023
011: 2047
100: 4095
101: 8191
110: 16383
111: reserved
Note: These bits must not be modified when an acquisition is on-going.
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RM0376
Touch sensing controller (TSC)
Bit 4 IODEF: I/O Default mode
This bit is set and cleared by software. It defines the configuration of all the TSC I/Os when
there is no on-going acquisition. When there is an on-going acquisition, it defines the
configuration of all unused I/Os (not defined as sampling capacitor I/O or as channel I/O).
0: I/Os are forced to output push-pull low
1: I/Os are in input floating
Note: This bit must not be modified when an acquisition is on-going.
Bit 3 SYNCPOL: Synchronization pin polarity
This bit is set and cleared by software to select the polarity of the synchronization input pin.
0: Falling edge only
1: Rising edge and high level
Bit 2 AM: Acquisition mode
This bit is set and cleared by software to select the acquisition mode.
0: Normal acquisition mode (acquisition starts as soon as START bit is set)
1: Synchronized acquisition mode (acquisition starts if START bit is set and when the
selected signal is detected on the SYNC input pin)
Note: This bit must not be modified when an acquisition is on-going.
Bit 1 START: Start a new acquisition
This bit is set by software to start a new acquisition. It is cleared by hardware as soon as the
acquisition is complete or by software to cancel the on-going acquisition.
0: Acquisition not started
1: Start a new acquisition
Bit 0 TSCE: Touch sensing controller enable
This bit is set and cleared by software to enable/disable the touch sensing controller.
0: Touch sensing controller disabled
1: Touch sensing controller enabled
Note: When the touch sensing controller is disabled, TSC registers settings have no effect.
17.6.2
TSC interrupt enable register (TSC_IER)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MCEIE
EOAIE
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Touch sensing controller (TSC)
RM0376
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 MCEIE: Max count error interrupt enable
This bit is set and cleared by software to enable/disable the max count error interrupt.
0: Max count error interrupt disabled
1: Max count error interrupt enabled
Bit 0 EOAIE: End of acquisition interrupt enable
This bit is set and cleared by software to enable/disable the end of acquisition interrupt.
0: End of acquisition interrupt disabled
1: End of acquisition interrupt enabled
17.6.3
TSC interrupt clear register (TSC_ICR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MCEIC EOAIC
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 MCEIC: Max count error interrupt clear
This bit is set by software to clear the max count error flag and it is cleared by hardware when
the flag is reset. Writing a ‘0’ has no effect.
0: No effect
1: Clears the corresponding MCEF of the TSC_ISR register
Bit 0 EOAIC: End of acquisition interrupt clear
This bit is set by software to clear the end of acquisition flag and it is cleared by hardware
when the flag is reset. Writing a ‘0’ has no effect.
0: No effect
1: Clears the corresponding EOAF of the TSC_ISR register
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RM0376
Touch sensing controller (TSC)
17.6.4
TSC interrupt status register (TSC_ISR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MCEF
EOAF
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 MCEF: Max count error flag
This bit is set by hardware as soon as an analog I/O group counter reaches the max count
value specified. It is cleared by software writing 1 to the bit MCEIC of the TSC_ICR register.
0: No max count error (MCE) detected
1: Max count error (MCE) detected
Bit 0 EOAF: End of acquisition flag
This bit is set by hardware when the acquisition of all enabled group is complete (all GxS bits
of all enabled analog I/O groups are set or when a max count error is detected). It is cleared by
software writing 1 to the bit EOAIC of the TSC_ICR register.
0: Acquisition is on-going or not started
1: Acquisition is complete
17.6.5
TSC I/O hysteresis control register (TSC_IOHCR)
Address offset: 0x10
Reset value: 0xFFFF FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 Gx_IOy: Gx_IOy Schmitt trigger hysteresis mode
These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger
hysteresis.
0: Gx_IOy Schmitt trigger hysteresis disabled
1: Gx_IOy Schmitt trigger hysteresis enabled
Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is
(even if controlled by standard GPIO registers).
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Touch sensing controller (TSC)
17.6.6
RM0376
TSC I/O analog switch control register (TSC_IOASCR)
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 Gx_IOy: Gx_IOy analog switch enable
These bits are set and cleared by software to enable/disable the Gx_IOy analog switch.
0: Gx_IOy analog switch disabled (opened)
1: Gx_IOy analog switch enabled (closed)
Note: These bits control the I/O analog switch whatever the I/O control mode is (even if
controlled by standard GPIO registers).
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RM0376
Touch sensing controller (TSC)
17.6.7
TSC I/O sampling control register (TSC_IOSCR)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 Gx_IOy: Gx_IOy sampling mode
These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor
I/O. Only one I/O per analog I/O group must be defined as sampling capacitor.
0: Gx_IOy unused
1: Gx_IOy used as sampling capacitor
Note: These bits must not be modified when an acquisition is on-going.
During the acquisition phase and even if the TSC peripheral alternate function is not
enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch
is automatically controlled by the touch sensing controller.
17.6.8
TSC I/O channel control register (TSC_IOCCR)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 Gx_IOy: Gx_IOy channel mode
These bits are set and cleared by software to configure the Gx_IOy as a channel I/O.
0: Gx_IOy unused
1: Gx_IOy used as channel
Note: These bits must not be modified when an acquisition is on-going.
During the acquisition phase and even if the TSC peripheral alternate function is not
enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch
is automatically controlled by the touch sensing controller.
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Touch sensing controller (TSC)
17.6.9
RM0376
TSC I/O group control status register (TSC_IOGCSR)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
G8S
G7S
G6S
G5S
G4S
G3S
G2S
G1S
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
G8E
G7E
G6E
G5E
G4E
G3E
G2E
G1E
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 GxS: Analog I/O group x status
These bits are set by hardware when the acquisition on the corresponding enabled analog I/O
group x is complete. They are cleared by hardware when a new acquisition is started.
0: Acquisition on analog I/O group x is on-going or not started
1: Acquisition on analog I/O group x is complete
Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O
groups are not set.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 GxE: Analog I/O group x enable
These bits are set and cleared by software to enable/disable the acquisition (counter is
counting) on the corresponding analog I/O group x.
0: Acquisition on analog I/O group x disabled
1: Acquisition on analog I/O group x enabled
17.6.10
TSC I/O group x counter register (TSC_IOGxCR) (x = 1..8)
Address offset: 0x30 + 0x04 x Analog I/O group number
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
r
r
r
r
r
r
CNT[13:0]
r
r
r
r
r
r
r
r
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:0 CNT[13:0]: Counter value
These bits represent the number of charge transfer cycles generated on the analog I/O group
x to complete its acquisition (voltage across CS has reached the threshold).
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0x0034
TSC_IOG1CR
0x002C
0
0
0
0
0
0
0
0
Reserved
0
Reset value
DocID025941 Rev 1
G1_IO3
G1_IO2
G1_IO1
G2_IO1
G1_IO4
G1_IO3
G1_IO2
G1_IO1
G4_IO2
G4_IO1
G3_IO4
0
G3_IO3
G3_IO2
G3_IO1
G2_IO4
G2_IO3
G2_IO2
0
0
0
0
0
0
0
G2_IO1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNT[13:0]
0
0
0
0
0
0
0
0
0
0
0
0
G1_IO4
G1_IO3
G1_IO2
G1_IO1
Reset value
Reset value
EOAIC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSCE
0
0
0
EOAIE
AM
Res.
START
Res.
0
Res.
Res.
IODEF
Res.
Res.
Res.
Res.
Res.
SYNCPOL
Res.
Res.
Res.
Res.
PGPSC[2:0]
0
MCEIE
Reset value
EOAF
Res.
Res.
0
MCEIC
Res.
0
MCEF
Res.
Res.
0
Res.
Res.
Res.
Res.
MCV
[2:0]
Res.
Res.
Res.
TSC_IER
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
Res.
Res.
Res.
SSE
SSPSC
0
Res.
Res.
Res.
Res.
Res.
0
G1E
G1_IO4
G2_IO2
G4_IO3
Res.
Res.
0
G2E
G2_IO1
G2_IO3
G4_IO4
Res.
Res.
0
G3E
G2_IO2
G5_IO1
Res.
Res.
0
G4E
G2_IO3
G2_IO4
G5_IO2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
G5E
G1_IO1
0
G1_IO2
0
G1_IO3
0
G1_IO4
0
G2_IO1
0
G2_IO2
0
G2_IO3
Reset value
G3_IO1
G5_IO3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
G6E
0
G7E
0
G2_IO4
0
G2_IO4
0
G8E
0
G3_IO1
0
G3_IO1
0
G3_IO2
0
Res.
0
G3_IO2
0
G3_IO2
0
G3_IO3
0
Res.
0
G3_IO3
0
G3_IO3
0
G3_IO4
0
G4_IO1
0
Res.
0
G3_IO4
0
G4_IO1
0
G4_IO2
0
G4_IO3
0
G3_IO4
0
G4_IO2
Reset value
G4_IO3
0
G4_IO4
0
G5_IO1
0
G4_IO1
0x0024
G4_IO4
0x001C
G5_IO1
Reset value
G5_IO2
G5_IO3
1
G5_IO4
G6_IO1
1
G5_IO2
G5_IO4
G6_IO2
1
G5_IO3
G6_IO1
G6_IO3
1
Res.
G5_IO3
G6_IO2
G6_IO4
1
G5_IO4
G6_IO1
G6_IO3
G7_IO1
1
Res.
G5_IO4
G6_IO2
G6_IO4
G7_IO2
1
G4_IO2
G6_IO1
G6_IO3
G7_IO1
G7_IO3
1
G4_IO3
G6_IO2
G6_IO4
G7_IO2
G7_IO4
1
Res.
G6_IO3
G7_IO1
G7_IO3
G8_IO1
1
Res.
G1S
0
Res.
G6_IO4
G7_IO2
G7_IO4
G8_IO2
1
Res.
G2S
0
Res.
G7_IO1
G7_IO3
G8_IO1
1
G4_IO4
G3S
0
Res.
G7_IO2
G7_IO4
G8_IO2
Reset value
Res.
G4S
0
Res.
G7_IO3
G8_IO1
0
SSD[6:0]
Res.
G5S
0
Res.
G7_IO4
G8_IO2
0x0014
G5_IO1
G6S
0
Res.
G8_IO1
Res.
Res.
0
CTPL[3:0]
G5_IO2
G7S
0
Res.
Res.
Res.
Res.
Res.
G8S
Reset value
Res.
Res.
Res.
TSC_IOGCSR
Res.
0x0030
Res.
0x0000
Reset value
CTPH[3:0]
Res.
G8_IO2
TSC_ISR
Res.
0x000C
Res.
TSC_IOHCR
G8_IO3
0x0010
G8_IO4
TSC_ICR
Res.
TSC_IOASCR
G8_IO3
0x0018
G8_IO4
0x0008
Res.
TSC_IOSCR
G8_IO3
0x0020
G8_IO4
0x0004
Res.
TSC_IOCCR
G8_IO3
0x0028
G8_IO4
TSC_CR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
17.6.11
Res.
RM0376
Touch sensing controller (TSC)
TSC register map
Table 68. TSC register map and reset values
0
0
0
0
0
0
Reserved
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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0x0050
TSC_IOG8CR
Reset value
DocID025941 Rev 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG7CR
Res.
0x004C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG6CR
Res.
0x0048
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG5CR
Res.
0x0044
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG4CR
Res.
0x0040
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG3CR
Res.
0x003C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG2CR
Res.
0x0038
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
Touch sensing controller (TSC)
RM0376
Table 68. TSC register map and reset values (continued)
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
CNT[13:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2.2 for the register boundary addresses.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNT[13:0]
0
CNT[13:0]
0
CNT[13:0]
0
CNT[13:0]
0
CNT[13:0]
0
CNT[13:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0376
18
Advanced encryption standard hardware accelerator (AES)
Advanced encryption standard hardware accelerator
(AES)
The AES is only available on Cat. 2 with AES microcontrollers.
18.1
Introduction
The AES hardware accelerator can be used to both encipher and decipher data using AES
algorithm. It is a fully compliant implementation of the following standard:
•
The advanced encryption standard (AES) as defined by Federal Information
Processing Standards Publication (FIPS PUB 197, 2001 November 26)
The accelerator encrypts and decrypts 128-bit blocks using 128-bit key length. It can also
perform key derivation. The encryption or decryption key is stored in an internal register in
order to minimize write operations by the CPU or DMA when processing several data blocks
using the same key.
By default, Electronic CodebBook mode (ECB) is selected. Cipher block chaining (CBC) or
Counter (CTR) mode) chaining algorithms are also supported by the hardware.
The AES supports DMA transfer for incoming and for outcoming data (2 DMA channels
required).
18.2
AES main features
•
Encryption/Decryption using AES Rijndael Block Cipher algorithm
•
NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm
•
Internal 128-bit register for storing the encryption or derivation key (4x 32-bit registers)
•
Electronic codebook (ECB), Cipher block chaining (CBC), and Counter mode (CTR)
supported
•
Key scheduler
•
Key derivation for decryption
•
128-bit data block processing
•
128-bit key length
•
213 clock cycles to encrypt or decrypt one 128-bit block (including the input and output
phases)
•
1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer.
•
Register access supporting 32-bit data width only.
•
One 128-bit Register for the initialization vector when AES is configured in CBC mode
or for the 32-bit counter initialization when CTR mode is selected.
•
Automatic data flow control with support of direct memory access (DMA) using 2
channels, one for incoming data, and one for outcoming data.
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18.3
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AES functional description
Figure 67 shows the block diagram of the AES accelerator.
Figure 67. Block diagram
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The AES accelerator processes data blocks of 128-bits (4 words) using a key with a length
of 128 bits, and an initialization vector when CBC or CTR chaining mode is selected.
It provides 4 operating modes:
•
Mode 1: Encryption using the encryption key stored in the AES_KEYRx registers.
•
Mode 2: Key Derivation stored internally in the AES_KEYRx registers at the end of the
key derivation processed from the encryption key stored in this register before enabling
the AES. This mode is independent from the AES chaining mode selection.
•
Mode 3: Decryption using a given (precomputed) decryption key stored in the
AES_KEYRx registers.
•
Mode 4: Key Derivation + Decryption using an encryption key stored in the
AES_KEYRx registers (not used when the AES is configured in Counter mode for
perform a chaining algorithm).
The operating mode is selected by programming bits MODE[1:0] into the AES_CR register.
The mode must be changed only when the AES is disabled (bit EN=0 in the AES_CR
register). The KEY registers (AES_KEYRx) must be stored before enabling the AES.
To select which one of the ECB, CBC or CTR mode is going to be used for the cryptographic
solution, it is mandatory to write the bit CHMOD[1:0] of the AES_CR register and the
AES_IVR register (only used for the CBC and CTR chaining modes) when the AES is
disabled (bit EN =0 in the AES_CR register).
Once enabled (bit EN=1), the AES is in the input phase, waiting for the software to write the
input data words into the AES_DINR (4 words) for the modes 1, 3 or 4. The data
corresponds either to the plaintext message or the cipher message. A wait cycle is
automatically inserted between two consecutive writes to the AES_DINR register in order to
send, interleaved with the data, the key to the AES processor.
For mode 2, the key derivation processing is started immediately after the EN bit in the
AES_CR register is set. It requires that the AES_KEYRx registers are loaded with the
encrypted KEY before enabling the AES. At the end of the Key derivation processing (CCF
flag is set), the derivative key is available in the AES_KEYRx registers and the AES is
disabled by hardware. In this mode, the AES_KEYRx registers must not be read when AES
is enabled and until the CCF flag is set to 1 by hardware.
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Advanced encryption standard hardware accelerator (AES)
The status flag CCF (Computation Complete Flag) in the AES_SR register is set once the
computation phase is complete. An interrupt can be generated if bit CCFIE=1 in the
AES_CR register. The software can then read back the data from the AES_DOUTR register
(for modes 1, 3, 4) or from the AES_KEYRx registers (if mode 2 is selected).
The flag CCF has no meaning when DMAOUTEN = 1 in the AES_CR register, because the
reading the AES_DOUTR register is managed by DMA automatically without any software
action at the end of the computation phase.
The operation ends with the output phase, during which the software reads successively the
4 output data words from the AES_DOUTR register in mode 1, 3 or 4. In mode 2 (key
derivation mode), the data is automatically stored in the AES_KEYRx registers and the AES
is disabled by hardware. Then, software can select mode 3 (decryption mode) before it
enables the AES to start the decryption using this derivative key.
During the input and output phases, the software must read or write the data bytes
successively (except in mode 2) but the AES is tolerant of any delays occurring between
each read or write operation (example: if servicing another interrupt at this time).
The RDERR and WRERR flags in the AES_SR register are set when an unexpected read or
write operation is detected. An interrupt can be generated if the ERRIE bit is set in the
AES_CR register. AES is not disabled after an error detection and continues processing as
normal.
It is also possible to use the general purpose DMA to write the input words and to read the
output words (refer to Figure 82 and Figure 83).
The AES can be re-initialized at any moment by resetting the EN bit in the AES_CR register.
Then the AES can be re-started from the beginning by setting EN=1, waiting for the first
input data byte to be written (except in mode 2 where Key derivation processing starts as
soon as the EN bit is set, starting from the value stored in the AES_KEYRx registers).
18.4
Encryption and derivation keys
The AES_KEYRx registers are used to store the encryption or decryption keys. These four
registers are organized in little-endian configuration: Register AES_KEYR0 has to be
loaded with the 32-bit LSB of the key. Consequently, AES_KEYR3 has to be loaded with the
32-bit MSB of the 128-bit key.
The key for encryption or decryption must be stored in these registers when the AES is
disabled (EN = 0 into the AES_CR register). Their endianess are fixed.
In mode 2 (key derivation), the AES_KEYRx needs to be loaded with the encryption key.
Then, the AES has to be enabled. At the end of the computation phase, the derivation key is
stored automatically in the AES_KEYRx registers, overwriting the previous encryption key.
The AES is disabled by hardware when the derivation key is available. If the software needs
to switch the AES to mode 3 (decryption mode), there is no need to write the AES_KEYRx
registers if their content corresponds to the derivation key (previously computed by mode 2).
In mode 4 (key derivation + decryption), the AES_KEYRx registers contain only the
encryption key. The derivation key is calculated internally without any write to these
registers.
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18.5
RM0376
AES chaining algorithms
Three algorithms are supported by the AES hardware and can be selected through the
CHMOD[1:0] bits in the AES_CR register when the AES is disabled (bit EN = 0):
18.5.1
•
Electronic CodeBook (ECB)
•
Cipher Block Chaining (CBC)
•
Counter Mode (CTR)
Electronic CodeBook (ECB)
This is the default mode. This mode doesn’t use the AES_IVR register. There are no
chaining operations. The message is divided into blocks and each block is encrypted
separately.
Figure 68 and Figure 69 describe the principle of the Electronic Codebook algorithm for
encryption and decryption respectively.
Figure 68. ECB encryption mode
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Advanced encryption standard hardware accelerator (AES)
Figure 69. ECB decryption mode
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18.5.2
Cipher block chaining (CBC)
In cipher-block chaining (CBC) mode, each block of plain text is XORed with the previous
cipher text block before being encrypted. To make each message unique, an initialization
vector (AES_IVRx) is used during the first block processing.
The initialization vector is XORed after the swapping management block in during
encryption mode and before it in decryption mode (refer to Figure 70 and Figure 71).
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Figure 70. CBC mode encryption
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Figure 71. CBC mode decryption
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Note:
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When the AES is enabled, reading the AES_IVR returns the value 0x00000000.
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Advanced encryption standard hardware accelerator (AES)
Suspended mode for a given message
It is possible to suspend a message if another message with a higher priority needs to be
processed. At the end of sending of this highest priority message, the suspended message
may be resumed in both encryption or decryption mode. This feature is available only when
the data transfer is done by CPU accesses to the AES_DOUTR and AES_DINR registers. It
is advised to not use it when the DMA controller is managing the data transfer.
For correct operation, the message must be suspended at the end of processing a block
(after the fourth read of the AES_DOUTR register and before the next AES_DINR write
access corresponding to the input of the next block to be processed).
The AES should be disabled writing bit EN = 0 in the AES_CR register. The software has to
read the AES_IVRx which contains the latest value to be used for the chaining XOR
operation before message interruption. This value has to be stored for reuse by writing the
AES_IVRx registers as soon as the interrupted message has to be resumed (when AES is
disabled). It should be noted that this does not break the chaining operation and the
message processing can be resumed as soon as the AES is enabled again to send the next
128-bit data block.
This behavior is valid whatever the AES configuration (encryption or decryption mode).
Figure 72 gives an example of a message 1 which is suspended in order to send a higher
priority message 2, shorter than message 1. At the end of the 128-bit block processing, AES
is disabled. The AES_IVR register is read back to store the value to be retrieved later on
when the message is resumed, in order not to break the chaining operation. Then, the AES
is configured to send message 2 and it is enabled to start processing. At the end of
message 2 processing, AES has to be disabled again and the AES_IVRx registers have to
be loaded with the value previously stored when the message 1 was interrupted. Then
software has to restart from the input value corresponding to block 4 as soon as AES is
enabled to resume message 1.
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Figure 72. Example of suspend mode management
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18.5.3
Counter Mode (CTR)
In counter mode, a 32-bit counter is used in addition to a nonce value for the XOR operation
with the cipher text or plain text (refer to Figure 73 and Figure 74).
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Advanced encryption standard hardware accelerator (AES)
Figure 73. CTR mode encryption
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Figure 74. CTR mode decryption
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The nonce value and 32-bit counter are accessible through the AES_IVRx register and
organized like below in Figure 75:
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Figure 75. 32-bit counter + nonce organization
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In Counter Mode, the counter is incremented from the initialized value for each block to be
processed in order to guarantee a unique sequence which is not repeated for a long time. It
is a 32-bit counter, meaning that the nonce message is kept to the initialized value stored
when the AES was disabled. Only the 32-bit LSB of the 128-bit initialization vector register
represents the counter. In contrast to CBC mode (which uses the AES_IVRx registers only
once when processing the first data block), in Counter mode, the AES_IVRx registers are
used for processing each data block.
In counter mode, key derivation+decryption mode is not applicable.
Note:
The AES_IVRx register has be written only when the AES is disabled (bit EN = 0) to
guarantee good AES behavior.
Reading it while AES is enabled returns the value 0x00000000.
Reading it while the AES is disabled returns the latest counter value (useful for managing
suspend mode).
In CTR mode, key derivation + decryption serves no purpose. Consequently it is forbidden
to set MODE[1:0] = 11 in the AES_CR register and any attempt to set this configuration is
forced to MODE[1:0] = 10 (which corresponds to CTR mode decryption). This uses the
encryption block of the AES processor to decipher the message as shown in Figure 74).
Suspend mode in CTR mode
Like for the CBC mode, it is possible to interrupt a message, sending a higher priority
message and resume the message which was interrupted. Refer to the Figure 72 and
Chapter 18.5.2 for more details about the suspend mode capability.
18.6
Data type
Data are entered in the AES processor 32 bits at a time (words), by writing them in the
AES_DINR register. AES handles 128-bit data blocks. The AES_DINR or AES_DOUTR
registers must be read or written four times to handle one 128-bit data block with the MSB
first.
The system memory organization is little-endian: whatever the data type (bit, byte, 16-bit
half-word, 32-bit word) used, the less-significant data occupies the lowest address location.
Thus, there must be a bit, byte, or half-word swapping operation to be performed on data to
be written in the AES_DINR from system memory before entering the AES processor, and
the same swapping must be performed for AES data to be read from the AES_DOUTR
register to the system memory, depending on to the kind of data to be encrypted or
decrypted.
The DATATYPE bits in the AES_CR register offer different swap modes to be applied to the
AES_DINR register before sending it to the AES processor and to be applied on the
AES_DOUTR register on the data coming out from the processor (refer to Figure 76).
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Note:
Advanced encryption standard hardware accelerator (AES)
The swapping operation concerns only the AES_DOUTR and AES_DINR registers. The
AES_KEYRx and AES_IVRx registers are not sensitive to the swap mode selected. They
have a fixed little-endian configuration (refer to Section 18.4 and Section 18.12).
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Figure 76. 128-bit block construction according to the data type
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Figure 77. 128-bit block construction according to the data type (continued)
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18.7
Operating modes
18.7.1
Mode 1: encryption
1.
Disable the AES by resetting bit the EN bit in the AES_CR register.
2.
Configure the Mode 1 by programming MODE[1:0]=00 in the AES_CR register and
select which type of chaining mode needs to be performed by programming the
CHMOD[1:0] bits.
3.
Write the AES_KEYRx registers (128-bit encryption key) and the AES_IVRx registers if
CTR or CBC mode is selected. For EBC mode, the AES_IVRx register is not used.
4.
Enable the AES by setting the EN bit in the AES_CR register.
5.
Write the AES_DINR register 4 times to input the plain text (MSB first) as shown in
Figure 78: Mode 1: encryption on page 367.
6.
Wait until the CCF flag is set in the AES_SR register.
7.
Reads the AES_DOUTR register 4 times to get the cipher text (MSB first) as shown in
Figure 78: Mode 1: encryption on page 367.
8.
Repeat steps 5,6,7 to process all the blocks with the same encryption key.
Figure 78. Mode 1: encryption
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18.7.2
RM0376
Mode 2: key derivation
1.
Disable the AES by resetting the EN bit in the AES_CR register.
2.
Configure Mode 2 by programming MODE[1:0]=01 in the AES_CR register. Note that
the CHMOD[1:0] bits are not significant in this case because this key derivation mode
is independent from the chaining algorithm selected.
3.
Write the AES_KEYRx registers with the encryption key to obtain the derivative key. A
write to the AES_IVRx has no effect.
4.
Enable the AES by setting the EN bit in the AES_CR register.
5.
Wait until the CCF flag is set in the AES_SR register.
6.
The derivation key is put automatically into the AES_KEYRx registers. Read the
AES_KEYRx register to obtain the decryption key if needed. The AES is disabled by
hardware. To restart a derivation key calculation, repeat steps 3, 4, 5 and 6.
Figure 79. Mode 2: key derivation
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Mode 3: decryption
1.
Disable the AES by resetting the EN bit in the AES_CR register.
2.
Configure Mode 3 by programming MODE[1:0] =10 in the AES_CR register and select
which type of chaining mode needs to be performed by programming the CHMOD[1:0]
bits.
3.
Write the AES_KEYRx registers with the decryption key (this step can be bypassed if
the derivation key is already stored in the AES_KEYRx registers using mode 2: key
derivation). Write the AES_IVRx registers if CTR or CBC mode is selected. For EBC
mode, the AES_IVRx registers are not used.
4.
Enable the AES by setting the EN bit in the AES_CR register.
5.
Write the AES_DINR register 4 times to input the cipher text (MSB first) as shown in
Figure 80: Mode 3: decryption on page 369.
6.
Wait until the CCF flag is set in the AES_SR register.
7.
Read the AES_DOUTR register 4 times to get the plain text (MSB first) as shown in
Figure 80: Mode 3: decryption on page 369.
8.
Repeat steps 5, 6, 7 to process all the blocks using the same derivation key stored in
the AES_KEYRx registers.
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Advanced encryption standard hardware accelerator (AES)
Figure 80. Mode 3: decryption
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Mode 4: key derivation and decryption
1.
Disable the AES by resetting the EN bit in the AES_CR register.
2.
Configure Mode 4 by programming MODE[1:0]=11 in the AES_CR register. This mode
is forbidden when AES is configured in CTR mode. It will be forced to CTR decryption
mode if the software writes MODE[1:0] = 11 and CHMOD[1:0] = 10.
3.
Write the AES_KEYRx register with the encryption key. Write the AES_IVRx register if
the CBC mode is selected.
4.
Enable the AES by setting the EN bit in the AES_CR register.
5.
Write the AES_DINR register 4 times to input the cipher text (MSB first) as shown in
Figure 81: Mode 4: key derivation and decryption on page 369.
6.
Wait until the CCF flag is set in the AES_SR register.
7.
Read the AES_DOUTR register 4 times to get the plain text (MSB first) as shown in
Figure 81: Mode 4: key derivation and decryption on page 369.
8.
Repeat steps 5, 6, 7 to process all the blocks with the same encryption key
The AES_KEYRx registers contain the encryption key during all phases of the processing,
No derivation key is stored in these registers. The derivation key starting from the encryption
key is stored internally in the AES without storing a copy in the AES_KEYRx registers.
Figure 81. Mode 4: key derivation and decryption
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-36
AES DMA interface
The AES accelerator provides an interface to connect to the DMA controller.
The DMA must be configured to transfer words.
The AES can be associated with two distinct DMA request channels:
•
A DMA request channel for the inputs: When the DMAINEN bit is set in the AES_CR
register, the AES initiates a DMA request (AES_IN) during the INPUT phase each time
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Advanced encryption standard hardware accelerator (AES)
RM0376
it requires a word to be written to the AES_DINR register. The DMA channel must be
configured in memory-to-peripheral mode with 32-bit data size.
•
A DMA request channel for the outputs: When the DMAOUTEN bit is enabled, the AES
initiates a DMA request (AES_OUT) during the OUTPUT phase each time it requires a
word to be read from the AES_DOUTR register. The DMA channel must be configured
in peripheral-to-memory mode with a data size equal to 32-bit.
Four DMA requests are asserted for each phase, these are described in Figure 82 and
Figure 83.
DMA requests are generated until the AES is disabled. So, after the data output phase at
the end of processing a 128-bit data block, the AES switches automatically to a new data
input phase for the next data block if any.
Note:
For mode 2 (key derivation), access to the AES_KEYRx registers can be done by software
using the CPU. No DMA channel is provided for this purpose. Consequently, the DMAINEN
bit and DMAOUTEN bits in the AES_CR register have no effect during this mode.
The CCF flag is not relevant when DMAOUTEN = 1 and software does not need to read it in
this case. This bit may stay high and has to be cleared by software if the application needs
to disable the AES to cancel the DMA management and use CPU access for the data input
or data output phase.
Figure 82. DMA requests and data transfers during Input phase (AES_IN)
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Figure 83. DMA requests during Output phase (AES_OUT)
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-36
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18.9
Advanced encryption standard hardware accelerator (AES)
Error flags
The RDERR flag in the AES_SR register is set when an unexpected read operation is
detected during the computation phase or during the input phase.
The WRERR flag in the AES_SR register is set when an unexpected write operation is
detected during the output phase or during the computation phase.
The flags may be cleared setting the respective bit in the AES_CR register (CCFC bit to
clear the CCF flag, ERRC bit to clear the WERR and RDERR flags).
An interrupt can be generated when one of the error flags is set if the ERRIE bit in the
AES_CR register has been previously set.
If an error is detected, AES is not disabled by hardware and continues processing as
normal.
18.10
Processing time
The table summarizes the time required to process a 128-bit block for each mode of
operation.
Table 69. Processing time (in clock cycle)
Input phase
Computation
phase
Mode 1: Encryption
8
202
4
214
Mode 2: Key derivation
-
80
-
80
Mode 3: Decryption
8
202
4
214
Mode 4: Key derivation + decryption
8
276
4
288
Mode of operation
18.11
Output
phase
Total
AES interrupts
Table 70. AES interrupt requests
Event flag
Enable
control bit
Exit from
Wait
CCF
CCFIE
yes
AES read error flag
RDERR
ERRIE
yes
AES write error flag
WRERR
ERRIE
yes
Interrupt event
AES computation completed flag
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18.12
AES registers
18.12.1
AES control register (AES_CR)
RM0376
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ERRIE
CCFIE
ERRC
CCFC
rw
rw
rw
rw
DMAO DMAI
UTEN NEN
Reserved
r
r
r
rw
rw
CHMOD[1:0]
MODE[1:0]
rw
rw
rw
rw
DATATYPE[1:0]
rw
rw
EN
rw
Bit 31:13 Reserved, read as 0
Bit 12 DMAOUTEN: Enable DMA management of data output phase
0: DMA (during data output phase) disabled
1: DMA (during data output phase) enabled
If the DMAOUTEN bit is set, DMA requests are generated for the output data phase in mode 1, 3 or
4. This bit has no effect in mode 2 (Key derivation).
Bit 11 DMAINEN: Enable DMA management of data input phase
0: DMA (during data input phase) disabled
1: DMA (during data input phase) enabled
If the DMAINEN bit is set, DMA requests are generated for the data input phase in mode 1, 3 or 4.
This bit has no action in mode 2 (Key Derivation).
Bit 10 ERRIE: Error interrupt enable
An interrupt is generated if at least one of the both flags RDERR or WRERR is set.
0: Error interrupt disabled
1: Error interrupt enabled
Bit 9 CCFIE: CCF flag interrupt enable
An interrupt is generated if the CCF flag is set.
0: CCF interrupt disabled
1: CCF interrupt enabled
Bit 8 ERRC: Error clear
Writing 1 to this bit clears the RDERR and WRERR flags.
This bit is always read low.
Bit 7 CCFC: Computation Complete Flag Clear
Writing 1 to this bit clears the CCF flag.
This bit is always read low.
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Advanced encryption standard hardware accelerator (AES)
Bits 6:5 CHMOD[1:0]: AES chaining mode
00: Electronic codebook (EBC)
01: Cipher-Block Chaining (CBC)
10: Counter Mode (CTR)
11: Reserved.
The AES chaining mode must only be changed while the AES is disabled. Writing these bits while
the AES is enabled is forbidden to avoid unpredictable AES behavior.
Bits 4:3 MODE[1:0]: AES operating mode
00: Mode 1: Encryption
01: Mode 2: Key derivation
10: Mode 3: Decryption
11: Mode 4: Key derivation + decryption
The operation mode must only be changed if the AES is disabled. Writing these bits while the AES is
enabled is forbidden to avoid unpredictable AES behavior.
Mode 4 is forbidden if CTR mode is selected. It will be forced to Mode 3 if the software,
nevertheless, attempts to set mode 4 for this CTR mode configuration.
Bits 2:1 DATATYPE[1:0]: Data type selection (for data in and data out to/from the cryptographic block)
00: 32-bit data. No swapping.
01: 16-bit data or half-word. In the word, each half-word is swapped. For example, if one of the four
32-bit data written in the AES_DINR register is 0x764356AB, the value given to the cryptographic
block is 0x56AB7643
10: 8-bit data or bytes. In the word, all the bytes are swapped. For example, if one of the four 32-bit
data written in the AES_DINR register is 0x764356AB, the value given to the cryptographic block is
0xAB564376.
11: Bit data. In the word all the bits are swapped. For example, if one of the four 32-bit data written in
the AES_DINR register is 0x764356AB, the value given to the cryptographic block is 0xD56AC26E
The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is
enabled is forbidden to avoid unpredictable AES behavior.
Bits 0 EN: AES enable
0: AES disable
1: AES enable
The AES can be re-initialized at any moment by resetting this bit: the AES is then ready to start
processing a new block when EN is set.
This bit is cleared by hardware when the AES computation is finished in mode 2 (Key derivation)
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18.12.2
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AES status register (AES_SR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
r
r
r
r
r
r
r
WRERR RDERR
r
r
r
r
r
r
r
r
CCF
r
Bits 31:3 Reserved, read as 0
Bit 2 WRERR: Write error flag
This bit is set by hardware when an unexpected write operation to the AES_DINR register is
detected (during computation or data output phase). An interrupt is generated if the ERRIE bit has
been previously set in the AES_CR register. This flag has no impact on the AES which continues
running if even if WERR is set.
It is cleared by software by setting the ERRC bit in the AES_CR register.
0: No write error detected
1: Write error detected
Bit 1 RDERR: Read error flag
This bit is set by hardware when an unexpected read operation from the AES_DOUTR register is
detected (during computation or data input phase). An interrupt is generated if the ERRIE bit has
been previously set in the AES_CR register.This flag has no impact on the AES which continues
running if even if RDERR is set.
It is cleared by software by setting the ERRC bit i in the AES_CR register.
0: No read error detected
1: Read error detected
Bit 0 CCF: Computation complete flag
This bit is set by hardware when the computation is complete. An interrupt is generated if the CCFIE
bit has been previously set in the AES_CR register.
It is cleared by software by setting the CCFC bit in the AES_CR register.
0: Computation complete
1: Computation is not complete
Note: This bit is significant only when DMAOUTEN = 0. It may stay high when DMA_EN = 1.
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Advanced encryption standard hardware accelerator (AES)
18.12.3
AES data input register (AES_DINR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DINR[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
DINR[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 DINR[31:0]: Data Input Register.
This register must be written 4 times during the input phase:
– In Mode 1 (Encryption), 4 words must be written which represent the plain text from MSB to LSB.
– In Mode 2 (Key Derivation), This register is not used because this mode concerns only derivative
key calculation starting from the AES_KEYRx register.
– In Mode 3 (Decryption) and 4 (Key Derivation+Decryption), 4 words must be written which represent
the cipher text MSB to LSB.
Note: This register must be accessed with 32-bit data width.
18.12.4
AES data output register (AES_DOUTR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DOUTR[31:16]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
DOUTR[15:0]
r
r
r
r
r
r
r
r
r
Bits 31:0 DOUTR[31:0]: Data output register
This register is read only.
Once the CCF flag (Computation Complete Flag) is set, reading this data register 4 times gives
access to the 128-bit output results:
- In Mode 1 (Encryption), the 4 words read represent the cipher text from MSB to LSB.
- In Mode 2 (Key Derivation), there is no need to read this register because the derivative key is
located in the AES_KEYRx registers.
- In Mode 3 (Decryption) and Mode 4 (Key Derivation+Decryption), the 4 words read represent the
plain text from MSB to LSB.
Note: This register must be accessed with 32-bit data width.
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18.12.5
RM0376
AES key register 0(AES_KEYR0) (LSB: key [31:0])
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
KEYR0[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
KEYR0[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 KEYR0[31:0]: Data Output Register (LSB key [31:0])
This register must be written before the EN bit in the AES_CR register is set:
In Mode 1 (Encryption), mode 2 (Key Derivation) and mode 4 (Key Derivation + Decryption), the
value to be written represents the encryption key from LSB, meaning Key [31:0].
In Mode 3 (Decryption), the value to be written represents the decryption key from LSB, meaning
Key [31:0]. When the register is written with the encryption key in this decryption mode, reading it
before the AES is enabled will return the encryption value. Reading it after CCF flag is set will return
the derivation key.
Reading this register while AES is enabled return an unpredictable value.
Note: This register does not contain the derivation key in mode 4 (derivation key + decryption). It
always contains the encryption key value.
18.12.6
AES key register 1 (AES_KEYR1) (Key[63:32])
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
KEYR1[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
KEYR1[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 KEYR1[31:0]: AES key register (key [63:32])
Refer to the description of AES_KEYR0.
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18.12.7
Advanced encryption standard hardware accelerator (AES)
AES key register 2 (AES_KEYR2) (Key [95:64])
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
KEYR2[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
KEYR2[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 KEYR2[31:0]: AES key register (key [95:64])
Refer to the description of AES_KEYR0.
18.12.8
AES key register 3 (AES_KEYR3) (MSB: key[127:96])
Address offset: 0x1C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
KEYR3[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
KEYR3[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 KEYR3[31:0]: AES key register (MSB key [127:96])
Refer to the description of AES_KEYR0.
18.12.9
AES initialization vector register 0 (AES_IVR0) (LSB: IVR[31:0])
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IVR0[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
IVR0[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
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Bits 31:0 IVR0[31:0]: initialization vector register (LSB IVR [31:0])
This register must be written before the EN bit in the AES_CR register is set:
The register value has no meaning if:
- The EBC mode (Electronic codebook) is selected.
- The CTR or CBC mode is selected in addition with the Key derivation.
In CTR mode (Counter mode), this register contains the 32-bit counter value.
Reading this register while AES is enabled will return the value 0x00000000.
18.12.10 AES initialization vector register 1 (AES_IVR1) (IVR[63:32])
Address offset: 0x24
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IVR1[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
IVR1[15:0]
rw
rw
Bits 31:0
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rw
rw
rw
rw
rw
rw
rw
IVR1[31:0]: Initialization Vector Register (IVR [63:32])
This register must be written before the EN bit in the AES_CR register is set:
The register value has no meaning if:
- The EBC mode (Electronic codebook) is selected.
- The CTR or CBC mode is selected in addition with the Key derivation or key
derivation+decryption mode.
In CTR mode (Counter mode), this register contains the nonce value.
Reading this register while AES is enabled will return the value 0x00000000.
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Advanced encryption standard hardware accelerator (AES)
18.12.11 AES initialization vector register 2 (AES_IVR2) (IVR[95:64])
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IVR2[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
IVR2[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 IVR2[31:0]: Initialization Vector Register (IVR [95:64])
This register must be written before the EN bit in the AES_CR register is set:
The register value has no meaning if:
- The EBC mode (Electronic codebook) is selected.
- The CTR or CBC mode is selected in addition with the Key derivation or key derivation+decryption
mode.
In CTR mode (Counter mode), this register contains the nonce value.
Reading this register while AES is enabled will return the value 0x00000000.
18.12.12 AES initialization vector register 3 (AES_IVR3) (MSB: IVR[127:96])
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IVR3[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
IVR3[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 IVR3[31:0]: Initialization Vector Register (MSB IVR [127:96])
This register must be written before the EN bit in the AES_CR register is set:
The register value has no meaning if:
- The EBC mode (Electronic codebook) is selected.
- The CTR or CBC mode is selected in addition with the Key derivation or key derivation+decryption
mode.
In CTR mode (Counter mode), this register contains the nonce value.
Reading this register while AES is enabled will return the value 0x00000000.
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18.12.13 AES register map
ERRC
CCFC
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x0008
0x000C
0x0010
0x0014
0x0018
AES_DINR
Reset value
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RDERR
CCF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AES_KEYR1[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AES_KEYR2[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AES_KEYR3[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AES_IVR0[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AES_IVR1[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AES_IVR2[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AES_IVR3
0
0
0
0
AES_IVR3[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2.2 for the register boundary addresses.
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0
AES_KEYR0[31:0]
AES_IVR2
Reset value
0
AES_DOUTR[31:0]
AES_IVR1
Reset value
0x002C
0
AES_IVR0
Reset value
0x0028
0
AES_KEYR3
Reset value
0x0024
0
AES_KEYR2
Reset value
0x0020
0
AES_KEYR1
Reset value
0x001C
0
AES_KEYR0
Reset value
0
AES_DINR[31:0]
0
AES_DOUTR
Reset value
WRERR
MODE[1:0]
Reset value
EN
CCFIE
0
Res.
DATATYPE[1:0]
ERRIE
0
CHMOD[1:0]
DMAINEN
0
Res.
Res.
DMAOUTEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AES_SR
Res.
0x0004
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
AES_CR
Res.
0x0000
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 71. AES register map
DocID025941 Rev 1
RM0376
Random number generator (RNG)
19
Random number generator (RNG)
19.1
Introduction
The RNG processor is a random number generator, based on a continuous analog noise,
that provides a random 32-bit value to the host when read.
The RNG passed the FIPS PUB 140-2 (2001 October 10) tests with a success ratio of 99%.
19.2
19.3
RNG main features
•
It delivers 32-bit random numbers, produced by an analog generator
•
40 periods of the PLL48CLK clock signal between two consecutive random numbers
•
Monitoring of the RNG entropy to flag abnormal behavior (generation of stable values,
or of a stable sequence of values)
•
It can be disabled to reduce power consumption
RNG functional description
Figure 84 shows the RNG block diagram.
Figure 84. Block diagram
BIT!("BUS
DATAREGISTER
#ONTROLREGISTER
2.'?$2
2.' ?#2
,&32
2.'?#,+
3TATUSREGISTER
2.' ?32
#LOCKCHECKER
FAULTDETECTOR
FEEDA,INEAR&EEDBACK
3HIFT2EGISTER
!NALOGSEED
AI
The random number generator implements an analog circuit. This circuit generates seeds
that feed a linear feedback shift register (RNG_LFSR) in order to produce 32-bit random
numbers.
The analog circuit is made of several ring oscillators whose outputs are XORed to generate
the seeds. The RNG_LFSR is clocked by a dedicated clock (PLL48CLK) at a constant
frequency, so that the quality of the random number is independent of the HCLK frequency.
The contents of the RNG_LFSR are transferred into the data register (RNG_DR) when a
significant number of seeds have been introduced into the RNG_LFSR.
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Random number generator (RNG)
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In parallel, the analog seed and the dedicated PLL48CLK clock are monitored. Status bits
(in the RNG_SR register) indicate when an abnormal sequence occurs on the seed or when
the frequency of the PLL48CLK clock is too low. An interrupt can be generated when an
error is detected.
19.3.1
Operation
To run the RNG, follow the steps below:
1.
Enable the interrupt if needed (to do so, set the IE bit in the RNG_CR register). An
interrupt is generated when a random number is ready or when an error occurs.
2.
Enable the random number generation by setting the RNGEN bit in the RNG_CR
register. This activates the analog part, the RNG_LFSR and the error detector.
3.
At each interrupt, check that no error occurred (the SEIS and CEIS bits should be ‘0’ in
the RNG_SR register) and that a random number is ready (the DRDY bit is ‘1’ in the
RNG_SR register). The contents of the RNG_DR register can then be read.
As required by the FIPS PUB (Federal Information Processing Standard Publication) 140-2,
the first random number generated after setting the RNGEN bit should not be used, but
saved for comparison with the next generated random number. Each subsequent generated
random number has to be compared with the previously generated number. The test fails if
any two compared numbers are equal (continuous random number generator test).
19.3.2
Error management
If the CEIS bit is read as ‘1’ (clock error)
In the case of a clock, the RNG is no more able to generate random numbers because the
PLL48CLK clock is not correct. Check that the clock controller is correctly configured to
provide the RNG clock and clear the CEIS bit. The RNG can work when the CECS bit is ‘0’.
The clock error has no impact on the previously generated random numbers, and the
RNG_DR register contents can be used.
If the SEIS bit is read as ‘1’ (seed error)
In the case of a seed error, the generation of random numbers is interrupted for as long as
the SECS bit is ‘1’. If a number is available in the RNG_DR register, it must not be used
because it may not have enough entropy.
What you should do is clear the SEIS bit, then clear and set the RNGEN bit to reinitialize
and restart the RNG.
19.4
RNG registers
The RNG is associated with a control register, a data register and a status register. They
have to be accessed by words (32 bits).
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Random number generator (RNG)
19.4.1
RNG control register (RNG_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
6
5
4
19
18
17
16
1
0
Reserved
15
14
13
12
11
10
9
8
7
Reserved
3
2
IE
RNGEN
rw
rw
Reserved
Bits 31:4 Reserved, must be kept at reset value
Bit 3 IE: Interrupt enable
0: RNG Interrupt is disabled
1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY=1 or SEIS=1 or
CEIS=1 in the RNG_SR register.
Bit 2 RNGEN: Random number generator enable
0: Random number generator is disabled
1: random Number Generator is enabled.
Bits 1:0 Reserved, must be kept at reset value
19.4.2
RNG status register (RNG_SR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
15
14
13
12
11
10
9
8
23
22
21
20
19
4
3
18
17
16
Reserved
Reserved
7
6
5
SEIS
CEIS
rc_w0
rc_w0
Reserved
2
1
0
SECS
CECS
DRDY
r
r
r
Bits 31:3 Reserved, must be kept at reset value
Bit 6 SEIS: Seed error interrupt status
This bit is set at the same time as SECS, it is cleared by writing it to 0.
0: No faulty sequence detected
1: One of the following faulty sequences has been detected:
–
More than 64 consecutive bits at the same value (0 or 1)
–
More than 32 consecutive alternations of 0 and 1 (0101010101...01)
An interrupt is pending if IE = 1 in the RNG_CR register.
Bit 5 CEIS: Clock error interrupt status
This bit is set at the same time as CECS, it is cleared by writing it to 0.
0: The PLL48CLK clock was correctly detected
1: The PLL48CLK was not correctly detected (fPLL48CLK< fHCLK/16)
An interrupt is pending if IE = 1 in the RNG_CR register.
Bits 4:3 Reserved, must be kept at reset value
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Random number generator (RNG)
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Bit 2 SECS: Seed error current status
0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a
faulty sequence was detected and the situation has been recovered.
1: One of the following faulty sequences has been detected:
–
More than 64 consecutive bits at the same value (0 or 1)
–
More than 32 consecutive alternations of 0 and 1 (0101010101...01)
Bit 1 CECS: Clock error current status
0: The PLL48CLK clock has been correctly detected. If the CEIS bit is set, this means that a
clock error was detected and the situation has been recovered
1: The PLL48CLK was not correctly detected (fPLL48CLK< fHCLK/16).
Bit 0 DRDY: Data ready
0: The RNG_DR register is not yet valid, no random data is available
1: The RNG_DR register contains valid random data
Note: An interrupt is pending if IE = 1 in the RNG_CR register.
Once the RNG_DR register has been read, this bit returns to 0 until a new valid value is
computed.
19.4.3
RNG data register (RNG_DR)
Address offset: 0x08
Reset value: 0x0000 0000
The RNG_DR register is a read-only register that delivers a 32-bit random value when read.
After being read, this register delivers a new random value after a maximum time of 40
periods of the PLL48CLK clock. The software must check that the DRDY bit is set before
reading the RNDATA value.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RNDATA
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RNDATA
r
Bits 31:0 RNDATA: Random data
32-bit random data.
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19.4.4
Random number generator (RNG)
RNG register map
Table 72 gives the RNG register map and reset values.
Table 72. RNG register map and reset map
Register size
0x08
RNG_DR
0x0000000
Res.
Res.
Res.
0
Res.
IE
Res.
RNGEN
0
0
SECS
0
Res.
CEIS
Res.
Res.
Res.
Res.
Res.
Res.
SEIS
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x04
RNG_SR
0x0000000
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RNG_CR
0x0000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reset value
Res.
0x00
Register name
Res.
Offset
0
RNDATA[31:0]
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General-purpose timers (TIM2)
RM0376
20
General-purpose timers (TIM2)
20.1
TIM2 introduction
The general-purpose timer consist of a 16-bit auto-reload counter driven by a programmable
prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The timer is completely independent, and do not share any resources. It can be
synchronized together as described in Section 20.3.15.
20.2
TIM2 main features
General-purpose TIMx timer features include:
386/869
•
16-bit (TIM2) up, down, up/down auto-reload counter.
•
16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535.
•
Up to 4 independent channels for:
–
Input capture
–
Output compare
–
PWM generation (Edge- and Center-aligned modes)
–
One-pulse mode output
•
Synchronization circuit to control the timer with external signals and to interconnect
several timers.
•
Interrupt/DMA generation on the following events:
–
Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
–
Trigger event (counter start, stop, initialization or count by internal/external trigger)
–
Input capture
–
Output compare
•
Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
purposes
•
Trigger input for external clock or cycle-by-cycle current management
DocID025941 Rev 1
RM0376
General-purpose timers (TIM2)
Figure 85. General-purpose timer block diagram
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20.3
TIM2 functional description
20.3.1
Time-base unit
The main block of the programmable timer is a 16-bit with its related auto-reload register.
The counter can count up, down or both up and down but also down or both up and down.
The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
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General-purpose timers (TIM2)
RM0376
The time-base unit includes:
•
Counter Register (TIMx_CNT)
•
Prescaler Register (TIMx_PSC):
•
Auto-Reload Register (TIMx_ARR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC
register). It can be changed on the fly as this control register is buffered. The new prescaler
ratio is taken into account at the next update event.
Figure 86 and Figure 20.3.2 give some examples of the counter behavior when the
prescaler ratio is changed on the fly:
Figure 86. Counter timing diagram with prescaler division change from 1 to 2
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General-purpose timers (TIM2)
Figure 87. Counter timing diagram with prescaler division change from 1 to 4
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20.3.2
Counter modes
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
An Update event can be generated at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.
This is to avoid updating the shadow registers while writing new values in the preload
registers. Then no update event occurs until the UDIS bit has been written to 0. However,
the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate
does not change). In addition, if the URS bit (update request selection) in TIMx_CR1
register is set, setting the UG bit generates an update event UEV but without setting the UIF
flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
•
The auto-reload shadow register is updated with the preload value (TIMx_ARR)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
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General-purpose timers (TIM2)
RM0376
Figure 88. Counter timing diagram, internal clock divided by 1
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Figure 89. Counter timing diagram, internal clock divided by 2
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General-purpose timers (TIM2)
Figure 90. Counter timing diagram, internal clock divided by 4
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Figure 91. Counter timing diagram, internal clock divided by N
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General-purpose timers (TIM2)
RM0376
Figure 92. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
preloaded)
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Figure 93. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR
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RM0376
General-purpose timers (TIM2)
Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 94. Counter timing diagram, internal clock divided by 1
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General-purpose timers (TIM2)
RM0376
Figure 95. Counter timing diagram, internal clock divided by 2
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Figure 96. Counter timing diagram, internal clock divided by 4
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Figure 97. Counter timing diagram, internal clock divided by N
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Figure 98. Counter timing diagram, Update event when repetition counter
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Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center
aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,
CMS = "11").
In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupt when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.
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Figure 99. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
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1. Here, center-aligned mode 1 is used (for more details refer to Section 20.4.1: TIMx control register 1
(TIMx_CR1) on page 426).
Figure 100. Counter timing diagram, internal clock divided by 2
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Figure 101. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
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1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 102. Counter timing diagram, internal clock divided by N
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Figure 103. Counter timing diagram, Update event with ARPE=1 (counter underflow)
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Figure 104. Counter timing diagram, Update event with ARPE=1 (counter overflow)
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20.3.3
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Clock selection
The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1: external input pin (TIx)
•
External clock mode2: external trigger input (ETR)
•
Internal trigger inputs (ITRx): using one timer as prescaler for another timer. Refer to :
Using one timer as prescaler for another on page 420 for more details.
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except UG which remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 105 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Figure 105. Control circuit in normal mode, internal clock divided by 1
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External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.
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Figure 106. TI2 external clock connection example
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For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
Note:
1.
Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the
TIMx_CCMR1 register.
2.
Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
The capture prescaler is not used for triggering, so you don’t need to configure it.
3.
Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER
register.
4.
Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
5.
Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register.
6.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.
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Figure 107. Control circuit in external clock mode 1
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External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
Figure 108 gives an overview of the external trigger input block.
Figure 108. External trigger input block
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For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
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1.
As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2.
Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3.
Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4.
Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 109. Control circuit in external clock mode 2
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20.3.4
Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
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Figure 110. Capture/compare channel (example: channel 1 input stage)
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The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Figure 111. Capture/compare channel 1 main circuit
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Figure 112. Output stage of capture/compare channel (channel 1)
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The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
20.3.5
Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to 0 or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
1.
Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
2.
Program the input filter duration you need with respect to the signal you connect to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been
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detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
3.
Select the edge of the active transition on the TI1 channel by writing the CC1P and
CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case).
4.
Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the
TIMx_CCMR1 register).
5.
Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
6.
If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
When an input capture occurs:
•
The TIMx_CCR1 register gets the value of the counter on the active transition.
•
CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
•
An interrupt is generated depending on the CC1IE bit.
•
A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note:
IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.
20.3.6
PWM input mode
This mode is a particular case of input capture mode. The procedure is the same except:
•
Two ICx signals are mapped on the same TIx input.
•
These 2 ICx signals are active on edges with opposite polarity.
•
One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
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1.
Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).
2.
Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge).
3.
Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).
4.
Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
bit to ‘1’ and the CC2NP bit to ’0’(active on falling edge).
5.
Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).
6.
Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
7.
Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register.
Figure 113. PWM input mode timing
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20.3.7
Forced output mode
In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCxREF/OCx) to its active level, you just need to write
101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCxREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
e.g.: CCxP=0 (OCx active high) => OCx is forced to high level.
OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the Output Compare Mode section.
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Output compare mode
This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
•
Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
•
Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
•
Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
•
Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).
Procedure:
1.
Select the counter clock (internal, external, prescaler).
2.
Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3.
Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be
generated.
4.
Select the output mode. For example, you must write OCxM=011, OCxPE=0, CCxP=0
and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not
used, OCx is enabled and active high.
5.
Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 114.
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Figure 114. Output compare mode, toggle on OC1.
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20.3.9
PWM mode
Pulse width modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. You must enable the corresponding preload register by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by the CCxE bit in
the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx≤ TIMx_CNT or TIMx_CNT≤ TIMx_CCRx (depending on the direction
of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be
cleared by an external event through the ETR signal until the next PWM period), the
OCREF signal is asserted only:
•
When the result of the comparison changes, or
•
When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from
the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes
(OCxM=‘110 or ‘111).
This forces the PWM by software while the timer is running.
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The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.
PWM edge-aligned mode
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Section :
Upcounting mode on page 389.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1.
If the compare value is 0 then OCxREF is held at ‘0. Figure 115 shows some edge-aligned
PWM waveforms in an example where TIMx_ARR=8.
Figure 115. Edge-aligned PWM waveforms (ARR=8)
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Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Section :
Downcounting mode on page 393.
In PWM mode 1, the reference signal OCxREF is low as long as TIMx_CNT>TIMx_CCRx
else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload
value in TIMx_ARR, then OCxREF is held at ‘1. 0% PWM is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00 (all the remaining configurations having the same effect on the OCxREF/OCx signals).
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The compare flag is set when the counter counts up, when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
Section : Center-aligned mode (up/down counting) on page 396.
Figure 116 shows some center-aligned PWM waveforms in an example where:
•
TIMx_ARR=8,
•
PWM mode is the PWM mode 1,
•
The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.
Figure 116. Center-aligned PWM waveforms (ARR=8)
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Hints on using center-aligned mode:
•
When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
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in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
•
•
20.3.10
Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
–
The direction is not updated if you write a value in the counter that is greater than
the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was
counting up, it continues to count up.
–
The direction is updated if you write 0 or write the TIMx_ARR value in the counter
but no Update Event UEV is generated.
The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.
One-pulse mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. You select One-pulse mode
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
•
In upcounting: CNT<CCRx≤ ARR (in particular, 0<CCRx),
•
In downcounting: CNT>CCRx.
Figure 117. Example of one-pulse mode.
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For example you may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
•
Map TI2FP2 on TI2 by writing IC2S=01 in the TIMx_CCMR1 register.
•
TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER
register.
•
Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in
the TIMx_SMCR register.
•
TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register
(trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
•
The tDELAY is defined by the value written in the TIMx_CCR1 register.
•
The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1).
•
Let’s say you want to build a waveform with a transition from ‘0 to ‘1 when a compare
match occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload
value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1
register. You can optionally enable the preload registers by writing OC1PE=1 in the
TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to
write the compare value in the TIMx_CCR1 register, the auto-reload value in the
TIMx_ARR register, generate an update by setting the UG bit and wait for external
trigger event on TI2. CC1P is written to ‘0 in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1
register to stop the counter at the next update event (when the counter rolls over from the
auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the
Repetitive Mode is selected.
Particular case: OCx fast enable:
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the
TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
20.3.11
Clearing the OCxREF signal on an external event
1.
The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR
register are cleared to 00.
2.
The external clock mode 2 must be disabled: bit ECE in the TIMx_SMCR register is
cleared to 0.
3.
The external trigger polarity (ETP) and the external trigger filter (ETF) can be
configured according to the application’s needs.
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Figure 118 shows the behavior of the OCxREF signal when the ETRF input becomes high,
for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in
PWM mode.
Figure 118. Clearing TIMx OCxREF
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1. In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter
overflow.
20.3.12
Encoder interface mode
To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter
is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if
it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. CC1NP and CC2NP must be kept cleared. When needed, you can program the
input filter as well.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 73. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must
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configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler,
trigger output features continue to work as normal.
In this mode, the counter is modified automatically following the speed and the direction of
the incremental encoder and its content, therefore, always represents the encoder’s
position. The count direction correspond to the rotation direction of the connected sensor.
The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the
same time.
Table 73. Counting direction versus encoder signals
Level on opposite
signal (TI1FP1 for
TI2, TI2FP2 for TI1)
Rising
Falling
Rising
Falling
Counting on
TI1 only
High
Down
Up
No Count
No Count
Low
Up
Down
No Count
No Count
Counting on
TI2 only
High
No Count
No Count
Up
Down
Low
No Count
No Count
Down
Up
Counting on
TI1 and TI2
High
Down
Up
Up
Down
Low
Up
Down
Down
Up
Active edge
TI1FP1 signal
TI2FP2 signal
An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
Figure 119 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
•
CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1)
•
CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2)
•
CC1P=0, CC1NP = ‘0’ (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1)
•
CC2P=0, CC2NP = ‘0’ (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2)
•
SMS= 011 (TIMx_SMCR register, both inputs are active on both rising and falling
edges)
•
CEN= 1 (TIMx_CR1 register, Counter is enabled)
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Figure 119. Example of counter operation in encoder interface mode
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Figure 120 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=1).
Figure 120. Example of encoder interface mode with TI1FP1 polarity inverted
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The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. You can obtain dynamic information (speed, acceleration, deceleration) by
measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. You can do this by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a Real-Time clock.
20.3.13
Timer input XOR function
The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture.
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General-purpose timers (TIM2)
Timers and external trigger synchronization
The TIMx Timers can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.
Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
•
Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect
rising edges only).
•
Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
•
Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.
Figure 121. Control circuit in reset mode
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Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
1.
Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect low
level only).
2.
Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
3.
Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.
Figure 122. Control circuit in gated mode
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1. The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect
in gated mode because gated mode acts on a level and not on an edge.
Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
1.
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Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. CC2S bits are
selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write
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General-purpose timers (TIM2)
CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low
level only).
2.
Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.
Figure 123. Control circuit in trigger mode
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Slave mode: External Clock mode 2 + trigger mode
The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input when operating in reset mode,
gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS
bits of TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:
1.
2.
3.
Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
–
ETF = 0000: no filter
–
ETPS=00: prescaler disabled
–
ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
Configure the channel 1 as follows, to detect rising edges on TI:
–
IC1F=0000: no filter.
–
The capture prescaler is not used for triggering and does not need to be
configured.
–
CC1S=01in TIMx_CCMR1 register to select only the input capture source
–
CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect
rising edge only).
Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
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A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
Figure 124. Control circuit in external clock mode 2 + trigger mode
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20.3.15
Timer synchronization
The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
Figure 125: Master/Slave timer example presents an overview of the trigger selection and
the master mode selection blocks.
Using one timer as prescaler for another
Figure 125. Master/Slave timer example
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For example, you can configure Timer x to act as a prescaler for Timer y. Refer to
Figure 125. To do this:
Note:
1.
Configure Timer x in master mode so that it outputs a periodic trigger signal on each
update event UEV. If you write MMS=010 in the TIMx_CR2 register, a rising edge is
output on TRGO1 each time an update event is generated.
2.
To connect the TRGO1 output of Timer x to Timer y, Timer y must be configured in
slave mode using ITR1 as internal trigger. You select this through the TS bits in the
TIMy_SMCR register (writing TS=000).
3.
Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the
TIMy_SMCR register). This causes Timer y to be clocked by the rising edge of the
periodic Timer x trigger signal (which correspond to the timer x counter overflow).
4.
Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
If OCx is selected on Timer x as trigger output (MMS=1xx), its rising edge is used to clock
the counter of timer y.
Using one timer to enable another timer
In this example, we control the enable of Timer y with the output compare 1 of Timer x.
Refer to Figure 125 for connections. Timer y counts on the divided internal clock only when
OC1REF of Timer x is high. Both counter clock frequencies are divided by 3 by the
prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
Note:
1.
Configure Timer x master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIMx_CR2 register).
2.
Configure the Timer x OC1REF waveform (TIMx_CCMR1 register).
3.
Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR
register).
4.
Configure Timer y in gated mode (SMS=101 in TIMy_SMCR register).
5.
Enable Timer y by writing ‘1 in the CEN bit (TIMy_CR1 register).
6.
Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register).
The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer y
counter enable signal.
Figure 126. Gating timer y with OC1REF of timer x
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In the example in Figure 126, the Timer y counter and prescaler are not initialized before
being started. So they start counting from their current value. It is possible to start from a
given value by resetting both timers before starting Timer x. You can then write any value
you want in the timer counters. The timers can easily be reset by software using the UG bit
in the TIMx_EGR registers.
In the next example, we synchronize Timer x and Timer y. Timer x is the master and starts
from 0. Timer y is the slave and starts from 0xE7. The prescaler ratio is the same for both
timers. Timer y stops when Timer x is disabled by writing ‘0 to the CEN bit in the TIMy_CR1
register:
1.
Configure Timer x master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIMx_CR2 register).
2.
Configure the Timer x OC1REF waveform (TIMx_CCMR1 register).
3.
Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR
register).
4.
Configure Timer y in gated mode (SMS=101 in TIMy_SMCR register).
5.
Reset Timer x by writing ‘1 in UG bit (TIMx_EGR register).
6.
Reset Timer y by writing ‘1 in UG bit (TIMy_EGR register).
7.
Initialize Timer y to 0xE7 by writing ‘0xE7’ in the timer y counter (TIMy_CNTL).
8.
Enable Timer y by writing ‘1 in the CEN bit (TIMy_CR1 register).
9.
Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register).
10. Stop Timer x by writing ‘0 in the CEN bit (TIMx_CR1 register).
Figure 127. Gating timer y with Enable of timer x
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Using one timer to start another timer
In this example, we set the enable of Timer y with the update event of Timer x. Refer to
Figure 125 for connections. Timer y starts counting from its current value (which can be
nonzero) on the divided internal clock as soon as the update event is generated by Timer x.
When Timer y receives the trigger signal its CEN bit is automatically set and the counter
counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock
frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
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1.
Configure Timer x master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIMx_CR2 register).
2.
Configure the Timer x period (TIMx_ARR registers).
3.
Configure Timer y to get the input trigger from Timer x (TS=000 in the TIM2_SMCR
register).
4.
Configure Timer y in trigger mode (SMS=110 in TIM2_SMCR register).
5.
Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register).
Figure 128. Triggering timer y with update of timer x
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As in the previous example, you can initialize both counters before starting counting.
Figure 129 shows the behavior with the same configuration as in Figure 128 but in trigger
mode instead of gated mode (SMS=110 in the TIMy_SMCR register).
Figure 129. Triggering timer y with Enable of timer x
&.B,17
7,0(5[&(1 &17B(1
7,0(5[&17B,1,7
7,0(5[&17
7,0(5\&17
&'
(
(
(
($
7,0(5\&17B,1,7
7,0(5\
ZULWH&17
7,0(5\7,)
:ULWH7,) 069
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General-purpose timers (TIM2)
RM0376
Using one timer as prescaler for another timer
For example, you can configure Timer x to act as a prescaler for Timer y. Refer to
Figure 125 for connections. To do this:
1.
Configure Timer x master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIMx_CR2 register). then it outputs a periodic signal on each counter
overflow.
2.
Configure the Timer x period (TIMx_ARR registers).
3.
Configure Timer y to get the input trigger from Timer x (TS=000 in the TIM2_SMCR
register).
4.
Configure Timer y in external clock mode 1 (SMS=111 in TIM2_SMCR register).
5.
Start Timer y by writing ‘1 in the CEN bit (TIMy_CR1 register).
6.
Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register).
Starting 2 timers synchronously in response to an external trigger
In this example, we set the enable of timer x when its TI1 input rises, and the enable of
Timer y with the enable of Timer x. Refer to Figure 125 for connections. To ensure the
counters are aligned, Timer x must be configured in Master/Slave mode (slave with respect
to TI1, master with respect to Timer y):
1.
Configure Timer x master mode to send its Enable as trigger output (MMS=001 in the
TIMx_CR2 register).
2.
Configure Timer x slave mode to get the input trigger from TI1 (TS=100 in the
TIMx_SMCR register).
3.
Configure Timer x in trigger mode (SMS=110 in the TIMx_SMCR register).
4.
Configure the Timer x in Master/Slave mode by writing MSM=1 (TIMx_SMCR register).
5.
Configure Timer y to get the input trigger from Timer x (TS=000 in the TIM2_SMCR
register).
6.
Configure Timer y in trigger mode (SMS=110 in the TIM2_SMCR register).
When a rising edge occurs on TI1 (Timer x), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note:
424/869
In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but you can easily insert an offset between them by
writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on timer x.
DocID025941 Rev 1
RM0376
General-purpose timers (TIM2)
Figure 130. Triggering timer x and y with timer x TI1 input
&.B,17
7,0(5[7,
7,0(5[&(1 &17B(1
7,0(5[&.B36&
7,0(5[&17
7,0(5[7,)
7,0(5\&(1 &17B(1
7,0(5\&.B36&
7,0(5\&17
7,0(5\7,)
069
20.3.16
Debug mode
When the microcontroller enters debug mode (Cortex®-M0+ core - halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers,
watchdog, bxCAN and I2C.
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General-purpose timers (TIM2)
20.4
RM0376
TIM2 registers
Refer to Section 1.1 on page 43 for a list of abbreviations used in register descriptions.
The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral
registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be
done by bytes (8 bits), half-words (16 bits) or words (32 bits).
20.4.1
TIMx control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15
14
13
12
11
10
Res.
Res.
Res.
Res.
Res.
Res.
9
8
CKD[1:0]
rw
7
6
ARPE
rw
rw
5
CMS
rw
rw
4
3
2
1
0
DIR
OPM
URS
UDIS
CEN
rw
rw
rw
rw
rw
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (ETR, TIx),
00: tDTS = tCK_INT
01: tDTS = 2 × tCK_INT
10: tDTS = 4 × tCK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
the counter is enabled (CEN=1)
Bit 4 DIR: Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
mode.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
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General-purpose timers (TIM2)
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.
CEN is cleared automatically in one-pulse mode, when an update event occurs.
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General-purpose timers (TIM2)
20.4.2
RM0376
TIMx control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TI1S
rw
6
5
4
MMS[2:0]
rw
rw
rw
3
2
1
0
CCDS
Res.
Res.
Res.
rw
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 TI1S: TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Bits 6:4 MMS: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO)
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bits 2:0 Reserved, must be kept at reset value.
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General-purpose timers (TIM2)
20.4.3
TIMx slave mode control register (TIMx_SMCR)
Address offset: 0x08
Reset value: 0x0000
15
14
ETP
ECE
13
rw
rw
12
11
ETPS[1:0]
rw
rw
10
9
8
ETF[3:0]
rw
rw
7
6
MSM
rw
rw
rw
5
4
TS[2:0]
rw
rw
3
2
Res.
rw
1
0
SMS[2:0]
rw
rw
rw
Bit 15 ETP: External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is noninverted, active at high level or rising edge
1: ETR is inverted, active at low level or falling edge
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI
connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the following slave modes:
reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to
ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the
external clock input is ETRF.
Bits 13:12 ETPS: External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
Bits 11:8 ETF[3:0]: External trigger filter
This bit-field then defines the frequency used to sample ETRP signal and the length of the
digital filter applied to ETRP. The digital filter is made of an event counter in which N events
are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
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Bit 7 MSM: Master/Slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
Bits 6:4 TS: Trigger selection
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0).
001: Internal Trigger 1 (ITR1).
010: Reserved.
011: Reserved.
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See Table 74: TIM2 internal trigger connection on page 430 for more details on ITRx
meaning for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at ‘1’.
Bits 2:0 SMS: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).
Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode
checks the level of the trigger signal.
Table 74. TIM2 internal trigger connection
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Slave TIM
ITR0 (TS = 000)
ITR1 (TS = 001)
TIM2
TIM21
TIM22
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RM0376
General-purpose timers (TIM2)
20.4.4
TIMx DMA/Interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000
15
14
13
Res.
TDE
Res.
rw
12
rw
Bit 15
11
10
9
CC4DE CC3DE CC2DE CC1DE
rw
rw
rw
8
7
6
5
4
3
2
1
0
UDE
Res.
TIE
Res.
CC4IE
CC3IE
CC2IE
CC1IE
UIE
rw
rw
rw
rw
rw
rw
rw
Reserved, must be kept at reset value.
Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
Bit 13
Reserved, always read as 0
Bit 12 CC4DE: Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled.
1: CC4 DMA request enabled.
Bit 11 CC3DE: Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bit 7
Reserved, must be kept at reset value.
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Bit 5
Reserved, must be kept at reset value.
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled.
1: CC4 interrupt enabled.
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled
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Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
20.4.5
TIMx status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
15
14
13
Res.
Res.
Res.
12
10
9
CC4OF CC3OF CC2OF CC1OF
rc_w0
Bit 15:13
11
rc_w0
rc_w0
8
7
Res.
Res.
rc_w0
6
5
4
3
2
1
TIF
Res.
CC4IF
CC3IF
CC2IF
CC1IF
UIF
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
0
Reserved, must be kept at reset value.
Bit 12 CC4OF: Capture/Compare 4 overcapture flag
refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
refer to CC1OF description
Bit 10 CC2OF: Capture/compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7
Reserved, must be kept at reset value.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode. It is set when the counter
starts or stops when gated mode is selected. It is cleared by software.
0: No trigger event occurred
1: Trigger interrupt pending
Bit 5
Reserved, must be kept at reset value.
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
refer to CC1IF description
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General-purpose timers (TIM2)
Bit 2 CC2IF: Capture/Compare 2 interrupt flag
refer to CC1IF description
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register
description). It is cleared by software.
0: No match
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit
goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow
(in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected
on IC1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
″
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
″
At overflow or underflow and if UDIS=0 in the TIMx_CR1 register.
″
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by a trigger event (refer to the synchro control register description),
if URS=0 and UDIS=0 in the TIMx_CR1 register.
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20.4.6
RM0376
TIMx event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TG
Res.
CC4G
CC3G
CC2G
CC1G
UG
w
w
w
w
w
w
Bits 15:7 Reserved, must be kept at reset value.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4G: Capture/compare 4 generation
refer to CC1G description
Bit 3 CC3G: Capture/compare 3 generation
refer to CC1G description
Bit 2 CC2G: Capture/compare 2 generation
refer to CC1G description
Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).
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General-purpose timers (TIM2)
20.4.7
TIMx capture/compare mode register 1 (TIMx_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.
15
14
OC2CE
13
12
OC2M[2:0]
IC2F[3:0]
rw
rw
rw
11
10
OC2PE OC2FE
IC2PSC[1:0]
rw
rw
rw
9
8
CC2S[1:0]
rw
7
6
OC1CE
rw
5
4
OC1M[2:0]
IC1F[3:0]
rw
rw
rw
3
2
OC1PE OC1FE
IC1PSC[1:0]
rw
rw
rw
1
0
CC1S[1:0]
rw
rw
Output compare mode
Bit 15 OC2CE: Output compare 2 clear enable
Bits 14:12 OC2M[2:0]: Output compare 2 mode
Bit 11 OC2PE: Output compare 2 preload enable
Bit 10 OC2FE: Output compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bit 7 OC1CE: Output compare 1 clear enable
OC1CE: Output Compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input
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RM0376
Bits 6:4 OC1M: Output compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends
on CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing
base).
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else
inactive.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in
output).
2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
Bit 3 OC1PE: Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in
output).
2: The PWM mode can be used without validating the preload register only in onepulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC
is set to the compare level independently from the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if
the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
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RM0376
General-purpose timers (TIM2)
Input capture mode
Bits 15:12 IC2F: Input capture 2 filter
Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Bits 9:8 CC2S: Capture/compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bits 7:4 IC1F: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter
applied to TI1. The digital filter is made of an event counter in which N events are needed to
validate a transition on the output:
0000: No filter, sampling is done at fDTS1000: fSAMPLING=fDTS/8, N=6
0001: fSAMPLING=fCK_INT, N=21001: fSAMPLING=fDTS/8, N=8
0010: fSAMPLING=fCK_INT, N=41010: fSAMPLING=fDTS/16, N=5
0011: fSAMPLING=fCK_INT, N=81011: fSAMPLING=fDTS/16, N=6
0100: fSAMPLING=fDTS/2, N=61100: fSAMPLING=fDTS/16, N=8
0101: fSAMPLING=fDTS/2, N=81101: fSAMPLING=fDTS/32, N=5
0110: fSAMPLING=fDTS/4, N=61110: fSAMPLING=fDTS/32, N=6
0111: fSAMPLING=fDTS/4, N=81111: fSAMPLING=fDTS/32, N=8
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=0 (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
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General-purpose timers (TIM2)
20.4.8
RM0376
TIMx capture/compare mode register 2 (TIMx_CCMR2)
Address offset: 0x1C
Reset value: 0x0000
Refer to the above CCMR1 register description.
15
14
OC4CE
13
12
OC4M[2:0]
IC4F[3:0]
rw
rw
rw
11
10
OC4PE OC4FE
IC4PSC[1:0]
rw
rw
rw
9
8
CC4S[1:0]
rw
7
6
OC3CE
rw
5
4
OC3M[2:0]
IC3F[3:0]
rw
rw
rw
3
2
OC3PE OC3FE
IC3PSC[1:0]
rw
rw
rw
1
0
CC3S[1:0]
rw
rw
Output compare mode
Bit 15 OC4CE: Output compare 4 clear enable
Bits 14:12 OC4M: Output compare 4 mode
Bit 11 OC4PE: Output compare 4 preload enable
Bit 10 OC4FE: Output compare 4 fast enable
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bit 7 OC3CE: Output compare 3 clear enable
Bits 6:4 OC3M: Output compare 3 mode
Bit 3 OC3PE: Output compare 3 preload enable
Bit 2 OC3FE: Output compare 3 fast enable
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
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General-purpose timers (TIM2)
Input capture mode
Bits 15:12 IC4F: Input capture 4 filter
Bits 11:10 IC4PSC: Input capture 4 prescaler
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bits 7:4 IC3F: Input capture 3 filter
Bits 3:2 IC3PSC: Input capture 3 prescaler
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
20.4.9
TIMx capture/compare enable register (TIMx_CCER)
Address offset: 0x20
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CC4NP
Res.
CC4P
CC4E
CC3NP
Res.
CC3P
CC3E
CC2NP
Res.
CC2P
CC2E
CC1NP
Res.
CC1P
CC1E
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bit 15 CC4NP: Capture/Compare 4 output Polarity.
Refer to CC1NP description
Bit 14
Reserved, must be kept at reset value.
Bit 13 CC4P: Capture/Compare 4 output Polarity.
refer to CC1P description
Bit 12 CC4E: Capture/Compare 4 output enable.
refer to CC1E description
Bit 11 CC3NP: Capture/Compare 3 output Polarity.
refer to CC1NP description
Bit 10
Reserved, must be kept at reset value.
Bit 9 CC3P: Capture/Compare 3 output Polarity.
refer to CC1P description
Bit 8 CC3E: Capture/Compare 3 output enable.
refer to CC1E description
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General-purpose timers (TIM2)
RM0376
Bit 7 CC2NP: Capture/Compare 2 output Polarity.
refer to CC1NP description
Bit 6
Reserved, must be kept at reset value.
Bit 5 CC2P: Capture/Compare 2 output Polarity.
refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable.
refer to CC1E description
Bit 3 CC1NP: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
CC1NP must be kept cleared in this case.
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P
description.
Bit 2
Reserved, must be kept at reset value.
Bit 1 CC1P: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
01: inverted/falling edge
Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
10: reserved, do not use this configuration.
11: noninverted/both edges
Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external
clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration
must not be used for encoder mode.
Bit 0 CC1E: Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off - OC1 is not active
1: On - OC1 signal is output on the corresponding output pin
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled
Table 75. Output control bit for standard OCx channels
CCxE bit
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OCx output state
0
Output Disabled (OCx=0, OCx_EN=0)
1
OCx=OCxREF + Polarity, OCx_EN=1
DocID025941 Rev 1
RM0376
General-purpose timers (TIM2)
Note:
The state of the external I/O pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.
20.4.10
TIMx counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNT[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CNT[15:0]: Low counter value
20.4.11
TIMx prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15
14
13
12
11
10
9
PSC[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event.
20.4.12
TIMx auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
ARR[15:0]
rw
rw
rw
Bits 15:0
20.4.13
rw
rw
rw
rw
rw
rw
ARR[15:0]: Low Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 20.3.1: Time-base unit on page 387 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.
TIMx capture/compare register 1 (TIMx_CCR1)
Address offset: 0x34
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR1[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
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General-purpose timers (TIM2)
RM0376
Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
20.4.14
TIMx capture/compare register 2 (TIMx_CCR2)
Address offset: 0x38
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR2[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
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General-purpose timers (TIM2)
20.4.15
TIMx capture/compare register 3 (TIMx_CCR3)
Address offset: 0x3C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR3[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CCR3[15:0]: Low Capture/Compare value
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register
(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.
If channel CC3is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3).
20.4.16
TIMx capture/compare register 4 (TIMx_CCR4)
Address offset: 0x40
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR4[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CCR4[15:0]: Low Capture/Compare value
1.
if CC4 channel is configured as output (CC4S bits):
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4
register (bit OC4PE). Else the preload value is copied in the active capture/compare 4
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
2.
if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):
CCR4 is the counter value transferred by the last input capture 4 event (IC4).
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General-purpose timers (TIM2)
20.4.17
RM0376
TIMx DMA control register (TIMx_DCR)
Address offset: 0x48
Reset value: 0x0000
15
14
13
Res.
Res.
Res.
12
11
10
9
8
DBL[4:0]
rw
rw
rw
rw
7
6
5
Res.
Res.
Res.
rw
4
3
2
1
0
rw
rw
DBA[4:0]
rw
rw
rw
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bit vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this
case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
20.4.18
TIMx DMA address for full transfer (TIMx_DMAR)
Address offset: 0x4C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
DMAB[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Example of how to use the DMA burst feature
In this example the timer DMA burst feature is used to update the contents of the CCRx
registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.
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General-purpose timers (TIM2)
This is done in the following steps:
1.
Note:
Configure the corresponding DMA channel as follows:
–
DMA channel peripheral address is the DMAR register address
–
DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into CCRx registers.
–
Number of data to transfer = 3 (See note below).
–
Circular mode disabled.
2.
Configure the DCR register by configuring the DBA and DBL bit fields as follows:
DBL = 3 transfers, DBA = 0xE.
3.
Enable the TIMx update DMA request (set the UDE bit in the DIER register).
4.
Enable TIMx
5.
Enable the DMA channel
This example is for the case where every CCRx register to be updated once. If every CCRx
register is to be updated twice for example, the number of data to transfer should be 6. Let's
take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and
data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.
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General-purpose timers (TIM2)
20.4.19
RM0376
TIM2 option register (TIM2_OR)
Address offset: 0x50
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
4
3
2
1
TI4_RMP
rw
0
ETR_RMP
rw
rw
rw
rw
Bits 15:5 Reserved, must be kept at reset value.
Bits 4:3 TI4_RMP: Internal trigger (TI4 connected to TIM2_CH4) remap
This bit is set and cleared by software.
01: TIM2 TI4 input connected to COMP2_OUT
10: TIM2 TI4 input connected to COMP1_OUT
others: TIM2 TI4 input connected to ORed GPIOs. Refer to the Alternate function mapping
table in the device datasheets.
Bits 2:0 ETR_RMP: Timer2 ETR remap
This bit is set and cleared by software.
111: TIM2 ETR input is connected to COMP1_OUT
110: TIM2 ETR input is connected to COMP2_OUT
101: TIM2 ETR input is connected to LSE
100: TIM2 ETR input is connected to HSI48 (see note below)
others: TIM2 ETR input is connected to ORed GPIOs. Refer to the Alternate function
mapping table in the device datasheets
Note: When TIM2 ETR is fed with HSI48, this ETR must be prescaled internally to the TIMER2
because the maximum system frequency is 32 MHz.
20.4.20
TIMx register map
TIMx registers are mapped as described in the table below:
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0
0
0
0
DocID025941 Rev 1
0
0
0
0
0
0
TS[2:0]
0
0
1
0
UDIS
CEN
0
0
0
Res.
Res.
MMS[2:0]
2
Res.
0
URS
3
OPM
0
CCDS
5
4
TI1S
0
0
0
Res.
0
ETF[3:0]
0
CMS
[1:0]
MSM
ECE
Reset value
ETPS [1:0]
TIMx_SMCR
ETP
0
DIR
0
6
7
0
Reset value
0x08
ARPE
8
9
0
Res.
Res.
Res.
Res.
Res.
TIMx_CR2
Res.
0x04
Res.
Reset value
CKD
[1:0]
Res.
10
Res.
11
Res.
12
Res.
14
13
Res.
TIMx_CR1
Res.
0x00
Register
Res.
Offset
15
Table 76. TIM2 register map and reset values
0
SMS[2:0]
0
0
0
RM0376
General-purpose timers (TIM2)
TIMx_CCMR2
Output Compare
mode
Reset value
0
0
0
0
IC4
PSC
[1:0]
0
UIF
UG
CC1IF
CC1G
CC2IF
CC2G
0
0
0
0
0
OC1FE
CC3IF
CC3G
CC4IF
0
OC1PE
Res.
0
CC4G
Res.
TIF
0
0
0
OC1M
[2:0]
0
0
0
IC1
PSC
[1:0]
CC4S
[1:0]
0
CC4S
[1:0]
0
0
0
OC3M
[2:0]
0
0
0
0
0
0
0
IC3
PSC
[1:0]
0
0
CC1S
[1:0]
0
0
CC3S
[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIMx_CCER
CC4E
CC3NP
Res.
CC3P
CC3E
CC2NP
Res.
Res.
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CC1E
0
CC1P
TIMx_CNT
CC1NP
0
CC2E
0
CC4P
CC3S
[1:0]
Res.
IC3F[3:0]
CC1S
[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNT[15:0]
0
0
0
0
0
0
0
TIMx_PSC
0
0
PSC[15:0]
0
0
0
0
0
0
0
TIMx_ARR
Reset value
0
0
ARR[15:0]
0
0
0
0
0
0x30
0x34
0
0
0
IC1F[3:0]
0
0
0
CC4NP
IC4F[3:0]
OC1CE
OC2FE
0
0
UIE
4
CC4IE
0
0
1
5
Res.
OC4M
[2:0]
0
CC2S
[1:0]
CC1IE
6
TIE
0
0
0
0
Reset value
0x2C
0
0
0
Reset value
Reset value
0x28
IC2
PSC
[1:0]
0
0
CC2P
0x24
0
0
0
OC3FE
0
0
0
OC3PE
Reset value
TIMx_CCMR2
Input Capture mode
0x20
0
IC2F[3:0]
O24CE
0x1C
0
CC2S
[1:0]
OC3CE
TIMx_CCMR1
Input Capture mode
0
OC4FE
0
OC2PE
Reset value
OC2M
[2:0]
OC4PE
0x18
0
TIMx_CCMR1
Output Compare
mode
OC2CE
Reset value
TG
0
2
7
Res.
Res.
0
Res.
0
CC2IE
8
UDE
Res.
0
Res.
0
0
3
9
CC1DE
CC1OF
Res.
TIMx_EGR
Res.
0x14
Res.
Reset value
Res.
10
CC2DE
0
CC2OF
0
Res.
11
CC3DE
0
CC3OF
0
Res.
12
CC4DE
0
CC4OF
0
Res.
13
COMDE
0
Res.
TIMx_SR
14
0x10
Res.
Reset value
TDE
TIMx_DIER
Res.
0x0C
Register
15
Offset
Res.
Table 76. TIM2 register map and reset values (continued)
0
0
0
0
Res.
TIMx_CCR1
Reset value
CCR1[15:0]
0
0
0
0
0
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0
0
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3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CCR3[15:0]
0
0
0
0
0
0
0
0
0
CCR4[15:0]
0
0
0
0
0
0
0
0
Res.
Res.
DBL[4:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIM2_OR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Refer to Section 2.2.2 for the register boundary addresses.
DocID025941 Rev 1
ETR_RMP
Reset value
Res.
DMAB[15:0]
Res.
TIMx_DMAR
0
DBA[4:0]
TI4_RMP
TIMx_DCR
Res.
Res.
Reset value
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7
8
9
10
11
12
0
Res.
0x50
4
0
Reset value
0x4C
5
0
0x44
0x48
0
Res.
0
TIMx_CCR4
Reset value
6
0x40
0
CCR2[15:0]
TIMx_CCR3
Reset value
0
Res.
Reset value
0x3C
13
TIMx_CCR2
Res.
0x38
Register
14
Offset
15
Table 76. TIM2 register map and reset values (continued)
0
RM0376
General-purpose timers (TIM21/22)
21
General-purpose timers (TIM21/22)
21.1
Introduction
The TIM21/22 general-purpose timers consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The TIM21/22 timers are completely independent, and do not share any resources. They
can be synchronized together as described in Section 21.3.14.
21.2
TIM21/22 main features
21.2.1
TIM21/22 main features
The features of the TIM21/22 general-purpose timer include:
•
16-bit up, down, up/down, auto-reload counter
•
16-bit programmable prescaler used to divide the counter clock frequency by any factor
between 1 and 65535 (can be changed “on the fly”)
•
Up to 2 independent channels for:
–
Input capture
–
Output compare
–
PWM generation (edge- and center-aligned mode)
–
One-pulse mode output
•
Synchronization circuit to control the timer with external signals and to interconnect
several timers together
•
Interrupt generation on the following events:
–
Update: counter overflow/underflow, counter initialization (by software or internal
trigger)
–
Trigger event (counter start, stop, initialization or count by internal trigger)
–
Input capture
–
Output compare
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Figure 131. General-purpose timer block diagram (TIM21/22)
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General-purpose timers (TIM21/22)
21.3
TIM21/22 functional description
21.3.1
Time-base unit
The main block of the timer is a 16-bit counter with its related auto-reload register. The
counters counts up, down or both up and down but also down or both up and down. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
•
Counter register (TIMx_CNT)
•
Prescaler register (TIMx_PSC)
•
Auto-reload register (TIMx_ARR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be
generated by software. The generation of the update event is described in detailed for each
configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 133 and Figure 134 give some examples of the counter behavior when the prescaler
ratio is changed on the fly.
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Figure 132. Counter timing diagram with prescaler division change from 1 to 2
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General-purpose timers (TIM21/22)
Figure 133. Counter timing diagram with prescaler division change from 1 to 4
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21.3.2
Counter modes
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller on TIM21/22) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
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When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The auto-reload shadow register is updated with the preload value (TIMx_ARR),
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 134. Counter timing diagram, internal clock divided by 1
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Figure 135. Counter timing diagram, internal clock divided by 2
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Figure 136. Counter timing diagram, internal clock divided by 4
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Figure 137. Counter timing diagram, internal clock divided by N
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Figure 138. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)
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General-purpose timers (TIM21/22)
Figure 139. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)
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Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.
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The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 140. Counter timing diagram, internal clock divided by 1
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Figure 141. Counter timing diagram, internal clock divided by 2
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Figure 142. Counter timing diagram, internal clock divided by 4
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Figure 143. Counter timing diagram, internal clock divided by N
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Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center
aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,
CMS = "11").
In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupt when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
•
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
•
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.
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Figure 144. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
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1. Here, center-aligned mode 1 is used (for more details refer to Section 21.4.1: TIM21/22 control register 1
(TIMx_CR1) on page 485).
Figure 145. Counter timing diagram, internal clock divided by 2
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Figure 146. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
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1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 147. Counter timing diagram, internal clock divided by N
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Figure 148. Counter timing diagram, Update event with ARPE=1 (counter underflow)
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Figure 149. Counter timing diagram, Update event with ARPE=1 (counter overflow)
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21.3.3
RM0376
Clock selection
The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1 (for TIM21): external input pin (TIx)
•
External clock mode2: external trigger input (ETR connected internally to LSE)
•
Internal trigger inputs (ITRx) (for TIM21/22): connecting the trigger output from another
timer. Refer to Section : Using one timer as prescaler for another for more details.
Internal clock source (CK_INT)
The internal clock source is selected when the slave mode controller is disabled
(SMS=’000’). The CEN bit in the TIMx_CR1 register and the UG bit in the TIMx_EGR
register are then used as control bits and can be changed only by software (except for UG
which remains cleared). As soon as the CEN bit is programmed to 1, the prescaler is
clocked by the internal clock CK_INT.
Figure 150 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
Figure 150. Control circuit in normal mode, internal clock divided by 1
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General-purpose timers (TIM21/22)
External clock source mode 1(TIM21)
This mode is selected when SMS=’111’ in the TIMx_SMCR register. The counter can count
at each rising or falling edge on a selected input.
Figure 151. TI2 external clock connection example
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For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in
the TIMx_CCMR1 register.
Note:
2.
Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=’0000’).
3.
Select the rising edge polarity by writing CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER
register.
4.
Configure the timer in external clock mode 1 by writing SMS=’111’ in the TIMx_SMCR
register.
5.
Select TI2 as the trigger input source by writing TS=’110’ in the TIMx_SMCR register.
6.
Enable the counter by writing CEN=’1’ in the TIMx_CR1 register.
The capture prescaler is not used for triggering, so you don’t need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.
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Figure 152. Control circuit in external clock mode 1
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This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 153 gives an overview of the external trigger input block.
Figure 153. External trigger input block
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For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
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General-purpose timers (TIM21/22)
1.
As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2.
Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3.
Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4.
Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 154. Control circuit in external clock mode 2
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21.3.4
Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 155 to Figure 157 give an overview of one capture/compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
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Figure 155. Capture/compare channel (example: channel 1 input stage)
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The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Figure 156. Capture/compare channel 1 main circuit
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Figure 157. Output stage of capture/compare channel (channel 1 and 2)
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The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
21.3.5
Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
1.
Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’,
the channel is configured in input mode and the TIMx_CCR1 register becomes readonly.
2.
Program the input filter duration you need with respect to the signal you connect to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been
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detected (sampled at fDTS frequency). Then write IC1F bits to ‘0011’ in the
TIMx_CCMR1 register.
3.
Select the edge of the active transition on the TI1 channel by programming CC1P and
CC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case).
4.
Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).
5.
Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
6.
If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register.
When an input capture occurs:
•
The TIMx_CCR1 register gets the value of the counter on the active transition.
•
CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
•
An interrupt is generated depending on the CC1IE bit.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note:
IC interrupt requests can be generated by software by setting the corresponding CCxG bit in
the TIMx_EGR register.
21.3.6
PWM input mode
This mode is a particular case of input capture mode. The procedure is the same except:
•
Two ICx signals are mapped on the same TIx input.
•
These 2 ICx signals are active on edges with opposite polarity.
•
One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
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1.
Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1
register (TI1 selected).
2.
Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge).
3.
Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’ in the TIMx_CCMR1
register (TI1 selected).
4.
Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): program the
CC2P and CC2NP bits to ‘11’ (active on falling edge).
5.
Select the valid trigger input: write the TS bits to ‘101’ in the TIMx_SMCR register
(TI1FP1 selected).
6.
Configure the slave mode controller in reset mode: write the SMS bits to ‘100’ in the
TIMx_SMCR register.
7.
Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.
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General-purpose timers (TIM21/22)
Figure 158. PWM input mode timing
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1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only
TI1FP1 and TI2FP2 are connected to the slave mode controller.
21.3.7
Forced output mode
In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, you just need to write
‘101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=’0’ (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to ‘100’ in the
TIMx_CCMRx register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is
described in the output compare mode section below.
21.3.8
Output compare mode
This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
1.
Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=’000’), be set
active (OCxM=’001’), be set inactive (OCxM=’010’) or can toggle (OCxM=’011’) on
match.
2.
Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
3.
Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
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The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).
Procedure:
1.
Select the counter clock (internal, external, prescaler).
2.
Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3.
Set the CCxIE bit if an interrupt request is to be generated.
4.
Select the output mode. For example:
5.
–
Write OCxM = ‘011’ to toggle OCx output pin when CNT matches CCRx
–
Write OCxPE = ‘0’ to disable preload register
–
Write CCxP = ‘0’ to select active high polarity
–
Write CCxE = ‘1’ to enable the output
Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 159.
Figure 159. Output compare mode, toggle on OC1
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21.3.9
General-purpose timers (TIM21/22)
PWM mode
Pulse Width Modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing the OCxM bits in the TIMx_CCMRx register. Only the edge-aligned mode
is available on TIMER20 and TIMER21. You must enable the corresponding preload
register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the autoreload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in
the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIMx_EGR register.
The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register.
It can be programmed as active high or active low. The OCx output is enabled by the CCxE
bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more
details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CNT ≤ TIMx_CCRx.
The timer is able to generate PWM in edge-aligned mode only since the counter is
upcounting.
•
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the
Upcounting mode on page 453.
In the following example, we consider PWM mode 1. The reference PWM signal
OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the
compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)
then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’.
Figure 160 shows some edge-aligned PWM waveforms in an example where
TIMx_ARR=8.
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Figure 160. Edge-aligned PWM waveforms (ARR=8)
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•
Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the
Downcounting mode on page 457
In PWM mode 1, the reference signal OCxRef is low as long as
TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is
greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM
is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals).
The compare flag is set when the counter counts up, when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
the Center-aligned mode (up/down counting) on page 460.
Figure 161 shows some center-aligned PWM waveforms in an example where:
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•
TIMx_ARR=8,
•
PWM mode is the PWM mode 1,
•
The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.
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General-purpose timers (TIM21/22)
Figure 161. Center-aligned PWM waveforms (ARR=8)
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Hints on using center-aligned mode
•
When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
•
Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
•
–
The direction is not updated if you write a value in the counter that is greater than
the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was
counting up, it continues to count up.
–
The direction is updated if you write 0 or write the TIMx_ARR value in the counter
but no Update Event UEV is generated.
The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.
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21.3.10
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Clearing the OCxREF signal on an external event
The OCxREF signal for a given channel can be driven Low by applying a High level to the
ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The
OCxREF signal remains Low until the next update event, UEV, occurs.
This function can only be used in output compare and PWM modes, and does not work in
forced mode.
For example, the ETR signal can be connected to the output of a comparator to be used for
current handling. In this case, the ETR must be configured as follow:
1.
The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR
register set to ‘00’.
2.
The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to
‘0’.
3.
The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to the user needs.
Figure 162 shows the behavior of the OCxREF signal when the ETRF Input becomes High,
for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in
PWM mode.
Figure 162. Clearing TIMx OCxREF
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Note:
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In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at
the next counter overflow.
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One-pulse mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. You select One-pulse mode
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be as follows:
CNT < CCRx≤ ARR (in particular, 0 < CCRx)
Figure 163. Example of one pulse mode
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For example you may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Use TI2FP2 as trigger 1:
1.
Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.
2.
TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP = ‘0’ in the TIMx_CCER
register.
3.
Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in
the TIMx_SMCR register.
4.
TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register
(trigger mode).
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The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
•
The tDELAY is defined by the value written in the TIMx_CCR1 register.
•
The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1).
•
Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this you enable PWM mode 2 by writing OC1M=’111’ in the TIMx_CCMR1
register. You can optionally enable the preload registers by writing OC1PE=’1’ in the
TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to
write the compare value in the TIMx_CCR1 register, the auto-reload value in the
TIMx_ARR register, generate an update by setting the UG bit and wait for external
trigger event on TI2. CC1P is written to ‘0’ in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1
register to stop the counter at the next update event (when the counter rolls over from the
auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the
Repetitive Mode is selected.
Particular case: OCx fast enable
In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
21.3.12
Encoder interface mode
To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter
is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if
it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. CC1NP and CC2NP must be kept cleared. When needed, you can program the
input filter as well. CC1NP and CC2NP must be kept low.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 77. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
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General-purpose timers (TIM21/22)
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must
configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler,
trigger output features continue to work as normal.
In this mode, the counter is modified automatically following the speed and the direction of
the quadrature encoder and its content, therefore, always represents the encoder’s position.
The count direction correspond to the rotation direction of the connected sensor. The table
summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same
time.
Table 77. Counting direction versus encoder signals
Level on opposite
signal (TI1FP1 for
TI2, TI2FP2 for TI1)
Rising
Falling
Rising
Falling
Counting on
TI1 only
High
Down
Up
No Count
No Count
Low
Up
Down
No Count
No Count
Counting on
TI2 only
High
No Count
No Count
Up
Down
Low
No Count
No Count
Down
Up
Counting on
TI1 and TI2
High
Down
Up
Up
Down
Low
Up
Down
Down
Up
Active edge
TI1FP1 signal
TI2FP2 signal
An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
Figure 164 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
•
CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1)
•
CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2)
•
CC1P and CC1NP = ‘0’ (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1)
•
CC2P and CC2NP = ‘0’ (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2)
•
SMS= 011 (TIMx_SMCR register, both inputs are active on both rising and falling
edges)
•
CEN= 1 (TIMx_CR1 register, Counter is enabled)
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Figure 164. Example of counter operation in encoder interface mode
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Figure 165 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=1).
Figure 165. Example of encoder interface mode with TI1FP1 polarity inverted
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The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. You can obtain dynamic information (speed, acceleration, deceleration) by
measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. You can do this by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a Real-Time clock.
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21.3.13
General-purpose timers (TIM21/22)
TIM21/22 external trigger synchronization
The TIM21/22 timers can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.
Slave mode: Reset mode
The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
1.
Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S = ‘01’ in the TIMx_CCMR1 register.
Program CC1P and CC1NP to ‘00’ in TIMx_CCER register to validate the polarity (and
detect rising edges only).
2.
Configure the timer in reset mode by writing SMS=’100’ in TIMx_SMCR register. Select
TI1 as the input source by writing TS=’101’ in TIMx_SMCR register.
3.
Start the counter by writing CEN=’1’ in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if
enabled (depending on the TIE bit in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.
Figure 166. Control circuit in reset mode
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Slave mode: Gated mode
The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
1.
Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S=’01’ in TIMx_CCMR1 register. Program
CC1P=’1’ and CC1NP= ‘0’ in TIMx_CCER register to validate the polarity (and detect
low level only).
2.
Configure the timer in gated mode by writing SMS=’101’ in TIMx_SMCR register.
Select TI1 as the input source by writing TS=’101’ in TIMx_SMCR register.
3.
Enable the counter by writing CEN=’1’ in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=’0’, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.
Figure 167. Control circuit in gated mode
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Slave mode: Trigger mode
The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
1.
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Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
–
ETF = 0000: no filter
–
ETPS = 00: prescaler disabled
–
ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
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General-purpose timers (TIM21/22)
1.
Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC2F=’0000’). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are
configured to select the input capture source only, CC2S=’01’ in TIMx_CCMR1 register.
Program CC2P=’1’ and CC2NP=’0’ in TIMx_CCER register to validate the polarity (and
detect low level only).
2.
Configure the timer in trigger mode by writing SMS=’110’ in TIMx_SMCR register.
Select TI2 as the input source by writing TS=’110’ in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.
Figure 168. Control circuit in trigger mode
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General-purpose timers (TIM21/22)
21.3.14
RM0376
Timer synchronization (TIM21/22)
The timers are linked together internally for timer synchronization or chaining. Refer to
Section 20.3.15: Timer synchronization on page 420 for details.
21.3.15
Debug mode
When the microcontroller enters debug mode (Cortex®-M0+ core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers,
watchdog, bxCAN and I2C.
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General-purpose timers (TIM21/22)
21.4
TIM21/22 registers
Refer to Section 1.1 on page 43 for a list of abbreviations used in register descriptions.
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
21.4.1
TIM21/22 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15
14
13
12
11
10
Res.
Res.
Res.
Res.
Res.
Res.
9
8
CKD[1:0]
rw
7
6
ARPE
rw
rw
5
CMS[1:0]
rw
rw
4
3
2
1
0
DIR
OPM
URS
UDIS
CEN
rw
rw
rw
rw
rw
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (TIx),
00: tDTS = tCK_INT
01: tDTS = 2 × tCK_INT
10: tDTS = 4 × tCK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:5 CMS[1:0]: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
the counter is enabled (CEN=1).
Bit 4 DIR: Direction
0: Counter used as upcounter
1: Counter used as downcounter
Bit 3 OPM: One-pulse mode
0: Counter is not stopped on the update event
1: Counter stops counting on the next update event (clearing the CEN bit).
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Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generates an update interrupt if enabled:
–
Counter overflow
–
Setting the UG bit
1: Only counter overflow generates an update interrupt if enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable update event (UEV) generation.
0: UEV enabled. An UEV is generated by one of the following events:
–
Counter overflow
–
Setting the UG bit
Buffered registers are then loaded with their preload values.
1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,
CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
CEN is cleared automatically in one-pulse mode, when an update event occurs.
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General-purpose timers (TIM21/22)
21.4.2
TIM21/22 control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
6
5
4
MMS[2:0]
rw
rw
3
2
1
0
Res.
Res.
Res.
Res.
rw
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:4 MMS: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO)
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Reserved
111: Reserved
Bits 3:0 Reserved, must be kept at reset value.
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21.4.3
RM0376
TIM21/22 slave mode control register (TIMx_SMCR)
Address offset: 0x08
Reset value: 0x0000
15
14
ETP
ECE
rw
rw
13
12
11
rw
rw
10
9
8
ETF[3:0]
ETPS[1:0]
rw
rw
7
6
MSM
rw
rw
rw
5
4
TS[2:0]
rw
rw
3
2
Res.
rw
1
0
SMS[2:0]
rw
rw
rw
Bit 15 ETP: External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI
connected to ETRF (SMS=111 and TS=111).
It is possible to simultaneously use external clock mode 2 with the following slave
modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be
connected to ETRF in this case (TS bits must not be 111).
If external clock mode 1 and external clock mode 2 are enabled at the same time, the
external clock input is ETRF.
Bits 13:12 ETPS[1:0]: External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
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General-purpose timers (TIM21/22)
Bits 11:8 ETF[3:0]: External trigger filter
This bit-field then defines the frequency used to sample ETRP signal and the length of the
digital filter applied to ETRP. The digital filter is made of an event counter in which N events
are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8
Bit 7 MSM: Master/Slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful in
order to synchronize several timers on a single external event.
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Bits 6:4 TS: Trigger selection
This bitfield selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Internal Trigger 1 (ITR1)
010: Reserved
011: Reserved
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: Reserved.
See Table 78: TIMx Internal trigger connection on page 490 for more details on the meaning
of ITRx for each timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=’000’) to
avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SMS: Slave mode selection
When external signals are selected, the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input control register and Control register
descriptions.
000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal
clock
001: Reserved
010: Reserved
011: Reserved
100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers
101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Counter starts and stops
are both controlled
110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled
111: Reserved
Note: The Gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
Gated mode checks the level of the trigger signal.
Table 78. TIMx Internal trigger connection(1)
Slave TIM
ITR0 (TS = 000)
ITR1 (TS = 001)
TIM21
TIM2
TIM22
TIM22
TIM21
TIM2
1. When a timer is not present in the product, the corresponding trigger ITRx is not available.
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21.4.4
TIM21/22 Interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIE
Res.
Res.
Res.
CC2IE
CC1IE
UIE
rw
rw
rw
rw
Bit 15:7
Reserved, must be kept at reset value.
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Bit 5:3
Reserved, must be kept at reset value.
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled.
1: CC2 interrupt enabled.
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled.
1: CC1 interrupt enabled.
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled.
1: Update interrupt enabled.
21.4.5
TIM21/22 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
15
14
13
12
11
Res.
Res.
Res.
Res.
Res.
10
rc_w0
Bit 15:11
9
CC2OF CC1OF
8
7
6
5
4
3
2
1
0
Res.
Res.
TIF
Res.
Res.
Res.
CC2IF
CC1IF
UIF
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
Reserved, must be kept at reset value.
Bit 10 CC2OF: Capture/compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7
Reserved, must be kept at reset value.
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Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode. It is set when the counter
starts or stops when gated mode is selected. It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bit 5:3
Reserved, must be kept at reset value.
Bit 2 CC2IF: Capture/Compare 2 interrupt flag
refer to CC1IF description
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value. It is cleared by
software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
bit goes high on the counter overflow.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected
on IC1 which matches the selected polarity).
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow and if UDIS=’0’ in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and
UDIS=’0’ in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to the synchro control register
description), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.
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General-purpose timers (TIM21/22)
21.4.6
TIM21/22 event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TG
Res.
Res.
Res.
CC2G
CC1G
UG
w
w
w
w
Bits 15:7 Reserved, must be kept at reset value.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled
Bits 5:3 Reserved, must be kept at reset value.
Bit 2 CC2G: Capture/compare 2 generation
refer to CC1G description
Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software to generate an event, it is automatically cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
the CC1IF flag is set, the corresponding interrupt is sent if enabled.
If channel CC1 is configured as input:
The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the
corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was
already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initializes the counter and generates an update of the registers. The prescaler counter
is also cleared and the prescaler ratio is not affected. The counter is cleared.
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21.4.7
RM0376
TIM21/22 capture/compare mode register 1 (TIMx_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits in this register have different functions in input and output modes. For a given bit, OCxx
describes its function when the channel is configured in output mode, ICxx describes its
function when the channel is configured in input mode. So you must take care that the same
bit can have different meanings for the input stage and the output stage.
15
14
Res.
rw
13
12
11
10
OC2M[2:0]
OC2PE OC2FE
IC2F[3:0]
IC2PSC[1:0]
rw
rw
rw
rw
9
8
CC2S[1:0]
rw
7
6
Res.
rw
rw
5
4
3
2
OC1M[2:0]
OC1PE OC1FE
IC1F[3:0]
IC1PSC[1:0]
rw
rw
rw
rw
1
0
CC1S[1:0]
rw
rw
Output compare mode
Bit 15
Reserved, must be kept at reset value.
Bits 14:12 OC2M[2:0]: Output compare 2 mode
Bit 11 OC2PE: Output compare 2 preload enable
Bit 10 OC2FE: Output compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an
internal trigger input is selected through the TS bit (TIMx_SMCR register
Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bit 7
494/869
Reserved, must be kept at reset value.
DocID025941 Rev 1
RM0376
General-purpose timers (TIM21/22)
Bits 6:4 OC1M: Output compare 1 mode
These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N
depend on the CC1P and CC1NP bits, respectively.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing
base).
001: Set channel 1 to active level on match. The OC1REF signal is forced high when the
TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. The OC1REF signal is forced low when the
TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1
100: Force inactive level - OC1REF is forced low
101: Force active level - OC1REF is forced high
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else it is inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as
TIMx_CNT>TIMx_CCR1, else it is active (OC1REF=’1’)
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else it is active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1
else it is inactive.
Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
Bit 3 OC1PE: Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken into account immediately
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded into the active register at each update event
Note: The PWM mode can be used without validating the preload register only in one-pulse
mode (OPM bit set in the TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on the counter and CCR1 values even when the
trigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the
trigger input is 5 clock cycles
1: An active edge on the trigger input acts like a compare match on the CC1 output. Then,
OC is set to the compare level independently of the result of the comparison. Delay to
sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE
acts only if the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an
internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
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General-purpose timers (TIM21/22)
RM0376
Input capture mode
Bits 15:12 IC2F: Input capture 2 filter
Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Bits 9:8 CC2S: Capture/compare 2 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an
internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bits 7:4 IC1F: Input capture 1 filter
This bitfield defines the frequency used to sample the TI1 input and the length of the digital
filter applied to TI1. The digital filter is made of an event counter in which N events are
needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS1000: fSAMPLING=fDTS/8, N=6
0001: fSAMPLING=fCK_INT, N=21001: fSAMPLING=fDTS/8, N=8
0010: fSAMPLING=fCK_INT, N=41010: fSAMPLING=fDTS/16, N=5
0011: fSAMPLING=fCK_INT, N=8 1011: fSAMPLING=fDTS/16, N=6
0100: fSAMPLING=fDTS/2, N=61100: fSAMPLING=fDTS/16, N=8
0101: fSAMPLING=fDTS/2, N=81101: fSAMPLING=fDTS/32, N=5
0110: fSAMPLING=fDTS/4, N=61110: fSAMPLING=fDTS/32, N=6
0111: fSAMPLING=fDTS/4, N=81111: fSAMPLING=fDTS/32, N=8
Note: In the current silicon revision, fDTS is replaced in the formula by CK_INT when
ICxF[3:0]= 1, 2 or 3.
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
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General-purpose timers (TIM21/22)
21.4.8
TIM21/22 capture/compare enable register (TIMx_CCER)
Address offset: 0x20
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CC2NP
Res.
CC2P
CC2E
CC1NP
Res.
CC1P
CC1E
rw
rw
rw
rw
rw
rw
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 CC2NP: Capture/Compare 2 output Polarity
refer to CC1NP description
Bits 6 Reserved, must be kept at reset value.
Bit 5 CC2P: Capture/Compare 2 output Polarity
refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable
refer to CC1E description
Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity
CC1 channel configured as output: CC1NP must be kept cleared
CC1 channel configured as input: CC1NP is used in conjunction with CC1P to define
TI1FP1/TI2FP1 polarity (refer to CC1P description).
Bits 2 Reserved, must be kept at reset value.
Bit 1 CC1P: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high.
1: OC1 active low.
CC1 channel configured as input:
CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
01: inverted/falling edge
Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
10: reserved, do not use this configuration.
Note: 11: noninverted/both edges
Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset,
external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This
configuration must not be used for encoder mode.
Bit 0 CC1E: Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off - OC1 is not active.
1: On - OC1 signal is output on the corresponding output pin.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled.
1: Capture enabled.
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RM0376
Table 79. Output control bit for standard OCx channels
CCxE bit
OCx output state
0
Output disabled (OCx=’0’, OCx_EN=’0’)
1
OCx=OCxREF + Polarity, OCx_EN=’1’
Note:
The states of the external I/O pins connected to the standard OCx channels depend on the
state of the OCx channel and on the GPIO registers.
21.4.9
TIM21/22 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000 0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CNT[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CNT[15:0]: Counter value
21.4.10
TIM21/22 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15
14
13
12
11
10
9
8
PSC[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded into the active prescaler register at each update event.
21.4.11
TIM21/22 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x0000 0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
ARR[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded into the actual auto-reload register.
Refer to the Section 21.3.1: Time-base unit on page 451 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.
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General-purpose timers (TIM21/22)
21.4.12
TIM21/22 capture/compare register 1 (TIMx_CCR1)
Address offset: 0x34
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR1[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(OC1PE bit). Else the preload value is copied into the active capture/compare 1 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the TIMx_CNT
counter and signaled on the OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
21.4.13
TIM21/22 capture/compare register 2 (TIMx_CCR2)
Address offset: 0x38
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CCR2[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CCR2[15:0]: Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded into the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(OC2PE bit). Else the preload value is copied into the active capture/compare 2 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the TIMx_CNT
counter and signalled on the OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
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General-purpose timers (TIM21/22)
21.4.14
RM0376
TIM21 option register (TIM21_OR)
Address offset: 0x50
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TI2_RMP
rw
4
3
2
TI1_RMP
rw
rw
1
0
ETR_RMP
rw
rw
rw
Bits 15:6 Reserved, must be kept at reset value.
Bit 5 TI2_RMP: Timer21 TI2 (connected to TIM21_CH1) remap
This bit is set and cleared by software.
0: TIM21 TI2 input connected to GPIO. Refer to the Alternate function mapping table in the
device datasheet.
1: TIM21 TI2 input connected to COMP2_OUT
Bit 4:2 TI1_RMP: Timer21 TI1 (connected to TIM21_CH1) remap
This bit is set and cleared by software.
000: TIM21 TI1 input connected to GPIO. Refer to the Alternate function mapping table in the
device datasheet.
001:TIM21 TI1 input connected to RTC WAKEUP interrupt
010: TIM21 TI1 input connected to HSE_RTC clock
011: TIM21 TI1 input connected to MSI clock
100: TIM21 TI1 input connected to LSE clock
101: TIM21 TI1 input connected to LSI clock
110: TIM21 TI1 input connected to COMP1_OUT
111: TIM21 TI1 input connected to MCO clock
Bit 1:0 ETR_RMP: Timer21 ETR remap
This bit is set and cleared by software.
00: TIM21 ETR input connected to GPIO. Refer to the Alternate function mapping table in the
device datasheet.
01: TIM21 ETR input connected to COMP2_OUT
10: TIM21 ETR input connected to COMP1_OUT
11: TIM21 ETR input connected to LSE clock
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General-purpose timers (TIM21/22)
21.4.15
TIM22 option register (TIM22_OR)
Address offset: 0x50
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
TI1_RMP
rw
0
ETR_RMP
rw
rw
rw
Bits 15:4 Reserved, must be kept at reset value.
Bit 3:2 TI1_RMP: Timer22 TI1 (connected to TIM22_CH1) remap
This bit is set and cleared by software.
00: TIM22 TI1 input connected to GPIO. Refer to the Alternate function mapping table in the
device datasheet.
01:TIM22 TI1 input connected to COMP2_OUT
10: TIM22 TI1 input connected to COMP1_OUT
11: TIM22 TI1 input connected to GPIO. Refer to the Alternate function mapping table in the
device datasheet.
Bits 1:0 ETR_RMP: Timer22 ETR remap
This bit is set and cleared by software.
00: TIM22 ETR input connected to GPIO. Refer to the Alternate function mapping table in the
device datasheet.
01: TIM22 ETR input connected to COMP2_OUT
10: TIM22 ETR input connected to COMP1_OUT
11: TIM22 ETR input connected to LSE clock
21.4.16
TIM21/22 register map
The table below shows TIM21/22 register map and reset values.
DIR
OPM
URS
UDIS
CEN
Res.
Res.
Res.
SMS[2:0]
0
0
0
0
Res.
Res.
0
0
0
UIE
0
CC1IE
0
CC2IE
Res.
0
TIE
Res.
MSM
0
TS[2:0]
0
DocID025941 Rev 1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIMx_DIER
0x0C
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
Reset value
ETF[3:0]
Res.
ETP
ECE
ETPS
[1:0]
Res.
TIMx_SMCR
0x08
0
MMS[2:0]
0
Res.
Reset value
0
Res.
0
Res.
0
CMS
[1:0]
Res.
ARPE
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIMx_CR2
0x04
Res.
Reset value
CKD
[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIMx_CR1
0x00
Res.
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 80. TIM21/22 register map and reset values
0
0
0
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502/869
0x38
TIMx_CCR2
Res.
Res.
Res.
0x3C to
0x4C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x30
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
DocID025941 Rev 1
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
CC2NP
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IC2F[3:0]
0
0
0
0
0
0
OC2FE
0
0
0
IC2
PSC
[1:0]
CC2
S
[1:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
OC2PE
0
CC2
S
[1:0]
0
0
0
CNT[15:0]
0
0
0
0
0
0
0
PSC[15:0]
0
ARR[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
CCR1[15:0]
CCR2[15:0]
Res.
CCR2[15:0]
CC1E
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
CC1P
0
0
IC1F[3:0]
CC2G
CC1G
UG
0
0
0
0
OC1FE
0
OC1PE
OC1M
[2:0]
Res.
Res.
Res.
TG
Res.
CC1IF
UIF
0
CC2IF
Res.
Res.
Res.
TIF
Res.
Res.
CC1OF
Res.
Res.
CC2OF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
CC2E
0
Res.
Reset value
OC2M
[2:0]
0
CC1NP
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
CC2P
0
Res.
Res.
0
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x1C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIMx_CCR2
Res.
0x38
Res.
TIMx_CCR1
Res.
0x34
Res.
TIMx_ARR
Res.
0x2C
Res.
TIMx_PSC
Res.
0x28
Res.
TIMx_CNT
Res.
0x24
Res.
TIMx_CCER
Res.
0x20
Res.
TIMx_CCMR1
Input Capture
mode
Res.
TIMx_CCMR1
Output
Compare mode
Res.
TIMx_EGR
Res.
0x14
Res.
TIMx_SR
Res.
0x10
Res.
0x18
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
General-purpose timers (TIM21/22)
RM0376
Table 80. TIM21/22 register map and reset values (continued)
0
0
0
CC1
S
[1:0]
0
0
0
0
IC1
PSC
[1:0]
CC1
S
[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x50
TIM22_OR
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Reset value
0
0
0
0
0
ETR_RMP
TI1_RMP
0
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIM21_OR
Res.
0x50
ETR_RMP
TI1_RMP
TI2_RMP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
RM0376
General-purpose timers (TIM21/22)
Table 80. TIM21/22 register map and reset values (continued)
0
0
0
0
Refer to Section 2.2.2 for the register boundary addresses.
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22
Basic timers (TIM6)
22.1
Introduction
The basic timer TIM6 consists of a 16-bit auto-reload counter driven by a programmable
prescaler.
It may be used as generic timers for time-base generation but they are also specifically used
to drive the digital-to-analog converter (DAC). In fact, the timer is internally connected to the
DAC and are able to drive it through their trigger outputs.
The timer is completely independent, and do not share any resources.
22.2
TIM6 main features
Basic timer (TIM6) features include:
•
16-bit auto-reload upcounter
•
16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65536
•
Synchronization circuit to trigger the DAC
•
Interrupt/DMA generation on the update event: counter overflow
Figure 169. Basic timer block diagram
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Basic timers (TIM6)
22.3
TIM6 functional description
22.3.1
Time-base unit
The main block of the programmable timer is a 16-bit upcounter with its related auto-reload
register. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
•
Counter Register (TIMx_CNT)
•
Prescaler Register (TIMx_PSC)
•
Auto-Reload Register (TIMx_ARR)
The auto-reload register is preloaded. The preload register is accessed each time an
attempt is made to write or read the auto-reload register. The contents of the preload
register are transferred into the shadow register permanently or at each update event UEV,
depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The
update event is sent when the counter reaches the overflow value and if the UDIS bit equals
0 in the TIMx_CR1 register. It can also be generated by software. The generation of the
update event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in the TIMx_CR1 register is set.
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as the TIMx_PSC control register is buffered. The new
prescaler ratio is taken into account at the next update event.
Figure 170 and Figure 171 give some examples of the counter behavior when the prescaler
ratio is changed on the fly.
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Figure 170. Counter timing diagram with prescaler division change from 1 to 2
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Figure 171. Counter timing diagram with prescaler division change from 1 to 4
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22.3.2
Basic timers (TIM6)
Counting mode
The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register),
then restarts from 0 and generates a counter overflow event.
An update event can be generate at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This avoids updating the shadow registers while writing new values into the preload
registers. In this way, no update event occurs until the UDIS bit has been written to 0,
however, the counter and the prescaler counter both restart from 0 (but the prescale rate
does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1
register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set
(so no interrupt or DMA request is sent).
When an update event occurs, all the registers are updated and the update flag (UIF bit in
the TIMx_SR register) is set (depending on the URS bit):
•
The buffer of the prescaler is reloaded with the preload value (contents of the
TIMx_PSC register)
•
The auto-reload shadow register is updated with the preload value (TIMx_ARR)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR = 0x36.
Figure 172. Counter timing diagram, internal clock divided by 1
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Figure 173. Counter timing diagram, internal clock divided by 2
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Figure 174. Counter timing diagram, internal clock divided by 4
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Basic timers (TIM6)
Figure 175. Counter timing diagram, internal clock divided by N
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Figure 176. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded)
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Figure 177. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)
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069
Clock source
The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 178 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
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Figure 178. Control circuit in normal mode, internal clock divided by 1
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22.3.4
Debug mode
When the microcontroller enters the debug mode (Cortex®-M0+ core - halted), the TIMx
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module. For more details, refer to Section 31.16.2: Debug
support for timers, watchdog, bxCAN and I2C.
22.4
TIM6 registers
Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in
register descriptions.
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
22.4.1
TIM6 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ARPE
Res.
Res.
Res.
OPM
URS
UDIS
CEN
rw
rw
rw
rw
rw
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:4 Reserved, must be kept at reset value.
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Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generates an update interrupt or DMA request if enabled.
These events can be:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
–
Counter overflow/underflow
–
Setting the UG bit
–
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if
a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: Gated mode can work only if the CEN bit has been previously set by software.
However trigger mode can set the CEN bit automatically by hardware.
CEN is cleared automatically in one-pulse mode, when an update event occurs.
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22.4.2
TIM6 control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
6
5
4
MMS[2:0]
rw
rw
3
2
1
0
Res.
Res.
Res.
Res.
rw
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:4 MMS: Master mode selection
These bits are used to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer
is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR
register).
010: Update - The update event is selected as a trigger output (TRGO). For instance a
master timer can then be used as a prescaler for a slave timer.
Bits 3:0 Reserved, must be kept at reset value.
22.4.3
TIM6 DMA/Interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
UDE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
UIE
rw
rw
Bit 15:9 Reserved, must be kept at reset value.
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bit 7:1 Reserved, must be kept at reset value.
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled.
1: Update interrupt enabled.
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22.4.4
RM0376
TIM6 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
UIF
rc_w0
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the
TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0
and UDIS = 0 in the TIMx_CR1 register.
22.4.5
TIM6 event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
UG
w
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initializes the timer counter and generates an update of the registers. Note that the
prescaler counter is cleared too (but the prescaler ratio is not affected).
22.4.6
TIM6 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
CNT[15:0]
rw
rw
Bits 15:0
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rw
rw
rw
rw
rw
rw
CNT[15:0]: Counter value
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22.4.7
TIM6 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15
14
13
12
11
10
9
8
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
PSC[15:0]
rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded into the active prescaler register at each update event.
22.4.8
TIM6 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
ARR[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded into the actual auto-reload register.
Refer to Section 22.3.1: Time-base unit on page 505 for more details about ARR update and
behavior.
The counter is blocked while the auto-reload value is null.
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0x1C
Res.
0x20
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x18
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Reset value
Reset value
DocID025941 Rev 1
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2.2 for the register boundary addresses.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
Reset value
UIF
Res.
Res.
0
UG
Res.
Res.
Res.
Res.
Res.
Res.
UIE
URS
UDIS
CEN
OPM
Res.
Res.
Res.
ARPE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
0
Res.
0
Res.
Res.
0
Res.
MMS[2:0
]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
UDE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x08
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIMx_PSC
Res.
0x28
TIMx_CNT
Res.
0x24
TIMx_EGR
Res.
0x14
TIMx_SR
Res.
0x10
TIMx_DIER
Res.
0x0C
TIMx_CR2
Res.
0x04
TIMx_CR1
Res.
0x00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
Res.
Offset
Res.
22.4.9
Res.
Basic timers (TIM6)
RM0376
TIM6 register map
TIMx registers are mapped as 16-bit addressable registers as described in the table below:
Table 81. TIM6 register map and reset values
0
0
0
0
0
0
CNT[15:0]
PSC[15:0]
ARR[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0376
Low power timer (LPTIM)
23
Low power timer (LPTIM)
23.1
Introduction
The LPTIM is a 16-bit timer that benefits from the ultimate developments in power
consumption reduction. Thanks to its diversity of clock sources, the LPTIM is able to keep
running whatever the selected power mode. Given its capability to run even with no internal
clock source, the LPTIM can be used as a “Pulse Counter” which can be useful in some
applications. Also, the LPTIM capability to wake up the system from low-power modes,
makes it suitable to realize “Timeout functions” with extremely low power consumption.
The LPTIM introduces a flexible clock scheme that provides the needed functionalities and
performance, while minimizing the power consumption.
23.2
23.3
LPTIM main features
•
16 bit upcounter
•
3-bit prescaler with 8 possible dividing factor (1,2,4,8,16,32,64,128)
•
Selectable clock
–
Internal clock sources: LSE, LSI, HSI16 or APB clock
–
External clock source over ULPTIM input (working with no LP oscillator running,
used by Pulse Counter application)
•
16 bit ARR autoreload register
•
16 bit compare register
•
Continuous/one shot mode
•
Selectable sw/hw input trigger
•
Programmable Digital Glitch filter
•
Configurable output: Pulse, PWM
•
Configurable I/O polarity
•
Encoder mode
LPTIM implementation
Table 82 describes LPTIM implementation on STM32L0x2 devices.
Table 82. STM32L0x2 LPTIM features
LPTIM modes/features(1)
Encoder mode
LPTIM1
X
1. X = supported.
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23.4
LPTIM functional description
23.4.1
LPTIM block diagram
Figure 179. Low Power Timer block diagram
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23.4.2
LPTIM reset and clocks
The LPTIM can be clocked using several clock sources. It can be clocked using an internal
clock signal which can be chosen among APB, LSI, LSE or HSI16 sources through the
Clock Tree controller (RCC). Also, the LPTIM can be clocked using an external clock signal
injected on its external Input1. When clocked with an external clock source, the LPTIM may
run in one of these two possible configurations:
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•
The first configuration is when the LPTIM is clocked by an external signal but in the
same time an internal clock signal is provided to the LPTIM either from APB or any
other embedded oscillator including LSE, LSI and HSI16.
•
The second configuration is when the LPTIM is solely clocked by an external clock
source through its external Input1. This configuration is the one used to realize Timeout
function or Pulse counter function when all the embedded oscillators are turned off
after entering a low-power mode.
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Low power timer (LPTIM)
Writing to CKSEL bit allows to determine whether the LPTIM will use an external clock
source or an internal one.
When configured to use an external clock source, the CKPOL bits are used to select the
external clock signal active edge. If both edges are configured to be active ones, an internal
clock signal should also be provided (first configuration). In this case, the internal clock
signal frequency should be at least four time higher than the external clock signal frequency.
23.4.3
Glitch filter
The LPTIM inputs, either external or internal, are protected with digital filters that prevent
any glitches and noise perturbations to propagate inside the LPTIM. This is in order to
prevent spurious counts or triggers.
Before activating the digital filters, an internal clock source should first be provided to the
LPTIM. This is necessary to guarantee the proper operation of the filters.
The digital filters are divided into two groups:
Note:
•
The first group of digital filters protects the LPTIM external inputs. The digital filters
sensitivity is controlled by the CKFLT bits
•
The second group of digital filters protects the LPTIM internal trigger inputs. The digital
filters sensitivity is controlled by the TRGFLT bits.
The digital filters sensitivity is controlled by groups. It is not possible to configure each digital
filter sensitivity separately inside the same group.
The filter sensitivity acts on the number of consecutive equal samples that should be
detected on one of the LPTIM inputs to consider a signal level change as a valid transition.
Figure 180 shows an example of glitch filter behavior in case of a 2 consecutive samples
programmed.
Figure 180. Glitch filter timing diagram
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Note:
In case no internal clock signal is provided, the digital filter must be deactivated by setting
the CKFLT and TRGFLT bits to ‘0’. In that case, an external analog filter may be used to
protect the LPTIM external inputs against glitches.
23.4.4
Prescaler
The LPTIM 16-bit counter is preceded by a configurable power-of-2 prescaler. The prescaler
division ratio is controlled by the PRESC[2:0] 3-bit field. The table below lists all the possible
division ratios:
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Table 83. Prescaler division ratios
23.4.5
programming
dividing factor
000
/1
001
/2
010
/4
011
/8
100
/16
101
/32
110
/64
111
/128
Trigger multiplexer
The LPTIM counter may be started either by software or after the detection of an active
edge on one of the 8 trigger inputs.
TRIGEN[1:0] is used to determine the LPTIM trigger source:
•
When TRIGEN[1:0] equals ‘00’, The LPTIM counter is started as soon as one of the
CNTSTRT or the SNGSTRT bits is set by software.
•
The three remaining possible values for the TRIGEN[1:0] are used to configure the
active edge used by the trigger inputs. The LPTIM counter starts as soon as an active
edge is detected.
When TRIGEN[1:0] is different than ‘00’, TRIGSEL[2:0] is used to select which of the 8
trigger inputs is used to start the counter.
The external triggers are considered asynchronous signals for the LPTIM. So after a trigger
detection, a two-counter-clock period latency is needed before the timer starts running due
to the synchronization.
If a new trigger event occurs when the timer is already started it will be ignored (unless
timeout function is enabled).
Note:
The timer must be enabled before setting the SNGSTRT/CNTSTRT bits. Any write on these
bits when the timer is disabled will be discarded by hardware.
23.4.6
Operating mode
The LPTIM features two operating modes:
•
The Continuous mode: the timer is free running, the timer is started from a trigger event
and never stops until the timer is disabled
•
One shot mode: the timer is started from a trigger event and stops when reaching the
ARR value.
A new trigger event will re-start the timer. Any trigger event occurring after the counter starts
and before the counter reaches ARR will be discarded.
To enable the one shot counting, the SNGSTRT bit must be set.
In case an external trigger is selected, an external trigger event arriving after SNGSTRT is
set will start the counter for one shot counting.
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Low power timer (LPTIM)
In case of software start (TRIGEN[1:0] = ‘00’), the SNGSTRT setting will start the counter for
one shot counting.
To enable the continuous counting, the CNTSTRT bit must be set.
In case an external trigger is selected, an external trigger event arriving after CNTSTRT is
set will start the counter for continuous counting.
In case of software start (TRIGEN[1:0] = ‘00’), setting CNTSTRT will start the counter for
continuous counting.
SNGSTRT and CNTSTRT bits can only be set when the timer is enabled (The ENABLE bit
is set to ‘1’). It is possible to change “on the fly” from One Shot mode to Continuous mode.
If the Continuous mode was previously selected, setting SNGSTRT will switch the LPTIM to
the One Shot mode. The counter (if active) will stop as soon as it reaches ARR.
If the One Shot mode was previously selected, setting CNTSTRT will switch the LPTIM to
the Continuous mode. The counter (if active) will restart as soon as it reaches ARR.
23.4.7
Timeout function
The detection of an active edge on one selected trigger input can be used to reset the
LPTIM counter. This feature is controlled through the TIMOUT bit.
The first trigger event will start the timer, any successive trigger event will reset the counter
and the timer will restart.
A low power timeout function can be realized. The timeout value corresponds to the
compare value; if no trigger occurs within the expected time frame, the MCU is waked-up by
the compare match event.
23.4.8
Waveform generation
Two 16-bit registers, the LPTIMx_ARR (autoreload register) and LPTIMx_CMP (Compare
register), are used to generate several different waveforms on LPTIM output
The timer can generate the following waveforms:
•
The PWM mode: the LPTIM output is set as soon as a match occurs between the
LPTIMx_CMP and the LPTIMx_CNT registers. The LPTIM output is reset as soon as a
match occurs between the LPTIMx_ARR and the LPTIMx_CNT registers
•
The One-pulse mode: the output waveform is similar to the one of the PWM mode for
the first pulse, then the output is permanently reset
•
The Set Once mode: the output waveform is similar to the One-pulse mode except that
the output is kept to the last signal level (depends on the output configured polarity).
The above described modes require that the LPTIMx_ARR register value be strictly greater
than the LPTIMx_CMP register value.
The LPTIM output waveform can be configured through the WAVE bit as follow:
•
Resetting the WAVE bit to ‘0’ forces the LPTIM to generate either a PWM waveform or
a One pulse waveform depending on which bit is set: CNTSTRT or SNGSTRT.
•
Setting the WAVE bit to ‘1’ forces the LPTIM to generate a Set Once waveform.
The WAVPOL bit controls the LPTIM output polarity. The change takes effect immediately,
so the output default value will change immediately after the polarity is re-configured, even
before the timer is enabled.
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Signals with frequencies up to the LPTIM clock frequency divided by 2 can be generated.
Figure 181 below shows the three possible waveforms that can be generated on the LPTIM
output. Also, it shows the effect of the polarity change using the WAVPOL bit.
Figure 181. Waveform generation
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23.4.9
Register update
The LPTIMx_ARR register and LPTIMx_CMP register are updated immediately after the
APB bus write operation, or at the end of the current period if the timer is already started.
The PRELOAD bit controls how the LPTIMx_ARR and the LPTIMx_CMP registers are
updated:
•
When the PRELOAD bit is reset to ‘0’, the LPTIMx_ARR and the LPTIMx_CMP
registers are immediately updated after any write access.
•
When the PRELOAD bit is set to ‘1’, the LPTIMx_ARR and the LPTIMx_CMP registers
are updated at the end of the current period, if the timer has been already started.
The APB bus and the LPTIM use different clocks, so there is some latency between the
APB write and the moment when these values are available to the counter comparator.
Within this latency period, any additional write into these registers must be avoided.
The ARROK flag and the CMPOK flag in the LPTIMx_ISR register indicate when the write
operation is completed to respectively the LPTIMx_ARR register and the LPTIMx_CMP
register.
After a write to the LPTIMx_ARR register or the LPTIMx_CMP register, a new write
operation to the same register can only be performed when the previous write operation is
completed. Any successive write before respectively the ARROK flag or the CMPOK flag be
set, will lead to unpredictable results.
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23.4.10
Low power timer (LPTIM)
Counter mode
The LPTIM counter can be used to count external events on the LPTIM Input1 or it can be
used to count internal clock cycles. The COUNTMODE bit controls which source will be
used for updating the counter.
In case the LPTIM is configured to count external events on Input1, the counter can be
updated following a rising edge, falling edge or both edges depending on the value written
to the CKPOL[1:0] bits.
The CKSEL bit determines how the LPTIM is clocked and also condition which edges of the
source signal can be used to update the counter:
•
CKSEL = 0: the LPTIM is clocked by an internal clock source.
When the LPTIM is configured to be clocked by an internal clock source and the LPTIM
counter is configured to be updated by active edges detected on the LPTIM external
Input1, the internal clock provided to the LPTIM must be not be prescaled (PRESC[2:0]
= ‘000’).
The LPTIM external Input1 is sampled with the internal clock provided to the LPTIM.
Consequently, in order not to miss any event, the frequency of the changes on the
external Input1 signal should never exceed the frequency of the internal clock provided
to the LPTIM.
•
CKSEL = 1: the LPTIM is clocked by an external clock source
In this configuration, the LPTIM has no need for an internal clock source. The signal
injected on the LPTIM external Input1 is used as system clock for the LPTIM. This
configuration is suitable for operation modes where no embedded oscillator is enabled.
For this configuration, the LPTIM counter can be updated either on rising edges or
falling edges of the input1 clock signal but not on both rising and falling edges.
Since the signal injected on the LPTIM external Input1 is also used to clock the LPTIM,
there is some initial latency (after the LPTIM is enabled) before the counter is
incremented. More precisely, the first five active edges on the LPTIM external Input1
(after LPTIM is enable) are lost.
23.4.11
Timer enable
The ENABLE bit located in the LPTIMx_CR register is used to enable/disable the LPTIM.
After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM is
actually enabled.
The LPTIMx_CFGR and LPTIMx_IER registers must be modified only when the LPTIM is
disabled.
23.4.12
Encoder mode
This mode allows handling signals from quadrature encoders used to detect angular
position of rotary elements. Encoder interface mode acts simply as an external clock with
direction selection. This means that the counter just counts continuously between 0 and the
auto-reload value programmed into the LPTIMx_ARR register (0 up to ARR or ARR down to
0 depending on the direction). Therefore you must configure LPTIMx_ARR before starting.
From the two external input signals, Input1 and Input2, a clock signal is generated to clock
the LPTIM counter. The phase between those two signals determines the counting direction.
The Encoder mode is only available when the LPTIM is clocked by an internal clock source.
The signals frequency on both Input1 and Input2 inputs must not exceed the LPTIM internal
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clock frequency divided by 4. This is mandatory in order to guarantee a proper operation of
the LPTIM.
Direction change is signalized by the two Down and Up flags in the LPTIMx_ISR register.
Also, an interrupt can be generated for both direction change events if enabled through the
LPTIMx_IER register.
To activate the Encoder mode the ENC bit has to be set to ‘1’. The LPTIM must first be
configured in continuous mode.
When Encoder mode is active, the LPTIM counter is modified automatically following the
speed and the direction of the incremental encoder. Therefore, its content always
represents the encoder’s position. The count direction, signaled by the Up and Down flags,
correspond to the rotation direction of the connected sensor.
According to the edge sensitivity configured using the CKPOL[1:0] bits, different counting
scenarios are possible. The following table summarizes the possible combinations,
assuming that Input1 and Input2 do not switch at the same time.
Table 84. Encoder counting scenarios
Active edge
Rising Edge
Falling Edge
Both Edges
Level on opposite
signal (Input1 for
Input2, Input2 for
Input1)
Input1 signal
Input2 signal
Rising
Falling
Rising
Falling
High
Down
No count
Up
No count
Low
Up
No count
Down
No count
High
No count
Up
No count
Down
Low
No count
Down
No count
Up
High
Down
Up
Up
Down
Low
Up
Down
Down
Up
The following figure shows a counting sequence for Encoder mode where both edges
sensitivity is configured.
Caution:
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In this mode the LPTIM must be clocked by an internal clock source, so the CKSEL bit must
be maintained to its reset value which is equal to ‘0’. Also, the prescaler division ratio must
be equal to its reset value which is 1 (PRESC[2:0] bits must be ‘000’).
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Low power timer (LPTIM)
Figure 182. Encoder mode counting sequence
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LPTIM interrupts
The following events generate an interrupt/wake-up event, if they are enabled through the
LPTIMx_IER register:
Note:
•
Compare match
•
Auto-reload match (whatever the direction if encoder mode)
•
External trigger event
•
Autoreload register write completed
•
Compare register write completed
•
Direction change (encoder mode), programmable (up / down / both).
if any bit in the LPTIMx_IER register (Interrupt Enable Register) is set after that its
corresponding flag in the LPTIMx_ISR register (Status Register) is set, the interrupt is not
asserted
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23.6
LPTIM registers
23.6.1
LPTIM Interrupt and Status Register (LPTIMx_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DOWN
UP
ARROK
CMPOK
EXTTRIG
r
r
r
r
r
ARRM CMPM
r
r
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 DOWN: Counter direction change up to down
In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has
changed from up to down.
Bit 5 UP: Counter direction change down to up
In Encoder mode, UP bit is set by hardware to inform application that the counter direction has
changed from down to up.
Bit 4 ARROK: Autoreload register update OK
ARROK is set by hardware to inform application that the APB bus write operation to the LPTIMx_ARR
register has been successfully completed. If so, a new one can be initiated.
Bit 3 CMPOK: Compare register update OK
CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIMx_CMP
register has been successfully completed. If so, a new one can be initiated.
Bit 2 EXTTRIG: External trigger edge event
EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger
input has occurred. If the trigger is ignored because the timer has already started, then this flag is not
set.
Bit 1 ARRM: Autoreload match
ARRM is set by hardware to inform application that LPTIMx_CNT register’s value reached the
LPTIMx_ARR register’s value.
Bit 0 CMPM: Compare match
The CMPM bit is set by hardware to inform application that LPTIMx_CNT register value reached the
LPTIMx_CMP register’s value.
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23.6.2
LPTIM Interrupt Clear Register (LPTIMx_ICR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DOWN
CF
UPCF
ARRO
KCF
ARRM
CF
CMPM
CF
w
w
w
w
w
CMPO EXTTR
KCF
IGCF
w
w
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 DOWNCF: Direction change to down Clear Flag
Writing 1 to this bit clear the DOWN flag in the LPT_ISR register
Bit 5 UPCF: Direction change to UP Clear Flag
Writing 1 to this bit clear the UP flag in the LPT_ISR register
Bit 4 ARROKCF: Autoreload register update OK Clear Flag
Writing 1 to this bit clears the ARROK flag in the LPT_ISR register
Bit 3 CMPOKCF: Compare register update OK Clear Flag
Writing 1 to this bit clears the CMPOK flag in the LPT_ISR register
Bit 2 EXTTRIGCF: External trigger valid edge Clear Flag
Writing 1 to this bit clears the EXTTRIG flag in the LPT_ISR register
Bit 1 ARRMCF: Autoreload match Clear Flag
Writing 1 to this bit clears the ARRM flag in the LPT_ISR register
Bit 0 CMPMCF: compare match Clear Flag
Writing 1 to this bit clears the CMP flag in the LPT_ISR register
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23.6.3
RM0376
LPTIM Interrupt Enable Register (LPTIMx_IER)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DOWNI
E
UPIE
ARRO
KIE
rw
rw
rw
CMPO EXTTR ARRMI CMPMI
KIE
IGIE
E
E
rw
rw
rw
rw
Bits 31:7 Reserved, must be kept at reset value.
B