datasheet for PUMA68FV32006 by Apta Group

datasheet for PUMA68FV32006 by Apta Group
1M x 32 FLASH MEMORY
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Features
• Fast Access Times of 90/120/150 ns.
• Output Configurable as 32 / 16 / 8 bit wide.
• Operating Power 660/330/165 mW (Max).
• Low Power Standby 1.1mA (Max).
• Industrial and Military (Restricted) grade parts.
• Automatic Write/Erase by Embedded Algorithm - end
of Write/Erase indicated by DATA Polling and Toggle
Bit.
• Flexible Sector Erase Architecture - 64K byte sector
size, with hardware protection of any number of
sectors.
• 3.3V operation, 3.3V program.
• Single Byte Program Time of 9µS (Typ).
• Sector Program Time of 1sec (Typ).
• Erase/Write Cycle Endurance 100,000 (Min).
Block Diagram (see page 20 for 'A' version)
Pin Definition (see page 20 for 'A' version)
NC
A0
A1
A2
A3
A4
A5
CS3
GND
CS4
WE
A6
A7
A8
A9
A10
Vcc
Description
The PUMA 68FV32006 is a high density 32Mbit
CMOS 3.3V Only FLASH memory organised as 1M
x 32 in a JEDEC 68 pin surface mount PLCC, with
read access times of 90, 120, and 150ns. The
plastic device is screened to ensure high reliability.
The output width is user configurable as 8 , 16 or 32
bits using four Chip Selects (CS1~4) for optimum
application flexibility.
The device incorporates Embedded Algorithms for
Program and Erase with Sector architecture (64K
sector) and supports full chip erase.
The PUMA 68FV32006 also features hardware
sector protection, which disables both program and
erase operations in any of the 32 sectors on the
device.
A0~A19
OE
WE
1M x 8
1M x 8
1M x 8
1M x 8
FLASH
FLASH
FLASH
FLASH
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
VIEW
17
53
FROM
18
52
19
51
ABOVE
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PUMA 68FV32006
Vcc
A11
A12
A13
A14
A15
A16
CS1
OE
CS2
A17
NC
NC
NC
A18
GND
A19
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
A0-A19
CS1-4
OE
GND
Address Input
Chip Enables
Output Enable
Ground
Pin Functions
D0-D31
WE
Vcc
Data Inputs/Outputs
Write Enable
Power (+3.3V)
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
Absolute Maximum Ratings (1)
Range
-0.5 to +Vcc+0.5
-0.5 to +4.0
-0.5 to +12.5
-65 to +150
Voltage on any pin w.r.t. Gnd
Supply Voltage (2)
Voltage on A9, OE, Reset w.r.t. Gnd (3)
Storage Temperature
Notes : (1)
(2)
(3)
unit
V
V
V
°C
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operationof the device at those or any other conditions above those indicated in the operational sections of this specification
is not implied.
Minimum DC voltage on any input or I/O pin is -0.5V. Maximum DC voltage on output and I/O pins is Vcc+0.5V
During transitions voltage may overshoot to Vcc +1.0V for periods of 10ns
Minimum DC input voltage on A9,OE, Reset is -0.5V during voltage transitions, A9,OE, Reset may overshoot Vss to -1V
for periods of up to 10ns, maximum DC input voltage on A9 is 12.5V which may overshoot to 14.0V for periods up to 10ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
VCC
VIH
VIL
TA
TAI
TAM
min
3.0
0.7VCC
-0.5
0
-40
-55
typ
3.3
-
max
3.6
VCC+0.3
0.8
70
85
115
unit
V
V
V
°C
O
C (-I suffix)
O
C (-M suffix)
DC Electrical Characteristic (TA=-55oC to +115oC, Vcc=3.3V + 10%)
Parameter
Symbol Test Condition
I/P Leakage CurrentAddress, OE, WE ILI1
A9 Input Leakage Current
ILI2
Other Pins ILI3
Output Leakage Current
ILO
VCC Read Current
32 bit ICCO32
16 bit ICCO16
8 bit ICCO8
VCCWrite Current
32 bit
16 bit
8 bit
Standby Supply Current
Autoselect / Sector Unprotect Voltage
Output Low Voltage
Output High Voltage
Low VCC Lock-Out Voltage
ICCP32
ICCP16
ICCP8
ISB1
VID
VOL
VOH1
VLKO
min
-
±4
140
±4
±4
64
32
16
µA
µA
µA
µA
mA
mA
mA
-
-
120
60
30
mA
mA
mA
11.5
0.85Vcc
2.3
-
40
12.5
0.45
2.5
µA
V
V
V
V
VCC=VCC max, A9=12.5V
VCC=VCC max, VIN=0V or VCC
VCC=VCC max, VOUT=0V or VCC
CS=VIL(1), OE=VIH, IOUT=0mA, f=5MHz
As above
As above
Programming in Progress
As above
As above
VCC=VCC max, CS(1),Reset=Vcc + 0.3V
IOL=4mA. VCC = VCC min.
IOH=-2.0mA. VCC = VCC min.
unit
-
VCC=VCC max, VIN=0V or VCC
VCC = 3.3V
typ max
Notes (1) CS above are accessed through CS1-4. These inputs must be operated simultaneously for 32 bit operation,
in pairs in 16 bit mode and singly for 8 bit mode.
2
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
Capacitance (TA=25°C,f=1MHz)
Parameter
Symbol
Test Condition
Input CapacitanceAddress, OE, WE
Other pins
CIN1
CIN2
VIN=0V
VIN=0V
Output Capacitance
COUT8
VOUT=0V
8 bit
typ
max
Unit
-
35
10
pF
pF
-
52
pF
Note: These parameters are calculated, not measured.
AC Test Conditions
* Input pulse levels : 0.0V to 3.0V
* Input rise and fall times : 5 ns
* Input and output timing reference levels : 1.5V
* VCC = 3.3V +/- 10%
* Module tested in 32 bit mode
I/O Pin
166 Ω
1.76V
30pF
3
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
AC OPERATING CONDITIONS
Read Cycle
Parameter
90
typ
-
max
-
min
120
120
typ
-
max
-
min
150
150
typ
-
max Unit
- ns
Read Cycle Time
tRC
min
90
Address to output delay
tACC
-
-
90
-
-
120
-
-
150 ns
Chip enable to output
tCE
-
-
90
-
-
120
-
-
150 ns
Output enable to output
tOE
-
-
40
-
-
50
-
-
55 ns
Output enable to output High Z
tDF
-
-
30
-
-
35
-
-
40 ns
Output hold time from address
tOH
0
-
-
0
-
-
0
-
-
min
90
0
50
50
0
0
0
0
0
50
30
50
90
typ
9
1
-
max
-
min
120
0
55
55
0
0
0
0
0
55
30
50
120
typ
9
1
-
max
-
min
150
0
65
65
0
0
0
0
0
65
35
50
150
typ
9
1
-
max
-
ns
CS or OE whichever occurs first
Write/Erase/Program
Parameter
Symbol
Write Cycle time (4)
Address Setup time
Address Hold time
Data Setup Time
Data hold Time
Output Enable Setup Time
Read Recover before Write
CS setup time
CS hold time
WE Pulse Width
WE Pulse Width High
Programming operation
Sector Erase operation (1)
VCC setup time (4)
tWC
tAS
tAH
tDS
tDH
tOES
tGHWL
tCE
tCH
tWP
tWPH
tWHWH1
tWHWH2
tVCS
Notes: (1) This does not include the preprogramming time.
(2) Not 100% tested.Under Development.
Under Development.
4
unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
Write/Erase/Program Alternate CS controlled Writes
Symbol
min
90
typ
max
min
120
typ
max
min
150
typ
tWC
90
-
-
120
-
-
150
-
-
ns
Address Setup time
tAS
0
-
-
0
-
-
0
-
-
ns
Address Hold time
tAH
50
-
-
55
-
-
65
-
-
ns
Data Setup Time
tDS
50
-
-
55
-
-
65
-
-
ns
Data hold Time
tDH
0
-
-
0
-
-
0
-
-
ns
Output Enable Setup Time
tOES
0
-
-
0
-
-
0
-
-
ns
Read Recover before Write
tGHEL
0
-
-
0
-
-
0
-
-
ns
WE setup time
tWS
0
-
-
0
-
-
0
-
-
ns
WE hold time
tWH
0
-
-
0
-
-
0
-
-
ns
CS Pulse Width
tCP
50
-
-
55
-
-
65
-
-
ns
CS Pulse Width High
tCPH
30
-
-
30
-
-
35
-
-
ns
tWHWH1
-
9
-
-
9
-
-
9
-
us
tWHWH2
-
1
-
-
1
-
-
1
-
sec
Parameter
Write Cycle time
(2)
Programming operation
Sector Erase operation
(1)
Note: (1) Does not include pre-programming time.
(2) Not 100% tested.
Under Development.
5
max Unit
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
AC Waveforms for Read Operation
t RC
Addresses Stable
Addresses
t ACC
CE
t DF
t OE
OE
t OH
t CE
WE
High Z
Outputs
High Z
Output Valid
AC Waveforms Program
Data Polling
Address
PA
5555H
tWC
t AS
PA
tAH
tRC
CE
t GHWL
OE
t WP
t WHWH1
t WHP
t OE
CE
t CS
t DF
t DH
DATA
A0H
PD
DQ7
D OUT
tDS
VCC
t OE
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the out put of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
6
t OH
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
A.C Waveforms - Alternate CS controlled Program operation timings
Data Polling
PA
555
Address
tWC
t AS
PA
tAH
tRC
WE
t GHEL
OE
t CP
t WHWH1 OR 2
t CHP
t OE
CE
t WS
t DH
DATA
A0
PD
DQ7
DDOUT
OUT
tDS
t OH
VCC
NOTES:
1. PA is address of memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
AC Waveforms for Data Polling During Embedded Algorithm Operations
tCH
CE
t DF
tOE
OE
tOEH
t CE
WE
tOH
*
DQ7
DQ7=
Valid Data
DQ7
HIGH Z
t WHWH 1 or 2
DQ0-DQ6
= Invalid
DQ0-DQ6
DQ0-DQ7=
Vaild Data
tOE
7
HIGH Z
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
AC Waveforms for Toggle Bit During Embedded Algorithm Operations
CE
WE
tOEH
OE
*
DATA
(DQ0-DQ7)
DQ6=Toggle
tOH
DQ6=
Stop Toggling
DQ6=Toggle
DQ0-DQ7
Valid
t OE
* DQ6 stops toggling ( the device has completed the embedded operations)
AC Waveforms Chip / Sector Erase
tAS
Address
5555H
tAH
2AAAH
5555H
5555H
2AAAH
80H
AAH
55H
SA
CE
tGHWL
OE
tWP
WE
tWPH
tCS
tDH
Data
Vcc
tDS
AAH
55H
tVCS
NOTES:
1. SA is the address for sector erase. Addresses = don't care for Chip Erase.
8
30H
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
EMBEDDED PROGRAMMING ALGORITHM
Start
Write Program Command
Sequence
(see below)
Data Poll Device
Increment Address
No
Last
Address
?
Yes
Programming
Completed
EMBEDDED ERASE ALGORITHM
START
Write Erase Command Sequence
See below
Data Poll or Toggle Bit
Successfully Completed
Erasure Completed
9
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
DATA POLLING ALGORITHM
START
Read Byte
(DQ0-DQ7)
Addr =VA
DQ7 = Data ?
YES
NO
NO
DQ5 = 1 ?
YES
Read Byte
(DQ0-DQ7)
Addr =VA
DQ7 = Data ?
YES
PASS
NO
FAIL
NOTE:
1. DQ7 is rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
2. VA = Byte address for programming.
= Any of the sector addresses within the sector being erased during sector erase operation
= XXXXXH during chip erase
TOGGLE BIT ALGORITHM
START
Read Byte
(DQ0-DQ7)
NO
DQ6=Toggle ?
YES
NO
DQ5 = 1 ?
YES
Read Byte
(DQ0-DQ7) twice
Note (1,2)
DQ6=Toggle ?
NO
PASS
YES
FAIL
NOTES:
1. DQ6 is rechecked even if DQ5 = 1 because DQ6 may stop toggling at the same time as DQ5 changing to "1".
2 Read toggle bit twice to determin wether or not it is toggling.
10
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
TEMPORARY SECTOR UNPROTECT WAVEFORM
12 V
RESET
0 OR 3 V
0 OR 3 V
t V I DR
t V I DR
Program or Erase Command Sequence
CE
WE
tRSP
RY/BY
11
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
DEVICE OPERATION
The following description deals with the device operating in 8 bit mode accessed through CS1,
however status flag definitions shown apply equally to the corresponding flag for each device in the module.
Read Mode
The device has two control functions which must be satisfied in order to obtain data at the outputs
CS1-4 is the power control and should be used for device selection
OE is the output control and should be used to gate data to the output pins if the device is selected.
Standby Mode
Two standby modes are available :
CMOS standby : CS1-4 held at Vcc +/- 0.3V
TTL standby : CS1-4 held at VIH
In the standby mode the outputs are in a high impedance state independent of the OE input. If the device is
deselected during erasure or programming the device will draw active current until the operation is completed.
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7 - DQ0. This mode is primarily intended for programing equipment to
automaticly match a device to be programed with its corresponding programing algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID (11.5V to 12.5V) on address pin A9.
Address pins A6, A1 and A0 must be as shown in the table below. In addition, when verifying sector protection,
the sector address must appear on the appropriate highest order address bits. The table below shows the
remaining address bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7 - DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the
command register, as shown in command definitions table. This method does not require VID.
Description
Sector Protection Verification
CE
L
OE
L
WE
H
A19
A12
A8
A5
TO
TO
TO
TO
A13
A10
SA
X
A9
VID
A7
X
A6
L
A2
X
DQ7
TO
A1
H
A0
L
DQ0
01H
(PROTECTED)
00H
(UNPROTECTED)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care
Write
Device erasure and programming are accomplished via the command register. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The
register is a latch used to store the commands along with the address and data information required to execute
the command. The command register is written by bringing WE/WE1-4 to VIL while CS1-4 is at VIL and
OE is at VIH.Addresses are latched on the falling edge of WE/WE1-4 while data is latched on the rising edge.
12
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
COMMAND DEFINITIONS
Command
Sequence
Bus
Write
Cycles
Req'd
First Bus
Write Cycle
Addr
Data
Bus Cycles (Notes 2-4)
Fourth Bus
Read/Write
Cycle
Second Bus
Write Cycle
Addr
Data
Third Bus
Write Cycle
Addr
Data
Addr
Data
Fifth Bus
Write Cycle
Addr
Data
Sixth Bus
Write Cycle
Addr
Data
Read (Note 5)
1
RA
RD
Reset
1
XXX
FO
4
XXX
XXX
AA
XXX
XXX
55
XXX
XXX
90
(SA)
X02
00
01
Program
4
XXX
AA
XXX
55
XXX
A0
PA
PD
Chip Erase
6
XXX
AA
XXX
55
XXX
80
XXX
AA
XXX
55
XXX
10
Sector Erase
6
XXX
AA
XXX
55
XXX
80
XXX
AA
XXX
55
SA
30
Autoselect
(Note 7)
S ect or P ro t e ct
V eri fy (Note 8)
Sector Erase Suspend (Note 9)
1
Erase can be suspended during sector erase with Addr (don't care) Data (B0)
Sector Erase Resume (Note 10)
1
Erase can be resumed after suspend with Addr (Don't Care), Data (30)
NOTES:
2.
3.
4.
5.
6.
All values are in hexadecimal.
Except when reading array or autoselect data, all bus cycles are write operations.
All address bits are don't cares for unlock and command cycles, except when SA or PA required.
No unlock or command cycles required when reading array data.
The reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes
high (while device is providing status data.
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector.
9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase
Suspend mode. The Erase Suspend command is valid only during a sector erase operation.
10. The Erase Resume command is valid only during the Erase Suspend mode.
Read / Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads
until the command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for specific timing parameters.
Sector Unprotect
Sectors which have previously been protected from being programmed or erased may be unprotected using
the Sector Unprotect Algorithm. All sectors must be placed in the protection mode using the protection
algorithm before unprotection can proceed.
A special high voltage for unprotection VSP is defined to be 12V+/-0.5V.
The unprotection mode is entered by setting OE to VID or VSP, WE to VSP, A5 to VIH and A0=A9 to VIL. Unprotect
is invoked by applying to negative pulses on CS for a period of tWPP2.
13
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
Sector Protection
The device features hardware sector protection. This feature will disable both program and erase operations in
any sector. The sector protect feature is enabled using programming equipment at the users site. The device
is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, and
CS=VIH. The sector adresses (A19, A18, A17 and A16) should be set to the sector to be protected. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising
edge of the same. Sector addresses must be held constant during the WE pulse.
To verify programming of the protection equipment circuitry, the programming equipment must force VID on
address pin A9 with CE and OE at VIL and WE at VIH. Reading the device at a particular sector address (A16,
A17, A18 and A19) while (A6,A1,A0) = (0,1,0) will produce 01H at data output D0 for a protected sector.
Otherwise the device will read 00H for unprotected sector. In this mode, the lower order addresses, except for
A0, A1 and A6 , are don't care. Address with A1=VIL are reserved for autoselect codes.
It is also possible to determine if a sector is protected in the system by writing the autoselect command.
Performing a read operation at XX02H , where the higher order addresses (A16, A17, A18 and A19) are sector
addresses,(other addresses are a don't care) will produce 01H data if those sectors are protected. Otherwise
the devidce will read 00H for an unprotected sector.
Sector Address Table
A19
A18
A17
A16
A d d re s s R a n g e
SA0
0
0
0
0
0 0 0 0 0 h -0 F F F F h
SA1
0
0
0
1
1 0 0 0 0 h -1 F F F F h
SA2
0
0
1
0
2 0 0 0 0 h -2 F F F F h
SA3
0
0
1
1
3 0 0 0 0 h -3 F F F F h
SA4
0
1
0
0
4 0 0 0 0 h -4 F F F F h
SA5
0
1
0
1
5 0 0 0 0 h -5 F F F F h
SA6
0
1
1
0
6 0 0 0 0 h -6 F F F F h
SA7
0
1
1
1
7 0 0 0 0 h -7 F F F F h
SA8
1
0
0
0
8 0 0 0 0 h -8 F F F F h
SA9
1
0
0
1
90000h9FFFFh
S A 10
1
0
1
0
A 0 0 0 0 h -A F F F F h
S A 11
1
0
1
1
B 0 0 0 0 h -B F F F F h
S A 12
1
1
0
0
C 0 0 0 0 h -C F F F F h
S A 13
1
1
0
1
D 0 0 0 0 h -D F F F F h
S A 14
1
1
1
0
E 0 0 0 0 h -E F F F F h
S A 15
1
1
1
1
F 0 0 0 0 h -F F F F F h
14
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
Autoselect Command
The Autoselect command sequence allows the host system to access the manufacturer and devices codes,
and determine whether or not a sector is protected. See Command definitions table. This method is an
alternative to that shown in the autoselect codes table, which is intended for PROM programmers and requires
VID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect mode, and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle containing a sector address (SA) and the address 02h in it, returns 01h if that sector is protected,
or 00h if it is unprotected. Refer to sector address table for valid sector address.
The system must write the reset command to exit the autoselect mode and return to reading array data.
Byte Programming
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock
write cycles, followed by the program set-up command. The program address and data are writen next, which
in turn initiate the Embeded Program Algorithm. The system is not required to provide further controls or
timings. The device automaticlly provides internally generated program pulses and verify the programmed cell
margin. Command definitions table shows the address and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or
DQ6. See "Write Operation Status" for information on these status bits.
Any commands writen to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediatly terminates the programming opperation. The program command sequence should be
reinitiated once the device has reset to reading data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot from a "0" back to a "1".
Attempting to do so may halt the opperation and set DQ5 to "1", or cause the data Polling Algorithm to indicate
the opperation was sucessful. However, a succeeding read will show that the data is still "0". Only erase
operations can convert a "0" to a "1".
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase doesn't require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device automatically will program and verify the entire memory for an all
zero data pattern prior to electrical erase. The systems is not required to provide any controls or timings during
these operations.
Any commands written to the chip during the Embeded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately terminates the operation. The chip Erase Command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6 or DQ2. See "Write Operation
Status" for information on these status bits. When the Embeded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer latched.
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PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
Sector Erase
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector erase command. The command definitions table shows the
addresses and data requirements for the sector erase command sequence.
The device does not require the system to preprogram the memory prior to erase. The Embeded Erase
Algorithm automaticlly programs and verifies the sector for an all zero data pattern prior to electrical erase.
The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50ms begins. During the time-out period,
additional sector addresses and sector erase commands may be writen. Loading the sector erase buffer may
be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between
these additional cycles must be less than 50ms, otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended that the processor interrupts be disabled during this time
to ensure all commands are accepted. The interupts can be re-enabled after the last Sector Erase command
is writen. If the time between additional sector erase commands can be assumed to be less than 50ms, the
system need not monitor DQ3. Any command other than Sector Erase Suspend during the time-out
period resets the device to reading array data. The system must rewrite the command sequence and any
additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out. The time-out begins from
the rising edge of the final WE pulse in the command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the sector erase operation immediately terminates the
operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embeded Erase algorithm is complete, the device returns to reading array data and addresses are
no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6 or DQ2.
Erase Suspend
The Erase Suspend Command allows the system to interupt a sector erase operation and then read data
from, or program data to, any sector not selected for erasure. This command is valid only during the sector
erase operation, including the 50µs time out period during the sector erase command sequence. The Erase
Suspend Command is ignored if written during the chip erase operation or Embeded Program algorithm.
Writing the Erase Suspend command during the sector erase time-out immediately terminates the time-out
period and suspends the erase operation. Addresses are "don't-cares" when writing the Erase Suspend
command.
When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20µs to suspend the erase operation. However, when the Erase Suspend command is written during
the sector erase time-out, the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the system can read array data from or program data to any
sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read
and write timings and command definitions apply. Reading at any address within erase-suspended sectors
produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a
sector is actively erasing or is erase suspended.
After an erase-suspended program operation is complete, the system can once again read array data within
non-suspended sectors. The system can determine the status of the program operation.
16
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
The system may also write the autoselect command sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes
are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the
Erase Suspend mode, and is ready for another valid operation.
The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further writes of the resume command are ignored. Another
Erase Suspend command can be writen after the device has resumed erasing.
WRITE OPERATIONS STATUS
DQ7 (2)
DQ6
DQ5(1)
DQ3
DQ2(2)
DQ7
Toggle
0
N/A
No Toggle
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
Reading within Erase
Suspended Sector
1
No Toggle
0
N/A
Toggle
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
Erase Suspend Program
DQ7
Toggle
0
N/A
N/A
Operation
Embedded Program Algorithm
Standard
Mode
Erase
Suspend
Mode
Notes:
1. DQ5 switches to '1' when an Embedded Program or Embedded Erase operation has exceeded
the maximum timing limits.
2. DQ7 and DQ2 require a valid address when reading status information.
D7 Data Polling
The device features Data Polling as a method to indicate to the host system that the Embedded Algorithms are
in progress or completed.
During the Embedded Programming Algorithm, an attempt to read the device will produce complement data of
the data last written to D7. Upon completion of the Embedded Programming Algorithm an attempt to read the
device will produce the true data last written to D7. Data Polling is valid after the rising edge of the forth WE
pulse in the four write pulse sequence.
During the Embedded Erase Algorithm, D7 will be "0" until the erase operation is completed. Upon completion
the data at D7 is "1". For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the
six write pulse sequence. For sector erase, Data Polling is valid after the last rising edge of the sector erase
WE pulse.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, or sector erase time-out.
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PUMA 68FV32006/A - 90/12/15
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D6 Toggle Bit
The device also features the "toggle bit" as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read data from the device will
result in D6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is
completed, D6 will stop toggling and valid data will be read on successive attempts. During programming, the
Toggle bit is valid after the rising edge of the forth WE pulse in the four write command pulse sequence. For
chip erase, the Toggle bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is
active during the sector time-out.
D5 Exceeding Time Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under
these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously
programmed to "0." Only an erase operation can change a "0" back to a "1". Under this condition, the
device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a "1."
Under both these conditions, the system must issue the reset command to return the device to reading array
data.
D3 Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may be
used to determine if the sector erase timer window is still open. If D3 is high the internally controlled erase
cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If D3 is low , the device will accept additional
sector erase commands. To insure the command has been accepted, the software should check the status of
D3 prior to and following each subsequent sector erase command. If D3 were high on the second status
check, the command may not have been accepted.
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PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
DATA PROTECTION
The device is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its controls register architecture , alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power up
and power down transitions or system noise.
Low VCC Write Inhibit
When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc powerup and power-down. The command register and all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored untill Vcc is greater than VLKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when Vcc is greater than VLKO.
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on OE, CS, WE will not initiate a write cycle
Logical Inhibit
Writing is inhibited by holding any one of OE=VIL, CS=VIH or WE=VIH. To initiate a write cycle CS and WE
must be logical zero while OE is a logical one.
Power Up Write Inhibit
Power-up of the device with WE=CS=VIL and OE=VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
Sector Protect
Sectors of the device may be hardware protected at the users factory. The protection circuitry will disable both
program and erase functions for the protected sector(s). Requests to program or erase a protected sector will
be ignored by the device.
ERASE AND PROGRAMMING PERFORMANCE
Limits
Typ(1)
Max(2)
Unit
Sector Erase Time
1
15
sec
Excludes 00H programming
prior to erasure
Byte Programming Time
9
300
us
Excludes System level
Overhead
Chip Programming Time
9
27
sec
Excludes System level
Overhead
Parameter
Erase/Program Time
Chip Erase Time
Min
100,000
1,000,000
cycles
16
sec
Notes : (1) 25OC, 3V VCC, 100,000 cycles.
(2) Under work conditions 0f 90OC, VCC 2.7V, 100,000 Cycles
19
Comments
10,000 Min.
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
Version 'A' Block Diagram
NC
A0
A1
A2
A3
A4
A5
CS3
GND
CS4
WE1
A6
A7
A8
A9
A10
Vcc
Version 'A' Pin Definition
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
VIEW
17
53
FROM
18
52
19
51
ABOVE
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PUMA 68FV32006A
WE4
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
WE3
WE2
WE1
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
Vcc
A11
A12
A13
A14
A15
A16
CS1
OE
CS2
A17
WE2
WE3
WE4
A18
GND
A19
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
A0~A19
OE
20
1M x 8
1M x 8
1M x 8
1M x 8
FLASH
FLASH
FLASH
FLASH
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
Package Details
68 'J' Leaded Surface Mount Hi-Rel Plastic Package
25.40 (1.000)
24.89 (0.980)
1.27
(0.050) Typ.
0.43
(0.017) Typ.
24.13 (0.950)
23.11 (0.910)
5.08 (0.200)
Max.
1.02 (0.040)
Typ.
Ordering Information
PUMA 68FV32006AM-90
Speed
90 = 90 ns
12 = 120 ns
15 = 150 ns
Temp. range/screening Blank = Commercial Temperature
I = Industrial Temperature
M = Military Temperature (Restricted)
WE Option
Blank = Single WE
A = WE1~WE4
Organisation
32006 = 1M x 32, user confiurable as
2M x 16 and 4M x 8
Technology
Package Type
FV = FLASH MEMORY
(3.3V Operation)
PUMA 68= 68 pin "J" Leaded PLCC
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create any
warranty of merchantibility or fitness for aparticular purpose.
Our products are subject to a constant process of development. Data may be changed without notice.
Products are not authorised for use as critical components in life support devices without the express written approval of a
company director.
21
PUMA 68FV32006/A - 90/12/15
Issue 1.4 : May 2001
Visual Inspection Standard
All devices inspected to ANSI/J-STD-001B Class 2 standard
Moisture Sensitivity
Devices are moisture sensitive.
Shelf Life in Sealed Bag 12 months at <40OC and <90% relative humidity (RH).
After this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or
equivalent processing (peak package body temp 220OC) must be :
A : Mounted within 72 Hours at factory conditions of <30OC/60% RH
OR
B : Stored at <20% RH
If these conditions are not met or indicator card is >20% when read at 23OC +/-5% devices require baking
as specified below.
If baking is required, devices may be baked for :A : 24 hours at 125OC +/-5% for high temperature device containers
OR
B : 192 hours at 40OC +5OC/-0OC and <5% RH for low temperature device containers.
Packaging Standard
Devices packaged in dry nitrogen, JED-STD-020.
Packaged in trays as standard.
Tape and reel available for shipment quantities exceeding 200pcs upon request.
Soldering Recomendations
IR/Convection -
Ramp Rate
Temp. exceeding 183OC
Peak Temperature
Time within 5OC of peak
Ramp down
6OC/sec max.
150 secs. max.
225OC
20 secs max.
6OC/sec max.
Vapour Phase -
Ramp up rate
Peak Temperature
Time within 5OC of peak
Ramp down
6OC/sec max.
215 - 219OC
60 secs max.
6OC/sec max.
The above conditions must not be exceeded.
Note : The above recommendations are based on standard industry practice. Failure to comply with
the above recommendations invalidates product warranty.
22
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