System - XMC4000 System

XMC4000 System

Agenda



XMC4000 and ARM Cortex-M4



Memories



Bus System



Interrupt System



Clock



Reset



Power

2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 2

Agenda






Memories



Bus System



Interrupt System



Clock



Reset



Power


XMC4000 Block Diagram

2015-01-23

XMC4000 is based on a Cortex-M4 architecture with a rich peripheral set for communication and sensor/actuator applications.

Copyright © Infineon Technologies AG 2015. All rights reserved. Page 4

Architecture of Cortex-M4

Highlights

Cortex-M4 is a high efficiency processor core with 1.25 DMIPS/MHz. Due to the

Thumb-2 instruction set it reaches excellent code density.

Its optimised interrupt controller allows use in hard real-time applications.

Widespread standard core offers a broad variety of software tools and components.

Key Feature

Standard core

Customer Benefits

Availability of third party tools, software libraries and engineering force

DSP instruction set

Offers computing performance for realtime applications

Single precision floating point unit

2015-01-23

Avoids complex scaling and allows direct programming in C-language



Standard Core (1/2)

Integrated Nested Vectored

Interrupt Controller and

SYSTICK Timer

Central Core (including DSP)

1.25 DMIPS/MHz

Thumb-2 / Thumb ISA

Single Cycle MAC

Floating Point Unit

Single precision

Memory Protection

Unit (MPU)

8-Region

Debug Access Port:

JTAG or Serial Wire

Data Watch Point and

Trace Unit (DWT)

4x Data Watchpoints

&

Event Monitors

Embedded Trace

Macrocell (ETM) for

Instruction Trace

Instrumentation Trace

Macrocell (ITM ) for

Data Trace via Single

Wire Output

Flash Patch &

Breakpoint Unit

8x Hardware

Breakpoints

2x AHB-Lite Buses

I_CODE (Instruction Code Bus)

D_CODE (Data/Coefficients Code Bus)

1x AHB-Lite Bus

SYSTEM (SRAM & Fast Peripherals)

1x APB Bus

ARM Peripheral Bus (Internal & Slow Peripherals)

Source: http://www.arm.com



Standard Core (2/2)

Cortex-M Architecture Comparison

ARM

Cortex-M

Cortex-M0

Cortex-M3

Cortex-M4

Thumb

Most

Entire

Entire

Thumb-2

Subset

Entire

Entire

ARM

Cortex-M

Hardware multiply

Cortex-M0 1 or 32 cycle

Cortex-M3

1 cycle

Cortex-M4

1 cycle

Hardware divide

No

Yes

Yes

Source: Wikipedia

2015-01-23

ARM architecture

ARMv6-M

ARMv7-M

ARMv7E-M

Saturated math

No

Yes

Yes

Copyright © Infineon Technologies AG 2015. All rights reserved.

DSP extensi ons

No

No

Yes

Core architecture

Von Neumann

Harvard

Harvard

Floatingpoint

No

No

Optional

Page 7


DSP Instruction Set (1/2)


2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved.

Cortex-M4F is an

ARMv7E-M architecture.

It has a full

Thumb and

Thumb-2 instruction set.

Cortex-M4F has a single precision floating point unit.

Page 8


DSP Instruction Set (2/2)



Single

Cycle

MAC

Instructions

Page 9


Single Precision Floating Point Unit



Cortex-M4 SIMD + FPU



Fix point: ~2x faster



Floating point: ~10x faster

CMSIS DSP Library Benchmark: Cortex-M3 vs. Cortex-M4

FIR q15 fixed point

PID q15 fixed point

IIR q31 fixed point

Matrix Mul fixed point

Cycles: smaller numbers are better


2015-01-23

Cortex-M3 Cortex-M4


Correlation floating point

Memory Access Cycles

Page 10


CPU Performance Benchmark

400

Coremark

(The higher the better)

XMC4

@120 MHz,

3 WS

2015-01-23

7759

CRC Routine

(The lower the better) clock cycles millisec

5681

3681

3100

119

XMC4000

Flash cached

XMC4000

Flash uncached

47.3

XMC1000

Flash

XMC1

@32 MHz,

1.3 WS

65

XMC4000

Flash uncached

31

XMC4000

Flash cached

178

XMC1000

Flash

97

XMC1000

RAM

XMC4

@120 MHz,

3 WS


XMC1

@32 MHz,

1.3 WS

Page 11

Agenda






Memories



Bus System



Interrupt System



Clock



Reset



Power


Memories

BootROM

PSRAM

Memories

DSRAM1

DSRAM2

Flash

Cache

Highlights

The memory map is based on standard ARM

Cortex-M4 system memory map.

The peripherals are memory mapped into the linear address space. The on-chip memories provide zero wait state accesses to code and data. Flash module has very high performance with low latency. With the external bus interface (EBU), memory can be extended to 65 MBytes.

Key Feature Customer Benefits

Flash acceleration with cache

Parity protected RAM and ECC protected Flash

Flash IP protection

2015-01-23

Integrated cache reduces code execution time and saves power

High code/data integrity due to hardware error detection and correction mechanism.

Protect against unauthorized read-out of memory content


Memories

Flash acceleration with cache (1/2)



256 bit data buffer



Single line



Critical word first, streaming



4 KByte instruction buffer



2 way set associative, 256 bit line



Bypass and invalidation supported



LRU replacement policy



Critical word first, streaming


Memories

Flash acceleration with cache (2/2)



Performance for Cortex-M4 @ 120 MHz, 3 wait states:

500



Execution with cache: ~2.5 – 3.4x faster



Note: compiler play a big role in benchmark results

EEMBC with IAR

400

EEMBC with Keil

400

300

300

200

200 400 402

100

0

119

61

142

150

100

0

95

260

253

91

208

253

Coremark Dhrystone

Coremark Dhrystone

Flash Flash cached PSRAM

Flash Flash cached PSRAM

2015-01-23

Numbers in clock cycles: higher numbers are better


Memories

Parity protected RAM and ECC protected Flash



RAM supports parity bit generation and error detection



Parity bit can be inverted to force an error for test purposes



Hardware support for ClassB Library saves CPU load for volatile memory test



Flash supports ECC with:



Single bit error detection and correction



Double bit error detection



Flash supports margin checks for preventive maintenance



All memories with zero wait state:



8-bit, 16-bit and 32-bit write access



32-bit read access


Memories

Flash IP protection



For software IP protection there are several modes available which allow both flexibility and safe protection against unauthorized read or manipulation



Hierarchical write protection control with 3 levels



Password based read protection for temporary disabling protection



Global read and sector-specific write granularity



Read protection blocks debug accesses and is globally for the whole flash area.



Write protection blocks flash write and erase accesses and is sector-specific



OTP protection

 one-time set, never change



Granularity: sector-specific, e. g. for a user-specific bootloader


Memories

External memory interface with external Bus Unit (EBU)



External Bus Interface (EBU) enables communication with external memories and on-chip peripherals



Supports memory access types:



Synchronous



Asynchronous



Burst Protocol



Multiple memory types can be accessed in time-multiplex


Memories

Flash Memory Characteristics



When Flash is busy, any access to the Flash memory or write access to Flash SFRs will be stalled automatically

Parameter

Voltage range

Erase time per sector

Min. Typical Max. Unit Note

3.1

-

-

-

-

0.3

1.2

5

3.6 V

0.4 s

1.4 s

5.5 s

Sector = 16 Kbytes

Sector = 64 Kbytes

Sector = 256 Kbytes

Erase all

Write time per page

Data retention

-

-

20

-

5.5

-

22 s At 1 Mbyte

11 ms

- years

Page = 256 bytes

Ta = 125°C, 1k cycles

Flash Wait States

Erase cycles per sector

Total erase cycles

2

3

-

-

-

-

-

-

- cycles f

MCLK

= 80 MHz

- cycles f

MCLK

= 120 MHz

10k cycles Sector = 64 Kbytes

20k cycles Cycling @ 2 x 64 Kbytes


Agenda






Memories



Bus System



Interrupt System



Clock



Reset



Power


Bus System

Highlights

Access parallelism through multilayer bus, multi-masters and multi-slaves.

Zero wait state data accesses between masters and slaves.

Simultaneous access can be handled by arbitration priority scheme.

Key Feature

Access parallelism


High throughput and real-time access of the system

Fast memory access

Zero wait state access to memories

Arbitration priority scheme

2015-01-23

Optimize system performance


Bus System

Prioritization Scheme

Masters

2015-01-23

Access Priorities per Slave

Examples of simultaneous accesses:

1) Ethernet-DMA to DSRAM2 while

2) CPU to PSRAM while

3) DMA0 to DSRAM1

FLASH

PSRAM

DSRAM1

CPU GPD

MA0

1 2

1 2

1 2

GPD

MA1

3

3

3

ETH USB

-

-

4

-

-

5

DSRAM2 1 4 5 2 3

EBU

PBA0-2

1

1

2

2

3

3

-

-

-

-


Agenda






Memories



Bus System



Interrupt System



Clock



Reset



Power


Interrupt System

Highlights

The interrupt system consists of the

Nested Vectored Interrupt Controller

(NVIC) and the interrupt generation blocks in the individual modules.

Events from peripherals can be routed via the connection matrix directly to other peripherals and can trigger interrupt requests.


Flexible priority control

Key Feature

64 programmable priority level

Interrupt Tail-chaining

Speed up interrupt servicing

Automatic State Saving and Restoring

2015-01-23

Low latency exception handling


Interrupt System

64 Programmable Priority Level



NVIC supports 112 interrupt nodes



Each interrupt node has an 8-bit priority field in IPRn register



One of 64 priority levels is assigned to an interrupt node by writing to its corresponding priority field



The lower the value written to the priority field, the higher the priority



A higher priority interrupt can interrupt an existing lower priority interrupt, resulting in nested interrupts



When multiple interrupts have the same priority level, the pending interrupt with the lower node ID takes precedence


Interrupt System

Interrupt Tail-chaining



When a current ISR is completed and there is a pending interrupt, stack pop is skipped and control is transferred to the new ISR



Allows interrupt servicing to speed up

Tail-chaining

Reference: http://www.arm.com


Interrupt System

Automatic State Saving and Restoring



Automatic state saving and restoring are done without any instruction overhead:



State registers are pushed onto the stack before entering the

ISR



Reading of vector table entry is done after the state saving



State registers are popped after exiting the ISR


Interrupt System

Interrupt Latency



Defined as the time from detection of interrupt pulse and latching of interrupt by NVIC, to execution of first instruction in

ISR



Typically 12 Cycles

CLK

1 2 11 12

12-cycle latency due to core

Interrupt request active/sampled

Note: Flash wait states are not considered

1st instruction at ISR


Interrupt System

General Module Interrupt Structure



Generates interrupt levels to NVIC



Status flag is a sticky bit – has to be cleared by SW


Interrupt System

Connection Matrix



Peripheral outputs can trigger events which are routed to peripheral inputs or to the NVIC



Additional event routing is possible via the Event Request Unit

ERU which can store events and logically combine two events



This allows very flexible and powerful system design


Agenda






Memories



Bus System



Interrupt System



Clock



Reset



Power


Clock

4-40

MHz

32.768 kHz

Clock

Main

Clock

Generation

Standby

Clock

Generation

Key Feature

Separate clock sources

Internal backup clock

Clock

Select

-ion

Unit

Optional automatic clock calibration

2015-01-23

Highlights

The main function of the clock system is to generate clock for the CPU and on-chip peripherals. The clock can be generated internally, by an external crystal or via direct input. The clock selection is flexible, and clocking system prevents against invalid clock configuration. A clock supervisory ensures always a safe clock for operation. Peripheral clock can run at twice the speed of CPU clock.


Wide choice of clock frequency for peripherals and system

Emergency clock if external clock fails

(fail safe feature)

Reduce bill of material


Clock

Separate Clock Sources



Two separate PLLs available for the system clock, ETH and USB



System clock

(32 kHz to 120 MHz)



ETH (>100 MHz)



USB/SDMMC (48 MHz)



Due to individual prescaler a very flexible configuration for the CPU system and peripherals is possible



Clock source (e.g. f

OFI

) for WDT can be independent from CPU

(f

CPU

) clock f

PLL f

PLLUSB f

OFI f

STDBY


1:n

1:n

Clock

Selection

Unit

1:n

1:n f

CPU f

DMA f

PERIPH f

CCU f

USB f

SDMMC f

ETH f

EBU f

WDT f

EXT

Page 33

Clock

Internal Backup Clock



A clock malfunction e.g. no clock, clock too slow, clock too fast and spikes in the clock is detected via a hardware oscillator watchdog



A backup clock (OFI or OSI) is available in case of a clock malfunction; the backup clock is automatically selected in emergency case

Main

Clock Generation

Standby

Clock Generation

OFI

OSI

4-40

MHz

PLL

USB

PLL

Clock

Select.

Unit

32.768 kHz f

STDBY f

RTC


Clock

Optional Automatic Clock Calibration



The two backup clocks can be used as clock source for cost sensitive applications



OFI and OSI can be calibrated



Factory calibration via one-time setting from flash config sector



Automatic calibration – on-the fly

¬ In case of using an accurate 32.678 kHz crystal for the RTC, one can use this clock to calibrate the OFI

¬ OFI can be used as PLL input clock

Uncalibrated

Factory calibrated

Automatic calibrated

OFI

36.5 MHz +/- 25%

24 MHz +/-15%

24 MHz +/-0.5%


Automatic Clock

Calibration

OFI

+/-0.5% cal

32.768 kHz

PLL

RTC

OSI

32 kHz +/- 10%

32 kHz +/- 4-10%

-

Page 35

Agenda






Memories



Bus System



Interrupt System



Clock



Reset



Power


Reset

Poweron Reset

Reset Types

Debug

Reset

System

Reset

Standby

Reset

Highlights

Always ensure safe application state via on-chip reset generation.

Full user control via reset event signalizing and software control.

Two domains core and hibernate with independent power supply and reset generation.

Key Feature

Power-on reset


Ensure safe operating conditions and defined system state

Fail safe reset mechanisms

Reset will bring the system into safe operation

Hibernate domain with separate reset

Hibernate domain can save information safely when using a backup supply


Reset

Reset Types and Reset Sources


Reset

Power-on Reset



Power-on reset



Supply voltage (3.3V) and core voltage (internally generated 1.3V) monitoring inside EVR



Hysteresis on threshold of poweron reset for supply voltage

¬ Immunity to noise (>250 mV) in the supply voltage



Pad control ensures defined pad state in undefined voltage range

(VDDP < VDDPmin)


Reset

Fail safe reset mechanisms



Brown-out detection pre-warning



Prepare system for reset, or, perform software corrective actions avoiding reset



Parity error detection



Optional system reset in case of parity error



Lockup reset



Standard ARM CPU feature



Optional reset in case of unrecoverable CPU states



Watchdog Timer reset



Watchdog reset generated if CPU is not responsive



Watchdog reset can be avoided with optional pre-warning



Software can trigger a System Reset


Reset

Hibernate domain with separate reset



Hibernate state will be preserved in case of system reset



System context memory retention



Hibernate configuration preserved



No impact on real-time clock



Hibernate domain can be reset with a software reset



Explicit reset triggered in user’s software



Note: the Hibernate Domain has a separate Power-on mechanism (via

Vbat supply) independent to the core system


Agenda






Memories



Bus System



Interrupt System



Clock



Reset



Power


Power

3.3V

Battery

Power

EVR

Pads

Hibernate

CPU clocks memories logic

Highlights

The single 3.3V supply concept allows a wide range of use cases. There are several power saving modes to tailor the current consumption to the application requirements. The power system is optimized for robustness and fail safe behavior for usage in a rugged industrial environment.

A battery backed hibernate domain with realtime clock is good for current critical application.

Key Feature

Different power saving modes


Scalable power consumption according to application use case

Hibernate domain with RTC

Power monitoring and validation

2015-01-23

Time and context keeping at low current consumption

Fail safe functionality


Power

Different power saving modes (1/2)



Simple transition scheme



All power saving states entered from Active state

¬ Active – Sleep

¬ Active – Deep Sleep

¬ Active – Hibernate



Power saving states entered with a single request

¬ Sleep and Deep Sleep entered via CPU instruction

¬ Hibernate request with single register access



Flexible Wake-up trigger

¬ One wake-up trigger source can serve different power saving modes



Prevention of wrong clock configuration in hardware

Mode

Active

Sleep

Power Saving

- Clock scaling

- Disable selected peripherals

- Flash on/off

- Stop CPU

- Disable ETH, USB, CCU,

WDT

Deep Sleep - Stop CPU

- Disable ETH, USB, CCU,

WDT

- Disable PLLs, flash

Hibernate - Core power supply off

Recovery

- Fully SW control

- Wake via interrupt

- Automatic restore

- Wake via interrupt

- Automatic restore

- Wake via event


Power

Different power saving modes (2/2)



Robust supply concept can be adapted to a wide range of power consumption to the user‘s need



Supports enough headroom for worst case current consumption

XMC Family

XMC4500

XMC4400

XMC4200

Typical

[mA]

~122

~113

~80

Worst case

[mA]

~180

~170

~140



Load step due to frequency change*)

150

100

50

0

Typical current consumption [mA]

XMC4400

113

53

Active @ 120MHz

- from flash

- from RAM

113

61

51

Freq scale

@ 120 MHz

@ 24MHz

104

80

8

Combined Saving

CPU off @ 120MHz

Peri. off @ 120MHz

@ 1MHz All off @ 24MHz



Max negative load step is ~150mA



Max positve load step is ~50mA

*) Increasing the frequency has to be done in steps, e. g.

24 MHz - 68 MHz - 120

MHz.

2015-01-23

Major current contributors [mA]

80

60

40

20

0

60

Flash on/off

@ 120


XMC4400

62

Freq scale

120 to 1

31

Peripherals on/off

@ 120

9

CPU on/off

@ 120

Page 45

Power

Hibernate with RTC



Hibernate state will be preserved in case of system power off





System context memory retention (16 x 32 bit register)

Hibernate configuration preserved

Hibernate with RTC

Battery

2.1–3.6V

RTC

LPAC

RAM

Standby clock

HIB_IO



No impact on real-time clock



Very low current consumption in

Hibernate Domain



Battery supply

15

10

5

0

Hibernate Current Consumption

XMC4400 [µA]

12.8

9

7.7

7

@ 3.3 V @ 2.4 V @ 2.0 V RTC off

@ 2.0 V


Power

Power Monitoring and Validation



Core domain power validation



Pad domain power monitoring



Supply voltage V

DDP



Threshold level V

POR

¬ Upper level of hysteresis is 3.1V

¬ Lower level of hysteresis is 2.85V



PORST activated when V

DDP

< V

PV



Core voltage V

DDC



Threshold level V

PV

(1.3V)



PORST activated when V

DDC

< V

PV

Safe power up and down with automatic internal reset handling (release & issue) and external signalization via bi-directional PORST signal.

V

DDP

EVR

V

DDC

V

POR

PORST#

V

DDP t

V

PV

PORST#

V

DDC t


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