Low Power, 12.65 mW, 2.3 V to 5.5 V, AD9833-EP Enhanced Product

Low Power, 12.65 mW, 2.3 V to 5.5 V, AD9833-EP Enhanced Product

Enhanced Product

Low Power, 12.65 mW, 2.3 V to 5.5 V,

Programmable Waveform Generator

AD9833-EP

FEATURES GENERAL DESCRIPTION

Digitally programmable frequency and phase

12.65 mW power consumption at 3 V

0 MHz to 12.5 MHz output frequency range

28-bit resolution: 0.1 Hz at 25 MHz reference clock

Sinusoidal, triangular, and square wave outputs

2.3 V to 5.5 V power supply

No external components required

3-wire SPI interface

Power-down option

10-lead MSOP package

Enhanced product features

Supports defense and aerospace applications (AQEC)

Temperature range: −55°C to +125°C

Controlled manufacturing baseline

1 assembly/test site

1 fabrication site

Enhanced product change notification

Qualification data available upon request

The AD9833-EP is a low power, programmable waveform generator capable of producing sine, triangular, and square wave outputs. Waveform generation is required in various types of sensing, actuation, and time domain reflectometry (TDR) applications. The output frequency and phase are software programmable, allowing easy tuning. No external components are needed. The frequency registers are 28 bits wide. With a 25 MHz clock rate, a resolution of 0.1 Hz can be achieved; with a 1 MHz clock rate, the AD9833-EP can be tuned to 0.004 Hz resolution.

The AD9833-EP is written to via a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. The device operates with a power supply from 2.3 V to 5.5 V.

The AD9833-EP has a power-down function (SLEEP). This function allows sections of the device that are not being used to be powered down, thus minimizing the current consumption of the part. For example, the DAC can be powered down when a clock output is being generated.

APPLICATIONS

Frequency stimulus/waveform generation

Liquid and gas flow measurement

Sensory applications: proximity, motion, defect detection

Line loss/attenuation

Test and medical equipment

Sweep/clock generators

Time domain reflectometry (TDR) applications

The AD9833-EP is available in a 10-lead MSOP package.

Additional application and technical information can be found in the AD9833 data sheet.

FUNCTIONAL BLOCK DIAGRAM

AGND DGND

VDD CAP/2.5V

MCLK

AVDD/

DVDD

REGULATOR

2.5V

ON-BOARD

REFERENCE

FULL-SCALE

CONTROL

COMP

FREQ0 REG

MUX

PHASE

ACCUMULATOR

(28-BIT)

12

SIN

ROM

MUX 10-BIT DAC

FREQ1 REG

MSB

PHASE0 REG

PHASE1 REG

MUX

DIVIDE

BY 2

MUX

VOUT

CONTROL REGISTER

R

200Ω

SERIAL INTERFACE

AND

CONTROL LOGIC AD9833-EP

FSYNC SCLK SDATA

Rev. 0 Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

©2013 Analog Devices, Inc. All rights reserved. www.analog.com

AD9833-EP

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 4

REVISION HISTORY

8/13—Revision 0: Initial Version

Enhanced Product

Absolute Maximum Ratings ............................................................5

ESD Caution...................................................................................5

Pin Configuration and Function Descriptions ..............................6

Typical Performance Characteristics ..............................................7

Outline Dimensions ....................................................................... 10

Ordering Guide .......................................................................... 10

Rev. 0 | Page 2 of 12

Enhanced Product

SPECIFICATIONS

VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, T

A

= T

MIN

to T

MAX

, R

SET

= 6.8 kΩ for VOUT, unless otherwise noted.

Table 1.

Parameter

1

SIGNAL

Resolution

AD9833-EP

DC Accuracy

Wideband (0 to Nyquist)

Narrow-Band (±200 kHz)

−60

−78 dBc dBc

Differential LSB

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD)

53.5 60

−66 −53.5 dB dBc f

MCLK

= 25 MHz, f

OUT

= f

MCLK

/4096 f

MCLK

= 25 MHz, f

OUT

= f

MCLK

/4096 f

MCLK

= 25 MHz, f

OUT

= f

MCLK

/50 f

MCLK

= 25 MHz, f

OUT

= f

MCLK

/50

LOGIC INPUTS

Input High Voltage, V

INH

Input Low Voltage, V

INL

Input Current, I

INH

/I

INL

Input Capacitance, C

IN

1.7

2.0

2.8

0.5

0.7

0.8

V

V

V

V

V

V

2.3 V to 2.7 V power supply

2.7 V to 3.6 V power supply

4.5 V to 5.5 V power supply

2.3 V to 2.7 V power supply

2.7 V to 3.6 V power supply

4.5 V to 5.5 V power supply

VDD

I

DD

Low Power Sleep Mode

f

MCLK

= 25 MHz, f

OUT

= f

MCLK

/4096

2.3 5.5 V

4.5 5.5 mA I

DD

code dependent; see Figure 7

0.5 mA DAC powered down, MCLK running

1 Operating temperature range is −55°C to +125°C; typical specifications are at 25°C.

VDD

100nF

10nF

CAP/2.5V

COMP

REGULATOR

12

SIN

ROM

10-BIT DAC

VOUT

AD9833-EP

Figure 2. Test Circuit Used to Test Specifications

20pF

Rev. 0 | Page 3 of 12

AD9833-EP

TIMING CHARACTERISTICS

VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.

1

Enhanced Product

Table 2.

Parameter Limit

MAX

Description

ns min MCLK period t

1 t

2 t

3 t

4 t

5 t

6 t

7 t

8 min t

8 max

40

16

16

25

10

10

5

10 t

4

− 5 t

9 t

10

5

3 t

11

5

1 Guaranteed by design, not production tested. ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns min

MCLK high duration

MCLK low duration

SCLK period

SCLK high duration

SCLK low duration

FSYNC to SCLK falling edge setup time

FSYNC to SCLK hold time

Data setup time

Data hold time

SCLK high to FSYNC falling edge setup time

Timing Diagrams

t

1

MCLK t

2 t

3

Figure 3. Master Clock

t

11 t

5 t

4

SCLK t

7 t

6 t

8

FSYNC

SDATA

D15 D14 D2 t

9 t

10

D1 D0 D15 D14

Figure 4. Serial Timing

Rev. 0 | Page 4 of 12

Enhanced Product

ABSOLUTE MAXIMUM RATINGS

T

A

= 25°C, unless otherwise noted.

Table 3.

Parameter

VDD to AGND

VDD to DGND

AGND to DGND

CAP/2.5V

Digital I/O Voltage to DGND

Analog I/O Voltage to AGND

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

MSOP Package

Rating

−0.3 V to +6 V

−0.3 V to +6 V

−0.3 V to +0.3 V

2.75 V

−0.3 V to VDD + 0.3 V

−0.3 V to VDD + 0.3 V

−55°C to +125°C

−65°C to +150°C

150°C

θ

JA

Thermal Impedance

θ

JC

Thermal Impedance

206°C/W

44°C/W

Lead Temperature, Soldering (10 sec) 300°C

IR Reflow, Peak Temperature 220°C

AD9833-EP

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 12

AD9833-EP

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Enhanced Product

COMP

1

VDD

2

CAP/2.5V

3

DGND

4

MCLK

5

AD9833-EP

TOP VIEW

(Not to Scale)

7

6

10

VOUT

9

AGND

8

FSYNC

SCLK

SDATA

Figure 5. Pin Configuration

1

2

3

4

5

6

7

8

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

9

10

COMP

VDD

CAP/2.5V

DGND

MCLK

SDATA

SCLK

FSYNC

AGND

VOUT

DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.

Positive Power Supply for the Analog and Digital Interface Sections. The on-board 2.5 V regulator is also supplied from VDD. VDD can have a value from 2.3 V to 5.5 V. A 0.1 µF and a 10 µF decoupling capacitor should be connected between VDD and AGND.

The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from VDD using an on-board regulator when VDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is connected from CAP/2.5V to DGND. If VDD is less than or equal to 2.7 V, CAP/2.5V should be tied directly to VDD.

Digital Ground.

Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock.

Serial Data Input. The 16-bit serial data-word is applied to this input.

Serial Clock Input. Data is clocked into the AD9833-EP on each falling edge of SCLK.

Active Low Control Input. FSYNC is the frame synchronization signal for the input data. When FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device.

Analog Ground.

Voltage Output. The analog and digital output from the AD9833-EP is available at this pin. An external load resistor is not required because the device has a 200 Ω resistor on board.

Rev. 0 | Page 6 of 12

Enhanced Product

TYPICAL PERFORMANCE CHARACTERISTICS

5.5

T

A

= 25°C

5.0

VDD = 5V

4.5

VDD = 3V

4.0

3.5

3.0

0 5 10 15

MCLK FREQUENCY (MHz)

20 25

Figure 6. Typical Current Consumption (I

DD

) vs. MCLK Frequency for f

OUT

= MCLK/10

4

3

6

VDD = 5V

VDD = 3V

5

2

1

0

100 1k 10k 100k f

OUT

(Hz)

1M

Figure 7. Typical I

DD

vs. f

OUT

for f

MCLK

= 25 MHz

10M

AD9833-EP

–40

VDD = 3V

T

A

= 25°C

–45

–50

–55

–60

–65

MCLK/7

MCLK/50

–70

5 7 9 11 13 15 17 19

MCLK FREQUENCY (MHz)

21

Figure 9. Wideband SFDR vs. MCLK Frequency

23 25

–50

–60

–70

–80

0

–10

VDD = 3V

T

A

= 25°C

–20

–30

–40 f

MCLK

= 10MHz f

MCLK

= 18MHz f

MCLK

= 1MHz f

MCLK

= 25MHz

–90

0.001

0.01

0.1

1 10 100 f

OUT

/ f

MCLK

Figure 10. Wideband SFDR vs. f

OUT

/f

MCLK

for Various MCLK Frequencies

–60

VDD = 3V

T

A

= 25°C

–65

–70

–75

–80

MCLK/7

MCLK/50

–85

–90

0 5 10 15

MCLK FREQUENCY (MHz)

20

Figure 8. Narrow-Band SFDR vs. MCLK Frequency

25

–40

–45

VDD = 3V

T

A

= 25°C f

OUT

= MCLK/4096

–50

–55

–60

–65

–70

1.0

5.0

10.0

MCLK FREQUENCY (MHz)

12.5

Figure 11. SNR vs. MCLK Frequency

25.0

Rev. 0 | Page 7 of 12

1.250

1.225

1.200

1.175

1.150

1.125

1.100

–40

AD9833-EP

1000

950

900

850

800

750

700

650

600

550

500

–40

VDD = 5.5V

VDD = 2.3V

25

TEMPERATURE (°C)

Figure 12. Wake-Up Time vs. Temperature

UPPER RANGE

LOWER RANGE

25

TEMPERATURE (°C)

Figure 13. V

REF

vs. Temperature

105

105

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

RWB 100

VWB 30

FREQUENCY (Hz)

100k

ST 100 SEC

Figure 14. Power vs. Frequency, f

MCLK

= 10 MHz, f

OUT

= 2.4 kHz,

Frequency Word = 0x000FBA9

Rev. 0 | Page 8 of 12

Enhanced Product

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

RWB 1k

VWB 300

5M

ST 50 SEC

FREQUENCY (Hz)

Figure 15. Power vs. Frequency, f

MCLK

= 10 MHz, f

OUT

= 1.43 MHz = f

MCLK

/7,

Frequency Word = 0x2492492

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

RWB 1k VWB 300

5M

ST 50 SEC

FREQUENCY (Hz)

Figure 16. Power vs. Frequency, f

MCLK

= 10 MHz, f

OUT

= 3.33 MHz = f

MCLK

/3,

Frequency Word = 0x5555555

–30

–40

–50

–60

–70

0

–10

–20

–80

–90

–100

0

RWB 100 VWB 30

FREQUENCY (Hz)

100k

ST 100 SEC

Figure 17. Power vs. Frequency, f

MCLK

= 25 MHz, f

OUT

= 6 kHz,

Frequency Word = 0x000FBA9

Enhanced Product

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

RWB 300 VWB 100

FREQUENCY (Hz)

1M

ST 100 SEC

Figure 18. Power vs. Frequency, f

MCLK

= 25 MHz, f

OUT

= 60 kHz,

Frequency Word = 0x009D495

AD9833-EP

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

RWB 1k VWB 300

12.5M

ST 100 SEC

FREQUENCY (Hz)

Figure 21. Power vs. Frequency, f

MCLK

= 25 MHz, f

OUT

= 3.857 MHz = f

MCLK

/7,

Frequency Word = 0x2492492

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–100

0

RWB 1k

VWB 300

FREQUENCY (Hz)

12.5M

ST 100 SEC

Figure 19. Power vs. Frequency, f

MCLK

= 25 MHz, f

OUT

= 600 kHz,

Frequency Word = 0x0624DD3

–30

–40

–50

–60

–70

–80

0

–10

–20

–90

–100

0

RWB 1k VWB 300

FREQUENCY (Hz)

12.5M

ST 100 SEC

Figure 20. Power vs. Frequency, f

MCLK

= 25 MHz, f

OUT

= 2.4 MHz,

Frequency Word = 0x189374D

Rev. 0 | Page 9 of 12

–30

–40

–50

–60

–70

0

–10

–20

–80

–90

–100

0

RWB 1k VWB 300

12.5M

ST 100 SEC

FREQUENCY (Hz)

Figure 22. Power vs. Frequency, f

MCLK

= 25 MHz, f

OUT

= 8.333 MHz = f

MCLK

/3,

Frequency Word = 0x5555555

AD9833-EP

OUTLINE DIMENSIONS

3.10

3.00

2.90

3.10

3.00

2.90

10

1

6 5.15

4.90

4.65

5

PIN 1

IDENTIFIER

0.50 BSC

0.95

0.85

0.75

0.15

0.05

COPLANARITY

0.10

0.30

0.15

1.10 MAX

15° MAX

0.23

0.13

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 23. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

0.70

0.55

0.40

ORDERING GUIDE

Model 1

AD9833SRMZ-EP-RL7

1 Z = RoHS Compliant Part.

Temperature Range

−55°C to +125°C

Package Description

10-Lead MSOP

Enhanced Product

Package Option Branding

RM-10 DMR

Rev. 0 | Page 10 of 12

Enhanced Product

NOTES

AD9833-EP

Rev. 0 | Page 11 of 12

AD9833-EP

NOTES

Enhanced Product

©2013 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D11545-0-8/13(0)

Rev. 0 | Page 12 of 12

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