W19B320BTT7H даташит

W19B320BTT7H даташит
W19B320BT/B DATASHEET
Table of Contents1.
GENERAL DESCRIPTION ......................................................................................................................4
2.
FEATURES ..............................................................................................................................................4
3.
PIN CONFIGURATIONS .........................................................................................................................5
4.
BLOCK DIAGRAM ...................................................................................................................................5
5.
PIN DESCRIPTION..................................................................................................................................5
6.
FUNCTIONAL DESCRIPTION ................................................................................................................6
6.1
Device Bus Operation.....................................................................................................................6
6.1.1
Word/Byte Configuration ................................................................................................................6
6.1.2
Reading Array Data ........................................................................................................................6
6.1.3
Writing Commands/Command Sequences ....................................................................................6
6.1.4
Standby Mode.................................................................................................................................7
6.1.5
Automatic Sleep Mode....................................................................................................................7
6.1.6
#RESET: Hardware Reset Pin .......................................................................................................7
6.1.7
Output Disable Mode ......................................................................................................................8
6.1.8
AUTOSELECT Mode......................................................................................................................8
6.1.9
Sector/Sector Block Protection and Unprotection ..........................................................................8
6.1.10
Write Protect (#WP)........................................................................................................................8
6.1.11
Temporary Sector Unprotect ..........................................................................................................8
6.1.12
Security Sector Flash Memory Region ...........................................................................................9
6.1.13
Hardware Data Protection ............................................................................................................10
6.2
Command Definitions ...................................................................................................................10
6.2.1
Reading Array Data ......................................................................................................................10
6.2.2
Reset Command...........................................................................................................................10
6.2.3
AUTOSELECT Command Sequence...........................................................................................11
6.2.4
Byte/Word Program Command Sequence ...................................................................................11
6.2.5
Unlock Bypass Command Sequence...........................................................................................12
6.2.6
Chip Erase Command Sequence .................................................................................................12
6.2.7
Sector Erase Command Sequence ..............................................................................................13
6.3
Write Operation Status .................................................................................................................13
6.3.1
DQ7: #Data Polling .......................................................................................................................13
6.3.2
RY/#BY: Ready/#Busy..................................................................................................................14
6.3.3
DQ6: Toggle Bit I ..........................................................................................................................14
6.3.4
Reading Toggle Bits DQ6/DQ2 ....................................................................................................14
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7.
8.
6.3.5
DQ5: Exceeded Timing Limits ......................................................................................................15
6.3.6
DQ3: Sector Erase Timer .............................................................................................................15
TABLE OF OPERATION MODES .........................................................................................................16
7.1
Device Bus Operations.................................................................................................................16
7.2
AUTOSELECT Codes (High Voltage Method) .............................................................................17
7.3
Sector Address Table (Top Boot Block) .......................................................................................18
7.4
Sector Address Table (Bottom Boot Block)..................................................................................20
7.5
CFI Query Identification String .....................................................................................................25
7.5.1
System Interface String ................................................................................................................25
7.5.2
Device Geometry Definition..........................................................................................................26
7.5.3
Primary Vendor-Specific Extended Query....................................................................................27
7.5.4
Command Definitions ...................................................................................................................28
7.5.5
Write Operation Status .................................................................................................................29
7.6
Temporary Sector Unprotect Algorithm........................................................................................30
7.7
In-System Sector Protect/Unprotect Algorithms...........................................................................31
7.8
Security Sector Protect Verify.......................................................................................................32
7.9
Program Algorithm........................................................................................................................32
7.10
Erase Algorithm.........................................................................................................................33
7.11
Data Polling Algorithm ..............................................................................................................33
7.12
Toggle Bit Algorithm..................................................................................................................34
ELECTRICAL CHARACTERISTICS......................................................................................................35
8.1
Absolute Maximum Ratings..........................................................................................................35
8.2
Operating Ranges.........................................................................................................................35
8.3
DC Characteristics........................................................................................................................36
8.4
CMOS Compatible........................................................................................................................36
8.5
AC Characteristics ........................................................................................................................37
8.6
Test Condition...............................................................................................................................37
8.6.1
9.
AC Test Load and Waveforms .....................................................................................................37
8.7
Read-Only Operations..................................................................................................................38
8.8
Hardware Reset (#RESET) ..........................................................................................................38
8.9
Word/Byte Configuration (#BYTE)................................................................................................38
8.10
Erase and Program Operation ..................................................................................................39
8.11
Temporary Sector Unprotect.....................................................................................................39
8.12
Alternate #CE Controlled Erase and Program Operations .......................................................40
TIMING WAVEFORMS ..........................................................................................................................41
9.1
AC Read Waveform......................................................................................................................41
9.2
Reset Waveform ...........................................................................................................................41
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9.3
#BYTE Waveform for Read Operation .........................................................................................42
9.4
#BYTE Waveform for Write Operation .........................................................................................42
9.5
Programming Waveform...............................................................................................................43
9.6
Accelerated Programming Waveform ..........................................................................................43
9.7
Chip/Sector Erase Waveform .......................................................................................................44
9.8
Back-to back Read/Write Cycle Waveform ..................................................................................44
9.9
#Data Polling Waveform (During Embedded Algorithms) ............................................................45
9.10
Toggle Bit Waveform (During Embedded Algorithms)..............................................................45
9.11
Temporary Sector Unprotect Timing Diagram ..........................................................................46
9.12
Sector/Sector Block Protect and Unprotect Timing Diagram....................................................46
9.13
Alternate #CE Controlled Write (Erase/Program) Operation Timing ........................................47
10.
LATCHUP CHARACTERISTICS ...........................................................................................................48
11.
CAPACITANCE......................................................................................................................................48
12.
ORDERING INFORMATION .................................................................................................................49
13.
PACKAGE DIMENSION ........................................................................................................................50
13.1
14.
48-Pin Standard Thin Small Outline Package ..........................................................................50
VERSION HISTORY ..............................................................................................................................51
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1. GENERAL DESCRIPTION
The W19B320BT/B is a 32Mbit, 2.7~3.6-volt single bank CMOS flash memory organized as 4M x 8 or 2M × 16
bits. The word-wide (× 16) data appears on DQ15-DQ0, and byte-wide (x 8) data appears on DQ7-DQ0. The
device can be programmed and erased in-system with a standard 3.0-volt power supply. A 12-volt VPP is not
required. The unique cell architecture of the W19B320BT/B results in fast program/erase operations with
extremely low current consumption (compared to other comparable 3-volt flash memory products). The device
can also be programmed and erased by using standard EPROM programmers.
2. FEATURES
Performance
• 2.7~3.6-volt write (program and erase)
operations
• Fast write operation
− Sector erases time: 0.4 Sec (typical)
− Chip erases time: 30Sec (typical)
− Byte/Word programming time: 7/9 μs (typical)
• Read access time: 70 ns
• Typical program/erase cycles: 100K
• Twenty-year data retention
• Ultra low power consumption
− Active current (Read): 10 mA (typical)
− Active current (Read while Erase): 21 mA
(typical)
− Standby current: 0.2 μA (typical)
Architecture
• Sector erase architecture
− Eight 8KB, and sixty-three 64KB sectors
− Top or bottom boot block configurations
available
− Supports full chip erase
• Security Sector Size: 256 Bytes
− The Security Sector is an OTP; once the sector
is programmed, it cannot be erased
• JEDEC standard byte-wide and word-wide
pinouts
• Compatible with common Flash Memory
Interface (CFI) specification
− Flash device parameters stored directly on the
device
− Allows software driver to identify and use a
variety of different current and future Flash
products
• End of program detection
− Software method: Toggle bit/Data polling
• Unlock Bypass Program command
− Reduces overall programming time when
issuing multiple program command sequences
Hardware Features
• Ready/#Busy output (RY/#BY)
− Detect program or erase cycle completion
• Hardware reset pin (#RESET)
− Reset the internal state machine to the read
mode
• #WP/ACC input pin
− Write protect (#WP) function allows protection
of two outermost boot sectors, regardless of
sector protection status
Temperature range
• Extended temperature range (-20℃ to 85 ℃)•
• Manufactured on WinStack 0.13μm process
technology
• Available packages: 48-pin TSOP
Software Features
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3. PIN CONFIGURATIONS
4. BLOCK DIAGRAM
VDD
VSS
#CE
#OE
#WE
#WP/ACC
#BYTE
#RESET
CONTROL
OUTPUT
BUFFER
DECODER
BANK
DQ0
.
.
DQ15/A-1
DQ15/A-1
A0
.
.
.
A20
5. PIN DESCRIPTION
SYMBOL
A0−A20
PIN NAME
Address Inputs
DQ0−DQ14 Data Inputs/Outputs
DQ15/A-1
DQ15 is Data
Inputs/Outputs
Byte
mode
A-1 is Address input
#CE
Chip Enable
#OE
Output Enable
#WE
Write Enable
#WP/ACC
#BYTE
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Word
mode
Hardware Write Protect/
Acceleration Pin
Byte Enable Input
#RESET
Hardware Reset
RY/#BY
Ready/Busy Status
VDD
Power Supply
VSS
Ground
NC
No Connection
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6. FUNCTIONAL DESCRIPTION
6.1
Device Bus Operation
6.1.1
Word/Byte Configuration
The #BYTE pin controls the device data I/O pins operate whether in the byte or word configuration.
When the #BYTE pin is ‘1’, the device is in word configuration; DQ0 -DQ15 are active and controlled by
#CE and #OE.
When the #BYTE pin is ‘0’, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active
and controlled by #CE and #OE. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
6.1.2
Reading Array Data
To read array data from the outputs, the #CE and #OE pins must be set to VIL. #CE is the power control
and used to select the device. #OE is the output control and gates array data to the output pins. #WE
should stay at VIH. The #BYTE pin determines the device outputs array data whether in words or bytes.
The internal state machine is set for reading array data when device power-up, or after hardware reset.
This ensures that no excess modification of the memory content occurs during the power transition. In
this mode there is no command necessary to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs produce valid data on the device data outputs.
Each bank remains enabled for read access until the command register contents are changed.
6.1.3
Writing Commands/Command Sequences
In writhing a command or command sequence (which includes programming data to the device and
erasing sectors of memory), the system must drive #WE and #CE to VIL, and #OE to VIH.
For program operations, the #BYTE pin determines the device accepts program data whether in bytes
or in words. Refer to “Word/Byte Configuration” for more information.
The Unlock Bypass mode of device is to facilitate a faster programming. When a bank enters the
Unlock Bypass mode, only two write cycles are required to program a word or byte. Please refer to
"Word/Byte Configuration” section for details on programming data to the device using both standard
and Unlock Bypass command sequences.
The erase operation can erase a sector, multiple sectors, even the entire device. The “sector address”
is the address bits required to solely select a sector.
Accelerated Program Operation
The device provides accelerated program operations through the ACC function. This is one of two
functions provided by the #WP/ACC pin. This function is primarily intended to allow a faster
manufacturing throughput in the factory.
If #WP/ACC pin is set at VHH, the device automatically enters into the Unlock Bypass mode. Then the
device will temporarily unprotect any protected sectors, and uses the higher voltage on this pin to
reduce the time required for program operations. The system would use a two-cycle program command
sequence required by the Unlock Bypass mode. When VHH is removed from the #WP/ACC pin, the
device is back to a normal operation.
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Please note that the #WP/ACC pin can not be at VHH for operations except accelerated programming;
otherwise, the device will be damaged. In addition, the #WP/ACC pin can not be left floating; otherwise,
an unconnected inconsistent behavior will occur.
AUTOSELECT Functions
When the system writes the AUTOSELECT command sequence, the device enters the AUTOSELECT
mode. The system can then read AUTOSELECT codes from the internal register (which is separate
from the memory array) on DQ0 –DQ7. The standard read cycle timings are applied in this mode.
Please refer to the AUTOSELECT Mode and AUTOSELECT Command Sequence sections for more
information.
6.1.4
Standby Mode
When the system is not reading or writing to the device, the device will be in a standby mode. In this
mode, current consumption is greatly reduced, and the outputs are in the high impedance state,
independent from the #OE input.
When the #CE and #RESET pins are both held at VDD ± 0.3V, the device enters into the CMOS standby
mode (note that this is a more restricted voltage range than VIH.) When #CE and #RESET are held at VIH,
but not within VDD ± 0.3V, the device will be in the standby mode, but the standby current will be greater. The
device requires standard access time (tCE) for read access when the device is in either of these standby
modes, before it is ready to read data.
When the device is deselected during erasing or programming, the device initiates active current until
the operation is completed.
6.1.5
Automatic Sleep Mode
The automatic sleep mode minimizes device's energy consumption. When addresses remain stable for
tACC + 30ns, the device will enable this mode automatically. The automatic sleep mode is independent
from the #CE, #WE, and #OE control signals. Standard address access timings provide new data when
addresses are changed. In sleep mode, output data is latched and always available to the system.
6.1.6
#RESET: Hardware Reset Pin
The #RESET pin provides a hardware method to reset the device to reading array data. When the
#RESET pin is set to low for at least a period of tRP, the device will immediately terminate every
operation in progress, tri-states all output pins, and ignores all read/write commands for the duration of
the #RESET pulse. The device also resets the internal state machine to reading array data mode. To
ensure data integrity, the interrupted operation needs to be reinitiated when the device is ready to
accept another command sequence.
Current is reduced for the duration of the #RESET pulse. When #RESET is held at VSS ± 0.3V, the
device initiates the CMOS standby current (ICC4). If #RESET is held at VIL but not within VSS ± 0.3V, the
standby current will be greater.
The #RESET pin may be tied to the system-reset circuitry. Thus the system reset would also reset the
device, enabling the system to read the boot-up firmware from the device.
If #RESET is asserted during the program or erase operation, the RY/#BY pin will be at “0” (busy) until
the internal reset operation is complete. If #RESET is asserted when a program or erase operation is
not processing (RY/#BY pin is “1”), the reset operation is completed within a time of tREADY (not during
Embedded Algorithms). After the #RESET pin returns to VIH, the system can read data tRH.
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6.1.7
Output Disable Mode
When the #OE input is at VIH, output from the device is disabled. The output pins are set in the high
impedance state.
6.1.8
AUTOSELECT Mode
The AUTOSELECT mode offers manufacturer and device identification, as well as sector protection
verification, through identifier codes output on DQ0-DQ7. This mode is primarily intended for
programming equipment to automatically match a device to be programmed with its corresponding
programming algorithm. However, the AUTOSELECT codes can also be accessed in-system through
the command register.
When using programming equipment, the AUTOSELECT mode requires VID (8.5V to 11.5V) on address
pins A9. Address pins A6, A1, and A0 must be as shown in table. In addition, when verifying sector
protection, the sector address must appear on the appropriate highest order address bits. When all
necessary bits have been set as required, the programming equipment may then read the
corresponding identifier code on DQ0-DQ7.
6.1.9
Sector/Sector Block Protection and Unprotection
The hardware sector protection feature disables both program and erasure operations in any sectors.
The hardware sector Unprotection feature re-enables both program and erasure operations in
previously protected sectors. Sector Protection/Unprotection can be implemented through two methods.
The primary method requires VID on the #RESET pin, and can be implemented either in-system or through
programming equipment. This method uses standard microprocessor bus cycle timing.
The alternate method intended only for programming equipment requires VID on address pin A9 and #OE. It
is possible to determine whether a sector is protected or unprotected. See the Application Note for detail
information.
6.1.10 Write Protect (#WP)
The Write Protect function provides a hardware method to protect the certain boot sectors without using
VID. This function is one of two features provided by the #WP/ACC pin.
When the #WP/ACC pin is set at VIL, the device disables program and erase functions in the two
outermost 8 Kbytes boot sectors independently of whether those sectors were protected or unprotected
using the method described in “Sector/Sector Block Protection and Unprotection.” The two outermost 8
Kbytes boot sectors are the two sectors containing either the lowest addresses in a bottom-bootconfigured device or the highest addresses in a top-boot-configured device.
When the #WP/ACC pin is set at VIH, the device reverts to the two outermost 8 Kbytes boot sectors
were last set either to be protected or unprotected. That is, sector Protection or Unprotection for these
two sectors depends on whether they were last protected or unprotected using the method described in
“Sector/Sector Block Protection and Unprotection”.
Please note that the #WP/ACC pin must not be left floating or unconnected; otherwise, the inconsistent
behavior of the device may occur.
6.1.11 Temporary Sector Unprotect
This feature allows temporary Unprotection of previously protected sectors to change data in-system.
When the #RESET pin is set to VID, the Sector Unprotect mode is activated. During this mode, formerly
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protected sectors can be programmed or erased by selecting the sector addresses. What if VID is
removed from the #RESET pin, all the previously protected sectors are protected again.
6.1.12 Security Sector Flash Memory Region
The Security Sector feature provides an OTP memory region that enables permanent device
identification through an Electronic Serial Number (ESN). The Security Sector uses a Security Sector
Indicator Bit (DQ7) to indicate whether the Security Sector is locked or not when shipped from the
factory. The DQ7 is permanently set when it is in the factory and cannot be changed, which prevents
copying of a factory locked part. This ensures the security of the ESN when the product is shipped to
the field. This issue should be considered during system design. Winbond offers the device with the
Security Sector either factory locked or customer lockable. The factory-locked version is always
protected when shipped from the factory, and has the Security Sector Indicator Bit permanently set to
“1” The customer-lockable version is shipped with the Security Sector unprotected, which allowing
customers to utilize the sector in any ways they choose. The customer-lockable version has the
Security Sector Indicator Bit permanently set to “0.” Thus, the Security Sector Indicator Bit prevents
customer-lockable devices from being used to replace devices that are factory locked.
The system accesses the Security Sector through a command sequence (see “Enter Security
Sector/Exit Security Sector Command Sequence”). After the system has written the Enter Security
Sector command sequence, it may read the Security Sector by using the addresses normally occupied
by the boot sectors. This mode of operation continues until the system issues the Exit Security Sector
command sequence, or until power is removed from the device. On power-up, or following a hardware
reset, the device reverts to sending commands to the boot sectors.
Factory Locked: Security Sector Programmed and Protected At the Factory
The device Security Sector is protected when it is shipped from the factory, and it cannot be modified in
any way. The device is available to be preprogrammed by one of the following:
•
A random, secure ESN only
•
Customer code through the supplier's service
•
Both a random, secure ESN and customer code through supplier's service.
In devices with an ESN, the Bottom Boot device will be with the 16-byte ESN in the lowest addressable
memory area at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). In
the Top Boot device the starting address of the ESN will be at the bottom of the highest 8 Kbytes boot
sector at addresses 1FF000h–1FF007h in word mode (or addresses 3FE000h–3FE00Fh in byte
mode). Customers may choose have their code programmed by Winbond. Winbond can program the
customer’s code, with or without the random ESN. The devices are then shipped with the Security
Sector permanently locked.
Customer Lockable: Security Sector NOT Programmed or Protected At the Factory
If the security feature is not necessary, the Security Sector can be seen as an additional OTP memory
space. When in system design, this issue should be considered. The Security Sector can be read,
programmed; but cannot be erased. Please note that when programming the Security Sector, the
accelerated programming (ACC) and unlock bypass functions are not available. The Security Sector
area can be protected using one of the following procedures:
•
Write the three-cycle Enter Security Sector Region command sequence, and then follow the insystem sector protect algorithm, except that #RESET may be at either V IH or VID. This allows
in-system protection of the Security Sector without raising any device pin to a high voltage.
Please note that this method is only suitable for the Security Sector.
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W19B320BT/B DATASHEET
•
To verify the protect/unprotect status of the Security Sector; follow the algorithm show in
Security Sector Protect Verify.
The Security Sector protection must be used with caution, since there is no procedure available for
unprotect the Security Sector area and none of the bits in the Security Sector memory space can be
modified in any ways.
6.1.13 Hardware Data Protection
The command sequence requirements of unlock cycles for programming or erasing provides data
protection against negligent writes. In addition, the following hardware data protection measures
prevent inadvertent erasure or programming, which might be caused by spurious system level signals
during VDD power-up and power-down transitions, or from system noise.
Write Pulse “Glitch” Protection
Noise pulses, which is less than 5 ns (typical) on #OE, #CE or #WE, do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of #OE = VIL, #CE = VIH or #WE = VIH. #CE and #WE
must be a logical zero while #OE is a logical one to initiate a write cycle.
Power-Up Write Inhibit
During power up, if #WE = #CE = VIL and #OE = VIH, the device does not accept commands on the
rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up.
6.2
Command Definitions
The device operation can be initiated by writing specific address and data commands or sequences into
the command register. The device will be reset to reading array data when writing incorrect address
and data values or writing them in the improper sequence.
The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the
data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing
waveforms.
6.2.1
Reading Array Data
After device power-up, it is automatically set to reading array data. There is no commands are required
to retrieve data. After completing an Embedded Program or Embedded Erase algorithm, each bank is
ready to read array data.
The system must initiate the reset command to return a bank to read mode if DQ5 goes high during an
active program or erase operation, or the bank is in the AUTOSELECT mode. See Reset Command
section and Requirements for Reading Array Data in the Device Bus Operations section for more
information.
6.2.2
Reset Command
The banks will be to the read mode when writing the reset command. For this command, the address
bits are Don’t Care.
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The reset command may be written between the sequential cycles in an erase command sequence
before erasing begins. This resets the bank to which the system was writing to the read mode. Once
erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence
before programming begins. This resets the bank, to which the system was writing to the read mode.
When programming begins, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an AUTOSELECT command
sequence. When in the AUTOSELECT mode, the reset command must be written to return to the read
mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to
the read mode.
6.2.3
AUTOSELECT Command Sequence
The AUTOSELECT command sequence provides the host system to access the manufacturer and
device codes, and determine whether a sector is protected or not. This is an alternative method, which
is intended for PROM programmers and requires VID on address pin A9. The AUTOSELECT command
sequence may be written to an address within a bank that is either in the read mode. When the device
is actively programming or erasing in the other bank, the AUTOSELECT command may not be written.
The first writing two unlock cycles initiate the AUTOSELECT command sequence. This is followed by a
third write cycle that contains the bank address and the AUTOSELECT command. The bank then
enters into the AUTOSELECT mode. The system may read at any address within the same bank
without initiating another AUTOSELECT command sequence:
• A read cycle at address (BA) XX00h (where BA is
the bank address) returns the manufacturer code.
• A read cycle at address (BA) XX01h in word mode
(or (BA) XX02h in byte mode) returns the device code.
• A read cycle to an address containing a sector address
(SA) within the same bank, and the address 02h on
A7-A0 in word mode (or the address 04h on A6-A-1 in byte mode) returns 01h if the sector is
protected or 00h if it is unprotected.
To return to read mode, the system must write the reset command.
Enter Security Sector/Exit Security Sector Command Sequence
The Security Sector region provides a secured data area containing a random, sixteen-byte electronic
serial number (ESN). The system can access the Security Sector region by issuing the three-cycle
Enter Security Sector command sequence. The device continues to access the Security Sector region
until the system issues the four-cycle Exit Security Sector command sequence. The Exit Security
Sector command sequence returns the device to normal operation. See “Security Sector Flash Memory
Region” for further information.
6.2.4
Byte/Word Program Command Sequence
The device can be programmed either by word or byte, which depending on the state of the #BYTE pin.
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program setup command. The program address and data are
written next, which in turn initiate the Embedded Program algorithm. The device automatically provides
internally generated program pulses and verifies the programmed cell margin.
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Once the Embedded Program algorithm is complete, the bank then returns to the read mode and
addresses are no longer latched. The system can determine the status of the program operation by
using DQ7, DQ6, or RY/#BY. Please refer to the Write Operation Status section for bits' information.
Any commands written to the device during the Embedded Program Algorithm are ignored. Please note
that a hardware reset will immediately stop the program operation. The program command sequence
should be reinitiated when the bank has returned to the read mode, in order to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed
from “0” back to “1.” If trying to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6
status bits to indicate that the operation is successful. However, a succeeding read will show that the
data is still “0.” Only erase operations can change “0” to “1.”
6.2.5
Unlock Bypass Command Sequence
The unlock bypass feature provides the system to program bytes or words to a bank which is faster
than using the standard program command sequence. The unlock bypass command sequence is
initiated by first writing two unlock cycles. And a third write cycle containing the unlock bypass
command, 20h, is followed. Then, the bank enters into the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the program
address and data. In the same manner, additional data is programmed. This mode dispenses with the
initial two unlock cycles which required in the standard program command sequence, resulting in faster
total programming time.
All through the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset
commands are valid. The system must issue the two-cycle unlock bypass reset command sequence to
exit the unlock bypass mode. The first cycle must contain the bank address and the data 90h. The
second cycle needs to contain the data 00h. Then, the bank returns to the read mode.
The device offers accelerated program operations by the #WP/ACC pin. When the VHH is set at the
#WP/ACC pin, the device automatically enters into the Unlock Bypass mode. Then, the two-cycle
Unlock Bypass program command sequence may be written. To accelerate the operation, the device
must use the higher voltage on the #WP/ACC pin. Please note that the #WP/ACC pin must not be at
VHH in any operation other than accelerated programming; otherwise the device may be damaged. In
addition, the #WP/ACC pin must not be left floating or unconnected; otherwise the device inconsistent
behavior may occur.
6.2.6
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation. Writing two unlock cycles initiate the chip erase command
sequence, which is followed by a set-up command. After chip erase command, two additional unlock
write cycles are then followed, which in turn invokes the Embedded Erase algorithm. The system
preprogram is not required prior to erase. Before electrical erase, the Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern. Any controls or
timings during these operations is not required in system.
As the Embedded Erase algorithm is complete, the bank returns to the read mode and addresses are
no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/#BY. Please refer to the Write Operation Status section for information on these status bits.
- 12 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
Any commands written during the chip erase operation will be ignored. However, a hardware reset shall
terminate the erase operation immediately. If this happens, to ensure data integrity, the chip erase
command sequence should be reinitiated when that bank has returned to reading array data.
6.2.7
Sector Erase Command Sequence
Sector erase is a six-bus cycle operation. Writing two unlock cycles initiate the sector erase command
sequence, which is followed by a set-up command. Two additional unlock cycles are written, and are
then followed by the address of the sector to be erased, and the sector erase command.
The device does not require the system to preprogram before erase. Before electrical erase, the
Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data
pattern. Any controls or timings during these operations are not required in system.
A sector erase time-out of 50 μs occurs after the command sequence is written. Additional sector
addresses and sector erase commands may be written during the time-out period. Loading the sector
erase buffer may be done in any sequence, and the number of sectors may be from one sector to all
sectors. The time between these additional cycles must be less than 50 μs; otherwise, erasure may
begin. Any sector erase address and command following the exceeded time-out may or may not be
accepted. To ensure all commands are accepted, processor interrupts be disabled during this time is
recommended. The interrupts can be re-enabled after the last Sector Erase command is written. Any
command other than Sector Erase during the time-out period resets the bank to the read mode. The
system must rewrite the command sequence and any additional addresses and commands.
The system can monitor DQ3 to determine whether or not the sector erase timer has timed out (See the
section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final #WE pulse
in the command sequence.
As the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses
are no longer latched. Please note that when the Embedded Erase operation is in progress, the system
can read data from the non-erasing bank at the same time. By reading DQ7, DQ6, DQ2, or RY/#BY in
the erasing bank, the system can determine the status of the erase operation. Please refer to the Write
Operation Status section for information on these status bits.
When the sector erase operation begins, no command is valid. All commands are ignored. However, a
hardware reset shall terminate the erase operation immediately. If this occurs, to ensure data integrity,
the sector erase command sequence should be reinitiated once the bank has returned to reading array
data.
6.3
Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3,
DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or
erase operation is complete or in progress. The device also offers a hardware-based output signal,
RY/#BY, to determine whether an Embedded Program or Erase operation is in progress or has been
completed.
6.3.1
DQ7: #Data Polling
The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in progress
or completed. Data Polling is valid after the rising edge of the final #WE pulse in the command
sequence.
- 13 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data
programmed to DQ7. Once the Embedded Program algorithm has completed that the device outputs
the data programmed to DQ7. The system must provide the program address to read valid status
information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is active
for about 1μs, and then that bank returns to the read mode.
During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7. Once the Embedded Erase
algorithm has completed, #Data Polling produces “1” on DQ7. An address within any of the sectors
selected for erasure must be provided to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, #Data
Polling on DQ7 is active for about 100 μs, and then the bank returns to the read mode. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
Just before the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may change
from providing status information to valid data on DQ7. Depending on when it samples the DQ7 output,
the system may read the status or valid data. Even if the device has completed the program or erase
operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on
DQ0-DQ7 will appear on successive read cycles.
6.3.2
RY/#BY: Ready/#Busy
The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in
progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the
command sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in
parallel with a pull-up resistor to VDD.
When the output is low (Busy), the device is actively erasing or programming. When the output is high
(Ready), the device is in the read mode or the standby mode.
6.3.3
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete.
Toggle Bit I may be read at any address, and is valid after the rising edge of the final #WE pulse in the
command sequence (before the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. The system may use either #OE or #CE to control the read cycles. Once the operation has
completed, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for about 100 μs, and then returns to reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors which are protected.
If a program address falls within a protected sector, DQ6 toggles for about 1 μs after the program
command sequence is written, and then returns to reading array data.
6.3.4
Reading Toggle Bits DQ6/DQ2
Whenever the system initially starts to read toggle bit status, it must read DQ0-DQ7 at least twice in a row to
determine whether a toggle bit is toggling or not. Typically, the system would note and store the value of the
toggle bit after the first read. While after the second read, the system would compare the new value of the
- 14 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
toggle bit with the first one. If the toggle bit is not toggling, the device has completed the program or erasure
operation. The system can read array data on DQ0-DQ7 on the following read cycle.
However, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high or not(see the section on DQ5). If DQ5 is high, the system
should then determine again whether the toggle bit is toggling or not, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed
the program or erasure operation. If it is still toggling, the device did not complete the operation, and the
system must write the reset command to return to reading array data.
Then the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system
may continue to monitor the toggle bit and DQ5 through successive read cycles, and determines the status
as described in the previous paragraph. Alternatively, the system may choose to perform other system tasks.
In this case, the system must start at the beginning of the algorithm while it returns to determine the status of
the operation.
6.3.5
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not
successfully completed.
The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously
programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the device
stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.”
Under both these conditions, the system must write the reset command to return to the read mode.
6.3.6
DQ3: Sector Erase Timer
After writing a sector erasure command sequence, the system may read DQ3 to determine whether erasure
has begun or not. (The sector erase timer does not apply to the chip erase command.) The entire time-out
applies after each additional sector erasure command if additional sectors are selected for erasure. Once the
timeout period has completed, DQ3 switches from “0” to “1.” If the time between additional sector erase
commands from the system can be assumed to be less than 50 μs, the system need not monitor, DQ3 does
not need to be monitored. Please also refer to Sector Erase Command Sequence section.
After the sector erase command is written, the system should read the status of DQ7 (#Data Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3
is“1,” the Embedded Erase algorithm has begun; all further commands are ignored until the erase operation
is complete. If DQ3 is “0,” the device will accept additional sector erase commands.
The system software should check the status of DQ3 before and following each subsequent sector erase
command to ensure the command has been accepted. If DQ3 is high on the second status check, the last
command might not have been accepted.
- 15 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
7. TABLE OF OPERATION MODES
7.1
Device Bus Operations
MODE
#WP/ACC ADDRESSES DQ0-DQ7
#CE
#OE
#WE
#RESET
Read
L
L
H
H
L/H
AIN
Write
L
H
L
H
(Note2)
VDD
±0.3V
X
X
VDD ±0.3V
H
Output Disable
L
H
H
H
L/H
X
Reset
X
X
X
L
L/H
X
Sector Protect
L
H
L
VID
L/H
SA, A6=L,
A1=H, A0=L
Sector Unprotect
L
H
L
VID
(Note2)
Temporary
Sector Unprotect
X
X
X
VID
(Note2)
Standby
DQ8-DQ15
#BYTE=VIH
#BYTE =VIL
DOUT
DOUT
DQ8-DQ14
AIN
DIN
DIN
=High-Z,
DQ15=A-1
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DIN
X
X
SA, A6=H,
A1=H, A0=L
DIN
X
X
AIN
DIN
DIN
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5 ~ 11.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out.
Notes:
1.
Addresses are A20:A0 in word mode (#BYTE = VIH), A20: A-1 in byte mode (#BYTE = VIL).
2.
If #WP/ACC = VIL, the two outermost boot sectors remain protected. If #WP/ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector
Block Protection and Unprotect ion”. If #WP/ACC = VHH, all sectors will be unprotected.
- 16 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
7.2
AUTOSELECT Codes (High Voltage Method)
DESCRIPTION
#CE #OE #WE
A20
TO
A12
A11
TO
A10
A9
A8
TO
A7
A6
A5
TO
A2
A1
A0
DQ8 TO
DQ15
#BYTE #BYTE
= VIH = VIL
DQ7
TO
DQ0
Manufacturer ID:
Winbond
VIL
VIL
VIH
X
X
VID
X
VIL
X
VIL
VIL
X
X
DAh
Device ID:
W19B320BT
(Top Boot Block)
VIL
VIL
VIH
X
X
VID
X
VIL
X
VIL
VIH
22h
X
BAh
Device ID:
W19B320BB
(Bottom Boot Block)
VIL
VIL
VIH
X
X
VID
X
VIL
X
VIL
VIH
22h
X
2Ah
VIL
VIL
VIH
SA
X
VID
X
VIL
X
VIH
VIL
X
X
X
X
(protected) 00h
(unprotected)
X
82h (factory
locked)
02h (not
factory
locked)
Sector Protection
Verification
Security Indicator Bit
(DQ7)
VIL
VIL
VIH
X
X
VID
X
VIL
X
VIH
VIH
X
01h
Legend: SA= Sector Address, X= Don't Care.
- 17 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
7.3
Sector
Sector Address Table (Top Boot Block)
Sector Address
A20-A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Address Range
SA0
000000XXX
64/32
000000h-00FFFFh
000000h-07FFFh
SA1
000001XXX
64/32
010000h-01FFFFh
008000h-0FFFFh
SA2
000010XXX
64/32
020000h-02FFFFh
010000h-17FFFh
SA3
000011XXX
64/32
030000h-03FFFFh
018000h-01FFFFh
SA4
000100XXX
64/32
040000h-04FFFFh
020000h-027FFFh
SA5
000101XXX
64/32
050000h-05FFFFh
028000h-02FFFFh
SA6
000110XXX
64/32
060000h-06FFFFh
030000h-037FFFh
SA7
000111XXX
64/32
070000h-07FFFFh
038000h-03FFFFh
SA8
001000XXX
64/32
080000h-08FFFFh
040000h-047FFFh
SA9
001001XXX
64/32
090000h-09FFFFh
048000h-04FFFFh
SA10
001010XXX
64/32
0A0000h-0AFFFFh
050000h-057FFFh
SA11
001011XXX
64/32
0B0000h-0BFFFFh
058000h-05FFFFh
SA12
001100XXX
64/32
0C0000h-0CFFFFh
060000h-067FFFh
SA13
001101XXX
64/32
0D0000h-0DFFFFh
068000h-06FFFFh
SA14
001110XXX
64/32
0E0000h-0EFFFFh
070000h-077FFFh
SA15
001111XXX
64/32
0F0000h-0FFFFFh
078000h-07FFFFh
SA16
010000XXX
64/32
100000h-10FFFFh
080000h-087FFFh
SA17
010001XXX
64/32
110000h-11FFFFh
088000h-08FFFFh
SA18
010010XXX
64/32
120000h-12FFFFh
090000h-097FFFh
SA19
010011XXX
64/32
130000h-13FFFFh
098000h-09FFFFh
SA20
010100XXX
64/32
140000h-14FFFFh
0A0000h-0A7FFFh
SA21
010101XXX
64/32
150000h-15FFFFh
0A8000h-0AFFFFh
SA22
010110XXX
64/32
160000h-16FFFFh
0B0000h-0B7FFFh
SA23
010111XXX
64/32
170000h-17FFFFh
0B8000h-0BFFFFh
SA24
011000XXX
64/32
180000h-18FFFFh
0C0000h-0C7FFFh
SA25
011001XXX
64/32
190000h-19FFFFh
0C8000h-0CFFFFh
SA26
011010XXX
64/32
1A0000h-1AFFFFh
0D0000h-0D7FFFh
SA27
011011XXX
64/32
1B0000h-1BFFFFh
0D8000h-0DFFFFh
SA28
011100XXX
64/32
1C0000h-1CFFFFh
0E0000h-0E7FFFh
SA29
011101XXX
64/32
1D0000h-1DFFFFh
0E8000h-0EFFFFh
SA30
011110XXX
64/32
1E0000h-1EFFFFh
0F0000h-0F7FFFh
SA31
011111XXX
64/32
1F0000h-1FFFFFh
0F8000h-0FFFFFh
SA32
100000XXX
64/32
200000h-20FFFFh
100000h-107FFFh
SA33
100001XXX
64/32
210000h-21FFFFh
108000h-10FFFFh
SA34
100010XXX
64/32
220000h-22FFFFh
110000h-117FFFh
- 18 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
Sector Address Table (Top Boot Block), continued
SECTOR ADDRESS
SECTOR SIZE
(Kbytes/Kwords)
(X8)
(X16)
A20-A12
ADDRESS RANGE
ADDRESS RANGE
SA35
100011XXX
64/32
230000h-23FFFFh
118000h-11FFFFh
SA36
100100XXX
64/32
240000h-24FFFFh
120000h-127FFFh
SA37
100101XXX
64/32
250000h-25FFFFh
128000h-12FFFFh
SECTOR
SA38
100110XXX
64/32
260000h-26FFFFh
130000h-137FFFh
SA39
100111XXX
64/32
270000h-27FFFFh
138000h-13FFFFh
SA40
101000XXX
64/32
280000h-28FFFFh
140000h-147FFFh
SA42
101010XXX
64/32
2A0000h-2AFFFFh
150000h-157FFFh
SA43
101011XXX
64/32
2B0000h-2BFFFFh
158000h-15FFFFh
SA44
101100XXX
64/32
2C0000h-2CFFFFh
160000h-167FFFh
SA45
101101XXX
64/32
2D0000h-2DFFFFh
168000h-16FFFFh
SA46
101110XXX
64/32
2E0000h-2EFFFFh
170000h-177FFFh
SA47
101111XXX
64/32
2F0000h-2FFFFFh
178000h-17FFFFh
SA48
110000XXX
64/32
300000h-30FFFFh
180000h-187FFFh
SA49
110001XXX
64/32
310000h-31FFFFh
188000h-18FFFFh
SA50
110010XXX
64/32
320000h-32FFFFh
190000h-197FFFh
SA51
110011XXX
64/32
330000h-33FFFFh
198000h-19FFFFh
SA52
110100XXX
64/32
340000h-34FFFFh
1A0000h-1A7FFFh
SA53
110101XXX
64/32
350000h-35FFFFh
1A8000h-1AFFFFh
SA54
110110XXX
64/32
360000h-36FFFFh
1B0000h-1B7FFFh
SA55
110111XXX
64/32
370000h-37FFFFh
1B8000h-1BFFFFh
SA56
111000XXX
64/32
380000h-38FFFFh
1C0000h-1C7FFFh
SA57
111001XXX
64/32
390000h-39FFFFh
1C8000h-1CFFFFh
SA58
111010XXX
64/32
3A0000h-3AFFFFh
1D0000h-1D7FFFh
SA59
111011XXX
64/32
3B0000h-3BFFFFh
1D8000h-1DFFFFh
SA60
111100XXX
64/32
3C0000h-3CFFFFh
1E0000h-1E7FFFh
SA61
111101XXX
64/32
3D0000h-3DFFFFh
1E8000h-1EFFFFh
SA62
111110XXX
64/32
3E0000h-3EFFFFh
1F0000h-1F7FFFh
SA63
111111000
8/4
3F0000h-3F1FFFh
1F8000h-1F8FFFh
SA64
111111001
8/4
3F2000h-3F3FFFh
1F9000h-1F9FFFh
SA65
111111010
8/4
3F4000h-3F5FFFh
1FA000h-1FAFFFh
SA66
111111011
8/4
3F6000h-3F7FFFh
1FB000h-1FBFFFh
SA67
111111100
8/4
3F8000h-3F9FFFh
1FC000h-1FCFFFh
SA68
111111101
8/4
3FA000h-3FBFFFh
1FD000h-1FDFFFh
SA69
111111110
8/4
3FC000h-3FDFFFh
1FE000h-1FEFFFh
SA70
111111111
8/4
3FE000h-3FFFFFh
1FF000h-1FFFFFh
Note: The address range is [A20: A-1] in byte mode (#BYTE =VIL) or [A20:A0] in word mode (#BYTE = VIH).
- 19 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
Security Sector Addresses for Top Boot Devices
DEVICE
W19B320BT/
B
7.4
Sector Address
A20-A12
111111XXX
SECTOR SIZE
(bytes/words)
(X 8)
(X 16)
ADDRESS RANGE
ADDRESS RANGE
3FE000h-3FE0FFh
1FF000h-1FF07Fh
256/128
Sector Address Table (Bottom Boot Block)
SECTOR ADDRESS
SECTOR SIZE
(Kbytes/Kwords)
(X8)
(X16)
A20-A12
ADDRESS RANGE
ADDRESS RANGE
SA0
000000000
8/4
000000h-001FFFh
000000h-000FFFh
SA1
000000001
8/4
002000h-003FFFh
001000h-001FFFh
SA2
000000010
8/4
004000h-005FFFh
002000h-002FFFh
SA3
000000011
8/4
006000h-007FFFh
003000h-003FFFh
SA4
000000100
8/4
008000h-009FFFh
004000h-004FFFh
SA5
000000101
8/4
00A000h-00BFFFh
005000h-005FFFh
SA6
000000110
8/4
00C000h-00DFFFh
006000h-006FFFh
SA7
000000111
8/4
00E000h-00FFFFh
007000h-007FFFh
SA8
000001XXX
64/32
010000h-01FFFFh
008000h-00FFFFh
SA9
000010XXX
64/32
020000h-02FFFFh
010000h-017FFFh
SA10
000011XXX
64/32
030000h-03FFFFh
018000h-01FFFFh
SECTOR
SA11
000100XXX
64/32
040000h-04FFFFh
020000h-027FFFh
SA12
000101XXX
64/32
050000h-05FFFFh
028000h-02FFFFh
SA13
000110XXX
64/32
060000h-06FFFFh
030000h-037FFFh
SA14
000111XXX
64/32
070000h-07FFFFh
038000h-03FFFFh
SA15
001000XXX
64/32
080000h-08FFFFh
040000h-047FFFh
SA16
001001XXX
64/32
090000h-09FFFFh
048000h-04FFFFh
SA17
001010XXX
64/32
0A0000h-0AFFFFh
050000h-057FFFh
058000h-05FFFFh
SA18
001011XXX
64/32
0B0000h-0BFFFFh
SA19
001100XXX
64/32
0C0000h-0CFFFFh
060000h-067FFFh
SA20
001101XXX
64/32
0D0000h-0DFFFFh
068000h-06FFFFh
SA21
001110XXX
64/32
0E0000h-0EFFFFh
070000h-077FFFh
SA22
001111XXX
64/32
0F0000h-0FFFFFh
078000h-07FFFFh
SA23
010000XXX
64/32
100000h-10FFFFh
080000h-087FFFh
SA24
010001XXX
64/32
110000h-11FFFFh
088000h-08FFFFh
SA25
010010XXX
64/32
120000h-12FFFFh
090000h-097FFFh
SA26
010011XXX
64/32
130000h-13FFFFh
098000h-09FFFFh
SA27
010100XXX
64/32
140000h-14FFFFh
0A0000h-0A7FFFh
SA28
010101XXX
64/32
150000h-15FFFFh
0A8000h-0AFFFFh
SA29
010110XXX
64/32
160000h-16FFFFh
0B0000h-0B7FFFh
SA30
010111XXX
64/32
170000h-17FFFFh
0B8000h-0BFFFFh
SA31
011000XXX
64/32
180000h-18FFFFh
0C0000h-0C7FFFh
- 20 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
Sector Address Table (Bottom Boot Block), continued
SECTOR ADDRESS
(X8)
(X16)
ADDRESS RANGE
ADDRESS RANGE
64/32
190000h-19FFFFh
0C8000h-0CFFFFh
64/32
1A0000h-1AFFFFh
0D0000h-0D7FFFh
011011XXX
64/32
1B0000h-1BFFFFh
0D8000h-0DFFFFh
SA35
011100XXX
64/32
1C0000h-1CFFFFh
0E0000h-0E7FFFh
SA36
011101XXX
64/32
1D0000h-1DFFFFh
0E8000h-0EFFFFh
SA37
011110XXX
64/32
1E0000h-1EFFFFh
0F0000h-0F7FFFh
SA38
011111XXX
64/32
1F0000h-1FFFFFh
0F8000h-0FFFFFh
A20-A12
SECTOR SIZE
(Kbytes/Kwords)
SA32
011001XXX
SA33
011010XXX
SA34
SECTOR
SA39
100000XXX
64/32
200000h-20FFFFh
100000h-107FFFh
SA40
100001XXX
64/32
210000h-21FFFFh
108000h-10FFFFh
SA41
100010XXX
64/32
220000h-22FFFFh
110000h-117FFFh
SA42
100011XXX
64/32
230000h-23FFFFh
118000h-11FFFFh
SA43
100100XXX
64/32
240000h-24FFFFh
120000h-127FFFh
SA44
100101XXX
64/32
250000h-25FFFFh
128000h-12FFFFh
SA45
100110XXX
64/32
260000h-26FFFFh
130000h-137FFFh
SA46
100111XXX
64/32
270000h-27FFFFh
138000h-13FFFFh
SA47
101000XXX
64/32
280000h-28FFFFh
140000h-147FFFh
SA48
101001XXX
64/32
290000h-29FFFFh
148000h-14FFFFh
SA49
101010XXX
64/32
2A0000h-2AFFFFh
150000h-157FFFh
SA50
101011XXX
64/32
2B0000h-2BFFFFh
158000h-15FFFFh
SA51
101100XXX
64/32
2C0000h-2CFFFFh
160000h-167FFFh
SA52
101101XXX
64/32
2D0000h-2DFFFFh
168000h-16FFFFh
SA53
101110XXX
64/32
2E0000h-2EFFFFh
170000h-177FFFh
SA54
101111XXX
64/32
2F0000h-2FFFFFh
178000h-17FFFFh
SA55
111000XXX
64/32
300000h-30FFFFh
180000h-187FFFh
SA56
110001XXX
64/32
310000h-31FFFFh
188000h-18FFFFh
SA57
110010XXX
64/32
320000h-32FFFFh
190000h-197FFFh
SA58
110011XXX
64/32
330000h-33FFFFh
198000h-19FFFFh
SA59
110100XXX
64/32
340000h-34FFFFh
1A0000h-1A7FFFh
SA60
110101XXX
64/32
350000h-35FFFFh
1A8000h-1AFFFFh
SA61
110110XXX
64/32
360000h-36FFFFh
1B0000h-1B7FFFh
SA62
110111XXX
64/32
370000h-37FFFFh
1B8000h-1BFFFFh
SA63
111000XXX
64/32
380000h-38FFFFh
1C0000h-1C7FFFh
SA64
111001XXX
64/32
390000h-39FFFFh
1C8000h-1CFFFFh
SA65
111010XXX
64/32
3A0000h-3AFFFFh
1D0000h-1D7FFFh
SA65
111011XXX
64/32
3B0000h-3BFFFFh
1D8000h-1DFFFFh
SA67
111100XXX
64/32
3C0000h-3CFFFFh
1E0000h-1E7FFFh
SA68
111101XXX
64/32
3D0000h-3DFFFFh
1E8000h-1EFFFFh
SA69
111110XXX
64/32
3E0000h-3EFFFFh
1F0000h-1F7FFFh
SA70
111111XXX
64/32
3F0000h-3FFFFFh
1F8000h-1FFFFFh
Note: The address range is [A20: A-1] in byte mode (#BYTE =VIL) or [A20:A0] in word mode (#BYTE =VIH).
- 21 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
Security Sector Addresses for Bottom Boot Devices
DEVICE
W19B320BT/
B
SECTOR ADDRESS
(X8)
(X16)
A20-A12
SECTOR SIZE
(bytes/words)
ADDRESS RANGE
ADDRESS RANGE
000000XXX
256/128
000000h-0000FFh
000000h-00007Fh
- 22 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
Top Boot Sector/Sector Block Address for Protection/Unprotection)
SECTOR
A20-A12
SECTOR/SECTOR BLOCK SIZE
SA0-SA3
000000XXX
000001XXX
000010XXX
000011XXX
256(4x64) K bytes
SA4-SA7
0001XXXXX
256(4x64) K bytes
SA8-SA11
0010XXXXX
256(4x64) K bytes
SA12-SA15
0011XXXXX
256(4x64) K bytes
SA16-SA19
0100XXXXX
256(4x64) K bytes
SA20-SA23
0101XXXXX
256(4x64) K bytes
SA24-SA27
0110XXXXX
256(4x64) K bytes
SA28-SA31
0111XXXXX
256(4x64) K bytes
SA32-SA35
1000XXXXX
256(4x64) K bytes
SA36-SA39
1001XXXXX
256(4x64) K bytes
SA40-SA43
1010XXXXX
256(4x64) K bytes
SA44-SA47
1011XXXXX
256(4x64) K bytes
SA48-SA51
1100XXXXX
256(4x64) K bytes
SA52-SA55
1101XXXXX
256(4x64) K bytes
SA56-SA59
1110XXXXX
256(4x64) K bytes
SA60-SA62
111100XXX
111101XXX
111110XXX
192(3x64) K bytes
SA63
111111000
8 K bytes
SA64
111111001
8 K bytes
SA65
111111010
8 K bytes
SA66
111111011
8 K bytes
SA67
111111100
8 K bytes
SA68
111111101
8 K bytes
SA69
111111110
8 K bytes
SA70
111111111
8 K bytes
- 23 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
Bottom Boot Sector/Sector Block Address for Protection/Unprotection)
SECTOR
A20-A12
SECTOR/SECTOR BLOCK SIZE
SA70-SA67
111111XXX
111110XXX
111101XXX
111100XXX
256(4x64) K bytes
SA66-SA63
1110XXXXX
256(4x64) K bytes
SA62-SA59
1101XXXXX
256(4x64) K bytes
SA58-SA55
1100XXXXX
256(4x64) K bytes
SA54-SA51
1011XXXXX
256(4x64) K bytes
SA50-SA47
1010XXXXX
256(4x64) K bytes
SA46-SA43
1001XXXXX
256(4x64) K bytes
SA42-SA39
1000XXXXX
256(4x64) K bytes
SA38-SA35
0111XXXXX
256(4x64) K bytes
SA34-SA31
0110XXXXX
256(4x64) K bytes
SA30-SA27
0101XXXXX
256(4x64) K bytes
SA26-SA23
0100XXXXX
256(4x64) K bytes
SA22-SA19
0011XXXXX
256(4x64) K bytes
SA18-SA15
0010XXXXX
256(4x64) K bytes
SA14-SA11
0001XXXXX
256(4x64) K bytes
SA10-SA8
000011XXX
000010XXX
000001XXX
192(3x64) K bytes
SA7
000000111
8 K bytes
SA6
000000110
8 K bytes
SA5
000000101
8 K bytes
SA4
000000100
8 K bytes
SA3
000000011
8 K bytes
SA2
000000010
8 K bytes
SA1
000000001
8 K bytes
SA0
000000000
8 K bytes
- 24 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
7.5
CFI Query Identification String
ADDRESS
(Word Mode)
DATA
ADDRESS
(Byte Mode)
10h
0051h
20h
11h
0052h
22h
12h
0059h
24h
13h
0002h
26h
14h
0000h
28h
15h
0040h
2Ah
16h
0000h
2Ch
17h
0000h
2Eh
18h
0000h
30h
19h
0000h
32h
1Ah
0000h
34h
ADDRESS
(Word Mode)
DATA
ADDRESS
(Byte Mode)
1Bh
0027h
36h
1Ch
0036h
38h
VPP Min. voltage (00h=no VPP pin present)
1Dh
0000h
3Ah
VPP Max. voltage (00h=no VPP pin present)
1Eh
0000h
3Ch
Typical timeout per single byte/word write 2N μs
1Fh
0004h
3Eh
Typical timeout for Min. size buffer write 2N μs (00h=not supported)
20h
0000h
40h
Typical timeout per individual block erase 2N ms
21h
000Ah
42h
Typical timeout for full chip erase 2N ms (00h=not supported)
22h
0000h
44h
23h
0005h
46h
24h
0000h
48h
25h
0004h
4Ah
26h
0000h
4Ch
DESCRIPTION
Query-unique ASCII string "QRY"
Primary OEM Command Set
Address for primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternative OEM Extended table (00h = none exists)
7.5.1
System Interface String
DESCRIPTION
VDD Min. (write/erase)
D7-D4: volt , D3-D0: 100 mV
VDD Max. (write/erase)
D7-D4: volt , D3-D0: 100 mV
Max. timeout for byte/word write
Max. timeout for buffer write
2N
2N times
times typical
Max. timeout per individual block erase
Max. timeout for full chip erase
supported)
typical
2N
2N
times typical
times typical ( 00h = not
- 25 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
7.5.2
Device Geometry Definition
ADDRESS
(Word Mode)
DATA
ADDRESS
(Byte Mode)
27h
0016h
4Eh
28h
0002h
50h
29h
0000h
52h
2Ah
0000h
54h
2Bh
0000h
56h
2Ch
0002h
58h
2Dh
0007h
5Ah
Erase Block Region 1 Information
2Eh
0000h
5Ch
(refer to the CFI specification or CFI publication 100 )
2Fh
0020h
5Eh
30h
0000h
60h
31h
003Eh
62h
32h
0000h
64h
33h
0000h
66h
34h
0001h
68h
35h
0000h
6Ah
36h
0000h
6Ch
37h
0000h
6Eh
38h
0000h
70h
39h
0000h
72h
3Ah
0000h
74h
3Bh
0000h
76h
3Ch
0000h
78h
DESCRIPTION
Device size =2N bytes
Flash device interface description (refer to CFI publication 100)
Max. number of bytes in multi-byte write=2N (00h=not supported)
Number of Erase Block Regions within devices
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
- 26 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
7.5.3
Primary Vendor-Specific Extended Query
ADDRESS
(Word Mode)
DATA
ADDRESS
( Byte Mode)
40h
0050h
80h
41h
0052h
82h
42h
0049h
84h
Major version number, ASCII
43h
0031h
86h
Minor version number, ASCII
44h
0033h
88h
45h
0001h
8Ah
46h
0000h
8Ch
47h
0001h
8Eh
48h
0001h
90h
49h
0004h
92h
4Ah
0038h
94h
4Bh
0000h
96h
4Ch
0000h
98h
4Dh
0085h
9Ah
4Eh
0095h
9Ch
DESCRIPTION
Query-unique ASCII string "PRI"
Silicon Revision Number
01h = 0.13 μm
Erase suspend
0 = Not supported, 1= To read only; 2 = To read & write
Sector protect
00 = Not supported, 01=Supported
Sector Temporary Unprotect
00 = Not supported, 01=Supported
Sector protect/unprotect scheme
Simultaneous operation
Number of Sectors (except for Bank 1)
Burst mode type
00 = Not supported, 01=Supported
Page mode type
00 = Not Supported, 01=4 Word Page, 02=8 Word Page
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
4Fh
02h=Bottom Boot Device, 03h=Top Boot Device
- 27 -
000Xh
9Eh
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
7.5.4
Command Definitions
BUS CYCLES (note 2-5)
COMMAND
SEQUENCE
(note 1 )
CYCLE
FIRST
ADDR
DATA
Read (note 6)
1
RA
RD
Reset (note 7)
1
XXX
F0
Normal
Program
Unlock Bypass
Word
Byte
Word
Byte
4
3
555
AAA
555
AAA
AA
AA
SECOND
ADDR
2AA
555
2AA
555
DATA
55
55
Unlock Bypass
Program (note 11)
2
XXX
A0
PA
PD
Unlock Bypass Reset
(note12)
2
XXX
90
XXX
00
Chip Erase
Sector Erase
Word
Byte
Word
Byte
AUTOSELECT(note8)
Manufacturer Word
Code
Byte
Device
Code
Word
Byte
Security
Word
Sector Factory
Protect (Note Byte
9)
Sector/Sect
or Block
Protect
Verify (note
10)
6
6
4
4
555
AAA
555
AAA
555
AAA
555
AAA
AAA
4
Exit Security
Sector Region
Word
Common Flash
Interface (CFI)
Query (note 15)
Word
Byte
Byte
Byte
AA
AA
4
555
2AA
555
2AA
555
2AA
555
555
AA
555
AAA
555
AAA
55
55
55
55
AA
555
AAA
555
AAA
555
AAA
555
AAA
55
AAA
AAA
55
2AA
555
2AA
555
ADDR
DATA
A0
PA
PD
80
80
90
90
55
555
AAA
555
AAA
X00
X01
X02
X06
555
555
AAA
AA
AA
2AA
555
2AA
555
55
55
555
AAA
SA
10
30
DA
(note
16)
82/02
X02
90
AAA
SIXTH
DATA ADDR DATA
X03
90
AAA
55
FIFTH
ADDR
20
555
555
AA
555
AAA
FOURTH
DATA
555
55
2AA
AAA
3
2AA
2AA
AA
555
Byte
Word
AA
555
4
Word
Enter Security
Sector Region
AA
THIRD
ADDR
00/01
X04
88
90
XXX
00
55
1
AA
98
Legend:
X = Don’t Care
RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the #WE or #CE pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of #WE or #CE pulse, whichever happens first.
RD = Data read from location RA during read operation.
SA = Address of the sector to be verified (in AUTOSELECT mode) or erased. Address bits A20-A12 uniquely select any sector.
Notes:
1. See Bus Operations Table for details.
2. All values are in hexadecimal.
- 28 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
3. Except for the read cycle and the fourth cycle of the AUTOSELECT command sequence, all bus cycles are write cycles.
4. Data bits DQ15-DQ8 are don’t care in command sequences, except for RD and PD.
5. Unless otherwise noted, address bits A20-A11 are “don’t care”.
6. No unlock or command cycles required when bank is reading array data.
7. The Reset command is required to return to the read mode when the device is in the AUTOSELECT mode, or if DQ5
goes high (while the device is providing status information).
8. The fourth cycle of the AUTOSELECT command sequence is a read cycle. Data bits DQ15-DQ8 are don’t care. See the
AUTOSELECT Command Sequence section for more information.
9. The data is 82h for factory locked and 02h for not factory locked.
10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
11. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
12. The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode.
13. Command is valid when device is ready to read array data or when device is in AUTOSELECT mode.
14. See Autoselect Codes table for device ID information
7.5.5
Write Operation Status
DQ7
(Note 2)
DQ6
DQ5
(Note1)
DQ3
DQ2
(Note 2)
RY/#BY
Embedded Program
Algorithm
#DQ7
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Status
Standard
Mode
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing
limits. Refer to DQ5 description section for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded
Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
- 29 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
7.6
Temporary Sector Unprotect Algorithm
START
#RESET = VID
(Note 1)
Perform Erase or
Program Operations
#RESET = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected (If #WP/ACC = VIL, outermost boot sectors will remain protected).
2. All previously protected sectors are protected once again.
- 30 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
7.7
In-System Sector Protect/Unprotect Algorithms
START
START
PLSCNT=1
#RESET=VID
Wait 1 μ s
No
Temporary Sector
Unprotect Mode
Protect all sectors
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT=1
#RESET=VID
Wait 1 μ s
No
First Write
Cycle=60h?
First Write
Cycle=60h?
Yes
Yes
No
Set up sector
address
All sectors
protected ?
Sector Protect:
Write 60h to sector
address with
A6=0,A1=1,A0=0
Yes
Set up first sector
address
Wait 150 μ s
Verity Sector
Protect:Write 40h
to sector address
with A6=0,
Increment
PLSCNT
Sector Unprotect:
Write 60h to any
address with
A6=1,A1=1,A0=0
Reset
PLSCNT=1
Wait 15 mS
Increment
PLSCNT
A1=1,A0=0
A1=1,A0=0
Read from
sector address
with A6=1,
A1=1,A0=0
No
PLSCNT
=25?
Yes
Device failed
Data=01h?
No
Yes
Protect another
sector?
PLSCNT
=1000?
Yes
Yes
No
Remove VID
from #RESET
Sector Protect
Algorithm
Verity Sector
Unprotect:Write 40h
to sector address
with A6=1,
Read from
sector address
with A6=0,
A1=1,A0=0
No
No
Set up
next sector
address
Data=00h?
Yes
No
Device failed
Write reset
command
Sector Protect
complete
Temporary Sector
Unprotect Mode
Sector Unprotect
Algorithm
Last sector
verified
Yes
Remove VID
from #RESET
Write reset
command
Sector Unprotect
complete
- 31 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
7.8
Security Sector Protect Verify
START
Enter Security
Sector
If data = 00h,
Security Sector is
unprotected.
If data = 01h,
Security Sector is
producted.
#RESET =
V IH or V ID
Wait 1 μ s
Remove V IH or V ID
from #RESET
Write 60h to
any address
Write reset
command
Write 40h to Security
Sector Address
with A6 = 0
A1 = 1, A0 = 0
Exit Security
Sector
Read from Security
Sector address
Security Sector
Protect Verify
complete
with A6 = 0
A1 = 1, A0 = 0
7.9
Program Algorithm
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
- 32 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
7.10
Erase Algorithm
START
Write Program
Command Sequence
(Note1,2)
Data Poll to Erasing
Bank from System
No
Embedded
Erase
algorithm
in progress
Data=FFh?
Yes
Erase Completed
Notes:
1. See Command Definitions Table for erase command sequence details.
2. See DQ3 section for the sector erase timer details.
7.11
Data Polling Algorithm
START
Read DQ7-DQ0
Addr=VA
Yes
DQ7=Data?
No
No
DQ5=1?
Yes
Read DQ7-DQ0
Addr=VA
DQ7=Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector erase operation; a valid address is any sector address within the
sector being erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
- 33 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
7.12
Toggle Bit Algorithm
START
Read DQ7-DQ0
Read DQ7-DQ0
Toggle Bit
=Toggle?
No
Yes
No
DQ5=1?
Yes
Read DQ7-DQ0
Twice
Toggle Bit
=Toggle?
No
Yes
Program/Erase
Operation Not
Complete,Write
Reset Command
Program/Erase
Complete
Note: The system should recheck the toggle bit even if DQ5 =”1” because the toggle bit may stop toggling as DQ5 changes to “1”.
See DQ6 and DQ2 section for more information
- 34 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
8. ELECTRICAL CHARACTERISTICS
8.1
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Storage Temperature Plastic Packages
-65 to +150
°C
Ambient Temperature with Power Applied
-65 to +125
°C
VDD (Note 1)
-0.5 to +4.0
V
A9, #OE, and #RESET (Note 2)
-0.5 to +11.5
V
#WP/ACC
-0.5 to +10.5
V
-0.5 to VDD +0.5
V
200
mA
Voltage with Respect
to Ground
All other pins (Note 1)
Output Short Circuit Current (Note 3)
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0
V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VDD +0.5 V. During voltage transitions, input or
I/O pins may overshoot to VDD +2.0 V for periods up to 20 ns.
2. Minimum DC input voltage on pins A9, #OE, #RESET, and #WP/ACC is -0.5 V. During voltage transitions, A9, #OE,
#WP/ACC, and #RESET may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is
+11.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on #WP/ACC is +9.5 V
which may overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one
second.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at these or any other conditions above those indicated in
the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
8.2
Operating Ranges
PARAMETER
Ambient Temperature (TA )
RATING
Industrial Grade
-40 to +85
Extended Grade
-20 to +85
VDD Supply Voltages
2.7 to 3.6
VDD for standard voltage range
UNIT
°C
V
Operating ranges define those limits between which the functionality of the device is guaranteed.
- 35 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
8.3
8.4
DC Characteristics
CMOS Compatible
PARAMETER
SYM.
LIMITS
TEST CONDITIONS
MIN.
TYP.
MAX.
±1.0
UNIT
μA
Input Load Current
ILI
VIN =VSS to VDD, VDD = VDD (Max.)
-
-
A9 Input Load Current
ILIT
VDD = VDD (Max.), A9 = VID (Max.)
-
-
35
μA
Output Leakage Current
ILO
VOUT =VSS to VDD, VDD =VDD (Max.)
-
-
#CE = VIL, #OE = VIH
5 MHz
1 MHz
5 MHz
1 MHz
-
10
2
10
2
±1.0
16
4
16
4
μA
mA
mA
mA
mA
#CE = VIL, #OE = VIH, #WE = VIL
-
15
30
mA
-
0.2
5
μA
VDD Active Read Current
(Note 1, 2)
ICC1
Byte Mode
#CE = VIL, #OE = VIH
Word Mode
VDD Active Write Current
(Note 2, 3)
ICC2
#CE = VDD ±0.3V, #RESET = VDD
VDD Standby Current (Note2,5)
ICC3
VDD Reset Current (Note2)
ICC4
#RESET = VSS ±0.3V
-
0.2
5
μA
Automatic Sleep Mode
Current (note 2, 4,5)
ICC5
VIH = VDD ±0.3V, VIL = VSS ±0.3V
-
0.2
5
μA
ACC Accelerated Program
Current, Word or Byte
IAcc
#CE = VIL, #OE = VIH
-0.5
0.7x VDD
5
15
-
10
30
0.8
VDD +0.3
mA
mA
V
V
Input Low Voltage
Input High Voltage
Voltage for #WP/ACC Sector
Protect/ Unprotect and
Program Acceleration
Voltage for AUTOSELECT
and Temporary Sector
Unprotected
Output Low Voltage
Output High Voltage
±0.3V
VIL
VIH
ACC Pin
VDD Pin
-
VHH
VDD =3.0V ±10%
8.5
-
9.5
V
VID
VDD =3.0V ±10%
8.5
-
11.5
V
V
V
VOL
VOH1
IOL = 4.0 mA, VDD = VDD (Min.)
IOH = -2.0 mA, VDD = VDD (Min.)
0.85 VDD
-
0.45
-
VOH2
IOH = -100 μA, VDD = VDD (Min.)
VDD -0.4
-
-
Notes:
1.
2.
3.
4.
The ICC current listed is typically less than 2 mA/ MHz, with #OE at VIH.
Maximum ICC specifications are tested with VDD = VDD max.
ICC active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode
current is200 nA.
5. For temperature >70 degree C, Vih(Max.)=Vdd+0.1V and Vil(Min)=Vss-0.1V.
6. Not 100% tested
- 36 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
8.5
8.6
AC Characteristics
Test Condition
TEST CONDITION
70ns
Output Load
UNIT
1 TTL gate
Output Load Capacitance, CL (including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
0-3.0
V
Input timing measurement reference levels
1.5
V
Output timing measurement reference levels
1.5
V
Input Pulse Levels
8.6.1
AC Test Load and Waveforms
- 37 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
8.7
Read-Only Operations
PARAMETER
Read Cycle Time
SYM.
70ns
TEST SETUP
MAX.
70
-
ns
#OE, #CE =VIL
-
70
ns
#OE, = VIL
-
70
ns
TRC
Address to Output Delay
TACC
UNIT
MIN.
Chip Enable to Output Delay
TCE
Output Enable to Output Delay
TOE
-
30
ns
Chip Enable to Output High Z
TDF
-
16
ns
Output Enable to Output High Z
TDF
-
16
ns
Output Hold Time From Address, #OE or #CE,
Whichever Occurs First
TOH
0
-
ns
0
-
ns
10
-
ns
Read
Output Enable Hold Time
Toggle and
#Data polling
TOEH
Note: Not 100 % tested
8.8
Hardware Reset (#RESET)
PARAMETER
SYM.
MIN.
MAX.
UNIT
#RESET PIN Low (During Embedded Algorithms) to
Read Mode
TReady
-
20
μs
#RESET Pin Low (Not During Embedded Algorithms)
to Read Mode
TReady
-
500
ns
#RESET Pulse Width
TRP
500
-
ns
Reset High Time Before Read
TRH
50
-
ns
#RESET Low to Standby Mode
TRPD
20
-
μs
TRB
0
-
ns
RY/#BY Recovery Time
Note: Not 100 % tested
8.9
Word/Byte Configuration (#BYTE)
PARAMETER
SYM.
70ns
MIN.
MAX.
UNIT
#CE to #BYTE Switching Low or High
TELFL/TELFH
-
5
ns
#BYTE Switching Low to Output High Z
TFLQZ
-
16
ns
#BYTE Switching High to Output Active
TFHQV
70
-
ns
- 38 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
8.10
Erase and Program Operation
PARAMETER
70ns
SYM.
MIN.
TYP.
MAX.
UNIT
Write Cycle Timing (Note 1)
TWC
70
-
-
ns
Address setup Time
TAS
0
-
-
ns
TASO
15
-
-
Address Hold Time
TAH
45
-
-
ns
Address Hold Time From #CE or #OE high during
toggle bit polling
TAHT
0
-
-
ns
Data Setup Time
TDS
35
-
-
ns
Data Hold Time
TDH
0
-
-
ns
Output Enable High During toggle bit polling
TOEPH
20
-
-
ns
Read Recovery Time Before Write (#OE High to
#WE Low)
TGHWL
0
-
-
ns
TCS
0
-
-
ns
Address Setup Timing to #OE low during toggle bit
polling
#CE Setup Time
ns
#CE HOLD Time
TCH
0
-
-
ns
Write Pulse Width
TWP
30
-
-
ns
Write Pulse Width High
TWPH
30
-
-
ns
Latency Between Read and Write Operation
TSR/W
0
-
-
ns
Byte
TPB
-
7
150
μs
Word
TPW
-
9
210
μs
TACCP
4
-
μs
Programming Time (Note 2)
Accelerated Programming Time
(Noe2)
Byte
Word
Sector Erase Time (Note 2)
TSE
-
0.4
-
sec
VDD Setup Time (Note 1)
TVCS
50
-
-
μs
Write Recovery Time from RY/#BY
TRB
0
-
-
ns
TBUSY
90
-
-
ns
Program/Erase Valid to RY/#BY Delay
Notes:
1.
2.
Not 100 % tested
See the “Alternate #CE Controlled Erase and Program Operations“ section for more information
8.11
Temporary Sector Unprotect
PARAMETER
SYM.
MIN.
MAX.
UNIT
VID Rise and Fall Time
TVIDR
500
-
ns
VHH Rise and Fall Time
TVHH
250
-
ns
#RESET Setup Time for Temporary Sector Unprotect
TRSP
4
-
μs
#RESET Hold Time from RY/#BY High for Temporary
Sector Unprotect
TRRB
4
-
μs
Note: Not 100 % tested1
- 39 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
8.12
Alternate #CE Controlled Erase and Program Operations
70 ns
PARAMETER
SYM.
Min.
Typical
Max.
(Note3)
(Note4)
Unit
Write Cycle Time (Note 1)
TWC
70
-
-
ns
Address Setup Time
TAS
0
-
-
ns
Address Hold Time
TAH
45
-
-
ns
Data Setup Time
TDS
35
-
-
ns
Data Hold Time
TDH
0
-
-
ns
TGHEL
0
-
-
ns
#WE Setup Time
TWS
0
-
-
ns
#WE Hold Time
TWH
0
-
-
ns
#CE Pulse Width
TCP
30
-
-
ns
TCPH
30
-
-
ns
Byte
TPB
-
7
150
Word
TPW
-
9
210
TACCP
-
4
120
μs
Sector Erase Time (Note 2)
TSE
-
0.4
15
sec
Chip Erase Time (Note 2)
TCE
-
30
-
sec
Byte
TCPB
-
21
63
Word
TCPW
-
14
42
Read Recover Time Before Write (#OE High to
#WE Low)
#CE Pulse Width High
Programming Time (Note 6)
Accelerated Programming Time
(Note 6)
Chip Program Time (Note 5)
Byte
Word
μs
sec
Notes:
1. Not 100 % tested.
2. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
3. Typical program and erase time assume the following conditions :25℃,3.0 V VDD, 100,000 cycles .Additionally,
programming typicals assume checkerboard pattern.
4. Under worst case conditions of 90℃, VDD =2.7V, 100,000 cycles.
5. The typical chip programming time is considerably less than the maximun chip programming time listed,since most bytes
program faster than maximun program times listed.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
7. The device has a minimum erase and program cycle endurance of 100,000 cycles.
- 40 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
9. TIMING WAVEFORMS
9.1
AC Read Waveform
TRC
Addresses Stable
Address
TACC
#CE
TRH
#OE
TRH
TOE
TDF
TOEH
#WE
T CE
T OH
High-Z
Outputs
High-Z
Output Valid
#RESET
RY/#BY
9.2
0V
Reset Waveform
RY/#BY
#OE,#CE
TRH
#RESET
TRP
TReady
Reset Timing NOT during Embedded Algorithms
TReady
RY/#BY
TRB
#OE,#CE
#RESET
TRP
Reset Timings during Embedded Algorithms
- 41 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
9.3
#BYTE Waveform for Read Operation
#CE
#OE
#BYTE
#BYTE
Switching
from word
to byte
mode
TELFL
Data Output
(DQ0-DQ14)
DQ0-DQ14
Data Output
(DQ0-DQ7)
DQ15
Output
DQ15/A-1
TELFH
Address
Input
TFLQZ
#BYTE
#BYTE
Switching
from byte
to word
mode
DQ0-DQ14
DQ15/A-1
Data Output
(DQ0-DQ7)
Address
Input
Data Output
(DQ0-DQ14)
DQ15
Output
TFHQV
9.4
#BYTE Waveform for Write Operation
#CE
The falling edge of the last #WE signal
#WE
#BYTE
T SET
(TAS )
THOLD (TAH )
Note: Refer to the Erase /Program Operations table for TAS and TAH Specifications.
- 42 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
9.5
Programming Waveform
Program Command Sequence (last two cycles)
TWC
Address
Read Status Data (last two cycles)
TAS
555h
PA
PA
PA
TAH
#CE
TCH
#OE
TWP
#WE
TCS
T DS
A0h
Data
TPW
TWPH
TDH
Status
PD
DOUT
TBUSY
TRB
RY/#BY
VDD
TVCS
Notes:
1.
2.
9.6
PA = program address, PD = program data,DOUT is the true data at the program address
Illustration shows device in word mode
Accelerated Programming Waveform
V HH
#WP/ACC
V IL or
V IL or
V IH
V IH
TVHH
TVHH
- 43 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
9.7
Chip/Sector Erase Waveform
Erase Command Sequence (last two cycles)
TWC
TAS
2AAh
Address
Read Status Data
VA
SA
VA
555h for chip erase
TAH
#CE
TCH
#OE
TWP
#WE
TWPH
TCS
TDS
Data
55h
TSE
TDH
Complete
TBUSY
RY/#BY
VDD
In
Progress
30h
10 for Chip Erase
TRB
TVCS
Notes :
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write operation Status”).
2. These waveforms are for the word mode
9.8
Back-to back Read/Write Cycle Waveform
TRC
TWC
Addresses
T WC
Valid RA
Valid PA
TAH
Valid PA
Valid PA
TCPH
TACC
TCE
#CE
T WC
TCP
TOE
#OE
TWP
TGHWL
TOEH
#WE
TWPH
Data
TDF
T DS
Valid
In
TOH
TDH
Valid
Out
Valid
In
Valid
In
TSR/W
#WE Controlled Write Cycle
Read Cycle
- 44 -
#CE Controlled Write Cycle
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
9.9
#Data Polling Waveform (During Embedded Algorithms)
TRC
Addresses
VA
VA
VA
TACC
TCE
#CE
TCH
TOE
#OE
TDF
T OEH
#WE
TOH
DQ7
DQ0-DQ6
TBUSY
High Z
Complement
Complement
True
Valid Data
Status Data
Status Data
True
Valid Data
High Z
RY/#BY
Note: VA= Valid Address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
9.10
Toggle Bit Waveform (During Embedded Algorithms)
T AHT
TAS
Addresses
TAHT
TASO
#CE
TCEPH
TOEH
#WE
#OE
DQ6/DQ2
TOEPH
TDH
Valid Data
Valid
Status
(first read)
TOE
Valid
Status
Valid
Status
(second read)
(stop toggling)
Valid Data
RY/#BY
Note: VA= Valid address;not requires for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
- 45 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
9.11
Temporary Sector Unprotect Timing Diagram
VID
#RESET
VID
VSS ,VIL,
or VIH
VSS ,VIL,
or VIH
TVIDR
TVIDR
Program or Erase Command Sequence
#CE
#WE
T RSP
TRRB
RY/#BY
9.12
Sector/Sector Block Protect and Unprotect Timing Diagram
VID
#RESET VIH
SA,A6,
A1,A0
Valid*
Valid*
60h
DATA
Valid*
Verify
Sector/sector Block Protect or Unprotect
40h
60h
Status
Sector/Sector Block Protect:150μs,
Sector/Sector Block Unprotect:15ms
#CE
1μs
#WE
#OE
*For sector protect,A6=0,A1=1,A0=0.For sector unprotect ,A6=1,A1=1,A0=0
- 46 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
9.13
Alternate #CE Controlled Write (Erase/Program) Operation Timing
#Data Polling
Address
PA for program
555 for program
2AA for erase
555 for chip erase
TWC
TWH
t GHEL
#WE
TAS
#OE
PA
SA for sector erase
TAH
TCP
TCPH
TWS
#CE
TPW, T ACCP, or T SE
TDS
.
DATA
TRH
A0 for program
55 for erase
TDH
TBUSY
.
#DQ7
D OUT
PD for program
30 for sector erase
10 for chip erase
#RESET
RY/#BY
Notes:
1. Firgure indicates last two bus cycles of a program or erase operation.
2. PA= program address, SA= sector address, PD= program data.
3. #DQ7 is the complement of the data written to the device. Dout is the data written to the device.
4. Waveforms are for the word mode.
- 47 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
10. LATCHUP CHARACTERISTICS
PARAMETER
MIN.
MAX.
Input voltage with respect to VSS on all pins except I/O pins
(including A9, #OE, and #RESET)
-1.0V
11.5 V
Input voltage with respect to VSS on all I/O pins
-1.0V
VDD +1.0V
-100mA
+100mA
VDD Current
Note: Includes all pins except VDD. Test conditions: VDD = 3.0 V, one pin at a time.
11. CAPACITANCE
PARAMETER
SYM.
TEST SETUP
CIN
Output Capacitance
Control Pin Capacitance
Input Capacitance
TSOP
UNIT
Typical
Max.
VIN = 0
6
7.5
pF
COUT
VOUT = 0
8.5
12
pF
CIN2
VIN = 0
7.5
9
pF
Notes:
1. Sampled, not 100 % tested.
2. Test condition TA = 25 °C, f = 1.0 MHz.
- 48 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
12. ORDERING INFORMATION
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
- 49 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
13. PACKAGE DIMENSION
13.1 48-Pin Standard Thin Small Outline Package
1
48
e
MILLIMETER
INCH
Sym. MIN. NOM.
MAX. MIN. NOM. MAX.
1.20
A
E
b
c
D
HD
A2
0.95
1.00
1.05
0.037 0.039 0.041
D
18.3
18.4
18.5
0.720 0.724 0.728
HD
19.8
20.0
20.2
0.780 0.787 0.795
E
11.9
12.0
12.1
0.468 0.472 0.476
b
c
0.17
0.22
0.10
A1
0.50
Y
- 50 -
0.27 0.007 0.009 0.011
0.020
0.60
0.70
0.020 0.024 0.028
0.031
0.004
0.10
0
0.008
0.21 0.004
0.80
Y
θ
0.002
0.50
e
L1
A
θ L
L1
0.05
L
A2
0.047
A1
5
0
5
Publication Release Date:Dec, 22, 2008
Revisionv A5
W19B320BT/B DATASHEET
14. VERSION HISTORY
VERSION
DATE
PAGE
A0
Dec,31, 2006
ALL
A1
June,15,2007
ALL
A2
Oct,17,2007
46
DESCRIPTION
Initial Issued ,note p21
1. VID was changed from 12.5 to 11.5
2. Erase time was changed form 49 Sec to 30Sec
3. Re-typesetting
1. Update package material as Green
1. Add note 5 and 6
A3
Dec.20,2007
37,40,41
2. Add max of tPB and tPW
3. Modify format and setting
A4
Oct,29,2008
1. Update order information and industrial devices
ambient temperature
2,3,37,48,
2. Remove BGA package type
49
3. Update AC Test Load
A5
Dec,22,2008
Remove Erase Suspend/Resume feature
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
- 51 -
Publication Release Date:Dec, 22, 2008
Revisionv A5
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